From 382dab31225a2351dca08ee96a31621a10068a67 Mon Sep 17 00:00:00 2001 From: Joseph Richey Date: Tue, 10 Sep 2019 13:31:55 -0700 Subject: [PATCH] Update Vendored simulator source (#43) * Update vendored simulator source * Update include list to work with new simulator source * Make simulator work with new internal interface * Readd test change from #39 --- simulator/internal/include.c | 27 +- simulator/internal/internal.go | 41 +- .../Samples/ARM32-FirmwareTPM/README.md | 101 - .../ARM32-FirmwareTPM/optee_ta/.gitignore | 3 - .../ARM32-FirmwareTPM/optee_ta/Makefile | 10 - .../ARM32-FirmwareTPM/optee_ta/fTPM/Makefile | 13 - .../ARM32-FirmwareTPM/optee_ta/fTPM/fTPM.c | 439 - .../optee_ta/fTPM/include/fTPM.h | 106 - .../optee_ta/fTPM/lib/sub.mk | 8 - .../optee_ta/fTPM/lib/tpm/sub.mk | 254 - .../optee_ta/fTPM/lib/wolf/sub.mk | 49 - .../optee_ta/fTPM/platform/AdminPPI.c | 426 - .../optee_ta/fTPM/platform/Cancel.c | 80 - .../optee_ta/fTPM/platform/Clock.c | 302 - .../optee_ta/fTPM/platform/EPS.c | 90 - .../optee_ta/fTPM/platform/Entropy.c | 128 - .../optee_ta/fTPM/platform/LocalityPlat.c | 65 - .../optee_ta/fTPM/platform/NVMem.c | 646 - .../optee_ta/fTPM/platform/NvAdmin.c | 151 - .../optee_ta/fTPM/platform/PPPlat.c | 80 - .../optee_ta/fTPM/platform/PlatformData.c | 82 - .../optee_ta/fTPM/platform/PowerPlat.c | 113 - .../optee_ta/fTPM/platform/RunCommand.c | 90 - .../optee_ta/fTPM/platform/Unique.c | 102 - .../optee_ta/fTPM/platform/include/Admin.h | 230 - .../fTPM/platform/include/PlatformData.h | 137 - .../fTPM/platform/include/Platform_fp.h | 432 - .../optee_ta/fTPM/reference/RuntimeSupport.c | 84 - .../fTPM/reference/include/Implementation.h | 1179 - .../fTPM/reference/include/RuntimeSupport.h | 93 - .../optee_ta/fTPM/reference/include/TpmSal.h | 115 - .../fTPM/reference/include/VendorString.h | 93 - .../optee_ta/fTPM/reference/include/bool.h | 51 - .../ARM32-FirmwareTPM/optee_ta/fTPM/sub.mk | 53 - .../optee_ta/fTPM/user_ta_header_defines.h | 56 - .../ta_prod_signing_scripts/README.md | 17 - .../generate_digest.py | 90 - .../ta_prod_signing_scripts/stitch_ta.py | 104 - .../ms-tpm-20-ref/Samples/Google/Clock.c | 163 + .../ms-tpm-20-ref/Samples/Google/Entropy.c | 11 + .../ms-tpm-20-ref/Samples/Google/NVMem.c | 81 + .../ms-tpm-20-ref/Samples/Google/Platform.h | 71 + .../Samples/Google/PlatformData.h | 86 + .../Samples/Google/Platform_fp.h | 197 + simulator/ms-tpm-20-ref/Samples/Google/Run.c | 78 + .../Samples/Nucleo-TPM/L476RG/.cproject | 311 - .../Samples/Nucleo-TPM/L476RG/.mxproject | 14 - .../Samples/Nucleo-TPM/L476RG/.project | 155 - ...lic.truestudio.debug.hardware_device.prefs | 11 - .../L476RG/.settings/language.settings.xml | 20 - .../org.eclipse.cdt.managedbuilder.core.prefs | 11 - .../Device/ST/STM32L4xx/Include/stm32l476xx.h | 18537 -------------- .../Device/ST/STM32L4xx/Include/stm32l4xx.h | 257 - .../ST/STM32L4xx/Include/system_stm32l4xx.h | 123 - .../Drivers/CMSIS/Include/arm_common_tables.h | 136 - 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--- a/simulator/internal/include.c +++ b/simulator/internal/include.c @@ -3,24 +3,19 @@ // as the Go code. Thus to allow us to use the Mircosoft code as a submodule, we // have to textually include all of the sources into this file. -// Most of the sources can be included in any order. However, this file has to -// be included first as it instantiates all of the libraries global variables. -#include "support/Global.c" +#define _CRYPT_HASH_C_ +#define _X509_SPT_ -// libplatform sources -#include "Cancel.c" +// Google sources #include "Clock.c" -#include "DebugHelpers.c" #include "Entropy.c" -#include "LocalityPlat.c" #include "NVMem.c" -#include "PPPlat.c" -#include "PlatformData.c" -#include "PowerPlat.c" -#include "RunCommand.c" -#include "Unique.c" +#include "Run.c" + +// Most of the sources can be included in any order. However, this file has to +// be included first as it instantiates all of the libraries global variables. +#include "support/Global.c" -// libtpm sources #include "X509/TpmASN1.c" #include "X509/X509_ECC.c" #include "X509/X509_RSA.c" @@ -173,15 +168,9 @@ #include "crypt/PrimeData.c" #include "crypt/RsaKeyCache.c" #include "crypt/Ticket.c" -#include "crypt/ltc/TpmToLtcDesSupport.c" -#include "crypt/ltc/TpmToLtcMath.c" -#include "crypt/ltc/TpmToLtcSupport.c" #include "crypt/ossl/TpmToOsslDesSupport.c" #include "crypt/ossl/TpmToOsslMath.c" #include "crypt/ossl/TpmToOsslSupport.c" -#include "crypt/wolf/TpmToWolfDesSupport.c" -#include "crypt/wolf/TpmToWolfMath.c" -#include "crypt/wolf/TpmToWolfSupport.c" #include "events/_TPM_Hash_Data.c" #include "events/_TPM_Hash_End.c" #include "events/_TPM_Hash_Start.c" diff --git a/simulator/internal/internal.go b/simulator/internal/internal.go index 9aab0c656..172309c67 100644 --- a/simulator/internal/internal.go +++ b/simulator/internal/internal.go @@ -18,12 +18,11 @@ package internal // // Directories containing .h files in the simulator source -// #cgo CFLAGS: -I ../ms-tpm-20-ref/TPMCmd/Platform/include -// #cgo CFLAGS: -I ../ms-tpm-20-ref/TPMCmd/Platform/include/prototypes +// #cgo CFLAGS: -I ../ms-tpm-20-ref/Samples/Google // #cgo CFLAGS: -I ../ms-tpm-20-ref/TPMCmd/tpm/include // #cgo CFLAGS: -I ../ms-tpm-20-ref/TPMCmd/tpm/include/prototypes // // Allows simulator.c to import files without repeating the source repo path. -// #cgo CFLAGS: -I ../ms-tpm-20-ref/TPMCmd/Platform/src +// #cgo CFLAGS: -I ../ms-tpm-20-ref/Samples/Google // #cgo CFLAGS: -I ../ms-tpm-20-ref/TPMCmd/tpm/src // // Store NVDATA in memory, and we don't care about updates to failedTries. // #cgo CFLAGS: -DVTPM=NO -DSIMULATION=NO -DUSE_DA_USED=NO @@ -32,10 +31,16 @@ package internal // // Silence known warnings from the reference code and CGO code. // #cgo CFLAGS: -Wno-missing-braces -Wno-empty-body -Wno-unused-variable // // Link against the system OpenSSL -// #cgo CFLAGS: -DHASH_LIB=Ossl -DSYM_LIB=Ossl -DMATH_LIB=Ossl +// #cgo CFLAGS: -DDEBUG=YES +// #cgo CFLAGS: -DSIMULATION=NO +// #cgo CFLAGS: -DCOMPILER_CHECKS=DEBUG +// #cgo CFLAGS: -DRUNTIME_SIZE_CHECKS=DEBUG +// #cgo CFLAGS: -DUSE_DA_USED=NO +// #cgo CFLAGS: -DCERTIFYX509_DEBUG=NO // #cgo LDFLAGS: -lcrypto // // #include +// #include "Platform.h" // #include "Tpm.h" // // void sync_seeds() { @@ -46,7 +51,6 @@ package internal import "C" import ( "errors" - "fmt" "io" "unsafe" ) @@ -59,29 +63,10 @@ func SetSeeds(r io.Reader) { r.Read(C.gp.PPSeed[2:]) } -// On starts the simulator. Does not call TPM2_Startup -func On() { - // Setup the simulator to receive commands - C._plat__Signal_PowerOn() - C._plat__Signal_Reset() - C._plat__SetNvAvail() - C._plat__Signal_PhysicalPresenceOn() -} - -// Off stops the simulator. Does not call TPM2_Shutdown -func Off() { - C._plat__Signal_PhysicalPresenceOff() - C._plat__ClearNvAvail() - C._plat__Signal_PowerOff() -} - -// ManufactureReset resets the TPM to its initial factory state. -func ManufactureReset() error { - rc := C.TPM_Manufacture(1) - if rc != C.TPM_RC_SUCCESS { - return fmt.Errorf("manufacture reset failed: code %x", rc) - } - return nil +// Reset simulates toggling the power the the TPM. If forceManufacture is true, +// the reset will be a manufacturer reset. +func Reset(forceManufacture bool) { + C._plat__Reset(C.bool(forceManufacture)) } // RunCommand passes cmd to the simulator and returns the simulator's response. diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/README.md b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/README.md deleted file mode 100644 index 8c4e2225d..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/README.md +++ /dev/null @@ -1,101 +0,0 @@ -MS-IoT fTPM -=========== -## Trusted firmware for Windows based AArch32 (32-bit) ARM SoC's -Please see the [build-firmware document](https://github.com/ms-iot/imx-iotcore/blob/develop/Documentation/build-firmware.md) in the iMX IoT Core repo for additional information on including this TA in an IoT Core image for iMX boards. - -## Included TAs - -### fTPM TA -The fTPM Trusted Application (TA) provides a secure firmware implementation of a TPM using the MS reference implementation. -Platform specific code is copied and modified locally in [`optee_ta/fTPM/platform`](./optee_ta/fTPM/platform), while [`/fTPM/reference`](./fTPM/reference) contains files to support WolfSSL, control the fTPM's functionality, and define basic types, which may not be found in OpTEE. - -See the reference implementation for more details. - ---- - -## Extra Installation Steps - -The secure firmware utilizes the OP-TEE implementation of the Global Platform specifications. The OP-TEE project is -not duplicated in this repository but is obtained directly from the public release. The build of OP-TEE is based on a -native Linux build, however the following installation steps allow OP-TEE to be built under Windows using WSL. Only the optee_os -repository is relevant for trusted firmware use - the optee_client & optee_linuxdriver repositories are integration -components for Linux and can serve as a reference for the Windows equivalent components. Note that optee_linuxdriver -is GPL. - -OpTEE generates a build environment for trusted applications which is based on Make (See TA_DEV_KIT_DIR in the build directions). -This build environment places several constraints on how the code is organized, which are explained in the relevant makefiles. -See the [optee_os documentation](https://github.com/OP-TEE/optee_os/blob/master/documentation/build_system.md) for details about how OpTEE build works. - -#### 1. Enable Windows Subsystem for Linux -See instructions [here](https://docs.microsoft.com/en-us/windows/wsl/install-win10): - -#### 2. Launch Bash -Search for "bash" in the start menu, OR press Windows key + 'R', then type bash. -Update if needed. - -In WSL: -```sh -sudo apt-get update -``` - -#### 3. Install the ARM tool chain -Install the ARM toolchain to a directory of your choice. -```sh -cd ~ -wget https://releases.linaro.org/components/toolchain/binaries/6.4-2017.11/arm-linux-gnueabihf/gcc-linaro-6.4.1-2017.11-x86_64_arm-linux-gnueabihf.tar.xz -tar xf gcc-linaro-6.4.1-2017.11-x86_64_arm-linux-gnueabihf.tar.xz -rm gcc-linaro-6.4.1-2017.11-x86_64_arm-linux-gnueabihf.tar.xz -``` - -#### 4. Clone the OpTEE OS source code -If you do not already have a version of the OP-TEE OS repo cloned on your machine you may run: -```sh -cd ~ -git clone https://github.com/ms-iot/ms-iot-optee_os.git -``` - -#### 5. Build OP-TEE OS for the target platform - -`TA_CROSS_COMPILE` should point to the ARM toolchain installed in [step 3](#3-install-the-arm-tool-chain). - -```sh -cd ~/optee_os -CROSS_COMPILE=~/gcc-linaro-6.4.1-2017.11-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf- make PLATFORM=imx-mx6qhmbedge CFG_TEE_CORE_LOG_LEVEL=4 CFG_REE_FS=n CFG_RPMB_FS=y CFG_RPMB_TESTKEY=y CFG_RPMB_WRITE_KEY=y -j20 -``` -Additional information on Microsoft IoT fork of OP-TEE OS can be found [here](https://github.com/ms-iot/ms-iot-optee_os). - -#### 6. Clone the ms-tpm-20-ref source code -```sh -cd ~ -git clone https://github.com/Microsoft/ms-tpm-20-ref.git -``` - -#### 7. Initialize the git submodules -```sh -cd ~/ms-tpm-20-ref -git submodule init -git submodule update -``` - ---- - -## Building the TPM - -#### 1. Build the Firmware TPM Trusted Application -`TA_CROSS_COMPILE` should point to the ARM toolchain installed in [step 3](#3-install-the-arm-tool-chain). - -`TA_DEV_KIT_DIR` should point to the directory the optee_os TA devkit was compiled to in [step 5](#6-clone-the-ms-tpm-20-ref-source-code -). - -`-j` increases the parallelism of the build process. - -```sh -cd ~/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta -TA_CPU=cortex-a9 TA_CROSS_COMPILE=~/gcc-linaro-6.4.1-2017.11-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf- TA_DEV_KIT_DIR=~/optee_os/out/arm-plat-imx/export-ta_arm32 CFG_TEE_TA_LOG_LEVEL=2 make -j20 -``` -Debugging options you may want to add: - -`CFG_TEE_TA_LOG_LEVEL=3` 1 is fatal errors only, other values increase debug tracing output. - -`CFG_TA_DEBUG=y` Turns on debug output from the TAs, and enables extra correctness checks in the fTPM TA. - diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/.gitignore b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/.gitignore deleted file mode 100644 index f8465228d..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -out -/fTPM/lib/tpm/tpm_symlink -/fTPM/lib/wolf/wolf_symlink \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/Makefile b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/Makefile deleted file mode 100644 index ddf67848e..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/Makefile +++ /dev/null @@ -1,10 +0,0 @@ - -export V?=0 - -.PHONY: all -all: - $(MAKE) -C fTPM CROSS_COMPILE=$(TA_CROSS_COMPILE) - -.PHONY: clean -clean: - $(MAKE) -C fTPM clean \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/Makefile b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/Makefile deleted file mode 100644 index c71eecd6d..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -BINARY=bc50d971-d4c9-42c4-82cb-343fb7f37896 - -O ?= ../out/fTPM -WOLF_ROOT := ../../../../external/wolfssl/ -TPM_ROOT := ../../../../ - -include $(TA_DEV_KIT_DIR)/mk/ta_dev_kit.mk - -clean: clean_stripped_file -.PHONY: clean_stripped_file -clean_stripped_file: - rm -f $(BINARY).stripped.elf - diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/fTPM.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/fTPM.c deleted file mode 100644 index 6fe5880d4..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/fTPM.c +++ /dev/null @@ -1,439 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#define STR_TRACE_USER_TA "fTPM" - -#include -#include -#include - -#include "fTPM.h" - -#define TA_ALL_PARAM_TYPE(type) TEE_PARAM_TYPES(type, type, type, type) - -// -// Ensure we have only one active session -// -static bool fTPMSessionActive = false; - -// -// Initialization -// -bool fTPMInitialized = false; - -// -// Local (SW) command buffer -// -static uint8_t fTPMCommand[MAX_COMMAND_SIZE]; - -// -// A subset of TPM return codes (see TpmTypes.h) -// -typedef uint32_t TPM_RC; -#define RC_VER1 (TPM_RC) (0x100) -#define TPM_RC_SUCCESS (TPM_RC) (0x000) -#define TPM_RC_FAILURE (TPM_RC) (RC_VER1+0x001) - -// -// Helper functions for byte ordering of TPM commands/responses -// -static uint16_t SwapBytes16(uint16_t Value) -{ - return (uint16_t)((Value << 8) | (Value >> 8)); -} - -static uint32_t SwapBytes32(uint32_t Value) -{ - uint32_t LowerBytes; - uint32_t HigherBytes; - - LowerBytes = (uint32_t)SwapBytes16((uint16_t)Value); - HigherBytes = (uint32_t)SwapBytes16((uint16_t)(Value >> 16)); - - return (LowerBytes << 16 | HigherBytes); -} - -// -// Helper function to read response codes from TPM responses -// -static uint32_t fTPMResponseCode(uint32_t ResponseSize, - uint8_t *ResponseBuffer) -{ - uint32_t ResponseCode; - union { - uint32_t Data; - uint8_t Index[4]; - } Value; - - // In case of too-small response size, assume failure. - if (ResponseSize < 0xA) { - return TPM_RC_FAILURE; - } - - Value.Index[0] = ResponseBuffer[6]; - Value.Index[1] = ResponseBuffer[7]; - Value.Index[2] = ResponseBuffer[8]; - Value.Index[3] = ResponseBuffer[9]; - ResponseCode = SwapBytes32(Value.Data); - - return ResponseCode; -} - -// -// Called when TA instance is created. This is the first call to the TA. -// -TEE_Result TA_CreateEntryPoint(void) -{ - #define STARTUP_SIZE 0x0C - - uint8_t startupClear[STARTUP_SIZE] = { 0x80, 0x01, 0x00, 0x00, 0x00, 0x0c, - 0x00, 0x00, 0x01, 0x44, 0x00, 0x00 }; - uint8_t startupState[STARTUP_SIZE] = { 0x80, 0x01, 0x00, 0x00, 0x00, 0x0c, - 0x00, 0x00, 0x01, 0x44, 0x00, 0x01 }; - uint32_t respLen; - uint8_t *respBuf; - -#ifdef fTPMDebug - DMSG("Entry Point\n"); -#endif - - // If we've been here before, don't init again. - if (fTPMInitialized) { - // We may have had TA_DestroyEntryPoint called but we didn't - // actually get torn down. Re-NVEnable, just in case. - if (_plat__NVEnable(NULL) == 0) { - TEE_Panic(TEE_ERROR_BAD_STATE); - } - return TEE_SUCCESS; - } - - // Initialize NV admin state - _admin__NvInitState(); - - // If we fail to open fTPM storage we cannot continue. - if (_plat__NVEnable(NULL) == 0) { - TEE_Panic(TEE_ERROR_BAD_STATE); - } - -#ifdef fTPMDebug - DMSG("NVEnable Complete\n"); -#endif - - // This only occurs when there is no previous NV state, i.e., on first - // boot, after recovering from data loss, we reset the platform, etc. - if (_plat__NvNeedsManufacture()) { -#ifdef fTPMDebug - DMSG("TPM_Manufacture\n"); -#endif - TPM_Manufacture(1); - } - - // "Power-On" the platform - _plat__Signal_PowerOn(); - - // Internal init for reference implementation - _TPM_Init(); - -#ifdef fTPMDebug - DMSG("Init Complete\n"); -#endif - - // Startup with state - if (g_chipFlags.fields.TpmStatePresent) { - - // Re-use request buffer for response (ignored) - respBuf = startupState; - respLen = STARTUP_SIZE; - - ExecuteCommand(STARTUP_SIZE, startupState, &respLen, &respBuf); - if (fTPMResponseCode(respLen, respBuf) == TPM_RC_SUCCESS) { - goto Exit; - } - -#ifdef fTPMDebug - DMSG("Fall through to startup clear\n"); -#endif - - goto Clear; - } - -#ifdef fTPMDebug - DMSG("No TPM state present\n"); -#endif - -Clear: - // Re-use request buffer for response (ignored) - respBuf = startupClear; - respLen = STARTUP_SIZE; - - // Fall back to a Startup Clear - ExecuteCommand(STARTUP_SIZE, startupClear, &respLen, &respBuf); - -Exit: - // Init is complete, indicate so in fTPM admin state. - g_chipFlags.fields.TpmStatePresent = 1; - _admin__SaveChipFlags(); - - // Initialization complete - fTPMInitialized = true; - - return TEE_SUCCESS; -} - - -// -// Called when TA instance destroyed. This is the last call in the TA. -// -void TA_DestroyEntryPoint(void) -{ - // We should only see this called after the OS has shutdown and there - // will be no further commands sent to the TPM. Right now, just close - // our storage object, becasue the TPM driver should have already - // shutdown cleanly. - _plat__NVDisable(); - return; -} - - -// -// Called when a new session is opened to the TA. -// -TEE_Result TA_OpenSessionEntryPoint(uint32_t param_types, - TEE_Param params[4], - void **sess_ctx) -{ - uint32_t exp_param_types = TA_ALL_PARAM_TYPE(TEE_PARAM_TYPE_NONE); - - // Unreferenced parameters - UNREFERENCED_PARAMETER(params); - UNREFERENCED_PARAMETER(sess_ctx); - - // Validate parameter types - if (param_types != exp_param_types) { - return TEE_ERROR_BAD_PARAMETERS; - } - - // Only one active session to the fTPM is permitted - if (fTPMSessionActive) { - return TEE_ERROR_ACCESS_CONFLICT; - } - - // Active session - fTPMSessionActive = true; - - // If return value != TEE_SUCCESS the session will not be created. - return TEE_SUCCESS; -} - - -// -// Called when a session is closed. -// -void TA_CloseSessionEntryPoint(void *sess_ctx) -{ - // Unused parameter(s) - UNREFERENCED_PARAMETER(sess_ctx); - - // Clear active session - if (fTPMSessionActive) { - fTPMSessionActive = false; - } -} - -// -// Called to handle command submission. -// -static TEE_Result fTPM_Submit_Command(uint32_t param_types, - TEE_Param params[4] -) -{ - uint8_t *cmdBuf, *respBuf; - uint32_t cmdLen, respLen; - uint32_t exp_param_types = TEE_PARAM_TYPES(TEE_PARAM_TYPE_MEMREF_INPUT, - TEE_PARAM_TYPE_MEMREF_INOUT, - TEE_PARAM_TYPE_NONE, - TEE_PARAM_TYPE_NONE); - - // Validate parameter types - if (param_types != exp_param_types) { -#ifdef fTPMDebug - IMSG("Bad param type(s)\n"); -#endif - return TEE_ERROR_BAD_PARAMETERS; - } - - // Sanity check our buffer sizes - if ((params[0].memref.size == 0) || - (params[1].memref.size == 0) || - (params[0].memref.size > MAX_COMMAND_SIZE) || - (params[1].memref.size > MAX_RESPONSE_SIZE)) { -#ifdef fTPMDebug - IMSG("Bad param size(s)\n"); -#endif - return TEE_ERROR_BAD_PARAMETERS; - } - - // Copy command locally - memcpy(fTPMCommand, params[0].memref.buffer, params[0].memref.size); - - // Pull the command length from the actual TPM command. The memref size - // field descibes the buffer containing the command, not the command. - cmdBuf = fTPMCommand; - cmdLen = BYTE_ARRAY_TO_UINT32((uint8_t *)&(cmdBuf[2])); - - // Sanity check cmd length included in TPM command - if (cmdLen > params[0].memref.size) { - return TEE_ERROR_BAD_PARAMETERS; - } - - respBuf = (uint8_t *)(params[1].memref.buffer); - respLen = params[1].memref.size; - - // Check if this is a PPI Command - if (!_admin__PPICommand(cmdLen, cmdBuf, &respLen, &respBuf)) { - // If not, pass through to TPM - ExecuteCommand(cmdLen, cmdBuf, &respLen, &respBuf); - } - - // Unfortunately, this cannot be done until after we have our response in - // hand. We will, however, make an effort to return at least a portion of - // the response along with TEE_ERROR_SHORT_BUFFER. - if (respLen > params[1].memref.size) - { -#ifdef fTPMDebug - IMSG("Insufficient buffer length RS: 0x%x > BL: 0x%x\n", respLen, params[1].memref.size); -#endif - return TEE_ERROR_SHORT_BUFFER; - } - -#ifdef fTPMDebug - DMSG("Success, RS: 0x%x\n", respLen); -#endif - - return TEE_SUCCESS; -} - -// -// Called to handle PPI commands -// -static TEE_Result fTPM_Emulate_PPI(uint32_t param_types, - TEE_Param params[4] -) -{ - uint8_t *cmdBuf, *respBuf; - uint32_t cmdLen, respLen; - uint32_t exp_param_types = TEE_PARAM_TYPES(TEE_PARAM_TYPE_MEMREF_INPUT, - TEE_PARAM_TYPE_MEMREF_INOUT, - TEE_PARAM_TYPE_NONE, - TEE_PARAM_TYPE_NONE); - - // Validate parameter types - if (param_types != exp_param_types) { -#ifdef fTPMDebug - IMSG("Bad param type(s)\n"); -#endif - return TEE_ERROR_BAD_PARAMETERS; - } - - // Sanity check our buffer sizes - if ((params[0].memref.size == 0) || - (params[1].memref.size == 0) || - (params[0].memref.size > MAX_COMMAND_SIZE) || - (params[1].memref.size > MAX_RESPONSE_SIZE)) { -#ifdef fTPMDebug - IMSG("Bad param size(s)\n"); -#endif - return TEE_ERROR_BAD_PARAMETERS; - } - - // Copy command locally - memcpy(fTPMCommand, params[0].memref.buffer, params[0].memref.size); - - cmdBuf = fTPMCommand; - cmdLen = params[0].memref.size; - - respBuf = (uint8_t *)(params[1].memref.buffer); - respLen = params[1].memref.size; - - // Pass along to platform PPI processing - if (_admin__PPIRequest(cmdLen, cmdBuf, &respLen, &respBuf)) { -#ifdef fTPMDebug - DMSG("Handled PPI command via TA interface\n"); -#endif - } - else { -#ifdef fTPMDebug - IMSG("Failed to handle PPI command via TA interface\n"); -#endif - } - - if (respLen > params[1].memref.size) { -#ifdef fTPMDebug - IMSG("Insufficient buffer length RS: 0x%x > BL: 0x%x\n", respLen, params[1].memref.size); -#endif - return TEE_ERROR_SHORT_BUFFER; - } - - params[1].memref.size = respLen; - return TEE_SUCCESS; -} - -// -// Called when a TA is invoked. Note, paramters come from normal world. -// -TEE_Result TA_InvokeCommandEntryPoint(void *sess_ctx, - uint32_t cmd_id, - uint32_t param_types, - TEE_Param params[4]) -{ - // Unused parameter(s) - UNREFERENCED_PARAMETER(sess_ctx); - - // Handle command invocation - switch (cmd_id) { - - case TA_FTPM_SUBMIT_COMMAND: { - return fTPM_Submit_Command(param_types, params); - } - - case TA_FTPM_EMULATE_PPI: { - return fTPM_Emulate_PPI(param_types, params); - } - - default: { - return TEE_ERROR_BAD_PARAMETERS; - } - } -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/include/fTPM.h b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/include/fTPM.h deleted file mode 100644 index 7b1192ad9..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/include/fTPM.h +++ /dev/null @@ -1,106 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef FTPM_TA_H -#define FTPM_TA_H - -#include - -/* This UUID is generated with uuidgen */ -#define TA_FTPM_UUID { 0xBC50D971, 0xD4C9, 0x42C4, \ - {0x82, 0xCB, 0x34, 0x3F, 0xB7, 0xF3, 0x78, 0x96}} - -/* The TAFs ID implemented in this TA */ -#define TA_FTPM_SUBMIT_COMMAND (0) -#define TA_FTPM_EMULATE_PPI (1) - -// -// These must match values from reference/TPM/include/Implementation.h -// -#define MAX_COMMAND_SIZE 4096 -#define MAX_RESPONSE_SIZE 4096 - -// -// Macro for intentionally unreferenced parameters -// -#define UNREFERENCED_PARAMETER(_Parameter_) (void)(_Parameter_) - -// -// Shorthand for TA functions taking uniform arg types -// -#define TA_ALL_PARAM_TYPE(a) TEE_PARAM_TYPES((a), (a), (a), (a)) - -// -// Used to extract size field from TPM command buffers -// -#define BYTE_ARRAY_TO_UINT32(b) (uint32_t)( ((b)[0] << 24) \ - + ((b)[1] << 16) \ - + ((b)[2] << 8 ) \ - + (b)[3]) -// -// Entrypoint for reference implemntation -// -extern void ExecuteCommand( - uint32_t requestSize, // IN: command buffer size - unsigned char *request, // IN: command buffer - uint32_t *responseSize, // OUT: response buffer size - unsigned char **response // OUT: response buffer - ); - -// -// External functions supporting TPM initialization -// -extern int _plat__NVEnable(void *platParameter); -extern int TPM_Manufacture(bool firstTime); -extern bool _plat__NvNeedsManufacture(void); -extern void _TPM_Init(void); -extern void _plat__Signal_PowerOn(void); -extern void _plat__NVDisable(void); -extern void _admin__SaveChipFlags(void); - -// -// External types/data supporting TPM initialization -// -typedef union { - uint32_t flags; - struct { - uint32_t Remanufacture : 1; // Perform a TPM_Remanufacture() on startup (SET by default) - uint32_t TpmStatePresent : 1; // Init TPM and NV with contents of TpmState and NVState on startup - uint32_t Reserved : 30; - } fields; -} TPM_CHIP_STATE; - -extern TPM_CHIP_STATE g_chipFlags; -#endif /* FTPM_TA_H */ \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/lib/sub.mk b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/lib/sub.mk deleted file mode 100644 index 79205e626..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/lib/sub.mk +++ /dev/null @@ -1,8 +0,0 @@ -.PHONY: create_lib_symlinks -create_lib_symlinks: ./lib/tpm/tpm_symlink ./lib/wolf/wolf_symlink - -.PHONY: clean_lib_symlinks -clean_lib_symlinks: remove_tpm_symlink remove_wolf_symlink - -subdirs-y += wolf -subdirs-y += tpm \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/lib/tpm/sub.mk b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/lib/tpm/sub.mk deleted file mode 100644 index ac472b38e..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/lib/tpm/sub.mk +++ /dev/null @@ -1,254 +0,0 @@ -FTPM_FLAGS = -DGCC -DUSE_WOLFCRYPT -DSIMULATION=NO -DUSE_PLATFORM_EPS -DVTPM -FTPM_DEBUG = -DCOMPILER_CHECKS=YES -DfTPMDebug -DRUNTIME_SIZE_CHECKS -DLIBRARY_COMPATIBILITY_CHECK -FTPM_RELEASE = -DCOMPILER_CHECKS=NO -DRUNTIME_SIZE_CHECKS=NO -DLIBRARY_COMPATIBILITY_CHECK=NO - -# -# The fTPM needs to overwrite some of the header files used in the reference implementation. The search order GCC -# uses is dependent on the order the '-I/include/path' arguments are passed in. This is depended on the optee_os build -# system which makes it brittle. Force including these files here will make sure the correct files are used first. -# - -FTPM_INCLUDES = -include ./reference/include/VendorString.h -include ./reference/include/Implementation.h - -# -# The TPM causes a few warnings when compiled with GCC which are not critical. -# - -FTPM_WARNING_SUPPRESS = -Wno-cast-align -Wno-switch-default -Wno-suggest-attribute=noreturn -Wno-missing-braces -Wno-sign-compare - -cflags-y += $(FTPM_FLAGS) $(WOLF_SSL_FLAGS) $(FTPM_INCLUDES) $(FTPM_WARNING_SUPPRESS) - -ifeq ($(CFG_TA_DEBUG),y) -cflags-y += $(FTPM_DEBUG) -else -cflags-y += $(FTPM_RELEASE) -endif - -# -# For the purposes of this command the current working directory is the makefile root (/fTPM) folder, -# but the symlink will be created relative to THIS directory so the source requires an extra '../../'. -# -# Symlinks are needed since all build output is placed relative to the root. External libraries would result in -# binaries located outside the ouptut folder. -# -./lib/tpm/tpm_symlink: - @echo Checking symlink to the TPM folder: $(abspath $(TPM_ROOT)) - @if [ -L ./lib/tpm/tpm_symlink ] ; \ - then \ - echo Symlink already established ; \ - else \ - echo Establishing symlink. ; \ - ln -s ../../$(TPM_ROOT) ./lib/tpm/tpm_symlink; \ - fi - -.PHONY: remove_tpm_symlink -remove_tpm_symlink: - @if [ -e ./lib/tpm/tpm_symlink ] ; \ - then \ - unlink ./lib/tpm/tpm_symlink ; \ - echo Clearing symlink to the TPM folder: $(abspath $(TPM_ROOT)) ; \ - fi - -global-incdirs-y += tpm_symlink/TPMCmd/tpm/include -global-incdirs-y += tpm_symlink/TPMCmd/tpm/include/ltc -global-incdirs-y += tpm_symlink/TPMCmd/tpm/include/prototypes -global-incdirs-y += tpm_symlink/TPMCmd/tpm/include/wolf - -# -# Generated in WSL using: -# find -name *.c | while read line; do echo XXXX$line; done | sed -e 's/XXXX.\//srcs-y += tpm_symlink/TPMCmd/tpm/src//g' -# This may need to be updated if there are any changes to the reference implementation. -# - -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Asymmetric/ECC_Parameters.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Asymmetric/ECDH_KeyGen.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Asymmetric/ECDH_ZGen.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Asymmetric/EC_Ephemeral.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Asymmetric/RSA_Decrypt.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Asymmetric/RSA_Encrypt.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Asymmetric/ZGen_2Phase.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/AttachedComponent/AC_GetCapability.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/AttachedComponent/AC_Send.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/AttachedComponent/AC_spt.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/AttachedComponent/Policy_AC_SendSelect.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Attestation/Attest_spt.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Attestation/Certify.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Attestation/CertifyCreation.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Attestation/GetCommandAuditDigest.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Attestation/GetSessionAuditDigest.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Attestation/GetTime.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Attestation/Quote.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Capability/GetCapability.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Capability/TestParms.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/ClockTimer/ClockRateAdjust.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/ClockTimer/ClockSet.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/ClockTimer/ReadClock.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/CommandAudit/SetCommandCodeAuditStatus.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Context/ContextLoad.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Context/ContextSave.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Context/Context_spt.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Context/EvictControl.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Context/FlushContext.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/DA/DictionaryAttackLockReset.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/DA/DictionaryAttackParameters.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Duplication/Duplicate.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Duplication/Import.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Duplication/Rewrap.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyAuthorize.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyAuthorizeNV.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyAuthValue.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyCommandCode.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyCounterTimer.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyCpHash.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyDuplicationSelect.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyGetDigest.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyLocality.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyNameHash.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyNV.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyNvWritten.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyOR.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyPassword.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyPCR.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyPhysicalPresence.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicySecret.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicySigned.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyTemplate.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/PolicyTicket.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/EA/Policy_spt.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Ecdaa/Commit.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/FieldUpgrade/FieldUpgradeData.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/FieldUpgrade/FieldUpgradeStart.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/FieldUpgrade/FirmwareRead.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/HashHMAC/EventSequenceComplete.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/HashHMAC/HashSequenceStart.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/HashHMAC/HMAC_Start.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/HashHMAC/MAC_Start.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/HashHMAC/SequenceComplete.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/HashHMAC/SequenceUpdate.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Hierarchy/ChangeEPS.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Hierarchy/ChangePPS.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Hierarchy/Clear.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Hierarchy/ClearControl.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Hierarchy/CreatePrimary.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Hierarchy/HierarchyChangeAuth.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Hierarchy/HierarchyControl.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Hierarchy/SetPrimaryPolicy.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Misc/PP_Commands.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Misc/SetAlgorithmSet.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_Certify.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_ChangeAuth.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_DefineSpace.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_Extend.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_GlobalWriteLock.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_Increment.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_Read.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_ReadLock.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_ReadPublic.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_SetBits.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_spt.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_UndefineSpace.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_UndefineSpaceSpecial.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_Write.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/NVStorage/NV_WriteLock.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Object/ActivateCredential.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Object/Create.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Object/CreateLoaded.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Object/Load.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Object/LoadExternal.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Object/MakeCredential.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Object/ObjectChangeAuth.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Object/Object_spt.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Object/ReadPublic.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Object/Unseal.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/PCR/PCR_Allocate.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/PCR/PCR_Event.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/PCR/PCR_Extend.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/PCR/PCR_Read.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/PCR/PCR_Reset.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/PCR/PCR_SetAuthPolicy.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/PCR/PCR_SetAuthValue.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Random/GetRandom.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Random/StirRandom.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Session/PolicyRestart.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Session/StartAuthSession.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Signature/Sign.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Signature/VerifySignature.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Startup/Shutdown.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Startup/Startup.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Symmetric/EncryptDecrypt.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Symmetric/EncryptDecrypt2.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Symmetric/EncryptDecrypt_spt.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Symmetric/Hash.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Symmetric/HMAC.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Symmetric/MAC.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Testing/GetTestResult.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Testing/IncrementalSelfTest.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Testing/SelfTest.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/command/Vendor/Vendor_TCG_Test.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/AlgorithmTests.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/BnConvert.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/BnMath.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/BnMemory.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptCmac.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptDes.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptEccData.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptEccKeyExchange.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptEccMain.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptEccSignature.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptHash.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptHashData.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptPrime.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptPrimeSieve.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptRand.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptRsa.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptSelfTest.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptSmac.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptSym.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/CryptUtil.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/ltc/TpmToLtcDesSupport.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/ltc/TpmToLtcMath.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/ltc/TpmToLtcSupport.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/ossl/TpmToOsslDesSupport.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/ossl/TpmToOsslMath.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/ossl/TpmToOsslSupport.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/PrimeData.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/RsaKeyCache.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/Ticket.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/wolf/TpmToWolfDesSupport.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/wolf/TpmToWolfMath.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/crypt/wolf/TpmToWolfSupport.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/events/_TPM_Hash_Data.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/events/_TPM_Hash_End.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/events/_TPM_Hash_Start.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/events/_TPM_Init.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/main/CommandDispatcher.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/main/ExecCommand.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/main/SessionProcess.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/subsystem/CommandAudit.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/subsystem/DA.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/subsystem/Hierarchy.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/subsystem/NvDynamic.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/subsystem/NvReserved.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/subsystem/Object.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/subsystem/PCR.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/subsystem/PP.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/subsystem/Session.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/subsystem/Time.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/AlgorithmCap.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/Bits.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/CommandCodeAttributes.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/Entity.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/Global.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/Handle.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/IoBuffers.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/Locality.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/Manufacture.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/Marshal.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/MathOnByteBuffers.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/Memory.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/Power.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/PropertyCap.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/Response.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/ResponseCodeProcessing.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/TpmFail.c -srcs-y += tpm_symlink/TPMCmd/tpm/src/support/TpmSizeChecks.c \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/lib/wolf/sub.mk b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/lib/wolf/sub.mk deleted file mode 100644 index 7eaeb876f..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/lib/wolf/sub.mk +++ /dev/null @@ -1,49 +0,0 @@ - -WOLF_SSL_FLAGS = -DSINGLE_THREADED -DNO_WOLFSSL_CLIENT -DNO_WOLFSSL_SERVER -DOPENSSL_EXTRA -DNO_FILESYSTEM -DWOLFSSL_USER_SETTINGS -DTIME_OVERRIDES -DSTRING_USER -DCTYPE_USER - -# -# Wolfcrypt has multiple unused functions, unfortunately the OPTEE build system can only turn off compiler flags for -# files in the same directory as the sub.mk file. It is not possible to place sub.mk files in the git submodules without -# creating a new fork of each submodule repo. To avoid spurious warnings these warnings are disabled here globally. -# - -WOLF_WARNING_SUPPRESS = -Wno-unused-function - -cflags-y += $(WOLF_SSL_FLAGS) $(WOLF_WARNING_SUPPRESS) - -# -# For the purposes of this command the current working directory is the makefile root (/fTPM) folder, -# but the symlink will be created relative to THIS directory so the source requires an extra '../../'. -# -./lib/wolf/wolf_symlink: - @echo Checking symlink to the WolfSSL folder: $(abspath $(WOLF_ROOT)) - @if [ -L ./lib/wolf/wolf_symlink ] ; \ - then \ - echo Symlink already established ; \ - else \ - echo Establishing symlink. ; \ - ln -s ../../$(WOLF_ROOT) ./lib/wolf/wolf_symlink; \ - fi - -.PHONY: remove_wolf_symlink -remove_wolf_symlink: - @if [ -e ./lib/wolf/wolf_symlink ] ; \ - then \ - unlink ./lib/wolf/wolf_symlink ; \ - echo Clearing symlink to the Wolf folder: $(abspath $(WOLF_ROOT)) ; \ - fi - -global-incdirs-y += wolf_symlink - -srcs-y += wolf_symlink/wolfcrypt/src/aes.c -srcs-y += wolf_symlink/wolfcrypt/src/asn.c -srcs-y += wolf_symlink/wolfcrypt/src/ecc.c -srcs-y += wolf_symlink/wolfcrypt/src/integer.c -srcs-y += wolf_symlink/wolfcrypt/src/memory.c -srcs-y += wolf_symlink/wolfcrypt/src/sha.c -srcs-y += wolf_symlink/wolfcrypt/src/sha256.c -srcs-y += wolf_symlink/wolfcrypt/src/sha512.c -srcs-y += wolf_symlink/wolfcrypt/src/tfm.c -srcs-y += wolf_symlink/wolfcrypt/src/wolfmath.c -srcs-y += wolf_symlink/wolfcrypt/src/des3.c -srcs-y += wolf_symlink/wolfcrypt/src/random.c \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/AdminPPI.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/AdminPPI.c deleted file mode 100644 index 01d382d72..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/AdminPPI.c +++ /dev/null @@ -1,426 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//**Introduction -// This file contains the emulated Physical Presence Interface. - -#include "assert.h" -#include "Admin.h" -#include "string.h" - -#include -#include - -#define TPM_CC_EmulatePPI 0x200001FF - -// -// Hand marshaling, unmarshaling, and maximally sized structures for EmulatePPI -// -#pragma pack (push, 1) -typedef struct { - TPM_ST tag; - UINT32 paramSize; - TPM_CC commandCode; -} TPM2_COMMAND_HEADER; - -typedef struct { - TPM_ST tag; - UINT32 paramSize; - TPM_RC responseCode; -} TPM2_RESPONSE_HEADER; - -typedef struct{ - UINT32 FunctionIndex; - UINT32 Op; -} EmulatePPI_In; - -typedef struct{ - UINT32 Result1; - UINT32 Result2; - UINT32 Result3; -} EmulatePPI_Out; - -typedef struct{ - TPM2_COMMAND_HEADER header; - EmulatePPI_In inputParameters; -} TPM2_EmulatePPI_cmd_t; - -typedef struct{ - TPM2_RESPONSE_HEADER header; - EmulatePPI_Out outputParameters; -} TPM2_EmulatePPI_res_t; -#pragma pack (pop) - -FTPM_PPI_STATE s_PPIState; - -extern int _plat__NvCommit(void); - -static void -ExecutePPICommand( - _In_ UINT32 FunctionIndex, - _In_ UINT32 Op, - _Out_ UINT32 *Result1, - _Out_ UINT32 *Result2, - _Out_ UINT32 *Result3 - ) -{ - UINT32 retVal1 = 0; - UINT32 retVal2 = 0; - UINT32 retVal3 = 0; - - _admin__RestorePPIState(); - - memset(Result1, 0, sizeof(UINT32)); - memset(Result2, 0, sizeof(UINT32)); - memset(Result3, 0, sizeof(UINT32)); - - switch (FunctionIndex) { - case FTPM_PPI_CMD_QUERY: - retVal1 = 0x1AB; // Per PPI 1.2 specification - break; - - case FTPM_PPI_CMD_VERSION: - retVal1 = FTPM_PPI_VERSION; // String "1.2" - break; - - case FTPM_PPI_CMD_SUBMIT_OP_REQ: - case FTPM_PPI_CMD_GET_PLATFORM_ACTION: - retVal1 = 2; // Reboot/General Failure - break; - - case FTPM_PPI_CMD_GET_PENDING_OP: - retVal1 = 0; // Success - retVal2 = s_PPIState.PendingPseudoOp; - break; - - case FTPM_PPI_CMD_RETURN_OP_RESP: - retVal1 = 0; // Success - retVal2 = s_PPIState.PseudoOpFromLastBoot; - retVal3 = s_PPIState.ReturnResponse; - break; - - case FTPM_PPI_CMD_SUBMIT_USER_LANG: - retVal1 = 3; // Not Implemented - break; - - case FTPM_PPI_CMD_SUBMIT_OP_REQ2: - switch (Op) { - case FTPM_PPI_OP_NOP: - case FTPM_PPI_OP_ENABLE: - case FTPM_PPI_OP_DISABLE: - case FTPM_PPI_OP_ACTIVATE: - case FTPM_PPI_OP_DEACTIVATE: - case FTPM_PPI_OP_CLEAR: // Causes Clear - case FTPM_PPI_OP_E_A: - case FTPM_PPI_OP_D_D: - case FTPM_PPI_OP_OWNERINSTALL_TRUE: - case FTPM_PPI_OP_OWNERINSTALL_FALSE: - case FTPM_PPI_OP_E_A_OI_TRUE: - case FTPM_PPI_OP_OI_FALSE_D_D: - case FTPM_PPI_OP_FIELD_UPGRADE: - case FTPM_PPI_OP_OPERATOR_AUTH: - case FTPM_PPI_OP_C_E_A: // Causes Clear - case FTPM_PPI_OP_SET_NO_PROV_FALSE: - case FTPM_PPI_OP_SET_NO_PROV_TRUE: - case FTPM_PPI_OP_SET_NO_MAINT_FALSE: - case FTPM_PPI_OP_SET_NO_MAINT_TRUE: - case FTPM_PPI_OP_E_A_C: // Causes Clear - case FTPM_PPI_OP_E_A_C_E_A: // Causes Clear - retVal1 = 0; // Success - s_PPIState.PendingPseudoOp = Op; - _admin__SavePPIState(); - break; - - case FTPM_PPI_OP_SET_NO_CLEAR_FALSE: - case FTPM_PPI_OP_SET_NO_CLEAR_TRUE: - default: - retVal1 = 1; // Not Implemented - break; - } - break; - - case FTPM_PPI_CMD_GET_USER_CONF: - switch (Op) { - case FTPM_PPI_OP_NOP: - case FTPM_PPI_OP_ENABLE: - case FTPM_PPI_OP_DISABLE: - case FTPM_PPI_OP_ACTIVATE: - case FTPM_PPI_OP_DEACTIVATE: - case FTPM_PPI_OP_E_A: - case FTPM_PPI_OP_D_D: - case FTPM_PPI_OP_OWNERINSTALL_TRUE: - case FTPM_PPI_OP_OWNERINSTALL_FALSE: - case FTPM_PPI_OP_E_A_OI_TRUE: - case FTPM_PPI_OP_OI_FALSE_D_D: - retVal1 = 4; // Allowed and PP user NOT required - break; - - case FTPM_PPI_OP_CLEAR: - case FTPM_PPI_OP_C_E_A: - case FTPM_PPI_OP_E_A_C: - case FTPM_PPI_OP_E_A_C_E_A: - retVal1 = 3; // Allowed and PP user required - break; - - default: - retVal1 = 0; // Not Implemented - break; - } - break; - - default: - break; - } - - memcpy(Result1, &retVal1, sizeof(UINT32)); - memcpy(Result2, &retVal2, sizeof(UINT32)); - memcpy(Result3, &retVal3, sizeof(UINT32)); -} - -static TPM2_EmulatePPI_res_t PPIResponse; - -#pragma warning(push) -#pragma warning(disable:28196) -// -// The fTPM TA (OpTEE) may receive, from the TrEE driver, a PPI request -// thru it's ACPI inteface rather than via the TPM_Emulate_PPI command -// we're used to. This function creates a well formes TPM_Emulate_PPI -// command and forwards the request on to _admin__PPICommand to handle. -// -// Return: -// 0 - Omproperly formatted PPI command. -// Otherwise - Return from _admin__PPICommand -// -int -_admin__PPIRequest( - UINT32 CommandSize, - __in_ecount(CommandSize) UINT8 *CommandBuffer, - UINT32 *ResponseSize, - __deref_out_ecount(*ResponseSize) UINT8 **ResponseBuffer - ) -{ - TPM2_EmulatePPI_cmd_t cmd; - TPM2_EmulatePPI_res_t rsp; - TPM2_EmulatePPI_res_t *rspPtr = &rsp; - UINT32 rspLen = sizeof(TPM2_EmulatePPI_res_t); - UINT8 *CmdBuffer; - - // Drop request if CommandSize is invalid - if (CommandSize < sizeof(UINT32)) { - return 0; - } - - CmdBuffer = CommandBuffer; - - cmd.header.tag = __builtin_bswap16(TPM_ST_NO_SESSIONS); - cmd.header.paramSize = __builtin_bswap32(sizeof(TPM2_EmulatePPI_cmd_t)); - cmd.header.commandCode = __builtin_bswap32(TPM_CC_EmulatePPI); - - cmd.inputParameters.FunctionIndex = BYTE_ARRAY_TO_UINT32(CmdBuffer); - CmdBuffer += sizeof(UINT32); - CommandSize -= sizeof(UINT32); - - // Parameter checking is done in _admin__PPICommand but we still need - // to sanity check the size field so as not to overrun CommandBuffer. - if (CommandSize > 0) { - - if (CommandSize < sizeof(UINT32)) - return 0; - - cmd.inputParameters.Op = BYTE_ARRAY_TO_UINT32(CmdBuffer); - } - - if (!_admin__PPICommand(sizeof(TPM2_EmulatePPI_cmd_t), - (UINT8 *)&cmd, - &rspLen, - (UINT8**)&rspPtr)) { - return 0; - } - - memcpy(*ResponseBuffer, &(rsp.outputParameters.Result1), (rspLen - sizeof(TPM2_RESPONSE_HEADER))); - *ResponseSize = (rspLen - sizeof(TPM2_RESPONSE_HEADER)); - return 1; -} - -// -// Return: -// 1 - Command has been consumed -// 0 - Not a properly formated PPI command, caller should pass through to TPM -// -int -_admin__PPICommand( - UINT32 CommandSize, - __in_ecount(CommandSize) UINT8 *CommandBuffer, - UINT32 *ResponseSize, - __deref_out_ecount(*ResponseSize) UINT8 **ResponseBuffer -) -{ - TPM2_EmulatePPI_cmd_t cmd; - UINT8 *CmdBuffer; - UINT32 FunctionIndex; - UINT32 Op; - UINT32 NumberResults = 0; - UINT16 Tag; - - memset(&PPIResponse, 0, sizeof(PPIResponse)); - memset(&cmd, 0, sizeof(cmd)); - - CmdBuffer = CommandBuffer; - - if (CommandSize < sizeof(TPM2_COMMAND_HEADER)) { - PPIResponse.header.responseCode = TPM_RC_COMMAND_SIZE; - goto Exit; - } - - cmd.header.tag = BYTE_ARRAY_TO_UINT16(CmdBuffer); - CmdBuffer += sizeof(UINT16); - CommandSize -= sizeof(UINT16); - - cmd.header.paramSize = BYTE_ARRAY_TO_UINT32(CmdBuffer); - CmdBuffer += sizeof(UINT32); - CommandSize -= sizeof(UINT32); - - cmd.header.commandCode = BYTE_ARRAY_TO_UINT32(CmdBuffer); - CmdBuffer += sizeof(UINT32); - CommandSize -= sizeof(UINT32); - - // - // First check that this must be the command we want to execute - // - if (cmd.header.commandCode != TPM_CC_EmulatePPI) { - return 0; - } - - // - // Must not be a session - // - if (cmd.header.tag != TPM_ST_NO_SESSIONS) { - PPIResponse.header.responseCode = TPM_RC_BAD_TAG; - goto Exit; - } - - // - // Must have enough command space left - // - if (cmd.header.paramSize < CommandSize) { - PPIResponse.header.responseCode = TPM_RC_COMMAND_SIZE; - goto Exit; - } - - if (CommandSize < sizeof(UINT32)) { - PPIResponse.header.responseCode = TPM_RC_COMMAND_SIZE; - goto Exit; - } - - FunctionIndex = BYTE_ARRAY_TO_UINT32(CmdBuffer); - CmdBuffer += sizeof(UINT32); - CommandSize -= sizeof(UINT32); - - switch (FunctionIndex) { - case FTPM_PPI_CMD_QUERY: - case FTPM_PPI_CMD_VERSION: - case FTPM_PPI_CMD_SUBMIT_OP_REQ: - case FTPM_PPI_CMD_GET_PLATFORM_ACTION: - case FTPM_PPI_CMD_SUBMIT_USER_LANG: - NumberResults = 1; - Op = 0; - break; - - case FTPM_PPI_CMD_GET_PENDING_OP: - NumberResults = 2; - Op = 0; - break; - - case FTPM_PPI_CMD_RETURN_OP_RESP: - NumberResults = 3; - Op = 0; - break; - - case FTPM_PPI_CMD_SUBMIT_OP_REQ2: - case FTPM_PPI_CMD_GET_USER_CONF: - NumberResults = 1; - - if (CommandSize < sizeof(UINT32)) { - PPIResponse.header.responseCode = TPM_RC_COMMAND_SIZE; - goto Exit; - } - - Op = BYTE_ARRAY_TO_UINT32(CmdBuffer); - CmdBuffer += sizeof(UINT32); - CommandSize -= sizeof(UINT32); - break; - - default: - NumberResults = 0; - PPIResponse.header.responseCode = TPM_RC_FAILURE; - goto Exit; - } - - - ExecutePPICommand(FunctionIndex, - Op, -#pragma warning (push) -#pragma warning (disable:4366) // The result of unary '&' may be unaligned - &PPIResponse.outputParameters.Result1, - &PPIResponse.outputParameters.Result2, - &PPIResponse.outputParameters.Result3); -#pragma warning (pop) - - PPIResponse.header.responseCode = TPM_RC_SUCCESS; - -Exit: - if (PPIResponse.header.responseCode != TPM_RC_SUCCESS) { - NumberResults = 0; - } - - *ResponseSize = sizeof(TPM2_RESPONSE_HEADER) + (NumberResults * sizeof(UINT32)); - - // - // Fill in tag, and size - // - Tag = TPM_ST_NO_SESSIONS; - PPIResponse.header.tag = BYTE_ARRAY_TO_UINT16((BYTE *)&Tag); - PPIResponse.header.paramSize = BYTE_ARRAY_TO_UINT32((BYTE *)ResponseSize); - PPIResponse.header.responseCode = BYTE_ARRAY_TO_UINT32((BYTE *)&PPIResponse.header.responseCode); - - // - // Results are in host byte order - // - memcpy(*ResponseBuffer, &PPIResponse, (sizeof(PPIResponse) < *ResponseSize) ? sizeof(PPIResponse) : *ResponseSize); - - return 1; -} -#pragma warning(pop) - diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/Cancel.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/Cancel.c deleted file mode 100644 index b0c86db4f..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/Cancel.c +++ /dev/null @@ -1,80 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Description -// -// This module simulates the cancel pins on the TPM. -// -//** Includes, Typedefs, Structures, and Defines -#include "PlatformData.h" -#include "Platform_fp.h" - -//** Functions - -//***_plat__IsCanceled() -// Check if the cancel flag is set -// return type: BOOL -// TRUE(1) if cancel flag is set -// FALSE(0) if cancel flag is not set -LIB_EXPORT int -_plat__IsCanceled( - void - ) -{ - // return cancel flag - return s_isCanceled; -} - -//***_plat__SetCancel() - -// Set cancel flag. -LIB_EXPORT void -_plat__SetCancel( - void - ) -{ - s_isCanceled = TRUE; - return; -} - -//***_plat__ClearCancel() -// Clear cancel flag -LIB_EXPORT void -_plat__ClearCancel( - void - ) -{ - s_isCanceled = FALSE; - return; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/Clock.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/Clock.c deleted file mode 100644 index 37e8ddd2b..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/Clock.c +++ /dev/null @@ -1,302 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Description -// -// This file contains the routines that are used by the simulator to mimic -// a hardware clock on a TPM. -// -// In this implementation, all the time values are measured in millisecond. -// However, the precision of the clock functions may be implementation dependent. - -//** Includes and Data Definitions -#include "PlatformData.h" -#include "Platform_fp.h" -#include "TpmFail_fp.h" -#include -#include - -//** Simulator Functions -//*** Introduction -// This set of functions is intended to be called by the simulator environment in -// order to simulate hardware events. - -//***_plat__TimerReset() -// This function sets current system clock time as t0 for counting TPM time. -// This function is called at a power on event to reset the clock. When the clock -// is reset, the indication that the clock was stopped is also set. -LIB_EXPORT void -_plat__TimerReset( - void - ) -{ -TEE_Result Result; - TEE_Time Time = { 0 }; - - // Reset our TA persistent time, this affects all instances. - Result = TEE_SetTAPersistentTime(&Time); - - // Nothing we can do on failure here. - assert(Result == TEE_SUCCESS); - - s_adjustRate = 0; - s_lastSystemTime = 0; - s_tpmTime = 0; - s_adjustRate = CLOCK_NOMINAL; - s_timerReset = TRUE; - s_timerStopped = TRUE; - - return; -} - -//*** _plat__TimerRestart() -// This function should be called in order to simulate the restart of the timer -// should it be stopped while power is still applied. -LIB_EXPORT void -_plat__TimerRestart( - void - ) -{ - s_timerStopped = TRUE; - return; -} - -//** Functions Used by TPM -//*** Introduction -// These functions are called by the TPM code. They should be replaced by -// appropriated hardware functions. - -#include -TEE_Time debugTime; - -//*** _plat__RealTime() -// This is another, probably futile, attempt to define a portable function -// that will return a 64-bit clock value that has mSec resolution. -uint64_t -_plat__RealTime( - void -) -{ - TEE_Result Result; - TEE_Time Time; - uint64_t Elapsed, Temp; - - Result = TEE_GetTAPersistentTime(&Time); - - // Error conditions from GetTime may be resolved with a clock reset - if ((Result == TEE_ERROR_TIME_NOT_SET) || - (Result == TEE_ERROR_TIME_NEEDS_RESET)) { - // - // REVISIT: Since error conditions from get time may be resolved - // by resetting time. Determine if, when this happens, we see - // an issue with timing in the reference implementaiton. - // - _plat__TimerReset(); - - Result = TEE_GetTAPersistentTime(&Time); - // If the reset didn't resolve the error condision, give up. - assert(Result == TEE_SUCCESS); - } - assert(Result == TEE_SUCCESS); - - Elapsed = ((Time.seconds * 1000) + (Time.millis)); - - return Elapsed; -} - -//***_plat__TimerRead() -// This function provides access to the tick timer of the platform. The TPM code -// uses this value to drive the TPM Clock. -// -// The tick timer is supposed to run when power is applied to the device. This timer -// should not be reset by time events including _TPM_Init. It should only be reset -// when TPM power is re-applied. -// -// If the TPM is run in a protected environment, that environment may provide the -// tick time to the TPM as long as the time provided by the environment is not -// allowed to go backwards. If the time provided by the system can go backwards -// during a power discontinuity, then the _plat__Signal_PowerOn should call -// _plat__TimerReset(). -LIB_EXPORT uint64_t -_plat__TimerRead( - void - ) -{ -#ifdef HARDWARE_CLOCK -#error "need a defintion for reading the hardware clock" - return HARDWARE_CLOCK -#else - clock64_t timeDiff; - clock64_t adjustedTimeDiff; - clock64_t timeNow; - clock64_t readjustedTimeDiff; - - // This produces a timeNow that is basically locked to the system clock. - timeNow = _plat__RealTime(); - - // if this hasn't been initialized, initialize it - if(s_lastSystemTime == 0) - { - s_lastSystemTime = timeNow; - TEE_GetSystemTime(&debugTime); - s_lastReportedTime = 0; - s_realTimePrevious = 0; - } - // The system time can bounce around and that's OK as long as we don't allow - // time to go backwards. When the time does appear to go backwards, set - // lastSystemTime to be the new value and then update the reported time. - if(timeNow < s_lastReportedTime) - s_lastSystemTime = timeNow; - s_lastReportedTime = s_lastReportedTime + timeNow - s_lastSystemTime; - s_lastSystemTime = timeNow; - timeNow = s_lastReportedTime; - - // The code above produces a timeNow that is similar to the value returned - // by Clock(). The difference is that timeNow does not max out, and it is - // at a ms. rate rather than at a CLOCKS_PER_SEC rate. The code below - // uses that value and does the rate adjustment on the time value. - // If there is no difference in time, then skip all the computations - if(s_realTimePrevious >= timeNow) - return s_tpmTime; - // Compute the amount of time since the last update of the system clock - timeDiff = timeNow - s_realTimePrevious; - - // Do the time rate adjustment and conversion from CLOCKS_PER_SEC to mSec - adjustedTimeDiff = (timeDiff * CLOCK_NOMINAL) / ((uint64_t)s_adjustRate); - - // update the TPM time with the adjusted timeDiff - s_tpmTime += (clock64_t)adjustedTimeDiff; - - // Might have some rounding error that would loose CLOCKS. See what is not - // being used. As mentioned above, this could result in putting back more than - // is taken out. Here, we are trying to recreate timeDiff. - readjustedTimeDiff = (adjustedTimeDiff * (uint64_t)s_adjustRate ) - / CLOCK_NOMINAL; - - // adjusted is now converted back to being the amount we should advance the - // previous sampled time. It should always be less than or equal to timeDiff. - // That is, we could not have use more time than we started with. - s_realTimePrevious = s_realTimePrevious + readjustedTimeDiff; - -#ifdef DEBUGGING_TIME - // Put this in so that TPM time will pass much faster than real time when - // doing debug. - // A value of 1000 for DEBUG_TIME_MULTIPLER will make each ms into a second - // A good value might be 100 - return (s_tpmTime * DEBUG_TIME_MULTIPLIER); -#endif - return s_tpmTime; -#endif -} - - - -//*** _plat__TimerWasReset() -// This function is used to interrogate the flag indicating if the tick timer has -// been reset. -// -// If the resetFlag parameter is SET, then the flag will be CLEAR before the -// function returns. -LIB_EXPORT BOOL -_plat__TimerWasReset( - void - ) -{ - BOOL retVal = s_timerReset; - s_timerReset = FALSE; - return retVal; -} - -//*** _plat__TimerWasStopped() -// This function is used to interrogate the flag indicating if the tick timer has -// been stopped. If so, this is typically a reason to roll the nonce. -// -// This function will CLEAR the s_timerStopped flag before returning. This provides -// functionality that is similar to status register that is cleared when read. This -// is the model used here because it is the one that has the most impact on the TPM -// code as the flag can only be accessed by one entity in the TPM. Any other -// implementation of the hardware can be made to look like a read-once register. -LIB_EXPORT BOOL -_plat__TimerWasStopped( - void - ) -{ - BOOL retVal = s_timerStopped; - s_timerStopped = FALSE; - return retVal; -} - -//***_plat__ClockAdjustRate() -// Adjust the clock rate -LIB_EXPORT void -_plat__ClockAdjustRate( - int adjust // IN: the adjust number. It could be positive - // or negative - ) -{ - // We expect the caller should only use a fixed set of constant values to - // adjust the rate - switch(adjust) - { - case CLOCK_ADJUST_COARSE: - s_adjustRate += CLOCK_ADJUST_COARSE; - break; - case -CLOCK_ADJUST_COARSE: - s_adjustRate -= CLOCK_ADJUST_COARSE; - break; - case CLOCK_ADJUST_MEDIUM: - s_adjustRate += CLOCK_ADJUST_MEDIUM; - break; - case -CLOCK_ADJUST_MEDIUM: - s_adjustRate -= CLOCK_ADJUST_MEDIUM; - break; - case CLOCK_ADJUST_FINE: - s_adjustRate += CLOCK_ADJUST_FINE; - break; - case -CLOCK_ADJUST_FINE: - s_adjustRate -= CLOCK_ADJUST_FINE; - break; - default: - // ignore any other values; - break; - } - - if(s_adjustRate > (CLOCK_NOMINAL + CLOCK_ADJUST_LIMIT)) - s_adjustRate = CLOCK_NOMINAL + CLOCK_ADJUST_LIMIT; - if(s_adjustRate < (CLOCK_NOMINAL - CLOCK_ADJUST_LIMIT)) - s_adjustRate = CLOCK_NOMINAL - CLOCK_ADJUST_LIMIT; - - return; -} - diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/EPS.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/EPS.c deleted file mode 100644 index c8fb553c7..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/EPS.c +++ /dev/null @@ -1,90 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -// -// Platform Endorsement Primary Seed -// - -#include "TpmError.h" -#include "Admin.h" - -#include -#include - -#define TEE_EPS_SIZE (256/2) // From TPM2B_RSA_TEST_PRIME in Hierarchy.c - -void -_plat__GetEPS(UINT16 Size, uint8_t *EndorsementSeed) -{ - TEE_Result Result = TEE_ERROR_ITEM_NOT_FOUND; - uint8_t EPS[TEE_EPS_SIZE] = { 0 }; - size_t EPSLen; - - IMSG("Size=%" PRIu16 "",Size); - IMSG("EPS=%d",TEE_EPS_SIZE); - - pAssert(Size <= (TEE_EPS_SIZE)); - - Result = TEE_GetPropertyAsBinaryBlock(TEE_PROPSET_CURRENT_TA, - "com.microsoft.ta.endorsementSeed", - EPS, - &EPSLen); - - if ((EPSLen < Size) || (Result != TEE_SUCCESS)) { - // We failed to access the property. We can't continue without it - // and we can't just fail to manufacture, so randomize EPS and - // continue. If necessary, fTPM TA storage can be cleared, or the - // TA updated, and we can trigger remanufacture and try again. - _plat__GetEntropy(EndorsementSeed, TEE_EPS_SIZE); - return; - } - - memcpy(EndorsementSeed, EPS, Size); - -#ifdef fTPMDebug - { - uint32_t x; - uint8_t *seed = EndorsementSeed; - DMSG("TEE_GetProperty 0x%x, seedLen 0x%x\n", Result, Size); - for (x = 0; x < Size; x = x + 8) { - DMSG(" seed(%2.2d): %2.2x,%2.2x,%2.2x,%2.2x,%2.2x,%2.2x,%2.2x,%2.2x\n", x, - seed[x + 0], seed[x + 1], seed[x + 2], seed[x + 3], - seed[x + 4], seed[x + 5], seed[x + 6], seed[x + 7]); - } - } -#endif - - return; -} diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/Entropy.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/Entropy.c deleted file mode 100644 index 3bb2283ea..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/Entropy.c +++ /dev/null @@ -1,128 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Includes and Local Values - -#define _CRT_RAND_S -#include -#include -#include "PlatformData.h" -#include "Platform_fp.h" -#include - -#include - -#ifdef _MSC_VER -#include -#else -#include -#endif - -// This is the last 32-bits of hardware entropy produced. We have to check to -// see that two consecutive 32-bit values are not the same because -// (according to FIPS 140-2, annex C -// -// 1. If each call to a RNG produces blocks of n bits (where n > 15), the first -// n-bit block generated after power-up, initialization, or reset shall not be -// used, but shall be saved for comparison with the next n-bit block to be -// generated. Each subsequent generation of an n-bit block shall be compared with -// the previously generated block. The test shall fail if any two compared n-bit -// blocks are equal. -extern uint32_t lastEntropy; - -//** Functions - -//*** rand32() -// Local function to get a 32-bit random number -static uint32_t -rand32( - void -) -{ - - uint32_t rndNum; - TEE_GenerateRandom((void *)(&rndNum), sizeof(uint32_t)); - return rndNum; -} - - -//** _plat__GetEntropy() -// This function is used to get available hardware entropy. In a hardware -// implementation of this function, there would be no call to the system -// to get entropy. -// return type: int32_t -// < 0 hardware failure of the entropy generator, this is sticky -// >= 0 the returned amount of entropy (bytes) -// -LIB_EXPORT int32_t -_plat__GetEntropy( - unsigned char *entropy, // output buffer - uint32_t amount // amount requested -) -{ - uint32_t rndNum; - int32_t ret; - - if(amount == 0) - { - lastEntropy = rand32(); - ret = 0; - } - else - { - rndNum = rand32(); - if(rndNum == lastEntropy) - { - ret = -1; - } - else - { - lastEntropy = rndNum; - // Each process will have its random number generator initialized according - // to the process id and the initialization time. This is not a lot of - // entropy so, to add a bit more, XOR the current time value into the - // returned entropy value. - // NOTE: the reason for including the time here rather than have it in - // in the value assigned to lastEntropy is that rand() could be broken and - // using the time would in the lastEntropy value would hide this. - rndNum ^= (uint32_t)_plat__RealTime(); - - // Only provide entropy 32 bits at a time to test the ability - // of the caller to deal with partial results. - ret = MIN(amount, sizeof(rndNum)); - memcpy(entropy, &rndNum, ret); - } - } - return ret; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/LocalityPlat.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/LocalityPlat.c deleted file mode 100644 index 22ca28b88..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/LocalityPlat.c +++ /dev/null @@ -1,65 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Includes - -#include "PlatformData.h" -#include "Platform_fp.h" - -//** Functions - -//***_plat__LocalityGet() -// Get the most recent command locality in locality value form. -// This is an integer value for locality and not a locality structure -// The locality can be 0-4 or 32-255. 5-31 is not allowed. -LIB_EXPORT unsigned char -_plat__LocalityGet( - void - ) -{ - return s_locality; -} - -//***_plat__LocalitySet() -// Set the most recent command locality in locality value form -LIB_EXPORT void -_plat__LocalitySet( - unsigned char locality - ) -{ - if(locality > 4 && locality < 32) - locality = 0; - s_locality = locality; - return; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/NVMem.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/NVMem.c deleted file mode 100644 index 908806bf5..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/NVMem.c +++ /dev/null @@ -1,646 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Description -// -// This file contains the NV read and write access methods. This implementation -// uses RAM/file and does not manage the RAM/file as NV blocks. -// The implementation may become more sophisticated over time. -// - -#include "TpmError.h" -#include "Admin.h" -#include "VendorString.h" -#include "stdint.h" -#include "malloc.h" -#include "string.h" - -#include -#include - -// -// Overall size of NV, not just the TPM's NV storage -// -#define NV_CHIP_MEMORY_SIZE (NV_MEMORY_SIZE + NV_TPM_STATE_SIZE) - -// -// OpTEE still has an all or nothing approach to reads/writes. To provide -// more performant access to storage, break up NV accross 1Kbyte blocks. -// -// Note that NV_CHIP_MEMORY_SIZE *MUST* be a factor of NV_BLOCK_SIZE. -// -#define NV_BLOCK_SIZE 0x200 -#define NV_BLOCK_COUNT ((NV_CHIP_MEMORY_SIZE) / (NV_BLOCK_SIZE)) - -// -// For cleaner descriptor validation -// -#define IS_VALID(a) ((a) != (TEE_HANDLE_NULL)) - -// -// Storage flags -// -#define TA_STORAGE_FLAGS (TEE_DATA_FLAG_ACCESS_READ | \ - TEE_DATA_FLAG_ACCESS_WRITE | \ - TEE_DATA_FLAG_ACCESS_WRITE_META) - -// -// The base Object ID for fTPM storage -// -static const UINT32 s_StorageObjectID = 0x54504D00; // 'TPM00' - -// -// Object handle list for persistent storage objects containing NV -// -static TEE_ObjectHandle s_NVStore[NV_BLOCK_COUNT] = { TEE_HANDLE_NULL }; - -// -// Bitmap for NV blocks. Moving from UINT64 requires change to NV_DIRTY_ALL. -// -static UINT64 s_blockMap = 0x0ULL; - -// -// Shortcut for 'dirty'ing all NV blocks. Note the type. -// -#if NV_BLOCK_COUNT < 64 -#define NV_DIRTY_ALL ((UINT64)((0x1ULL << NV_BLOCK_COUNT) - 1)) -#elif NV_BLOCK_COUNT == 64 -#define NV_DIRTY_ALL (~(0x0ULL)) -#else -#error "NV block count exceeds 64 bit block map. Adjust block or NV size." -#endif - -// -// NV state -// -static BOOL s_NVChipFileNeedsManufacture = FALSE; -static BOOL s_NVInitialized = FALSE; -static UCHAR s_NV[NV_CHIP_MEMORY_SIZE]; - -// -// Firmware revision -// -static const UINT32 firmwareV1 = FIRMWARE_V1; -static const UINT32 firmwareV2 = FIRMWARE_V2; - -// -// Revision fro NVChip -// -static UINT64 s_chipRevision = 0; - -// -// This offset puts the revision field immediately following the TPM Admin -// state. The Admin space in NV is down to ~16 bytes but is padded out to -// 256bytes to avoid alignment issues and allow for growth. -// -#define NV_CHIP_REVISION_OFFSET ((NV_MEMORY_SIZE) + (TPM_STATE_SIZE)) - -VOID -_plat__NvInitFromStorage() -{ - DMSG("_plat__NvInitFromStorage()"); - UINT32 i; - BOOL initialized; - UINT32 objID; - UINT32 bytesRead; - TEE_Result Result; - - // Don't re-initialize. - if (s_NVInitialized) { - return; - } - - // - // If the NV file is successfully read from the storage then - // initialized must be set. We are setting initialized to true - // here but if an error is encountered reading the NV file it will - // be reset. - // - - initialized = TRUE; - - // Collect storage objects and init NV. - for (i = 0; i < NV_BLOCK_COUNT; i++) { - - // Form storage object ID for this block. - objID = s_StorageObjectID + i; - - // Attempt to open TEE persistent storage object. - Result = TEE_OpenPersistentObject(TEE_STORAGE_PRIVATE, - (void *)&objID, - sizeof(objID), - TA_STORAGE_FLAGS, - &s_NVStore[i]); - - // If the open failed, try to create this storage object. - if (Result != TEE_SUCCESS) { - - // There was an error, fail the init, NVEnable can retry. - if (Result != TEE_ERROR_ITEM_NOT_FOUND) { -#ifdef fTPMDebug - DMSG("Failed to open fTPM storage object"); -#endif - goto Error; - } - - // Storage object was not found, create it. - Result = TEE_CreatePersistentObject(TEE_STORAGE_PRIVATE, - (void *)&objID, - sizeof(objID), - TA_STORAGE_FLAGS, - NULL, - (void *)&(s_NV[i * NV_BLOCK_SIZE]), - NV_BLOCK_SIZE, - &s_NVStore[i]); - - // There was an error, fail the init, NVEnable can retry. - if (Result != TEE_SUCCESS) { -#ifdef fTPMDebug - DMSG("Failed to create fTPM storage object"); -#endif - goto Error; - } - - // A clean storage object was created, we must (re)manufacture. - s_NVChipFileNeedsManufacture = TRUE; - - // To ensure NV is consistent, force a write back of all NV blocks - s_blockMap = NV_DIRTY_ALL; - - // Need to re-initialize - initialized = FALSE; - -#ifdef fTPMDebug - IMSG("Created fTPM storage object, i: 0x%x, s: 0x%x, id: 0x%x, h:0x%x\n", - i, NV_BLOCK_SIZE, objID, s_NVStore[i]); -#endif - } - else { - // Successful open, now read fTPM storage object. - Result = TEE_ReadObjectData(s_NVStore[i], - (void *)&(s_NV[i * NV_BLOCK_SIZE]), - NV_BLOCK_SIZE, - &bytesRead); - - // Give up on failed or incomplete reads. - if ((Result != TEE_SUCCESS) || (bytesRead != NV_BLOCK_SIZE)) { -#ifdef fTPMDebug - DMSG("Failed to read fTPM storage object"); -#endif - goto Error; - } - -#ifdef fTPMDebug - IMSG("Read fTPM storage object, i: 0x%x, s: 0x%x, id: 0x%x, h:0x%x\n", - i, bytesRead, objID, s_NVStore[i]); -#endif - } - } - - // Storage objects are open and valid, next validate revision - s_chipRevision = ((((UINT64)firmwareV2) << 32) | (firmwareV1)); - if ((s_chipRevision != *(UINT64*)&(s_NV[NV_CHIP_REVISION_OFFSET]))) { - - // Failure to validate revision, re-init. - memset(s_NV, 0, NV_CHIP_MEMORY_SIZE); - - // Dirty the block map, we're going to re-init. - s_blockMap = NV_DIRTY_ALL; - - // Init with proper revision - s_chipRevision = ((((UINT64)firmwareV2) << 32) | (firmwareV1)); - *(UINT64*)&(s_NV[NV_CHIP_REVISION_OFFSET]) = s_chipRevision; - -#ifdef fTPMDebug - DMSG("Failed to validate revision."); -#endif - - // Force (re)manufacture. - s_NVChipFileNeedsManufacture = TRUE; - - // Need to re-initialize - initialized = FALSE; - - return; - } - - s_NVInitialized = initialized; - - return; - -Error: - s_NVInitialized = FALSE; - for (i = 0; i < NV_BLOCK_COUNT; i++) { - if (IS_VALID(s_NVStore[i])) { - TEE_CloseObject(s_NVStore[i]); - s_NVStore[i] = TEE_HANDLE_NULL; - } - } - - return; -} - - -static void -_plat__NvWriteBack() -{ - UINT32 i; - UINT32 objID; - TEE_Result Result; - - // Exit if no dirty blocks. - if ((!s_blockMap) || (!s_NVInitialized)) { - return; - } - -#ifdef fTPMDebug - DMSG("bMap: 0x%x\n", s_blockMap); -#endif - - // Write dirty blocks. - for (i = 0; i < NV_BLOCK_COUNT; i++) { - - if ((s_blockMap & (0x1ULL << i))) { - - // Form storage object ID for this block. - objID = s_StorageObjectID + i; - - // Move data position associated with handle to start of block. - Result = TEE_SeekObjectData(s_NVStore[i], 0, TEE_DATA_SEEK_SET); - if (Result != TEE_SUCCESS) { - goto Error; - } - - // Write out this block. - Result = TEE_WriteObjectData(s_NVStore[i], - (void *)&(s_NV[i * NV_BLOCK_SIZE]), - NV_BLOCK_SIZE); - if (Result != TEE_SUCCESS) { - goto Error; - } - - // Force storage stack to update its backing store - TEE_CloseObject(s_NVStore[i]); - - Result = TEE_OpenPersistentObject(TEE_STORAGE_PRIVATE, - (void *)&objID, - sizeof(objID), - TA_STORAGE_FLAGS, - &s_NVStore[i]); - // Success? - if (Result != TEE_SUCCESS) { - goto Error; - } - - // Clear dirty bit. - s_blockMap &= ~(0x1ULL << i); - } - } - - return; - -Error: - // Error path. -#ifdef fTPMDebug - DMSG("NV write back failed"); -#endif - s_NVInitialized = FALSE; - for (i = 0; i < NV_BLOCK_COUNT; i++) { - if (IS_VALID(s_NVStore[i])) { - TEE_CloseObject(s_NVStore[i]); - s_NVStore[i] = TEE_HANDLE_NULL; - } - } - - return; -} - - -BOOL -_plat__NvNeedsManufacture() -{ - return s_NVChipFileNeedsManufacture; -} - -//***_plat__NVEnable() -// Enable NV memory. -// -// This version just pulls in data from a file. In a real TPM, with NV on chip, -// this function would verify the integrity of the saved context. If the NV -// memory was not on chip but was in something like RPMB, the NV state would be -// read in, decrypted and integrity checked. -// -// The recovery from an integrity failure depends on where the error occurred. It -// it was in the state that is discarded by TPM Reset, then the error is -// recoverable if the TPM is reset. Otherwise, the TPM must go into failure mode. -// return type: int -// 0 if success -// > 0 if receive recoverable error -// <0 if unrecoverable error -LIB_EXPORT int -_plat__NVEnable( - void *platParameter // IN: platform specific parameters - ) -{ - UNREFERENCED_PARAMETER(platParameter); - DMSG("_plat__NVEnable()"); - - - UINT32 retVal = 0; - UINT32 firmwareV1 = FIRMWARE_V1; - UINT32 firmwareV2 = FIRMWARE_V2; - - // Don't re-open the backing store. - if (s_NVInitialized) { - return 0; - } - - // Clear NV - memset(s_NV, 0, NV_CHIP_MEMORY_SIZE); - - // Prepare for potential failure to retreieve NV from storage - s_chipRevision = ((((UINT64)firmwareV2) << 32) | (firmwareV1)); - *(UINT64*)&(s_NV[NV_CHIP_REVISION_OFFSET]) = s_chipRevision; - - // Pick up our NV memory. - _plat__NvInitFromStorage(); - - // Were we successful? - if (!s_NVInitialized) { - // Arriving here means one of two things: Either there existed no - // NV state before we came along and we just (re)initialized our - // storage. Or there is an error condition preventing us from - // accessing storage. Check which is the case. - if (s_NVChipFileNeedsManufacture == FALSE) { - // This condition means we cannot access storage. However, it - // isn't up to the platform layer to decide what to do in this - // case. The decision to proceed is made in the fTPM init code - // in TA_CreateEntryPoint. Here, we're going to make sure that, - // should we decide not to just TEE_Panic, we can continue - // execution after (re)manufacture. Later an attempt at re-init - // can be made by calling _plat__NvInitFromStorage again. - retVal = 0; - } - else { - retVal = 1; - } - - // Going to manufacture, zero flags - g_chipFlags.flags = 0; - - // Save flags - _admin__SaveChipFlags(); - - // Now we're done - s_NVInitialized = TRUE; - - return retVal; - } - else { - // In the transition out of UEFI to Windows, we may not tear down - // the TA. We close out one session and start another. This means - // our s_NVChipFileNeedsManufacture flag, if set, will be stale. - // Make sure we don't re-manufacture. - s_NVChipFileNeedsManufacture = FALSE; - - // We successfully initialized NV now pickup TPM state. - _admin__RestoreChipFlags(); - - // Success - retVal = 1; - } - - return retVal; -} - -//***_plat__NVDisable() -// Disable NV memory -LIB_EXPORT void -_plat__NVDisable( - void - ) -{ - UINT32 i; - - if (!s_NVInitialized) { - return; - } - - // Final write - _plat__NvWriteBack(); - - // Close out all handles - for (i = 0; i < NV_BLOCK_COUNT; i++) { - if (IS_VALID(s_NVStore[i])) { - TEE_CloseObject(s_NVStore[i]); - s_NVStore[i] = TEE_HANDLE_NULL; - } - } - - // We're no longer init-ed - s_NVInitialized = FALSE; - - return; -} - -//***_plat__IsNvAvailable() -// Check if NV is available -// return type: int -// 0 NV is available -// 1 NV is not available due to write failure -// 2 NV is not available due to rate limit -LIB_EXPORT int -_plat__IsNvAvailable( - void - ) -{ - // This is not enabled for OpTEE TA. Storage is always available. - return 0; -} - - - -//***_plat__NvMemoryRead() -// Function: Read a chunk of NV memory -LIB_EXPORT void -_plat__NvMemoryRead( - unsigned int startOffset, // IN: read start - unsigned int size, // IN: size of bytes to read - void *data // OUT: data buffer - ) -{ - pAssert((startOffset + size) <= NV_CHIP_MEMORY_SIZE); - pAssert(s_NV != NULL); - - memcpy(data, &s_NV[startOffset], size); -} - -//*** _plat__NvIsDifferent() -// This function checks to see if the NV is different from the test value. This is -// so that NV will not be written if it has not changed. -// return value: int -// TRUE(1) the NV location is different from the test value -// FALSE(0) the NV location is the same as the test value -LIB_EXPORT int -_plat__NvIsDifferent( - unsigned int startOffset, // IN: read start - unsigned int size, // IN: size of bytes to read - void *data // IN: data buffer - ) -{ - return (memcmp(&s_NV[startOffset], data, size) != 0); -} - -static -void -_plat__MarkDirtyBlocks ( - unsigned int startOffset, - unsigned int size -) -{ - unsigned int blockEnd; - unsigned int blockStart; - unsigned int i; - - // - // Integer math will round down to the start of the block. - // blockEnd is actually the last block + 1. - // - - blockStart = startOffset / NV_BLOCK_SIZE; - blockEnd = (startOffset + size) / NV_BLOCK_SIZE; - if ((startOffset + size) % NV_BLOCK_SIZE != 0) { - blockEnd += 1; - } - - for (i = blockStart; i < blockEnd; i++) { - s_blockMap |= (0x1ULL << i); - } -} - -//***_plat__NvMemoryWrite() -// This function is used to update NV memory. The "write" is to a memory copy of -// NV. At the end of the current command, any changes are written to -// the actual NV memory. -// NOTE: A useful optimization would be for this code to compare the current -// contents of NV with the local copy and note the blocks that have changed. Then -// only write those blocks when _plat__NvCommit() is called. -LIB_EXPORT void -_plat__NvMemoryWrite( - unsigned int startOffset, // IN: write start - unsigned int size, // IN: size of bytes to write - void *data // OUT: data buffer - ) -{ - pAssert(startOffset + size <= NV_CHIP_MEMORY_SIZE); - pAssert(s_NV != NULL); - - _plat__MarkDirtyBlocks(startOffset, size); - memcpy(&s_NV[startOffset], data, size); -} - -//***_plat__NvMemoryClear() -// Function is used to set a range of NV memory bytes to an implementation-dependent -// value. The value represents the erase state of the memory. -LIB_EXPORT void -_plat__NvMemoryClear( - unsigned int start, // IN: clear start - unsigned int size // IN: number of bytes to clear - ) -{ - pAssert(start + size <= NV_MEMORY_SIZE); - - _plat__MarkDirtyBlocks(start, size); - memset(&s_NV[start], 0, size); -} - -//***_plat__NvMemoryMove() -// Function: Move a chunk of NV memory from source to destination -// This function should ensure that if there overlap, the original data is -// copied before it is written -LIB_EXPORT void -_plat__NvMemoryMove( - unsigned int sourceOffset, // IN: source offset - unsigned int destOffset, // IN: destination offset - unsigned int size // IN: size of data being moved - ) -{ - pAssert(sourceOffset + size <= NV_CHIP_MEMORY_SIZE); - pAssert(destOffset + size <= NV_CHIP_MEMORY_SIZE); - pAssert(s_NV != NULL); - - _plat__MarkDirtyBlocks(sourceOffset, size); - _plat__MarkDirtyBlocks(destOffset, size); - - memmove(&s_NV[destOffset], &s_NV[sourceOffset], size); -} - -//***_plat__NvCommit() -// This function writes the local copy of NV to NV for permanent store. It will write -// NV_MEMORY_SIZE bytes to NV. If a file is use, the entire file is written. -// return type: int -// 0 NV write success -// non-0 NV write fail -LIB_EXPORT int -_plat__NvCommit( - void - ) -{ - _plat__NvWriteBack(); - return 0; -} - -//***_plat__SetNvAvail() -// Set the current NV state to available. This function is for testing purpose -// only. It is not part of the platform NV logic -LIB_EXPORT void -_plat__SetNvAvail( - void - ) -{ - // NV will not be made unavailable on this platform - return; -} - -//***_plat__ClearNvAvail() -// Set the current NV state to unavailable. This function is for testing purpose -// only. It is not part of the platform NV logic -LIB_EXPORT void -_plat__ClearNvAvail( - void - ) -{ - // The anti-set; not on this platform. - return; -} diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/NvAdmin.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/NvAdmin.c deleted file mode 100644 index 257600153..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/NvAdmin.c +++ /dev/null @@ -1,151 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//**Includes -// Force Global.h contents inclusion -#define GLOBAL_C - -#include "Admin.h" - -//**Types, Structures, and Defines -// -// List of pre-defined address of TPM state data -// -static UINT32 s_stateAddr[NV_TPM_STATE_LAST]; - -// -// List of pre-defined TPM state data size in byte -// -static UINT32 s_stateSize[NV_TPM_STATE_LAST]; - -// -// The current chip state -// -TPM_CHIP_STATE g_chipFlags; - -// -// The current PPI state -// -extern FTPM_PPI_STATE s_PPIState; - -//***_admin__NvInitState() -// Initialize the state NV runtime state values -void -_admin__NvInitState() -{ - UINT16 i; - UINT32 stateAddr; - - // - // Initialize TPM saved runtime state - // - s_stateSize[NV_TPM_STATE_FLAGS] = sizeof(TPM_CHIP_STATE); - s_stateSize[NV_TPM_STATE_PPI] = sizeof(FTPM_PPI_STATE); - - // - // Initialize TPM state data addresses. Stored after the main NV space. - // - stateAddr = NV_MEMORY_SIZE; - for (i = 0; i < NV_TPM_STATE_LAST; i++) { - s_stateAddr[i] = stateAddr; - stateAddr += s_stateSize[i]; - } - - pAssert(stateAddr <= (NV_MEMORY_SIZE + NV_TPM_STATE_SIZE)); -} - -//***_admin__SaveChipFlags() -// Save the g_chipFlags runtime state -void -_admin__SaveChipFlags() -{ - _admin__NvWriteState(NV_TPM_STATE_FLAGS, &g_chipFlags); -} - -//***_admin__RestoreChipFlags() -// Restore the g_chipFlags runtime state -void -_admin__RestoreChipFlags() -{ - _admin__NvReadState(NV_TPM_STATE_FLAGS, &g_chipFlags); -} - -//***_admin__SavePPIState() -// Save the s_PPIState runtime state -void -_admin__SavePPIState() -{ - _admin__NvWriteState(NV_TPM_STATE_PPI, &s_PPIState); - - _plat__NvCommit(); -} - -//***_admin__RestorePPIState() -// Restore the s_PPIState runtime state -void -_admin__RestorePPIState() -{ - _admin__NvReadState(NV_TPM_STATE_PPI, &s_PPIState); -} - -//***_admin__NvReadState() -// Read TPM state data from NV memory to RAM -void -_admin__NvReadState( - NV_TPM_STATE type, // IN: type of state data - void *buffer // OUT: data buffer - ) -{ - // Input type should be valid - pAssert(type >= 0 && type < NV_TPM_STATE_LAST); - - _plat__NvMemoryRead(s_stateAddr[type], s_stateSize[type], buffer); - return; -} - -//***_admin__NvWriteState() -// Write TPM state data to NV memory -void -_admin__NvWriteState( - NV_TPM_STATE type, // IN: type of state data - void *buffer // IN: data buffer - ) -{ - // Input type should be valid - pAssert(type >= 0 && type < NV_TPM_STATE_LAST); - - _plat__NvMemoryWrite(s_stateAddr[type], s_stateSize[type], buffer); - return; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/PPPlat.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/PPPlat.c deleted file mode 100644 index 66583d905..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/PPPlat.c +++ /dev/null @@ -1,80 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Description - -// This module simulates the physical presence interface pins on the TPM. - -//** Includes -#include "PlatformData.h" -#include "Platform_fp.h" - -//** Functions - -//***_plat__PhysicalPresenceAsserted() -// Check if physical presence is signaled -// return type: int -// TRUE(1) if physical presence is signaled -// FALSE(0) if physical presence is not signaled -LIB_EXPORT int -_plat__PhysicalPresenceAsserted( - void - ) -{ - // Do not know how to check physical presence without real hardware. - // so always return TRUE; - return s_physicalPresence; -} - -//***_plat__Signal_PhysicalPresenceOn() -// Signal physical presence on -LIB_EXPORT void -_plat__Signal_PhysicalPresenceOn( - void - ) -{ - s_physicalPresence = TRUE; - return; -} - -//***_plat__Signal_PhysicalPresenceOff() -// Signal physical presence off -LIB_EXPORT void -_plat__Signal_PhysicalPresenceOff( - void - ) -{ - s_physicalPresence = FALSE; - return; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/PlatformData.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/PlatformData.c deleted file mode 100644 index ee2656d6a..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/PlatformData.c +++ /dev/null @@ -1,82 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Description -// This file will instance the TPM variables that are not stack allocated. The -// descriptions for these variables are in Global.h for this project. - -//** Includes -#include "Implementation.h" -#include "PlatformData.h" - -// From Cancel.c -BOOL s_isCanceled; - -// From Clock.c -unsigned int s_adjustRate; -BOOL s_timerReset; -BOOL s_timerStopped; - -#ifndef HARDWARE_CLOCK -clock64_t s_realTimePrevious; -clock64_t s_tpmTime; - -clock64_t s_lastSystemTime; -clock64_t s_lastReportedTime; - - -#endif - - -// From LocalityPlat.c -unsigned char s_locality; - -// From Power.c -BOOL s_powerLost; - -// From Entropy.c -// This values is used to determine if the entropy generator is broken. If two -// consecutive values are the same, then the entropy generator is considered to be -// broken. -uint32_t lastEntropy; - - -// For NVMem.c -unsigned char s_NV[NV_MEMORY_SIZE]; -BOOL s_NvIsAvailable; -BOOL s_NV_unrecoverable; -BOOL s_NV_recoverable; - -// From PPPlat.c -BOOL s_physicalPresence; \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/PowerPlat.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/PowerPlat.c deleted file mode 100644 index 5acc456b7..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/PowerPlat.c +++ /dev/null @@ -1,113 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Includes and Function Prototypes - -#include "PlatformData.h" -#include "Platform_fp.h" -#include "_TPM_Init_fp.h" - -//** Functions - -//***_plat__Signal_PowerOn() -// Signal platform power on -LIB_EXPORT int -_plat__Signal_PowerOn( - void - ) -{ - // Reset the timer - _plat__TimerReset(); - - // Need to indicate that we lost power - s_powerLost = TRUE; - - return 0; -} - -//*** _plat__WasPowerLost() -// Test whether power was lost before a _TPM_Init. -// -// This function will clear the "hardware" indication of power loss before return. -// This means that there can only be one spot in the TPM code where this value -// gets read. This method is used here as it is the most difficult to manage in the -// TPM code and, if the hardware actually works this way, it is hard to make it -// look like anything else. So, the burden is placed on the TPM code rather than the -// platform code -// return type: int -// TRUE(1) power was lost -// FALSE(0) power was not lost -LIB_EXPORT int -_plat__WasPowerLost( - void - ) -{ - BOOL retVal = s_powerLost; - s_powerLost = FALSE; - return retVal; -} - -//*** _plat_Signal_Reset() -// This a TPM reset without a power loss. -LIB_EXPORT int -_plat__Signal_Reset( - void - ) -{ - // Initialize locality - s_locality = 0; - - // Command cancel - s_isCanceled = FALSE; - - _TPM_Init(); - - // if we are doing reset but did not have a power failure, then we should - // not need to reload NV ... - - return 0; -} - -//***_plat__Signal_PowerOff() -// Signal platform power off -LIB_EXPORT void -_plat__Signal_PowerOff( - void - ) -{ - // Prepare NV memory for power off - _plat__NVDisable(); - - return; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/RunCommand.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/RunCommand.c deleted file mode 100644 index a2fd696bb..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/RunCommand.c +++ /dev/null @@ -1,90 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//**Introduction -// This module provides the platform specific entry and fail processing. The -// _plat__RunCommand() function is used to call to ExecuteCommand() in the TPM code. -// This function does whatever processing is necessary to set up the platform -// in anticipation of the call to the TPM including settup for error processing. -// -// The _plat__Fail() function is called when there is a failure in the TPM. The TPM -// code will have set the flag to indicate that the TPM is in failure mode. -// This call will then recursively call ExecuteCommand in order to build the -// failure mode response. When ExecuteCommand() returns to _plat__Fail(), the -// platform will do some platform specif operation to return to the environment in -// which the TPM is executing. For a simulator, setjmp/longjmp is used. For an OS, -// a system exit to the OS would be appropriate. - -//** Includes and locals -#include "PlatformData.h" -#include "Platform_fp.h" -#include -#include "ExecCommand_fp.h" - -#include -#include - -jmp_buf s_jumpBuffer; - -//** Functions - -//***_plat__RunCommand() -// This version of RunCommand will set up a jum_buf and call ExecuteCommand(). If -// the command executes without failing, it will return and RunCommand will return. -// If there is a failure in the command, then _plat__Fail() is called and it will -// longjump back to RunCommand which will call ExecuteCommand again. However, this -// time, the TPM will be in failure mode so ExecuteCommand will simply build -// a failure response and return. -LIB_EXPORT void -_plat__RunCommand( - uint32_t requestSize, // IN: command buffer size - unsigned char *request, // IN: command buffer - uint32_t *responseSize, // IN/OUT: response buffer size - unsigned char **response // IN/OUT: response buffer - ) -{ - setjmp(s_jumpBuffer); - ExecuteCommand(requestSize, request, responseSize, response); -} - - -//***_plat__Fail() -// This is the platform depended failure exit for the TPM. -LIB_EXPORT NORETURN void -_plat__Fail( - void - ) -{ - TEE_Panic(TEE_ERROR_BAD_STATE); -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/Unique.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/Unique.c deleted file mode 100644 index 9221057ac..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/Unique.c +++ /dev/null @@ -1,102 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Introduction -// In some implementations of the TPM, the hardware can provide a secret -// value to the TPM. This secret value is statistically unique to the -// instance of the TPM. Typical uses of this value are to provide -// personalization to the random number generation and as a shared secret -// between the TPM and the manufacturer. - -//** Includes -#include "PlatformData.h" -#include "Platform_fp.h" - -#include -#include - -//static TEE_UUID deviceUniqueValue = { 0 }; -static char *deviceUniqueValue[sizeof(TEE_UUID)+1]; -static bool initializedUniqueValue = false; - -//** _plat__GetUnique() -// This function is used to access the platform-specific unique value. -// This function places the unique value in the provided buffer ('b') -// and returns the number of bytes transferred. The function will not -// copy more data than 'bSize'. -// NOTE: If a platform unique value has unequal distribution of uniqueness -// and 'bSize' is smaller than the size of the unique value, the 'bSize' -// portion with the most uniqueness should be returned. -LIB_EXPORT uint32_t -_plat__GetUnique( - uint32_t which, // authorities (0) or details - uint32_t bSize, // size of the buffer - unsigned char *b // output buffer - ) -{ - const char *from = (char *)&deviceUniqueValue; - uint32_t uSize = sizeof(TEE_UUID) + 1; - uint32_t retVal = 0; - TEE_Result teeResult; - - // Check if we've initialized our unique platform value. - if (!initializedUniqueValue) { - teeResult = TEE_GetPropertyAsUUID(TEE_PROPSET_TEE_IMPLEMENTATION, - "gpd.tee.deviceID", - (TEE_UUID*)&deviceUniqueValue); - assert(teeResult == TEE_SUCCESS); - } - deviceUniqueValue[uSize-1] = '\0'; - - if(which == 0) // the authorities value - { - for(retVal = 0; - *from != 0 && retVal < bSize; - retVal++) - { - *b++ = *from++; - } - } - else - { - b = &b[((bSize < uSize) ? bSize : uSize) - 1]; - for(retVal = 0; - *from != 0 && retVal < bSize; - retVal++) - { - *b-- = *from++; - } - } - return retVal; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/include/Admin.h b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/include/Admin.h deleted file mode 100644 index ffda1aff4..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/include/Admin.h +++ /dev/null @@ -1,230 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//**Introduction -/* - This file contains the admin interfaces. -*/ - -#ifndef _ADMIN_H -#define _ADMIN_H - -//**Includes -#include -#include -#include "swap.h" -#include "Implementation.h" -#include "TpmSal.h" -#include "TpmError.h" - -// Parameter reference and types from ref impl headers -#ifndef UNREFERENCED_PARAMETER -#define UNREFERENCED_PARAMETER(a) do { (void)(a); } while (0) -#endif - -#define FAIL(errorCode) (TpmFail(__FUNCTION__, __LINE__, errorCode)) - -#if defined(EMPTY_ASSERT) -#define pAssert(a) ((void)0) -#else -#define pAssert(a) \ - do { \ - if (!(a)) { \ - EMSG("## ASSERT:" #a "##\n"); \ - FAIL(FATAL_ERROR_PARAMETER); \ - } \ - } while (0) -#endif - -#if defined(__GNUC__) -typedef unsigned char UCHAR; -typedef unsigned char * PUCHAR; -typedef void VOID; -typedef void * PVOID; -#endif - -// Admin space tacked on to NV, padded out to NV_BLOCK_SIZE alignment. -#define NV_TPM_STATE_SIZE 0x200 - -// Actual size of Admin space used. (See note in NVMem.c) -#define TPM_STATE_SIZE 0x10 - -// Select TPM types/defines for AdminPPI.c -typedef UINT16 TPM_ST; -#define TPM_ST_NO_SESSIONS (TPM_ST)(0x8001) - -typedef UINT32 TPM_RC; -#define TPM_RC_SUCCESS (TPM_RC)(0x000) -#define RC_VER1 (TPM_RC)(0x100) -#define TPM_RC_BAD_TAG (TPM_RC)(0x01E) -#define TPM_RC_FAILURE (TPM_RC)(RC_VER1+0x001) -#define TPM_RC_COMMAND_SIZE (TPM_RC)(RC_VER1+0x042) - -// Chip flags -typedef union { - UINT32 flags; - struct { - UINT32 Remanufacture : 1; // Ignored on OpTEE platforms - UINT32 TpmStatePresent : 1; // Set when sate present (startup STATE) - UINT32 Reserved : 30; - } fields; -} TPM_CHIP_STATE; - -// -// The current NV Chip state -// -extern TPM_CHIP_STATE g_chipFlags; - -// -// Simulated Physical Presence Interface (PPI) -// -#define FTPM_PPI_CMD_QUERY 0 -#define FTPM_PPI_CMD_VERSION 1 -#define FTPM_PPI_CMD_SUBMIT_OP_REQ 2 -#define FTPM_PPI_CMD_GET_PENDING_OP 3 -#define FTPM_PPI_CMD_GET_PLATFORM_ACTION 4 -#define FTPM_PPI_CMD_RETURN_OP_RESP 5 -#define FTPM_PPI_CMD_SUBMIT_USER_LANG 6 -#define FTPM_PPI_CMD_SUBMIT_OP_REQ2 7 -#define FTPM_PPI_CMD_GET_USER_CONF 8 - -#define FTPM_PPI_OP_NOP 0 -#define FTPM_PPI_OP_ENABLE 1 -#define FTPM_PPI_OP_DISABLE 2 -#define FTPM_PPI_OP_ACTIVATE 3 -#define FTPM_PPI_OP_DEACTIVATE 4 -#define FTPM_PPI_OP_CLEAR 5 -#define FTPM_PPI_OP_E_A 6 -#define FTPM_PPI_OP_D_D 7 -#define FTPM_PPI_OP_OWNERINSTALL_TRUE 8 -#define FTPM_PPI_OP_OWNERINSTALL_FALSE 9 -#define FTPM_PPI_OP_E_A_OI_TRUE 10 -#define FTPM_PPI_OP_OI_FALSE_D_D 11 -#define FTPM_PPI_OP_FIELD_UPGRADE 12 -#define FTPM_PPI_OP_OPERATOR_AUTH 13 -#define FTPM_PPI_OP_C_E_A 14 -#define FTPM_PPI_OP_SET_NO_PROV_FALSE 15 -#define FTPM_PPI_OP_SET_NO_PROV_TRUE 16 -#define FTPM_PPI_OP_SET_NO_CLEAR_FALSE 17 -#define FTPM_PPI_OP_SET_NO_CLEAR_TRUE 18 -#define FTPM_PPI_OP_SET_NO_MAINT_FALSE 19 -#define FTPM_PPI_OP_SET_NO_MAINT_TRUE 20 -#define FTPM_PPI_OP_E_A_C 21 -#define FTPM_PPI_OP_E_A_C_E_A 22 -#define FTPM_PPI_OP_RESERVED_FIRST 23 -#define FTPM_PPI_OP_RESERVED_LAST 127 -#define FTPM_PPI_OP_VENDOR_FIRST 128 - -#define FTPM_PPI_VERSION 0x00322E31 // "1.2" - -#define FTPM_PPI_OP_NOT_IMPLEMENTED 0xFFFFFFFF // Any Op other than E_A_C_E_A - -#pragma pack(1) -typedef struct { - UINT32 PendingPseudoOp; - UINT32 PseudoOpFromLastBoot; - UINT32 ReturnResponse; -} FTPM_PPI_STATE; -#pragma pack() - -// -// The types of TPM runtime state stored to NV -// -typedef enum { - NV_TPM_STATE_FLAGS = 0, - NV_TPM_STATE_PPI, - NV_TPM_STATE_LAST // A mark of the end of the TPM state -} NV_TPM_STATE; - -//***_admin__NvInitState() -// Initialize the NV admin state -void -_admin__NvInitState(); - -//***_admin__NvReadState() -// Read TPM state data from NV memory to RAM -void -_admin__NvReadState( - NV_TPM_STATE type, // IN: type of state data - void *buffer // OUT: data buffer - ); - -//***_admin__NvWriteState() -// Write TPM state data to NV memory -void -_admin__NvWriteState( - NV_TPM_STATE type, // IN: type of state data - void *buffer // IN: data buffer - ); - -// -// Save and restore runtime state -// - - -//***_admin__SaveChipFlags() -// Save the g_chipFlags runtime state -void -_admin__SaveChipFlags(); - -//***_admin__RestoreChipFlags() -// Restore the g_chipFlags runtime state -void -_admin__RestoreChipFlags(); - -//***_admin__SavePPIState() -// Save the s_PPIState runtime state -void -_admin__SavePPIState(); - -//***_admin__RestorePPIState() -// Restore the s_PPIState runtime state -void -_admin__RestorePPIState(); - -//***_admin__PPICommand() -// Returns 1 when PPI command has been consumed -// Returns 0 when it is not a properly formated PPI command, -// caller should pass through to TPM -// -int -_admin__PPICommand( - UINT32 CommandSize, - __in_ecount(CommandSize) UINT8 *CommandBuffer, - UINT32 *ResponseSize, - __deref_out_ecount(*ResponseSize) UINT8 **ResponseBuffer -); - -#endif diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/include/PlatformData.h b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/include/PlatformData.h deleted file mode 100644 index aa06c9a32..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/include/PlatformData.h +++ /dev/null @@ -1,137 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -// This file contains the instance data for the Platform module. It is collected -// in this file so that the state of the module is easier to manage. - -#ifndef _PLATFORM_DATA_H_ -#define _PLATFORM_DATA_H_ - - -#include "Implementation.h" - -// From Cancel.c -// Cancel flag. It is initialized as FALSE, which indicate the command is not -// being canceled -extern int s_isCanceled; - -#ifndef HARDWARE_CLOCK -typedef uint64_t clock64_t; -// This is the value returned the last time that the system clock was read. This -// is only relevant for a simulator or virtual TPM. -extern clock64_t s_realTimePrevious; - -// These values are used to try to synthesize a long lived version of clock(). -extern clock64_t s_lastSystemTime; -extern clock64_t s_lastReportedTime; - -// This is the rate adjusted value that is the equivalent of what would be read from -// a hardware register that produced rate adjusted time. -extern clock64_t s_tpmTime; -#endif // HARDWARE_CLOCK - -// This value indicates that the timer was reset -extern BOOL s_timerReset; -// This value indicates that the timer was stopped. It causes a clock discontinuity. -extern BOOL s_timerStopped; - -// CLOCK_NOMINAL is the number of hardware ticks per mS. A value of 300000 means -// that the nominal clock rate used to drive the hardware clock is 30 MHz. The -// adjustment rates are used to determine the conversion of the hardware ticks to -// internal hardware clock value. In practice, we would expect that there woudl be -// a hardware register will accumulated mS. It would be incremented by the output -// of a pre-scaler. The pre-scaler would divide the ticks from the clock by some -// value that would compensate for the difference between clock time and real time. -// The code in Clock does the emulation of this function. -#define CLOCK_NOMINAL 30000 -// A 1% change in rate is 300 counts -#define CLOCK_ADJUST_COARSE 300 -// A 0.1% change in rate is 30 counts -#define CLOCK_ADJUST_MEDIUM 30 -// A minimum change in rate is 1 count -#define CLOCK_ADJUST_FINE 1 -// The clock tolerance is +/-15% (4500 counts) -// Allow some guard band (16.7%) -#define CLOCK_ADJUST_LIMIT 5000 - -// This variable records the time when _plat__TimerReset is called. This mechanism -// allow us to subtract the time when TPM is power off from the total -// time reported by clock() function -extern uint64_t s_initClock; - -// This variable records the timer adjustment factor. -extern unsigned int s_adjustRate; - -// For LocalityPlat.c -// Locality of current command -extern unsigned char s_locality; - -// For NVMem.c -// Choose if the NV memory should be backed by RAM or by file. -// If this macro is defined, then a file is used as NV. If it is not defined, -// then RAM is used to back NV memory. Comment out to use RAM. - -#if (!defined VTPM) || ((VTPM != NO) && (VTPM != YES)) -# undef VTPM -# define VTPM YES // Default: Either YES or NO -#endif - -// For a simulation, use a file to back up the NV -#if (!defined FILE_BACKED_NV) || ((FILE_BACKED_NV != NO) && (FILE_BACKED_NV != YES)) -# undef FILE_BACKED_NV -# define FILE_BACKED_NV (VTPM && YES) // Default: Either YES or NO -#endif - -#if !SIMULATION -# undef FILE_BACKED_NV -# define FILE_BACKED_NV NO -#endif // SIMULATION - -extern unsigned char s_NV[NV_MEMORY_SIZE]; -extern BOOL s_NvIsAvailable; -extern BOOL s_NV_unrecoverable; -extern BOOL s_NV_recoverable; - - -// For PPPlat.c -// Physical presence. It is initialized to FALSE -extern BOOL s_physicalPresence; - -// From Power -extern BOOL s_powerLost; - -// For Entropy.c -extern uint32_t lastEntropy; - -#endif // _PLATFORM_DATA_H_ diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/include/Platform_fp.h b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/include/Platform_fp.h deleted file mode 100644 index 011a441b3..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/platform/include/Platform_fp.h +++ /dev/null @@ -1,432 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*(Auto-generated) - * Created by TpmPrototypes; Version 3.0 July 18, 2017 - * Date: Aug 7, 2018 Time: 03:39:35PM - */ - -#ifndef _PLATFORM_FP_H_ -#define _PLATFORM_FP_H_ - -//** From EPS.c - -LIB_EXPORT void -_plat__GetEPS(UINT16 Size, uint8_t *EndorsementSeed); - -//** From Cancel.c - -//***_plat__IsCanceled() -// Check if the cancel flag is set -// return type: BOOL -// TRUE(1) if cancel flag is set -// FALSE(0) if cancel flag is not set -LIB_EXPORT int -_plat__IsCanceled( - void - ); - -// Set cancel flag. -LIB_EXPORT void -_plat__SetCancel( - void - ); - -//***_plat__ClearCancel() -// Clear cancel flag -LIB_EXPORT void -_plat__ClearCancel( - void - ); - - -//** From Clock.c - -//***_plat__TimerReset() -// This function sets current system clock time as t0 for counting TPM time. -// This function is called at a power on event to reset the clock. When the clock -// is reset, the indication that the clock was stopped is also set. -LIB_EXPORT void -_plat__TimerReset( - void - ); - -//*** _plat__TimerRestart() -// This function should be called in order to simulate the restart of the timer -// should it be stopped while power is still applied. -LIB_EXPORT void -_plat__TimerRestart( - void - ); - -//*** _plat__RealTime() -// This is another, probably futile, attempt to define a portable function -// that will return a 64-bit clock value that has mSec resolution. -uint64_t -_plat__RealTime( - void -); - -//***_plat__TimerRead() -// This function provides access to the tick timer of the platform. The TPM code -// uses this value to drive the TPM Clock. -// -// The tick timer is supposed to run when power is applied to the device. This timer -// should not be reset by time events including _TPM_Init. It should only be reset -// when TPM power is re-applied. -// -// If the TPM is run in a protected environment, that environment may provide the -// tick time to the TPM as long as the time provided by the environment is not -// allowed to go backwards. If the time provided by the system can go backwards -// during a power discontinuity, then the _plat__Signal_PowerOn should call -// _plat__TimerReset(). -LIB_EXPORT uint64_t -_plat__TimerRead( - void - ); - -//*** _plat__TimerWasReset() -// This function is used to interrogate the flag indicating if the tick timer has -// been reset. -// -// If the resetFlag parameter is SET, then the flag will be CLEAR before the -// function returns. -LIB_EXPORT BOOL -_plat__TimerWasReset( - void - ); - -//*** _plat__TimerWasStopped() -// This function is used to interrogate the flag indicating if the tick timer has -// been stopped. If so, this is typically a reason to roll the nonce. -// -// This function will CLEAR the s_timerStopped flag before returning. This provides -// functionality that is similar to status register that is cleared when read. This -// is the model used here because it is the one that has the most impact on the TPM -// code as the flag can only be accessed by one entity in the TPM. Any other -// implementation of the hardware can be made to look like a read-once register. -LIB_EXPORT BOOL -_plat__TimerWasStopped( - void - ); - -//***_plat__ClockAdjustRate() -// Adjust the clock rate -LIB_EXPORT void -_plat__ClockAdjustRate( - int adjust // IN: the adjust number. It could be positive - // or negative - ); - - -//** From Entropy.c - -//** _plat__GetEntropy() -// This function is used to get available hardware entropy. In a hardware -// implementation of this function, there would be no call to the system -// to get entropy. -// return type: int32_t -// < 0 hardware failure of the entropy generator, this is sticky -// >= 0 the returned amount of entropy (bytes) -// -LIB_EXPORT int32_t -_plat__GetEntropy( - unsigned char *entropy, // output buffer - uint32_t amount // amount requested - ); - - -//** From LocalityPlat.c - -//***_plat__LocalityGet() -// Get the most recent command locality in locality value form. -// This is an integer value for locality and not a locality structure -// The locality can be 0-4 or 32-255. 5-31 is not allowed. -LIB_EXPORT unsigned char -_plat__LocalityGet( - void - ); - -//***_plat__LocalitySet() -// Set the most recent command locality in locality value form -LIB_EXPORT void -_plat__LocalitySet( - unsigned char locality - ); - - -//** From NVMem.c - -//*** _plat__NvErrors() -// This function is used by the simulator to set the error flags in the NV -// subsystem to simulate an error in the NV loading process -LIB_EXPORT void -_plat__NvErrors( - int recoverable, - int unrecoverable - ); - -//***_plat__NVEnable() -// Enable NV memory. -// -// This version just pulls in data from a file. In a real TPM, with NV on chip, -// this function would verify the integrity of the saved context. If the NV -// memory was not on chip but was in something like RPMB, the NV state would be -// read in, decrypted and integrity checked. -// -// The recovery from an integrity failure depends on where the error occurred. It -// it was in the state that is discarded by TPM Reset, then the error is -// recoverable if the TPM is reset. Otherwise, the TPM must go into failure mode. -// return type: int -// 0 if success -// > 0 if receive recoverable error -// <0 if unrecoverable error -LIB_EXPORT int -_plat__NVEnable( - void *platParameter // IN: platform specific parameters - ); - -//***_plat__NVDisable() -// Disable NV memory -LIB_EXPORT void -_plat__NVDisable( - void - ); - -//***_plat__IsNvAvailable() -// Check if NV is available -// return type: int -// 0 NV is available -// 1 NV is not available due to write failure -// 2 NV is not available due to rate limit -LIB_EXPORT int -_plat__IsNvAvailable( - void - ); - -//***_plat__NvMemoryRead() -// Function: Read a chunk of NV memory -LIB_EXPORT void -_plat__NvMemoryRead( - unsigned int startOffset, // IN: read start - unsigned int size, // IN: size of bytes to read - void *data // OUT: data buffer - ); - -//*** _plat__NvIsDifferent() -// This function checks to see if the NV is different from the test value. This is -// so that NV will not be written if it has not changed. -// return value: int -// TRUE(1) the NV location is different from the test value -// FALSE(0) the NV location is the same as the test value -LIB_EXPORT int -_plat__NvIsDifferent( - unsigned int startOffset, // IN: read start - unsigned int size, // IN: size of bytes to read - void *data // IN: data buffer - ); - -//***_plat__NvMemoryWrite() -// This function is used to update NV memory. The "write" is to a memory copy of -// NV. At the end of the current command, any changes are written to -// the actual NV memory. -// NOTE: A useful optimization would be for this code to compare the current -// contents of NV with the local copy and note the blocks that have changed. Then -// only write those blocks when _plat__NvCommit() is called. -LIB_EXPORT void -_plat__NvMemoryWrite( - unsigned int startOffset, // IN: write start - unsigned int size, // IN: size of bytes to write - void *data // OUT: data buffer - ); - -//***_plat__NvMemoryClear() -// Function is used to set a range of NV memory bytes to an implementation-dependent -// value. The value represents the erase state of the memory. -LIB_EXPORT void -_plat__NvMemoryClear( - unsigned int start, // IN: clear start - unsigned int size // IN: number of bytes to clear - ); - -//***_plat__NvMemoryMove() -// Function: Move a chunk of NV memory from source to destination -// This function should ensure that if there overlap, the original data is -// copied before it is written -LIB_EXPORT void -_plat__NvMemoryMove( - unsigned int sourceOffset, // IN: source offset - unsigned int destOffset, // IN: destination offset - unsigned int size // IN: size of data being moved - ); - -//***_plat__NvCommit() -// This function writes the local copy of NV to NV for permanent store. It will write -// NV_MEMORY_SIZE bytes to NV. If a file is use, the entire file is written. -// return type: int -// 0 NV write success -// non-0 NV write fail -LIB_EXPORT int -_plat__NvCommit( - void - ); - -//***_plat__SetNvAvail() -// Set the current NV state to available. This function is for testing purpose -// only. It is not part of the platform NV logic -LIB_EXPORT void -_plat__SetNvAvail( - void - ); - -//***_plat__ClearNvAvail() -// Set the current NV state to unavailable. This function is for testing purpose -// only. It is not part of the platform NV logic -LIB_EXPORT void -_plat__ClearNvAvail( - void - ); - - -//** From PowerPlat.c - -//***_plat__Signal_PowerOn() -// Signal platform power on -LIB_EXPORT int -_plat__Signal_PowerOn( - void - ); - -//*** _plat__WasPowerLost() -// Test whether power was lost before a _TPM_Init. -// -// This function will clear the "hardware" indication of power loss before return. -// This means that there can only be one spot in the TPM code where this value -// gets read. This method is used here as it is the most difficult to manage in the -// TPM code and, if the hardware actually works this way, it is hard to make it -// look like anything else. So, the burden is placed on the TPM code rather than the -// platform code -// return type: int -// TRUE(1) power was lost -// FALSE(0) power was not lost -LIB_EXPORT int -_plat__WasPowerLost( - void - ); - -//*** _plat_Signal_Reset() -// This a TPM reset without a power loss. -LIB_EXPORT int -_plat__Signal_Reset( - void - ); - -//***_plat__Signal_PowerOff() -// Signal platform power off -LIB_EXPORT void -_plat__Signal_PowerOff( - void - ); - - -//** From PPPlat.c - -//***_plat__PhysicalPresenceAsserted() -// Check if physical presence is signaled -// return type: int -// TRUE(1) if physical presence is signaled -// FALSE(0) if physical presence is not signaled -LIB_EXPORT int -_plat__PhysicalPresenceAsserted( - void - ); - -//***_plat__Signal_PhysicalPresenceOn() -// Signal physical presence on -LIB_EXPORT void -_plat__Signal_PhysicalPresenceOn( - void - ); - -//***_plat__Signal_PhysicalPresenceOff() -// Signal physical presence off -LIB_EXPORT void -_plat__Signal_PhysicalPresenceOff( - void - ); - - -//** From RunCommand.c - -//***_plat__RunCommand() -// This version of RunCommand will set up a jum_buf and call ExecuteCommand(). If -// the command executes without failing, it will return and RunCommand will return. -// If there is a failure in the command, then _plat__Fail() is called and it will -// longjump back to RunCommand which will call ExecuteCommand again. However, this -// time, the TPM will be in failure mode so ExecuteCommand will simply build -// a failure response and return. -LIB_EXPORT void -_plat__RunCommand( - uint32_t requestSize, // IN: command buffer size - unsigned char *request, // IN: command buffer - uint32_t *responseSize, // IN/OUT: response buffer size - unsigned char **response // IN/OUT: response buffer - ); - -//***_plat__Fail() -// This is the platform depended failure exit for the TPM. -LIB_EXPORT NORETURN void -_plat__Fail( - void - ); - - -//** From Unique.c - -//** _plat__GetUnique() -// This function is used to access the platform-specific unique value. -// This function places the unique value in the provided buffer ('b') -// and returns the number of bytes transferred. The function will not -// copy more data than 'bSize'. -// NOTE: If a platform unique value has unequal distribution of uniqueness -// and 'bSize' is smaller than the size of the unique value, the 'bSize' -// portion with the most uniqueness should be returned. -LIB_EXPORT uint32_t -_plat__GetUnique( - uint32_t which, // authorities (0) or details - uint32_t bSize, // size of the buffer - unsigned char *b // output buffer - ); - -#endif // _PLATFORM_FP_H_ diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/RuntimeSupport.c b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/RuntimeSupport.c deleted file mode 100644 index a2d1cfa4f..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/RuntimeSupport.c +++ /dev/null @@ -1,84 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -/** - * Implementation of tolower() commonly found in ctype.h - * Returns an ASCII character, changing to lowercase if the character is - * in the range 'A'-'Z'. - */ - -int tolower (int c) -{ - if(c >= 'A' && c <= 'Z') - { - c -= ('A' - 'a'); - } - return c; -} - -int toupper (int c) -{ - if(c >= 'a' && c <= 'z') - { - c += ('A' - 'a'); - } - return c; -} - -int strncasecmp(const char *str1, const char *str2, size_t n) -{ - size_t i = 0; - for(i = 0; i < n && str1[i] && str2[i]; i++) - { - char delta = tolower(str1[i]) - tolower(str2[i]); - if (delta != 0) - { - return delta; - } - } - return 0; -} - -#ifdef CUSTOM_RAND_GENERATE_BLOCK -#include -int wolfRand(unsigned char* output, unsigned int sz) -{ - TEE_GenerateRandom((void *)output, (uint32_t)sz); - - return 0; -} -#endif \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/Implementation.h b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/Implementation.h deleted file mode 100644 index 58861fde4..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/Implementation.h +++ /dev/null @@ -1,1179 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _IMPLEMENTATION_H_ -#define _IMPLEMENTATION_H_ - -#include "RuntimeSupport.h" - -#include -#include -#include - -#undef TRUE -#undef FALSE - -#undef MAX -#define MAX(a, b) ((a) > (b) ? (a) : (b)) - -#undef MIN -#define MIN(a, b) ((a) < (b) ? (a) : (b)) - -// Table 2:3 - Definition of Base Types -// Base Types are in BaseTypes.h - -// Table 2:4 - Defines for Logic Values -#define TRUE 1 -#define FALSE 0 -#define YES 1 -#define NO 0 -#define SET 1 -#define CLEAR 0 - -// Table 0:1 - Defines for Processor Values -#ifndef BIG_ENDIAN_TPM -#define BIG_ENDIAN_TPM NO -#endif // BIG_ENDIAN_TPM -#define LITTLE_ENDIAN_TPM !BIG_ENDIAN_TPM -#ifndef MOST_SIGNIFICANT_BIT_0 -#define MOST_SIGNIFICANT_BIT_0 NO -#endif // MOST_SIGNIFICANT_BIT_0 -#define LEAST_SIGNIFICANT_BIT_0 !MOST_SIGNIFICANT_BIT_0 -#ifndef AUTO_ALIGN -#define AUTO_ALIGN NO -#endif // AUTO_ALIGN - -// Table 0:3 - Defines for Key Size Constants -#define RSA_KEY_SIZES_BITS {1024,2048} -#define RSA_KEY_SIZE_BITS_1024 RSA_ALLOWED_KEY_SIZE_1024 -#define RSA_KEY_SIZE_BITS_2048 RSA_ALLOWED_KEY_SIZE_2048 -#define MAX_RSA_KEY_BITS 2048 -#define MAX_RSA_KEY_BYTES 256 - -#define TDES_KEY_SIZES_BITS {128,192} -#define TDES_KEY_SIZE_BITS_128 TDES_ALLOWED_KEY_SIZE_128 -#define TDES_KEY_SIZE_BITS_192 TDES_ALLOWED_KEY_SIZE_192 -#define MAX_TDES_KEY_BITS 192 -#define MAX_TDES_KEY_BYTES 24 -#define MAX_TDES_BLOCK_SIZE_BYTES \ - MAX(TDES_128_BLOCK_SIZE_BYTES, MAX(TDES_192_BLOCK_SIZE_BYTES, 0)) - -#define AES_KEY_SIZES_BITS {128,256} -#define AES_KEY_SIZE_BITS_128 AES_ALLOWED_KEY_SIZE_128 -#define AES_KEY_SIZE_BITS_256 AES_ALLOWED_KEY_SIZE_256 -#define MAX_AES_KEY_BITS 256 -#define MAX_AES_KEY_BYTES 32 -#define MAX_AES_BLOCK_SIZE_BYTES \ - MAX(AES_128_BLOCK_SIZE_BYTES, MAX(AES_256_BLOCK_SIZE_BYTES, 0)) - -#define SM4_KEY_SIZES_BITS {128} -#define SM4_KEY_SIZE_BITS_128 SM4_ALLOWED_KEY_SIZE_128 -#define MAX_SM4_KEY_BITS 128 -#define MAX_SM4_KEY_BYTES 16 -#define MAX_SM4_BLOCK_SIZE_BYTES MAX(SM4_128_BLOCK_SIZE_BYTES, 0) - -#define CAMELLIA_KEY_SIZES_BITS {128} -#define CAMELLIA_KEY_SIZE_BITS_128 CAMELLIA_ALLOWED_KEY_SIZE_128 -#define MAX_CAMELLIA_KEY_BITS 128 -#define MAX_CAMELLIA_KEY_BYTES 16 -#define MAX_CAMELLIA_BLOCK_SIZE_BYTES MAX(CAMELLIA_128_BLOCK_SIZE_BYTES, 0) - -// Table 0:4 - Defines for Implemented Curves -#define ECC_NIST_P192 NO -#define ECC_NIST_P224 NO -#define ECC_NIST_P256 YES -#define ECC_NIST_P384 YES -#define ECC_NIST_P521 YES -#ifdef USE_WOLFCRYPT -#define ECC_BN_P256 NO -#define ECC_SM2_P256 NO -#else -#define ECC_BN_P256 YES -#define ECC_SM2_P256 YES -#endif -#define ECC_BN_P638 NO -#define ECC_CURVES \ - {TPM_ECC_BN_P256, TPM_ECC_BN_P638, TPM_ECC_NIST_P192, \ - TPM_ECC_NIST_P224, TPM_ECC_NIST_P256, TPM_ECC_NIST_P384, \ - TPM_ECC_NIST_P521, TPM_ECC_SM2_P256} -#define ECC_CURVE_COUNT \ - (ECC_BN_P256 + ECC_BN_P638 + ECC_NIST_P192 + ECC_NIST_P224 + \ - ECC_NIST_P256 + ECC_NIST_P384 + ECC_NIST_P521 + ECC_SM2_P256) -#define MAX_ECC_KEY_BITS \ - MAX(ECC_BN_P256 * 256, MAX(ECC_BN_P638 * 638, \ - MAX(ECC_NIST_P192 * 192, MAX(ECC_NIST_P224 * 224, \ - MAX(ECC_NIST_P256 * 256, MAX(ECC_NIST_P384 * 384, \ - MAX(ECC_NIST_P521 * 521, MAX(ECC_SM2_P256 * 256, \ - 0)))))))) -#define MAX_ECC_KEY_BYTES BITS_TO_BYTES(MAX_ECC_KEY_BITS) - -// Table 0:6 - Defines for PLATFORM Values -#define PLATFORM_FAMILY TPM_SPEC_FAMILY -#define PLATFORM_LEVEL TPM_SPEC_LEVEL -#define PLATFORM_VERSION TPM_SPEC_VERSION -#define PLATFORM_YEAR TPM_SPEC_YEAR -#define PLATFORM_DAY_OF_YEAR TPM_SPEC_DAY_OF_YEAR - -// Table 0:7 - Defines for Implementation Values -#define FIELD_UPGRADE_IMPLEMENTED NO -#define RADIX_BITS 32 -#define HASH_ALIGNMENT 4 -#define SYMMETRIC_ALIGNMENT 4 -#ifdef USE_WOLFCRYPT -#define HASH_LIB WOLF -#define SYM_LIB WOLF -#define MATH_LIB WOLF -#else -#define HASH_LIB OSSL -#define SYM_LIB OSSL -#define MATH_LIB OSSL -#endif -#define BSIZE UINT16 -#define IMPLEMENTATION_PCR 24 -#define PLATFORM_PCR 24 -#define DRTM_PCR 17 -#define HCRTM_PCR 0 -#define NUM_LOCALITIES 5 -#define MAX_HANDLE_NUM 3 -#define MAX_ACTIVE_SESSIONS 64 -#define CONTEXT_SLOT UINT16 -#define CONTEXT_COUNTER UINT64 -#define MAX_LOADED_SESSIONS 3 -#define MAX_SESSION_NUM 3 -#define MAX_LOADED_OBJECTS 3 -#define MIN_EVICT_OBJECTS 2 -#define NUM_POLICY_PCR_GROUP 1 -#define NUM_AUTHVALUE_PCR_GROUP 1 -#define MAX_CONTEXT_SIZE 2474 -#define MAX_DIGEST_BUFFER 1024 -#define MAX_NV_INDEX_SIZE 2048 -#define MAX_NV_BUFFER_SIZE 1024 -#define MAX_CAP_BUFFER 1024 -#define NV_MEMORY_SIZE 16384 -#define MIN_COUNTER_INDICES 8 -#define NUM_STATIC_PCR 16 -#define MAX_ALG_LIST_SIZE 64 -#define PRIMARY_SEED_SIZE 32 -#define CONTEXT_ENCRYPT_ALGORITHM AES -#define NV_CLOCK_UPDATE_INTERVAL 12 -#define NUM_POLICY_PCR 1 -#define MAX_COMMAND_SIZE 4096 -#define MAX_RESPONSE_SIZE 4096 -#define ORDERLY_BITS 8 -#define MAX_SYM_DATA 128 -#define MAX_RNG_ENTROPY_SIZE 64 -#define RAM_INDEX_SPACE 512 -#define RSA_DEFAULT_PUBLIC_EXPONENT 0x00010001 -#define ENABLE_PCR_NO_INCREMENT YES -#define CRT_FORMAT_RSA YES -#define VENDOR_COMMAND_COUNT 0 -#define MAX_VENDOR_BUFFER_SIZE 1024 -#define TPM_MAX_DERIVATION_BITS 8192 - -// Table 0:2 - Defines for Implemented Algorithms -#define ALG_AES ALG_YES -#define ALG_CAMELLIA ALG_NO /* Not specified by vendor */ -#define ALG_CBC ALG_YES -#define ALG_CFB ALG_YES -#define ALG_CMAC ALG_YES -#define ALG_CTR ALG_YES -#define ALG_ECB ALG_YES -#define ALG_ECC ALG_YES -#define ALG_ECDAA (ALG_YES && ALG_ECC) -#define ALG_ECDH (ALG_YES && ALG_ECC) -#define ALG_ECDSA (ALG_YES && ALG_ECC) -#define ALG_ECMQV (ALG_NO && ALG_ECC) -#define ALG_ECSCHNORR (ALG_YES && ALG_ECC) -#define ALG_HMAC ALG_YES -#define ALG_KDF1_SP800_108 ALG_YES -#define ALG_KDF1_SP800_56A (ALG_YES && ALG_ECC) -#define ALG_KDF2 ALG_NO -#define ALG_KEYEDHASH ALG_YES -#define ALG_MGF1 ALG_YES -#define ALG_OAEP (ALG_YES && ALG_RSA) -#define ALG_OFB ALG_YES -#define ALG_RSA ALG_YES -#define ALG_RSAES (ALG_YES && ALG_RSA) -#define ALG_RSAPSS (ALG_YES && ALG_RSA) -#define ALG_RSASSA (ALG_YES && ALG_RSA) -#define ALG_SHA ALG_NO /* Not specified by vendor */ -#define ALG_SHA1 ALG_YES -#define ALG_SHA256 ALG_YES -#define ALG_SHA384 ALG_YES -#define ALG_SHA512 ALG_YES -#define ALG_SM2 (ALG_NO && ALG_ECC) -#define ALG_SM3_256 ALG_NO -#define ALG_SM4 ALG_NO -#define ALG_SYMCIPHER ALG_YES -#define ALG_TDES ALG_NO -#define ALG_XOR ALG_YES - -// Table 1:2 - Definition of TPM_ALG_ID Constants -typedef UINT16 TPM_ALG_ID; -#define ALG_ERROR_VALUE 0x0000 -#define TPM_ALG_ERROR (TPM_ALG_ID)(ALG_ERROR_VALUE) -#define ALG_RSA_VALUE 0x0001 -#if ALG_RSA -#define TPM_ALG_RSA (TPM_ALG_ID)(ALG_RSA_VALUE) -#endif // ALG_RSA -#define ALG_TDES_VALUE 0x0003 -#if ALG_TDES -#define TPM_ALG_TDES (TPM_ALG_ID)(ALG_TDES_VALUE) -#endif // ALG_TDES -#define ALG_SHA_VALUE 0x0004 -#if ALG_SHA -#define TPM_ALG_SHA (TPM_ALG_ID)(ALG_SHA_VALUE) -#endif // ALG_SHA -#define ALG_SHA1_VALUE 0x0004 -#if ALG_SHA1 -#define TPM_ALG_SHA1 (TPM_ALG_ID)(ALG_SHA1_VALUE) -#endif // ALG_SHA1 -#define ALG_HMAC_VALUE 0x0005 -#if ALG_HMAC -#define TPM_ALG_HMAC (TPM_ALG_ID)(ALG_HMAC_VALUE) -#endif // ALG_HMAC -#define ALG_AES_VALUE 0x0006 -#if ALG_AES -#define TPM_ALG_AES (TPM_ALG_ID)(ALG_AES_VALUE) -#endif // ALG_AES -#define ALG_MGF1_VALUE 0x0007 -#if ALG_MGF1 -#define TPM_ALG_MGF1 (TPM_ALG_ID)(ALG_MGF1_VALUE) -#endif // ALG_MGF1 -#define ALG_KEYEDHASH_VALUE 0x0008 -#if ALG_KEYEDHASH -#define TPM_ALG_KEYEDHASH (TPM_ALG_ID)(ALG_KEYEDHASH_VALUE) -#endif // ALG_KEYEDHASH -#define ALG_XOR_VALUE 0x000A -#if ALG_XOR -#define TPM_ALG_XOR (TPM_ALG_ID)(ALG_XOR_VALUE) -#endif // ALG_XOR -#define ALG_SHA256_VALUE 0x000B -#if ALG_SHA256 -#define TPM_ALG_SHA256 (TPM_ALG_ID)(ALG_SHA256_VALUE) -#endif // ALG_SHA256 -#define ALG_SHA384_VALUE 0x000C -#if ALG_SHA384 -#define TPM_ALG_SHA384 (TPM_ALG_ID)(ALG_SHA384_VALUE) -#endif // ALG_SHA384 -#define ALG_SHA512_VALUE 0x000D -#if ALG_SHA512 -#define TPM_ALG_SHA512 (TPM_ALG_ID)(ALG_SHA512_VALUE) -#endif // ALG_SHA512 -#define ALG_NULL_VALUE 0x0010 -#define TPM_ALG_NULL (TPM_ALG_ID)(ALG_NULL_VALUE) -#define ALG_SM3_256_VALUE 0x0012 -#if ALG_SM3_256 -#define TPM_ALG_SM3_256 (TPM_ALG_ID)(ALG_SM3_256_VALUE) -#endif // ALG_SM3_256 -#define ALG_SM4_VALUE 0x0013 -#if ALG_SM4 -#define TPM_ALG_SM4 (TPM_ALG_ID)(ALG_SM4_VALUE) -#endif // ALG_SM4 -#define ALG_RSASSA_VALUE 0x0014 -#if ALG_RSASSA -#define TPM_ALG_RSASSA (TPM_ALG_ID)(ALG_RSASSA_VALUE) -#endif // ALG_RSASSA -#define ALG_RSAES_VALUE 0x0015 -#if ALG_RSAES -#define TPM_ALG_RSAES (TPM_ALG_ID)(ALG_RSAES_VALUE) -#endif // ALG_RSAES -#define ALG_RSAPSS_VALUE 0x0016 -#if ALG_RSAPSS -#define TPM_ALG_RSAPSS (TPM_ALG_ID)(ALG_RSAPSS_VALUE) -#endif // ALG_RSAPSS -#define ALG_OAEP_VALUE 0x0017 -#if ALG_OAEP -#define TPM_ALG_OAEP (TPM_ALG_ID)(ALG_OAEP_VALUE) -#endif // ALG_OAEP -#define ALG_ECDSA_VALUE 0x0018 -#if ALG_ECDSA -#define TPM_ALG_ECDSA (TPM_ALG_ID)(ALG_ECDSA_VALUE) -#endif // ALG_ECDSA -#define ALG_ECDH_VALUE 0x0019 -#if ALG_ECDH -#define TPM_ALG_ECDH (TPM_ALG_ID)(ALG_ECDH_VALUE) -#endif // ALG_ECDH -#define ALG_ECDAA_VALUE 0x001A -#if ALG_ECDAA -#define TPM_ALG_ECDAA (TPM_ALG_ID)(ALG_ECDAA_VALUE) -#endif // ALG_ECDAA -#define ALG_SM2_VALUE 0x001B -#if ALG_SM2 -#define TPM_ALG_SM2 (TPM_ALG_ID)(ALG_SM2_VALUE) -#endif // ALG_SM2 -#define ALG_ECSCHNORR_VALUE 0x001C -#if ALG_ECSCHNORR -#define TPM_ALG_ECSCHNORR (TPM_ALG_ID)(ALG_ECSCHNORR_VALUE) -#endif // ALG_ECSCHNORR -#define ALG_ECMQV_VALUE 0x001D -#if ALG_ECMQV -#define TPM_ALG_ECMQV (TPM_ALG_ID)(ALG_ECMQV_VALUE) -#endif // ALG_ECMQV -#define ALG_KDF1_SP800_56A_VALUE 0x0020 -#if ALG_KDF1_SP800_56A -#define TPM_ALG_KDF1_SP800_56A (TPM_ALG_ID)(ALG_KDF1_SP800_56A_VALUE) -#endif // ALG_KDF1_SP800_56A -#define ALG_KDF2_VALUE 0x0021 -#if ALG_KDF2 -#define TPM_ALG_KDF2 (TPM_ALG_ID)(ALG_KDF2_VALUE) -#endif // ALG_KDF2 -#define ALG_KDF1_SP800_108_VALUE 0x0022 -#if ALG_KDF1_SP800_108 -#define TPM_ALG_KDF1_SP800_108 (TPM_ALG_ID)(ALG_KDF1_SP800_108_VALUE) -#endif // ALG_KDF1_SP800_108 -#define ALG_ECC_VALUE 0x0023 -#if ALG_ECC -#define TPM_ALG_ECC (TPM_ALG_ID)(ALG_ECC_VALUE) -#endif // ALG_ECC -#define ALG_SYMCIPHER_VALUE 0x0025 -#if ALG_SYMCIPHER -#define TPM_ALG_SYMCIPHER (TPM_ALG_ID)(ALG_SYMCIPHER_VALUE) -#endif // ALG_SYMCIPHER -#define ALG_CAMELLIA_VALUE 0x0026 -#if ALG_CAMELLIA -#define TPM_ALG_CAMELLIA (TPM_ALG_ID)(ALG_CAMELLIA_VALUE) -#endif // ALG_CAMELLIA -#define ALG_CMAC_VALUE 0x003F -#if ALG_CMAC -#define TPM_ALG_CMAC (TPM_ALG_ID)(ALG_CMAC_VALUE) -#endif // ALG_CMAC -#define ALG_CTR_VALUE 0x0040 -#if ALG_CTR -#define TPM_ALG_CTR (TPM_ALG_ID)(ALG_CTR_VALUE) -#endif // ALG_CTR -#define ALG_OFB_VALUE 0x0041 -#if ALG_OFB -#define TPM_ALG_OFB (TPM_ALG_ID)(ALG_OFB_VALUE) -#endif // ALG_OFB -#define ALG_CBC_VALUE 0x0042 -#if ALG_CBC -#define TPM_ALG_CBC (TPM_ALG_ID)(ALG_CBC_VALUE) -#endif // ALG_CBC -#define ALG_CFB_VALUE 0x0043 -#if ALG_CFB -#define TPM_ALG_CFB (TPM_ALG_ID)(ALG_CFB_VALUE) -#endif // ALG_CFB -#define ALG_ECB_VALUE 0x0044 -#if ALG_ECB -#define TPM_ALG_ECB (TPM_ALG_ID)(ALG_ECB_VALUE) -#endif // ALG_ECB -// Values derived from Table 1:2 -#define ALG_FIRST_VALUE 0x0001 -#define TPM_ALG_FIRST (TPM_ALG_ID)(ALG_FIRST_VALUE) -#define ALG_LAST_VALUE 0x0044 -#define TPM_ALG_LAST (TPM_ALG_ID)(ALG_LAST_VALUE) - -// Table 1:3 - Definition of TPM_ECC_CURVE Constants -typedef UINT16 TPM_ECC_CURVE; -#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000) -#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001) -#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002) -#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003) -#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004) -#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005) -#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010) -#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011) -#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020) - -// Table 1:12 - Defines for SHA1 Hash Values -#define SHA1_DIGEST_SIZE 20 -#define SHA1_BLOCK_SIZE 64 -#define SHA1_DER_SIZE 15 -#define SHA1_DER \ - 0x30, 0x21, 0x30, 0x09, 0x06, 0x05, 0x2B, 0x0E, \ - 0x03, 0x02, 0x1A, 0x05, 0x00, 0x04, 0x14 - -// Table 1:13 - Defines for SHA256 Hash Values -#define SHA256_DIGEST_SIZE 32 -#define SHA256_BLOCK_SIZE 64 -#define SHA256_DER_SIZE 19 -#define SHA256_DER \ - 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, \ - 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, \ - 0x00, 0x04, 0x20 - -// Table 1:14 - Defines for SHA384 Hash Values -#define SHA384_DIGEST_SIZE 48 -#define SHA384_BLOCK_SIZE 128 -#define SHA384_DER_SIZE 19 -#define SHA384_DER \ - 0x30, 0x41, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, \ - 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x02, 0x05, \ - 0x00, 0x04, 0x30 - -// Table 1:15 - Defines for SHA512 Hash Values -#define SHA512_DIGEST_SIZE 64 -#define SHA512_BLOCK_SIZE 128 -#define SHA512_DER_SIZE 19 -#define SHA512_DER \ - 0x30, 0x51, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, \ - 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x03, 0x05, \ - 0x00, 0x04, 0x40 - -// Table 1:16 - Defines for SM3_256 Hash Values -#define SM3_256_DIGEST_SIZE 32 -#define SM3_256_BLOCK_SIZE 64 -#define SM3_256_DER_SIZE 18 -#define SM3_256_DER \ - 0x30, 0x30, 0x30, 0x0C, 0x06, 0x08, 0x2A, 0x81, \ - 0x1C, 0x81, 0x45, 0x01, 0x83, 0x11, 0x05, 0x00, \ - 0x04, 0x20 - -// Table 1:17 - Defines for AES Symmetric Cipher Algorithm Constants -#define AES_ALLOWED_KEY_SIZE_128 YES -#define AES_ALLOWED_KEY_SIZE_192 YES -#define AES_ALLOWED_KEY_SIZE_256 YES -#define AES_128_BLOCK_SIZE_BYTES 16 -#define AES_192_BLOCK_SIZE_BYTES 16 -#define AES_256_BLOCK_SIZE_BYTES 16 - -// Table 1:18 - Defines for SM4 Symmetric Cipher Algorithm Constants -#define SM4_ALLOWED_KEY_SIZE_128 YES -#define SM4_128_BLOCK_SIZE_BYTES 16 - -// Table 1:19 - Defines for CAMELLIA Symmetric Cipher Algorithm Constants -#define CAMELLIA_ALLOWED_KEY_SIZE_128 YES -#define CAMELLIA_ALLOWED_KEY_SIZE_192 YES -#define CAMELLIA_ALLOWED_KEY_SIZE_256 YES -#define CAMELLIA_128_BLOCK_SIZE_BYTES 16 -#define CAMELLIA_192_BLOCK_SIZE_BYTES 16 -#define CAMELLIA_256_BLOCK_SIZE_BYTES 16 - -// Table 1:17 - Defines for TDES Symmetric Cipher Algorithm Constants -#define TDES_ALLOWED_KEY_SIZE_128 YES -#define TDES_ALLOWED_KEY_SIZE_192 YES -#define TDES_128_BLOCK_SIZE_BYTES 8 -#define TDES_192_BLOCK_SIZE_BYTES 8 - -// Table 0:5 - Defines for Implemented Commands -#define CC_AC_GetCapability CC_YES -#define CC_AC_Send CC_YES -#define CC_ActivateCredential CC_YES -#define CC_Certify CC_YES -#define CC_CertifyCreation CC_YES -#define CC_ChangeEPS CC_YES -#define CC_ChangePPS CC_YES -#define CC_Clear CC_YES -#define CC_ClearControl CC_YES -#define CC_ClockRateAdjust CC_YES -#define CC_ClockSet CC_YES -#define CC_Commit (CC_YES && ALG_ECC) -#define CC_ContextLoad CC_YES -#define CC_ContextSave CC_YES -#define CC_Create CC_YES -#define CC_CreateLoaded CC_YES -#define CC_CreatePrimary CC_YES -#define CC_DictionaryAttackLockReset CC_YES -#define CC_DictionaryAttackParameters CC_YES -#define CC_Duplicate CC_YES -#define CC_ECC_Parameters (CC_YES && ALG_ECC) -#define CC_ECDH_KeyGen (CC_YES && ALG_ECC) -#define CC_ECDH_ZGen (CC_YES && ALG_ECC) -#define CC_EC_Ephemeral (CC_YES && ALG_ECC) -#define CC_EncryptDecrypt CC_YES -#define CC_EncryptDecrypt2 CC_YES -#define CC_EventSequenceComplete CC_YES -#define CC_EvictControl CC_YES -#define CC_FieldUpgradeData CC_NO -#define CC_FieldUpgradeStart CC_NO -#define CC_FirmwareRead CC_NO -#define CC_FlushContext CC_YES -#define CC_GetCapability CC_YES -#define CC_GetCommandAuditDigest CC_YES -#define CC_GetRandom CC_YES -#define CC_GetSessionAuditDigest CC_YES -#define CC_GetTestResult CC_YES -#define CC_GetTime CC_YES -#define CC_HMAC (CC_YES && !ALG_CMAC) -#define CC_HMAC_Start (CC_YES && !ALG_CMAC) -#define CC_Hash CC_YES -#define CC_HashSequenceStart CC_YES -#define CC_HierarchyChangeAuth CC_YES -#define CC_HierarchyControl CC_YES -#define CC_Import CC_YES -#define CC_IncrementalSelfTest CC_YES -#define CC_Load CC_YES -#define CC_LoadExternal CC_YES -#define CC_MAC (CC_YES && ALG_CMAC) -#define CC_MAC_Start (CC_YES && ALG_CMAC) -#define CC_MakeCredential CC_YES -#define CC_NV_Certify CC_YES -#define CC_NV_ChangeAuth CC_YES -#define CC_NV_DefineSpace CC_YES -#define CC_NV_Extend CC_YES -#define CC_NV_GlobalWriteLock CC_YES -#define CC_NV_Increment CC_YES -#define CC_NV_Read CC_YES -#define CC_NV_ReadLock CC_YES -#define CC_NV_ReadPublic CC_YES -#define CC_NV_SetBits CC_YES -#define CC_NV_UndefineSpace CC_YES -#define CC_NV_UndefineSpaceSpecial CC_YES -#define CC_NV_Write CC_YES -#define CC_NV_WriteLock CC_YES -#define CC_ObjectChangeAuth CC_YES -#define CC_PCR_Allocate CC_YES -#define CC_PCR_Event CC_YES -#define CC_PCR_Extend CC_YES -#define CC_PCR_Read CC_YES -#define CC_PCR_Reset CC_YES -#define CC_PCR_SetAuthPolicy CC_YES -#define CC_PCR_SetAuthValue CC_YES -#define CC_PP_Commands CC_YES -#define CC_PolicyAuthValue CC_YES -#define CC_PolicyAuthorize CC_YES -#define CC_PolicyAuthorizeNV CC_YES -#define CC_PolicyCommandCode CC_YES -#define CC_PolicyCounterTimer CC_YES -#define CC_PolicyCpHash CC_YES -#define CC_PolicyDuplicationSelect CC_YES -#define CC_PolicyGetDigest CC_YES -#define CC_PolicyLocality CC_YES -#define CC_PolicyNV CC_YES -#define CC_PolicyNameHash CC_YES -#define CC_PolicyNvWritten CC_YES -#define CC_PolicyOR CC_YES -#define CC_PolicyPCR CC_YES -#define CC_PolicyPassword CC_YES -#define CC_PolicyPhysicalPresence CC_YES -#define CC_PolicyRestart CC_YES -#define CC_PolicySecret CC_YES -#define CC_PolicySigned CC_YES -#define CC_PolicyTemplate CC_YES -#define CC_PolicyTicket CC_YES -#define CC_Policy_AC_SendSelect CC_YES -#define CC_Quote CC_YES -#define CC_RSA_Decrypt (CC_YES && ALG_RSA) -#define CC_RSA_Encrypt (CC_YES && ALG_RSA) -#define CC_ReadClock CC_YES -#define CC_ReadPublic CC_YES -#define CC_Rewrap CC_YES -#define CC_SelfTest CC_YES -#define CC_SequenceComplete CC_YES -#define CC_SequenceUpdate CC_YES -#define CC_SetAlgorithmSet CC_YES -#define CC_SetCommandCodeAuditStatus CC_YES -#define CC_SetPrimaryPolicy CC_YES -#define CC_Shutdown CC_YES -#define CC_Sign CC_YES -#define CC_StartAuthSession CC_YES -#define CC_Startup CC_YES -#define CC_StirRandom CC_YES -#define CC_TestParms CC_YES -#define CC_Unseal CC_YES -#define CC_Vendor_TCG_Test CC_YES -#define CC_VerifySignature CC_YES -#define CC_ZGen_2Phase (CC_YES && ALG_ECC) - -// Table 2:12 - Definition of TPM_CC Constants -typedef UINT32 TPM_CC; -#if CC_NV_UndefineSpaceSpecial -#define TPM_CC_NV_UndefineSpaceSpecial (TPM_CC)(0x0000011F) -#endif -#if CC_EvictControl -#define TPM_CC_EvictControl (TPM_CC)(0x00000120) -#endif -#if CC_HierarchyControl -#define TPM_CC_HierarchyControl (TPM_CC)(0x00000121) -#endif -#if CC_NV_UndefineSpace -#define TPM_CC_NV_UndefineSpace (TPM_CC)(0x00000122) -#endif -#if CC_ChangeEPS -#define TPM_CC_ChangeEPS (TPM_CC)(0x00000124) -#endif -#if CC_ChangePPS -#define TPM_CC_ChangePPS (TPM_CC)(0x00000125) -#endif -#if CC_Clear -#define TPM_CC_Clear (TPM_CC)(0x00000126) -#endif -#if CC_ClearControl -#define TPM_CC_ClearControl (TPM_CC)(0x00000127) -#endif -#if CC_ClockSet -#define TPM_CC_ClockSet (TPM_CC)(0x00000128) -#endif -#if CC_HierarchyChangeAuth -#define TPM_CC_HierarchyChangeAuth (TPM_CC)(0x00000129) -#endif -#if CC_NV_DefineSpace -#define TPM_CC_NV_DefineSpace (TPM_CC)(0x0000012A) -#endif -#if CC_PCR_Allocate -#define TPM_CC_PCR_Allocate (TPM_CC)(0x0000012B) -#endif -#if CC_PCR_SetAuthPolicy -#define TPM_CC_PCR_SetAuthPolicy (TPM_CC)(0x0000012C) -#endif -#if CC_PP_Commands -#define TPM_CC_PP_Commands (TPM_CC)(0x0000012D) -#endif -#if CC_SetPrimaryPolicy -#define TPM_CC_SetPrimaryPolicy (TPM_CC)(0x0000012E) -#endif -#if CC_FieldUpgradeStart -#define TPM_CC_FieldUpgradeStart (TPM_CC)(0x0000012F) -#endif -#if CC_ClockRateAdjust -#define TPM_CC_ClockRateAdjust (TPM_CC)(0x00000130) -#endif -#if CC_CreatePrimary -#define TPM_CC_CreatePrimary (TPM_CC)(0x00000131) -#endif -#if CC_NV_GlobalWriteLock -#define TPM_CC_NV_GlobalWriteLock (TPM_CC)(0x00000132) -#endif -#if CC_GetCommandAuditDigest -#define TPM_CC_GetCommandAuditDigest (TPM_CC)(0x00000133) -#endif -#if CC_NV_Increment -#define TPM_CC_NV_Increment (TPM_CC)(0x00000134) -#endif -#if CC_NV_SetBits -#define TPM_CC_NV_SetBits (TPM_CC)(0x00000135) -#endif -#if CC_NV_Extend -#define TPM_CC_NV_Extend (TPM_CC)(0x00000136) -#endif -#if CC_NV_Write -#define TPM_CC_NV_Write (TPM_CC)(0x00000137) -#endif -#if CC_NV_WriteLock -#define TPM_CC_NV_WriteLock (TPM_CC)(0x00000138) -#endif -#if CC_DictionaryAttackLockReset -#define TPM_CC_DictionaryAttackLockReset (TPM_CC)(0x00000139) -#endif -#if CC_DictionaryAttackParameters -#define TPM_CC_DictionaryAttackParameters (TPM_CC)(0x0000013A) -#endif -#if CC_NV_ChangeAuth -#define TPM_CC_NV_ChangeAuth (TPM_CC)(0x0000013B) -#endif -#if CC_PCR_Event -#define TPM_CC_PCR_Event (TPM_CC)(0x0000013C) -#endif -#if CC_PCR_Reset -#define TPM_CC_PCR_Reset (TPM_CC)(0x0000013D) -#endif -#if CC_SequenceComplete -#define TPM_CC_SequenceComplete (TPM_CC)(0x0000013E) -#endif -#if CC_SetAlgorithmSet -#define TPM_CC_SetAlgorithmSet (TPM_CC)(0x0000013F) -#endif -#if CC_SetCommandCodeAuditStatus -#define TPM_CC_SetCommandCodeAuditStatus (TPM_CC)(0x00000140) -#endif -#if CC_FieldUpgradeData -#define TPM_CC_FieldUpgradeData (TPM_CC)(0x00000141) -#endif -#if CC_IncrementalSelfTest -#define TPM_CC_IncrementalSelfTest (TPM_CC)(0x00000142) -#endif -#if CC_SelfTest -#define TPM_CC_SelfTest (TPM_CC)(0x00000143) -#endif -#if CC_Startup -#define TPM_CC_Startup (TPM_CC)(0x00000144) -#endif -#if CC_Shutdown -#define TPM_CC_Shutdown (TPM_CC)(0x00000145) -#endif -#if CC_StirRandom -#define TPM_CC_StirRandom (TPM_CC)(0x00000146) -#endif -#if CC_ActivateCredential -#define TPM_CC_ActivateCredential (TPM_CC)(0x00000147) -#endif -#if CC_Certify -#define TPM_CC_Certify (TPM_CC)(0x00000148) -#endif -#if CC_PolicyNV -#define TPM_CC_PolicyNV (TPM_CC)(0x00000149) -#endif -#if CC_CertifyCreation -#define TPM_CC_CertifyCreation (TPM_CC)(0x0000014A) -#endif -#if CC_Duplicate -#define TPM_CC_Duplicate (TPM_CC)(0x0000014B) -#endif -#if CC_GetTime -#define TPM_CC_GetTime (TPM_CC)(0x0000014C) -#endif -#if CC_GetSessionAuditDigest -#define TPM_CC_GetSessionAuditDigest (TPM_CC)(0x0000014D) -#endif -#if CC_NV_Read -#define TPM_CC_NV_Read (TPM_CC)(0x0000014E) -#endif -#if CC_NV_ReadLock -#define TPM_CC_NV_ReadLock (TPM_CC)(0x0000014F) -#endif -#if CC_ObjectChangeAuth -#define TPM_CC_ObjectChangeAuth (TPM_CC)(0x00000150) -#endif -#if CC_PolicySecret -#define TPM_CC_PolicySecret (TPM_CC)(0x00000151) -#endif -#if CC_Rewrap -#define TPM_CC_Rewrap (TPM_CC)(0x00000152) -#endif -#if CC_Create -#define TPM_CC_Create (TPM_CC)(0x00000153) -#endif -#if CC_ECDH_ZGen -#define TPM_CC_ECDH_ZGen (TPM_CC)(0x00000154) -#endif -#if CC_HMAC -#define TPM_CC_HMAC (TPM_CC)(0x00000155) -#endif -#if CC_MAC -#define TPM_CC_MAC (TPM_CC)(0x00000155) -#endif -#if CC_Import -#define TPM_CC_Import (TPM_CC)(0x00000156) -#endif -#if CC_Load -#define TPM_CC_Load (TPM_CC)(0x00000157) -#endif -#if CC_Quote -#define TPM_CC_Quote (TPM_CC)(0x00000158) -#endif -#if CC_RSA_Decrypt -#define TPM_CC_RSA_Decrypt (TPM_CC)(0x00000159) -#endif -#if CC_HMAC_Start -#define TPM_CC_HMAC_Start (TPM_CC)(0x0000015B) -#endif -#if CC_MAC_Start -#define TPM_CC_MAC_Start (TPM_CC)(0x0000015B) -#endif -#if CC_SequenceUpdate -#define TPM_CC_SequenceUpdate (TPM_CC)(0x0000015C) -#endif -#if CC_Sign -#define TPM_CC_Sign (TPM_CC)(0x0000015D) -#endif -#if CC_Unseal -#define TPM_CC_Unseal (TPM_CC)(0x0000015E) -#endif -#if CC_PolicySigned -#define TPM_CC_PolicySigned (TPM_CC)(0x00000160) -#endif -#if CC_ContextLoad -#define TPM_CC_ContextLoad (TPM_CC)(0x00000161) -#endif -#if CC_ContextSave -#define TPM_CC_ContextSave (TPM_CC)(0x00000162) -#endif -#if CC_ECDH_KeyGen -#define TPM_CC_ECDH_KeyGen (TPM_CC)(0x00000163) -#endif -#if CC_EncryptDecrypt -#define TPM_CC_EncryptDecrypt (TPM_CC)(0x00000164) -#endif -#if CC_FlushContext -#define TPM_CC_FlushContext (TPM_CC)(0x00000165) -#endif -#if CC_LoadExternal -#define TPM_CC_LoadExternal (TPM_CC)(0x00000167) -#endif -#if CC_MakeCredential -#define TPM_CC_MakeCredential (TPM_CC)(0x00000168) -#endif -#if CC_NV_ReadPublic -#define TPM_CC_NV_ReadPublic (TPM_CC)(0x00000169) -#endif -#if CC_PolicyAuthorize -#define TPM_CC_PolicyAuthorize (TPM_CC)(0x0000016A) -#endif -#if CC_PolicyAuthValue -#define TPM_CC_PolicyAuthValue (TPM_CC)(0x0000016B) -#endif -#if CC_PolicyCommandCode -#define TPM_CC_PolicyCommandCode (TPM_CC)(0x0000016C) -#endif -#if CC_PolicyCounterTimer -#define TPM_CC_PolicyCounterTimer (TPM_CC)(0x0000016D) -#endif -#if CC_PolicyCpHash -#define TPM_CC_PolicyCpHash (TPM_CC)(0x0000016E) -#endif -#if CC_PolicyLocality -#define TPM_CC_PolicyLocality (TPM_CC)(0x0000016F) -#endif -#if CC_PolicyNameHash -#define TPM_CC_PolicyNameHash (TPM_CC)(0x00000170) -#endif -#if CC_PolicyOR -#define TPM_CC_PolicyOR (TPM_CC)(0x00000171) -#endif -#if CC_PolicyTicket -#define TPM_CC_PolicyTicket (TPM_CC)(0x00000172) -#endif -#if CC_ReadPublic -#define TPM_CC_ReadPublic (TPM_CC)(0x00000173) -#endif -#if CC_RSA_Encrypt -#define TPM_CC_RSA_Encrypt (TPM_CC)(0x00000174) -#endif -#if CC_StartAuthSession -#define TPM_CC_StartAuthSession (TPM_CC)(0x00000176) -#endif -#if CC_VerifySignature -#define TPM_CC_VerifySignature (TPM_CC)(0x00000177) -#endif -#if CC_ECC_Parameters -#define TPM_CC_ECC_Parameters (TPM_CC)(0x00000178) -#endif -#if CC_FirmwareRead -#define TPM_CC_FirmwareRead (TPM_CC)(0x00000179) -#endif -#if CC_GetCapability -#define TPM_CC_GetCapability (TPM_CC)(0x0000017A) -#endif -#if CC_GetRandom -#define TPM_CC_GetRandom (TPM_CC)(0x0000017B) -#endif -#if CC_GetTestResult -#define TPM_CC_GetTestResult (TPM_CC)(0x0000017C) -#endif -#if CC_Hash -#define TPM_CC_Hash (TPM_CC)(0x0000017D) -#endif -#if CC_PCR_Read -#define TPM_CC_PCR_Read (TPM_CC)(0x0000017E) -#endif -#if CC_PolicyPCR -#define TPM_CC_PolicyPCR (TPM_CC)(0x0000017F) -#endif -#if CC_PolicyRestart -#define TPM_CC_PolicyRestart (TPM_CC)(0x00000180) -#endif -#if CC_ReadClock -#define TPM_CC_ReadClock (TPM_CC)(0x00000181) -#endif -#if CC_PCR_Extend -#define TPM_CC_PCR_Extend (TPM_CC)(0x00000182) -#endif -#if CC_PCR_SetAuthValue -#define TPM_CC_PCR_SetAuthValue (TPM_CC)(0x00000183) -#endif -#if CC_NV_Certify -#define TPM_CC_NV_Certify (TPM_CC)(0x00000184) -#endif -#if CC_EventSequenceComplete -#define TPM_CC_EventSequenceComplete (TPM_CC)(0x00000185) -#endif -#if CC_HashSequenceStart -#define TPM_CC_HashSequenceStart (TPM_CC)(0x00000186) -#endif -#if CC_PolicyPhysicalPresence -#define TPM_CC_PolicyPhysicalPresence (TPM_CC)(0x00000187) -#endif -#if CC_PolicyDuplicationSelect -#define TPM_CC_PolicyDuplicationSelect (TPM_CC)(0x00000188) -#endif -#if CC_PolicyGetDigest -#define TPM_CC_PolicyGetDigest (TPM_CC)(0x00000189) -#endif -#if CC_TestParms -#define TPM_CC_TestParms (TPM_CC)(0x0000018A) -#endif -#if CC_Commit -#define TPM_CC_Commit (TPM_CC)(0x0000018B) -#endif -#if CC_PolicyPassword -#define TPM_CC_PolicyPassword (TPM_CC)(0x0000018C) -#endif -#if CC_ZGen_2Phase -#define TPM_CC_ZGen_2Phase (TPM_CC)(0x0000018D) -#endif -#if CC_EC_Ephemeral -#define TPM_CC_EC_Ephemeral (TPM_CC)(0x0000018E) -#endif -#if CC_PolicyNvWritten -#define TPM_CC_PolicyNvWritten (TPM_CC)(0x0000018F) -#endif -#if CC_PolicyTemplate -#define TPM_CC_PolicyTemplate (TPM_CC)(0x00000190) -#endif -#if CC_CreateLoaded -#define TPM_CC_CreateLoaded (TPM_CC)(0x00000191) -#endif -#if CC_PolicyAuthorizeNV -#define TPM_CC_PolicyAuthorizeNV (TPM_CC)(0x00000192) -#endif -#if CC_EncryptDecrypt2 -#define TPM_CC_EncryptDecrypt2 (TPM_CC)(0x00000193) -#endif -#if CC_AC_GetCapability -#define TPM_CC_AC_GetCapability (TPM_CC)(0x00000194) -#endif -#if CC_AC_Send -#define TPM_CC_AC_Send (TPM_CC)(0x00000195) -#endif -#if CC_Policy_AC_SendSelect -#define TPM_CC_Policy_AC_SendSelect (TPM_CC)(0x00000196) -#endif -#define CC_VEND 0x20000000 -#if CC_Vendor_TCG_Test -#define TPM_CC_Vendor_TCG_Test (TPM_CC)(0x20000000) -#endif - -// Additional values for benefit of code -#define TPM_CC_FIRST 0x0000011F -#define TPM_CC_LAST 0x00000196 - - -#if COMPRESSED_LISTS -#define ADD_FILL 0 -#else -#define ADD_FILL 1 -#endif - -// Size the array of library commands based on whether or not -// the array is packed (only defined commands) or dense -// (having entries for unimplemented commands) -#define LIBRARY_COMMAND_ARRAY_SIZE (0 \ - + (ADD_FILL || CC_NV_UndefineSpaceSpecial) /* 0x0000011F */ \ - + (ADD_FILL || CC_EvictControl) /* 0x00000120 */ \ - + (ADD_FILL || CC_HierarchyControl) /* 0x00000121 */ \ - + (ADD_FILL || CC_NV_UndefineSpace) /* 0x00000122 */ \ - + ADD_FILL /* 0x00000123 */ \ - + (ADD_FILL || CC_ChangeEPS) /* 0x00000124 */ \ - + (ADD_FILL || CC_ChangePPS) /* 0x00000125 */ \ - + (ADD_FILL || CC_Clear) /* 0x00000126 */ \ - + (ADD_FILL || CC_ClearControl) /* 0x00000127 */ \ - + (ADD_FILL || CC_ClockSet) /* 0x00000128 */ \ - + (ADD_FILL || CC_HierarchyChangeAuth) /* 0x00000129 */ \ - + (ADD_FILL || CC_NV_DefineSpace) /* 0x0000012A */ \ - + (ADD_FILL || CC_PCR_Allocate) /* 0x0000012B */ \ - + (ADD_FILL || CC_PCR_SetAuthPolicy) /* 0x0000012C */ \ - + (ADD_FILL || CC_PP_Commands) /* 0x0000012D */ \ - + (ADD_FILL || CC_SetPrimaryPolicy) /* 0x0000012E */ \ - + (ADD_FILL || CC_FieldUpgradeStart) /* 0x0000012F */ \ - + (ADD_FILL || CC_ClockRateAdjust) /* 0x00000130 */ \ - + (ADD_FILL || CC_CreatePrimary) /* 0x00000131 */ \ - + (ADD_FILL || CC_NV_GlobalWriteLock) /* 0x00000132 */ \ - + (ADD_FILL || CC_GetCommandAuditDigest) /* 0x00000133 */ \ - + (ADD_FILL || CC_NV_Increment) /* 0x00000134 */ \ - + (ADD_FILL || CC_NV_SetBits) /* 0x00000135 */ \ - + (ADD_FILL || CC_NV_Extend) /* 0x00000136 */ \ - + (ADD_FILL || CC_NV_Write) /* 0x00000137 */ \ - + (ADD_FILL || CC_NV_WriteLock) /* 0x00000138 */ \ - + (ADD_FILL || CC_DictionaryAttackLockReset) /* 0x00000139 */ \ - + (ADD_FILL || CC_DictionaryAttackParameters) /* 0x0000013A */ \ - + (ADD_FILL || CC_NV_ChangeAuth) /* 0x0000013B */ \ - + (ADD_FILL || CC_PCR_Event) /* 0x0000013C */ \ - + (ADD_FILL || CC_PCR_Reset) /* 0x0000013D */ \ - + (ADD_FILL || CC_SequenceComplete) /* 0x0000013E */ \ - + (ADD_FILL || CC_SetAlgorithmSet) /* 0x0000013F */ \ - + (ADD_FILL || CC_SetCommandCodeAuditStatus) /* 0x00000140 */ \ - + (ADD_FILL || CC_FieldUpgradeData) /* 0x00000141 */ \ - + (ADD_FILL || CC_IncrementalSelfTest) /* 0x00000142 */ \ - + (ADD_FILL || CC_SelfTest) /* 0x00000143 */ \ - + (ADD_FILL || CC_Startup) /* 0x00000144 */ \ - + (ADD_FILL || CC_Shutdown) /* 0x00000145 */ \ - + (ADD_FILL || CC_StirRandom) /* 0x00000146 */ \ - + (ADD_FILL || CC_ActivateCredential) /* 0x00000147 */ \ - + (ADD_FILL || CC_Certify) /* 0x00000148 */ \ - + (ADD_FILL || CC_PolicyNV) /* 0x00000149 */ \ - + (ADD_FILL || CC_CertifyCreation) /* 0x0000014A */ \ - + (ADD_FILL || CC_Duplicate) /* 0x0000014B */ \ - + (ADD_FILL || CC_GetTime) /* 0x0000014C */ \ - + (ADD_FILL || CC_GetSessionAuditDigest) /* 0x0000014D */ \ - + (ADD_FILL || CC_NV_Read) /* 0x0000014E */ \ - + (ADD_FILL || CC_NV_ReadLock) /* 0x0000014F */ \ - + (ADD_FILL || CC_ObjectChangeAuth) /* 0x00000150 */ \ - + (ADD_FILL || CC_PolicySecret) /* 0x00000151 */ \ - + (ADD_FILL || CC_Rewrap) /* 0x00000152 */ \ - + (ADD_FILL || CC_Create) /* 0x00000153 */ \ - + (ADD_FILL || CC_ECDH_ZGen) /* 0x00000154 */ \ - + (ADD_FILL || CC_HMAC || CC_MAC) /* 0x00000155 */ \ - + (ADD_FILL || CC_Import) /* 0x00000156 */ \ - + (ADD_FILL || CC_Load) /* 0x00000157 */ \ - + (ADD_FILL || CC_Quote) /* 0x00000158 */ \ - + (ADD_FILL || CC_RSA_Decrypt) /* 0x00000159 */ \ - + ADD_FILL /* 0x0000015A */ \ - + (ADD_FILL || CC_HMAC_Start || CC_MAC_Start) /* 0x0000015B */ \ - + (ADD_FILL || CC_SequenceUpdate) /* 0x0000015C */ \ - + (ADD_FILL || CC_Sign) /* 0x0000015D */ \ - + (ADD_FILL || CC_Unseal) /* 0x0000015E */ \ - + ADD_FILL /* 0x0000015F */ \ - + (ADD_FILL || CC_PolicySigned) /* 0x00000160 */ \ - + (ADD_FILL || CC_ContextLoad) /* 0x00000161 */ \ - + (ADD_FILL || CC_ContextSave) /* 0x00000162 */ \ - + (ADD_FILL || CC_ECDH_KeyGen) /* 0x00000163 */ \ - + (ADD_FILL || CC_EncryptDecrypt) /* 0x00000164 */ \ - + (ADD_FILL || CC_FlushContext) /* 0x00000165 */ \ - + ADD_FILL /* 0x00000166 */ \ - + (ADD_FILL || CC_LoadExternal) /* 0x00000167 */ \ - + (ADD_FILL || CC_MakeCredential) /* 0x00000168 */ \ - + (ADD_FILL || CC_NV_ReadPublic) /* 0x00000169 */ \ - + (ADD_FILL || CC_PolicyAuthorize) /* 0x0000016A */ \ - + (ADD_FILL || CC_PolicyAuthValue) /* 0x0000016B */ \ - + (ADD_FILL || CC_PolicyCommandCode) /* 0x0000016C */ \ - + (ADD_FILL || CC_PolicyCounterTimer) /* 0x0000016D */ \ - + (ADD_FILL || CC_PolicyCpHash) /* 0x0000016E */ \ - + (ADD_FILL || CC_PolicyLocality) /* 0x0000016F */ \ - + (ADD_FILL || CC_PolicyNameHash) /* 0x00000170 */ \ - + (ADD_FILL || CC_PolicyOR) /* 0x00000171 */ \ - + (ADD_FILL || CC_PolicyTicket) /* 0x00000172 */ \ - + (ADD_FILL || CC_ReadPublic) /* 0x00000173 */ \ - + (ADD_FILL || CC_RSA_Encrypt) /* 0x00000174 */ \ - + ADD_FILL /* 0x00000175 */ \ - + (ADD_FILL || CC_StartAuthSession) /* 0x00000176 */ \ - + (ADD_FILL || CC_VerifySignature) /* 0x00000177 */ \ - + (ADD_FILL || CC_ECC_Parameters) /* 0x00000178 */ \ - + (ADD_FILL || CC_FirmwareRead) /* 0x00000179 */ \ - + (ADD_FILL || CC_GetCapability) /* 0x0000017A */ \ - + (ADD_FILL || CC_GetRandom) /* 0x0000017B */ \ - + (ADD_FILL || CC_GetTestResult) /* 0x0000017C */ \ - + (ADD_FILL || CC_Hash) /* 0x0000017D */ \ - + (ADD_FILL || CC_PCR_Read) /* 0x0000017E */ \ - + (ADD_FILL || CC_PolicyPCR) /* 0x0000017F */ \ - + (ADD_FILL || CC_PolicyRestart) /* 0x00000180 */ \ - + (ADD_FILL || CC_ReadClock) /* 0x00000181 */ \ - + (ADD_FILL || CC_PCR_Extend) /* 0x00000182 */ \ - + (ADD_FILL || CC_PCR_SetAuthValue) /* 0x00000183 */ \ - + (ADD_FILL || CC_NV_Certify) /* 0x00000184 */ \ - + (ADD_FILL || CC_EventSequenceComplete) /* 0x00000185 */ \ - + (ADD_FILL || CC_HashSequenceStart) /* 0x00000186 */ \ - + (ADD_FILL || CC_PolicyPhysicalPresence) /* 0x00000187 */ \ - + (ADD_FILL || CC_PolicyDuplicationSelect) /* 0x00000188 */ \ - + (ADD_FILL || CC_PolicyGetDigest) /* 0x00000189 */ \ - + (ADD_FILL || CC_TestParms) /* 0x0000018A */ \ - + (ADD_FILL || CC_Commit) /* 0x0000018B */ \ - + (ADD_FILL || CC_PolicyPassword) /* 0x0000018C */ \ - + (ADD_FILL || CC_ZGen_2Phase) /* 0x0000018D */ \ - + (ADD_FILL || CC_EC_Ephemeral) /* 0x0000018E */ \ - + (ADD_FILL || CC_PolicyNvWritten) /* 0x0000018F */ \ - + (ADD_FILL || CC_PolicyTemplate) /* 0x00000190 */ \ - + (ADD_FILL || CC_CreateLoaded) /* 0x00000191 */ \ - + (ADD_FILL || CC_PolicyAuthorizeNV) /* 0x00000192 */ \ - + (ADD_FILL || CC_EncryptDecrypt2) /* 0x00000193 */ \ - + (ADD_FILL || CC_AC_GetCapability) /* 0x00000194 */ \ - + (ADD_FILL || CC_AC_Send) /* 0x00000195 */ \ - + (ADD_FILL || CC_Policy_AC_SendSelect) /* 0x00000196 */ \ - ) - -#define VENDOR_COMMAND_ARRAY_SIZE (0 + CC_Vendor_TCG_Test) - -#define COMMAND_COUNT (LIBRARY_COMMAND_ARRAY_SIZE + VENDOR_COMMAND_ARRAY_SIZE) - -#define HASH_COUNT \ - (ALG_SHA1 + ALG_SHA256 + ALG_SHA384 + ALG_SHA512 + ALG_SM3_256) - -#define MAX_HASH_BLOCK_SIZE \ - (MAX(ALG_SHA1 * SHA1_BLOCK_SIZE, \ - MAX(ALG_SHA256 * SHA256_BLOCK_SIZE, \ - MAX(ALG_SHA384 * SHA384_BLOCK_SIZE, \ - MAX(ALG_SHA512 * SHA512_BLOCK_SIZE, \ - MAX(ALG_SM3_256 * SM3_256_BLOCK_SIZE, \ - 0)))))) - -#define MAX_DIGEST_SIZE \ - (MAX(ALG_SHA1 * SHA1_DIGEST_SIZE, \ - MAX(ALG_SHA256 * SHA256_DIGEST_SIZE, \ - MAX(ALG_SHA384 * SHA384_DIGEST_SIZE, \ - MAX(ALG_SHA512 * SHA512_DIGEST_SIZE, \ - MAX(ALG_SM3_256 * SM3_256_DIGEST_SIZE, \ - 0)))))) - - -#if MAX_DIGEST_SIZE == 0 || MAX_HASH_BLOCK_SIZE == 0 -#error "Hash data not valid" -#endif - -// Define the 2B structure that would hold any hash block -TPM2B_TYPE(MAX_HASH_BLOCK, MAX_HASH_BLOCK_SIZE); - -// Following typedef is for some old code -typedef TPM2B_MAX_HASH_BLOCK TPM2B_HASH_BLOCK; - -/* AddSymmetricConstants */ -#ifndef ALG_AES -#define ALG_AES NO -#endif -#ifndef MAX_AES_KEY_BITS -#define MAX_AES_KEY_BITS 0 -#define MAX_AES_BLOCK_SIZE_BYTES 0 -#endif -#ifndef ALG_CAMELLIA -#define ALG_CAMELLIA NO -#endif -#ifndef MAX_CAMELLIA_KEY_BITS -#define MAX_CAMELLIA_KEY_BITS 0 -#define MAX_CAMELLIA_BLOCK_SIZE_BYTES 0 -#endif -#ifndef ALG_SM4 -#define ALG_SM4 NO -#endif -#ifndef MAX_SM4_KEY_BITS -#define MAX_SM4_KEY_BITS 0 -#define MAX_SM4_BLOCK_SIZE_BYTES 0 -#endif -#ifndef ALG_TDES -#define ALG_TDES NO -#endif -#ifndef MAX_TDES_KEY_BITS -#define MAX_TDES_KEY_BITS 0 -#define MAX_TDES_BLOCK_SIZE_BYTES 0 -#endif -#define MAX_SYM_KEY_BITS \ - (MAX(ALG_AES * MAX_AES_KEY_BITS, \ - MAX(ALG_CAMELLIA * MAX_CAMELLIA_KEY_BITS, \ - MAX(ALG_SM4 * MAX_SM4_KEY_BITS, \ - MAX(ALG_TDES * MAX_TDES_KEY_BITS, \ - 0))))) - -#define MAX_SYM_KEY_BYTES ((MAX_SYM_KEY_BITS + 7) / 8) - -#define MAX_SYM_BLOCK_SIZE \ - (MAX(ALG_AES * MAX_AES_BLOCK_SIZE_BYTES, \ - MAX(ALG_CAMELLIA * MAX_CAMELLIA_BLOCK_SIZE_BYTES, \ - MAX(ALG_SM4 * MAX_SM4_BLOCK_SIZE_BYTES, \ - MAX(ALG_TDES * MAX_TDES_BLOCK_SIZE_BYTES, \ - 0))))) - -#if MAX_SYM_KEY_BITS == 0 || MAX_SYM_BLOCK_SIZE == 0 -# error Bad size for MAX_SYM_KEY_BITS or MAX_SYM_BLOCK_SIZE -#endif - -#endif // _IMPLEMENTATION_H_ diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/RuntimeSupport.h b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/RuntimeSupport.h deleted file mode 100644 index af2767691..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/RuntimeSupport.h +++ /dev/null @@ -1,93 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _RUNTIMESUPPORT_H_ -#define _RUNTIMESUPPORT_H_ - -// OPTEE provides simple versions of these headers -#include -#include -#include -#include - -typedef uint64_t clock_t; - -#ifndef XMEMCPY -#define XMEMCPY(pdest, psrc, size) memcpy((pdest), (psrc), (size)) -#endif - -#ifndef XMEMSET -#define XMEMSET(pdest, value, size) memset((pdest), (value), (size)) -#endif - -#ifndef XSTRLEN -#define XSTRLEN(str) strlen((str)) -#endif - -#ifndef XSTRNCPY -#define XSTRNCPY(str1,str2,n) strncpy((str1),(str2),(n)) -#endif - -#ifndef XSTRNCASECMP -int strncasecmp(const char *str1, const char *str2, size_t n); -#define XSTRNCASECMP(str1,str2,n) strncasecmp((str1),(str2),(n)) -#endif - -#ifndef XSTRNCMP -#define XSTRNCMP(str1,str2,n) strncmp((str1),(str2),(n)) -#endif - -#ifndef XMEMCMP -#define XMEMCMP(str1,str2,n) memcmp((str1),(str2),(n)) -#endif - -#ifndef XTOUPPER -int toupper (int c); -#define XTOUPPER(str1) toupper((str1)) -#endif - -#ifndef XTOLOWER -int tolower (int c); -#define XTOLOWER(str1) tolower((str1)) -#endif - -#undef WC_NO_HASHDRBG -#define WC_NO_HASHDRBG - -/* Bypass P-RNG and use only HW RNG */ -extern int wolfRand(unsigned char* output, unsigned int sz); -#undef CUSTOM_RAND_GENERATE_BLOCK -#define CUSTOM_RAND_GENERATE_BLOCK wolfRand -#endif diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/TpmSal.h b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/TpmSal.h deleted file mode 100644 index 020ac0d16..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/TpmSal.h +++ /dev/null @@ -1,115 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*** -* TpmSal.h provides a set of #defines that allow SymCrypt to be built -* in VS. -* -****/ - -#ifndef _TPM_SAL_H_ -#define _TPM_SAL_H_ - -#ifndef _Out_writes_bytes_ - -#define _Out_writes_( cbData ) -#define _Out_writes_bytes_( cbData ) -#define _Out_writes_opt_( cbData ) -#define _Out_writes_to_(n, c) -#define _In_reads_( cbBytes ) -#define _In_reads_opt_( cbAuthData ) -#define _In_reads_bytes_(size) -#define _Inout_updates_( nStates ) -#define _Inout_updates_bytes_(size) -#define _Field_size_( size ) -#define _Field_range_( min, max ) -#define _Writable_elements_(c) -#define _Ret_writes_bytes_to_(n, c) - -#define _Analysis_assume_(x) -#define _Analysis_noreturn_ - -#define _Use_decl_annotations_ - -#define __success(x) - -#define __assume -#define __analysis_assume -#define _In_ -#define _Out_ -#define __in -#define __in_opt -#define __in_bcount(x) -#define __in_bcount_opt(x) -#define __in_ecount(x) -#define __in_ecount_opt(x) -#define __in_xcount(x) -#define __out -#define __out_ecount(x) -#define __out_ecount_opt(x) -#define __out_ecount_full(x) -#define __out_ecount_part(x, y) -#define __out_bcount(x) -#define __out_bcount_part_opt(x, y) -#define __out_bcount_full(x) -#define __out_xcount(x) -#define __out_xcount_opt(x) -#define __out_ecount_part(x, y) -#define __out_ecount_part_opt(x, y) -#define __out_opt -#define __inout_ecount(x) -#define __inout_bcount(x) -#define __bound -#define __inout -#define __inout_opt -#define __inout_ecount_opt(x) -#define __deref_out_ecount(x) -#define __deref_opt_out_ecount(x) -#define __field_ecount(x) -#define _Post_invalid_ -#define _Pre_maybenull_ -#define __checkReturn -#define _In_bytecount_(x) - -#endif /* no SAL macros defined */ - -#ifndef _Interlocked_operand_ - -#define _Interlocked_operand_ - -#endif - - -#endif diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/VendorString.h b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/VendorString.h deleted file mode 100644 index b2b798ef3..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/VendorString.h +++ /dev/null @@ -1,93 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _VENDOR_STRING_H -#define _VENDOR_STRING_H - -// Define up to 4-byte values for MANUFACTURER. This value defines the response -// for TPM_PT_MANUFACTURER in TPM2_GetCapability. -// The following line should be un-commented and a vendor specific string -// should be provided here. -#define MANUFACTURER "MSFT" - -// The following #if macro may be deleted after a proper MANUFACTURER is provided. -#ifndef MANUFACTURER -#error MANUFACTURER is not provided. \ -Please modify include\VendorString.h to provide a specific \ -manufacturer name. -#endif - -// Define up to 4, 4-byte values. The values must each be 4 bytes long and the last -// value used may contain trailing zeros. -// These values define the response for TPM_PT_VENDOR_STRING_(1-4) -// in TPM2_GetCapability. -// The following line should be un-commented and a vendor specific string -// should be provided here. -// The vendor strings 2-4 may also be defined as appropriately. -#define VENDOR_STRING_1 "SSE " -#define VENDOR_STRING_2 "fTPM" -//#define VENDOR_STRING_3 -//#define VENDOR_STRING_4 - -// The following #if macro may be deleted after a proper VENDOR_STRING_1 -// is provided. -#ifndef VENDOR_STRING_1 -#error VENDOR_STRING_1 is not provided. \ -Please modify include\VendorString.h to provide a vendor specific \ -string. -#endif - -// the more significant 32-bits of a vendor-specific value -// indicating the version of the firmware -// The following line should be un-commented and a vendor-specific firmware V1 -// should be provided here. -// The FIRMWARE_V2 may also be defined as appropriate. - -//Date of last update: (0xYYYMMDD) -#define FIRMWARE_V1 (0x20180710) -// the less significant 32-bits of a vendor-specific value -// indicating the version of the firmware - -//Time of last update: (0x00HHMMSS) -#define FIRMWARE_V2 (0x00105300) - -// The following #if macro may be deleted after a proper FIRMWARE_V1 is provided. -#ifndef FIRMWARE_V1 -#error FIRMWARE_V1 is not provided. \ -Please modify include\VendorString.h to provide a vendor-specific firmware \ -version -#endif - -#endif diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/bool.h b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/bool.h deleted file mode 100644 index 60b55ee2f..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/reference/include/bool.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _BOOL_H -#define _BOOL_H - -#if defined(TRUE) -#undef TRUE -#endif - -#if defined FALSE -#undef FALSE -#endif - -typedef int BOOL; -#define FALSE ((BOOL)0) -#define TRUE ((BOOL)1) - -#endif diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/sub.mk b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/sub.mk deleted file mode 100644 index b719992e9..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/sub.mk +++ /dev/null @@ -1,53 +0,0 @@ -WARNS ?= 1 -NOWERROR ?= 1 -CFG_TA_DEBUG ?= 1 -CFG_TEE_TA_LOG_LEVEL ?= 1 - -cflags-y += -DTHIRTY_TWO_BIT -DCFG_TEE_TA_LOG_LEVEL=$(CFG_TEE_TA_LOG_LEVEL) -D_ARM_ -w -Wno-strict-prototypes -mcpu=$(TA_CPU) -fstack-protector -Wstack-protector - -ifeq ($(CFG_ARM64_ta_arm64),y) -cflags-y += -mstrict-align -else -cflags-y += -mno-unaligned-access -endif - -ifeq ($(CFG_TA_DEBUG),y) -cflags-y += -DfTPMDebug=1 -cflags-y += -DDBG=1 -cflags-y += -O0 -cflags-y += -DDEBUG -else -cflags-y += -Os -cflags-y += -DNDEBUG -endif - -# -# Link the required external code into the libraries folder. OP-TEE build -# does not work well when accessing anything below the root directory. Use -# symlinks to trick it. -# -all: create_lib_symlinks -clean: clean_lib_symlinks - -subdirs-y += lib - -global-incdirs-y += include -global-incdirs-y += reference/include -global-incdirs-y += platform/include - -srcs-y += platform/AdminPPI.c -srcs-y += platform/Cancel.c -srcs-y += platform/Clock.c -srcs-y += platform/Entropy.c -srcs-y += platform/LocalityPlat.c -srcs-y += platform/NvAdmin.c -srcs-y += platform/NVMem.c -srcs-y += platform/PowerPlat.c -srcs-y += platform/PlatformData.c -srcs-y += platform/PPPlat.c -srcs-y += platform/RunCommand.c -srcs-y += platform/Unique.c -srcs-y += platform/EPS.c -srcs-y += reference/RuntimeSupport.c - -srcs-y += fTPM.c diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/user_ta_header_defines.h b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/user_ta_header_defines.h deleted file mode 100644 index 72ecbf0cf..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/optee_ta/fTPM/user_ta_header_defines.h +++ /dev/null @@ -1,56 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * The name of this file must not be modified - */ - -#ifndef USER_TA_HEADER_DEFINES_H -#define USER_TA_HEADER_DEFINES_H - -#include - -#define TA_UUID TA_FTPM_UUID - -#define TA_FLAGS (TA_FLAG_SINGLE_INSTANCE | TA_FLAG_INSTANCE_KEEP_ALIVE) -#define TA_STACK_SIZE (64 * 1024) -#define TA_DATA_SIZE (32 * 1024) - -#define TA_CURRENT_TA_EXT_PROPERTIES \ - { "gp.ta.description", USER_TA_PROP_TYPE_STRING, \ - "fTPM TA" }, \ - { "gp.ta.version", USER_TA_PROP_TYPE_U32, &(const uint32_t){ 0x0010 } } - -#endif /*USER_TA_HEADER_DEFINES_H*/ diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/ta_prod_signing_scripts/README.md b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/ta_prod_signing_scripts/README.md deleted file mode 100644 index 4d992b9a2..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/ta_prod_signing_scripts/README.md +++ /dev/null @@ -1,17 +0,0 @@ -# Microsoft Production TA Signing Scripts - -##### The Python scripts `generate_digest.py` and `stitch_ta.py` are used to production sign Microsoft-built TAs. - -## Usage - -1. Compile the TAs as usual. -2. Take the `*.stripped.elf` file (TA with no signature), and run the following Python script. -This script will generate the digest (hash) for the unsigned TA. The digest will be stored in `6b51f84e-a93d-456c-ab0e29ad8f264a47.dig` in the same folder as the TA. The digest will be in ASCII Base64 format. -``` -c:\Python34\python.exe "generate_digest.py" --in "6b51f84e-a93d-456c-ab0e29ad8f264a47.stripped.elf" -``` -3. Send the `*.dig` file to the Security team for them to sign. They will return a `*.dig.signed` file. -4. Run the following Python script to generate the final Production-signed TA (`6b51f84e-a93d-456c-ab0e29ad8f264a47_signed.ta`): -``` -c:\Python34\python.exe "stitch_ta.py" --in "6b51f84e-a93d-456c-ab0e29ad8f264a47.stripped.elf" --dig "6b51f84e-a93d-456c-ab0e29ad8f264a47.dig" --sig "6b51f84e-a93d-456c-ab0e29ad8f264a47.dig.signed" --out "6b51f84e-a93d-456c-ab0e29ad8f264a47_signed.ta" -``` \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/ta_prod_signing_scripts/generate_digest.py b/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/ta_prod_signing_scripts/generate_digest.py deleted file mode 100644 index 18dbd1cde..000000000 --- a/simulator/ms-tpm-20-ref/Samples/ARM32-FirmwareTPM/ta_prod_signing_scripts/generate_digest.py +++ /dev/null @@ -1,90 +0,0 @@ -#!/usr/bin/env python -# -# Copyright (c) 2015, Linaro Limited -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# - -def get_args(): - from argparse import ArgumentParser - - parser = ArgumentParser() - parser.add_argument('--in', required=True, dest='inf', \ - help='Name of input file (unsigned TA)') - return parser.parse_args() - -def assert_file_exists(fname): - import os.path - - if(os.path.isfile(fname)): - return True - else: - raise FileNotFoundError('File ' + fname + ' was not found') - -def main(): - from Crypto.Signature import PKCS1_v1_5 - from Crypto.Hash import SHA256 - from Crypto.PublicKey import RSA - import struct, base64, os.path, sys - - args = get_args() - - assert_file_exists(args.inf) - - # Read input file (unsigned TA) - f = open(args.inf, 'rb') - img = f.read() - f.close() - - h = SHA256.new() - - digest_len = h.digest_size - #We plan to use RSA 2048 bit keys so signature is 256 bytes - sig_len = 256 #len(signer.sign(h)) - img_size = len(img) - - magic = 0x4f545348 # SHDR_MAGIC - img_type = 0 # SHDR_TA - algo = 0x70004830 # TEE_ALG_RSASSA_PKCS1_V1_5_SHA256 - shdr = struct.pack(' + +#include "PlatformData.h" +#include "Platform_fp.h" + +unsigned int s_adjustRate; +bool s_timerReset; + +clock64_t s_realTimePrevious; +clock64_t s_tpmTime; +clock64_t s_lastSystemTime; +clock64_t s_lastReportedTime; + +void _plat__TimerReset() { + s_lastSystemTime = 0; + s_tpmTime = 0; + s_adjustRate = CLOCK_NOMINAL; + s_timerReset = true; + return; +} + +static uint64_t _plat__RealTime() { + struct timespec systime; + clock_gettime(CLOCK_MONOTONIC, &systime); + return (clock64_t)systime.tv_sec * 1000 + (systime.tv_nsec / 1000000); +} + +uint64_t _plat__TimerRead() { + clock64_t timeDiff; + clock64_t adjustedTimeDiff; + clock64_t timeNow; + clock64_t readjustedTimeDiff; + + // This produces a timeNow that is basically locked to the system clock. + timeNow = _plat__RealTime(); + + // if this hasn't been initialized, initialize it + if (s_lastSystemTime == 0) { + s_lastSystemTime = timeNow; + s_lastReportedTime = 0; + s_realTimePrevious = 0; + } + // The system time can bounce around and that's OK as long as we don't allow + // time to go backwards. When the time does appear to go backwards, set + // lastSystemTime to be the new value and then update the reported time. + if (timeNow < s_lastReportedTime) s_lastSystemTime = timeNow; + s_lastReportedTime = s_lastReportedTime + timeNow - s_lastSystemTime; + s_lastSystemTime = timeNow; + timeNow = s_lastReportedTime; + + // The code above produces a timeNow that is similar to the value returned + // by Clock(). The difference is that timeNow does not max out, and it is + // at a ms. rate rather than at a CLOCKS_PER_SEC rate. The code below + // uses that value and does the rate adjustment on the time value. + // If there is no difference in time, then skip all the computations + if (s_realTimePrevious >= timeNow) return s_tpmTime; + // Compute the amount of time since the last update of the system clock + timeDiff = timeNow - s_realTimePrevious; + + // Do the time rate adjustment and conversion from CLOCKS_PER_SEC to mSec + adjustedTimeDiff = (timeDiff * CLOCK_NOMINAL) / ((uint64_t)s_adjustRate); + + // update the TPM time with the adjusted timeDiff + s_tpmTime += (clock64_t)adjustedTimeDiff; + + // Might have some rounding error that would loose CLOCKS. See what is not + // being used. As mentioned above, this could result in putting back more than + // is taken out. Here, we are trying to recreate timeDiff. + readjustedTimeDiff = + (adjustedTimeDiff * (uint64_t)s_adjustRate) / CLOCK_NOMINAL; + + // adjusted is now converted back to being the amount we should advance the + // previous sampled time. It should always be less than or equal to timeDiff. + // That is, we could not have use more time than we started with. + s_realTimePrevious = s_realTimePrevious + readjustedTimeDiff; + + return s_tpmTime; +} + +bool _plat__TimerWasReset() { + bool retVal = s_timerReset; + s_timerReset = false; + return retVal; +} + +void _plat__ClockAdjustRate(int adjust) { + // We expect the caller should only use a fixed set of constant values to + // adjust the rate + switch (adjust) { + case CLOCK_ADJUST_COARSE: + s_adjustRate += CLOCK_ADJUST_COARSE; + break; + case -CLOCK_ADJUST_COARSE: + s_adjustRate -= CLOCK_ADJUST_COARSE; + break; + case CLOCK_ADJUST_MEDIUM: + s_adjustRate += CLOCK_ADJUST_MEDIUM; + break; + case -CLOCK_ADJUST_MEDIUM: + s_adjustRate -= CLOCK_ADJUST_MEDIUM; + break; + case CLOCK_ADJUST_FINE: + s_adjustRate += CLOCK_ADJUST_FINE; + break; + case -CLOCK_ADJUST_FINE: + s_adjustRate -= CLOCK_ADJUST_FINE; + break; + default: + // ignore any other values; + break; + } + + if (s_adjustRate > (CLOCK_NOMINAL + CLOCK_ADJUST_LIMIT)) + s_adjustRate = CLOCK_NOMINAL + CLOCK_ADJUST_LIMIT; + if (s_adjustRate < (CLOCK_NOMINAL - CLOCK_ADJUST_LIMIT)) + s_adjustRate = CLOCK_NOMINAL - CLOCK_ADJUST_LIMIT; + + return; +} diff --git a/simulator/ms-tpm-20-ref/Samples/Google/Entropy.c b/simulator/ms-tpm-20-ref/Samples/Google/Entropy.c new file mode 100644 index 000000000..ecaba7950 --- /dev/null +++ b/simulator/ms-tpm-20-ref/Samples/Google/Entropy.c @@ -0,0 +1,11 @@ +#include + +#include "Platform_fp.h" + +// We get entropy from OpenSSL which gets its entropy from the OS. +int32_t _plat__GetEntropy(uint8_t *entropy, uint32_t amount) { + if (RAND_bytes(entropy, amount) != 1) { + return -1; + } + return amount; +} diff --git a/simulator/ms-tpm-20-ref/Samples/Google/NVMem.c b/simulator/ms-tpm-20-ref/Samples/Google/NVMem.c new file mode 100644 index 000000000..baac11b82 --- /dev/null +++ b/simulator/ms-tpm-20-ref/Samples/Google/NVMem.c @@ -0,0 +1,81 @@ +/* Microsoft Reference Implementation for TPM 2.0 + * + * The copyright in this software is being made available under the BSD + * License, included below. This software may be subject to other third party + * and contributor rights, including patent rights, and no such rights are + * granted under this license. + * + * Copyright (c) Microsoft Corporation + * + * All rights reserved. + * + * BSD License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS + * IS"" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +//** Description +// +// This file contains the NV read and write access methods. This +// implementation uses RAM/file and does not manage the RAM/file as NV +// blocks. The implementation may become more sophisticated over time. +// + +#include +#include + +#include "PlatformData.h" +#include "Platform_fp.h" + +unsigned char s_NV[NV_MEMORY_SIZE]; + +void _plat__NvMemoryRead(unsigned int start, unsigned int size, void *data) { + assert(start + size <= NV_MEMORY_SIZE); + memcpy(data, &s_NV[start], size); + return; +} + +int _plat__NvIsDifferent(unsigned int start, unsigned int size, void *data) { + return (memcmp(&s_NV[start], data, size) != 0); +} + +bool _plat__NvMemoryWrite(unsigned int start, unsigned int size, void *data) { + if (start + size <= NV_MEMORY_SIZE) { + memcpy(&s_NV[start], data, size); + return true; + } + return false; +} + +void _plat__NvMemoryClear(unsigned int start, unsigned int size) { + assert(start + size <= NV_MEMORY_SIZE); + // In this implementation, assume that the erase value for NV is all 1s + memset(&s_NV[start], 0xff, size); +} + +void _plat__NvMemoryMove(unsigned int sourceOffset, unsigned int destOffset, + unsigned int size) { + assert(sourceOffset + size <= NV_MEMORY_SIZE); + assert(destOffset + size <= NV_MEMORY_SIZE); + memmove(&s_NV[destOffset], &s_NV[sourceOffset], size); + return; +} diff --git a/simulator/ms-tpm-20-ref/Samples/Google/Platform.h b/simulator/ms-tpm-20-ref/Samples/Google/Platform.h new file mode 100644 index 000000000..b71713a7a --- /dev/null +++ b/simulator/ms-tpm-20-ref/Samples/Google/Platform.h @@ -0,0 +1,71 @@ +/* Microsoft Reference Implementation for TPM 2.0 + * + * The copyright in this software is being made available under the BSD + * License, included below. This software may be subject to other third party + * and contributor rights, including patent rights, and no such rights are + * granted under this license. + * + * Copyright (c) Microsoft Corporation + * + * All rights reserved. + * + * BSD License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS + * IS"" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +// External interface to the vTPM + +#ifndef _PLATFORM_H_ +#define _PLATFORM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +//***_plat__RunCommand() +// This version of RunCommand will set up a jum_buf and call ExecuteCommand(). +// If the command executes without failing, it will return and RunCommand will +// return. If there is a failure in the command, then _plat__Fail() is called +// and it will longjump back to RunCommand which will call ExecuteCommand again. +// However, this time, the TPM will be in failure mode so ExecuteCommand will +// simply build a failure response and return. +void _plat__RunCommand(uint32_t requestSize, // IN: command buffer size + unsigned char *request, // IN: command buffer + uint32_t *responseSize, // IN/OUT: response buffer size + unsigned char **response // IN/OUT: response buffer +); + +//*** _plat_Reset() +// Reset the TPM. This should always be called before _plat__RunCommand. The +// first time this function is called, the TPM will be manufactured. Pass true +// for forceManufacture to perfrom a manufacturer reset. +void _plat__Reset(bool forceManufacture); + +#ifdef __cplusplus +} +#endif + +#endif // _PLATFORM_H_ diff --git a/simulator/ms-tpm-20-ref/Samples/Google/PlatformData.h b/simulator/ms-tpm-20-ref/Samples/Google/PlatformData.h new file mode 100644 index 000000000..4d9a276d5 --- /dev/null +++ b/simulator/ms-tpm-20-ref/Samples/Google/PlatformData.h @@ -0,0 +1,86 @@ +/* Microsoft Reference Implementation for TPM 2.0 + * + * The copyright in this software is being made available under the BSD + * License, included below. This software may be subject to other third party + * and contributor rights, including patent rights, and no such rights are + * granted under this license. + * + * Copyright (c) Microsoft Corporation + * + * All rights reserved. + * + * BSD License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS + * IS"" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +// This file contains the instance data for the Platform module. It is collected +// in this file so that the state of the module is easier to manage. + +#ifndef _PLATFORM_DATA_H_ +#define _PLATFORM_DATA_H_ + +#include +#include + +#include "TpmProfile.h" // For NV_MEMORY_SIZE + +typedef uint64_t clock64_t; +// This is the value returned the last time that the system clock was read. This +// is only relevant for a simulator or virtual TPM. +extern clock64_t s_realTimePrevious; + +// These values are used to try to synthesize a long lived version of clock(). +extern clock64_t s_lastSystemTime; +extern clock64_t s_lastReportedTime; + +// This is the rate adjusted value that is the equivalent of what would be read +// from a hardware register that produced rate adjusted time. +extern clock64_t s_tpmTime; + +// This value indicates that the timer was reset +extern bool s_timerReset; +// This variable records the timer adjustment factor. +extern unsigned int s_adjustRate; + +// CLOCK_NOMINAL is the number of hardware ticks per mS. A value of 300000 means +// that the nominal clock rate used to drive the hardware clock is 30 MHz. The +// adjustment rates are used to determine the conversion of the hardware ticks +// to internal hardware clock value. In practice, we would expect that there +// would be a hardware register with accumulated mS. It would be incremented by +// the output of a prescaler. The prescaler would divide the ticks from the +// clock by some value that would compensate for the difference between clock +// time and real time. The code in Clock does the emulation of this function. +#define CLOCK_NOMINAL 30000 +// A 1% change in rate is 300 counts +#define CLOCK_ADJUST_COARSE 300 +// A 0.1% change in rate is 30 counts +#define CLOCK_ADJUST_MEDIUM 30 +// A minimum change in rate is 1 count +#define CLOCK_ADJUST_FINE 1 +// The clock tolerance is +/-15% (4500 counts) +// Allow some guard band (16.7%) +#define CLOCK_ADJUST_LIMIT 5000 + +extern unsigned char s_NV[NV_MEMORY_SIZE]; + +#endif // _PLATFORM_DATA_H_ diff --git a/simulator/ms-tpm-20-ref/Samples/Google/Platform_fp.h b/simulator/ms-tpm-20-ref/Samples/Google/Platform_fp.h new file mode 100644 index 000000000..e8d63d242 --- /dev/null +++ b/simulator/ms-tpm-20-ref/Samples/Google/Platform_fp.h @@ -0,0 +1,197 @@ +/* Microsoft Reference Implementation for TPM 2.0 + * + * The copyright in this software is being made available under the BSD + * License, included below. This software may be subject to other third party + * and contributor rights, including patent rights, and no such rights are + * granted under this license. + * + * Copyright (c) Microsoft Corporation + * + * All rights reserved. + * + * BSD License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS + * IS"" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +// Platform functions used by libtpm + +#ifndef _PLATFORM_FP_H_ +#define _PLATFORM_FP_H_ + +#include +#include + +//***_plat__IsCanceled() +// We opt to not support cancellation, so always return false. +// Return values: +// true(1) if cancel flag is set +// false(0) if cancel flag is not set +static inline int _plat__IsCanceled() { return false; } + +//***_plat__TimerReset() +// This function sets current system clock time as t0 for counting TPM time. +// This function is called at a power on event to reset the clock. When the +// clock is reset, the indication that the clock was stopped is also set. +void _plat__TimerReset(); + +//***_plat__TimerRead() +// This function provides access to the tick timer of the platform. The TPM code +// uses this value to drive the TPM Clock. +// +// The tick timer is supposed to run when power is applied to the device. This +// timer should not be reset by time events including _TPM_Init. It should only +// be reset when TPM power is re-applied. +// +// If the TPM is run in a protected environment, that environment may provide +// the tick time to the TPM as long as the time provided by the environment is +// not allowed to go backwards. If the time provided by the system can go +// backwards during a power discontinuity, then the _plat__Signal_PowerOn should +// call _plat__TimerReset(). +uint64_t _plat__TimerRead(); + +//*** _plat__TimerWasReset() +// This function is used to interrogate the flag indicating if the tick timer +// has been reset. +// +// If the resetFlag parameter is SET, then the flag will be CLEAR before the +// function returns. +bool _plat__TimerWasReset(); + +//*** _plat__TimerWasStopped() +// As we have CLOCK_STOPS=NO, we will only stop our timer on resets. +static inline bool _plat__TimerWasStopped() { return _plat__TimerWasReset(); } + +//***_plat__ClockAdjustRate() +// Adjust the clock rate +// IN: the adjust number. It could be positive or negative +void _plat__ClockAdjustRate(int adjust); + +//*** _plat__GetEntropy() +// This function is used to get available hardware entropy. In a hardware +// implementation of this function, there would be no call to the system +// to get entropy. +// Return values: +// < 0 hardware failure of the entropy generator, this is sticky +// >= 0 the returned amount of entropy (bytes) +int32_t _plat__GetEntropy(uint8_t *entropy, // output buffer + uint32_t amount // amount requested +); + +//***_plat__LocalityGet() +// We do not support non-zero localities, so just always return 0. +static inline uint8_t _plat__LocalityGet() { return 0; } + +//***_plat__NVEnable() +// As we just hold the NV data in memory, always return success. +// Return values: +// 0 if success +// > 0 if receive recoverable error +// < 0 if unrecoverable error +static inline int _plat__NVEnable(void *platParameter) { + (void)(platParameter); + return 0; +}; + +//***_plat__IsNvAvailable() +// Our NV Data is always available and has no write limits. +// Return values: +// 0 NV is available +// 1 NV is not available due to write failure +// 2 NV is not available due to rate limit +static inline int _plat__IsNvAvailable() { return 0; } + +//***_plat__NvMemoryRead() +// Function: Read a chunk of NV memory +void _plat__NvMemoryRead(unsigned int startOffset, // IN: read start + unsigned int size, // IN: size of bytes to read + void *data // OUT: data buffer +); + +//*** _plat__NvIsDifferent() +// This function checks to see if the NV is different from the test value. This +// is so that NV will not be written if it has not changed. +// Return Type: int +// TRUE(1) the NV location is different from the test value +// FALSE(0) the NV location is the same as the test value +int _plat__NvIsDifferent(unsigned int startOffset, // IN: read start + unsigned int size, // IN: size of bytes to read + void *data // IN: data buffer +); + +//***_plat__NvMemoryWrite() +// This function is used to update NV memory. The "write" is to a memory copy of +// NV. At the end of the current command, any changes are written to +// the actual NV memory. +// NOTE: A useful optimization would be for this code to compare the current +// contents of NV with the local copy and note the blocks that have changed. +// Then only write those blocks when _plat__NvCommit() is called. +bool _plat__NvMemoryWrite(unsigned int startOffset, // IN: write start + unsigned int size, // IN: size of bytes to write + void *data // OUT: data buffer +); + +//***_plat__NvMemoryClear() +// Function is used to set a range of NV memory bytes to an implementation- +// dependent value. The value represents the erase state of the memory. +void _plat__NvMemoryClear(unsigned int start, // IN: clear start + unsigned int size // IN: number of bytes to clear +); + +//***_plat__NvMemoryMove() +// Function: Move a chunk of NV memory from source to destination +// This function should ensure that if there overlap, the original data is +// copied before it is written +void _plat__NvMemoryMove(unsigned int sourceOffset, // IN: source offset + unsigned int destOffset, // IN: destination offset + unsigned int size // IN: size of data being moved +); + +//***_plat__NvCommit() +// Our NV Data is just in memory, so "committing" it is a no-op. +// Return values: +// 0 NV write success +// != 0 NV write fail +static inline int _plat__NvCommit() { return 0; } + +//*** _plat__WasPowerLost() +// Test whether power was lost before a _TPM_Init. As we use in-memory NV Data, +// there's no reason to to not do the power-loss activities on every _TPM_Init. +// Return values: +// true(1) power was lost +// false(0) power was not lost +static inline int _plat__WasPowerLost() { return true; } + +//** From PPPlat.c + +//***_plat__PhysicalPresenceAsserted() +// Our vTPM has no way to assert physical presence, so we always return true. +// Return values: +// true(1) if physical presence is signaled +// false(0) if physical presence is not signaled +static inline int _plat__PhysicalPresenceAsserted() { return true; } + +//***_plat__Fail() +// This is the platform depended failure exit for the TPM. +_Noreturn void _plat__Fail(); + +#endif // _PLATFORM_FP_H_ diff --git a/simulator/ms-tpm-20-ref/Samples/Google/Run.c b/simulator/ms-tpm-20-ref/Samples/Google/Run.c new file mode 100644 index 000000000..044dc043d --- /dev/null +++ b/simulator/ms-tpm-20-ref/Samples/Google/Run.c @@ -0,0 +1,78 @@ +/* Microsoft Reference Implementation for TPM 2.0 + * + * The copyright in this software is being made available under the BSD + * License, included below. This software may be subject to other third party + * and contributor rights, including patent rights, and no such rights are + * granted under this license. + * + * Copyright (c) Microsoft Corporation + * + * All rights reserved. + * + * BSD License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS + * IS"" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +//**Introduction +// This module provides the platform specific entry and fail processing. The +// _plat__RunCommand() function is used to call to ExecuteCommand() in the TPM +// code. This function does whatever processing is necessary to set up the +// platform in anticipation of the call to the TPM including settup for error +// processing. +// +// The _plat__Fail() function is called when there is a failure in the TPM. The +// TPM code will have set the flag to indicate that the TPM is in failure mode. +// This call will then recursively call ExecuteCommand in order to build the +// failure mode response. When ExecuteCommand() returns to _plat__Fail(), the +// platform will do some platform specif operation to return to the environment +// in which the TPM is executing. For a simulator, setjmp/longjmp is used. For +// an OS, a system exit to the OS would be appropriate. + +#include + +#include "CompilerDependencies.h" +#include "ExecCommand_fp.h" +#include "Manufacture_fp.h" +#include "Platform.h" +#include "Platform_fp.h" +#include "_TPM_Init_fp.h" + +jmp_buf s_jumpBuffer; + +void _plat__RunCommand(uint32_t requestSize, unsigned char *request, + uint32_t *responseSize, unsigned char **response) { + setjmp(s_jumpBuffer); + ExecuteCommand(requestSize, request, responseSize, response); +} + +_Noreturn void _plat__Fail(void) { longjmp(&s_jumpBuffer[0], 1); } + +void _plat__Reset(bool forceManufacture) { + // We ignore errors, as we don't care if the TPM has been Manufactured before. + if (forceManufacture) { + TPM_TearDown(); + } + TPM_Manufacture(0); + _plat__TimerReset(); + _TPM_Init(); +} diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.cproject b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.cproject deleted file mode 100644 index ab21e0abb..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.cproject +++ /dev/null @@ -1,311 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.mxproject b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.mxproject deleted file mode 100644 index c5963d689..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.mxproject +++ /dev/null @@ -1,14 +0,0 @@ -[PreviousGenFiles] -HeaderPath=D:/VS/brianTPM/Samples/Nucleo-TPM/L476RG/Inc -HeaderFiles=usb_device.h;usbd_conf.h;usbd_desc.h;usbd_cdc_if.h;stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h; -SourcePath=D:/VS/brianTPM/Samples/Nucleo-TPM/L476RG/Src -SourceFiles=usb_device.c;usbd_conf.c;usbd_desc.c;usbd_cdc_if.c;stm32l4xx_it.c;stm32l4xx_hal_msp.c;main.c; - -[PreviousLibFiles] -LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; - -[PreviousUsedTStudioFiles] -SourceFiles=..\Src\main.c;..\Src\usb_device.c;..\Src\usbd_conf.c;..\Src\usbd_desc.c;..\Src\usbd_cdc_if.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;../\Src/system_stm32l4xx.c;../Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;null;../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c; -HeaderPath=..\Drivers\STM32L4xx_HAL_Driver\Inc;..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;..\Middlewares\ST\STM32_USB_Device_Library\Core\Inc;..\Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Inc;..\Drivers\CMSIS\Device\ST\STM32L4xx\Include;..\Drivers\CMSIS\Include;..\Inc; -CDefines=__weak:__attribute__((weak));__packed:__attribute__((__packed__)); - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.project b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.project deleted file mode 100644 index faceb2549..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.project +++ /dev/null @@ -1,155 +0,0 @@ - - - Nucleo-L476RG - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?children? - ?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\|| - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc:/STM32100B-EVAL/Debug} - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - Inc/Platform - 2 - PARENT-1-PROJECT_LOC/Shared/Platform/include - - - Inc/TPMCmd - 2 - PARENT-3-PROJECT_LOC/TPMCmd/tpm/include - - - Inc/TPMDevice - 2 - PARENT-1-PROJECT_LOC/Shared/TPMDevice/include - - - Middlewares/Platform - 2 - PARENT-1-PROJECT_LOC/Shared/Platform/src - - - Middlewares/TPMCmd - 2 - PARENT-3-PROJECT_LOC/TPMCmd/tpm/src - - - Middlewares/TPMDevice - 2 - PARENT-1-PROJECT_LOC/Shared/TPMDevice/src - - - Src/syscalls.c - 1 - PARENT-1-PROJECT_LOC../Shared/syscalls.c - - - Middlewares/WolfCypt/aes.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/aes.c - - - Middlewares/WolfCypt/ecc.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/ecc.c - - - Middlewares/WolfCypt/integer.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/integer.c - - - Middlewares/WolfCypt/memory.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/memory.c - - - Middlewares/WolfCypt/sha.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/sha.c - - - Middlewares/WolfCypt/sha256.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/sha256.c - - - Middlewares/WolfCypt/sha512.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/sha512.c - - - Middlewares/WolfCypt/tfm.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/tfm.c - - - Middlewares/WolfCypt/wolfmath.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/wolfmath.c - - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.settings/com.atollic.truestudio.debug.hardware_device.prefs deleted file mode 100644 index f3ef444e7..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.settings/com.atollic.truestudio.debug.hardware_device.prefs +++ /dev/null @@ -1,11 +0,0 @@ -BOARD=None -CODE_LOCATION=FLASH -ENDIAN=Little-endian -MCU=STM32L476RG -MCU_VENDOR=STMicroelectronics -MODEL=Lite -PROBE=ST-LINK -PROJECT_FORMAT_VERSION=2 -TARGET=ARM\u00AE -VERSION=4.1.0 -eclipse.preferences.version=1 diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.settings/language.settings.xml b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.settings/language.settings.xml deleted file mode 100644 index 175a20393..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.settings/language.settings.xml +++ /dev/null @@ -1,20 +0,0 @@ - - - - - - - - - - - - - - - - - - - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.settings/org.eclipse.cdt.managedbuilder.core.prefs deleted file mode 100644 index 66eb6736f..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/.settings/org.eclipse.cdt.managedbuilder.core.prefs +++ /dev/null @@ -1,11 +0,0 @@ -eclipse.preferences.version=1 -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/CPATH/delimiter=; -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/CPATH/operation=remove -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/C_INCLUDE_PATH/delimiter=; -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/C_INCLUDE_PATH/operation=remove -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/append=true -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/appendContributed=true -environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/LIBRARY_PATH/delimiter=; -environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/LIBRARY_PATH/operation=remove -environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/append=true -environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/appendContributed=true diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h deleted file mode 100644 index 5e8e62d7e..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h +++ /dev/null @@ -1,18537 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l476xx.h - * @author MCD Application Team - * @brief CMSIS STM32L476xx Device Peripheral Access Layer Header File. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS_Device - * @{ - */ - -/** @addtogroup stm32l476xx - * @{ - */ - -#ifndef __STM32L476xx_H -#define __STM32L476xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32L4XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum -{ -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */ - TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ - TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ - TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ - DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */ - DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */ - DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */ - COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ - LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ - DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ - LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ - QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */ - SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */ - SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */ - TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ - LCD_IRQn = 78, /*!< LCD global interrupt */ - RNG_IRQn = 80, /*!< RNG global interrupt */ - FPU_IRQn = 81 /*!< FPU global interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_stm32l4xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ - __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ - __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ - __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, 0x1C */ - __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ - __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ - __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ - uint32_t RESERVED2; /*!< Reserved, 0x2C */ - __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ - __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ - uint32_t RESERVED3; /*!< Reserved, 0x44 */ - uint32_t RESERVED4; /*!< Reserved, 0x48 */ - __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ - uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ - __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ - __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ - __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ - __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ - uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ - __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ - __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ - __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ - __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ - uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ - __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ - __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ - uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ - uint32_t RESERVED9; /*!< Reserved, 0x0AC */ - __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ - -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ - __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ - __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ - __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ - __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ - __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ - __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ -} DAC_TypeDef; - -/** - * @brief DFSDM module registers - */ -typedef struct -{ - __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ - __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ - __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ - __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ - __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ - __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ - __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ - __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ - __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ - __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ - __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ - __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ - __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ - __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ - __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ -} DFSDM_Filter_TypeDef; - -/** - * @brief DFSDM channel configuration registers - */ -typedef struct -{ - __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ - __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ - __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and - short circuit detector register, Address offset: 0x08 */ - __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ - __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ -} DFSDM_Channel_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ - __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ -} DBGMCU_TypeDef; - - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register */ -} DMA_Request_TypeDef; - -/* Legacy define */ -#define DMA_request_TypeDef DMA_Request_TypeDef - - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ - __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ - __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ - __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ - __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ - __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ - __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ - __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ - __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ - __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ - __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ -} EXTI_TypeDef; - - -/** - * @brief Firewall - */ - -typedef struct -{ - __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ - __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ - __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ - __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ - __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ - __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ - uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ - __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ -} FIREWALL_TypeDef; - - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ - __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ - __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ - __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ - __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ - __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ - __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ - __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ - uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */ - __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ - __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ - __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ - __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ -} FLASH_TypeDef; - - -/** - * @brief Flexible Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FMC_Bank1_TypeDef; - -/** - * @brief Flexible Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FMC_Bank1E_TypeDef; - -/** - * @brief Flexible Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ - __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ - __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ - __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ -} FMC_Bank3_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - __IO uint32_t ASCR; /*!< GPIO analog switch control register, Address offset: 0x2C */ - -} GPIO_TypeDef; - - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ - __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ - __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ - __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ - __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ - __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ - __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ - __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ - __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ -} IWDG_TypeDef; - -/** - * @brief LCD - */ - -typedef struct -{ - __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ - __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ - __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ - __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ -} LCD_TypeDef; - -/** - * @brief LPTIMER - */ -typedef struct -{ - __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ - __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ - __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ - __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ - __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ - __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ -} LPTIM_TypeDef; - -/** - * @brief Operational Amplifier (OPAMP) - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ - __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ - __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ -} OPAMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ -} OPAMP_Common_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ - __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ - __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ - __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ - __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ - __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ - __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ - __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ - __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ - __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ - __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ - __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ - __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ - __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ - __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ - __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ - __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ - __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ - __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ - __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ - __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ -} PWR_TypeDef; - - -/** - * @brief QUAD Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ - __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ - __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ - __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ - __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ - __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ - __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ - __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ - __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ - __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ - __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ -} QUADSPI_TypeDef; - - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ - __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */ - __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */ - __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ - __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ - __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ - uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ - __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ - __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ - __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ - __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ - __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ - __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ - __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ - uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ - __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ - __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ - __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ - uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ - __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ - uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ - __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - uint32_t reserved; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ - __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ - __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ - __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ - __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ - __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ - __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ - __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ - __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ - __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ - __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ - __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ - __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ -} RTC_TypeDef; - - -/** - * @brief Serial Audio Interface - */ - -typedef struct -{ - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ -} SAI_TypeDef; - -typedef struct -{ - __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ - __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ - __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ - __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ - __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ - __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ -} SAI_Block_TypeDef; - - -/** - * @brief Secure digital input/output Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ -} SDMMC_TypeDef; - - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ - __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ - __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ - __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ - __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ -} SPI_TypeDef; - - -/** - * @brief Single Wire Protocol Master Interface SPWMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ - __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ - uint32_t RESERVED1; /*!< Reserved, 0x08 */ - __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ - __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ - __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ - __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ - __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ - __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ -} SWPMI_TypeDef; - - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ - __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ - __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ -} SYSCFG_TypeDef; - - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ - __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ - __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ - __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ - __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ - __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ -} TIM_TypeDef; - - -/** - * @brief Touch Sensing Controller (TSC) - */ - -typedef struct -{ - __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ - __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ - __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ - __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ - __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ - __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ - __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ -} TSC_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ - __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ - __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ - __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ -} USART_TypeDef; - -/** - * @brief VREFBUF - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ - __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ -} VREFBUF_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @brief USB_OTG_Core_register - */ -typedef struct -{ - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/ - __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - uint32_t Reserved30[2]; /* Reserved 030h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ - __IO uint32_t GHWCFG1; /* User HW config1 044h*/ - __IO uint32_t GHWCFG2; /* User HW config2 048h*/ - __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/ - uint32_t Reserved6; /* Reserved 050h*/ - __IO uint32_t GLPMCFG; /* LPM Register 054h*/ - __IO uint32_t GPWRDN; /* Power Down Register 058h*/ - __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/ - __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/ - uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */ -} USB_OTG_GlobalTypeDef; - -/** - * @brief USB_OTG_device_Registers - */ -typedef struct -{ - __IO uint32_t DCFG; /* dev Configuration Register 800h*/ - __IO uint32_t DCTL; /* dev Control Register 804h*/ - __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ - uint32_t Reserved0C; /* Reserved 80Ch*/ - __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ - __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ - __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ - __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ - __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ - __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ - __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ - __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ - __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ - uint32_t Reserved40; /* dedicated EP mask 840h*/ - __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ - uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ -} USB_OTG_DeviceTypeDef; - -/** - * @brief USB_OTG_IN_Endpoint-Specific_Register - */ -typedef struct -{ - __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ - __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ - __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ - __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ - uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ -} USB_OTG_INEndpointTypeDef; - -/** - * @brief USB_OTG_OUT_Endpoint-Specific_Registers - */ -typedef struct -{ - __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ - __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ - __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ - uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ -} USB_OTG_OUTEndpointTypeDef; - -/** - * @brief USB_OTG_Host_Mode_Register_Structures - */ -typedef struct -{ - __IO uint32_t HCFG; /* Host Configuration Register 400h*/ - __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /* Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ -} USB_OTG_HostTypeDef; - -/** - * @brief USB_OTG_Host_Channel_Specific_Registers - */ -typedef struct -{ - __IO uint32_t HCCHAR; - __IO uint32_t HCSPLT; - __IO uint32_t HCINT; - __IO uint32_t HCINTMSK; - __IO uint32_t HCTSIZ; - __IO uint32_t HCDMA; - uint32_t Reserved[2]; -} USB_OTG_HostChannelTypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */ -#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 96 KB) base address */ -#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(32 KB) base address */ -#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ -#define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */ -#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */ - -#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */ -#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ - -/* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE - -#define SRAM1_SIZE_MAX ((uint32_t)0x00018000U) /*!< maximum SRAM1 size (up to 96 KBytes) */ -#define SRAM2_SIZE ((uint32_t)0x00008000U) /*!< SRAM2 size (32 KBytes) */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) - -#define FMC_BANK1 FMC_BASE -#define FMC_BANK1_1 FMC_BANK1 -#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U) -#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U) -#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U) -#define FMC_BANK3 (FMC_BASE + 0x20000000U) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) -#define LCD_BASE (APB1PERIPH_BASE + 0x2400U) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) -#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) -#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) -#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) -#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) - - -/*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) -#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) -#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) -#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) -#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) -#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400U) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800U) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U) -#define SAI2_Block_A_BASE (SAI2_BASE + 0x004) -#define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U) -#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) -#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) -#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) -#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60) -#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80) -#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0) -#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0) -#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0) -#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100) -#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180) -#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200) -#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) - -/*!< AHB1 peripherals */ -#define DMA1_BASE (AHB1PERIPH_BASE) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) -#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) -#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) - - -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) - - -#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) -#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) -#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) -#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) - - -/*!< AHB2 peripherals */ -#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) -#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) -#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) -#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) -#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) -#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U) -#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U) -#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) - -#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U) - -#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) -#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U) -#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U) -#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) - - -#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) - - -/*!< FMC Banks registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) - -/* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t)0xE0042000U) - -/*!< USB registers base address */ -#define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U) - -#define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U) -#define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U) -#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U) -#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U) -#define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_HOST_BASE ((uint32_t)0x00000400U) -#define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U) -#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U) -#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U) -#define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U) -#define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U) - - -#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ -#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define LCD ((LCD_TypeDef *) LCD_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN ((CAN_TypeDef *) CAN1_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC1_BASE) -#define DAC1 ((DAC_TypeDef *) DAC1_BASE) -#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) -#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) -#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) -#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE) -#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) -#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) -#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) -#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) - -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) -#define COMP1 ((COMP_TypeDef *) COMP1_BASE) -#define COMP2 ((COMP_TypeDef *) COMP2_BASE) -#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) -#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define TIM15 ((TIM_TypeDef *) TIM15_BASE) -#define TIM16 ((TIM_TypeDef *) TIM16_BASE) -#define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define SAI1 ((SAI_TypeDef *) SAI1_BASE) -#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) -#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) -#define SAI2 ((SAI_TypeDef *) SAI2_BASE) -#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) -#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) -#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) -#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) -#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) -#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) -#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) -#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) -#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) -#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) -#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) -#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) -#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) -#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) -/* Aliases to keep compatibility after DFSDM renaming */ -#define DFSDM_Channel0 DFSDM1_Channel0 -#define DFSDM_Channel1 DFSDM1_Channel1 -#define DFSDM_Channel2 DFSDM1_Channel2 -#define DFSDM_Channel3 DFSDM1_Channel3 -#define DFSDM_Channel4 DFSDM1_Channel4 -#define DFSDM_Channel5 DFSDM1_Channel5 -#define DFSDM_Channel6 DFSDM1_Channel6 -#define DFSDM_Channel7 DFSDM1_Channel7 -#define DFSDM_Filter0 DFSDM1_Filter0 -#define DFSDM_Filter1 DFSDM1_Filter1 -#define DFSDM_Filter2 DFSDM1_Filter2 -#define DFSDM_Filter3 DFSDM1_Filter3 -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define TSC ((TSC_TypeDef *) TSC_BASE) - -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) - - -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE) - - -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) -#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) -#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE) - - -#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) -#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) -#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) - -#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) - -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - -/** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ - -/* - * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) - */ -#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ - -/******************** Bit definition for ADC_ISR register *******************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ -#define ADC_ISR_EOSMP_Pos (1U) -#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ -#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC_Pos (2U) -#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ -#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS_Pos (3U) -#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ -#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR_Pos (4U) -#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ -#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ -#define ADC_ISR_JEOC_Pos (5U) -#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ -#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ -#define ADC_ISR_JEOS_Pos (6U) -#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ -#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_ISR_AWD1_Pos (7U) -#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ -#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) -#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ -#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) -#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ -#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ -#define ADC_ISR_JQOVF_Pos (10U) -#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ -#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ - -/******************** Bit definition for ADC_IER register *******************/ -#define ADC_IER_ADRDYIE_Pos (0U) -#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ -#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE_Pos (1U) -#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ -#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE_Pos (2U) -#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ -#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE_Pos (3U) -#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ -#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE_Pos (4U) -#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ -#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ -#define ADC_IER_JEOCIE_Pos (5U) -#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ -#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ -#define ADC_IER_JEOSIE_Pos (6U) -#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ -#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_IER_AWD1IE_Pos (7U) -#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ -#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_IER_AWD2IE_Pos (8U) -#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ -#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ -#define ADC_IER_AWD3IE_Pos (9U) -#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ -#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ -#define ADC_IER_JQOVFIE_Pos (10U) -#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ -#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ - -/* Legacy defines */ -#define ADC_IER_ADRDY (ADC_IER_ADRDYIE) -#define ADC_IER_EOSMP (ADC_IER_EOSMPIE) -#define ADC_IER_EOC (ADC_IER_EOCIE) -#define ADC_IER_EOS (ADC_IER_EOSIE) -#define ADC_IER_OVR (ADC_IER_OVRIE) -#define ADC_IER_JEOC (ADC_IER_JEOCIE) -#define ADC_IER_JEOS (ADC_IER_JEOSIE) -#define ADC_IER_AWD1 (ADC_IER_AWD1IE) -#define ADC_IER_AWD2 (ADC_IER_AWD2IE) -#define ADC_IER_AWD3 (ADC_IER_AWD3IE) -#define ADC_IER_JQOVF (ADC_IER_JQOVFIE) - -/******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) -#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ -#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ -#define ADC_CR_ADDIS_Pos (1U) -#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ -#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ -#define ADC_CR_ADSTART_Pos (2U) -#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ -#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR_JADSTART_Pos (3U) -#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ -#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR_ADSTP_Pos (4U) -#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ -#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ -#define ADC_CR_JADSTP_Pos (5U) -#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ -#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ -#define ADC_CR_ADVREGEN_Pos (28U) -#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ -#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ -#define ADC_CR_DEEPPWD_Pos (29U) -#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ -#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ -#define ADC_CR_ADCALDIF_Pos (30U) -#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ -#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ -#define ADC_CR_ADCAL_Pos (31U) -#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ -#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ - -/******************** Bit definition for ADC_CFGR register ******************/ -#define ADC_CFGR_DMAEN_Pos (0U) -#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ -#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ -#define ADC_CFGR_DMACFG_Pos (1U) -#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ -#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ - -#define ADC_CFGR_RES_Pos (3U) -#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ -#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ - -#define ADC_CFGR_ALIGN_Pos (5U) -#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ - -#define ADC_CFGR_EXTSEL_Pos (6U) -#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ -#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ - -#define ADC_CFGR_EXTEN_Pos (10U) -#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ -#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ - -#define ADC_CFGR_OVRMOD_Pos (12U) -#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ -#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ -#define ADC_CFGR_CONT_Pos (13U) -#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ -#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR_AUTDLY_Pos (14U) -#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ -#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ - -#define ADC_CFGR_DISCEN_Pos (16U) -#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ -#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ - -#define ADC_CFGR_DISCNUM_Pos (17U) -#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ -#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ - -#define ADC_CFGR_JDISCEN_Pos (20U) -#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ -#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ -#define ADC_CFGR_JQM_Pos (21U) -#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ -#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ -#define ADC_CFGR_AWD1SGL_Pos (22U) -#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ -#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR_AWD1EN_Pos (23U) -#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ -#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR_JAWD1EN_Pos (24U) -#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ -#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CFGR_JAUTO_Pos (25U) -#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ -#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ - -#define ADC_CFGR_AWD1CH_Pos (26U) -#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ -#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ - -#define ADC_CFGR_JQDIS_Pos (31U) -#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ -#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ - -/******************** Bit definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_ROVSE_Pos (0U) -#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ -#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ -#define ADC_CFGR2_JOVSE_Pos (1U) -#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ -#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ - -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - -#define ADC_CFGR2_OVSS_Pos (5U) -#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ -#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ - -#define ADC_CFGR2_TROVS_Pos (9U) -#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ -#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ -#define ADC_CFGR2_ROVSM_Pos (10U) -#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ -#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ - -/******************** Bit definition for ADC_SMPR1 register *****************/ -#define ADC_SMPR1_SMP0_Pos (0U) -#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ -#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR1_SMP1_Pos (3U) -#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ -#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR1_SMP2_Pos (6U) -#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR1_SMP3_Pos (9U) -#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR1_SMP4_Pos (12U) -#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ -#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR1_SMP5_Pos (15U) -#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ -#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR1_SMP6_Pos (18U) -#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR1_SMP7_Pos (21U) -#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR1_SMP8_Pos (24U) -#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ -#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ - -#define ADC_SMPR1_SMP9_Pos (27U) -#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ -#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ - -/******************** Bit definition for ADC_SMPR2 register *****************/ -#define ADC_SMPR2_SMP10_Pos (0U) -#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ -#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR2_SMP11_Pos (3U) -#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ -#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR2_SMP12_Pos (6U) -#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR2_SMP13_Pos (9U) -#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR2_SMP14_Pos (12U) -#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ -#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR2_SMP15_Pos (15U) -#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ -#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR2_SMP16_Pos (18U) -#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR2_SMP17_Pos (21U) -#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR2_SMP18_Pos (24U) -#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ -#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ - -/******************** Bit definition for ADC_TR1 register *******************/ -#define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ -#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ - -#define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ -#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ - -/******************** Bit definition for ADC_TR2 register *******************/ -#define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ -#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ - -#define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ -#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ - -/******************** Bit definition for ADC_TR3 register *******************/ -#define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ -#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ - -#define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ -#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ - -/******************** Bit definition for ADC_SQR1 register ******************/ -#define ADC_SQR1_L_Pos (0U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ -#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ - -#define ADC_SQR1_SQ1_Pos (6U) -#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ -#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ - -#define ADC_SQR1_SQ2_Pos (12U) -#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ -#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ - -#define ADC_SQR1_SQ3_Pos (18U) -#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ -#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ - -#define ADC_SQR1_SQ4_Pos (24U) -#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ -#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR2 register ******************/ -#define ADC_SQR2_SQ5_Pos (0U) -#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ -#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ - -#define ADC_SQR2_SQ6_Pos (6U) -#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ -#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ - -#define ADC_SQR2_SQ7_Pos (12U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ -#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ - -#define ADC_SQR2_SQ8_Pos (18U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ -#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ - -#define ADC_SQR2_SQ9_Pos (24U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ -#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR3 register ******************/ -#define ADC_SQR3_SQ10_Pos (0U) -#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ -#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ - -#define ADC_SQR3_SQ11_Pos (6U) -#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ -#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ - -#define ADC_SQR3_SQ12_Pos (12U) -#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ -#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ - -#define ADC_SQR3_SQ13_Pos (18U) -#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ -#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ - -#define ADC_SQR3_SQ14_Pos (24U) -#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ -#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR4 register ******************/ -#define ADC_SQR4_SQ15_Pos (0U) -#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ -#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ - -#define ADC_SQR4_SQ16_Pos (6U) -#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ -#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_JSQR register ******************/ -#define ADC_JSQR_JL_Pos (0U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ -#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ - -#define ADC_JSQR_JEXTSEL_Pos (2U) -#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ -#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ - -#define ADC_JSQR_JEXTEN_Pos (6U) -#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ -#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ - -#define ADC_JSQR_JSQ1_Pos (8U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ -#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ - -#define ADC_JSQR_JSQ2_Pos (14U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ -#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ - -#define ADC_JSQR_JSQ3_Pos (20U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ -#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ - -#define ADC_JSQR_JSQ4_Pos (26U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ -#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for ADC_OFR1 register ******************/ -#define ADC_OFR1_OFFSET1_Pos (0U) -#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ -#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ -#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ - -#define ADC_OFR1_OFFSET1_CH_Pos (26U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ -#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ - -#define ADC_OFR1_OFFSET1_EN_Pos (31U) -#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ -#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ - -/******************** Bit definition for ADC_OFR2 register ******************/ -#define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ -#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ -#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ - -#define ADC_OFR2_OFFSET2_CH_Pos (26U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ -#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ - -#define ADC_OFR2_OFFSET2_EN_Pos (31U) -#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ -#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ - -/******************** Bit definition for ADC_OFR3 register ******************/ -#define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ -#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ -#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ - -#define ADC_OFR3_OFFSET3_CH_Pos (26U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ -#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ - -#define ADC_OFR3_OFFSET3_EN_Pos (31U) -#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ -#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ - -/******************** Bit definition for ADC_OFR4 register ******************/ -#define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ -#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ -#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ - -#define ADC_OFR4_OFFSET4_CH_Pos (26U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ -#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ - -#define ADC_OFR4_OFFSET4_EN_Pos (31U) -#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ -#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ - -/******************** Bit definition for ADC_JDR1 register ******************/ -#define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_JDR2 register ******************/ -#define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_JDR3 register ******************/ -#define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_JDR4 register ******************/ -#define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_AWD2CR register ****************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ -#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_AWD3CR register ****************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ -#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_DIFSEL register ****************/ -#define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ -#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_CALFACT register ***************/ -#define ADC_CALFACT_CALFACT_S_Pos (0U) -#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ -#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ - -#define ADC_CALFACT_CALFACT_D_Pos (16U) -#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ -#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ -#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ -#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ -#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ -#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ -#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ -#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ - -/************************* ADC Common registers *****************************/ -/******************** Bit definition for ADC_CSR register *******************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ - -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ - -/******************** Bit definition for ADC_CCR register *******************/ -#define ADC_CCR_DUAL_Pos (0U) -#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ -#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ -#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ -#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ -#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ -#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ -#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ - -#define ADC_CCR_DELAY_Pos (8U) -#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ -#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ -#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ -#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ -#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ -#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ - -#define ADC_CCR_DMACFG_Pos (13U) -#define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ -#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ - -#define ADC_CCR_MDMA_Pos (14U) -#define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ -#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ -#define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ -#define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ - -#define ADC_CCR_CKMODE_Pos (16U) -#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ -#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ -#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ - -#define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ -#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ -#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ - -#define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ -#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ -#define ADC_CCR_TSEN_Pos (23U) -#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ -#define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ -#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ - -/******************** Bit definition for ADC_CDR register *******************/ -#define ADC_CDR_RDATA_MST_Pos (0U) -#define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ -#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ -#define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ -#define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ -#define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ -#define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ -#define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ -#define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ -#define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ -#define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ -#define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ -#define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ -#define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ -#define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ -#define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ -#define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ -#define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ -#define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ - -#define ADC_CDR_RDATA_SLV_Pos (16U) -#define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ -#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ -#define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ -#define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ -#define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ -#define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ -#define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ - -/******************************************************************************/ -/* */ -/* Controller Area Network */ -/* */ -/******************************************************************************/ -/*!*/ -#define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ -#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ - -#define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ -#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ -#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ -#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx - * @{ - */ - -#ifndef __STM32L4xx_H -#define __STM32L4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L4) -#define STM32L4 -#endif /* STM32L4 */ - -/* Uncomment the line below according to the target STM32L4 device used in your - application - */ - -#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ - !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ - !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ - !defined (STM32L496xx) && !defined (STM32L4A6xx) && \ - !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) - /* #define STM32L431xx */ /*!< STM32L431xx Devices */ - /* #define STM32L432xx */ /*!< STM32L432xx Devices */ - /* #define STM32L433xx */ /*!< STM32L433xx Devices */ - /* #define STM32L442xx */ /*!< STM32L442xx Devices */ - /* #define STM32L443xx */ /*!< STM32L443xx Devices */ - /* #define STM32L451xx */ /*!< STM32L451xx Devices */ - /* #define STM32L452xx */ /*!< STM32L452xx Devices */ - /* #define STM32L462xx */ /*!< STM32L462xx Devices */ - /* #define STM32L471xx */ /*!< STM32L471xx Devices */ - /* #define STM32L475xx */ /*!< STM32L475xx Devices */ - /* #define STM32L476xx */ /*!< STM32L476xx Devices */ - /* #define STM32L485xx */ /*!< STM32L485xx Devices */ - /* #define STM32L486xx */ /*!< STM32L486xx Devices */ - /* #define STM32L496xx */ /*!< STM32L496xx Devices */ - /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ - /* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */ - /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */ - /* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */ - /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */ - /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */ - /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_HAL_DRIVER */ -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number - */ -#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ -#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L4_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L431xx) - #include "stm32l431xx.h" -#elif defined(STM32L432xx) - #include "stm32l432xx.h" -#elif defined(STM32L433xx) - #include "stm32l433xx.h" -#elif defined(STM32L442xx) - #include "stm32l442xx.h" -#elif defined(STM32L443xx) - #include "stm32l443xx.h" -#elif defined(STM32L451xx) - #include "stm32l451xx.h" -#elif defined(STM32L452xx) - #include "stm32l452xx.h" -#elif defined(STM32L462xx) - #include "stm32l462xx.h" -#elif defined(STM32L471xx) - #include "stm32l471xx.h" -#elif defined(STM32L475xx) - #include "stm32l475xx.h" -#elif defined(STM32L476xx) - #include "stm32l476xx.h" -#elif defined(STM32L485xx) - #include "stm32l485xx.h" -#elif defined(STM32L486xx) - #include "stm32l486xx.h" -#elif defined(STM32L496xx) - #include "stm32l496xx.h" -#elif defined(STM32L4A6xx) - #include "stm32l4a6xx.h" -#elif defined(STM32L4R5xx) - #include "stm32l4r5xx.h" -#elif defined(STM32L4R7xx) - #include "stm32l4r7xx.h" -#elif defined(STM32L4R9xx) - #include "stm32l4r9xx.h" -#elif defined(STM32L4S5xx) - #include "stm32l4s5xx.h" -#elif defined(STM32L4S7xx) - #include "stm32l4s7xx.h" -#elif defined(STM32L4S9xx) - #include "stm32l4s9xx.h" -#else - #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l4xx_hal.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L4xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h deleted file mode 100644 index e6e4376fd..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l4xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L4XX_H -#define __SYSTEM_STM32L4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L4xx_System_Exported_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/arm_common_tables.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index 8742a5699..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,136 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. October 2015 -* $Revision: V.1.4.5 a -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -/* extern const q31_t realCoefAQ31[1024]; */ -/* extern const q31_t realCoefBQ31[1024]; */ -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/arm_const_structs.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/arm_const_structs.h deleted file mode 100644 index 726d06eb6..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/arm_const_structs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.h -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/arm_math.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/arm_math.h deleted file mode 100644 index d33f8a9b3..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7154 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2015 ARM Limited. All rights reserved. -* -* $Date: 20. October 2015 -* $Revision: V1.4.5 b -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) - * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __GNUC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __ICCARM__ - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - -#elif defined __CSMC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - -#elif defined __TASKING__ - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - -/* - #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) - #define __CLZ __clz - #endif - */ -/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) - static __INLINE uint32_t __CLZ( - q31_t data); - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - } -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - } - - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - } -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE int32_t __QADD( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE int32_t __QSUB( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SXTB16( - uint32_t x) - { - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; - - - /** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - - /** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - - /** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - - /** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - - /** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f32; - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; - - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - - /** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - } - } - - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } - } - - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } - } - - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - float32_t arm_sin_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q31_t arm_sin_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q15_t arm_sin_q15( - q15_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - float32_t arm_cos_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q31_t arm_cos_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in >= 0.0f) - { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - /** - * @brief floating-point Circular write function. - */ - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q15 Circular write function. - */ - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - - /** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - - /** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - - /** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - } - - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); - } - - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); - } - - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); - } - - /** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__CSMC__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__TASKING__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/cmsis_armcc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/cmsis_armcc.h deleted file mode 100644 index 74c49c67d..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/cmsis_armcc.h +++ /dev/null @@ -1,734 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/cmsis_armcc_V6.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/cmsis_armcc_V6.h deleted file mode 100644 index cd13240ce..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/cmsis_armcc_V6.h +++ /dev/null @@ -1,1800 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc_V6.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_V6_H -#define __CMSIS_ARMCC_V6_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get IPSR Register (non-secure) - \details Returns the content of the non-secure IPSR Register when in secure state. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get APSR Register (non-secure) - \details Returns the content of the non-secure APSR Register when in secure state. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get xPSR Register (non-secure) - \details Returns the content of the non-secure xPSR Register when in secure state. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority with condition (non_secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - - -#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ - -/** - \brief Get FPSCR - \details eturns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#define __get_FPSCR __builtin_arm_get_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get FPSCR (non-secure) - \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#define __set_FPSCR __builtin_arm_set_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set FPSCR (non-secure) - \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __builtin_bswap32 - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -/*#define __SSAT __builtin_arm_ssat*/ -#define __SSAT(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat -#if 0 -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) -#endif - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1U) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/cmsis_gcc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/cmsis_gcc.h deleted file mode 100644 index bb89fbba9..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/cmsis_gcc.h +++ /dev/null @@ -1,1373 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* __CMSIS_GCC_H */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm0.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm0.h deleted file mode 100644 index 711dad551..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,798 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm0plus.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index b04aa3905..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,914 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm3.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm3.h deleted file mode 100644 index b4ac4c7b0..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1763 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm4.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm4.h deleted file mode 100644 index dc840ebf2..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1937 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm7.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm7.h deleted file mode 100644 index 3b7530ad5..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2512 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & 0x00000FF0UL) == 0x220UL) - { - return 2UL; /* Double + Single precision FPU */ - } - else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) - { - return 1UL; /* Single precision FPU */ - } - else - { - return 0UL; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cmFunc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 652a48af0..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cmInstr.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index f474b0e6f..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cmSimd.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cmSimd.h deleted file mode 100644 index 66bf5c2a7..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_cmSimd.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_sc000.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_sc000.h deleted file mode 100644 index 514dbd81b..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,926 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_sc300.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_sc300.h deleted file mode 100644 index 8bd18aa31..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1745 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h deleted file mode 100644 index 0ae9d0b24..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ /dev/null @@ -1,3309 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_hal_legacy.h - * @author MCD Application Team - * @brief This file contains aliases definition for the STM32Cube HAL constants - * macros and functions maintained for legacy purpose. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_HAL_LEGACY -#define __STM32_HAL_LEGACY - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose - * @{ - */ -#define AES_FLAG_RDERR CRYP_FLAG_RDERR -#define AES_FLAG_WRERR CRYP_FLAG_WRERR -#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF -#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR -#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - -/** - * @} - */ - -/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose - * @{ - */ -#define ADC_RESOLUTION12b ADC_RESOLUTION_12B -#define ADC_RESOLUTION10b ADC_RESOLUTION_10B -#define ADC_RESOLUTION8b ADC_RESOLUTION_8B -#define ADC_RESOLUTION6b ADC_RESOLUTION_6B -#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN -#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED -#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV -#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV -#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV -#define REGULAR_GROUP ADC_REGULAR_GROUP -#define INJECTED_GROUP ADC_INJECTED_GROUP -#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP -#define AWD_EVENT ADC_AWD_EVENT -#define AWD1_EVENT ADC_AWD1_EVENT -#define AWD2_EVENT ADC_AWD2_EVENT -#define AWD3_EVENT ADC_AWD3_EVENT -#define OVR_EVENT ADC_OVR_EVENT -#define JQOVF_EVENT ADC_JQOVF_EVENT -#define ALL_CHANNELS ADC_ALL_CHANNELS -#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS -#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS -#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR -#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 -#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 -#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 -#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO -#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 -#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 -#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE -#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING -#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING -#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING -#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 - -#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY -#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY -#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC -#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC -#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL -#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 -/** - * @} - */ - -/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose - * @{ - */ -#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE -#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE -#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 -#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 -#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 -#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 -#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 -#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 -#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ -#endif -#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR -#if defined(STM32F373xC) || defined(STM32F378xx) -#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 -#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR -#endif /* STM32F373xC || STM32F378xx */ - -#if defined(STM32L0) || defined(STM32L4) -#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON - -#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 -#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 -#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 -#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 -#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 -#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - -#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT -#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT -#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT -#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT -#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 -#if defined(STM32L0) -/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ -/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ -/* to the second dedicated IO (only for COMP2). */ -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 -#else -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 -#endif -#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 -#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 - -#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW -#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH - -/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ -/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ -#if defined(COMP_CSR_LOCK) -#define COMP_FLAG_LOCK COMP_CSR_LOCK -#elif defined(COMP_CSR_COMP1LOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK -#elif defined(COMP_CSR_COMPxLOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK -#endif - -#if defined(STM32L4) -#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 -#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 -#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 -#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 -#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE -#endif - -#if defined(STM32L0) -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER -#else -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED -#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER -#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER -#endif - -#endif -/** - * @} - */ - -/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose - * @{ - */ -#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig -/** - * @} - */ - -/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE -#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define DAC1_CHANNEL_1 DAC_CHANNEL_1 -#define DAC1_CHANNEL_2 DAC_CHANNEL_2 -#define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE 0x00000000U -#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 -#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 -#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE -#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE -#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE - -/** - * @} - */ - -/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP -#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE -#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - - - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD -#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD -#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS -#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES -#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES -#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE -#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE -#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE -#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE -#define OBEX_PCROP OPTIONBYTE_PCROP -#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG -#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE -#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE -#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE -#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD -#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD -#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE -#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD -#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD -#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE -#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD -#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -#define PAGESIZE FLASH_PAGE_SIZE -#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD -#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 -#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 -#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 -#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 -#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST -#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST -#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA -#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB -#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA -#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB -#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE -#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN -#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE -#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN -#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE -#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD -#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP -#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV -#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR -#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA -#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS -#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST -#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR -#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO -#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS -#define OB_WDG_SW OB_IWDG_SW -#define OB_WDG_HW OB_IWDG_HW -#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET -#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET -#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET -#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET -#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR -#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 -#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 -#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 - -/** - * @} - */ - -/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose - * @{ - */ - -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 -#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 -#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 -/** - * @} - */ - - -/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose - * @{ - */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) -#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE -#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE -#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 -#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 -#else -#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE -#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE -#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 -#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 -#endif -/** - * @} - */ - -/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef -#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef -/** - * @} - */ - -/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose - * @{ - */ -#define GET_GPIO_SOURCE GPIO_GET_INDEX -#define GET_GPIO_INDEX GPIO_GET_INDEX - -#if defined(STM32F4) -#define GPIO_AF12_SDMMC GPIO_AF12_SDIO -#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO -#endif - -#if defined(STM32F7) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32L4) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 -#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 -#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 - -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ - -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L1 */ - -#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH -#endif /* STM32F0 || STM32F3 || STM32F1 */ - -#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose - * @{ - */ - -#if defined(STM32H7) - #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE - #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE - #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET - #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET - #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE - #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE - - #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 - #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 - - #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX - #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX - - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT - #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 - #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO - - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT - #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT - #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 - #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 - #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT - #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT - #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT - #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT - #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT - #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT - - #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT - #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING - #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING - #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - - -#endif /* STM32H7 */ - - -/** - * @} - */ - - -/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - -#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER -#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER -#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD -#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD -#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER -#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER -#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE -#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE -#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE -#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE -#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE -#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE -#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE -#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE -#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) -#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX -#endif -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose - * @{ - */ -#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE -#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define KR_KEY_RELOAD IWDG_KEY_RELOAD -#define KR_KEY_ENABLE IWDG_KEY_ENABLE -#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE -#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE -/** - * @} - */ - -/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose - * @{ - */ - -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION -#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS - -#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING -#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING -#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING - -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION -#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/* The following 3 definition have also been present in a temporary version of lptim.h */ -/* They need to be renamed also to the right name, just in case */ -#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/** - * @} - */ - -/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b -#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b -#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b -#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b - -#define NAND_AddressTypedef NAND_AddressTypeDef - -#define __ARRAY_ADDRESS ARRAY_ADDRESS -#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE -#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE -#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE -#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE -/** - * @} - */ - -/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose - * @{ - */ -#define NOR_StatusTypedef HAL_NOR_StatusTypeDef -#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS -#define NOR_ONGOING HAL_NOR_STATUS_ONGOING -#define NOR_ERROR HAL_NOR_STATUS_ERROR -#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT - -#define __NOR_WRITE NOR_WRITE -#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT -/** - * @} - */ - -/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose - * @{ - */ - -#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 -#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 -#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 -#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - -#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 -#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 -#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 - -#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -#if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL -#endif -/** - * @} - */ - -/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose - * @{ - */ - -/* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD -#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA - -/* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD -#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD -#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD -#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD - -#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef -#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS -#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING -#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR -#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FORMAT_BIN RTC_FORMAT_BIN -#define FORMAT_BCD RTC_FORMAT_BCD - -#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE - -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT - -#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 - -#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE -#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 -#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 - -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 -#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 - -/** - * @} - */ - - -/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE -#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE - -#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE -#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE - -#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE -#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE - -#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE -#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE -/** - * @} - */ - - -/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE -#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE -#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE -#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE -#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE -#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE -#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE -#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE -#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE -#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE -#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose - * @{ - */ -#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE -#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE - -#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE -#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE - -#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE -#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose - * @{ - */ -#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK -#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - -#define TIM_DMABase_CR1 TIM_DMABASE_CR1 -#define TIM_DMABase_CR2 TIM_DMABASE_CR2 -#define TIM_DMABase_SMCR TIM_DMABASE_SMCR -#define TIM_DMABase_DIER TIM_DMABASE_DIER -#define TIM_DMABase_SR TIM_DMABASE_SR -#define TIM_DMABase_EGR TIM_DMABASE_EGR -#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 -#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 -#define TIM_DMABase_CCER TIM_DMABASE_CCER -#define TIM_DMABase_CNT TIM_DMABASE_CNT -#define TIM_DMABase_PSC TIM_DMABASE_PSC -#define TIM_DMABase_ARR TIM_DMABASE_ARR -#define TIM_DMABase_RCR TIM_DMABASE_RCR -#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 -#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 -#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 -#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 -#define TIM_DMABase_BDTR TIM_DMABASE_BDTR -#define TIM_DMABase_DCR TIM_DMABASE_DCR -#define TIM_DMABase_DMAR TIM_DMABASE_DMAR -#define TIM_DMABase_OR1 TIM_DMABASE_OR1 -#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 -#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 -#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 -#define TIM_DMABase_OR2 TIM_DMABASE_OR2 -#define TIM_DMABase_OR3 TIM_DMABASE_OR3 -#define TIM_DMABase_OR TIM_DMABASE_OR - -#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE -#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 -#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 -#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 -#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 -#define TIM_EventSource_COM TIM_EVENTSOURCE_COM -#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER -#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK -#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 - -#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER -#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS -#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS -#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS -#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS -#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS -#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS -#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS -#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS -#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS -#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS -#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS -#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS -#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS -#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS -#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS -#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS -#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS - -/** - * @} - */ - -/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose - * @{ - */ -#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING -#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose - * @{ - */ -#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE -#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE - -#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE -#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE - -#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 -#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 -#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 -#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 - -#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 -#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 -#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 -#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 - -#define __DIV_LPUART UART_DIV_LPUART - -#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE -#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose - * @{ - */ - -#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE -#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE - -#define USARTNACK_ENABLED USART_NACK_ENABLE -#define USARTNACK_DISABLED USART_NACK_DISABLE -/** - * @} - */ - -/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define CFR_BASE WWDG_CFR_BASE - -/** - * @} - */ - -/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose - * @{ - */ -#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 -#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME -#define INAK_TIMEOUT CAN_TIMEOUT_VALUE -#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE -#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) -#define CAN_TXSTATUS_OK ((uint8_t)0x01U) -#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) - -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define VLAN_TAG ETH_VLAN_TAG -#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD -#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD -#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD -#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK -#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK -#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK -#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK - -#define ETH_MMCCR 0x00000100U -#define ETH_MMCRIR 0x00000104U -#define ETH_MMCTIR 0x00000108U -#define ETH_MMCRIMR 0x0000010CU -#define ETH_MMCTIMR 0x00000110U -#define ETH_MMCTGFSCCR 0x0000014CU -#define ETH_MMCTGFMSCCR 0x00000150U -#define ETH_MMCTGFCR 0x00000168U -#define ETH_MMCRFCECR 0x00000194U -#define ETH_MMCRFAECR 0x00000198U -#define ETH_MMCRGUFCR 0x000001C4U - -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ -#if defined(STM32F1) -#else -#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ -#endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ - -/** - * @} - */ - -/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR -#define DCMI_IT_OVF DCMI_IT_OVR -#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI -#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI - -#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop -#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop -#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop - -/** - * @} - */ - -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose - * @{ - */ -#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 -#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 -#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 - -#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 -#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 -#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 -/** - * @} - */ -#endif /* STM32L4 || STM32F7*/ - -/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback -/** - * @} - */ - -/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef -#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef -#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish -#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish -#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish -#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish - -/*HASH Algorithm Selection*/ - -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 -#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 -#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 -#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 - -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH -#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC - -#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY -#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY -/** - * @} - */ - -/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode -#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode -#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode -#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode -#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode -#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) -#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect -#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) -#if defined(STM32L0) -#else -#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) -#endif -#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram -#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown -#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown -#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock -#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock -#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase -#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - - /** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter -#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter -#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter -#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter - -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) - /** - * @} - */ - -/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose - * @{ - */ -#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD -#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg -#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown -#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor -#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg -#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown -#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor -#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler -#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD -#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler -#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback -#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive -#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive -#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC -#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC -#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - -#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL -#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING -#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING -#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING -#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING -#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING -#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING - -#define CR_OFFSET_BB PWR_CR_OFFSET_BB -#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB -#define PMODE_BIT_NUMBER VOS_BIT_NUMBER -#define CR_PMODE_BB CR_VOS_BB - -#define DBP_BitNumber DBP_BIT_NUMBER -#define PVDE_BitNumber PVDE_BIT_NUMBER -#define PMODE_BitNumber PMODE_BIT_NUMBER -#define EWUP_BitNumber EWUP_BIT_NUMBER -#define FPDS_BitNumber FPDS_BIT_NUMBER -#define ODEN_BitNumber ODEN_BIT_NUMBER -#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER -#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER -#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER -#define BRE_BitNumber BRE_BIT_NUMBER - -#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - - /** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt -#define HAL_TIM_DMAError TIM_DMAError -#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt -#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback -#define HAL_LTDC_Relaod HAL_LTDC_Reload -#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig -#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig -/** - * @} - */ - - -/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported macros ------------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose - * @{ - */ -#define AES_IT_CC CRYP_IT_CC -#define AES_IT_ERR CRYP_IT_ERR -#define AES_FLAG_CCF CRYP_FLAG_CCF -/** - * @} - */ - -/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE -#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH -#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH -#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM -#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM -#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC -#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI -#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK -#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG -#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG -#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE -#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE -#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE - -#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY -#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 -#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS -#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER -#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER - -/** - * @} - */ - - -/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __ADC_ENABLE __HAL_ADC_ENABLE -#define __ADC_DISABLE __HAL_ADC_DISABLE -#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS -#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS -#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE -#define __ADC_IS_ENABLED ADC_IS_ENABLE -#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR -#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR -#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING -#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE - -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION -#define __HAL_ADC_JSQR_RK ADC_JSQR_RK -#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT -#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR -#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION -#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE -#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS -#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM -#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT -#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS -#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN -#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ -#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET -#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET -#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL -#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL -#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET -#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET -#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD - -#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION -#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER -#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI -#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER -#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER -#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE - -#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT -#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT -#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL -#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM -#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET -#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE -#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE -#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER - -#define __HAL_ADC_SQR1 ADC_SQR1 -#define __HAL_ADC_SMPR1 ADC_SMPR1 -#define __HAL_ADC_SMPR2 ADC_SMPR2 -#define __HAL_ADC_SQR3_RK ADC_SQR3_RK -#define __HAL_ADC_SQR2_RK ADC_SQR2_RK -#define __HAL_ADC_SQR1_RK ADC_SQR1_RK -#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS -#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS -#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV -#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection -#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_JSQR ADC_JSQR - -#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL -#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF -#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT -#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS -#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN -#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR -#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT -#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT -#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT -#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE - -/** - * @} - */ - -/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 -#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 -#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 -#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 -#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 -#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 -#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 -#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 -#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 -#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 -#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 -#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 -#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 -#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 -#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 -#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 - -#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 -#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 -#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 -#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 -#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 -#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 -#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 -#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 -#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 -#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 -#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 -#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 -#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 -#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 - - -#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 -#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 -#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 -#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 -#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 -#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 -#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC -#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC -#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG -#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG -#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG -#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG -#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT -#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT -#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT -#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT -#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT -#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT -#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 -#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 -#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 -#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 -#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 -#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32F3) -#define COMP_START __HAL_COMP_ENABLE -#define COMP_STOP __HAL_COMP_DISABLE -#define COMP_LOCK __HAL_COMP_LOCK - -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP7_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif -#else -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -#endif - -#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE - -#if defined(STM32L0) || defined(STM32L4) -/* Note: On these STM32 families, the only argument of this macro */ -/* is COMP_FLAG_LOCK. */ -/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ -/* argument. */ -#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) -#endif -/** - * @} - */ - -#if defined(STM32L0) || defined(STM32L4) -/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -/** - * @} - */ -#endif - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_WRPAREA IS_OB_WRPAREA -#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM -#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM -#define IS_TYPEERASE IS_FLASH_TYPEERASE -#define IS_NBSECTORS IS_FLASH_NBSECTORS -#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE - -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 -#define __HAL_I2C_GENERATE_START I2C_GENERATE_START -#if defined(STM32F1) -#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE -#else -#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE -#endif /* STM32F1 */ -#define __HAL_I2C_RISE_TIME I2C_RISE_TIME -#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD -#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST -#define __HAL_I2C_SPEED I2C_SPEED -#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE -#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ -#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS -#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE -#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ -#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB -#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB -#define __HAL_I2C_FREQRANGE I2C_FREQRANGE -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE -#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT - -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __IRDA_DISABLE __HAL_IRDA_DISABLE -#define __IRDA_ENABLE __HAL_IRDA_ENABLE - -#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION - -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE - - -/** - * @} - */ - - -/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS -#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS -/** - * @} - */ - - -/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT -#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT -#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE - -/** - * @} - */ - - -/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose - * @{ - */ -#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD -#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX -#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX -#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX -#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX -#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L -#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H -#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM -#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES -#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX -#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT -#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION -#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET - -/** - * @} - */ - - -/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE -#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE -#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine -#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) -#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention -#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 -#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 -#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB -#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB - -#if defined (STM32F4) -#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() -#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() -#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() -#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() -#else -#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG -#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT -#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT -#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG -#endif /* STM32F4 */ -/** - * @} - */ - - -/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose - * @{ - */ - -#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI -#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI - -#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) - -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE -#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET -#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET -#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE -#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE -#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET -#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET -#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE -#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE -#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE -#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET -#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE -#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE -#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET -#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET -#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET -#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET -#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET -#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET -#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET -#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET -#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET -#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET -#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET -#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET -#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET -#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET -#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE -#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE -#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET -#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET -#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE -#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE -#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE -#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE -#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET -#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET -#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE -#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE -#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE -#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE -#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET -#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET -#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE -#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE -#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET -#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET -#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE -#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE -#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE -#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE -#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET -#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET -#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE -#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE -#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET -#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET -#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE -#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE -#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE -#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE -#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET -#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET -#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE -#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE -#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET -#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET -#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE -#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE -#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE -#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE -#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET -#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET -#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE -#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE -#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE -#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE -#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET -#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET -#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE -#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE -#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE -#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE -#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET -#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET -#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE -#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE -#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET -#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET -#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE -#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE -#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE -#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE -#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE -#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE -#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE -#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE -#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE -#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE -#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET -#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET -#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE -#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE -#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET -#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET -#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE -#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE -#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE -#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE -#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE -#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE -#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET -#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET -#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE -#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE -#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE -#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE -#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE -#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE -#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET -#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET -#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE -#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE -#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE -#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE -#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET -#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET -#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE -#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE -#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE -#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE -#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET -#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET -#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE -#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE -#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE -#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE -#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET -#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET -#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE -#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE -#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE -#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE -#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET -#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET -#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE -#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE -#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE -#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE -#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET -#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET -#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE -#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE -#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE -#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE -#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET -#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET -#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE -#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE -#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE -#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE -#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET -#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET -#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE -#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE -#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE -#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE -#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET -#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET -#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE -#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE -#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE -#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE -#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET -#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET -#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE -#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE -#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE -#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE -#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET -#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET -#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE -#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE -#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE -#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE -#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET -#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET -#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE -#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE -#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE -#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE -#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET -#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET -#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE -#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE -#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE -#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE -#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET -#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET -#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE -#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE -#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE -#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE -#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET -#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET -#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE -#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE -#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE -#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE -#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET -#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET -#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE -#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE -#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE -#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE -#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET -#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET -#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE -#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE -#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE -#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE -#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET -#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET -#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE -#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE -#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE -#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE -#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET -#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET - -#if defined(STM32WB) -#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE -#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET -#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET -#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED -#define QSPI_IRQHandler QUADSPI_IRQHandler -#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ - -#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE -#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE -#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE -#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE -#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET -#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET -#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE -#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE -#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE -#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE -#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET -#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET -#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE -#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE -#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE -#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE -#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET -#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET -#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE -#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE -#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE -#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE -#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET -#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET -#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE -#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE -#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE -#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE -#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET -#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET -#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE -#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE -#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE -#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE -#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET -#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET -#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE -#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE -#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE -#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE -#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET -#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET -#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE -#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE -#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE -#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE -#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE -#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE -#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE -#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE -#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE -#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE -#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET -#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET -#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE -#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE -#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE -#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE -#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET -#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET -#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE -#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE -#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE -#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE -#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET -#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET -#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE -#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE -#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET -#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET -#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE -#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE -#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET -#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET -#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE -#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE -#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET -#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET -#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE -#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE -#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET -#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET -#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE -#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE -#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET -#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET -#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE -#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE -#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE -#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE -#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET -#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET -#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE -#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE -#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE -#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE -#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET -#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET -#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE -#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE -#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE -#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE -#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET -#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET -#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE -#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE -#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE -#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE -#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET -#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET -#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE -#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE -#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE -#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE -#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET -#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET -#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE -#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE -#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE -#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE -#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET -#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET -#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE -#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE -#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE -#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE -#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET -#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET -#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE -#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE -#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE -#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE -#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET -#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET -#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE -#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE -#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE -#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE -#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET -#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET -#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE -#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE -#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE -#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE -#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET -#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET -#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE -#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE -#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET -#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET -#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE -#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE -#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE -#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE -#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET -#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET -#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE -#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE -#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE -#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE -#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET -#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET -#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE -#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE -#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE -#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE -#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET -#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET -#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE -#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE -#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE -#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE -#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET -#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET -#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE -#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE -#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET -#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE -#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE -#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE -#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE -#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET -#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE -#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE -#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE -#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE -#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET -#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET -#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE -#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE -#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET -#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET -#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE -#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE -#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE -#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE -#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET -#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET -#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE -#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE -#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE -#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE -#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE -#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE -#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET -#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET -#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE -#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE - -#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET -#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE -#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE -#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE -#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE -#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE -#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE -#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE -#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE -#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE -#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET -#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET -#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE -#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE -#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE -#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE -#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET -#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET -#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE -#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE -#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE -#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET -#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET -#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE -#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE -#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE -#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET -#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE -#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE -#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE -#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE -#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE -#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE -#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE -#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE -#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE -#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE -#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE -#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE -#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET -#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET -#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE -#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE -#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE -#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET -#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET -#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE -#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE -#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE -#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET -#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET -#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE -#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE -#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE -#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET -#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET -#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE -#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE -#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE -#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET -#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE -#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE -#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE -#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE -#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET -#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET -#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE -#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE -#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE -#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED -#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE -#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE -#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE -#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE -#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET -#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET -#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE -#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE -#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE -#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET -#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET -#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE - -/* alias define maintained for legacy */ -#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET - -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE -#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE -#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE -#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE -#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE -#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE -#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE -#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE -#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE -#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE -#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE -#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE -#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE -#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE -#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE -#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE -#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE - -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET -#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET -#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET -#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET -#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET -#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET -#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET -#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET -#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET -#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET -#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET -#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET -#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET -#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET -#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET -#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET -#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET - -#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED -#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED -#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED -#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED -#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED -#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED -#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED -#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED -#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED -#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED -#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED -#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED -#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED -#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED -#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED -#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED -#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED -#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED -#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED -#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED -#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED -#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED -#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED -#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED -#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED -#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED -#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED -#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED -#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED -#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED -#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED -#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED -#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED -#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED -#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED -#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED -#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED -#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED -#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED -#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED -#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED -#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED -#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED -#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED -#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED -#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED -#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED -#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED -#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED -#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED -#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED -#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED -#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED -#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED -#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED -#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED -#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED -#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED -#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED -#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED -#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED -#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED -#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED -#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED -#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED -#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED -#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED -#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED -#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED -#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED -#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED -#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED -#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED -#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED -#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED -#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED -#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED -#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED -#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED -#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED -#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED -#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED -#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED -#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED -#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED -#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED -#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED -#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED -#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED -#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED -#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED -#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED -#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED -#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED -#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED -#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED -#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED -#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED -#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED -#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED -#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED -#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED -#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED -#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED -#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED -#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED -#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED -#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED -#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED -#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED -#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED -#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED -#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED -#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED - -#if defined(STM32F4) -#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED -#define Sdmmc1ClockSelection SdioClockSelection -#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO -#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 -#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK -#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG -#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET -#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE -#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE -#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED -#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED -#define SdioClockSelection Sdmmc1ClockSelection -#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 -#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE -#endif - -#if defined(STM32F7) -#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 -#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK -#endif - -#if defined(STM32H7) -#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() - -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() -#endif - -#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG -#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG - -#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE - -#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE -#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE -#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK -#define IS_RCC_HCLK_DIV IS_RCC_PCLK -#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK - -#define RCC_IT_HSI14 RCC_IT_HSI14RDY - -#define RCC_IT_CSSLSE RCC_IT_LSECSS -#define RCC_IT_CSSHSE RCC_IT_CSS - -#define RCC_PLLMUL_3 RCC_PLL_MUL3 -#define RCC_PLLMUL_4 RCC_PLL_MUL4 -#define RCC_PLLMUL_6 RCC_PLL_MUL6 -#define RCC_PLLMUL_8 RCC_PLL_MUL8 -#define RCC_PLLMUL_12 RCC_PLL_MUL12 -#define RCC_PLLMUL_16 RCC_PLL_MUL16 -#define RCC_PLLMUL_24 RCC_PLL_MUL24 -#define RCC_PLLMUL_32 RCC_PLL_MUL32 -#define RCC_PLLMUL_48 RCC_PLL_MUL48 - -#define RCC_PLLDIV_2 RCC_PLL_DIV2 -#define RCC_PLLDIV_3 RCC_PLL_DIV3 -#define RCC_PLLDIV_4 RCC_PLL_DIV4 - -#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE -#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG -#define RCC_MCO_NODIV RCC_MCODIV_1 -#define RCC_MCO_DIV1 RCC_MCODIV_1 -#define RCC_MCO_DIV2 RCC_MCODIV_2 -#define RCC_MCO_DIV4 RCC_MCODIV_4 -#define RCC_MCO_DIV8 RCC_MCODIV_8 -#define RCC_MCO_DIV16 RCC_MCODIV_16 -#define RCC_MCO_DIV32 RCC_MCODIV_32 -#define RCC_MCO_DIV64 RCC_MCODIV_64 -#define RCC_MCO_DIV128 RCC_MCODIV_128 -#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK -#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI -#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE -#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK -#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI -#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 -#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 -#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE -#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 - -#if defined(STM32L4) -#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) -#else -#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK -#endif - -#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 -#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL -#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI -#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 -#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 -#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 - -#define HSION_BitNumber RCC_HSION_BIT_NUMBER -#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER -#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER -#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER -#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER -#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER -#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER -#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER -#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER -#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER -#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER -#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER -#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER -#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER -#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER -#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER -#define LSION_BitNumber RCC_LSION_BIT_NUMBER -#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER -#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER -#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER -#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER -#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER -#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER -#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER -#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER -#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER -#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS -#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS -#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS -#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS -#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE -#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE - -#define CR_HSION_BB RCC_CR_HSION_BB -#define CR_CSSON_BB RCC_CR_CSSON_BB -#define CR_PLLON_BB RCC_CR_PLLON_BB -#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB -#define CR_MSION_BB RCC_CR_MSION_BB -#define CSR_LSION_BB RCC_CSR_LSION_BB -#define CSR_LSEON_BB RCC_CSR_LSEON_BB -#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB -#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB -#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB -#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB -#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB -#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB -#define CR_HSEON_BB RCC_CR_HSEON_BB -#define CSR_RMVF_BB RCC_CSR_RMVF_BB -#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB -#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB - -#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE -#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE -#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE -#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE -#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE - -#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT - -#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN -#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF - -#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 -#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ -#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP -#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ -#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE -#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 - -#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE -#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED -#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET -#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET -#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE -#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED -#define DfsdmClockSelection Dfsdm1ClockSelection -#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 -#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK -#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG -#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE -#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 -#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 -#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 - -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 -#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 - -/** - * @} - */ - -/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose - * @{ - */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) - -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32G0) -#else -#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG -#endif -#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT -#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT - -#if defined (STM32F1) -#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() - -#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() - -#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() - -#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() - -#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() -#else -#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) -#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) -#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) -#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) -#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) -#endif /* STM32F1 */ - -#define IS_ALARM IS_RTC_ALARM -#define IS_ALARM_MASK IS_RTC_ALARM_MASK -#define IS_TAMPER IS_RTC_TAMPER -#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER -#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT -#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE -#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION -#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE -#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ -#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION -#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER -#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK -#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER - -#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE -#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE - -/** - * @} - */ - -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE -#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS - -#if defined(STM32F4) || defined(STM32F2) -#define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT -#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND -/* alias CMSIS */ -#define SDMMC1_IRQn SDIO_IRQn -#define SDMMC1_IRQHandler SDIO_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED -#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION -#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND -#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT -#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED -#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE -#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE -#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE -#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE -#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT -#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT -#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG -#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG -#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT -#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND -/* alias CMSIS for compatibilities */ -#define SDIO_IRQn SDMMC1_IRQn -#define SDIO_IRQHandler SDMMC1_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) -#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef -#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef -#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef -#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef -#endif - -#if defined(STM32H7) -#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback -#endif -/** - * @} - */ - -/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT -#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT -#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE -#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE -#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE -#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE - -#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE - -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE - -/** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 -#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 -#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START -#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH -#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR -#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE -#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE -#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_SPI_1LINE_TX SPI_1LINE_TX -#define __HAL_SPI_1LINE_RX SPI_1LINE_RX -#define __HAL_SPI_RESET_CRC SPI_RESET_CRC - -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION -#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION - -#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD - -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT -#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT -#define __USART_ENABLE __HAL_USART_ENABLE -#define __USART_DISABLE __HAL_USART_DISABLE - -#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE -#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE - -/** - * @} - */ - -/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose - * @{ - */ -#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE - -#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE -#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE -#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE - -#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE -#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE -#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE - -#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE - -#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT - -#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT - -#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup -#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup - -#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo -#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE -#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE - -#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE -#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT - -#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE - -#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN -#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER -#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER -#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER -#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD -#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD -#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION -#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION -#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER -#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER -#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE -#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE - -#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT -#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT -#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG -#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER - -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE -#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE -#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_LTDC_LAYER LTDC_LAYER -#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG -/** - * @} - */ - -/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose - * @{ - */ -#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE -#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE -#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE -#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE -#define SAI_STREOMODE SAI_STEREOMODE -#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY -#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL -#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL -#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL -#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL -#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL -#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE -#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 -#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE -/** - * @} - */ - -/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32H7) -#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow -#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT -#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA -#endif -/** - * @} - */ - -/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32_HAL_LEGACY */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h deleted file mode 100644 index aafa7c351..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h +++ /dev/null @@ -1,669 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal.h - * @author MCD Application Team - * @brief This file contains all the functions prototypes for the HAL - * module driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_H -#define __STM32L4xx_HAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_conf.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup HAL - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants - * @{ - */ - -/** @defgroup SYSCFG_BootMode Boot Mode - * @{ - */ -#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) -#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1 -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2) -#define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0) -#else -#define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** - * @} - */ - -/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts - * @{ - */ -#define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ -#define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ -#define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ -#define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ -#define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ -#define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ - -/** - * @} - */ - -/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31) - * @{ - */ -#define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ -#define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ -#define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ -#define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ -#define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ -#define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ -#define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ -#define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ -#define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ -#define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ -#define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ -#define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ -#define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ -#define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ -#define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ -#define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ -#if defined(SYSCFG_SWPR_PAGE31) -#define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ -#define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ -#define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ -#define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ -#define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ -#define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ -#define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ -#define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ -#define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ -#define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ -#define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ -#define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ -#define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ -#define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ -#define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ -#define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ -#endif /* SYSCFG_SWPR_PAGE31 */ - -/** - * @} - */ - -#if defined(SYSCFG_SWPR2_PAGE63) -/** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63) - * @{ - */ -#define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */ -#define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */ -#define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */ -#define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */ -#define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */ -#define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */ -#define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */ -#define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */ -#define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */ -#define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */ -#define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */ -#define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */ -#define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */ -#define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */ -#define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */ -#define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */ -#define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */ -#define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */ -#define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */ -#define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */ -#define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */ -#define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */ -#define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */ -#define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */ -#define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */ -#define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */ -#define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */ -#define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */ -#define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */ -#define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */ -#define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */ -#define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */ - -/** - * @} - */ -#endif /* SYSCFG_SWPR2_PAGE63 */ - -#if defined(VREFBUF) -/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale - * @{ - */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ - -/** - * @} - */ - -/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance - * @{ - */ -#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ -#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ - -/** - * @} - */ -#endif /* VREFBUF */ - -/** @defgroup SYSCFG_flags_definition Flags - * @{ - */ - -#define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ -#define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ - -/** - * @} - */ - -/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO - * @{ - */ - -/** @brief Fast-mode Plus driving capability on a specific GPIO - */ -#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ -#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ -#if defined(SYSCFG_CFGR1_I2C_PB8_FMP) -#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ -#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ -#if defined(SYSCFG_CFGR1_I2C_PB9_FMP) -#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ -#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros - * @{ - */ - -/** @brief Freeze/Unfreeze Peripherals in Debug mode - */ -#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) -#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) -#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) -#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) -#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) -#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) -#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) -#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) -#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) -#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) -#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) -#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) -#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) -#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) -#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) -#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) -#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) -#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) -#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) -#endif - -#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) -#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) -#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP) -#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) -#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP) -#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) -#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) -#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) -#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) -#endif - -#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) -#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) -#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) -#endif - -#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) -#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) -#endif - -#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) -#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) -#endif - -#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) -#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) -#endif - -#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) -#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) -#endif - -#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) -#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) -#endif - -/** - * @} - */ - -/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros - * @{ - */ - -/** @brief Main Flash memory mapped at 0x00000000. - */ -#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) - -/** @brief System Flash memory mapped at 0x00000000. - */ -#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) - -/** @brief Embedded SRAM mapped at 0x00000000. - */ -#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - -/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. - */ -#define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - -/** @brief OCTOSPI mapped at 0x00000000. - */ -#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2)) -#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0)) - -#else - -/** @brief QUADSPI mapped at 0x00000000. - */ -#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** - * @brief Return the boot mode as configured by user. - * @retval The boot mode as configured by user. The returned value can be one - * of the following values: - * @arg @ref SYSCFG_BOOT_MAINFLASH - * @arg @ref SYSCFG_BOOT_SYSTEMFLASH - @if STM32L486xx - * @arg @ref SYSCFG_BOOT_FMC - @endif - * @arg @ref SYSCFG_BOOT_SRAM - * @arg @ref SYSCFG_BOOT_QUADSPI - */ -#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) - -/** @brief SRAM2 page 0 to 31 write protection enable macro - * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP - * @note Write protection can only be disabled by a system reset - */ -#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ - SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ - }while(0) - -#if defined(SYSCFG_SWPR2_PAGE63) -/** @brief SRAM2 page 32 to 63 write protection enable macro - * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63 - * @note Write protection can only be disabled by a system reset - */ -#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ - SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\ - }while(0) -#endif /* SYSCFG_SWPR2_PAGE63 */ - -/** @brief SRAM2 page write protection unlock prior to erase - * @note Writing a wrong key reactivates the write protection - */ -#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ - SYSCFG->SKR = 0x53;\ - }while(0) - -/** @brief SRAM2 erase - * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase - */ -#define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) - -/** @brief Floating Point Unit interrupt enable/disable macros - * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts - */ -#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ - SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ - }while(0) - -#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ - CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ - }while(0) - -/** @brief SYSCFG Break ECC lock. - * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. - * @note The selected configuration is locked and can be unlocked only by system reset. - */ -#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) - -/** @brief SYSCFG Break Cortex-M4 Lockup lock. - * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. - * @note The selected configuration is locked and can be unlocked only by system reset. - */ -#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) - -/** @brief SYSCFG Break PVD lock. - * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. - * @note The selected configuration is locked and can be unlocked only by system reset. - */ -#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) - -/** @brief SYSCFG Break SRAM2 parity lock. - * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. - * @note The selected configuration is locked and can be unlocked by system reset. - */ -#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) - -/** @brief Check SYSCFG flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag - * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0) - -/** @brief Set the SPF bit to clear the SRAM Parity Error Flag. - */ -#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) - -/** @brief Fast-mode Plus driving capability enable/disable macros - * @param __FASTMODEPLUS__ This parameter can be a value of : - * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 - * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 - * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 - * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 - */ -#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ - SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ - }while(0) - -#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ - CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ - }while(0) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros - * @{ - */ - -#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) - -#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ - ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ - ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ - ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) - -#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF)) - -#if defined(VREFBUF) -#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ - ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) - -#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ - ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) - -#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) -#endif /* VREFBUF */ - -#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) -#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) -#elif defined(SYSCFG_FASTMODEPLUS_PB8) -#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8)) -#elif defined(SYSCFG_FASTMODEPLUS_PB9) -#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) -#else -#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)) -#endif -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup HAL_Exported_Functions - * @{ - */ - -/** @addtogroup HAL_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_Init(void); -HAL_StatusTypeDef HAL_DeInit(void); -void HAL_MspInit(void); -void HAL_MspDeInit(void); -HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); - -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(uint32_t Delay); -uint32_t HAL_GetTick(void); -void HAL_SuspendTick(void); -void HAL_ResumeTick(void); -uint32_t HAL_GetHalVersion(void); -uint32_t HAL_GetREVID(void); -uint32_t HAL_GetDEVID(void); -uint32_t HAL_GetUIDw0(void); -uint32_t HAL_GetUIDw1(void); -uint32_t HAL_GetUIDw2(void); - -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group3 - * @{ - */ - -/* DBGMCU Peripheral Control functions *****************************************/ -void HAL_DBGMCU_EnableDBGSleepMode(void); -void HAL_DBGMCU_DisableDBGSleepMode(void); -void HAL_DBGMCU_EnableDBGStopMode(void); -void HAL_DBGMCU_DisableDBGStopMode(void); -void HAL_DBGMCU_EnableDBGStandbyMode(void); -void HAL_DBGMCU_DisableDBGStandbyMode(void); - -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group4 - * @{ - */ - -/* SYSCFG Control functions ****************************************************/ -void HAL_SYSCFG_SRAM2Erase(void); -void HAL_SYSCFG_EnableMemorySwappingBank(void); -void HAL_SYSCFG_DisableMemorySwappingBank(void); - -#if defined(VREFBUF) -void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); -void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); -void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); -HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); -void HAL_SYSCFG_DisableVREFBUF(void); -#endif /* VREFBUF */ - -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h deleted file mode 100644 index f3eea8a70..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h +++ /dev/null @@ -1,433 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_CORTEX_H -#define __STM32L4xx_HAL_CORTEX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup CORTEX CORTEX - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Types CORTEX Exported Types - * @{ - */ - -#if (__MPU_PRESENT == 1) -/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition - * @{ - */ -typedef struct -{ - uint8_t Enable; /*!< Specifies the status of the region. - This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ - uint8_t Number; /*!< Specifies the number of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Number */ - uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ - uint8_t Size; /*!< Specifies the size of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Size */ - uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint8_t TypeExtField; /*!< Specifies the TEX field level. - This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ - uint8_t AccessPermission; /*!< Specifies the region access permission type. - This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ - uint8_t DisableExec; /*!< Specifies the instruction access status. - This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ - uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ - uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. - This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ - uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ -}MPU_Region_InitTypeDef; -/** - * @} - */ -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group - * @{ - */ -#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, - 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, - 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, - 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, - 1 bit for subpriority */ -#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority, - 0 bit for subpriority */ -/** - * @} - */ - -/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source - * @{ - */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) -/** - * @} - */ - -#if (__MPU_PRESENT == 1) -/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control - * @{ - */ -#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) -#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) -#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) -#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable - * @{ - */ -#define MPU_REGION_ENABLE ((uint8_t)0x01) -#define MPU_REGION_DISABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access - * @{ - */ -#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) -#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable - * @{ - */ -#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable - * @{ - */ -#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable - * @{ - */ -#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels - * @{ - */ -#define MPU_TEX_LEVEL0 ((uint8_t)0x00) -#define MPU_TEX_LEVEL1 ((uint8_t)0x01) -#define MPU_TEX_LEVEL2 ((uint8_t)0x02) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size - * @{ - */ -#define MPU_REGION_SIZE_32B ((uint8_t)0x04) -#define MPU_REGION_SIZE_64B ((uint8_t)0x05) -#define MPU_REGION_SIZE_128B ((uint8_t)0x06) -#define MPU_REGION_SIZE_256B ((uint8_t)0x07) -#define MPU_REGION_SIZE_512B ((uint8_t)0x08) -#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) -#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) -#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) -#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) -#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) -#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) -#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) -#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) -#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) -#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) -#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) -#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) -#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) -#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) -#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) -#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) -#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) -#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) -#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) -#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) -#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) -#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) -#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes - * @{ - */ -#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) -#define MPU_REGION_PRIV_RW ((uint8_t)0x01) -#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) -#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) -#define MPU_REGION_PRIV_RO ((uint8_t)0x05) -#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number - * @{ - */ -#define MPU_REGION_NUMBER0 ((uint8_t)0x00) -#define MPU_REGION_NUMBER1 ((uint8_t)0x01) -#define MPU_REGION_NUMBER2 ((uint8_t)0x02) -#define MPU_REGION_NUMBER3 ((uint8_t)0x03) -#define MPU_REGION_NUMBER4 ((uint8_t)0x04) -#define MPU_REGION_NUMBER5 ((uint8_t)0x05) -#define MPU_REGION_NUMBER6 ((uint8_t)0x06) -#define MPU_REGION_NUMBER7 ((uint8_t)0x07) -/** - * @} - */ -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions - * @{ - */ - -/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * @{ - */ -/* Initialization and Configuration functions *****************************/ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); -void HAL_NVIC_SystemReset(void); -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); - -/** - * @} - */ - -/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions - * @{ - */ -/* Peripheral Control functions ***********************************************/ -uint32_t HAL_NVIC_GetPriorityGrouping(void); -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); -void HAL_SYSTICK_IRQHandler(void); -void HAL_SYSTICK_Callback(void); - -#if (__MPU_PRESENT == 1) -void HAL_MPU_Enable(uint32_t MPU_Control); -void HAL_MPU_Disable(void); -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); -#endif /* __MPU_PRESENT */ -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Macros CORTEX Private Macros - * @{ - */ -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ - ((GROUP) == NVIC_PRIORITYGROUP_1) || \ - ((GROUP) == NVIC_PRIORITYGROUP_2) || \ - ((GROUP) == NVIC_PRIORITYGROUP_3) || \ - ((GROUP) == NVIC_PRIORITYGROUP_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) - -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ - ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) - -#if (__MPU_PRESENT == 1) -#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ - ((STATE) == MPU_REGION_DISABLE)) - -#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ - ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) - -#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ - ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) - -#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ - ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) - -#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ - ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) - -#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ - ((TYPE) == MPU_TEX_LEVEL1) || \ - ((TYPE) == MPU_TEX_LEVEL2)) - -#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ - ((TYPE) == MPU_REGION_PRIV_RW) || \ - ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ - ((TYPE) == MPU_REGION_FULL_ACCESS) || \ - ((TYPE) == MPU_REGION_PRIV_RO) || \ - ((TYPE) == MPU_REGION_PRIV_RO_URO)) - -#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ - ((NUMBER) == MPU_REGION_NUMBER1) || \ - ((NUMBER) == MPU_REGION_NUMBER2) || \ - ((NUMBER) == MPU_REGION_NUMBER3) || \ - ((NUMBER) == MPU_REGION_NUMBER4) || \ - ((NUMBER) == MPU_REGION_NUMBER5) || \ - ((NUMBER) == MPU_REGION_NUMBER6) || \ - ((NUMBER) == MPU_REGION_NUMBER7)) - -#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ - ((SIZE) == MPU_REGION_SIZE_64B) || \ - ((SIZE) == MPU_REGION_SIZE_128B) || \ - ((SIZE) == MPU_REGION_SIZE_256B) || \ - ((SIZE) == MPU_REGION_SIZE_512B) || \ - ((SIZE) == MPU_REGION_SIZE_1KB) || \ - ((SIZE) == MPU_REGION_SIZE_2KB) || \ - ((SIZE) == MPU_REGION_SIZE_4KB) || \ - ((SIZE) == MPU_REGION_SIZE_8KB) || \ - ((SIZE) == MPU_REGION_SIZE_16KB) || \ - ((SIZE) == MPU_REGION_SIZE_32KB) || \ - ((SIZE) == MPU_REGION_SIZE_64KB) || \ - ((SIZE) == MPU_REGION_SIZE_128KB) || \ - ((SIZE) == MPU_REGION_SIZE_256KB) || \ - ((SIZE) == MPU_REGION_SIZE_512KB) || \ - ((SIZE) == MPU_REGION_SIZE_1MB) || \ - ((SIZE) == MPU_REGION_SIZE_2MB) || \ - ((SIZE) == MPU_REGION_SIZE_4MB) || \ - ((SIZE) == MPU_REGION_SIZE_8MB) || \ - ((SIZE) == MPU_REGION_SIZE_16MB) || \ - ((SIZE) == MPU_REGION_SIZE_32MB) || \ - ((SIZE) == MPU_REGION_SIZE_64MB) || \ - ((SIZE) == MPU_REGION_SIZE_128MB) || \ - ((SIZE) == MPU_REGION_SIZE_256MB) || \ - ((SIZE) == MPU_REGION_SIZE_512MB) || \ - ((SIZE) == MPU_REGION_SIZE_1GB) || \ - ((SIZE) == MPU_REGION_SIZE_2GB) || \ - ((SIZE) == MPU_REGION_SIZE_4GB)) - -#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_CORTEX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h deleted file mode 100644 index bb9816b41..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h +++ /dev/null @@ -1,213 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_def.h - * @author MCD Application Team - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DEF -#define __STM32L4xx_HAL_DEF - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx.h" -#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ -#include - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HAL Status structures definition - */ -typedef enum -{ - HAL_OK = 0x00, - HAL_ERROR = 0x01, - HAL_BUSY = 0x02, - HAL_TIMEOUT = 0x03 -} HAL_StatusTypeDef; - -/** - * @brief HAL Lock structures definition - */ -typedef enum -{ - HAL_UNLOCKED = 0x00, - HAL_LOCKED = 0x01 -} HAL_LockTypeDef; - -/* Exported macros -----------------------------------------------------------*/ - -#define HAL_MAX_DELAY 0xFFFFFFFFU - -#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) -#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) - -#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ - do{ \ - (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ - (__DMA_HANDLE__).Parent = (__HANDLE__); \ - } while(0) - -#define UNUSED(x) ((void)(x)) - -/** @brief Reset the Handle's State field. - * @param __HANDLE__: specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: - * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro - * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function - * HAL_PPP_Init() is called, the low level hardware initialization will be missed - * (i.e. HAL_PPP_MspInit() will not be executed). - * - When there is a need to reconfigure the low level hardware: instead of calling - * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). - * In this later function, when the Handle's "State" field is set to 0, it will execute the function - * HAL_PPP_MspInit() which will reconfigure the low level hardware. - * @retval None - */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) - -#if (USE_RTOS == 1) - /* Reserved for future use */ - #error " USE_RTOS should be 0 in the current HAL release " -#else - #define __HAL_LOCK(__HANDLE__) \ - do{ \ - if((__HANDLE__)->Lock == HAL_LOCKED) \ - { \ - return HAL_BUSY; \ - } \ - else \ - { \ - (__HANDLE__)->Lock = HAL_LOCKED; \ - } \ - }while (0) - - #define __HAL_UNLOCK(__HANDLE__) \ - do{ \ - (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0) -#endif /* USE_RTOS */ - -#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ -#endif /* __GNUC__ */ - - -/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ - #ifndef __ALIGN_END - #define __ALIGN_END __attribute__ ((aligned (4))) - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif /* __ALIGN_BEGIN */ -#else - #ifndef __ALIGN_END - #define __ALIGN_END - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #endif /* __CC_ARM */ - #endif /* __ALIGN_BEGIN */ -#endif /* __GNUC__ */ - -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC HAL_StatusTypeDef - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc HAL_StatusTypeDef - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) - -#endif - -/** - * @brief __NOINLINE definition - */ -#if defined ( __CC_ARM ) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- -*/ -#define __NOINLINE __attribute__ ( (noinline) ) - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- -*/ -#define __NOINLINE _Pragma("optimize = no_inline") - -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32L4xx_HAL_DEF */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h deleted file mode 100644 index c11a47cca..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h +++ /dev/null @@ -1,766 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_dma.h - * @author MCD Application Team - * @brief Header file of DMA HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DMA_H -#define __STM32L4xx_HAL_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup DMA_Exported_Types DMA Exported Types - * @{ - */ - -/** - * @brief DMA Configuration Structure definition - */ -typedef struct -{ - uint32_t Request; /*!< Specifies the request selected for the specified channel. - This parameter can be a value of @ref DMA_request */ - - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_Data_transfer_direction */ - - uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ - - uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_Memory_incremented_mode */ - - uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_Peripheral_data_size */ - - uint32_t MemDataAlignment; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_Memory_data_size */ - - uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_Priority_level */ -} DMA_InitTypeDef; - -/** - * @brief HAL DMA State structures definition - */ -typedef enum -{ - HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ -}HAL_DMA_StateTypeDef; - -/** - * @brief HAL DMA Error Code structure definition - */ -typedef enum -{ - HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */ -}HAL_DMA_LevelCompleteTypeDef; - - -/** - * @brief HAL DMA Callback ID structure definition - */ -typedef enum -{ - HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */ - HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */ - HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */ - HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */ - HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */ - -}HAL_DMA_CallbackIDTypeDef; - -/** - * @brief DMA handle Structure definition - */ -typedef struct __DMA_HandleTypeDef -{ - DMA_Channel_TypeDef *Instance; /*!< Register base address */ - - DMA_InitTypeDef Init; /*!< DMA communication parameters */ - - HAL_LockTypeDef Lock; /*!< DMA locking object */ - - __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - - void *Parent; /*!< Parent object state */ - - void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ - - void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ - - void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - - void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ - - __IO uint32_t ErrorCode; /*!< DMA Error code */ - - DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ - - uint32_t ChannelIndex; /*!< DMA Channel Index */ - -#if defined(DMAMUX1) - DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ - - DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ - - uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ - - DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ - - DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ - - uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ - -#endif /* DMAMUX1 */ - -}DMA_HandleTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants DMA Exported Constants - * @{ - */ - -/** @defgroup DMA_Error_Code DMA Error Code - * @{ - */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ -#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< Abort requested with no Xfer ongoing */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ -#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */ -#define HAL_DMA_ERROR_SYNC ((uint32_t)0x00000200U) /*!< DMAMUX sync overrun error */ -#define HAL_DMA_ERROR_REQGEN ((uint32_t)0x00000400U) /*!< DMAMUX request generator overrun error */ - -/** - * @} - */ - -/** @defgroup DMA_request DMA request - * @{ - */ -#if !defined (DMAMUX1) - -#define DMA_REQUEST_0 ((uint32_t)0x00000000) -#define DMA_REQUEST_1 ((uint32_t)0x00000001) -#define DMA_REQUEST_2 ((uint32_t)0x00000002) -#define DMA_REQUEST_3 ((uint32_t)0x00000003) -#define DMA_REQUEST_4 ((uint32_t)0x00000004) -#define DMA_REQUEST_5 ((uint32_t)0x00000005) -#define DMA_REQUEST_6 ((uint32_t)0x00000006) -#define DMA_REQUEST_7 ((uint32_t)0x00000007) - -#endif - -#if defined(DMAMUX1) - -#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ - -#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ -#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ -#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ -#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ - -#define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */ - -#define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */ -#define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */ - -#define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */ -#define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */ - -#define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */ -#define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */ -#define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */ -#define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */ -#define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */ -#define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */ - -#define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */ -#define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */ -#define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */ -#define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */ -#define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */ -#define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */ -#define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */ -#define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */ - -#define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */ -#define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */ -#define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */ -#define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */ -#define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */ -#define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */ - -#define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */ -#define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */ -#define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */ -#define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */ - -#define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */ -#define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */ - -#define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */ -#define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */ -#define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */ -#define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */ - -#define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */ -#define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */ - -#define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */ -#define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */ -#define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */ -#define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */ -#define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */ -#define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */ -#define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */ - -#define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */ -#define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */ -#define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */ -#define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */ -#define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */ -#define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */ -#define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */ - -#define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */ -#define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */ -#define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */ -#define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */ -#define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */ - -#define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */ -#define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */ -#define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */ -#define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */ -#define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */ -#define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */ - -#define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */ -#define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */ -#define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */ -#define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */ -#define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */ - -#define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */ -#define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */ -#define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */ -#define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */ -#define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */ -#define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */ - -#define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */ -#define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */ -#define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */ -#define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */ - -#define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */ -#define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */ -#define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */ -#define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */ - -#define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */ -#define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */ -#define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */ -#define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */ - -#define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */ - -#define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */ -#define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */ - -#define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */ - -#endif /* DMAMUX1 */ - -/** - * @} - */ - -/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction - * @{ - */ -#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode - * @{ - */ -#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ -#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode - * @{ - */ -#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ -#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size - * @{ - */ -#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ -#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ -#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_Memory_data_size DMA Memory data size - * @{ - */ -#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ -#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ -#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_mode DMA mode - * @{ - */ -#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ -#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ -/** - * @} - */ - -/** @defgroup DMA_Priority_level DMA Priority level - * @{ - */ -#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ -#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ -#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ -#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ -/** - * @} - */ - - -/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions - * @{ - */ -#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) -#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) -#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) -/** - * @} - */ - -/** @defgroup DMA_flag_definitions DMA flag definitions - * @{ - */ -#define DMA_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA_FLAG_TE7 ((uint32_t)0x08000000) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup DMA_Exported_Macros DMA Exported Macros - * @{ - */ - -/** @brief Reset DMA handle state. - * @param __HANDLE__: DMA handle - * @retval None - */ -#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) - -/** - * @brief Enable the specified DMA Channel. - * @param __HANDLE__: DMA handle - * @retval None - */ -#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) - -/** - * @brief Disable the specified DMA Channel. - * @param __HANDLE__: DMA handle - * @retval None - */ -#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) - - -/* Interrupt & Flag management */ - -/** - * @brief Return the current DMA Channel transfer complete flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer complete flag index. - */ - -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ - DMA_FLAG_TC7) - -/** - * @brief Return the current DMA Channel half transfer complete flag. - * @param __HANDLE__: DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ - DMA_FLAG_HT7) - -/** - * @brief Return the current DMA Channel transfer error flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ - DMA_FLAG_TE7) - -/** - * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ - DMA_ISR_GIF7) - -/** - * @brief Get the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * @arg DMA_FLAG_GLx: Global interrupt flag - * Where x can be from 1 to 7 to select the DMA Channel x flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ - (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) - -/** - * @brief Clear the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * @arg DMA_FLAG_GLx: Global interrupt flag - * Where x can be from 1 to 7 to select the DMA Channel x flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ - (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) - -/** - * @brief Enable the specified DMA Channel interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) - -/** - * @brief Disable the specified DMA Channel interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified DMA Channel interrupt is enabled or not. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval The state of DMA_IT (SET or RESET). - */ -#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) - -/** - * @brief Return the number of remaining data units in the current DMA Channel transfer. - * @param __HANDLE__: DMA handle - * @retval The number of remaining data units in the current DMA Channel transfer. - */ -#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) - -/** - * @} - */ - -#if defined(DMAMUX1) -/* Include DMA HAL Extension module */ -#include "stm32l4xx_hal_dma_ex.h" -#endif /* DMAMUX1 */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup DMA_Exported_Functions - * @{ - */ - -/** @addtogroup DMA_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); - -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DMA_Private_Macros DMA Private Macros - * @{ - */ - -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ - ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) - -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ - ((STATE) == DMA_PINC_DISABLE)) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ - ((STATE) == DMA_MINC_DISABLE)) - -#if !defined (DMAMUX1) - -#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ - ((REQUEST) == DMA_REQUEST_1) || \ - ((REQUEST) == DMA_REQUEST_2) || \ - ((REQUEST) == DMA_REQUEST_3) || \ - ((REQUEST) == DMA_REQUEST_4) || \ - ((REQUEST) == DMA_REQUEST_5) || \ - ((REQUEST) == DMA_REQUEST_6) || \ - ((REQUEST) == DMA_REQUEST_7)) -#endif - -#if defined(DMAMUX1) - -#define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN) - -#endif /* DMAMUX1 */ - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ - ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_PDATAALIGN_WORD)) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ - ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_MDATAALIGN_WORD )) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR)) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ - ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ - ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h deleted file mode 100644 index 0ce4b2ae2..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h +++ /dev/null @@ -1,298 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_dma_ex.h - * @author MCD Application Team - * @brief Header file of DMA HAL extension module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DMA_EX_H -#define __STM32L4xx_HAL_DMA_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(DMAMUX1) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMAEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Types DMAEx Exported Types - * @{ - */ - -/** - * @brief HAL DMA Synchro definition - */ - - -/** - * @brief HAL DMAMUX Synchronization configuration structure definition - */ -typedef struct -{ - uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. - This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */ - - uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. - This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */ - - FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled - This parameter can take the value ENABLE or DISABLE*/ - - - FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. - This parameter can take the value ENABLE or DISABLE */ - - uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event - This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ - - -}HAL_DMA_MuxSyncConfigTypeDef; - - -/** - * @brief HAL DMAMUX request generator parameters structure definition - */ -typedef struct -{ - uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator - This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */ - - uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. - This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */ - - uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event - This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ - -}HAL_DMA_MuxRequestGeneratorConfigTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants - * @{ - */ - -/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection - * @{ - */ -#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */ -#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */ -#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */ -#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */ -#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */ -#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */ -#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */ -#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */ -#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */ -#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */ -#define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */ -#define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */ -#define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */ -#define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */ -#define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */ -#define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */ -#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */ -#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */ -#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */ -#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */ -#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */ -#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 21U /*!< Synchronization Signal is LPTIM2 OUT */ -#define HAL_DMAMUX1_SYNC_DSI_TE 22U /*!< Synchronization Signal is DSI Tearing Effect */ -#define HAL_DMAMUX1_SYNC_DSI_EOT 23U /*!< Synchronization Signal is DSI End of refresh */ -#define HAL_DMAMUX1_SYNC_DMA2D_EOT 24U /*!< Synchronization Signal is DMA2D End of Transfer */ -#define HAL_DMAMUX1_SYNC_LDTC_IT 25U /*!< Synchronization Signal is LDTC IT */ - -/** - * @} - */ - -/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection - * @{ - */ -#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */ -#define HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0) /*!< synchronize with rising edge events */ -#define HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1) /*!< synchronize with falling edge events */ -#define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL) /*!< synchronize with rising and falling edge events */ - -/** - * @} - */ - -/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection - * @{ - */ - -#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */ -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */ -#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */ -#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */ -#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */ -#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */ - -/** - * @} - */ - -/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection - * @{ - */ -#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT 0U /*!< block request generator events */ -#define HAL_DMAMUX_REQUEST_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ -#define HAL_DMAMUX_REQUEST_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ -#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMAEx_Exported_Functions - * @{ - */ - -/* IO operation functions *****************************************************/ -/** @addtogroup DMAEx_Exported_Functions_Group1 - * @{ - */ - -/* ------------------------- REQUEST -----------------------------------------*/ -HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, - HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); -HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma); -/* -------------------------------------------------------------------------- */ - -/* ------------------------- SYNCHRO -----------------------------------------*/ -HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); -/* -------------------------------------------------------------------------- */ - -void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); - -/** - * @} - */ - -/** - * @} - */ - - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DMAEx_Private_Macros DMAEx Private Macros - * @brief DMAEx private macros - * @{ - */ - -#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LDTC_IT) - -#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) - -#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ - ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ - ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ - ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) - -#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) - -#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ - ((EVENT) == ENABLE)) - -#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQUEST_GEN_LTDC_IT) - -#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) - -#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQUEST_GEN_NO_EVENT) || \ - ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING) || \ - ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_FALLING) || \ - ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING_FALLING)) - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DMAMUX1 */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h deleted file mode 100644 index e05c897ba..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h +++ /dev/null @@ -1,1022 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_flash.h - * @author MCD Application Team - * @brief Header file of FLASH HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_FLASH_H -#define __STM32L4xx_HAL_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Types FLASH Exported Types - * @{ - */ - -/** - * @brief FLASH Erase structure definition - */ -typedef struct -{ - uint32_t TypeErase; /*!< Mass erase or page erase. - This parameter can be a value of @ref FLASH_Type_Erase */ - uint32_t Banks; /*!< Select bank to erase. - This parameter must be a value of @ref FLASH_Banks - (FLASH_BANK_BOTH should be used only for mass erase) */ - uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled - This parameter must be a value between 0 and (max number of pages in the bank - 1) - (eg : 255 for 1MB dual bank) */ - uint32_t NbPages; /*!< Number of pages to be erased. - This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ -} FLASH_EraseInitTypeDef; - -/** - * @brief FLASH Option Bytes Program structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< Option byte to be configured. - This parameter can be a combination of the values of @ref FLASH_OB_Type */ - uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). - Only one WRP area could be programmed at the same time. - This parameter can be value of @ref FLASH_OB_WRP_Area */ - uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). - This parameter must be a value between 0 and (max number of pages in the bank - 1) - (eg : 25 for 1MB dual bank) */ - uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). - This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */ - uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP). - This parameter can be a value of @ref FLASH_OB_Read_Protection */ - uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). - This parameter can be a combination of @ref FLASH_OB_USER_Type */ - uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). - This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, - @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, - @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, - @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, - @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, - @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, - @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */ - uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). - This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) - and @ref FLASH_OB_PCROP_RDP */ - uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). - This parameter must be a value between begin and end of bank - => Be careful of the bank swapping for the address */ - uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). - This parameter must be a value between PCROP Start address and end of bank */ -} FLASH_OBProgramInitTypeDef; - -/** - * @brief FLASH Procedure structure definition - */ -typedef enum -{ - FLASH_PROC_NONE = 0, - FLASH_PROC_PAGE_ERASE, - FLASH_PROC_MASS_ERASE, - FLASH_PROC_PROGRAM, - FLASH_PROC_PROGRAM_LAST -} FLASH_ProcedureTypeDef; - -/** - * @brief FLASH Cache structure definition - */ -typedef enum -{ - FLASH_CACHE_DISABLED = 0, - FLASH_CACHE_ICACHE_ENABLED, - FLASH_CACHE_DCACHE_ENABLED, - FLASH_CACHE_ICACHE_DCACHE_ENABLED -} FLASH_CacheTypeDef; - -/** - * @brief FLASH handle Structure definition - */ -typedef struct -{ - HAL_LockTypeDef Lock; /* FLASH locking object */ - __IO uint32_t ErrorCode; /* FLASH error code */ - __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ - __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */ - __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */ - __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ - __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ - __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */ -}FLASH_ProcessTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Constants FLASH Exported Constants - * @{ - */ - -/** @defgroup FLASH_Error FLASH Error - * @{ - */ -#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000) -#define HAL_FLASH_ERROR_OP ((uint32_t)0x00000001) -#define HAL_FLASH_ERROR_PROG ((uint32_t)0x00000002) -#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000004) -#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008) -#define HAL_FLASH_ERROR_SIZ ((uint32_t)0x00000010) -#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000020) -#define HAL_FLASH_ERROR_MIS ((uint32_t)0x00000040) -#define HAL_FLASH_ERROR_FAST ((uint32_t)0x00000080) -#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000100) -#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200) -#define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400) -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define HAL_FLASH_ERROR_PEMPTY ((uint32_t)0x00000800) -#endif -/** - * @} - */ - -/** @defgroup FLASH_Type_Erase FLASH Erase Type - * @{ - */ -#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!> 24) /*!< ECC Correction Interrupt source */ -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Macros FLASH Exported Macros - * @brief macros to control FLASH features - * @{ - */ - -/** - * @brief Set the FLASH Latency. - * @param __LATENCY__: FLASH Latency - * This parameter can be one of the following values : - * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state - * @arg FLASH_LATENCY_2: FLASH Two wait states - * @arg FLASH_LATENCY_3: FLASH Three wait states - * @arg FLASH_LATENCY_4: FLASH Four wait states - * @retval None - */ -#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))) - -/** - * @brief Get the FLASH Latency. - * @retval FLASH Latency - * This parameter can be one of the following values : - * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state - * @arg FLASH_LATENCY_2: FLASH Two wait states - * @arg FLASH_LATENCY_3: FLASH Three wait states - * @arg FLASH_LATENCY_4: FLASH Four wait states - */ -#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) - -/** - * @brief Enable the FLASH prefetch buffer. - * @retval None - */ -#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) - -/** - * @brief Disable the FLASH prefetch buffer. - * @retval None - */ -#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) - -/** - * @brief Enable the FLASH instruction cache. - * @retval none - */ -#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) - -/** - * @brief Disable the FLASH instruction cache. - * @retval none - */ -#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) - -/** - * @brief Enable the FLASH data cache. - * @retval none - */ -#define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) - -/** - * @brief Disable the FLASH data cache. - * @retval none - */ -#define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) - -/** - * @brief Reset the FLASH instruction Cache. - * @note This function must be used only when the Instruction Cache is disabled. - * @retval None - */ -#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ - } while (0) - -/** - * @brief Reset the FLASH data Cache. - * @note This function must be used only when the data Cache is disabled. - * @retval None - */ -#define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ - } while (0) - -/** - * @brief Enable the FLASH power down during Low-power run mode. - * @note Writing this bit to 0 this bit, automatically the keys are - * loss and a new unlock sequence is necessary to re-write it to 1. - */ -#define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ - WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ - SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ - } while (0) - -/** - * @brief Disable the FLASH power down during Low-power run mode. - * @note Writing this bit to 0 this bit, automatically the keys are - * loss and a new unlock sequence is necessary to re-write it to 1. - */ -#define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ - WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ - } while (0) - -/** - * @brief Enable the FLASH power down during Low-Power sleep mode - * @retval none - */ -#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) - -/** - * @brief Disable the FLASH power down during Low-Power sleep mode - * @retval none - */ -#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) - -/** - * @} - */ - -/** @defgroup FLASH_Interrupt FLASH Interrupts Macros - * @brief macros to handle FLASH interrupts - * @{ - */ - -/** - * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__: FLASH interrupt - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_OPERR: Error Interrupt - * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt - * @arg FLASH_IT_ECCC: ECC Correction Interrupt - * @retval none - */ -#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ - if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ - } while(0) - -/** - * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__: FLASH interrupt - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_OPERR: Error Interrupt - * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt - * @arg FLASH_IT_ECCC: ECC Correction Interrupt - * @retval none - */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ - if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ - } while(0) - -/** - * @brief Check whether the specified FLASH flag is set or not. - * @param __FLAG__: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH Operation error flag - * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH Size error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag - * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag - * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag - * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag - * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag - * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag - * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices) - * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected - * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) ? \ - (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ - (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) - -/** - * @brief Clear the FLASH's pending flags. - * @param __FLAG__: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH Operation error flag - * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH Size error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag - * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag - * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag - * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag - * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag - * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected - * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected - * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags - * @retval None - */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ - if((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ - } while(0) -/** - * @} - */ - -/* Include FLASH HAL Extended module */ -#include "stm32l4xx_hal_flash_ex.h" -#include "stm32l4xx_hal_flash_ramfunc.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASH_Exported_Functions - * @{ - */ - -/* Program operation functions ***********************************************/ -/** @addtogroup FLASH_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -/* FLASH IRQ handler method */ -void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ -void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); -void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); -/** - * @} - */ - -/* Peripheral Control functions **********************************************/ -/** @addtogroup FLASH_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_Lock(void); -/* Option bytes control */ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); -/** - * @} - */ - -/* Peripheral State functions ************************************************/ -/** @addtogroup FLASH_Exported_Functions_Group3 - * @{ - */ -uint32_t HAL_FLASH_GetError(void); -/** - * @} - */ - -/** - * @} - */ - -/* Private constants --------------------------------------------------------*/ -/** @defgroup FLASH_Private_Constants FLASH Private Constants - * @{ - */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x800 << 10) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) -#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) -#else -#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) -#endif - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) -#else -#define FLASH_BANK_SIZE (FLASH_SIZE) -#endif - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define FLASH_PAGE_SIZE ((uint32_t)0x1000) -#define FLASH_PAGE_SIZE_128_BITS ((uint32_t)0x2000) -#else -#define FLASH_PAGE_SIZE ((uint32_t)0x800) -#endif - -#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ - -#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ - ((VALUE) == FLASH_TYPEERASE_MASSERASE)) - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ - ((BANK) == FLASH_BANK_2) || \ - ((BANK) == FLASH_BANK_BOTH)) - -#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ - ((BANK) == FLASH_BANK_2)) -#else -#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) - -#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) -#endif - -#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ - ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BASE+0x1FFFFF)) -#else -#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \ - ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \ - ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \ - ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \ - ((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF)))))) -#endif - -#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF)) - -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS)) - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_FLASH_PAGE(PAGE) ((PAGE) < 256) -#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) -#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \ - ((PAGE) < 256))))) -#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 256) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \ - ((PAGE) < 256)))) -#else -#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? ((PAGE) < 64) : \ - ((PAGE) < 128)))) -#endif - -#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP))) - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ - ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) -#else -#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) -#endif - -#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ - ((LEVEL) == OB_RDP_LEVEL_1)/* ||\ - ((LEVEL) == OB_RDP_LEVEL_2)*/) - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFF) && ((TYPE) != 0)) -#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0)) -#else -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0)) -#endif - -#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ - ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ - ((LEVEL) == OB_BOR_LEVEL_4)) - -#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) - -#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) - -#define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) - -#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) - -#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) - -#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) - -#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) - -#define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) -#endif - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) -#endif - -#define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) - -#define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) - -#define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) - -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ - defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) - -#define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET)) -#endif - -#define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE)) - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ - ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ - ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ - ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ - ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ - ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ - ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ - ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) -#else -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ - ((LATENCY) == FLASH_LATENCY_1) || \ - ((LATENCY) == FLASH_LATENCY_2) || \ - ((LATENCY) == FLASH_LATENCY_3) || \ - ((LATENCY) == FLASH_LATENCY_4)) -#endif -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_FLASH_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h deleted file mode 100644 index 63d5c9fcd..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_flash_ex.h - * @author MCD Application Team - * @brief Header file of FLASH HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_FLASH_EX_H -#define __STM32L4xx_HAL_FLASH_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASHEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -#if defined (FLASH_CFGR_LVEN) -/** @addtogroup FLASHEx_Exported_Constants - * @{ - */ -/** @defgroup FLASHEx_LVE_PIN_CFG FLASHEx LVE pin configuration - * @{ - */ -#define FLASH_LVE_PIN_CTRL 0x00000000U /*!< LVE FLASH pin controlled by power controller */ -#define FLASH_LVE_PIN_FORCED FLASH_CFGR_LVEN /*!< LVE FLASH pin enforced to low (external SMPS used) */ -/** - * @} - */ - -/** - * @} - */ -#endif /* FLASH_CFGR_LVEN */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASHEx_Exported_Functions - * @{ - */ - -/* Extended Program operation functions *************************************/ -/** @addtogroup FLASHEx_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); -/** - * @} - */ - -#if defined (FLASH_CFGR_LVEN) -/** @addtogroup FLASHEx_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE); -/** - * @} - */ -#endif /* FLASH_CFGR_LVEN */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** - @cond 0 - */ -#if defined (FLASH_CFGR_LVEN) -#define IS_FLASH_LVE_PIN(CFG) (((CFG) == FLASH_LVE_PIN_CTRL) || ((CFG) == FLASH_LVE_PIN_FORCED)) -#endif /* FLASH_CFGR_LVEN */ -/** - @endcond - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_FLASH_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h deleted file mode 100644 index b0988b027..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_flash_ramfunc.h - * @author MCD Application Team - * @brief Header file of FLASH RAMFUNC driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_FLASH_RAMFUNC_H -#define __STM32L4xx_FLASH_RAMFUNC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH_RAMFUNC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC HAL_StatusTypeDef - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc HAL_StatusTypeDef - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) - -#endif - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASH_RAMFUNC_Exported_Functions - * @{ - */ - -/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 - * @{ - */ -/* Peripheral Control functions ************************************************/ -__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void); -__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void); -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -__RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig); -#endif -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_FLASH_RAMFUNC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h deleted file mode 100644 index 9f4bbac54..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h +++ /dev/null @@ -1,316 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_gpio.h - * @author MCD Application Team - * @brief Header file of GPIO HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_GPIO_H -#define __STM32L4xx_HAL_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Types GPIO Exported Types - * @{ - */ -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_mode */ - - uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. - This parameter can be a value of @ref GPIO_pull */ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_speed */ - - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins - This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ -}GPIO_InitTypeDef; - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - GPIO_PIN_RESET = 0, - GPIO_PIN_SET -}GPIO_PinState; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Constants GPIO Exported Constants - * @{ - */ -/** @defgroup GPIO_pins GPIO pins - * @{ - */ -#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ - -#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ -/** - * @} - */ - -/** @defgroup GPIO_mode GPIO mode - * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, Alternate or Analog) - * @{ - */ -#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ -#define GPIO_MODE_ANALOG_ADC_CONTROL ((uint32_t)0x0000000B) /*!< Analog Mode for ADC conversion */ -#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ -/** - * @} - */ - -/** @defgroup GPIO_speed GPIO speed - * @brief GPIO Output Maximum frequency - * @{ - */ -#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< range up to 5 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< range 5 MHz to 25 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< range 50 MHz to 80 MHz, please refer to the product datasheet */ -/** - * @} - */ - - /** @defgroup GPIO_pull GPIO pull - * @brief GPIO Pull-Up or Pull-Down Activation - * @{ - */ -#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ -#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** - * @brief Check whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__: specifies the EXTI line flag to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) - -/** - * @brief Clear the EXTI's line pending flags. - * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) - -/** - * @brief Check whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__: specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) - -/** - * @brief Clear the EXTI's line pending bits. - * @param __EXTI_LINE__: specifies the EXTI lines to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ -#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) - -#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\ - (((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00)) - -#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ - ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ - ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ - ((__MODE__) == GPIO_MODE_AF_PP) ||\ - ((__MODE__) == GPIO_MODE_AF_OD) ||\ - ((__MODE__) == GPIO_MODE_IT_RISING) ||\ - ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ - ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ - ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ - ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ - ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ - ((__MODE__) == GPIO_MODE_ANALOG) ||\ - ((__MODE__) == GPIO_MODE_ANALOG_ADC_CONTROL)) - -#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ - ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ - ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ - ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) - -#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ - ((__PULL__) == GPIO_PULLUP) || \ - ((__PULL__) == GPIO_PULLDOWN)) -/** - * @} - */ - -/* Include GPIO HAL Extended module */ -#include "stm32l4xx_hal_gpio_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * @{ - */ - -/* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); - -/** - * @} - */ - -/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_GPIO_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h deleted file mode 100644 index 63c69cb9e..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h +++ /dev/null @@ -1,822 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_gpio_ex.h - * @author MCD Application Team - * @brief Header file of GPIO HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_GPIO_EX_H -#define __STM32L4xx_HAL_GPIO_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIOEx GPIOEx - * @brief GPIO Extended HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants - * @{ - */ - -/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection - * @{ - */ - -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) -/*--------------STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx---*/ -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#if defined(STM32L433xx) || defined(STM32L443xx) -#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */ -#endif /* STM32L433xx || STM32L443xx */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART1 Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ -#define GPIO_AF6_COMP1 ((uint8_t)0x06) /* COMP1 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) -#define GPIO_AF10_USB_FS ((uint8_t)0x0A) /* USB_FS Alternate Function mapping */ -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ -#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */ - -#if defined(STM32L433xx) || defined(STM32L443xx) -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */ -#endif /* STM32L433xx || STM32L443xx */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_SWPMI1 ((uint8_t)0x0C) /* SWPMI1 Alternate Function mapping */ -#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ -#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ -#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ -#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) - -#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ - -#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) -/*--------------STM32L451xx/STM32L452xx/STM32L462xx---------------------------*/ -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_I2C4 ((uint8_t)0x02) /* I2C4 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ -#define GPIO_AF3_CAN1 ((uint8_t)0x03) /* CAN1 Alternate Function mapping */ -#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF6_COMP1 ((uint8_t)0x06) /* COMP1 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ - - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#if defined(STM32L452xx) || defined(STM32L462xx) -#define GPIO_AF10_USB_FS ((uint8_t)0x0A) /* USB_FS Alternate Function mapping */ -#endif /* STM32L452xx || STM32L462xx */ -#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */ -#define GPIO_AF10_CAN1 ((uint8_t)0x0A) /* CAN1 Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ -#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ -#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ -#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ -#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) - -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) -/*--------------STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx/STM32L486xx---*/ -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#if defined(STM32L476xx) || defined(STM32L486xx) -#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */ -#endif /* STM32L476xx || STM32L486xx */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ -#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ - - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ -#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */ - -#if defined(STM32L476xx) || defined(STM32L486xx) -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */ -#endif /* STM32L476xx || STM32L486xx */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#define GPIO_AF12_SWPMI1 ((uint8_t)0x0C) /* SWPMI1 Alternate Function mapping */ -#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ -#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ -#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */ -#define GPIO_AF13_TIM8_COMP2 ((uint8_t)0x0D) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ -#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ -#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ -#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM8_COMP1 ((uint8_t)0x0E) /* TIM8/COMP1 Break in Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - -#if defined(STM32L496xx) || defined(STM32L4A6xx) -/*--------------------------------STM32L496xx/STM32L4A6xx---------------------*/ -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ -#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -#define GPIO_AF2_I2C4 ((uint8_t)0x02) /* I2C4 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF3_CAN2 ((uint8_t)0x03) /* CAN2 Alternate Function mapping */ -#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ -#define GPIO_AF3_QUADSPI ((uint8_t)0x03) /* QUADSPI Alternate Function mapping */ -#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */ -#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ -#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */ -#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */ -#define GPIO_AF5_QUADSPI ((uint8_t)0x05) /* QUADSPI Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF8_CAN2 ((uint8_t)0x08) /* CAN2 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */ -#define GPIO_AF10_CAN2 ((uint8_t)0x0A) /* CAN2 Alternate Function mapping */ -#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#define GPIO_AF12_SWPMI1 ((uint8_t)0x0C) /* SWPMI1 Alternate Function mapping */ -#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ -#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ -#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */ -#define GPIO_AF13_TIM8_COMP2 ((uint8_t)0x0D) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ -#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ -#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ -#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM8_COMP1 ((uint8_t)0x0E) /* TIM8/COMP1 Break in Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) - -#endif /* STM32L496xx || STM32L4A6xx */ - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -/*---STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx--*/ -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ -#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ -#define GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OctoSPI Manager Port 1 Alternate Function mapping */ -#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */ -#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ -#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */ -#define GPIO_AF5_DFSDM1 ((uint8_t)0x05) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */ -#define GPIO_AF5_OCTOSPIM_P1 ((uint8_t)0x05) /* OctoSPI Manager Port 1 Alternate Function mapping */ -#define GPIO_AF5_OCTOSPIM_P2 ((uint8_t)0x05) /* OctoSPI Manager Port 2 Alternate Function mapping */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */ -#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */ -#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OctoSPI Manager Port 1 Alternate Function mapping */ -#define GPIO_AF10_OCTOSPIM_P2 ((uint8_t)0x0A) /* OctoSPI Manager Port 2 Alternate Function mapping */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_DSI ((uint8_t)0x0B) /* DSI Alternate Function mapping */ -#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ -#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_DSI ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ -#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */ -#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ -#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ -#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ -#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM8_COMP2 ((uint8_t)0x0E) /* TIM8/COMP2 Break in Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros - * @{ - */ - -/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index -* @{ - */ -#if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx) - -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U : 7U) - -#endif /* STM32L431xx || STM32L433xx || STM32L443xx */ - -#if defined(STM32L432xx) || defined(STM32L442xx) - -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U : 7U) - -#endif /* STM32L432xx || STM32L442xx */ - -#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) - -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U : 7U) - -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) - -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U : 7U) - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - -#if defined(STM32L496xx) || defined(STM32L4A6xx) - -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) - -#endif /* STM32L496xx || STM32L4A6xx */ - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_GPIO_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h deleted file mode 100644 index 7a8f85f29..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h +++ /dev/null @@ -1,708 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_i2c.h - * @author MCD Application Team - * @brief Header file of I2C HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_I2C_H -#define __STM32L4xx_HAL_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup I2C_Exported_Types I2C Exported Types - * @{ - */ - -/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition - * @brief I2C Configuration Structure definition - * @{ - */ -typedef struct -{ - uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization - section in Reference manual */ - - uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_ADDRESSING_MODE */ - - uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ - - uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ - - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ - - uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ - - uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ - -} I2C_InitTypeDef; - -/** - * @} - */ - -/** @defgroup HAL_state_structure_definition HAL state structure definition - * @brief HAL State structure definition - * @note HAL I2C State value coding follow below described bitmap :\n - * b7-b6 Error information\n - * 00 : No Error\n - * 01 : Abort (Abort user request on going)\n - * 10 : Timeout\n - * 11 : Error\n - * b5 IP initilisation status\n - * 0 : Reset (IP not initialized)\n - * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n - * b4 (not used)\n - * x : Should be set to 0\n - * b3\n - * 0 : Ready or Busy (No Listen mode ongoing)\n - * 1 : Listen (IP in Address Listen Mode)\n - * b2 Intrinsic process state\n - * 0 : Ready\n - * 1 : Busy (IP busy with some configuration or internal operations)\n - * b1 Rx state\n - * 0 : Ready (no Rx operation ongoing)\n - * 1 : Busy (Rx operation ongoing)\n - * b0 Tx state\n - * 0 : Ready (no Tx operation ongoing)\n - * 1 : Busy (Tx operation ongoing) - * @{ - */ -typedef enum -{ - HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ - HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ - HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ - HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ - HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission - process is ongoing */ - HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception - process is ongoing */ - HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ - -} HAL_I2C_StateTypeDef; - -/** - * @} - */ - -/** @defgroup HAL_mode_structure_definition HAL mode structure definition - * @brief HAL Mode structure definition - * @note HAL I2C Mode value coding follow below described bitmap :\n - * b7 (not used)\n - * x : Should be set to 0\n - * b6\n - * 0 : None\n - * 1 : Memory (HAL I2C communication is in Memory Mode)\n - * b5\n - * 0 : None\n - * 1 : Slave (HAL I2C communication is in Slave Mode)\n - * b4\n - * 0 : None\n - * 1 : Master (HAL I2C communication is in Master Mode)\n - * b3-b2-b1-b0 (not used)\n - * xxxx : Should be set to 0000 - * @{ - */ -typedef enum -{ - HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ - HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ - HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ - HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ - -} HAL_I2C_ModeTypeDef; - -/** - * @} - */ - -/** @defgroup I2C_Error_Code_definition I2C Error Code definition - * @brief I2C Error Code definition - * @{ - */ -#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ -#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ -#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ -#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ -#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ -/** - * @} - */ - -/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition - * @brief I2C handle Structure definition - * @{ - */ -typedef struct __I2C_HandleTypeDef -{ - I2C_TypeDef *Instance; /*!< I2C registers base address */ - - I2C_InitTypeDef Init; /*!< I2C communication parameters */ - - uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ - - uint16_t XferSize; /*!< I2C transfer size */ - - __IO uint16_t XferCount; /*!< I2C transfer counter */ - - __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can - be a value of @ref I2C_XFEROPTIONS */ - - __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - - HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ - - DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ - - HAL_LockTypeDef Lock; /*!< I2C locking object */ - - __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ - - __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ - - __IO uint32_t ErrorCode; /*!< I2C Error code */ - - __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ -} I2C_HandleTypeDef; -/** - * @} - */ - -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Constants I2C Exported Constants - * @{ - */ - -/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options - * @{ - */ -#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) -#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -/** - * @} - */ - -/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode - * @{ - */ -#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) -#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) -/** - * @} - */ - -/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode - * @{ - */ -#define I2C_DUALADDRESS_DISABLE (0x00000000U) -#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN -/** - * @} - */ - -/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks - * @{ - */ -#define I2C_OA2_NOMASK ((uint8_t)0x00U) -#define I2C_OA2_MASK01 ((uint8_t)0x01U) -#define I2C_OA2_MASK02 ((uint8_t)0x02U) -#define I2C_OA2_MASK03 ((uint8_t)0x03U) -#define I2C_OA2_MASK04 ((uint8_t)0x04U) -#define I2C_OA2_MASK05 ((uint8_t)0x05U) -#define I2C_OA2_MASK06 ((uint8_t)0x06U) -#define I2C_OA2_MASK07 ((uint8_t)0x07U) -/** - * @} - */ - -/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode - * @{ - */ -#define I2C_GENERALCALL_DISABLE (0x00000000U) -#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN -/** - * @} - */ - -/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode - * @{ - */ -#define I2C_NOSTRETCH_DISABLE (0x00000000U) -#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH -/** - * @} - */ - -/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size - * @{ - */ -#define I2C_MEMADD_SIZE_8BIT (0x00000001U) -#define I2C_MEMADD_SIZE_16BIT (0x00000002U) -/** - * @} - */ - -/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View - * @{ - */ -#define I2C_DIRECTION_TRANSMIT (0x00000000U) -#define I2C_DIRECTION_RECEIVE (0x00000001U) -/** - * @} - */ - -/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode - * @{ - */ -#define I2C_RELOAD_MODE I2C_CR2_RELOAD -#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND -#define I2C_SOFTEND_MODE (0x00000000U) -/** - * @} - */ - -/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode - * @{ - */ -#define I2C_NO_STARTSTOP (0x00000000U) -#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) -#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) -/** - * @} - */ - -/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition - * @brief I2C Interrupt definition - * Elements values convention: 0xXXXXXXXX - * - XXXXXXXX : Interrupt control mask - * @{ - */ -#define I2C_IT_ERRI I2C_CR1_ERRIE -#define I2C_IT_TCI I2C_CR1_TCIE -#define I2C_IT_STOPI I2C_CR1_STOPIE -#define I2C_IT_NACKI I2C_CR1_NACKIE -#define I2C_IT_ADDRI I2C_CR1_ADDRIE -#define I2C_IT_RXI I2C_CR1_RXIE -#define I2C_IT_TXI I2C_CR1_TXIE -/** - * @} - */ - -/** @defgroup I2C_Flag_definition I2C Flag definition - * @{ - */ -#define I2C_FLAG_TXE I2C_ISR_TXE -#define I2C_FLAG_TXIS I2C_ISR_TXIS -#define I2C_FLAG_RXNE I2C_ISR_RXNE -#define I2C_FLAG_ADDR I2C_ISR_ADDR -#define I2C_FLAG_AF I2C_ISR_NACKF -#define I2C_FLAG_STOPF I2C_ISR_STOPF -#define I2C_FLAG_TC I2C_ISR_TC -#define I2C_FLAG_TCR I2C_ISR_TCR -#define I2C_FLAG_BERR I2C_ISR_BERR -#define I2C_FLAG_ARLO I2C_ISR_ARLO -#define I2C_FLAG_OVR I2C_ISR_OVR -#define I2C_FLAG_PECERR I2C_ISR_PECERR -#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT -#define I2C_FLAG_ALERT I2C_ISR_ALERT -#define I2C_FLAG_BUSY I2C_ISR_BUSY -#define I2C_FLAG_DIR I2C_ISR_DIR -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Macros I2C Exported Macros - * @{ - */ - -/** @brief Reset I2C handle state. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) - -/** @brief Enable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) - -/** @brief Disable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - -/** @brief Check whether the specified I2C interrupt source is enabled or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the I2C interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Check whether the specified I2C flag is set or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref I2C_FLAG_TXE Transmit data register empty - * @arg @ref I2C_FLAG_TXIS Transmit interrupt status - * @arg @ref I2C_FLAG_RXNE Receive data register not empty - * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure received flag - * @arg @ref I2C_FLAG_STOPF STOP detection flag - * @arg @ref I2C_FLAG_TC Transfer complete (master mode) - * @arg @ref I2C_FLAG_TCR Transfer complete reload - * @arg @ref I2C_FLAG_BERR Bus error - * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun - * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref I2C_FLAG_ALERT SMBus alert - * @arg @ref I2C_FLAG_BUSY Bus busy - * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) - * - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) - -/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg @ref I2C_FLAG_TXE Transmit data register empty - * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure received flag - * @arg @ref I2C_FLAG_STOPF STOP detection flag - * @arg @ref I2C_FLAG_BERR Bus error - * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun - * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref I2C_FLAG_ALERT SMBus alert - * - * @retval None - */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ - : ((__HANDLE__)->Instance->ICR = (__FLAG__))) - -/** @brief Enable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Disable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) -/** - * @} - */ - -/* Include I2C HAL Extended module */ -#include "stm32l4xx_hal_i2c_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2C_Exported_Functions - * @{ - */ - -/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -/* Initialization and de-initialization functions******************************/ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ -/* IO operation functions ****************************************************/ -/******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); - -/******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); - -/******* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -/** - * @} - */ - -/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ -/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); -void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @{ - */ -/* Peripheral State, Mode and Error functions *********************************/ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); - -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Constants I2C Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2C_Private_Macro I2C Private Macros - * @{ - */ - -#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == I2C_ADDRESSINGMODE_10BIT)) - -#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) - -#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ - ((MASK) == I2C_OA2_MASK01) || \ - ((MASK) == I2C_OA2_MASK02) || \ - ((MASK) == I2C_OA2_MASK03) || \ - ((MASK) == I2C_OA2_MASK04) || \ - ((MASK) == I2C_OA2_MASK05) || \ - ((MASK) == I2C_OA2_MASK06) || \ - ((MASK) == I2C_OA2_MASK07)) - -#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ - ((CALL) == I2C_GENERALCALL_ENABLE)) - -#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLE)) - -#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) - -#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ - ((MODE) == I2C_AUTOEND_MODE) || \ - ((MODE) == I2C_SOFTEND_MODE)) - -#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ - ((REQUEST) == I2C_GENERATE_START_READ) || \ - ((REQUEST) == I2C_GENERATE_START_WRITE) || \ - ((REQUEST) == I2C_NO_STARTSTOP)) - -#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ - ((REQUEST) == I2C_NEXT_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME)) - -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) - -#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U) -#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) -#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) -#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) -#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) - -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) - -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -/* Private functions are defined in stm32l4xx_hal_i2c.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L4xx_HAL_I2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h deleted file mode 100644 index 726a83fba..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h +++ /dev/null @@ -1,186 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_i2c_ex.h - * @author MCD Application Team - * @brief Header file of I2C HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_I2C_EX_H -#define __STM32L4xx_HAL_I2C_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2CEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants - * @{ - */ - -/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter - * @{ - */ -#define I2C_ANALOGFILTER_ENABLE 0x00000000U -#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF -/** - * @} - */ - -/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus - * @{ - */ -#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ -#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ -#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ -#if defined(SYSCFG_CFGR1_I2C_PB8_FMP) -#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ -#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ -#else -#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */ -#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */ -#endif -#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ -#if defined(SYSCFG_CFGR1_I2C2_FMP) -#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ -#else -#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ -#endif -#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ -#if defined(SYSCFG_CFGR1_I2C4_FMP) -#define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ -#else -#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */ -#endif -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions - * @{ - */ - -/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); -void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); -void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros - * @{ - */ -#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLE)) - -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) - -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ - ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4))) -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions - * @{ - */ -/* Private functions are defined in stm32l4xx_hal_i2c_ex.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_I2C_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h deleted file mode 100644 index 51e0e5740..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h +++ /dev/null @@ -1,874 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pcd.h - * @author MCD Application Team - * @brief Header file of PCD HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_PCD_H -#define __STM32L4xx_HAL_PCD_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_ll_usb.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup PCD - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup PCD_Exported_Types PCD Exported Types - * @{ - */ - - /** - * @brief PCD State structure definition - */ -typedef enum -{ - HAL_PCD_STATE_RESET = 0x00, - HAL_PCD_STATE_READY = 0x01, - HAL_PCD_STATE_ERROR = 0x02, - HAL_PCD_STATE_BUSY = 0x03, - HAL_PCD_STATE_TIMEOUT = 0x04 -} PCD_StateTypeDef; - -/* Device LPM suspend state */ -typedef enum -{ - LPM_L0 = 0x00, /* on */ - LPM_L1 = 0x01, /* LPM L1 sleep */ - LPM_L2 = 0x02, /* suspend */ - LPM_L3 = 0x03, /* off */ -}PCD_LPM_StateTypeDef; - -#if defined (USB) -/** - * @brief PCD double buffered endpoint direction - */ -typedef enum -{ - PCD_EP_DBUF_OUT, - PCD_EP_DBUF_IN, - PCD_EP_DBUF_ERR, -}PCD_EP_DBUF_DIR; - -/** - * @brief PCD endpoint buffer number - */ -typedef enum -{ - PCD_EP_NOBUF, - PCD_EP_BUF0, - PCD_EP_BUF1 -}PCD_EP_BUF_NUM; -#endif /* USB */ - -#if defined (USB_OTG_FS) -typedef USB_OTG_GlobalTypeDef PCD_TypeDef; -typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; -typedef USB_OTG_EPTypeDef PCD_EPTypeDef; -#endif /* USB_OTG_FS */ - -#if defined (USB) -typedef USB_TypeDef PCD_TypeDef; -typedef USB_CfgTypeDef PCD_InitTypeDef; -typedef USB_EPTypeDef PCD_EPTypeDef; -#endif /* USB */ - -/** - * @brief PCD Handle Structure definition - */ -typedef struct -{ - PCD_TypeDef *Instance; /*!< Register base address */ - PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address: not used by USB OTG FS */ - PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */ - HAL_LockTypeDef Lock; /*!< PCD peripheral status */ - __IO PCD_StateTypeDef State; /*!< PCD communication state */ - uint32_t Setup[12]; /*!< Setup packet buffer */ - PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ - uint32_t BESL; - - - uint32_t lpm_active; /*!< Enable or disable the Link Power Management . - This parameter can be set to ENABLE or DISABLE */ - - uint32_t battery_charging_active; /*!< Enable or disable Battery charging. - This parameter can be set to ENABLE or DISABLE */ - void *pData; /*!< Pointer to upper stack Handler */ - -} PCD_HandleTypeDef; - -/** - * @} - */ - -/* Include PCD HAL Extended module */ -#include "stm32l4xx_hal_pcd_ex.h" - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PCD_Exported_Constants PCD Exported Constants - * @{ - */ - -/** @defgroup PCD_Speed PCD Speed - * @{ - */ -#define PCD_SPEED_FULL 1 -/** - * @} - */ - -/** @defgroup PCD_PHY_Module PCD PHY Module - * @{ - */ -#define PCD_PHY_EMBEDDED 1 -/** - * @} - */ - -/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value - * @{ - */ -#ifndef USBD_FS_TRDT_VALUE - #define USBD_FS_TRDT_VALUE 5 -#endif /* USBD_FS_TRDT_VALUE */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup PCD_Exported_Macros PCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ -#if defined (USB_OTG_FS) -#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) - -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) -#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) - - -#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \ - ~(USB_OTG_PCGCCTL_STOPCLK) - -#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK - -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR1 & (USB_OTG_FS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR1 = USB_OTG_FS_WAKEUP_EXTI_LINE - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do {\ - EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\ - EXTI->FTSR1 |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - } while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\ - EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - EXTI->FTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= USB_OTG_FS_WAKEUP_EXTI_LINE) - -#endif /* USB_OTG_FS */ - -#if defined (USB) -#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) - -#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE -#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE) -#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR1 & (USB_WAKEUP_EXTI_LINE) -#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR1 = USB_WAKEUP_EXTI_LINE - -#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() do {\ - EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\ - EXTI->FTSR1 |= (USB_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - } while(0) - -#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\ - EXTI->RTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE;\ - EXTI->FTSR1 |= USB_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= USB_WAKEUP_EXTI_LINE) - -#endif /* USB */ - -/** - * @} - */ - -/** @addtogroup PCD_Exported_Functions PCD Exported Functions - * @{ - */ - -/* Initialization/de-initialization functions ********************************/ -/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); -void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); -void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); -/** - * @} - */ - -/* I/O operation functions ***************************************************/ -/* Non-Blocking mode: Interrupt */ -/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ - /* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); - -void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); -/** - * @} - */ - -/* Peripheral Control functions **********************************************/ -/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); -HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -/** - * @} - */ - -/* Peripheral State functions ************************************************/ -/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions - * @{ - */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup PCD_Private_Constants PCD Private Constants - * @{ - */ -/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt - * @{ - */ -#if defined (USB_OTG_FS) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08) -#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10) - -#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the USB EXTI Line */ -#endif /* USB_OTG_FS */ - -#if defined (USB) -#define USB_WAKEUP_EXTI_LINE ((uint32_t)0x00020000) /*!< External interrupt line 17Connected to the USB EXTI Line */ -#endif /* USB */ - -/** - * @} - */ - -#if defined (USB) -/** @defgroup PCD_EP0_MPS PCD EP0 MPS - * @{ - */ -#define PCD_EP0MPS_64 DEP0CTL_MPS_64 -#define PCD_EP0MPS_32 DEP0CTL_MPS_32 -#define PCD_EP0MPS_16 DEP0CTL_MPS_16 -#define PCD_EP0MPS_08 DEP0CTL_MPS_8 -/** - * @} - */ - -/** @defgroup PCD_ENDP PCD ENDP - * @{ - */ -#define PCD_ENDP0 ((uint8_t)0) -#define PCD_ENDP1 ((uint8_t)1) -#define PCD_ENDP2 ((uint8_t)2) -#define PCD_ENDP3 ((uint8_t)3) -#define PCD_ENDP4 ((uint8_t)4) -#define PCD_ENDP5 ((uint8_t)5) -#define PCD_ENDP6 ((uint8_t)6) -#define PCD_ENDP7 ((uint8_t)7) -/** - * @} - */ - -/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind - * @{ - */ -#define PCD_SNG_BUF 0 -#define PCD_DBL_BUF 1 -/** - * @} - */ -#endif /* USB */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup PCD_Private_Macros PCD Private Macros - * @{ - */ -#if defined (USB) -/* SetENDPOINT */ -#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue)) - -/* GetENDPOINT */ -#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2)) - -/* ENDPOINT transfer */ -#define USB_EP0StartXfer USB_EPStartXfer - -/** - * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wType: Endpoint Type. - * @retval None - */ -#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) ))) - -/** - * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval Endpoint Type - */ -#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) - -/** - * @brief free buffer used from the application realizing it to the line - toggles bit SW_BUF in the double buffered endpoint register - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bDir: Direction - * @retval None - */ -#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\ -{\ - if ((bDir) == PCD_EP_DBUF_OUT)\ - { /* OUT double buffered endpoint */\ - PCD_TX_DTOG((USBx), (bEpNum));\ - }\ - else if ((bDir) == PCD_EP_DBUF_IN)\ - { /* IN double buffered endpoint */\ - PCD_RX_DTOG((USBx), (bEpNum));\ - }\ -} - -/** - * @brief gets direction of the double buffered endpoint - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval EP_DBUF_OUT, EP_DBUF_IN, - * EP_DBUF_ERR if the endpoint counter not yet programmed. - */ -#define PCD_GET_DB_DIR(USBx, bEpNum)\ -{\ - if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\ - return(PCD_EP_DBUF_OUT);\ - else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\ - return(PCD_EP_DBUF_IN);\ - else\ - return(PCD_EP_DBUF_ERR);\ -} - -/** - * @brief sets the status for tx transfer (bits STAT_TX[1:0]). - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wState: new state - * @retval None - */ -#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\ - \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\ - /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wState))!= 0)\ - { \ - _wRegVal ^= USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));\ - } /* PCD_SET_EP_TX_STATUS */ - -/** - * @brief sets the status for rx transfer (bits STAT_TX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wState: new state - * @retval None - */ -#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ - register uint16_t _wRegVal; \ - \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\ - /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ - } /* PCD_SET_EP_RX_STATUS */ - -/** - * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wStaterx: new state. - * @param wStatetx: new state. - * @retval None - */ -#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\ - register uint32_t _wRegVal; \ - \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ - /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG2; \ - } \ - /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ - } /* PCD_SET_EP_TXRX_STATUS */ - -/** - * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] - * /STAT_RX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval status - */ -#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) -#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT) - -/** - * @brief sets directly the VALID tx/rx-status into the endpoint register - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) -#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) - -/** - * @brief checks stall condition in an endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval TRUE = endpoint in stall condition. - */ -#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ - == USB_EP_TX_STALL) -#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \ - == USB_EP_RX_STALL) - -/** - * @brief set & clear EP_KIND bit. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK)))) -#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK)))) - -/** - * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) -#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) - -/** - * @brief Sets/clears directly EP_KIND bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) -#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) - -/** - * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK)) -#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK)) - -/** - * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) -#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) - -/** - * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\ - { \ - PCD_RX_DTOG((USBx), (bEpNum)); \ - } -#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\ - { \ - PCD_TX_DTOG((USBx), (bEpNum)); \ - } - -/** - * @brief Sets address in an endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bAddr: Address. - * @retval None - */ -#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ - USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr)) - -#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) - -#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400))) - -#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ - uint16_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ - } - -/** - * @brief sets address of the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wAddr: address to be set (must be word aligned). - * @retval None - */ -#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) -#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) - -/** - * @brief Gets address of the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval address of the buffer. - */ -#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) -#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) - -/** - * @brief Sets counter of rx buffer with no. of blocks. - * @param dwReg: Register - * @param wCount: Counter. - * @param wNBlocks: no. of Blocks. - * @retval None - */ -#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 5;\ - if(((wCount) & 0x1f) == 0)\ - { \ - (wNBlocks)--;\ - } \ - *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \ - }/* PCD_CALC_BLK32 */ - -#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 1;\ - if(((wCount) & 0x1) != 0)\ - { \ - (wNBlocks)++;\ - } \ - *pdwReg = (uint16_t)((wNBlocks) << 10);\ - }/* PCD_CALC_BLK2 */ - -#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\ - uint16_t wNBlocks;\ - if((wCount) > 62) \ - { \ - PCD_CALC_BLK32((dwReg),(wCount),wNBlocks); \ - } \ - else \ - { \ - PCD_CALC_BLK2((dwReg),(wCount),wNBlocks); \ - } \ - }/* PCD_SET_EP_CNT_RX_REG */ - -#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\ - uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ - } - -/** - * @brief sets counter for the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wCount: Counter value. - * @retval None - */ -#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount)) - - -/** - * @brief gets counter of the tx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval Counter value - */ -#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff) -#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff) - -/** - * @brief Sets buffer 0/1 address in a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wBuf0Addr: buffer 0 address. - * @retval Counter value - */ -#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));} -#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));} - -/** - * @brief Sets addresses in a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wBuf0Addr: buffer 0 address. - * @param wBuf1Addr = buffer 1 address. - * @retval None - */ -#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \ - PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\ - PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\ - } /* PCD_SET_EP_DBUF_ADDR */ - -/** - * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) -#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) - -/** - * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bDir: endpoint dir EP_DBUF_OUT = OUT - * EP_DBUF_IN = IN - * @param wCount: Counter value - * @retval None - */ -#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ - if((bDir) == PCD_EP_DBUF_OUT)\ - /* OUT endpoint */ \ - {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \ - else if((bDir) == PCD_EP_DBUF_IN)\ - /* IN endpoint */ \ - *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ - } /* SetEPDblBuf0Count*/ - -#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \ - if((bDir) == PCD_EP_DBUF_OUT)\ - {/* OUT endpoint */ \ - PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)); \ - } \ - else if((bDir) == PCD_EP_DBUF_IN)\ - {/* IN endpoint */ \ - *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ - } \ - } /* SetEPDblBuf1Count */ - -#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\ - PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ - PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ - } /* PCD_SET_EP_DBUF_CNT */ - -/** - * @brief Gets buffer 0/1 rx/tx counter for double buffering. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) -#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) - -#endif /* USB */ - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) - -/** @defgroup PCD_Instance_definition PCD Instance definition - * @{ - */ -#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE -/** - * @} - */ -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L4xx_HAL_PCD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h deleted file mode 100644 index f27c8b6a4..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h +++ /dev/null @@ -1,136 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pcd_ex.h - * @author MCD Application Team - * @brief Header file of PCD HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_PCD_EX_H -#define __STM32L4xx_HAL_PCD_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup PCDEx - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -typedef enum -{ - PCD_LPM_L0_ACTIVE = 0x00, /* on */ - PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ -}PCD_LPM_MsgTypeDef; - -typedef enum -{ - PCD_BCD_ERROR = 0xFF, - PCD_BCD_CONTACT_DETECTION = 0xFE, - PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, - PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, - PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, - PCD_BCD_DISCOVERY_COMPLETED = 0x00, - -}PCD_BCD_MsgTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* Exported macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions - * @{ - */ -/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @{ - */ - -#if defined(USB_OTG_FS) -HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); -HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); -#endif /* USB_OTG_FS */ - -#if defined (USB) -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, - uint16_t ep_addr, - uint16_t ep_kind, - uint32_t pmaadress); -#endif /* USB */ -HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); -void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); -void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); -void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L4xx_HAL_PCD_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h deleted file mode 100644 index f33df34e8..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h +++ /dev/null @@ -1,427 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pwr.h - * @author MCD Application Team - * @brief Header file of PWR HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_PWR_H -#define __STM32L4xx_HAL_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Types PWR Exported Types - * @{ - */ - -/** - * @brief PWR PVD configuration structure definition - */ -typedef struct -{ - uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. - This parameter can be a value of @ref PWR_PVD_detection_level. */ - - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWR_PVD_Mode. */ -}PWR_PVDTypeDef; - - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants PWR Exported Constants - * @{ - */ - - -/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels - * @{ - */ -#define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */ -#define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */ -#define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */ -#define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */ -#define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */ -#define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */ -#define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */ -#define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */ -/** - * @} - */ - -/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode - * @{ - */ -#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */ -#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ -/** - * @} - */ - - - - -/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode - * @{ - */ -#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */ -#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */ -/** - * @} - */ - -/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry - * @{ - */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */ -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */ -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry - * @{ - */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */ -#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */ -/** - * @} - */ - - -/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line - * @{ - */ -#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ -/** - * @} - */ - -/** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line - * @{ - */ -#define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup PWR_Exported_Macros PWR Exported Macros - * @{ - */ - -/** @brief Check whether or not a specific PWR flag is set. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event - * was received from the WKUP pin 1. - * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event - * was received from the WKUP pin 2. - * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event - * was received from the WKUP pin 3. - * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event - * was received from the WKUP pin 4. - * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event - * was received from the WKUP pin 5. - * @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system - * entered StandBy mode. - * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on - * the internal wakeup line. - * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the - * low-power regulator is ready. - * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the - * regulator is ready in main mode or is in low-power mode. - * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready - * in the selected voltage range or is still changing to the required voltage level. - * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is - * below or above the selected PVD threshold. - * @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is - * is below or above PVM1 threshold (applicable when USB feature is supported). - @if STM32L486xx - * @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is - * is below or above PVM2 threshold (applicable when VDDIO2 is present on device). - @endif - * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is - * is below or above PVM3 threshold. - * @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is - * is below or above PVM4 threshold. - * - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\ - (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\ - (PWR->SR2 & (1U << ((__FLAG__) & 31U))) ) - -/** @brief Clear a specific PWR flag. - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event - * was received from the WKUP pin 1. - * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event - * was received from the WKUP pin 2. - * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event - * was received from the WKUP pin 3. - * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event - * was received from the WKUP pin 4. - * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event - * was received from the WKUP pin 5. - * @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags. - * @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system - * entered Standby mode. - * @retval None - */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\ - (PWR->SCR = (__FLAG__)) :\ - (PWR->SCR = (1U << ((__FLAG__) & 31U))) ) -/** - * @brief Enable the PVD Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Enable the PVD Event Line. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) - -/** - * @brief Disable the PVD Event Line. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) - -/** - * @brief Enable the PVD Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Enable the PVD Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) - - -/** - * @brief Disable the PVD Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) - - -/** - * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) - -/** - * @brief Check whether or not the PVD EXTI interrupt flag is set. - * @retval EXTI PVD Line Status. - */ -#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD) - -/** - * @brief Clear the PVD EXTI interrupt flag. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD) - -/** - * @} - */ - - -/* Private macros --------------------------------------------------------*/ -/** @addtogroup PWR_Private_Macros PWR Private Macros - * @{ - */ - -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ - ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ - ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ - ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) - -#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\ - ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ - ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ - ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ - ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ - ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ - ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) - -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) - -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) - -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) - -/** - * @} - */ - -/* Include PWR HAL Extended module */ -#include "stm32l4xx_hal_pwr_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions *******************************/ -void HAL_PWR_DeInit(void); -void HAL_PWR_EnableBkUpAccess(void); -void HAL_PWR_DisableBkUpAccess(void); - -/** - * @} - */ - -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); -void HAL_PWR_EnablePVD(void); -void HAL_PWR_DisablePVD(void); - - -/* WakeUp pins configuration functions ****************************************/ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); - -/* Low Power modes configuration functions ************************************/ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -void HAL_PWR_EnterSTANDBYMode(void); - -void HAL_PWR_EnableSleepOnExit(void); -void HAL_PWR_DisableSleepOnExit(void); -void HAL_PWR_EnableSEVOnPend(void); -void HAL_PWR_DisableSEVOnPend(void); - -void HAL_PWR_PVDCallback(void); - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L4xx_HAL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h deleted file mode 100644 index 283047816..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h +++ /dev/null @@ -1,906 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pwr_ex.h - * @author MCD Application Team - * @brief Header file of PWR HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_PWR_EX_H -#define __STM32L4xx_HAL_PWR_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWREx - * @{ - */ - - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Types PWR Extended Exported Types - * @{ - */ - - -/** - * @brief PWR PVM configuration structure definition - */ -typedef struct -{ - uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. - This parameter can be a value of @ref PWREx_PVM_Type. - @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). -@if STM32L486xx - @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). -@endif - @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. - @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */ - - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWREx_PVM_Mode. */ -}PWR_PVMTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants - * @{ - */ - -/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants - * @{ - */ -#define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */ -/** - * @} - */ - - -/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins - * @{ - */ -#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ -#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ -#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ -#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ -#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ -#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ -#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ -#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ -#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ -#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ -#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<IMR2, PWR_EXTI_LINE_PVM1) - -/** - * @brief Disable the PVM1 Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) - -/** - * @brief Enable the PVM1 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) - -/** - * @brief Disable the PVM1 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) - -/** - * @brief Enable the PVM1 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) - -/** - * @brief Disable the PVM1 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) - -/** - * @brief Enable the PVM1 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) - - -/** - * @brief Disable the PVM1 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) - - -/** - * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1) - -/** - * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. - * @retval EXTI PVM1 Line Status. - */ -#define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1) - -/** - * @brief Clear the PVM1 EXTI flag. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1) - -#endif /* PWR_CR2_PVME1 */ - - -#if defined(PWR_CR2_PVME2) -/** - * @brief Enable the PVM2 Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) - -/** - * @brief Disable the PVM2 Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) - -/** - * @brief Enable the PVM2 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) - -/** - * @brief Disable the PVM2 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) - -/** - * @brief Enable the PVM2 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) - -/** - * @brief Disable the PVM2 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) - -/** - * @brief Enable the PVM2 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) - - -/** - * @brief Disable the PVM2 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) - - -/** - * @brief PVM2 EXTI line configuration: set rising & falling edge trigger. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2) - -/** - * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not. - * @retval EXTI PVM2 Line Status. - */ -#define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2) - -/** - * @brief Clear the PVM2 EXTI flag. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2) - -#endif /* PWR_CR2_PVME2 */ - - -/** - * @brief Enable the PVM3 Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) - -/** - * @brief Disable the PVM3 Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) - -/** - * @brief Enable the PVM3 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) - -/** - * @brief Disable the PVM3 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) - -/** - * @brief Enable the PVM3 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) - -/** - * @brief Disable the PVM3 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) - -/** - * @brief Enable the PVM3 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) - - -/** - * @brief Disable the PVM3 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) - - -/** - * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3) - -/** - * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. - * @retval EXTI PVM3 Line Status. - */ -#define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3) - -/** - * @brief Clear the PVM3 EXTI flag. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3) - - - - -/** - * @brief Enable the PVM4 Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) - -/** - * @brief Disable the PVM4 Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) - -/** - * @brief Enable the PVM4 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) - -/** - * @brief Disable the PVM4 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) - -/** - * @brief Enable the PVM4 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) - -/** - * @brief Disable the PVM4 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) - -/** - * @brief Enable the PVM4 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) - - -/** - * @brief Disable the PVM4 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) - - -/** - * @brief PVM4 EXTI line configuration: set rising & falling edge trigger. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4) - -/** - * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set. - * @retval EXTI PVM4 Line Status. - */ -#define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4) - -/** - * @brief Clear the PVM4 EXTI flag. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4) - - -/** - * @brief Configure the main internal regulator output voltage. - * @param __REGULATOR__: specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption. - * This parameter can be one of the following values: - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, - * typical output voltage at 1.2 V, - * system frequency up to 80 MHz. - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, - * typical output voltage at 1.0 V, - * system frequency up to 26 MHz. - * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check - * whether or not VOSF flag is cleared when moving from range 2 to range 1. User - * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. - * @retval None - */ -#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ - __IO uint32_t tmpreg; \ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ - UNUSED(tmpreg); \ - } while(0) - -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros - * @{ - */ - -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2) || \ - ((PIN) == PWR_WAKEUP_PIN3) || \ - ((PIN) == PWR_WAKEUP_PIN4) || \ - ((PIN) == PWR_WAKEUP_PIN5) || \ - ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ - ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ - ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ - ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ - ((PIN) == PWR_WAKEUP_PIN5_LOW)) - -#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ - ((TYPE) == PWR_PVM_2) ||\ - ((TYPE) == PWR_PVM_3) ||\ - ((TYPE) == PWR_PVM_4)) -#elif defined (STM32L471xx) -#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\ - ((TYPE) == PWR_PVM_3) ||\ - ((TYPE) == PWR_PVM_4)) -#endif - -#if defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ - ((TYPE) == PWR_PVM_3) ||\ - ((TYPE) == PWR_PVM_4)) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx) -#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\ - ((TYPE) == PWR_PVM_4)) -#endif - -#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ - ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ - ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ - ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ - ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ - ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ - ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) - -#if defined(PWR_CR5_R1MODE) -#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) -#else -#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) -#endif - - -#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ - ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) - -#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ - ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) - -#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) - - -#if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ - ((GPIO) == PWR_GPIO_B) ||\ - ((GPIO) == PWR_GPIO_C) ||\ - ((GPIO) == PWR_GPIO_D) ||\ - ((GPIO) == PWR_GPIO_E) ||\ - ((GPIO) == PWR_GPIO_H)) -#elif defined (STM32L432xx) || defined (STM32L442xx) -#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ - ((GPIO) == PWR_GPIO_B) ||\ - ((GPIO) == PWR_GPIO_C) ||\ - ((GPIO) == PWR_GPIO_H)) -#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) -#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ - ((GPIO) == PWR_GPIO_B) ||\ - ((GPIO) == PWR_GPIO_C) ||\ - ((GPIO) == PWR_GPIO_D) ||\ - ((GPIO) == PWR_GPIO_E) ||\ - ((GPIO) == PWR_GPIO_F) ||\ - ((GPIO) == PWR_GPIO_G) ||\ - ((GPIO) == PWR_GPIO_H)) -#elif defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ - ((GPIO) == PWR_GPIO_B) ||\ - ((GPIO) == PWR_GPIO_C) ||\ - ((GPIO) == PWR_GPIO_D) ||\ - ((GPIO) == PWR_GPIO_E) ||\ - ((GPIO) == PWR_GPIO_F) ||\ - ((GPIO) == PWR_GPIO_G) ||\ - ((GPIO) == PWR_GPIO_H) ||\ - ((GPIO) == PWR_GPIO_I)) -#endif - - -/** - * @} - */ - - -/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions - * @{ - */ - -/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions - * @{ - */ - - -/* Peripheral Control functions **********************************************/ -uint32_t HAL_PWREx_GetVoltageRange(void); -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); -void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); -void HAL_PWREx_DisableBatteryCharging(void); -#if defined(PWR_CR2_USV) -void HAL_PWREx_EnableVddUSB(void); -void HAL_PWREx_DisableVddUSB(void); -#endif /* PWR_CR2_USV */ -#if defined(PWR_CR2_IOSV) -void HAL_PWREx_EnableVddIO2(void); -void HAL_PWREx_DisableVddIO2(void); -#endif /* PWR_CR2_IOSV */ -void HAL_PWREx_EnableInternalWakeUpLine(void); -void HAL_PWREx_DisableInternalWakeUpLine(void); -HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); -HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); -HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); -HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); -void HAL_PWREx_EnablePullUpPullDownConfig(void); -void HAL_PWREx_DisablePullUpPullDownConfig(void); -void HAL_PWREx_EnableSRAM2ContentRetention(void); -void HAL_PWREx_DisableSRAM2ContentRetention(void); -#if defined(PWR_CR1_RRSTP) -void HAL_PWREx_EnableSRAM3ContentRetention(void); -void HAL_PWREx_DisableSRAM3ContentRetention(void); -#endif /* PWR_CR1_RRSTP */ -#if defined(PWR_CR3_DSIPDEN) -void HAL_PWREx_EnableDSIPinsPDActivation(void); -void HAL_PWREx_DisableDSIPinsPDActivation(void); -#endif /* PWR_CR3_DSIPDEN */ -#if defined(PWR_CR2_PVME1) -void HAL_PWREx_EnablePVM1(void); -void HAL_PWREx_DisablePVM1(void); -#endif /* PWR_CR2_PVME1 */ -#if defined(PWR_CR2_PVME2) -void HAL_PWREx_EnablePVM2(void); -void HAL_PWREx_DisablePVM2(void); -#endif /* PWR_CR2_PVME2 */ -void HAL_PWREx_EnablePVM3(void); -void HAL_PWREx_DisablePVM3(void); -void HAL_PWREx_EnablePVM4(void); -void HAL_PWREx_DisablePVM4(void); -HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); - - -/* Low Power modes configuration functions ************************************/ -void HAL_PWREx_EnableLowPowerRunMode(void); -HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); -void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); -void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); -void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); -void HAL_PWREx_EnterSHUTDOWNMode(void); - -void HAL_PWREx_PVD_PVM_IRQHandler(void); -#if defined(PWR_CR2_PVME1) -void HAL_PWREx_PVM1Callback(void); -#endif /* PWR_CR2_PVME1 */ -#if defined(PWR_CR2_PVME2) -void HAL_PWREx_PVM2Callback(void); -#endif /* PWR_CR2_PVME2 */ -void HAL_PWREx_PVM3Callback(void); -void HAL_PWREx_PVM4Callback(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L4xx_HAL_PWR_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h deleted file mode 100644 index 9c8014cde..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h +++ /dev/null @@ -1,4594 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rcc.h - * @author MCD Application Team - * @brief Header file of RCC HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_RCC_H -#define __STM32L4xx_HAL_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RCC_Exported_Types RCC Exported Types - * @{ - */ - -/** - * @brief RCC PLL configuration structure definition - */ -typedef struct -{ - uint32_t PLLState; /*!< The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ - - uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. - This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */ - - uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. - This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ - - uint32_t PLLP; /*!< PLLP: Division factor for SAI clock. - This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ - - uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks. - This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ - - uint32_t PLLR; /*!< PLLR: Division for the main system clock. - User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ. - This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ - -}RCC_PLLInitTypeDef; - -/** - * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition - */ -typedef struct -{ - uint32_t OscillatorType; /*!< The oscillators to be configured. - This parameter can be a value of @ref RCC_Oscillator_Type */ - - uint32_t HSEState; /*!< The new state of the HSE. - This parameter can be a value of @ref RCC_HSE_Config */ - - uint32_t LSEState; /*!< The new state of the LSE. - This parameter can be a value of @ref RCC_LSE_Config */ - - uint32_t HSIState; /*!< The new state of the HSI. - This parameter can be a value of @ref RCC_HSI_Config */ - - uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */ - - uint32_t LSIState; /*!< The new state of the LSI. - This parameter can be a value of @ref RCC_LSI_Config */ - - uint32_t MSIState; /*!< The new state of the MSI. - This parameter can be a value of @ref RCC_MSI_Config */ - - uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - - uint32_t MSIClockRange; /*!< The MSI frequency range. - This parameter can be a value of @ref RCC_MSI_Clock_Range */ - - uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices). - This parameter can be a value of @ref RCC_HSI48_Config */ - - RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ - -}RCC_OscInitTypeDef; - -/** - * @brief RCC System, AHB and APB busses clock configuration structure definition - */ -typedef struct -{ - uint32_t ClockType; /*!< The clock to be configured. - This parameter can be a value of @ref RCC_System_Clock_Type */ - - uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). - This parameter can be a value of @ref RCC_System_Clock_Source */ - - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_AHB_Clock_Source */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - - uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - -}RCC_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_Timeout_Value Timeout Values - * @{ - */ -#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT -/** - * @} - */ - -/** @defgroup RCC_Oscillator_Type Oscillator Type - * @{ - */ -#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ -#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ -#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ -#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ -#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ -#define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */ -#if defined(RCC_HSI48_SUPPORT) -#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_HSE_Config HSE Config - * @{ - */ -#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ -#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ -#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ -/** - * @} - */ - -/** @defgroup RCC_LSE_Config LSE Config - * @{ - */ -#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ -#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ -#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ -/** - * @} - */ - -/** @defgroup RCC_HSI_Config HSI Config - * @{ - */ -#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ -#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ - -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) -#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ -#else -#define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */ -#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ -/** - * @} - */ - -/** @defgroup RCC_LSI_Config LSI Config - * @{ - */ -#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ -#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ -/** - * @} - */ - -/** @defgroup RCC_MSI_Config MSI Config - * @{ - */ -#define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ -#define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ - -#define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ -/** - * @} - */ - -#if defined(RCC_HSI48_SUPPORT) -/** @defgroup RCC_HSI48_Config HSI48 Config - * @{ - */ -#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ -#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ -/** - * @} - */ -#else -/** @defgroup RCC_HSI48_Config HSI48 Config - * @{ - */ -#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ -/** - * @} - */ -#endif /* RCC_HSI48_SUPPORT */ - -/** @defgroup RCC_PLL_Config PLL Config - * @{ - */ -#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ -#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ -#define RCC_PLL_ON 0x00000002U /*!< PLL activation */ -/** - * @} - */ - -/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider - * @{ - */ -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) -#define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ -#define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ -#define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ -#define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ -#define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ -#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ -#define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ -#define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ -#define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ -#define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ -#define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ -#define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ -#define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ -#define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ -#define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ -#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ -#define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ -#define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ -#define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ -#define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ -#define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ -#define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ -#define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ -#define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ -#define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ -#define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ -#define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ -#define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ -#define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ -#define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ -#else -#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ -#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ -#endif /* RCC_PLLP_DIV_2_31_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider - * @{ - */ -#define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ -#define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ -#define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ -#define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ -/** - * @} - */ - -/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider - * @{ - */ -#define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ -#define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ -#define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ -#define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source PLL Clock Source - * @{ - */ -#define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ -#define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ -#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ -#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Output PLL Clock Output - * @{ - */ -#if defined(RCC_PLLSAI2_SUPPORT) -#define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */ -#else -#define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */ -#endif /* RCC_PLLSAI2_SUPPORT */ -#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ -#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ -/** - * @} - */ - -/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output - * @{ - */ -#define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */ -#define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */ -#define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */ -/** - * @} - */ - -#if defined(RCC_PLLSAI2_SUPPORT) - -/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output - * @{ - */ -#define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */ -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) -#define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2 */ -#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) -#define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */ -#else -#define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ -/** - * @} - */ - -#endif /* RCC_PLLSAI2_SUPPORT */ - -/** @defgroup RCC_MSI_Clock_Range MSI Clock Range - * @{ - */ -#define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ -#define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ -#define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ -#define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ -#define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ -#define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ -#define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ -#define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ -#define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ -#define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ -#define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ -#define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Type System Clock Type - * @{ - */ -#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ -#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ -#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ -#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source System Clock Source - * @{ - */ -#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ -#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ -#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ -#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status - * @{ - */ -#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source AHB Clock Source - * @{ - */ -#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ -#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ -#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ -#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ -#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ -#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ -#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ -#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ -#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source - * @{ - */ -#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ -#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ -#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ -#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ -#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source RTC Clock Source - * @{ - */ -#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ -/** - * @} - */ - -/** @defgroup RCC_MCO_Index MCO Index - * @{ - */ -#define RCC_MCO1 0x00000000U -#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source - * @{ - */ -#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ -#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ -#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ -#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ -#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ -#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ -#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ -#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ -#if defined(RCC_HSI48_SUPPORT) -#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */ -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler - * @{ - */ -#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ -#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ -#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ -#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ -#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_Interrupt Interrupts - * @{ - */ -#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ -#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ -#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ -#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ -#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ -#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ -#define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ -#if defined(RCC_PLLSAI2_SUPPORT) -#define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ -#endif /* RCC_PLLSAI2_SUPPORT */ -#define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ -#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ -#if defined(RCC_HSI48_SUPPORT) -#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_Flag Flags - * Elements values convention: XXXYYYYYb - * - YYYYY : Flag position in the register - * - XXX : Register index - * - 001: CR register - * - 010: BDCR register - * - 011: CSR register - * - 100: CRRCR register - * @{ - */ -/* Flags in the CR register */ -#define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ -#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ -#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ -#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ -#define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ -#if defined(RCC_PLLSAI2_SUPPORT) -#define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ -#endif /* RCC_PLLSAI2_SUPPORT */ - -/* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ -#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ - -/* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ -#define RCC_FLAG_RMVF ((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos) /*!< Remove reset flag */ -#define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */ -#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ -#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ -#define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ -#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ -#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ -#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ -#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ - -#if defined(RCC_HSI48_SUPPORT) -/* Flags in the CRRCR register */ -#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_LSEDrive_Config LSE Drive Config - * @{ - */ -#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ -#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ -#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ -#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ -/** - * @} - */ - -/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock - * @{ - */ -#define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ -#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TSC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GFXMMU */ - - -#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) - -#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) - -#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) - -#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) -#endif /* GFXMMU */ - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GPIOI */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* HASH */ - -#define __HAL_RCC_RNG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ - - -#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) - -#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) - -#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) -#endif /* GPIOI */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) -#endif /* HASH */ - -#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) -#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ - -/** - * @} - */ - -/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* FMC_BANK1 */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OCTOSPI2 */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) -#endif /* FMC_BANK1 */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) -#endif /* OCTOSPI2 */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable - * @brief Enable or disable the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(LCD) -#define __HAL_RCC_LCD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* LCD */ - -#if defined(RCC_APB1ENR1_RTCAPBEN) -#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* RCC_APB1ENR1_RTCAPBEN */ - -#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(SPI2) -#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(USART3) -#define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* USB */ - -#define __HAL_RCC_PWR_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ - UNUSED(tmpreg); \ - } while(0) - - -#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) - -#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) - -#if defined(LCD) -#define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); -#endif /* LCD */ - -#if defined(RCC_APB1ENR1_RTCAPBEN) -#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); -#endif /* RCC_APB1ENR1_RTCAPBEN */ - -#if defined(SPI2) -#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) - -#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) - -#if defined(USART3) -#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); -#endif /* CRS */ - -#define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); -#endif /* USB */ - -#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) - -#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) - -#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) - -#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) - -#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable - * @brief Enable or disable the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ - -#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ - UNUSED(tmpreg); \ - } while(0) - - -#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* DSI */ - - -#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) - -#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) -#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ - -#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) - -#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) - -#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) - -#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the AHB1 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET) - -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != RESET) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET) - -#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET) - -#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != RESET) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != RESET) -#endif /* GFXMMU */ - - -#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET) - -#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == RESET) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET) - -#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET) - -#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == RESET) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == RESET) -#endif /* GFXMMU */ - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the AHB2 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET) - -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != RESET) - -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != RESET) -#endif /* GPIOI */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != RESET) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != RESET) -#endif /* HASH */ - -#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET) - - -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET) - -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET) - -#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == RESET) -#endif /* GPIOI */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == RESET) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == RESET) -#endif /* HASH */ - -#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET) - -/** - * @} - */ - -/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the AHB3 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET) -#endif /* FMC_BANK1 */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET) -#endif /* QUADSPI */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET) -#endif /* FMC_BANK1 */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET) -#endif /* QUADSPI */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the APB1 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET) - -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET) - -#if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET) -#endif /* LCD */ - -#if defined(RCC_APB1ENR1_RTCAPBEN) -#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET) -#endif /* RCC_APB1ENR1_RTCAPBEN */ - -#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET) - -#if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET) - -#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET) - -#if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != RESET) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != RESET) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET) -#endif /* USB */ - -#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET) - -#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET) - -#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET) - -#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET) - -#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET) - - -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET) - -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET) - -#if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET) -#endif /* LCD */ - -#if defined(RCC_APB1ENR1_RTCAPBEN) -#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET) -#endif /* RCC_APB1ENR1_RTCAPBEN */ - -#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET) - -#if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET) - -#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET) - -#if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == RESET) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == RESET) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET) -#endif /* USB */ - -#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET) - -#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET) - -#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET) - -#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET) - -#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the APB2 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET) - -#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET) - -#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET) -#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ - -#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET) - -#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET) - -#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET) - -#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != RESET) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != RESET) -#endif /* DSI */ - - -#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET) - -#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET) -#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ - -#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET) - -#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET) - -#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET) - -#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == RESET) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == RESET) -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset - * @brief Force or release AHB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) - -#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) - -#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) - -#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) - -#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) -#endif /* GFXMMU */ - - -#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) - -#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) - -#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) - -#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) - -#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) -#endif /* GFXMMU */ - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset - * @brief Force or release AHB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU) - -#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) - -#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) - -#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) -#endif /* GPIOI */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) -#endif /* HASH */ - -#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) -#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) -#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ - - -#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) - -#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) - -#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) - -#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) -#endif /* GPIOI */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) -#endif /* HASH */ - -#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) -#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) -#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ - -/** - * @} - */ - -/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset - * @brief Force or release AHB3 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU) - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) -#endif /* FMC_BANK1 */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) -#endif /* OCTOSPI2 */ - -#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) -#endif /* FMC_BANK1 */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) -#endif /* OCTOSPI2 */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU) - -#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) - -#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) - -#if defined(LCD) -#define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) -#endif /* LCD */ - -#if defined(SPI2) -#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) - -#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) - -#if defined(USART3) -#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) -#endif /* USB */ - -#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) - -#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) - -#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) - -#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) - -#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) - - -#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U) - -#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) - -#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) - -#if defined(LCD) -#define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) -#endif /* LCD */ - -#if defined(SPI2) -#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) - -#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) - -#if defined(USART3) -#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) -#endif /* USB */ - -#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) - -#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) - -#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) - -#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) - -#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) - -#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) - -#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) -#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) -#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ - -#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) - -#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) - -#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) - -#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) -#endif /* DSI */ - - -#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) - -#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) - -#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) -#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) -#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ - -#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) - -#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) - -#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) - -#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) - -#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) - -#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) - -#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) - -#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) -#endif /* GFXMMU */ - - -#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) - -#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) - -#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) - -#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) - -#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) -#endif /* GFXMMU */ - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) - -#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) - -#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) -#endif /* GPIOI */ - -#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) - -#if defined(SRAM3) -#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) -#endif /* SRAM3 */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) -#endif /* HASH */ - -#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) -#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ - - -#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) - -#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) - -#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) -#endif /* GPIOI */ - -#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) - -#if defined(SRAM3) -#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) -#endif /* SRAM3 */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) -#endif /* HASH */ - -#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) -#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ - -/** - * @} - */ - -/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) -#endif /* OCTOSPI2 */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) -#endif /* FMC_BANK1 */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) -#endif /* OCTOSPI2 */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) -#endif /* FMC_BANK1 */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) - -#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) - -#if defined(LCD) -#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) -#endif /* LCD */ - -#if defined(RCC_APB1SMENR1_RTCAPBSMEN) -#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) -#endif /* RCC_APB1SMENR1_RTCAPBSMEN */ - -#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) - -#if defined(SPI2) -#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) - -#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) - -#if defined(USART3) -#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) -#endif /* USB */ - -#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) - -#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) - -#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) - -#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) - -#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) - - -#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) - -#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) - -#if defined(LCD) -#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) -#endif /* LCD */ - -#if defined(RCC_APB1SMENR1_RTCAPBSMEN) -#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) -#endif /* RCC_APB1SMENR1_RTCAPBSMEN */ - -#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) - -#if defined(SPI2) -#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) - -#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) - -#if defined(USART3) -#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) -#endif /* USB */ - -#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) - -#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) - -#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) - -#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) - -#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) - -#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) -#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ - -#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) - -#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) - -#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) - -#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) -#endif /* DSI */ - - -#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) - -#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) -#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ - -#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) - -#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) - -#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) - -#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status - * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET) - -#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET) - -#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET) - -#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET) - -#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != RESET) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != RESET) -#endif /* GFXMMU */ - - -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET) - -#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET) - -#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET) - -#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET) - -#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == RESET) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == RESET) -#endif /* GFXMMU */ - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status - * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET) - -#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET) - -#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != RESET) -#endif /* GPIOI */ - -#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET) - -#if defined(SRAM3) -#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != RESET) -#endif /* SRAM3 */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != RESET) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != RESET) -#endif /* HASH */ - -#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != RESET) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != RESET) -#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ - - -#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET) - -#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET) - -#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == RESET) -#endif /* GPIOI */ - -#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET) - -#if defined(SRAM3) -#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == RESET) -#endif /* SRAM3 */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == RESET) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == RESET) -#endif /* HASH */ - -#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == RESET) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == RESET) -#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ - -/** - * @} - */ - -/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status - * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != RESET) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != RESET) -#endif /* OCTOSPI2 */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET) -#endif /* FMC_BANK1 */ - - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == RESET) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == RESET) -#endif /* OCTOSPI2 */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET) -#endif /* FMC_BANK1 */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status - * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET) - -#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET) - -#if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET) -#endif /* LCD */ - -#if defined(RCC_APB1SMENR1_RTCAPBSMEN) -#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET) -#endif /* RCC_APB1SMENR1_RTCAPBSMEN */ - -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET) - -#if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET) - -#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET) - -#if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != RESET) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != RESET) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET) -#endif /* USB */ - -#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET) - -#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET) - -#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET) - -#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET) - -#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET) - - -#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET) - -#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET) - -#if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET) -#endif /* LCD */ - -#if defined(RCC_APB1SMENR1_RTCAPBSMEN) -#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET) -#endif /* RCC_APB1SMENR1_RTCAPBSMEN */ - -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET) - -#if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET) - -#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET) - -#if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == RESET) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == RESET) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET) -#endif /* USB */ - -#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET) - -#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET) - -#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET) - -#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET) - -#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status - * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET) - -#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET) -#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ - -#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET) - -#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET) - -#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET) - -#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != RESET) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != RESET) -#endif /* DSI */ - - -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET) - -#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET) -#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ - -#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET) - -#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET) - -#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET) - -#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == RESET) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == RESET) -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset - * @{ - */ - -/** @brief Macros to force or release the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - * @retval None - */ -#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) - -#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) - -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration - * @{ - */ - -/** @brief Macros to enable or disable the RTC clock. - * @note As the RTC is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * HAL_PWR_EnableBkUpAccess() function before to configure the RTC - * (to be done once after reset). - * @note These macros must be used after the RTC clock source was selected. - * @retval None - */ -#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) - -#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) - -/** - * @} - */ - -/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - * @retval None - */ -#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) - -#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) - -/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value - * (default is RCC_HSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices). - * @retval None - */ -#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ - MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) - -/** - * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) - * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. - * @note The enable of this function has not effect on the HSION bit. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS) - -#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS) - -/** - * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) - * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. - * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication - * speed because of the HSI startup time. - * @note The enable of this function has not effect on the HSION bit. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) - -#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) - -/** - * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). - * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after - * startup from Reset, wakeup from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * @note MSI can not be stopped if it is used as system clock source. - * In this case, you have to select another source of the system - * clock then stop the MSI. - * @note After enabling the MSI, the application software should wait on - * MSIRDY flag to be set indicating that MSI clock is stable and can - * be used as system clock source. - * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator - * clock cycles. - * @retval None - */ -#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) - -#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) - -/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal MSI RC. - * Refer to the Application Note AN3300 for more details on how to - * calibrate the MSI. - * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value - * (default is RCC_MSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 255. - * @retval None - */ -#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ - MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos) - -/** - * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode - * @note After restart from Reset , the MSI clock is around 4 MHz. - * After stop the startup clock can be MSI (at any of its possible - * frequencies, the one that was used before entering stop mode) or HSI. - * After Standby its frequency can be selected between 4 possible values - * (1, 2, 4 or 8 MHz). - * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready - * (MSIRDY=1). - * @note The MSI clock range after reset can be modified on the fly. - * @param __MSIRANGEVALUE__ specifies the MSI clock range. - * This parameter must be one of the following values: - * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz - * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz - * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz - * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz - * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz - * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) - * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz - * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz - * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz - * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz - * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz - * @retval None - */ -#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ - do { \ - SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ - MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ - } while(0) - -/** - * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode - * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). - * @param __MSIRANGEVALUE__ specifies the MSI clock range. - * This parameter must be one of the following values: - * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz - * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) - * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz - * @retval None - */ -#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \ - MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) - -/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode - * @retval MSI clock range. - * This parameter must be one of the following values: - * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz - * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz - * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz - * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz - * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz - * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) - * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz - * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz - * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz - * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz - * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz - */ -#define __HAL_RCC_GET_MSI_RANGE() \ - ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \ - READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \ - READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U) - -/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - * @retval None - */ -#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) - -#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) - -/** - * @brief Macro to configure the External High Speed oscillator (HSE). - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param __STATE__ specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. - * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. - * @retval None - */ -#define __HAL_RCC_HSE_CONFIG(__STATE__) \ - do { \ - if((__STATE__) == RCC_HSE_ON) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else if((__STATE__) == RCC_HSE_BYPASS) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - } while(0) - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this macro. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param __STATE__ specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. - * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. - * @retval None - */ -#define __HAL_RCC_LSE_CONFIG(__STATE__) \ - do { \ - if((__STATE__) == RCC_LSE_ON) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else if((__STATE__) == RCC_LSE_BYPASS) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - } while(0) - -#if defined(RCC_HSI48_SUPPORT) - -/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). - * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. - * @note After enabling the HSI48, the application software should wait on HSI48RDY - * flag to be set indicating that HSI48 clock is stable. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) - -#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) - -#endif /* RCC_HSI48_SUPPORT */ - -/** @brief Macros to configure the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it cannot be changed unless the - * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by - * a Power On Reset (POR). - * - * @param __RTC_CLKSOURCE__ specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected - * - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - * @retval None - */ -#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ - MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) - - -/** @brief Macro to get the RTC clock source. - * @retval The returned value can be one of the following: - * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected - */ -#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) - -/** @brief Macros to enable or disable the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - * @retval None - */ -#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) - -#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) - -/** @brief Macro to configure the PLL clock source. - * @note This function must be used only when the main PLL is disabled. - * @param __PLLSOURCE__ specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry - * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). - * @retval None - * - */ -#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) - -/** @brief Macro to configure the PLL source division factor M. - * @note This function must be used only when the main PLL is disabled. - * @param __PLLM__ specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. - * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency - * of 16 MHz to limit PLL jitter. - * @retval None - * - */ -#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U) - -/** - * @brief Macro to configure the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param __PLLSOURCE__ specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry - * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). - * - * @param __PLLM__ specifies the division factor for PLL VCO input clock. - * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. - * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency - * of 16 MHz to limit PLL jitter. - * - * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. - * This parameter must be a number between 8 and 86. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 64 and 344 MHz. - * - * @param __PLLP__ specifies the division factor for SAI clock. - * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x - * else (2 to 31). - * - * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. - * This parameter must be in the range (2, 4, 6 or 8). - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - * @param __PLLR__ specifies the division factor for the main system clock. - * @note You have to set the PLLR parameter correctly to not exceed 80MHZ. - * This parameter must be in the range (2, 4, 6 or 8). - * @retval None - */ -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - -#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ - (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ - (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ - ((uint32_t)(__PLLP__) << 27U)) -#else - -#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ - (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ - (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ - (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) - -#endif /* RCC_PLLP_DIV_2_31_SUPPORT */ - -/** @brief Macro to get the oscillator used as PLL clock source. - * @retval The oscillator used as PLL clock source. The returned value can be one - * of the following: - * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. - */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) - -/** - * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) - * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime - * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot - * be stopped if used as System Clock. - * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. - * This parameter can be one or a combination of the following values: - * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), - * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). - * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) - * @retval None - */ -#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) - -#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) - -/** - * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) - * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. - * This parameter can be one of the following values: - * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), - * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). - * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) - * @retval SET / RESET - */ -#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) - -/** - * @brief Macro to configure the system clock source. - * @param __SYSCLKSOURCE__ specifies the system clock source. - * This parameter can be one of the following values: - * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. - * @retval None - */ -#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) - -/** @brief Macro to get the clock source used as system clock. - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. - * This parameter can be one of the following values: - * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. - * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. - * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. - * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. - * @retval None - */ -#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) - -/** - * @brief Macro to configure the wake up from stop clock. - * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. - * This parameter can be one of the following values: - * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source - * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source - * @retval None - */ -#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) - - -/** @brief Macro to configure the MCO clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled - * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee - * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source - @if STM32L443xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 - @endif - @if STM32L4A6xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 - @endif - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 - * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 - * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 - * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 - * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 - */ -#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) - -/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management - * @brief macros to manage the specified RCC Flags and interrupts. - * @{ - */ - -/** @brief Enable RCC interrupt(s). - * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_MSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt - * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 - * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt - @if STM32L443xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - @if STM32L4A6xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - * @retval None - */ -#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) - -/** @brief Disable RCC interrupt(s). - * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_MSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt - * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 - * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt - @if STM32L443xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - @if STM32L4A6xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - * @retval None - */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) - -/** @brief Clear the RCC's interrupt pending bits. - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_MSIRDY MSI ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt - * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 - * @arg @ref RCC_IT_CSS HSE Clock security system interrupt - * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt - @if STM32L443xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - @if STM32L4A6xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - * @retval None - */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) - -/** @brief Check whether the RCC interrupt has occurred or not. - * @param __INTERRUPT__ specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_MSIRDY MSI ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt - * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 - * @arg @ref RCC_IT_CSS HSE Clock security system interrupt - * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt - @if STM32L443xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - @if STM32L4A6xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) - -/** @brief Set RMVF bit to clear the reset flags. - * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, - * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. - * @retval None - */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) - -/** @brief Check whether the selected RCC flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready - * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready - * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready - * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready - * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready - * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2 - @if STM32L443xx - * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 - @endif - @if STM32L4A6xx - * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 - @endif - * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready - * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection - * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready - * @arg @ref RCC_FLAG_BORRST BOR reset - * @arg @ref RCC_FLAG_OBLRST OBLRST reset - * @arg @ref RCC_FLAG_PINRST Pin reset - * @arg @ref RCC_FLAG_FWRST FIREWALL reset - * @arg @ref RCC_FLAG_RMVF Remove reset Flag - * @arg @ref RCC_FLAG_SFTRST Software reset - * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset - * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset - * @arg @ref RCC_FLAG_LPWRRST Low Power reset - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#if defined(RCC_HSI48_SUPPORT) -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ - ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ - ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ - ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ - (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) -#else -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ - ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ - ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ - (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) -#endif /* RCC_HSI48_SUPPORT */ - -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Constants RCC Private Constants - * @{ - */ -/* Defines used for Flags */ -#define CR_REG_INDEX 1U -#define BDCR_REG_INDEX 2U -#define CSR_REG_INDEX 3U -#if defined(RCC_HSI48_SUPPORT) -#define CRRCR_REG_INDEX 4U -#endif /* RCC_HSI48_SUPPORT */ - -#define RCC_FLAG_MASK 0x1FU -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCC_Private_Macros - * @{ - */ - -#if defined(RCC_HSI48_SUPPORT) -#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) -#else -#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) -#endif /* RCC_HSI48_SUPPORT */ - -#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ - ((__HSE__) == RCC_HSE_BYPASS)) - -#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ - ((__LSE__) == RCC_LSE_BYPASS)) - -#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) - -#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) - -#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) - -#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) - -#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) - -#if defined(RCC_HSI48_SUPPORT) -#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) -#endif /* RCC_HSI48_SUPPORT */ - -#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ - ((__PLL__) == RCC_PLL_ON)) - -#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ - ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ - ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ - ((__SOURCE__) == RCC_PLLSOURCE_HSE)) - -#if defined(RCC_PLLM_DIV_1_16_SUPPORT) -#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) -#else -#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) -#endif /*RCC_PLLM_DIV_1_16_SUPPORT */ - -#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) - -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) -#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) -#else -#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) -#endif /*RCC_PLLP_DIV_2_31_SUPPORT */ - -#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ - ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) - -#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ - ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) - -#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ - (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \ - (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \ - (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) - -#if defined(RCC_PLLSAI2_SUPPORT) -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) -#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ - (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \ - (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) -#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ - (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \ - (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \ - (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U)) -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ -#endif /* RCC_PLLSAI2_SUPPORT */ - -#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ - ((__RANGE__) == RCC_MSIRANGE_1) || \ - ((__RANGE__) == RCC_MSIRANGE_2) || \ - ((__RANGE__) == RCC_MSIRANGE_3) || \ - ((__RANGE__) == RCC_MSIRANGE_4) || \ - ((__RANGE__) == RCC_MSIRANGE_5) || \ - ((__RANGE__) == RCC_MSIRANGE_6) || \ - ((__RANGE__) == RCC_MSIRANGE_7) || \ - ((__RANGE__) == RCC_MSIRANGE_8) || \ - ((__RANGE__) == RCC_MSIRANGE_9) || \ - ((__RANGE__) == RCC_MSIRANGE_10) || \ - ((__RANGE__) == RCC_MSIRANGE_11)) - -#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ - ((__RANGE__) == RCC_MSIRANGE_5) || \ - ((__RANGE__) == RCC_MSIRANGE_6) || \ - ((__RANGE__) == RCC_MSIRANGE_7)) - -#define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U)) - -#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) - -#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ - ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ - ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ - ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ - ((__HCLK__) == RCC_SYSCLK_DIV512)) - -#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ - ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ - ((__PCLK__) == RCC_HCLK_DIV16)) - -#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) - -#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) - -#if defined(RCC_HSI48_SUPPORT) -#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) -#else -#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) -#endif /* RCC_HSI48_SUPPORT */ - -#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ - ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ - ((__DIV__) == RCC_MCODIV_16)) - -#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ - ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ - ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ - ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) - -#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ - ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) -/** - * @} - */ - -/* Include RCC HAL Extended module */ -#include "stm32l4xx_hal_rcc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCC_Exported_Functions - * @{ - */ - - -/** @addtogroup RCC_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); - -/** - * @} - */ - -/** @addtogroup RCC_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); -void HAL_RCC_EnableCSS(void); -uint32_t HAL_RCC_GetSysClockFreq(void); -uint32_t HAL_RCC_GetHCLKFreq(void); -uint32_t HAL_RCC_GetPCLK1Freq(void); -uint32_t HAL_RCC_GetPCLK2Freq(void); -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); -/* CSS NMI IRQ handler */ -void HAL_RCC_NMI_IRQHandler(void); -/* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CSSCallback(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_RCC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h deleted file mode 100644 index b0000a7ab..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h +++ /dev/null @@ -1,3018 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rcc_ex.h - * @author MCD Application Team - * @brief Header file of RCC HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_RCC_EX_H -#define __STM32L4xx_HAL_RCC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Types RCCEx Exported Types - * @{ - */ - -/** - * @brief PLLSAI1 Clock structure definition - */ -typedef struct -{ - - uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ -#else - uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ -#endif - - uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. - This parameter must be a number between 8 and 86 or 127 depending on devices. */ - - uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock. - This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ - - uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock. - This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ - - uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock. - This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ - - uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. - This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ -}RCC_PLLSAI1InitTypeDef; - -#if defined(RCC_PLLSAI2_SUPPORT) - -/** - * @brief PLLSAI2 Clock structure definition - */ -typedef struct -{ - - uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ -#else - uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ -#endif - - uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock. - This parameter must be a number between 8 and 86 or 127 depending on devices. */ - - uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock. - This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ - -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) - uint32_t PLLSAI2Q; /*!< PLLSAI2Q: specifies the division factor for DSI clock. - This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ -#endif - - uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock. - This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ - - uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled. - This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */ -}RCC_PLLSAI2InitTypeDef; - -#endif /* RCC_PLLSAI2_SUPPORT */ - -/** - * @brief RCC extended clocks structure definition - */ -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. - This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */ - -#if defined(RCC_PLLSAI2_SUPPORT) - - RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters. - This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */ - -#endif /* RCC_PLLSAI2_SUPPORT */ - - uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. - This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ - - uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. - This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ - -#if defined(USART3) - - uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. - This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ - -#endif /* USART3 */ - -#if defined(UART4) - - uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. - This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ - -#endif /* UART4 */ - -#if defined(UART5) - - uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. - This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ - -#endif /* UART5 */ - - uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. - This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. - This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ - -#if defined(I2C2) - - uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. - This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ - -#endif /* I2C2 */ - - uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. - This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ - -#if defined(I2C4) - - uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. - This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ - -#endif /* I2C4 */ - - uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. - This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ - - uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. - This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ - - uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. - This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ - -#if defined(SAI2) - - uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. - This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ - -#endif /* SAI2 */ - -#if defined(USB_OTG_FS) || defined(USB) - - uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG). - This parameter can be a value of @ref RCCEx_USB_Clock_Source */ - -#endif /* USB_OTG_FS || USB */ - -#if defined(SDMMC1) - - uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG). - This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ - -#endif /* SDMMC1 */ - - uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1). - This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ - - uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. - This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ - -#if defined(SWPMI1) - - uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source. - This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */ - -#endif /* SWPMI1 */ - -#if defined(DFSDM1_Filter0) - - uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source. - This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source. - This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) - - uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source. - This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ - -#endif /* LTDC */ - -#if defined(DSI) - - uint32_t DsiClockSelection; /*!< Specifies DSI clock source. - This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ - -#endif /* DSI */ - -#if defined(OCTOSPI1) || defined(OCTOSPI2) - - uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. - This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ - -#endif - - uint32_t RTCClockSelection; /*!< Specifies RTC clock source. - This parameter can be a value of @ref RCC_RTC_Clock_Source */ -}RCC_PeriphCLKInitTypeDef; - -#if defined(CRS) - -/** - * @brief RCC_CRS Init structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. - This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ - - uint32_t Source; /*!< Specifies the SYNC signal source. - This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ - - uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. - This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ - - uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. - It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) - This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ - - uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. - This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ - - uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. - This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ - -}RCC_CRSInitTypeDef; - -/** - * @brief RCC_CRS Synchronization structure definition - */ -typedef struct -{ - uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. - This parameter must be a number between 0 and 0xFFFF */ - - uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. - This parameter must be a number between 0 and 0x3F */ - - uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter - value latched in the time of the last SYNC event. - This parameter must be a number between 0 and 0xFFFF */ - - uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the - frequency error counter latched in the time of the last SYNC event. - It shows whether the actual frequency is below or above the target. - This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ - -}RCC_CRSSynchroInfoTypeDef; - -#endif /* CRS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants - * @{ - */ - -/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source - * @{ - */ -#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ -#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ -/** - * @} - */ - -/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection - * @{ - */ -#define RCC_PERIPHCLK_USART1 0x00000001U -#define RCC_PERIPHCLK_USART2 0x00000002U -#if defined(USART3) -#define RCC_PERIPHCLK_USART3 0x00000004U -#endif -#if defined(UART4) -#define RCC_PERIPHCLK_UART4 0x00000008U -#endif -#if defined(UART5) -#define RCC_PERIPHCLK_UART5 0x00000010U -#endif -#define RCC_PERIPHCLK_LPUART1 0x00000020U -#define RCC_PERIPHCLK_I2C1 0x00000040U -#if defined(I2C2) -#define RCC_PERIPHCLK_I2C2 0x00000080U -#endif -#define RCC_PERIPHCLK_I2C3 0x00000100U -#define RCC_PERIPHCLK_LPTIM1 0x00000200U -#define RCC_PERIPHCLK_LPTIM2 0x00000400U -#define RCC_PERIPHCLK_SAI1 0x00000800U -#if defined(SAI2) -#define RCC_PERIPHCLK_SAI2 0x00001000U -#endif -#if defined(USB_OTG_FS) || defined(USB) -#define RCC_PERIPHCLK_USB 0x00002000U -#endif -#define RCC_PERIPHCLK_ADC 0x00004000U -#if defined(SWPMI1) -#define RCC_PERIPHCLK_SWPMI1 0x00008000U -#endif -#if defined(DFSDM1_Filter0) -#define RCC_PERIPHCLK_DFSDM1 0x00010000U -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#endif -#define RCC_PERIPHCLK_RTC 0x00020000U -#define RCC_PERIPHCLK_RNG 0x00040000U -#if defined(SDMMC1) -#define RCC_PERIPHCLK_SDMMC1 0x00080000U -#endif -#if defined(I2C4) -#define RCC_PERIPHCLK_I2C4 0x00100000U -#endif -#if defined(LTDC) -#define RCC_PERIPHCLK_LTDC 0x00400000U -#endif -#if defined(DSI) -#define RCC_PERIPHCLK_DSI 0x00800000U -#endif -#if defined(OCTOSPI1) || defined(OCTOSPI2) -#define RCC_PERIPHCLK_OSPI 0x01000000U -#endif -/** - * @} - */ - - -/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source - * @{ - */ -#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U -#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 -#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 -#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) -/** - * @} - */ - -/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source - * @{ - */ -#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U -#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 -#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 -#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) -/** - * @} - */ - -#if defined(USART3) -/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source - * @{ - */ -#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U -#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 -#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 -#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) -/** - * @} - */ -#endif /* USART3 */ - -#if defined(UART4) -/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source - * @{ - */ -#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U -#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 -#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 -#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) -/** - * @} - */ -#endif /* UART4 */ - -#if defined(UART5) -/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source - * @{ - */ -#define RCC_UART5CLKSOURCE_PCLK1 0x00000000U -#define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 -#define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 -#define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) -/** - * @} - */ -#endif /* UART5 */ - -/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source - * @{ - */ -#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U -#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 -#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 -#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) -/** - * @} - */ - -/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source - * @{ - */ -#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U -#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 -#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 -/** - * @} - */ - -#if defined(I2C2) -/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source - * @{ - */ -#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U -#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 -#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 -/** - * @} - */ -#endif /* I2C2 */ - -/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source - * @{ - */ -#define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U -#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 -#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 -/** - * @} - */ - -#if defined(I2C4) -/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source - * @{ - */ -#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U -#define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 -#define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 -/** - * @} - */ -#endif /* I2C4 */ - -/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source - * @{ - */ -#define RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U -#if defined(RCC_PLLSAI2_SUPPORT) -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0 -#else -#define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0 -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#endif /* RCC_PLLSAI2_SUPPORT */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR2_SAI1SEL_1 -#define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) -#define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 -#else -#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1 -#define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -/** - * @} - */ - -#if defined(SAI2) -/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source - * @{ - */ -#define RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0 -#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 -#define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) -#define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 -#else -#define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0 -#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1 -#define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -/** - * @} - */ -#endif /* SAI2 */ - -/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source - * @{ - */ -#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U -#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 -#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 -#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL -/** - * @} - */ - -/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source - * @{ - */ -#define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U -#define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 -#define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 -#define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL -/** - * @} - */ - -#if defined(SDMMC1) -/** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source - * @{ - */ -#if defined(RCC_HSI48_SUPPORT) -#define RCC_SDMMC1CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock selected as SDMMC1 clock */ -#else -#define RCC_SDMMC1CLKSOURCE_NONE 0x00000000U /*!< No clock selected as SDMMC1 clock */ -#endif /* RCC_HSI48_SUPPORT */ -#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */ -#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */ -#define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock selected as SDMMC1 clock */ -#if defined(RCC_CCIPR2_SDMMCSEL) -#define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLL "P" clock selected as SDMMC1 kernel clock */ -#endif /* RCC_CCIPR2_SDMMCSEL */ -/** - * @} - */ -#endif /* SDMMC1 */ - -/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source - * @{ - */ -#if defined(RCC_HSI48_SUPPORT) -#define RCC_RNGCLKSOURCE_HSI48 0x00000000U -#else -#define RCC_RNGCLKSOURCE_NONE 0x00000000U -#endif /* RCC_HSI48_SUPPORT */ -#define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 -#define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 -#define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL -/** - * @} - */ - -#if defined(USB_OTG_FS) || defined(USB) -/** @defgroup RCCEx_USB_Clock_Source USB Clock Source - * @{ - */ -#if defined(RCC_HSI48_SUPPORT) -#define RCC_USBCLKSOURCE_HSI48 0x00000000U -#else -#define RCC_USBCLKSOURCE_NONE 0x00000000U -#endif /* RCC_HSI48_SUPPORT */ -#define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 -#define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 -#define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL -/** - * @} - */ -#endif /* USB_OTG_FS || USB */ - -/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source - * @{ - */ -#define RCC_ADCCLKSOURCE_NONE 0x00000000U -#define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) -#define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ -#define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL -/** - * @} - */ - -#if defined(SWPMI1) -/** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source - * @{ - */ -#define RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U -#define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL -/** - * @} - */ -#endif /* SWPMI1 */ - -#if defined(DFSDM1_Filter0) -/** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source - * @{ - */ -#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL -#else -#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -/** - * @} - */ - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source - * @{ - */ -#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0x00000000U -#define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 -#define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 -/** - * @} - */ -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -/** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source - * @{ - */ -#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 0x00000000U -#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 -#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 -#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR -/** - * @} - */ -#endif /* LTDC */ - -#if defined(DSI) -/** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source - * @{ - */ -#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U -#define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL -/** - * @} - */ -#endif /* DSI */ - -#if defined(OCTOSPI1) || defined(OCTOSPI2) -/** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source - * @{ - */ -#define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U -#define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 -#define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 -/** - * @} - */ -#endif /* OCTOSPI1 || OCTOSPI2 */ - -/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line - * @{ - */ -#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ -/** - * @} - */ - -#if defined(CRS) - -/** @defgroup RCCEx_CRS_Status RCCEx CRS Status - * @{ - */ -#define RCC_CRS_NONE 0x00000000U -#define RCC_CRS_TIMEOUT 0x00000001U -#define RCC_CRS_SYNCOK 0x00000002U -#define RCC_CRS_SYNCWARN 0x00000004U -#define RCC_CRS_SYNCERR 0x00000008U -#define RCC_CRS_SYNCMISS 0x00000010U -#define RCC_CRS_TRIMOVF 0x00000020U -/** - * @} - */ - -/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource - * @{ - */ -#define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ -#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ -#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider - * @{ - */ -#define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ -#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ -#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ -#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ -#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ -#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ -#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ -#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity - * @{ - */ -#define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ -#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault - * @{ - */ -#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds - to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault - * @{ - */ -#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault - * @{ - */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. - The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value - corresponds to a higher output frequency */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection - * @{ - */ -#define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ -#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources - * @{ - */ -#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ -#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ -#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ -#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ -#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ -#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ -#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ - -/** - * @} - */ - -/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags - * @{ - */ -#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ -#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ -#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ -#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ -#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ -#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ -#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros - * @{ - */ - - -/** - * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. - * - * @note This function must be used only when the PLLSAI1 is disabled. - * @note PLLSAI1 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - @if STM32L4S9xx - * @param __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock. - * This parameter must be a number between Min_Data = 1 and Max_Data = 16. - * - @endif - * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. - * This parameter must be a number between 8 and 86. - * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO - * output frequency is between 64 and 344 MHz. - * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N - * - * @param __PLLSAI1P__ specifies the division factor for SAI clock. - * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx - * else (2 to 31). - * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P - * - * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. - * This parameter must be in the range (2, 4, 6 or 8). - * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q - * - * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock. - * This parameter must be in the range (2, 4, 6 or 8). - * ADC clock frequency = f(PLLSAI1) / PLLSAI1R - * - * @retval None - */ -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - -#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ - ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | \ - (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) - -#else - -#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ - (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ - (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) - -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ - -#else - -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - -#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ - ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) - -#else - -#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ - (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)) - -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ - -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - -/** - * @brief Macro to configure the PLLSAI1 clock multiplication factor N. - * - * @note This function must be used only when the PLLSAI1 is disabled. - * @note PLLSAI1 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. - * This parameter must be a number between 8 and 86. - * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO - * output frequency is between 64 and 344 MHz. - * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N - * - * @retval None - */ -#define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) - -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - -/** @brief Macro to configure the PLLSAI1 input clock division factor M. - * - * @note This function must be used only when the PLLSAI1 is disabled. - * @note PLLSAI1 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI1M__ specifies the division factor for PLLSAI1 clock. - * This parameter must be a number between Min_Data = 1 and Max_Data = 16. - * - * @retval None - */ - -#define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) - -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - -/** @brief Macro to configure the PLLSAI1 clock division factor P. - * - * @note This function must be used only when the PLLSAI1 is disabled. - * @note PLLSAI1 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI1P__ specifies the division factor for SAI clock. - * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx - * else (2 to 31). - * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P - * - * @retval None - */ -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - -#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) - -#else - -#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) - -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ - -/** @brief Macro to configure the PLLSAI1 clock division factor Q. - * - * @note This function must be used only when the PLLSAI1 is disabled. - * @note PLLSAI1 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. - * This parameter must be in the range (2, 4, 6 or 8). - * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q - * - * @retval None - */ -#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) - -/** @brief Macro to configure the PLLSAI1 clock division factor R. - * - * @note This function must be used only when the PLLSAI1 is disabled. - * @note PLLSAI1 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI1R__ specifies the division factor for ADC clock. - * This parameter must be in the range (2, 4, 6 or 8) - * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R - * - * @retval None - */ -#define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) - -/** - * @brief Macros to enable or disable the PLLSAI1. - * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. - * @retval None - */ - -#define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON) - -#define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON) - -/** - * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). - * @note Enabling and disabling those clocks can be done without the need to stop the PLL. - * This is mainly used to save Power. - * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. - * This parameter can be one or a combination of the following values: - * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), - * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). - * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. - * @retval None - */ - -#define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) - -#define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) - -/** - * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). - * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. - * This parameter can be one of the following values: - * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), - * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). - * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. - * @retval SET / RESET - */ -#define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) - -#if defined(RCC_PLLSAI2_SUPPORT) - -/** - * @brief Macro to configure the PLLSAI2 clock multiplication and division factors. - * - * @note This function must be used only when the PLLSAI2 is disabled. - * @note PLLSAI2 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - @if STM32L4S9xx - * @param __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock. - * This parameter must be a number between Min_Data = 1 and Max_Data = 16. - * - @endif - * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. - * This parameter must be a number between 8 and 86. - * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO - * output frequency is between 64 and 344 MHz. - * - * @param __PLLSAI2P__ specifies the division factor for SAI clock. - * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx - * else (2 to 31). - * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P - * - @if STM32L4S9xx - * @param __PLLSAI2Q__ specifies the division factor for DSI clock. - * This parameter must be in the range (2, 4, 6 or 8). - * DSI clock frequency = f(PLLSAI2) / PLLSAI2Q - * - @endif - * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock. - * This parameter must be in the range (2, 4, 6 or 8). - * - * @retval None - */ - -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - -# if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) - -#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ - (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) - -# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) - -#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ - (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) - -# else - -#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) - -# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ - -#else - -# if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) - -#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) - -# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) - -#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) - -# else - -#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)) - -# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ - -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - - -/** - * @brief Macro to configure the PLLSAI2 clock multiplication factor N. - * - * @note This function must be used only when the PLLSAI2 is disabled. - * @note PLLSAI2 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. - * This parameter must be a number between 8 and 86. - * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO - * output frequency is between 64 and 344 MHz. - * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N - * - * @retval None - */ -#define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) - -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - -/** @brief Macro to configure the PLLSAI2 input clock division factor M. - * - * @note This function must be used only when the PLLSAI2 is disabled. - * @note PLLSAI2 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI2M__ specifies the division factor for PLLSAI2 clock. - * This parameter must be a number between Min_Data = 1 and Max_Data = 16. - * - * @retval None - */ - -#define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) - -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - -/** @brief Macro to configure the PLLSAI2 clock division factor P. - * - * @note This function must be used only when the PLLSAI2 is disabled. - * @note PLLSAI2 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI2P__ specifies the division factor. - * This parameter must be a number in the range (7 or 17). - * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__ - * - * @retval None - */ -#define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) - -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) - -/** @brief Macro to configure the PLLSAI2 clock division factor Q. - * - * @note This function must be used only when the PLLSAI2 is disabled. - * @note PLLSAI2 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI2Q__ specifies the division factor for USB/RNG/SDMMC1 clock. - * This parameter must be in the range (2, 4, 6 or 8). - * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI2) / PLLSAI2Q - * - * @retval None - */ -#define __HAL_RCC_PLLSAI2_DIVQ_CONFIG(__PLLSAI2Q__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) - -#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ - -/** @brief Macro to configure the PLLSAI2 clock division factor R. - * - * @note This function must be used only when the PLLSAI2 is disabled. - * @note PLLSAI2 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI2R__ specifies the division factor. - * This parameter must be in the range (2, 4, 6 or 8). - * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__ - * - * @retval None - */ -#define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) - -/** - * @brief Macros to enable or disable the PLLSAI2. - * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes. - * @retval None - */ - -#define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON) - -#define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON) - -/** - * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). - * @note Enabling and disabling those clocks can be done without the need to stop the PLL. - * This is mainly used to save Power. - * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. - * This parameter can be one or a combination of the following values: - @if STM32L486xx - * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. - @endif - @if STM32L4A6xx - * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. - @endif - @if STM32L4S9xx - * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. - @endif - * @retval None - */ - -#define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) - -#define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) - -/** - * @brief Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). - * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. - * This parameter can be one of the following values: - @if STM32L486xx - * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. - @endif - @if STM32L4A6xx - * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. - @endif - @if STM32L4S9xx - * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. - @endif - * @retval SET / RESET - */ -#define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) - -#endif /* RCC_PLLSAI2_SUPPORT */ - -/** - * @brief Macro to configure the SAI1 clock source. - * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived - * from the PLLSAI1, system PLL or external clock (through a dedicated pin). - * This parameter can be one of the following values: - * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) - @if STM32L486xx - * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 - @endif - * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) - * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) - @if STM32L4S9xx - * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 - @endif - * - @if STM32L443xx - * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2. - @endif - * - * @retval None - */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__)) -#else -#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** @brief Macro to get the SAI1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) - @if STM32L486xx - * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 - @endif - * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) - * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) - * - * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 - * clock source when PLLs are disabled for devices without PLLSAI2. - * - */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL)) -#else -#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#if defined(SAI2) - -/** - * @brief Macro to configure the SAI2 clock source. - * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived - * from the PLLSAI2, system PLL or external clock (through a dedicated pin). - * This parameter can be one of the following values: - * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) - @if STM32L4S9xx - * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 - @endif - * - * @retval None - */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__)) -#else -#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** @brief Macro to get the SAI2 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) - */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL)) -#else -#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* SAI2 */ - -/** @brief Macro to configure the I2C1 clock (I2C1CLK). - * - * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock - * @retval None - */ -#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) - -/** @brief Macro to get the I2C1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock - */ -#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) - -#if defined(I2C2) - -/** @brief Macro to configure the I2C2 clock (I2C2CLK). - * - * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock - * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock - * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock - * @retval None - */ -#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) - -/** @brief Macro to get the I2C2 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock - * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock - * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock - */ -#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) - -#endif /* I2C2 */ - -/** @brief Macro to configure the I2C3 clock (I2C3CLK). - * - * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock - * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock - * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock - * @retval None - */ -#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) - -/** @brief Macro to get the I2C3 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock - * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock - * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock - */ -#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) - -#if defined(I2C4) - -/** @brief Macro to configure the I2C4 clock (I2C4CLK). - * - * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock - * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock - * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock - * @retval None - */ -#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) - -/** @brief Macro to get the I2C4 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock - * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock - * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock - */ -#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) - -#endif /* I2C4 */ - - -/** @brief Macro to configure the USART1 clock (USART1CLK). - * - * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock - * @retval None - */ -#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) - -/** @brief Macro to get the USART1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock - */ -#define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) - -/** @brief Macro to configure the USART2 clock (USART2CLK). - * - * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock - * @retval None - */ -#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) - -/** @brief Macro to get the USART2 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock - */ -#define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) - -#if defined(USART3) - -/** @brief Macro to configure the USART3 clock (USART3CLK). - * - * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock - * @retval None - */ -#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) - -/** @brief Macro to get the USART3 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock - */ -#define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) - -#endif /* USART3 */ - -#if defined(UART4) - -/** @brief Macro to configure the UART4 clock (UART4CLK). - * - * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock - * @retval None - */ -#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) - -/** @brief Macro to get the UART4 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock - */ -#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) - -#endif /* UART4 */ - -#if defined(UART5) - -/** @brief Macro to configure the UART5 clock (UART5CLK). - * - * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock - * @retval None - */ -#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) - -/** @brief Macro to get the UART5 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock - */ -#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) - -#endif /* UART5 */ - -/** @brief Macro to configure the LPUART1 clock (LPUART1CLK). - * - * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock - * @retval None - */ -#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) - -/** @brief Macro to get the LPUART1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock - */ -#define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) - -/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). - * - * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock - * @retval None - */ -#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) - -/** @brief Macro to get the LPTIM1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock - */ -#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) - -/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). - * - * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock - * @retval None - */ -#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__)) - -/** @brief Macro to get the LPTIM2 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock - */ -#define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)) - -#if defined(SDMMC1) - -/** @brief Macro to configure the SDMMC1 clock. - * - @if STM32L486xx - * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. - @endif - * - @if STM32L443xx - * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. - @endif - * - * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. - * This parameter can be one of the following values: - @if STM32L486xx - * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock - @endif - @if STM32L443xx - * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock - @endif - @if STM32L4S9xx - * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock - @endif - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock - * @retval None - */ -#if defined(RCC_CCIPR2_SDMMCSEL) -#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ - do \ - { \ - if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \ - { \ - SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \ - } \ - } while(0) -#else -#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)) -#endif /* RCC_CCIPR2_SDMMCSEL */ - -/** @brief Macro to get the SDMMC1 clock. - * @retval The clock source can be one of the following values: - @if STM32L486xx - * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock - @endif - @if STM32L443xx - * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock - @endif - @if STM32L4S9xx - * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock - @endif - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock - */ -#if defined(RCC_CCIPR2_SDMMCSEL) -#define __HAL_RCC_GET_SDMMC1_SOURCE() \ - ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) -#else -#define __HAL_RCC_GET_SDMMC1_SOURCE() \ - (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) -#endif /* RCC_CCIPR2_SDMMCSEL */ - -#endif /* SDMMC1 */ - -/** @brief Macro to configure the RNG clock. - * - * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. - * - * @param __RNG_CLKSOURCE__ specifies the RNG clock source. - * This parameter can be one of the following values: - @if STM32L486xx - * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 - @endif - @if STM32L443xx - * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 - @endif - * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock - * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock - * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock - * @retval None - */ -#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) - -/** @brief Macro to get the RNG clock. - * @retval The clock source can be one of the following values: - @if STM32L486xx - * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 - @endif - @if STM32L443xx - * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 - @endif - * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock - * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock - * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock - */ -#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) - -#if defined(USB_OTG_FS) || defined(USB) - -/** @brief Macro to configure the USB clock (USBCLK). - * - * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. - * - * @param __USB_CLKSOURCE__ specifies the USB clock source. - * This parameter can be one of the following values: - @if STM32L486xx - * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 - @endif - @if STM32L443xx - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 - @endif - * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock - * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock - * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock - * @retval None - */ -#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) - -/** @brief Macro to get the USB clock source. - * @retval The clock source can be one of the following values: - @if STM32L486xx - * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 - @endif - @if STM32L443xx - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 - @endif - * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock - * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock - * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock - */ -#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) - -#endif /* USB_OTG_FS || USB */ - -/** @brief Macro to configure the ADC interface clock. - * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock - @if STM32L486xx - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices - @endif - * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock - * @retval None - */ -#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__)) - -/** @brief Macro to get the ADC clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock - @if STM32L486xx - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices - @endif - * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock - */ -#define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)) - -#if defined(SWPMI1) - -/** @brief Macro to configure the SWPMI1 clock. - * @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock - * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock - * @retval None - */ -#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__)) - -/** @brief Macro to get the SWPMI1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock - * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock - */ -#define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)) - -#endif /* SWPMI1 */ - -#if defined(DFSDM1_Filter0) -/** @brief Macro to configure the DFSDM1 clock. - * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock - * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock - * @retval None - */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) -#else -#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** @brief Macro to get the DFSDM1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock - * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock - */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL)) -#else -#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -/** @brief Macro to configure the DFSDM1 audio clock. - * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock - * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock - * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock - * @retval None - */ -#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__)) - -/** @brief Macro to get the DFSDM1 audio clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock - * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock - * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock - */ -#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL)) - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) - -/** @brief Macro to configure the LTDC clock. - * @param __LTDC_CLKSOURCE__ specifies the DSI clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock - * @retval None - */ -#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__)) - -/** @brief Macro to get the LTDC clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock - */ -#define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)) - -#endif /* LTDC */ - -#if defined(DSI) - -/** @brief Macro to configure the DSI clock. - * @param __DSI_CLKSOURCE__ specifies the DSI clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock - * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock - * @retval None - */ -#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__)) - -/** @brief Macro to get the DSI clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock - * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock - */ -#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL)) - -#endif /* DSI */ - -#if defined(OCTOSPI1) || defined(OCTOSPI2) - -/** @brief Macro to configure the OctoSPI clock. - * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock - * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock - * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock - * @retval None - */ -#define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__)) - -/** @brief Macro to get the OctoSPI clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock - * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock - * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock - */ -#define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL)) - -#endif /* OCTOSPI1 || OCTOSPI2 */ - -/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management - * @brief macros to manage the specified RCC Flags and interrupts. - * @{ - */ - -/** @brief Enable PLLSAI1RDY interrupt. - * @retval None - */ -#define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) - -/** @brief Disable PLLSAI1RDY interrupt. - * @retval None - */ -#define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) - -/** @brief Clear the PLLSAI1RDY interrupt pending bit. - * @retval None - */ -#define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC) - -/** @brief Check whether PLLSAI1RDY interrupt has occurred or not. - * @retval TRUE or FALSE. - */ -#define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) - -/** @brief Check whether the PLLSAI1RDY flag is set or not. - * @retval TRUE or FALSE. - */ -#define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) - -#if defined(RCC_PLLSAI2_SUPPORT) - -/** @brief Enable PLLSAI2RDY interrupt. - * @retval None - */ -#define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) - -/** @brief Disable PLLSAI2RDY interrupt. - * @retval None - */ -#define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) - -/** @brief Clear the PLLSAI2RDY interrupt pending bit. - * @retval None - */ -#define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC) - -/** @brief Check whether the PLLSAI2RDY interrupt has occurred or not. - * @retval TRUE or FALSE. - */ -#define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) - -/** @brief Check whether the PLLSAI2RDY flag is set or not. - * @retval TRUE or FALSE. - */ -#define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)) - -#endif /* RCC_PLLSAI2_SUPPORT */ - - -/** - * @brief Enable the RCC LSE CSS Extended Interrupt Line. - * @retval None - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Disable the RCC LSE CSS Extended Interrupt Line. - * @retval None - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Enable the RCC LSE CSS Event Line. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Disable the RCC LSE CSS Event Line. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) - - -/** - * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) - - -/** - * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) - - -/** - * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. - * @retval EXTI RCC LSE CSS Line Status. - */ -#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) - -/** - * @brief Clear the RCC LSE CSS EXTI flag. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) - - -#if defined(CRS) - -/** - * @brief Enable the specified CRS interrupts. - * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval None - */ -#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) - -/** - * @brief Disable the specified CRS interrupts. - * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval None - */ -#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) - -/** @brief Check whether the CRS interrupt has occurred or not. - * @param __INTERRUPT__ specifies the CRS interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** @brief Clear the CRS interrupt pending bits - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt - * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt - * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt - */ -/* CRS IT Error Mask */ -#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) - -#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ - if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ - { \ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ - } \ - else \ - { \ - WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ - } \ - } while(0) - -/** - * @brief Check whether the specified CRS flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK - * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning - * @arg @ref RCC_CRS_FLAG_ERR Error - * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC - * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow - * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error - * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed - * @retval The new state of _FLAG_ (TRUE or FALSE). - */ -#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the CRS specified FLAG. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK - * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning - * @arg @ref RCC_CRS_FLAG_ERR Error - * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC - * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow - * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error - * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed - * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR - * @retval None - */ - -/* CRS Flag Error Mask */ -#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) - -#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ - if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ - { \ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ - } \ - else \ - { \ - WRITE_REG(CRS->ICR, (__FLAG__)); \ - } \ - } while(0) - -#endif /* CRS */ - -/** - * @} - */ - -#if defined(CRS) - -/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features - * @{ - */ -/** - * @brief Enable the oscillator clock for frequency error counter. - * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. - * @retval None - */ -#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) - -/** - * @brief Disable the oscillator clock for frequency error counter. - * @retval None - */ -#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) - -/** - * @brief Enable the automatic hardware adjustement of TRIM bits. - * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. - * @retval None - */ -#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) - -/** - * @brief Enable or disable the automatic hardware adjustement of TRIM bits. - * @retval None - */ -#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) - -/** - * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies - * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency - * of the synchronization source after prescaling. It is then decreased by one in order to - * reach the expected synchronization on the zero value. The formula is the following: - * RELOAD = (fTARGET / fSYNC) -1 - * @param __FTARGET__ Target frequency (value in Hz) - * @param __FSYNC__ Synchronization signal frequency (value in Hz) - * @retval None - */ -#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCCEx_Exported_Functions - * @{ - */ - -/** @addtogroup RCCEx_Exported_Functions_Group1 - * @{ - */ - -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); - -/** - * @} - */ - -/** @addtogroup RCCEx_Exported_Functions_Group2 - * @{ - */ - -HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); -HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); - -#if defined(RCC_PLLSAI2_SUPPORT) - -HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init); -HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void); - -#endif /* RCC_PLLSAI2_SUPPORT */ - -void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); -void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); -void HAL_RCCEx_EnableLSECSS(void); -void HAL_RCCEx_DisableLSECSS(void); -void HAL_RCCEx_EnableLSECSS_IT(void); -void HAL_RCCEx_LSECSS_IRQHandler(void); -void HAL_RCCEx_LSECSS_Callback(void); -void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); -void HAL_RCCEx_DisableLSCO(void); -void HAL_RCCEx_EnableMSIPLLMode(void); -void HAL_RCCEx_DisableMSIPLLMode(void); - -/** - * @} - */ - -#if defined(CRS) - -/** @addtogroup RCCEx_Exported_Functions_Group3 - * @{ - */ - -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); -void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); -void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); -uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); -void HAL_RCCEx_CRS_IRQHandler(void); -void HAL_RCCEx_CRS_SyncOkCallback(void); -void HAL_RCCEx_CRS_SyncWarnCallback(void); -void HAL_RCCEx_CRS_ExpectedSyncCallback(void); -void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCCEx_Private_Macros - * @{ - */ - -#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) - -#if defined(STM32L431xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) - -#elif defined(STM32L432xx) || defined(STM32L442xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)) - -#elif defined(STM32L433xx) || defined(STM32L443xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) - -#elif defined(STM32L451xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) - -#elif defined(STM32L452xx) || defined(STM32L462xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) - -#elif defined(STM32L471xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) - -#elif defined(STM32L496xx) || defined(STM32L4A6xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) - -#elif defined(STM32L4R5xx) || defined(STM32L4S5xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)) - -#elif defined(STM32L4R7xx) || defined(STM32L4S7xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) - -#elif defined(STM32L4R9xx) || defined(STM32L4S9xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)) - -#else - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) - -#endif /* STM32L431xx */ - -#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) - -#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) - -#if defined(USART3) - -#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) - -#endif /* USART3 */ - -#if defined(UART4) - -#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) - -#endif /* UART4 */ - -#if defined(UART5) - -#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) - -#endif /* UART5 */ - -#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) - -#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) - -#if defined(I2C2) - -#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) - -#endif /* I2C2 */ - -#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) - -#if defined(I2C4) - -#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) - -#endif /* I2C4 */ - -#if defined(RCC_PLLSAI2_SUPPORT) - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define IS_RCC_SAI1CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) -#else -#define IS_RCC_SAI1CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#else - -#define IS_RCC_SAI1CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) - -#endif /* RCC_PLLSAI2_SUPPORT */ - -#if defined(RCC_PLLSAI2_SUPPORT) - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define IS_RCC_SAI2CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) -#else -#define IS_RCC_SAI2CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* RCC_PLLSAI2_SUPPORT */ - -#define IS_RCC_LPTIM1CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) - -#define IS_RCC_LPTIM2CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) - -#if defined(SDMMC1) -#if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL) - -#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) - -#elif defined(RCC_HSI48_SUPPORT) - -#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) -#else - -#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) - -#endif /* RCC_HSI48_SUPPORT */ -#endif /* SDMMC1 */ - -#if defined(RCC_HSI48_SUPPORT) - -#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) - -#else - -#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) - -#endif /* RCC_HSI48_SUPPORT */ - -#if defined(USB_OTG_FS) || defined(USB) -#if defined(RCC_HSI48_SUPPORT) - -#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) - -#else - -#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) - -#endif /* RCC_HSI48_SUPPORT */ -#endif /* USB_OTG_FS || USB */ - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) - -#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) - -#else - -#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ - -#if defined(SWPMI1) - -#define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI)) - -#endif /* SWPMI1 */ - -#if defined(DFSDM1_Filter0) - -#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ - ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ - ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI)) - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) - -#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV2) || \ - ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV4) || \ - ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV8) || \ - ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV16)) - -#endif /* LTDC */ - -#if defined(DSI) - -#define IS_RCC_DSICLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY) || \ - ((__SOURCE__) == RCC_DSICLKSOURCE_PLLSAI2)) - -#endif /* DSI */ - -#if defined(OCTOSPI1) || defined(OCTOSPI2) - -#define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \ - ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)) - -#endif /* OCTOSPI1 || OCTOSPI2 */ - -#define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) - -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) -#define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) -#else -#define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - -#define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) - -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) -#define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) -#else -#define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ - -#define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ - ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) - -#define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ - ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) - -#if defined(RCC_PLLSAI2_SUPPORT) - -#define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) - -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) -#define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) -#else -#define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - -#define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) - -#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) -#define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) -#else -#define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) -#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ - -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) -#define IS_RCC_PLLSAI2Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ - ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) -#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ - -#define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ - ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) - -#endif /* RCC_PLLSAI2_SUPPORT */ - -#if defined(CRS) - -#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ - ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ - ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) - -#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ - ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ - ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ - ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) - -#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ - ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) - -#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) - -#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) - -#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) - -#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ - ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) - -#endif /* CRS */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_RCC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h deleted file mode 100644 index 4eedd1bb2..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h +++ /dev/null @@ -1,325 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rng.h - * @author MCD Application Team - * @brief Header file of RNG HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_RNG_H -#define __STM32L4xx_HAL_RNG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup RNG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Exported_Types RNG Exported Types - * @{ - */ - -#if defined(RNG_CR_CED) -/** - * @brief RNG Configuration Structure definition - */ -typedef struct -{ - uint32_t ClockErrorDetection; /*!< Clock error detection */ -}RNG_InitTypeDef; -#endif /* defined(RNG_CR_CED) */ - -/** - * @brief RNG HAL State Structure definition - */ -typedef enum -{ - HAL_RNG_STATE_RESET = 0x00, /*!< RNG not yet initialized or disabled */ - HAL_RNG_STATE_READY = 0x01, /*!< RNG initialized and ready for use */ - HAL_RNG_STATE_BUSY = 0x02, /*!< RNG internal process is ongoing */ - HAL_RNG_STATE_TIMEOUT = 0x03, /*!< RNG timeout state */ - HAL_RNG_STATE_ERROR = 0x04 /*!< RNG error state */ - -}HAL_RNG_StateTypeDef; - -/** - * @brief RNG Handle Structure definition - */ -typedef struct -{ - RNG_TypeDef *Instance; /*!< Register base address */ - -#if defined(RNG_CR_CED) - RNG_InitTypeDef Init; /*!< RNG configuration parameters */ -#endif /* defined(RNG_CR_CED) */ - - HAL_LockTypeDef Lock; /*!< RNG locking object */ - - __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ - - uint32_t RandomNumber; /*!< Last Generated RNG Data */ - -}RNG_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Exported_Constants RNG Exported Constants - * @{ - */ - -/** @defgroup RNG_Interrupt_definition RNG Interrupts Definition - * @{ - */ -#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */ -#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */ -#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */ -/** - * @} - */ - -/** @defgroup RNG_Flag_definition RNG Flags Definition - * @{ - */ -#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */ -#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */ -#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */ -/** - * @} - */ - -#if defined(RNG_CR_CED) -/** @defgroup RNG_Clock_Error_Detection RNG Clock Error Detection - * @{ - */ -#define RNG_CED_ENABLE ((uint32_t)0x00000000) /*!< Clock error detection enabled */ -#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */ -/** - * @} - */ -#endif /* defined(RNG_CR_CED) */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup RNG_Exported_Macros RNG Exported Macros - * @{ - */ - -/** @brief Reset RNG handle state. - * @param __HANDLE__: RNG Handle - * @retval None - */ -#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) - -/** - * @brief Enable the RNG peripheral. - * @param __HANDLE__: RNG Handle - * @retval None - */ -#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN) - -/** - * @brief Disable the RNG peripheral. - * @param __HANDLE__: RNG Handle - * @retval None - */ -#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN) - -/** - * @brief Check whether the specified RNG flag is set or not. - * @param __HANDLE__: RNG Handle - * @param __FLAG__: RNG flag - * This parameter can be one of the following values: - * @arg RNG_FLAG_DRDY: Data ready - * @arg RNG_FLAG_CECS: Clock error current status - * @arg RNG_FLAG_SECS: Seed error current status - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - - -/** - * @brief Clear the selected RNG flag status. - * @param __HANDLE__: RNG handle - * @param __FLAG__: RNG flag to clear - * @note WARNING: This is a dummy macro for HAL code alignment, - * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only. - * @retval None - */ -#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */ - - - -/** - * @brief Enable the RNG interrupt. - * @param __HANDLE__: RNG Handle - * @retval None - */ -#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE) - -/** - * @brief Disable the RNG interrupt. - * @param __HANDLE__: RNG Handle - * @retval None - */ -#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE) - -/** - * @brief Check whether the specified RNG interrupt has occurred or not. - * @param __HANDLE__: RNG Handle - * @param __INTERRUPT__: specifies the RNG interrupt status flag to check. - * This parameter can be one of the following values: - * @arg RNG_IT_DRDY: Data ready interrupt - * @arg RNG_IT_CEI: Clock error interrupt - * @arg RNG_IT_SEI: Seed error interrupt - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** - * @brief Clear the RNG interrupt status flags. - * @param __HANDLE__: RNG Handle - * @param __INTERRUPT__: specifies the RNG interrupt status flag to clear. - * This parameter can be one of the following values: - * @arg RNG_IT_CEI: Clock error interrupt - * @arg RNG_IT_SEI: Seed error interrupt - * @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY. - * @retval None - */ -#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__)) - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Exported_Functions RNG Exported Functions - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng); -HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng); -void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng); -void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng); -/** - * @} - */ - -/* Peripheral Control functions ************************************************/ -/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions - * @{ - */ -uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */ -uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */ - -HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); -HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng); - -void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); -void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); -void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit); -/** - * @} - */ - -/* Peripheral State functions **************************************************/ -/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions - * @{ - */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RNG_Private_Macros RNG Private Macros - * @{ - */ - -#if defined(RNG_CR_CED) -/** - * @brief Verify the RNG Clock Error Detection mode. - * @param __MODE__: RNG Clock Error Detection mode - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_RNG_CED(__MODE__) (((__MODE__) == RNG_CED_ENABLE) || \ - ((__MODE__) == RNG_CED_DISABLE)) -#endif /* defined(RNG_CR_CED) */ - -/** - * @} - */ -/* Private functions prototypes ----------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_RNG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h deleted file mode 100644 index ed269a98c..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h +++ /dev/null @@ -1,861 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rtc.h - * @author MCD Application Team - * @brief Header file of RTC HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_RTC_H -#define __STM32L4xx_HAL_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RTC_Exported_Types RTC Exported Types - * @{ - */ -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */ - HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */ - HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ - HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ - HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ - -}HAL_RTCStateTypeDef; - -/** - * @brief RTC Configuration Structure definition - */ -typedef struct -{ - uint32_t HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ - - uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ - - uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. - This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ - - uint32_t OutPutRemap; /*!< Specifies the remap for RTC output. - This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */ - - uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. - This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ - - uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. - This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ -}RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t Hours; /*!< Specifies the RTC Time Hour. - This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. - This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ - - uint8_t Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - - uint8_t Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - - uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ - - uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. - This parameter corresponds to a time unit range between [0-1] Second - with [1 Sec / SecondFraction +1] granularity */ - - uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content - corresponding to Synchronous pre-scaler factor value (PREDIV_S) - This parameter corresponds to a time unit range between [0-1] Second - with [1 Sec / SecondFraction +1] granularity. - This field will be used only by HAL_RTC_GetTime function */ - - uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. - This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ - - uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit - in CR register to store the operation. - This parameter can be a value of @ref RTC_StoreOperation_Definitions */ -}RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t Date; /*!< Specifies the RTC Date. - This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ - - uint8_t Year; /*!< Specifies the RTC Date Year. - This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ - -}RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ - - uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - - uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. - This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ - - uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. - If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint32_t Alarm; /*!< Specifies the alarm . - This parameter can be a value of @ref RTC_Alarms_Definitions */ -}RTC_AlarmTypeDef; - -/** - * @brief Time Handle Structure definition - */ -typedef struct -{ - RTC_TypeDef *Instance; /*!< Register base address */ - - RTC_InitTypeDef Init; /*!< RTC required parameters */ - - HAL_LockTypeDef Lock; /*!< RTC locking object */ - - __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ - -}RTC_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RTC_Exported_Constants RTC Exported Constants - * @{ - */ - -/** @defgroup RTC_Hour_Formats RTC Hour Formats - * @{ - */ -#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000) -#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040) -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions - * @{ - */ -#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000) -#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000) -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT - * @{ - */ -#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000) -#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE) -/** - * @} - */ - -/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap - * @{ - */ -#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000) -#define RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP) -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions - * @{ - */ -#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) -/** - * @} - */ - -/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions - * @{ - */ -#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000) -#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000) -#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions - * @{ - */ -#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000) -#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000) -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions - * @{ - */ -#define RTC_FORMAT_BIN ((uint32_t)0x00000000) -#define RTC_FORMAT_BCD ((uint32_t)0x00000001) -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions - * @{ - */ - -/* Coded in BCD format */ -#define RTC_MONTH_JANUARY ((uint8_t)0x01) -#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) -#define RTC_MONTH_MARCH ((uint8_t)0x03) -#define RTC_MONTH_APRIL ((uint8_t)0x04) -#define RTC_MONTH_MAY ((uint8_t)0x05) -#define RTC_MONTH_JUNE ((uint8_t)0x06) -#define RTC_MONTH_JULY ((uint8_t)0x07) -#define RTC_MONTH_AUGUST ((uint8_t)0x08) -#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) -#define RTC_MONTH_OCTOBER ((uint8_t)0x10) -#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) -#define RTC_MONTH_DECEMBER ((uint8_t)0x12) -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions - * @{ - */ -#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) -#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) -#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) -#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) -#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) -#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) -#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) -/** - * @} - */ - -/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions - * @{ - */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000) -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000) -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions - * @{ - */ -#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) -#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 -#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 -#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 -#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions - * @{ - */ -#define RTC_ALARM_A RTC_CR_ALRAE -#define RTC_ALARM_B RTC_CR_ALRBE -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions - * @{ - */ -#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm - comparison. Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm - comparison. Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match - to activate alarm. */ -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) /*!< Enable Timestamp Interrupt */ -#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) /*!< Enable Wakeup timer Interrupt */ -#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) /*!< Enable Alarm A Interrupt */ -#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) /*!< Enable Alarm B Interrupt */ -#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /*!< Enable all Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt */ -#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt */ -#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE) /*!< Enable Tamper 3 Interrupt */ -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions RTC Flags Definitions - * @{ - */ -#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF) -#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F) -#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F) -#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F) -#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF) -#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF) -#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF) -#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF) -#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF) -#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF) -#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF) -#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF) -#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS) -#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF) -#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF) -#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF) -#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup RTC_Exported_Macros RTC Exported Macros - * @{ - */ - -/** @brief Reset RTC handle state. - * @param __HANDLE__: RTC handle. - * @retval None - */ -#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) - -/** - * @brief Disable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->WPR = 0xCA; \ - (__HANDLE__)->Instance->WPR = 0x53; \ - } while(0) - -/** - * @brief Enable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->WPR = 0xFF; \ - } while(0) - - -/** - * @brief Enable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) - -/** - * @brief Disable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) - -/** - * @brief Enable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) - -/** - * @brief Disable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) - -/** - * @brief Enable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Alarm interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) - -/** - * @brief Get the selected RTC Alarm's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to check. - * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF - * @arg RTC_FLAG_ALRAWF - * @arg RTC_FLAG_ALRBWF - * @retval None - */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Clear the RTC Alarm's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. - * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF - * @retval None - */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Check whether the specified RTC Alarm interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** - * @brief Enable interrupt on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable interrupt on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) - -/** - * @brief Enable event on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable event on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) - -/** - * @brief Enable falling edge trigger on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable falling edge trigger on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) - -/** - * @brief Enable rising edge trigger on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable rising edge trigger on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) - -/** - * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not. - * @retval Line Status. - */ -#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Clear the RTC Alarm associated Exti line flag. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Generate a Software interrupt on RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @} - */ - -/* Include RTC HAL Extended module */ -#include "stm32l4xx_hal_rtc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTC_Exported_Functions - * @{ - */ - -/** @addtogroup RTC_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group2 - * @{ - */ -/* RTC Time and Date functions ************************************************/ -HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group3 - * @{ - */ -/* RTC Alarm functions ********************************************************/ -HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group4 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group5 - * @{ - */ -/* Peripheral State functions *************************************************/ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); - -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RTC_Private_Constants RTC Private Constants - * @{ - */ -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK 0x007F7F7FU -#define RTC_DR_RESERVED_MASK 0x00FFFF3FU -#define RTC_INIT_MASK 0xFFFFFFFFU -#define RTC_RSF_MASK 0xFFFFFF5FU - -#define RTC_TIMEOUT_VALUE 1000 - -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the RTC Alarm event */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup RTC_Private_Macros RTC Private Macros - * @{ - */ - -/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters - * @{ - */ - -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ - ((FORMAT) == RTC_HOURFORMAT_24)) - -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ - ((POL) == RTC_OUTPUT_POLARITY_LOW)) - -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ - ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) - -#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \ - ((REMAP) == RTC_OUTPUT_REMAP_POS1)) - -#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM)) - -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ - ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ - ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) - -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ - ((OPERATION) == RTC_STOREOPERATION_SET)) - -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) - -#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99) - -#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12)) - -#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31)) - -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) - -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31)) - -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ - ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) - -#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) - -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) - -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF) - -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) - -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F) - -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF) - -#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12)) - -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23) - -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59) - -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59) - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup RTC_Private_Functions - * @{ - */ - -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); -uint8_t RTC_ByteToBcd2(uint8_t Value); -uint8_t RTC_Bcd2ToByte(uint8_t Value); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_RTC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h deleted file mode 100644 index 102703f1e..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h +++ /dev/null @@ -1,1100 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rtc_ex.h - * @author MCD Application Team - * @brief Header file of RTC HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_RTC_EX_H -#define __STM32L4xx_HAL_RTC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup RTCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Types RTCEx Exported Types - * @{ - */ -/** - * @brief RTC Tamper structure definition - */ -typedef struct -{ - uint32_t Tamper; /*!< Specifies the Tamper Pin. - This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ - - uint32_t Interrupt; /*!< Specifies the Tamper Interrupt. - This parameter can be a value of @ref RTCEx_Tamper_Interrupt_Definitions */ - - uint32_t Trigger; /*!< Specifies the Tamper Trigger. - This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ - - uint32_t NoErase; /*!< Specifies the Tamper no erase mode. - This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */ - - uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. - This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */ - - uint32_t Filter; /*!< Specifies the RTC Filter Tamper. - This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ - - uint32_t SamplingFrequency; /*!< Specifies the sampling frequency. - This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */ - - uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration . - This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ - - uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp . - This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */ - - uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. - This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ -}RTC_TamperTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants - * @{ - */ - -/** @defgroup RTCEx_Output_selection_Definitions RTC Output Selection Definitions - * @{ - */ -#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000) -#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000) -#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000) -#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000) -/** - * @} - */ - -/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions - * @{ - */ -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#define RTC_BKP_DR20 ((uint32_t)0x00000014) -#define RTC_BKP_DR21 ((uint32_t)0x00000015) -#define RTC_BKP_DR22 ((uint32_t)0x00000016) -#define RTC_BKP_DR23 ((uint32_t)0x00000017) -#define RTC_BKP_DR24 ((uint32_t)0x00000018) -#define RTC_BKP_DR25 ((uint32_t)0x00000019) -#define RTC_BKP_DR26 ((uint32_t)0x0000001A) -#define RTC_BKP_DR27 ((uint32_t)0x0000001B) -#define RTC_BKP_DR28 ((uint32_t)0x0000001C) -#define RTC_BKP_DR29 ((uint32_t)0x0000001D) -#define RTC_BKP_DR30 ((uint32_t)0x0000001E) -#define RTC_BKP_DR31 ((uint32_t)0x0000001F) -/** - * @} - */ - -/** @defgroup RTCEx_TimeStamp_Edges_definitions RTC TimeStamp Edges Definitions - * @{ - */ -#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000) -#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection - * @{ - */ -#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions - * @{ - */ -#if defined(RTC_TAMPER1_SUPPORT) -#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E -#endif /* RTC_TAMPER1_SUPPORT */ -#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E -#if defined(RTC_TAMPER3_SUPPORT) -#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E -#endif /* RTC_TAMPER3_SUPPORT */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions - * @{ - */ -#if defined(RTC_TAMPER1_SUPPORT) -#define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE -#endif /* RTC_TAMPER1_SUPPORT */ -#define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE -#if defined(RTC_TAMPER3_SUPPORT) -#define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE -#endif /* RTC_TAMPER3_SUPPORT */ -#define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions - * @{ - */ -#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) -#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002) -#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE -#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Tamper EraseBackUp Definitions -* @{ -*/ -#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000) -#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Tamper Mask Flag Definitions -* @{ -*/ -#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000) -#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions - * @{ - */ -#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ - -#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8 - consecutive samples at the active level. */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions - * @{ - */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions - * @{ - */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions - * @{ - */ -#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions - * @{ - */ -#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ -/** - * @} - */ - -/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wakeup Timer Definitions - * @{ - */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003) -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004) -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions - * @{ - */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 8s, else 2exp18 RTCCLK seconds */ -/** - * @} - */ - -/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions - * @{ - */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0] - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0] */ -/** - * @} - */ - -/** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions - * @{ - */ -#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) -#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000) -/** - * @} - */ - -/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions - * @{ - */ -#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000) -#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros - * @{ - */ - -/** - * @brief Enable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) - -/** - * @brief Disable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) - -/** - * @brief Enable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) - -/** - * @brief Check whether the specified RTC Wake Up timer interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** - * @brief Get the selected RTC WakeUpTimer's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_WUTF - * @arg RTC_FLAG_WUTWF - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Clear the RTC Wake Up timer's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear. - * This parameter can be: - * @arg RTC_FLAG_WUTF - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -#if defined(RTC_TAMPER1_SUPPORT) -/** - * @brief Enable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E)) - -/** - * @brief Disable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E)) -#endif /* RTC_TAMPER1_SUPPORT */ - -/** - * @brief Enable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E)) - -/** - * @brief Disable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E)) - -#if defined(RTC_TAMPER3_SUPPORT) -/** - * @brief Enable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E)) - -/** - * @brief Disable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E)) -#endif /* RTC_TAMPER3_SUPPORT */ - -/** - * @brief Enable the RTC Tamper interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC Tamper interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. - * This parameter can be: - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT) -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \ - ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \ - (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET)) -#else -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) -#endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */ - -/** - * @brief Check whether the specified RTC Tamper interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** - * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper1 flag - * @arg RTC_FLAG_TAMP2F: Tamper2 flag - * @arg RTC_FLAG_TAMP3F: Tamper3 flag - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to clear. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper1 flag - * @arg RTC_FLAG_TAMP2F: Tamper2 flag - * @arg RTC_FLAG_TAMP3F: Tamper3 flag - * @retval None - */ -#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Enable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) - -/** - * @brief Disable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) - -/** - * @brief Enable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) - -/** - * @brief Check whether the specified RTC Time Stamp interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** - * @brief Get the selected RTC TimeStamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC TimeStamp Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_TSF - * @arg RTC_FLAG_TSOVF - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Clear the RTC Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. - * This parameter can be: - * @arg RTC_FLAG_TSF - * @arg RTC_FLAG_TSOVF - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Enable the RTC internal TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE)) - -/** - * @brief Disable the RTC internal TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE)) - -/** - * @brief Get the selected RTC Internal Time Stamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_ITSF - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Clear the RTC Internal Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear. - * This parameter can be: - * @arg RTC_FLAG_ITSF - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Enable the RTC calibration output. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) - -/** - * @brief Disable the calibration output. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) - -/** - * @brief Enable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) - -/** - * @brief Disable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) - -/** - * @brief Get the selected RTC shift operation's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC shift operation Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_SHPF - * @retval None - */ -#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable event on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable event on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. - * This parameter can be: - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not. - * @retval Line Status. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Clear the RTC WakeUp Timer associated Exti line flag. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) - -/** - * @brief Enable event on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable event on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) - -/** - * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) - -/** - * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) - -/** - * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. - * This parameter can be: - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not. - * @retval Line Status. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Clear the RTC Tamper and Timestamp associated Exti line flag. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTCEx_Exported_Functions - * @{ - */ - -/* RTC TimeStamp and Tamper functions *****************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); -HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); - -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); - -#if defined(RTC_TAMPER1_SUPPORT) -void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); -#endif /* RTC_TAMPER1_SUPPORT */ -void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); -#if defined(RTC_TAMPER3_SUPPORT) -void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); -#endif /* RTC_TAMPER3_SUPPORT */ -void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#if defined(RTC_TAMPER1_SUPPORT) -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#endif /* RTC_TAMPER1_SUPPORT */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#if defined(RTC_TAMPER3_SUPPORT) -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#endif /* RTC_TAMPER3_SUPPORT */ -/** - * @} - */ - -/* RTC Wake-up functions ******************************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -/** - * @} - */ - -/* Extended Control functions ************************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group3 - * @{ - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); - -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/* Extended RTC features functions *******************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group4 - * @{ - */ -void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RTCEx_Private_Constants RTCEx Private Constants - * @{ - */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup RTCEx_Private_Macros RTCEx Private Macros - * @{ - */ - -/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters - * @{ - */ - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ - ((OUTPUT) == RTC_OUTPUT_WAKEUP)) - -#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER) - -#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ - ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) - -#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) - -#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)0xFFB6FFFB) == 0x00) && ((INTERRUPT) != (uint32_t)RESET)) - -#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT)) - -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) - -#define IS_RTC_TAMPER_ERASE_MODE(MODE) (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \ - ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE)) - -#define IS_RTC_TAMPER_MASKFLAG_STATE(STATE) (((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \ - ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE)) - -#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ - ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) - -#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) - -#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) - -#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ - ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) - -#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ - ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) - -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) - -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) - -#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) - -#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ - ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) - -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) - -#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ - ((SEL) == RTC_SHIFTADD1S_SET)) - -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) - -#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ - ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_RTC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h deleted file mode 100644 index bfc0194b0..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h +++ /dev/null @@ -1,2043 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_tim.h - * @author MCD Application Team - * @brief Header file of TIM HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_TIM_H -#define __STM32L4xx_HAL_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIM_Exported_Types TIM Exported Types - * @{ - */ - -/** - * @brief TIM Time base Configuration Structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_ClockDivision */ - - uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. - This parameter can be a value of @ref TIM_AutoReloadPreload */ -} TIM_Base_InitTypeDef; - -/** - * @brief TIM Output Compare Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCFastMode; /*!< Specifies the Fast mode state. - This parameter can be a value of @ref TIM_Output_Fast_State - @note This parameter is valid only in PWM1 and PWM2 mode. */ - - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OC_InitTypeDef; - -/** - * @brief TIM One Pulse Mode Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_OnePulse_InitTypeDef; - - -/** - * @brief TIM Input Capture Configuration Structure definition - */ -typedef struct -{ - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_IC_InitTypeDef; - -/** - * @brief TIM Encoder Configuration Structure definition - */ -typedef struct -{ - uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Mode */ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC1Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC2Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC2Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_Encoder_InitTypeDef; - - -/** - * @brief Clock Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClockSource; /*!< TIM clock sources - This parameter can be a value of @ref TIM_Clock_Source */ - uint32_t ClockPolarity; /*!< TIM clock polarity - This parameter can be a value of @ref TIM_Clock_Polarity */ - uint32_t ClockPrescaler; /*!< TIM clock prescaler - This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClockConfigTypeDef; - -/** - * @brief Clear Input Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClearInputState; /*!< TIM clear Input state - This parameter can be ENABLE or DISABLE */ - uint32_t ClearInputSource; /*!< TIM clear Input sources - This parameter can be a value of @ref TIM_ClearInput_Source */ - uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity - This parameter can be a value of @ref TIM_ClearInput_Polarity */ - uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter can be a value of @ref TIM_ClearInput_Prescaler */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClearInputConfigTypeDef; - -/** - * @brief TIM Master configuration Structure definition - * @note Advanced timers provide TRGO2 internal line which is redirected - * to the ADC - */ -typedef struct { - uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ - uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ - uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode */ -}TIM_MasterConfigTypeDef; - -/** - * @brief TIM Slave configuration Structure definition - */ -typedef struct { - uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ - uint32_t InputTrigger; /*!< Input Trigger source - This parameter can be a value of @ref TIM_Trigger_Selection */ - uint32_t TriggerPolarity; /*!< Input Trigger polarity - This parameter can be a value of @ref TIM_Trigger_Polarity */ - uint32_t TriggerPrescaler; /*!< Input trigger prescaler - This parameter can be a value of @ref TIM_Trigger_Prescaler */ - uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - -}TIM_SlaveConfigTypeDef; - -/** - * @brief TIM Break input(s) and Dead time configuration Structure definition - * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable - * filter and polarity. - */ -typedef struct -{ - uint32_t OffStateRunMode; /*!< TIM off state in run mode - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity - This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t BreakFilter; /*!< Specifies the break input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Break2State; /*!< TIM Break2 State - This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ - uint32_t Break2Polarity; /*!< TIM Break2 input polarity - This parameter can be a value of @ref TIM_Break2_Polarity */ - uint32_t Break2Filter; /*!< TIM break2 input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BreakDeadTimeConfigTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ -}HAL_TIM_StateTypeDef; - -/** - * @brief HAL Active channel structures definition - */ -typedef enum -{ - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_5 = 0x10, /*!< The active channel is 5 */ - HAL_TIM_ACTIVE_CHANNEL_6 = 0x20, /*!< The active channel is 6 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ -}HAL_TIM_ActiveChannel; - -/** - * @brief TIM Time Base Handle Structure definition - */ -typedef struct -{ - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ -}TIM_HandleTypeDef; - -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_Exported_Constants TIM Exported Constants - * @{ - */ - -/** @defgroup TIM_ClearInput_Source TIM Clear Input Source - * @{ - */ -#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) -#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) -#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address TIM DMA Base Address - * @{ - */ -#define TIM_DMABASE_CR1 (0x00000000) -#define TIM_DMABASE_CR2 (0x00000001) -#define TIM_DMABASE_SMCR (0x00000002) -#define TIM_DMABASE_DIER (0x00000003) -#define TIM_DMABASE_SR (0x00000004) -#define TIM_DMABASE_EGR (0x00000005) -#define TIM_DMABASE_CCMR1 (0x00000006) -#define TIM_DMABASE_CCMR2 (0x00000007) -#define TIM_DMABASE_CCER (0x00000008) -#define TIM_DMABASE_CNT (0x00000009) -#define TIM_DMABASE_PSC (0x0000000A) -#define TIM_DMABASE_ARR (0x0000000B) -#define TIM_DMABASE_RCR (0x0000000C) -#define TIM_DMABASE_CCR1 (0x0000000D) -#define TIM_DMABASE_CCR2 (0x0000000E) -#define TIM_DMABASE_CCR3 (0x0000000F) -#define TIM_DMABASE_CCR4 (0x00000010) -#define TIM_DMABASE_BDTR (0x00000011) -#define TIM_DMABASE_DCR (0x00000012) -#define TIM_DMABASE_DMAR (0x00000013) -#define TIM_DMABASE_OR1 (0x00000014) -#define TIM_DMABASE_CCMR3 (0x00000015) -#define TIM_DMABASE_CCR5 (0x00000016) -#define TIM_DMABASE_CCR6 (0x00000017) -#define TIM_DMABASE_OR2 (0x00000018) -#define TIM_DMABASE_OR3 (0x00000019) -/** - * @} - */ - -/** @defgroup TIM_Event_Source TIM Extended Event Source - * @{ - */ -#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ -#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ -#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ -#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ -#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ -#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ -#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ -#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ -#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ -/** - * @} - */ - -/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity - * @{ - */ -#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Polarity TIM ETR Polarity - * @{ - */ -#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler - * @{ - */ -#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ -#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ -#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ -#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode TIM Counter Mode - * @{ - */ -#define TIM_COUNTERMODE_UP ((uint32_t)0x0000) -#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR -#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 -#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 -#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS -/** - * @} - */ - -/** @defgroup TIM_ClockDivision TIM Clock Division - * @{ - */ -#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) -#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) -#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) -/** - * @} - */ - -/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload - * @{ - */ -#define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000) /*!< TIMx_ARR register is not buffered */ -#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State TIM Output Compare State - * @{ - */ -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State - * @{ - */ -#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) -/** - * @} - */ - -/** @defgroup TIM_Output_Fast_State TIM Output Fast State - * @{ - */ -#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) -#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity - * @{ - */ -#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) -#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity - * @{ - */ -#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) -#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State - * @{ - */ -#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) -#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State - * @{ - */ -#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) -#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity - * @{ - */ -#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING -#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING -#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection - * @{ - */ -#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ -#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler - * @{ - */ -#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ -#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ -#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ -#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode - * @{ - */ -#define TIM_OPMODE_SINGLE (TIM_CR1_OPM) -#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode TIM Encoder Mode - * @{ - */ -#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) -#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) -#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) -/** - * @} - */ - -/** @defgroup TIM_Interrupt_definition TIM interrupt Definition - * @{ - */ -#define TIM_IT_UPDATE (TIM_DIER_UIE) -#define TIM_IT_CC1 (TIM_DIER_CC1IE) -#define TIM_IT_CC2 (TIM_DIER_CC2IE) -#define TIM_IT_CC3 (TIM_DIER_CC3IE) -#define TIM_IT_CC4 (TIM_DIER_CC4IE) -#define TIM_IT_COM (TIM_DIER_COMIE) -#define TIM_IT_TRIGGER (TIM_DIER_TIE) -#define TIM_IT_BREAK (TIM_DIER_BIE) -/** - * @} - */ - -/** @defgroup TIM_Commutation_Source TIM Commutation Source - * @{ - */ -#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) -#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources TIM DMA Sources - * @{ - */ -#define TIM_DMA_UPDATE (TIM_DIER_UDE) -#define TIM_DMA_CC1 (TIM_DIER_CC1DE) -#define TIM_DMA_CC2 (TIM_DIER_CC2DE) -#define TIM_DMA_CC3 (TIM_DIER_CC3DE) -#define TIM_DMA_CC4 (TIM_DIER_CC4DE) -#define TIM_DMA_COM (TIM_DIER_COMDE) -#define TIM_DMA_TRIGGER (TIM_DIER_TDE) -/** - * @} - */ - -/** @defgroup TIM_Flag_definition TIM Flag Definition - * @{ - */ -#define TIM_FLAG_UPDATE (TIM_SR_UIF) -#define TIM_FLAG_CC1 (TIM_SR_CC1IF) -#define TIM_FLAG_CC2 (TIM_SR_CC2IF) -#define TIM_FLAG_CC3 (TIM_SR_CC3IF) -#define TIM_FLAG_CC4 (TIM_SR_CC4IF) -#define TIM_FLAG_CC5 (TIM_SR_CC5IF) -#define TIM_FLAG_CC6 (TIM_SR_CC6IF) -#define TIM_FLAG_COM (TIM_SR_COMIF) -#define TIM_FLAG_TRIGGER (TIM_SR_TIF) -#define TIM_FLAG_BREAK (TIM_SR_BIF) -#define TIM_FLAG_BREAK2 (TIM_SR_B2IF) -#define TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF) -#define TIM_FLAG_CC1OF (TIM_SR_CC1OF) -#define TIM_FLAG_CC2OF (TIM_SR_CC2OF) -#define TIM_FLAG_CC3OF (TIM_SR_CC3OF) -#define TIM_FLAG_CC4OF (TIM_SR_CC4OF) -/** - * @} - */ - -/** @defgroup TIM_Channel TIM Channel - * @{ - */ -#define TIM_CHANNEL_1 ((uint32_t)0x0000) -#define TIM_CHANNEL_2 ((uint32_t)0x0004) -#define TIM_CHANNEL_3 ((uint32_t)0x0008) -#define TIM_CHANNEL_4 ((uint32_t)0x000C) -#define TIM_CHANNEL_5 ((uint32_t)0x0010) -#define TIM_CHANNEL_6 ((uint32_t)0x0014) -#define TIM_CHANNEL_ALL ((uint32_t)0x003C) -/** - * @} - */ - -/** @defgroup TIM_Clock_Source TIM Clock Source - * @{ - */ -#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) -#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) -#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) -#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) -/** - * @} - */ - -/** @defgroup TIM_Clock_Polarity TIM Clock Polarity - * @{ - */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler - * @{ - */ -#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ -#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ -#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity - * @{ - */ -#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler - * @{ - */ -#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state - * @{ - */ -#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) -#define TIM_OSSR_DISABLE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state - * @{ - */ -#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) -#define TIM_OSSI_DISABLE ((uint32_t)0x0000) -/** - * @} - */ -/** @defgroup TIM_Lock_level TIM Lock level - * @{ - */ -#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) -#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) -#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) -#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable - * @{ - */ -#define TIM_BREAK_ENABLE (TIM_BDTR_BKE) -#define TIM_BREAK_DISABLE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity TIM Break Input Polarity - * @{ - */ -#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) -#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) -/** - * @} - */ - -/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable - * @{ - */ -#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000) -#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) -/** - * @} - */ - -/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity - * @{ - */ -#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000) -#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable - * @{ - */ -#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) -#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 - * @{ - */ -#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ -#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ -#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ -#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection - * @{ - */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) -#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) -#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) -#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) -#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) -#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) - * @{ - */ -#define TIM_TRGO2_RESET ((uint32_t)0x00000000) -#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) -#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2)) -#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3)) -#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)) -#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode - * @{ - */ -#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) -#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode TIM Slave mode - * @{ - */ -#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) -#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2)) -#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)) -#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)) -#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)) -#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes - * @{ - */ -#define TIM_OCMODE_TIMING ((uint32_t)0x0000) -#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2) - -#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3) -#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Selection TIM Trigger Selection - * @{ - */ -#define TIM_TS_ITR0 ((uint32_t)0x0000) -#define TIM_TS_ITR1 ((uint32_t)0x0010) -#define TIM_TS_ITR2 ((uint32_t)0x0020) -#define TIM_TS_ITR3 ((uint32_t)0x0030) -#define TIM_TS_TI1F_ED ((uint32_t)0x0040) -#define TIM_TS_TI1FP1 ((uint32_t)0x0050) -#define TIM_TS_TI2FP2 ((uint32_t)0x0060) -#define TIM_TS_ETRF ((uint32_t)0x0070) -#define TIM_TS_NONE ((uint32_t)0xFFFF) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity - * @{ - */ -#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler - * @{ - */ -#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ -#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ -#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection - * @{ - */ -#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) -#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length - * @{ - */ -#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) -#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) -#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) -#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) -#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) -#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) -#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) -#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) -#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) -#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) -#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) -#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) -#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) -#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) -#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) -#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) -#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) -#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) -/** - * @} - */ - -/** @defgroup DMA_Handle_index TIM DMA Handle Index - * @{ - */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ -/** - * @} - */ - -/** @defgroup Channel_CC_State TIM Capture/Compare Channel State - * @{ - */ -#define TIM_CCx_ENABLE ((uint32_t)0x0001) -#define TIM_CCx_DISABLE ((uint32_t)0x0000) -#define TIM_CCxN_ENABLE ((uint32_t)0x0004) -#define TIM_CCxN_DISABLE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_Break_System TIM Break System - * @{ - */ -#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ -#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ -#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */ -#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */ -/** - * @} - */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup TIM_Exported_Macros TIM Exported Macros - * @{ - */ - -/** @brief Reset TIM handle state. - * @param __HANDLE__ TIM handle. - * @retval None - */ -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) - -/** - * @brief Enable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) - -/** - * @brief Enable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) - -/** - * @brief Disable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ - { \ - (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ - } \ - } \ - } while(0) - -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled - */ -#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ - { \ - (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ - } \ - } \ - } while(0) - -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled unconditionally - */ -#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) - -/** @brief Enable the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to enable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) - - -/** @brief Disable the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to disable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) - -/** @brief Enable the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to enable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) - -/** @brief Disable the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to disable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) - -/** @brief Check whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 6 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag - * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) - -/** @brief Clear the specified TIM interrupt flag. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to clear. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 6 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag - * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** - * @brief Check whether the specified TIM interrupt source is enabled or not. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval The state of TIM_IT (SET or RESET). - */ -#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Clear the TIM interrupt pending bits. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) - -/** - * @brief Indicates whether or not the TIM Counter is used as downcounter. - * @param __HANDLE__ TIM handle. - * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder -mode. - */ -#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) - - -/** - * @brief Set the TIM Prescaler on runtime. - * @param __HANDLE__ TIM handle. - * @param __PRESC__ specifies the Prescaler new value. - * @retval None - */ -#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) - -/** - * @brief Set the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @param __COUNTER__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) - -/** - * @brief Get the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) - */ -#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ - ((__HANDLE__)->Instance->CNT) - -/** - * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __AUTORELOAD__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) - -/** - * @brief Get the TIM Autoreload Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) - */ -#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ - ((__HANDLE__)->Instance->ARR) - -/** - * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __CKD__ specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - * @retval None - */ -#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) - -/** - * @brief Get the TIM Clock Division value on runtime. - * @param __HANDLE__ TIM handle. - * @retval The clock division can be one of the following values: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - */ -#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) - -/** - * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__ specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ - do{ \ - TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) - -/** - * @brief Get the TIM Input Capture prescaler on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get input capture 1 prescaler value - * @arg TIM_CHANNEL_2: get input capture 2 prescaler value - * @arg TIM_CHANNEL_3: get input capture 3 prescaler value - * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval The input capture prescaler can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - */ -#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) - -/** - * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param __COMPARE__ specifies the Capture Compare register new value. - * @retval None - */ -#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) - -/** - * @brief Get the TIM Capture Compare Register value on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channel associated with the capture compare register - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get capture/compare 1 register value - * @arg TIM_CHANNEL_2: get capture/compare 2 register value - * @arg TIM_CHANNEL_3: get capture/compare 3 register value - * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @arg TIM_CHANNEL_5: get capture/compare 5 register value - * @arg TIM_CHANNEL_6: get capture/compare 6 register value - * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) - */ -#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ - ((__HANDLE__)->Instance->CCR6)) - -/** - * @brief Set the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval None - */ -#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) - -/** - * @brief Reset the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval None - */ -#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) - -/** - * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__ TIM handle. - * @note When the USR bit of the TIMx_CR1 register is set, only counter - * overflow/underflow generates an update interrupt or DMA request (if - * enabled) - * @retval None - */ -#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) - -/** - * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__ TIM handle. - * @note When the USR bit of the TIMx_CR1 register is reset, any of the - * following events generate an update interrupt or DMA request (if - * enabled): - * _ Counter overflow underflow - * _ Setting the UG bit - * _ Update generation through the slave mode controller - * @retval None - */ -#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) - -/** - * @brief Set the TIM Capture x input polarity on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__ Polarity for TIx source - * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge - * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge - * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge - * @retval None - */ -#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - do{ \ - TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ - }while(0) - -/** - * @} - */ -/* End of exported macros ----------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup TIM_Private_Constants TIM Private Constants - * @{ - */ -/* The counter of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) -#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) -/** - * @} - */ -/* End of private constants --------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup TIM_Private_Macros TIM Private Macros - * @{ - */ - -#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) - -#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ - ((__BASE__) == TIM_DMABASE_CR2) || \ - ((__BASE__) == TIM_DMABASE_SMCR) || \ - ((__BASE__) == TIM_DMABASE_DIER) || \ - ((__BASE__) == TIM_DMABASE_SR) || \ - ((__BASE__) == TIM_DMABASE_EGR) || \ - ((__BASE__) == TIM_DMABASE_CCMR1) || \ - ((__BASE__) == TIM_DMABASE_CCMR2) || \ - ((__BASE__) == TIM_DMABASE_CCER) || \ - ((__BASE__) == TIM_DMABASE_CNT) || \ - ((__BASE__) == TIM_DMABASE_PSC) || \ - ((__BASE__) == TIM_DMABASE_ARR) || \ - ((__BASE__) == TIM_DMABASE_RCR) || \ - ((__BASE__) == TIM_DMABASE_CCR1) || \ - ((__BASE__) == TIM_DMABASE_CCR2) || \ - ((__BASE__) == TIM_DMABASE_CCR3) || \ - ((__BASE__) == TIM_DMABASE_CCR4) || \ - ((__BASE__) == TIM_DMABASE_BDTR) || \ - ((__BASE__) == TIM_DMABASE_CCMR3) || \ - ((__BASE__) == TIM_DMABASE_CCR5) || \ - ((__BASE__) == TIM_DMABASE_CCR6) || \ - ((__BASE__) == TIM_DMABASE_OR1) || \ - ((__BASE__) == TIM_DMABASE_OR2) || \ - ((__BASE__) == TIM_DMABASE_OR3)) - - -#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - - -#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ - ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) - -#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ - ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ - ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) - -#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ - ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) - -#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ - ((__STATE__) == TIM_OCFAST_ENABLE)) - -#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ - ((__POLARITY__) == TIM_OCPOLARITY_LOW)) - -#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ - ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) - -#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ - ((__STATE__) == TIM_OCIDLESTATE_RESET)) - -#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ - ((__STATE__) == TIM_OCNIDLESTATE_RESET)) - -#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ - ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) - -#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ - ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ - ((__SELECTION__) == TIM_ICSELECTION_TRC)) - -#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV8)) - -#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ - ((__MODE__) == TIM_OPMODE_REPETITIVE)) - -#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ - ((__MODE__) == TIM_ENCODERMODE_TI2) || \ - ((__MODE__) == TIM_ENCODERMODE_TI12)) - -#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - -#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2) || \ - ((__CHANNEL__) == TIM_CHANNEL_3) || \ - ((__CHANNEL__) == TIM_CHANNEL_4) || \ - ((__CHANNEL__) == TIM_CHANNEL_5) || \ - ((__CHANNEL__) == TIM_CHANNEL_6) || \ - ((__CHANNEL__) == TIM_CHANNEL_ALL)) - -#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2)) - -#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2) || \ - ((__CHANNEL__) == TIM_CHANNEL_3)) - -#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) - -#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) - -#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) - -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) - -#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) - -#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) - -#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) - - -#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ - ((__STATE__) == TIM_OSSR_DISABLE)) - -#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ - ((__STATE__) == TIM_OSSI_DISABLE)) - -#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_3)) - -#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF) - - -#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ - ((__STATE__) == TIM_BREAK_DISABLE)) - -#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) - -#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ - ((__STATE__) == TIM_BREAK2_DISABLE)) - -#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) - -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ - ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) - -#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000)) - -#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ - ((__SOURCE__) == TIM_TRGO_ENABLE) || \ - ((__SOURCE__) == TIM_TRGO_UPDATE) || \ - ((__SOURCE__) == TIM_TRGO_OC1) || \ - ((__SOURCE__) == TIM_TRGO_OC1REF) || \ - ((__SOURCE__) == TIM_TRGO_OC2REF) || \ - ((__SOURCE__) == TIM_TRGO_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO_OC4REF)) - -#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ - ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ - ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ - ((__SOURCE__) == TIM_TRGO2_OC1) || \ - ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ - ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ - ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ - ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) - -#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ - ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) - -#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ - ((__MODE__) == TIM_SLAVEMODE_RESET) || \ - ((__MODE__) == TIM_SLAVEMODE_GATED) || \ - ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ - ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ - ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) - -#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ - ((__MODE__) == TIM_OCMODE_PWM2) || \ - ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ - ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) - -#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ - ((__MODE__) == TIM_OCMODE_ACTIVE) || \ - ((__MODE__) == TIM_OCMODE_INACTIVE) || \ - ((__MODE__) == TIM_OCMODE_TOGGLE) || \ - ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ - ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ - ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ - ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) - -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ETRF)) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_NONE)) - - -#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) - -#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) - -#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) - -#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ - ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) - -#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) - -#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) - -#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF) - -#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) - -#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) - -#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) - -#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12)))) - -#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) - -/** - * @} - */ -/* End of private macros -----------------------------------------------------*/ - -/* Include TIM HAL Extended module */ -#include "stm32l4xx_hal_tim_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions - * @{ - */ -/* Time Base functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions - * @{ - */ -/* Timer Output Compare functions *********************************************/ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions - * @{ - */ -/* Timer PWM functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions - * @{ - */ -/* Timer Input Capture functions **********************************************/ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions - * @{ - */ -/* Timer One Pulse functions **************************************************/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions - * @{ - */ -/* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); - /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * @{ - */ -/* Interrupt Handler functions ***********************************************/ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * @{ - */ -/* Callback in non blocking modes (Interrupt and DMA) *************************/ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions - * @{ - */ -/* Peripheral State functions ************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @defgroup TIM_Private_Functions TIM Private Functions -* @{ -*/ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); - -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); -void TIM_DMAError(DMA_HandleTypeDef *hdma); -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); -/** -* @} -*/ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_TIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h deleted file mode 100644 index eae1c9a32..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h +++ /dev/null @@ -1,484 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_tim_ex.h - * @author MCD Application Team - * @brief Header file of TIM HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_TIM_EX_H -#define __STM32L4xx_HAL_TIM_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIMEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types - * @{ - */ - -/** - * @brief TIM Hall sensor Configuration Structure definition - */ - -typedef struct -{ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ -} TIM_HallSensor_InitTypeDef; - -/** - * @brief TIM Break/Break2 input configuration - */ -typedef struct { - uint32_t Source; /*!< Specifies the source of the timer break input. - This parameter can be a value of @ref TIMEx_Break_Input_Source */ - uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. - This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ - uint32_t Polarity; /*!< Specifies the break input source polarity. - This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity - Not relevant when analog watchdog output of the DFSDM1 used as break input source */ -} TIMEx_BreakInputConfigTypeDef; - -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants - * @{ - */ - -/** @defgroup TIMEx_Remap TIM Extended Remapping - * @{ - */ -#define TIM_TIM1_ETR_ADC1_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD2 */ -#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) -#define TIM_TIM1_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD1 */ -#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1) /* !< TIM1_ETR is connected to ADC3 AWD2 */ -#define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ -#define TIM_TIM1_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM1 TI1 is connected to GPIO */ -#define TIM_TIM1_TI1_COMP1 (TIM1_OR1_TI1_RMP) /* !< TIM1 TI1 is connected to COMP1 */ -#define TIM_TIM1_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM1_ETR is connected to GPIO */ -#define TIM_TIM1_ETR_COMP1 (TIM1_OR2_ETRSEL_0) /* !< TIM1_ETR is connected to COMP1 output */ -#define TIM_TIM1_ETR_COMP2 (TIM1_OR2_ETRSEL_1) /* !< TIM1_ETR is connected to COMP2 output */ - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM2_ITR1_TIM8_TRGO ((uint32_t)(0x00000000)) /* !< TIM2_ITR1 is connected to TIM8_TRGO */ -#define TIM_TIM2_ITR1_OTG_FS_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to OTG_FS SOF */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define TIM_TIM2_ITR1_NONE ((uint32_t)(0x00000000)) /* !< No internal trigger on TIM2_ITR1 */ -#define TIM_TIM2_ITR1_USB_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */ -#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ - /* STM32L451xx || STM32L452xx || STM32L462xx */ -#define TIM_TIM2_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM2_ETR is connected to GPIO */ -#define TIM_TIM2_ETR_LSE (TIM2_OR1_ETR1_RMP) /* !< TIM2_ETR is connected to LSE */ -#define TIM_TIM2_ETR_COMP1 (TIM2_OR2_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 output */ -#define TIM_TIM2_ETR_COMP2 (TIM2_OR2_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 output */ -#define TIM_TIM2_TI4_GPIO ((uint32_t)(0x00000000)) /* !< TIM2 TI4 is connected to GPIO */ -#define TIM_TIM2_TI4_COMP1 (TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to COMP1 output */ -#define TIM_TIM2_TI4_COMP2 (TIM2_OR1_TI4_RMP_1) /* !< TIM2 TI4 is connected to COMP2 output */ -#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */ - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM3_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM3 TI1 is connected to GPIO */ -#define TIM_TIM3_TI1_COMP1 (TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to COMP1 output */ -#define TIM_TIM3_TI1_COMP2 (TIM3_OR1_TI1_RMP_1) /* !< TIM3 TI1 is connected to COMP2 output */ -#define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */ -#define TIM_TIM3_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM3_ETR is connected to GPIO */ -#define TIM_TIM3_ETR_COMP1 (TIM3_OR2_ETRSEL_0) /* !< TIM3_ETR is connected to COMP1 output */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) -#define TIM_TIM8_ETR_ADC2_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */ -#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1) /* !< TIM8_ETR is connected to ADC2 AWD2 */ -#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */ -#define TIM_TIM8_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD1 */ -#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1) /* !< TIM8_ETR is connected to ADC3 AWD2 */ -#define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */ -#define TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */ -#define TIM_TIM8_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM8_ETR is connected to GPIO */ -#define TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */ -#define TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#define TIM_TIM15_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM15 TI1 is connected to GPIO */ -#define TIM_TIM15_TI1_LSE (TIM15_OR1_TI1_RMP) /* !< TIM15 TI1 is connected to LSE */ -#define TIM_TIM15_ENCODERMODE_NONE ((uint32_t)(0x00000000)) /* !< No redirection */ -#define TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0) /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1) /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#define TIM_TIM16_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM16 TI1 is connected to GPIO */ -#define TIM_TIM16_TI1_LSI (TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to LSI */ -#define TIM_TIM16_TI1_LSE (TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to LSE */ -#define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) -#define TIM_TIM16_TI1_MSI (TIM16_OR1_TI1_RMP_2) /* !< TIM16 TI1 is connected to MSI */ -#define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to HSE div 32 */ -#define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to MCO */ -#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ - /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L496xx || STM32L4A6xx */ - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM17_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM17 TI1 is connected to GPIO */ -#define TIM_TIM17_TI1_MSI (TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MSI */ -#define TIM_TIM17_TI1_HSE_32 (TIM17_OR1_TI1_RMP_1) /* !< TIM17 TI1 is connected to HSE div 32 */ -#define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input TIM Extended Break input - * @{ - */ -#define TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */ -#define TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source - * @{ - */ -#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */ -#define TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */ -#define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling - * @{ - */ -#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */ -#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity - * @{ - */ -#define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */ -#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */ -/** - * @} - */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros - * @{ - */ - -/** - * @} - */ -/* End of exported macro -----------------------------------------------------*/ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros - * @{ - */ -#define IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F)) - -#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ - ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1)) -#else -#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ - ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) - -#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) -/** - * @} - */ -/* End of private macro ------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions - * @{ - */ - -/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * @{ - */ -/* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); - -void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); - - /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * @{ - */ -/* Timer Complementary Output Compare functions *****************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * @{ - */ -/* Timer Complementary PWM functions ****************************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * @{ - */ -/* Timer Complementary One Pulse functions **********************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Extended Control functions ************************************************/ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); -HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); - -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions - * @brief Extended Callbacks functions - * @{ - */ -/* Extended Callback **********************************************************/ -void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions - * @brief Extended Peripheral State functions - * @{ - */ -/* Extended Peripheral State functions ***************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions -* @{ -*/ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); -/** -* @} -*/ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L4xx_HAL_TIM_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h deleted file mode 100644 index 34e100955..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h +++ /dev/null @@ -1,1638 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_uart.h - * @author MCD Application Team - * @brief Header file of UART HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_UART_H -#define __STM32L4xx_HAL_UART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UART_Exported_Types UART Exported Types - * @{ - */ - -/** - * @brief UART Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate register is computed using the following formula: - UART: - ===== - - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1 - LPUART: - ======= - Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - - where (uart/lpuart)_ker_ck_pres is the UART input clock divided by a prescaler */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UARTEx_Word_Length. */ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits. */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode. */ - - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). - This parameter can be a value of @ref UART_Over_Sampling. */ - - uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ - -#if defined(USART_PRESC_PRESCALER) - uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. - This parameter can be a value of @ref UART_ClockPrescaler. */ -#endif - -}UART_InitTypeDef; - -/** - * @brief UART Advanced Features initalization structure definition - */ -typedef struct -{ - uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several - Advanced Features may be initialized at the same time . - This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */ - - uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. - This parameter can be a value of @ref UART_Tx_Inv. */ - - uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. - This parameter can be a value of @ref UART_Rx_Inv. */ - - uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic - vs negative/inverted logic). - This parameter can be a value of @ref UART_Data_Inv. */ - - uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. - This parameter can be a value of @ref UART_Rx_Tx_Swap. */ - - uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. - This parameter can be a value of @ref UART_Overrun_Disable. */ - - uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. - This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ - - uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. - This parameter can be a value of @ref UART_AutoBaudRate_Enable */ - - uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate - detection is carried out. - This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ - - uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. - This parameter can be a value of @ref UART_MSB_First. */ -} UART_AdvFeatureInitTypeDef; - - - -/** - * @brief HAL UART State structures definition - * @note HAL UART State value is a combination of 2 different substates: gState and RxState. - * - gState contains UART state information related to global Handle management - * and also information related to Tx operations. - * gState value coding follow below described bitmap : - * b7-b6 Error information - * 00 : No Error - * 01 : (Not Used) - * 10 : Timeout - * 11 : Error - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized. HAL UART Init function already called) - * b4-b3 (not used) - * xx : Should be set to 00 - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) - * b1 (not used) - * x : Should be set to 0 - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) - * 1 : Busy (Tx operation ongoing) - * - RxState contains information related to Rx operations. - * RxState value coding follow below described bitmap : - * b7-b6 (not used) - * xx : Should be set to 00 - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized) - * b4-b2 (not used) - * xxx : Should be set to 000 - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 (not used) - * x : Should be set to 0. - */ -typedef enum -{ - HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ - HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ - HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing - Value is allowed for gState only */ - HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing - Value is allowed for gState only */ - HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing - Value is allowed for RxState only */ - HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ - HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state - Value is allowed for gState only */ - HAL_UART_STATE_ERROR = 0xE0U /*!< Error - Value is allowed for gState only */ -}HAL_UART_StateTypeDef; - -/** - * @brief HAL UART Error Code structure definition - */ -typedef enum -{ - HAL_UART_ERROR_NONE = 0x00U, /*!< No error */ - HAL_UART_ERROR_PE = 0x01U, /*!< Parity error */ - HAL_UART_ERROR_NE = 0x02U, /*!< Noise error */ - HAL_UART_ERROR_FE = 0x04U, /*!< frame error */ - HAL_UART_ERROR_ORE = 0x08U, /*!< Overrun error */ - HAL_UART_ERROR_DMA = 0x10U /*!< DMA transfer error */ -}HAL_UART_ErrorTypeDef; - -/** - * @brief UART clock sources definition - */ -typedef enum -{ - UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ - UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ - UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ - UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ - UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ - UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ -}UART_ClockSourceTypeDef; - -/** - * @brief UART handle Structure definition - */ -typedef struct __UART_HandleTypeDef -{ - USART_TypeDef *Instance; /*!< UART registers base address */ - - UART_InitTypeDef Init; /*!< UART communication parameters */ - - UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ - - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< UART Tx Transfer size */ - - __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< UART Rx Transfer size */ - - __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ - - uint16_t Mask; /*!< UART Rx RDR register mask */ - -#if defined(USART_CR1_FIFOEN) - uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ - - uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - - uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. - This parameter can be a value of @ref UARTEx_FIFO_mode. */ -#endif - -#if defined(USART_CR2_SLVEN) - uint32_t SlaveMode; /*!< Specifies if the UART SPI Slave mode is being used. - This parameter can be a value of @ref UARTEx_Slave_Mode. */ -#endif - - void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - - void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ - - DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ - - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ - - __IO uint32_t ErrorCode; /*!< UART Error code */ - -}UART_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UART_Exported_Constants UART Exported Constants - * @{ - */ - -/** @defgroup UART_Stop_Bits UART Number of Stop Bits - * @{ - */ -#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ -#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ -#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ -#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ -/** - * @} - */ - -/** @defgroup UART_Parity UART Parity - * @{ - */ -#define UART_PARITY_NONE 0x00000000U /*!< No parity */ -#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ -#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ -/** - * @} - */ - -/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control - * @{ - */ -#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ -#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ -#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ -#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ -/** - * @} - */ - -/** @defgroup UART_Mode UART Transfer Mode - * @{ - */ -#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ -#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ -#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ -/** - * @} - */ - -/** @defgroup UART_State UART State - * @{ - */ -#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ -#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ -/** - * @} - */ - -/** @defgroup UART_Over_Sampling UART Over Sampling - * @{ - */ -#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - -/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method - * @{ - */ -#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ -#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ -/** - * @} - */ - -#if defined(USART_PRESC_PRESCALER) -/** @defgroup UART_ClockPrescaler UART Clock Prescaler - * @{ - */ -#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ -#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ -#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ -#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ -#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ -#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ -#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ -#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ -#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ -#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ -#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ -#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ -/** - * @} - */ -#endif - -/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode - * @{ - */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */ -/** - * @} - */ - -/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut - * @{ - */ -#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */ -#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */ -/** - * @} - */ - -/** @defgroup UART_LIN UART Local Interconnection Network mode - * @{ - */ -#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ -#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ -/** - * @} - */ - -/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection - * @{ - */ -#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ -#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ -/** - * @} - */ - -/** @defgroup UART_DMA_Tx UART DMA Tx - * @{ - */ -#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ -#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ -/** - * @} - */ - -/** @defgroup UART_DMA_Rx UART DMA Rx - * @{ - */ -#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ -#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ -/** - * @} - */ - -/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection - * @{ - */ -#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ -#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ -/** - * @} - */ - -/** @defgroup UART_WakeUp_Methods UART WakeUp Methods - * @{ - */ -#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ -#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ -/** - * @} - */ - -/** @defgroup UART_Request_Parameters UART Request Parameters - * @{ - */ -#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ -#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ -#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ -#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ -#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ -/** - * @} - */ - -/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type - * @{ - */ -#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ -#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ -#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ -#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ -#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ -#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ -#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ -#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ -#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ -/** - * @} - */ - -/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion - * @{ - */ -#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ -#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion - * @{ - */ -#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ -#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion - * @{ - */ -#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ -#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap - * @{ - */ -#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ -#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ -/** - * @} - */ - -/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable - * @{ - */ -#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ -#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ -/** - * @} - */ - -/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable - * @{ - */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ -/** - * @} - */ - -/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error - * @{ - */ -#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ -#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ -/** - * @} - */ - -/** @defgroup UART_MSB_First UART Advanced Feature MSB First - * @{ - */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ -#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ -/** - * @} - */ - -/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable - * @{ - */ -#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ -#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ -/** - * @} - */ - -/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable - * @{ - */ -#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ -#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ -/** - * @} - */ - -/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register - * @{ - */ -#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ -/** - * @} - */ - -/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection - * @{ - */ -#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ -#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ -#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */ -/** - * @} - */ - -/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity - * @{ - */ -#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ -#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ -/** - * @} - */ - -/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register - * @{ - */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */ -/** - * @} - */ - -/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register - * @{ - */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ -/** - * @} - */ - -/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask - * @{ - */ -#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ -/** - * @} - */ - -/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value - * @{ - */ -#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ -/** - * @} - */ - -/** @defgroup UART_Flags UART Status Flags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the ISR register - * @{ - */ -#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ -#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ -#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ -#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ -#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ -#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ -#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ -#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ -#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ -#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ -#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ -#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ -#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ -#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ -#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ -#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ -#if defined(USART_CR1_FIFOEN) -#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */ -#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ -#else -#define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */ -#endif -#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ -#if defined(USART_CR1_FIFOEN) -#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ -#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ -#else -#define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */ -#endif -#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ -#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ -#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ -#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ -#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ -/** - * @} - */ - -/** @defgroup UART_Interrupt_definition UART Interrupts Definition - * Elements values convention: 000ZZZZZ0XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * - ZZZZZ : Flag position in the ISR register(5bits) - * @{ - */ -#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ -#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ -#if defined(USART_CR1_FIFOEN) -#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ -#endif -#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ -#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ -#if defined(USART_CR1_FIFOEN) -#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ -#endif -#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ -#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ -#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ -#define UART_IT_CM 0x112EU /*!< UART character match interruption */ -#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ -#if defined(USART_CR1_FIFOEN) -#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ -#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ -#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ -#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ -#endif - -/* Elements values convention: 000000000XXYYYYYb - - YYYYY : Interrupt source position in the XX register (5bits) - - XX : Interrupt source register (2bits) - - 01: CR1 register - - 10: CR2 register - - 11: CR3 register */ -#define UART_IT_ERR 0x0060U /*!< UART error interruption */ - -/* Elements values convention: 0000ZZZZ00000000b - - ZZZZ : Flag position in the ISR register(4bits) */ -#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ -#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ -#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ -/** - * @} - */ - -/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags - * @{ - */ -#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ -#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ -#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ -#if defined(USART_CR1_FIFOEN) -#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ -#endif -#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ -#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ -#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ -#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup UART_Exported_Macros UART Exported Macros - * @{ - */ - -/** @brief Reset UART handle states. - * @param __HANDLE__ UART handle. - * @retval None - */ -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - } while(0) -/** @brief Flush the UART Data registers. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ - } while(0) - -/** @brief Clear the specified UART pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag - * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag - * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_CMF Character Match Clear Flag - * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag - * @retval None - */ -#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - -/** @brief Clear the UART PE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) - -/** @brief Clear the UART FE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) - -/** @brief Clear the UART NE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) - -/** @brief Clear the UART ORE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) - -/** @brief Clear the UART IDLE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) - -#if defined(USART_CR1_FIFOEN) -/** @brief Clear the UART TX FIFO empty clear flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) -#endif - -/** @brief Check whether the specified UART flag is set or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag - * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag - * @arg @ref UART_FLAG_RXFF RXFIFO Full flag - * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag - * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag - * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag - * @arg @ref UART_FLAG_WUF Wake up from stop mode flag - * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) - * @arg @ref UART_FLAG_SBKF Send Break flag - * @arg @ref UART_FLAG_CMF Character match flag - * @arg @ref UART_FLAG_BUSY Busy flag - * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag - * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag - * @arg @ref UART_FLAG_CTS CTS Change flag - * @arg @ref UART_FLAG_LBDF LIN Break detection flag - * @arg @ref UART_FLAG_TXE Transmit data register empty flag - * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag - * @arg @ref UART_FLAG_TC Transmission Complete flag - * @arg @ref UART_FLAG_RXNE Receive data register not empty flag - * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag - * @arg @ref UART_FLAG_IDLE Idle Line detection flag - * @arg @ref UART_FLAG_ORE Overrun Error flag - * @arg @ref UART_FLAG_NE Noise Error flag - * @arg @ref UART_FLAG_FE Framing Error flag - * @arg @ref UART_FLAG_PE Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) - -/** @brief Enable the specified UART interrupt. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref UART_IT_RXFF RXFIFO Full interrupt - * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt - * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt - * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) - - -/** @brief Disable the specified UART interrupt. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref UART_IT_RXFF RXFIFO Full interrupt - * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt - * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt - * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) - -/** @brief Check whether the specified UART interrupt has occurred or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt to check. - * This parameter can be one of the following values: - * @arg @ref UART_IT_RXFF RXFIFO Full interrupt - * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt - * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt - * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) - -/** @brief Check whether the specified UART interrupt source is enabled or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref UART_IT_RXFF RXFIFO Full interrupt - * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt - * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt - * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) - -/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set - * to clear the corresponding interrupt - * This parameter can be one of the following values: - * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag - * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag - * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_CMF Character Match Clear Flag - * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag - * @retval None - */ -#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) - -/** @brief Set a specific UART request flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __REQ__ specifies the request flag to set - * This parameter can be one of the following values: - * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request - * @arg @ref UART_SENDBREAK_REQUEST Send Break Request - * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request - * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request - * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request - * @retval None - */ -#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__)) - -/** @brief Enable the UART one bit sample method. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) - -/** @brief Disable the UART one bit sample method. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) - -/** @brief Enable UART. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) - -/** @brief Disable UART. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) - -/** @brief Enable CTS flow control. - * @note This macro allows to enable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ - } while(0) - -/** @brief Disable CTS flow control. - * @note This macro allows to disable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ - } while(0) - -/** @brief Enable RTS flow control. - * @note This macro allows to enable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ - } while(0) - -/** @brief Disable RTS flow control. - * @note This macro allows to disable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ - } while(0) -/** - * @} - */ - -/* Private variables -----------------------------------------------------*/ -#if defined(USART_PRESC_PRESCALER) -/** @defgroup UART_Private_Variables UART Private Variables - * @{ - */ -static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; -/** - * @} - */ -#endif - -/* Private macros --------------------------------------------------------*/ -/** @defgroup UART_Private_Macros UART Private Macros - * @{ - */ -#if defined(USART_PRESC_PRESCALER) - -/** @brief BRR division operation to set BRR register with LPUART. - * @param __PCLK__ LPUART clock. - * @param __BAUD__ Baud rate set by the user. - * @param __CLOCKPRESCALER__ UART prescaler value. - * @retval Division result - */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((((uint64_t)(__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*256)) + ((__BAUD__)/2)) / (__BAUD__)) - -/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. - * @param __PCLK__ UART clock. - * @param __BAUD__ Baud rate set by the user. - * @param __CLOCKPRESCALER__ UART prescaler value. - * @retval Division result - */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__)) - -/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. - * @param __PCLK__ UART clock. - * @param __BAUD__ Baud rate set by the user. - * @param __CLOCKPRESCALER__ UART prescaler value. - * @retval Division result - */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__)) - -#else - -/** @brief BRR division operation to set BRR register with LPUART. - * @param __PCLK__ LPUART clock. - * @param __BAUD__ Baud rate set by the user. - * @retval Division result - */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__) (((((uint64_t)(__PCLK__)*256)) + ((__BAUD__)/2)) / (__BAUD__)) - -/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. - * @param __PCLK__ UART clock. - * @param __BAUD__ Baud rate set by the user. - * @retval Division result - */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__)) - -/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. - * @param __PCLK__ UART clock. - * @param __BAUD__ Baud rate set by the user. - * @retval Division result - */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__)) - -#endif /* USART_PRESC_PRESCALER */ - -/** @brief Check whether or not UART instance is Low Power UART. - * @param __HANDLE__ specifies the UART Handle. - * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) - */ -#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE(__HANDLE__->Instance)) - -/** @brief Check UART Baud rate. - * @param __BAUDRATE__ Baudrate specified by the user. - * The maximum Baud Rate is derived from the maximum clock on G0 (i.e. 52 MHz) - * divided by the smallest oversampling used on the USART (i.e. 8) - * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) - */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6500001U) - -/** @brief Check UART assertion time. - * @param __TIME__ 5-bit value assertion time. - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) - -/** @brief Check UART deassertion time. - * @param __TIME__ 5-bit value deassertion time. - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) - -/** - * @brief Ensure that UART frame number of stop bits is valid. - * @param __STOPBITS__ UART frame number of stop bits. - * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ -#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ - ((__STOPBITS__) == UART_STOPBITS_1) || \ - ((__STOPBITS__) == UART_STOPBITS_1_5) || \ - ((__STOPBITS__) == UART_STOPBITS_2)) - -/** - * @brief Ensure that LPUART frame number of stop bits is valid. - * @param __STOPBITS__ LPUART frame number of stop bits. - * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ -#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ - ((__STOPBITS__) == UART_STOPBITS_2)) - -/** - * @brief Ensure that UART frame parity is valid. - * @param __PARITY__ UART frame parity. - * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ -#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ - ((__PARITY__) == UART_PARITY_EVEN) || \ - ((__PARITY__) == UART_PARITY_ODD)) - -/** - * @brief Ensure that UART hardware flow control is valid. - * @param __CONTROL__ UART hardware flow control. - * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) - */ -#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ - (((__CONTROL__) == UART_HWCONTROL_NONE) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS) || \ - ((__CONTROL__) == UART_HWCONTROL_CTS) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) - -/** - * @brief Ensure that UART communication mode is valid. - * @param __MODE__ UART communication mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) - -/** - * @brief Ensure that UART state is valid. - * @param __STATE__ UART state. - * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) - */ -#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ - ((__STATE__) == UART_STATE_ENABLE)) - -/** - * @brief Ensure that UART oversampling is valid. - * @param __SAMPLING__ UART oversampling. - * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ -#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ - ((__SAMPLING__) == UART_OVERSAMPLING_8)) - -/** - * @brief Ensure that UART frame sampling is valid. - * @param __ONEBIT__ UART frame sampling. - * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) - */ -#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ - ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) - -/** - * @brief Ensure that UART auto Baud rate detection mode is valid. - * @param __MODE__ UART auto Baud rate detection mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) - -/** - * @brief Ensure that UART receiver timeout setting is valid. - * @param __TIMEOUT__ UART receiver timeout setting. - * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) - */ -#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ - ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) - -/** - * @brief Ensure that UART LIN state is valid. - * @param __LIN__ UART LIN state. - * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) - */ -#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ - ((__LIN__) == UART_LIN_ENABLE)) - -/** - * @brief Ensure that UART LIN break detection length is valid. - * @param __LENGTH__ UART LIN break detection length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ - ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) - -/** - * @brief Ensure that UART DMA TX state is valid. - * @param __DMATX__ UART DMA TX state. - * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) - */ -#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ - ((__DMATX__) == UART_DMA_TX_ENABLE)) - -/** - * @brief Ensure that UART DMA RX state is valid. - * @param __DMARX__ UART DMA RX state. - * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) - */ -#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ - ((__DMARX__) == UART_DMA_RX_ENABLE)) - -/** - * @brief Ensure that UART half-duplex state is valid. - * @param __HDSEL__ UART half-duplex state. - * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) - */ -#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ - ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) - -/** - * @brief Ensure that UART wake-up method is valid. - * @param __WAKEUP__ UART wake-up method . - * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) - */ -#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ - ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) - -/** - * @brief Ensure that UART request parameter is valid. - * @param __PARAM__ UART request parameter. - * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) - */ -#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ - ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ - ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ - ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ - ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) - -/** - * @brief Ensure that UART advanced features initialization is valid. - * @param __INIT__ UART advanced features initialization. - * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) - */ -#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ - UART_ADVFEATURE_TXINVERT_INIT | \ - UART_ADVFEATURE_RXINVERT_INIT | \ - UART_ADVFEATURE_DATAINVERT_INIT | \ - UART_ADVFEATURE_SWAP_INIT | \ - UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ - UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ - UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ - UART_ADVFEATURE_MSBFIRST_INIT)) - -/** - * @brief Ensure that UART frame TX inversion setting is valid. - * @param __TXINV__ UART frame TX inversion setting. - * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ - ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) - -/** - * @brief Ensure that UART frame RX inversion setting is valid. - * @param __RXINV__ UART frame RX inversion setting. - * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ - ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) - -/** - * @brief Ensure that UART frame data inversion setting is valid. - * @param __DATAINV__ UART frame data inversion setting. - * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ - ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) - -/** - * @brief Ensure that UART frame RX/TX pins swap setting is valid. - * @param __SWAP__ UART frame RX/TX pins swap setting. - * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) - */ -#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ - ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) - -/** - * @brief Ensure that UART frame overrun setting is valid. - * @param __OVERRUN__ UART frame overrun setting. - * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) - */ -#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ - ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) - -/** - * @brief Ensure that UART auto Baud rate state is valid. - * @param __AUTOBAUDRATE__ UART auto Baud rate state. - * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) - */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ - ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) - -/** - * @brief Ensure that UART DMA enabling or disabling on error setting is valid. - * @param __DMA__ UART DMA enabling or disabling on error setting. - * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) - */ -#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ - ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) - -/** - * @brief Ensure that UART frame MSB first setting is valid. - * @param __MSBFIRST__ UART frame MSB first setting. - * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) - */ -#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ - ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) - -/** - * @brief Ensure that UART stop mode state is valid. - * @param __STOPMODE__ UART stop mode state. - * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) - */ -#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ - ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) - -/** - * @brief Ensure that UART mute mode state is valid. - * @param __MUTE__ UART mute mode state. - * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) - */ -#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ - ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) - -/** - * @brief Ensure that UART wake-up selection is valid. - * @param __WAKE__ UART wake-up selection. - * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) - */ -#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ - ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ - ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) - -/** - * @brief Ensure that UART driver enable polarity is valid. - * @param __POLARITY__ UART driver enable polarity. - * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) - */ -#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ - ((__POLARITY__) == UART_DE_POLARITY_LOW)) - -#if defined(USART_PRESC_PRESCALER) -/** - * @brief Ensure that UART Prescaler is valid. - * @param __CLOCKPRESCALER__ UART Prescaler value. - * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) - */ -#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) -#endif - -#if defined(USART_CR1_FIFOEN) -/** - * @brief Ensure that UART TXFIFO threshold level is valid. - * @param __THRESHOLD__ UART TXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) - -/** - * @brief Ensure that UART RXFIFO threshold level is valid. - * @param __THRESHOLD__ UART RXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) -#endif - -/** - * @} - */ - -/* Include UART HAL Extended module */ -#include "stm32l4xx_hal_uart_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); -HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart); -void HAL_UART_MspInit(UART_HandleTypeDef *huart); -void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); -/* Transfer Abort functions */ -HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); - -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); -void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart); -void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart); -void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); -void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @{ - */ - -/* Peripheral State and Errors functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions -----------------------------------------------------------*/ -/** @addtogroup UART_Private_Functions UART Private Functions - * @{ - */ - -HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_UART_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h deleted file mode 100644 index 926662f36..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h +++ /dev/null @@ -1,771 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_uart_ex.h - * @author MCD Application Team - * @brief Header file of UART HAL Extended module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_UART_EX_H -#define __STM32L4xx_HAL_UART_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup UARTEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UARTEx_Exported_Types UARTEx Exported Types - * @{ - */ - -/** - * @brief UART wake up from stop mode parameters - */ -typedef struct -{ - uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF). - This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. - If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must - be filled up. */ - - uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. - This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ - - uint8_t Address; /*!< UART/USART node address (7-bit long max). */ -} UART_WakeUpTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants - * @{ - */ - -/** @defgroup UARTEx_Word_Length UARTEx Word Length - * @{ - */ -#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ -/** - * @} - */ - -/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length - * @{ - */ -#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ -/** - * @} - */ - -#if defined(USART_CR2_SLVEN) -/** @defgroup UARTEx_Slave_Select_management UARTEx Slave Select Management - * @{ - */ -#define UART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ -#define UART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ -/** - * @} - */ -#endif - -#if defined(USART_CR1_FIFOEN) -/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level - * @brief UART TXFIFO level - * @{ - */ -#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ -#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ -/** - * @} - */ - -/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level - * @brief UART RXFIFO level - * @{ - */ -#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ -#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ -/** - * @} - */ -#endif - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UARTEx_Exported_Functions - * @{ - */ - -/** @addtogroup UARTEx_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); - -/** - * @} - */ - -/** @addtogroup UARTEx_Exported_Functions_Group2 - * @{ - */ - -/* IO operation functions *****************************************************/ -void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); - -#if defined(USART_CR1_FIFOEN) -void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); -void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); -#endif - -/** - * @} - */ - -/** @addtogroup UARTEx_Exported_Functions_Group3 - * @{ - */ - -/* Peripheral Control functions **********************************************/ -HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); -HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); - -#if defined(USART_CR2_SLVEN) -HAL_StatusTypeDef HAL_UARTEx_EnableSlaveMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_DisableSlaveMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSConfig); -#endif - -#if defined(USART_CR1_FIFOEN) -HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); -HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); -#endif - - -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup UARTEx_Private_Constants UARTEx Private Constants - * @{ - */ -#if defined(USART_CR2_SLVEN) -/** @defgroup UARTEx_Slave_Mode UARTEx Synchronous Slave mode - * @{ - */ -#define UART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ -#define UART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ -/** - * @} - */ -#endif - -#if defined(USART_CR1_FIFOEN) -/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode - * @{ - */ -#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ -/** - * @} - */ -#endif -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup UARTEx_Private_Macros UARTEx Private Macros - * @{ - */ - -/** @brief Report the UART clock source. - * @param __HANDLE__ specifies the UART Handle. - * @param __CLOCKSOURCE__ output variable. - * @retval UART clocking source, written in __CLOCKSOURCE__. - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == UART4) \ - { \ - switch(__HAL_RCC_GET_UART4_SOURCE()) \ - { \ - case RCC_UART4CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART4CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART4CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART4CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == UART5) \ - { \ - switch(__HAL_RCC_GET_UART5_SOURCE()) \ - { \ - case RCC_UART5CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART5CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART5CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART5CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ - case RCC_LPUART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_LPUART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_LPUART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_LPUART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - } while(0) -#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ - case RCC_LPUART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_LPUART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_LPUART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_LPUART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - } while(0) -#elif defined (STM32L432xx) || defined (STM32L442xx) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ - case RCC_LPUART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_LPUART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_LPUART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_LPUART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - } while(0) -#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == UART4) \ - { \ - switch(__HAL_RCC_GET_UART4_SOURCE()) \ - { \ - case RCC_UART4CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART4CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART4CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART4CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ - case RCC_LPUART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_LPUART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_LPUART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_LPUART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - } while(0) -#endif - -/** @brief Report the UART mask to apply to retrieve the received data - * according to the word length and to the parity bits activation. - * @note If PCE = 1, the parity bit is not included in the data extracted - * by the reception API(). - * This masking operation is not carried out in the case of - * DMA transfers. - * @param __HANDLE__: specifies the UART Handle. - * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. - */ -#define UART_MASK_COMPUTATION(__HANDLE__) \ - do { \ - if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x01FF ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x00FF ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x00FF ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x007F ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x007F ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x003F ; \ - } \ - } \ -} while(0) - - -/** - * @brief Ensure that UART frame length is valid. - * @param __LENGTH__ UART frame length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ - ((__LENGTH__) == UART_WORDLENGTH_8B) || \ - ((__LENGTH__) == UART_WORDLENGTH_9B)) - -/** - * @brief Ensure that UART wake-up address length is valid. - * @param __ADDRESS__ UART wake-up address length. - * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) - */ -#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ - ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) - -#if defined(USART_CR2_SLVEN) -/** - * @brief Ensure that UART Negative Slave Select (NSS) pin management is valid. - * @param __NSS__ UART Negative Slave Select pin management. - * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) - */ -#define IS_UART_NSS(__NSS__) (((__NSS__) == UART_NSS_HARD) || \ - ((__NSS__) == UART_NSS_SOFT)) -#endif - -#if defined(USART_CR1_FIFOEN) -/** - * @brief Ensure that UART TXFIFO threshold level is valid. - * @param __THRESHOLD__ UART TXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) - -/** - * @brief Ensure that USART RXFIFO threshold level is valid. - * @param __THRESHOLD__ USART RXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) -#endif - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_UART_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h deleted file mode 100644 index d10baf2e6..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h +++ /dev/null @@ -1,617 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_ll_usb.h - * @author MCD Application Team - * @brief Header file of USB Core HAL module. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_USB_H -#define __STM32L4xx_LL_USB_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL - * @{ - */ - -/** @addtogroup USB_Core - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief USB Mode definition - */ -typedef enum -{ - USB_DEVICE_MODE = 0, - USB_HOST_MODE = 1, - USB_DRD_MODE = 2 - -}USB_ModeTypeDef; - -#if defined (USB_OTG_FS) -/** - * @brief URB States definition - */ -typedef enum { - URB_IDLE = 0, - URB_DONE, - URB_NOTREADY, - URB_NYET, - URB_ERROR, - URB_STALL - -}USB_OTG_URBStateTypeDef; - -/** - * @brief Host channel States definition - */ -typedef enum { - HC_IDLE = 0, - HC_XFRC, - HC_HALTED, - HC_NAK, - HC_NYET, - HC_STALL, - HC_XACTERR, - HC_BBLERR, - HC_DATATGLERR - -}USB_OTG_HCStateTypeDef; - -/** - * @brief PCD Initialization Structure definition - */ -typedef struct -{ - uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t Host_channels; /*!< Host Channels number. - This parameter Depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed_ */ - - uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */ - - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. - This parameter can be any value of @ref USB_EP0_MPS_ */ - - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY_ */ - - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - - uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ - - uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ - - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ - - uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ - - uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ - - uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ - -}USB_OTG_CfgTypeDef; - -typedef struct -{ - uint8_t num; /*!< Endpoint number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t is_stall; /*!< Endpoint stall condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type_ */ - - uint8_t data_pid_start; /*!< Initial data PID - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t even_odd_frame; /*!< IFrame parity - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint16_t tx_fifo_num; /*!< Transmission FIFO number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t maxpacket; /*!< Endpoint Max packet size - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ - - uint32_t xfer_len; /*!< Current transfer length */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ - -}USB_OTG_EPTypeDef; - -typedef struct -{ - uint8_t dev_addr ; /*!< USB device address. - This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ - - uint8_t ch_num; /*!< Host channel number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t ep_num; /*!< Endpoint number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t ep_is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t speed; /*!< USB Host speed. - This parameter can be any value of @ref USB_Core_Speed_ */ - - uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ - - uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ - - uint8_t ep_type; /*!< Endpoint Type. - This parameter can be any value of @ref USB_EP_Type_ */ - - uint16_t max_packet; /*!< Endpoint Max packet size. - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t data_pid; /*!< Initial data PID. - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - - uint32_t xfer_len; /*!< Current transfer length. */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ - - uint8_t toggle_in; /*!< IN transfer current toggle flag. - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t toggle_out; /*!< OUT transfer current toggle flag - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ - - uint32_t ErrCnt; /*!< Host channel error count.*/ - - USB_OTG_URBStateTypeDef urb_state; /*!< URB state. - This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ - - USB_OTG_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ - -}USB_OTG_HCTypeDef; -#endif /* USB_OTG_FS */ - -#if defined (USB) -/** - * @brief USB Initialization Structure definition - */ -typedef struct -{ - uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed */ - - uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */ - - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. - This parameter can be any value of @ref USB_EP0_MPS */ - - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY */ - - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - - uint32_t low_power_enable; /*!< Enable or disable Low Power mode */ - - uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ - - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ -} USB_CfgTypeDef; - -typedef struct -{ - uint8_t num; /*!< Endpoint number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t is_stall; /*!< Endpoint stall condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type */ - - uint16_t pmaadress; /*!< PMA Address - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint16_t pmaaddr0; /*!< PMA Address0 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint16_t pmaaddr1; /*!< PMA Address1 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint8_t doublebuffer; /*!< Double buffer enable - This parameter can be 0 or 1 */ - - uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral - This parameter is added to ensure compatibility across USB peripherals */ - - uint32_t maxpacket; /*!< Endpoint Max packet size - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - - uint32_t xfer_len; /*!< Current transfer length */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ - -} USB_EPTypeDef; -#endif /* USB */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PCD_Exported_Constants PCD Exported Constants - * @{ - */ -#if defined (USB_OTG_FS) -/** @defgroup USB_Core_Mode_ USB Core Mode - * @{ - */ -#define USB_OTG_MODE_DEVICE 0 -#define USB_OTG_MODE_HOST 1 -#define USB_OTG_MODE_DRD 2 -/** - * @} - */ - -/** @defgroup USB_Core_Speed_ USB Core Speed - * @{ - */ -#define USB_OTG_SPEED_HIGH 0 -#define USB_OTG_SPEED_HIGH_IN_FULL 1 -#define USB_OTG_SPEED_LOW 2 -#define USB_OTG_SPEED_FULL 3 -/** - * @} - */ - -/** @defgroup USB_Core_PHY_ USB Core PHY - * @{ - */ -#define USB_OTG_EMBEDDED_PHY 1 -/** - * @} - */ - -/** @defgroup USB_Core_MPS_ USB Core MPS - * @{ - */ -#define USB_OTG_FS_MAX_PACKET_SIZE 64 -#define USB_OTG_MAX_EP0_SIZE 64 -/** - * @} - */ - -/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency - * @{ - */ -#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1) -#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1) -#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1) -#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1) -/** - * @} - */ - -/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval - * @{ - */ -#define DCFG_FRAME_INTERVAL_80 0 -#define DCFG_FRAME_INTERVAL_85 1 -#define DCFG_FRAME_INTERVAL_90 2 -#define DCFG_FRAME_INTERVAL_95 3 -/** - * @} - */ - -/** @defgroup USB_EP0_MPS_ USB EP0 MPS - * @{ - */ -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 -/** - * @} - */ - -/** @defgroup USB_EP_Speed_ USB EP Speed - * @{ - */ -#define EP_SPEED_LOW 0 -#define EP_SPEED_FULL 1 -#define EP_SPEED_HIGH 2 -/** - * @} - */ - -/** @defgroup USB_EP_Type_ USB EP Type - * @{ - */ -#define EP_TYPE_CTRL 0 -#define EP_TYPE_ISOC 1 -#define EP_TYPE_BULK 2 -#define EP_TYPE_INTR 3 -#define EP_TYPE_MSK 3 -/** - * @} - */ - -/** @defgroup USB_STS_Defines_ USB STS Defines - * @{ - */ -#define STS_GOUT_NAK 1 -#define STS_DATA_UPDT 2 -#define STS_XFER_COMP 3 -#define STS_SETUP_COMP 4 -#define STS_SETUP_UPDT 6 -/** - * @} - */ - -/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines - * @{ - */ -#define HCFG_30_60_MHZ 0 -#define HCFG_48_MHZ 1 -#define HCFG_6_MHZ 2 -/** - * @} - */ - -/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines - * @{ - */ -#define HPRT0_PRTSPD_HIGH_SPEED 0 -#define HPRT0_PRTSPD_FULL_SPEED 1 -#define HPRT0_PRTSPD_LOW_SPEED 2 -/** - * @} - */ - -#define HCCHAR_CTRL 0 -#define HCCHAR_ISOC 1 -#define HCCHAR_BULK 2 -#define HCCHAR_INTR 3 - -#define HC_PID_DATA0 0 -#define HC_PID_DATA2 1 -#define HC_PID_DATA1 2 -#define HC_PID_SETUP 3 - -#define GRXSTS_PKTSTS_IN 2 -#define GRXSTS_PKTSTS_IN_XFER_COMP 3 -#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 -#define GRXSTS_PKTSTS_CH_HALTED 7 - -#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE) -#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE) - -#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) -#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) -#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) -#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE) - -#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE)) -#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE)) - -#endif /* USB_OTG_FS */ - -#if defined (USB) -/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS - * @{ - */ -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 -/** - * @} - */ - -/** @defgroup USB_LL_EP_Type USB Low Layer EP Type - * @{ - */ -#define EP_TYPE_CTRL 0 -#define EP_TYPE_ISOC 1 -#define EP_TYPE_BULK 2 -#define EP_TYPE_INTR 3 -#define EP_TYPE_MSK 3 -/** - * @} - */ - -#define BTABLE_ADDRESS (0x000) -#endif /* USB */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -#if defined (USB_OTG_FS) -#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) -#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) - -#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) -#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) -#endif /* USB_OTG_FS */ - -/* Exported functions --------------------------------------------------------*/ -#if defined (USB_OTG_FS) -HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); -HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); -HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed); -HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ); -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); -void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup); -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum); -void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); - -HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq); -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state); -uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); -uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num); -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num); -HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); -#endif /* USB_OTG_FS */ - -#if defined (USB) -HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef Init); -HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef Init); -HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx , uint8_t speed); -HAL_StatusTypeDef USB_FlushRxFifo (USB_TypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ); -HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep ,uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len); -void * USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx , USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx); -HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t dma, uint8_t *psetup); -uint32_t USB_ReadInterrupts (USB_TypeDef *USBx); -uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum); -void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt); - -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx); -void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -#endif /* USB */ -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L4xx_LL_USB_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c deleted file mode 100644 index 5e6dae988..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c +++ /dev/null @@ -1,693 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal.c - * @author MCD Application Team - * @brief HAL module driver. - * This is the common part of the HAL initialization - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. - [..] - The HAL contains two APIs' categories: - (+) Common HAL APIs - (+) Services HAL APIs - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL HAL - * @brief HAL module driver - * @{ - */ - -#ifdef HAL_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** - * @brief STM32L4xx HAL Driver version number - */ -#define __STM32L4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4xx_HAL_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */ -#define __STM32L4xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ -#define __STM32L4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4xx_HAL_VERSION ((__STM32L4xx_HAL_VERSION_MAIN << 24)\ - |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\ - |(__STM32L4xx_HAL_VERSION_SUB2 << 8 )\ - |(__STM32L4xx_HAL_VERSION_RC)) - -#if defined(VREFBUF) -#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms (to be confirmed) */ -#endif /* VREFBUF */ - -/* ------------ SYSCFG registers bit address in the alias region ------------ */ -#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) -/* --- MEMRMP Register ---*/ -/* Alias word address of FB_MODE bit */ -#define MEMRMP_OFFSET SYSCFG_OFFSET -#define FB_MODE_BitNumber ((uint8_t)0x8) -#define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4)) - -/* --- SCSR Register ---*/ -/* Alias word address of SRAM2ER bit */ -#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18) -#define BRER_BitNumber ((uint8_t)0x0) -#define SCSR_SRAM2ER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (BRER_BitNumber * 4)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -__IO uint32_t uwTick; - -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Functions HAL Exported Functions - * @{ - */ - -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the Flash interface the NVIC allocation and initial time base - clock configuration. - (+) De-initialize common part of the HAL. - (+) Configure the time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) SysTick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and - handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __weak - to make override possible in case of other implementations in user file. -@endverbatim - * @{ - */ - -/** - * @brief Configure the Flash prefetch, the Instruction and Data caches, - * the time base source, NVIC and any required global low level hardware - * by calling the HAL_MspInit() callback function to be optionally defined in user file - * stm32l4xx_hal_msp.c. - * - * @note HAL_Init() function is called at the beginning of program after reset and before - * the clock configuration. - * - * @note In the default implementation the System Timer (Systick) is used as source of time base. - * The Systick configuration is based on MSI clock, as MSI is the clock - * used after a system Reset and the NVIC configuration is set to Priority group 4. - * Once done, time base tick starts incrementing: the tick variable counter is incremented - * each 1ms in the SysTick_Handler() interrupt handler. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_Init(void) -{ - /* Configure Flash prefetch, Instruction cache, Data cache */ - /* Default configuration at reset is: */ - /* - Prefetch disabled */ - /* - Instruction cache enabled */ - /* - Data cache enabled */ -#if (INSTRUCTION_CACHE_ENABLE == 0) - __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); -#endif /* INSTRUCTION_CACHE_ENABLE */ - -#if (DATA_CACHE_ENABLE == 0) - __HAL_FLASH_DATA_CACHE_DISABLE(); -#endif /* DATA_CACHE_ENABLE */ - -#if (PREFETCH_ENABLE != 0) - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); -#endif /* PREFETCH_ENABLE */ - - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - - /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ - HAL_InitTick(TICK_INT_PRIORITY); - - /* Init the low level hardware */ - HAL_MspInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief De-initialize common part of the HAL and stop the source of time base. - * @note This function is optional. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DeInit(void) -{ - /* Reset of all peripherals */ - __HAL_RCC_APB1_FORCE_RESET(); - __HAL_RCC_APB1_RELEASE_RESET(); - - __HAL_RCC_APB2_FORCE_RESET(); - __HAL_RCC_APB2_RELEASE_RESET(); - - __HAL_RCC_AHB1_FORCE_RESET(); - __HAL_RCC_AHB1_RELEASE_RESET(); - - __HAL_RCC_AHB2_FORCE_RESET(); - __HAL_RCC_AHB2_RELEASE_RESET(); - - __HAL_RCC_AHB3_FORCE_RESET(); - __HAL_RCC_AHB3_RELEASE_RESET(); - - /* De-Init the low level hardware */ - HAL_MspDeInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initialize the MSP. - * @retval None - */ -__weak void HAL_MspInit(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the MSP. - * @retval None - */ -__weak void HAL_MspDeInit(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief This function configures the source of the time base: - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The SysTick interrupt must have higher priority (numerically lower) - * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - * The function is declared as __weak to be overwritten in case of other - * implementation in user file. - * @param TickPriority Tick interrupt priority. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(SystemCoreClock/1000); - - /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions - * -@verbatim - =============================================================================== - ##### HAL Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Provide a tick value in millisecond - (+) Provide a blocking delay in millisecond - (+) Suspend the time base source interrupt - (+) Resume the time base source interrupt - (+) Get the HAL API driver version - (+) Get the device identifier - (+) Get the device revision identifier - -@endverbatim - * @{ - */ - -/** - * @brief This function is called to increment a global variable "uwTick" - * used as application time base. - * @note In the default implementation, this variable is incremented each 1ms - * in SysTick ISR. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_IncTick(void) -{ - uwTick++; -} - -/** - * @brief Provide a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t HAL_GetTick(void) -{ - return uwTick; -} - -/** - * @brief This function provides minimum delay (in milliseconds) based - * on variable incremented. - * @note In the default implementation , SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals where uwTick - * is incremented. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void HAL_Delay(uint32_t Delay) -{ - uint32_t tickstart = HAL_GetTick(); - uint32_t wait = Delay; - - /* Add a period to guaranty minimum wait */ - if (wait < HAL_MAX_DELAY) - { - wait++; - } - - while((HAL_GetTick() - tickstart) < wait) - { - } -} - -/** - * @brief Suspend Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the SysTick interrupt will be disabled and so Tick increment - * is suspended. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_SuspendTick(void) -{ - /* Disable SysTick Interrupt */ - SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief Resume Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the SysTick interrupt will be enabled and so Tick increment - * is resumed. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_ResumeTick(void) -{ - /* Enable SysTick Interrupt */ - SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief Return the HAL revision. - * @retval version : 0xXYZR (8bits for each decimal, R for RC) - */ -uint32_t HAL_GetHalVersion(void) -{ - return __STM32L4xx_HAL_VERSION; -} - -/** - * @brief Return the device revision identifier. - * @retval Device revision identifier - */ -uint32_t HAL_GetREVID(void) -{ - return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16); -} - -/** - * @brief Return the device identifier. - * @retval Device identifier - */ -uint32_t HAL_GetDEVID(void) -{ - return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); -} - -/** - * @brief Return the first word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw0(void) -{ - return(READ_REG(*((uint32_t *)UID_BASE))); -} - -/** - * @brief Return the second word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw1(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); -} - -/** - * @brief Return the third word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw2(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions - * @brief HAL Debug functions - * -@verbatim - =============================================================================== - ##### HAL Debug functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Enable/Disable Debug module during SLEEP mode - (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes - (+) Enable/Disable Debug module during STANDBY mode - -@endverbatim - * @{ - */ - -/** - * @brief Enable the Debug Module during SLEEP mode. - * @retval None - */ -void HAL_DBGMCU_EnableDBGSleepMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Disable the Debug Module during SLEEP mode. - * @retval None - */ -void HAL_DBGMCU_DisableDBGSleepMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes. - * @retval None - */ -void HAL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes. - * @retval None - */ -void HAL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode. - * @retval None - */ -void HAL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode. - * @retval None - */ -void HAL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions - * @brief HAL SYSCFG configuration functions - * -@verbatim - =============================================================================== - ##### HAL SYSCFG configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start a hardware SRAM2 erase operation - (+) Enable/Disable the Internal FLASH Bank Swapping - (+) Configure the Voltage reference buffer - (+) Enable/Disable the Voltage reference buffer - (+) Enable/Disable the I/O analog switch voltage booster - -@endverbatim - * @{ - */ - -/** - * @brief Start a hardware SRAM2 erase operation. - * @note As long as SRAM2 is not erased the SRAM2ER bit will be set. - * This bit is automatically reset at the end of the SRAM2 erase operation. - * @retval None - */ -void HAL_SYSCFG_SRAM2Erase(void) -{ - /* unlock the write protection of the SRAM2ER bit */ - SYSCFG->SKR = 0xCA; - SYSCFG->SKR = 0x53; - /* Starts a hardware SRAM2 erase operation*/ - *(__IO uint32_t *) SCSR_SRAM2ER_BB = (uint8_t)0x00000001; -} - -/** - * @brief Enable the Internal FLASH Bank Swapping. - * - * @note This function can be used only for STM32L4xx devices. - * - * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) - * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) - * - * @retval None - */ -void HAL_SYSCFG_EnableMemorySwappingBank(void) -{ - *(__IO uint32_t *)FB_MODE_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disable the Internal FLASH Bank Swapping. - * - * @note This function can be used only for STM32L4xx devices. - * - * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) - * and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) - * - * @retval None - */ -void HAL_SYSCFG_DisableMemorySwappingBank(void) -{ - - *(__IO uint32_t *)FB_MODE_BB = (uint32_t)DISABLE; -} - -#if defined(VREFBUF) -/** - * @brief Configure the internal voltage reference buffer voltage scale. - * @param VoltageScaling specifies the output voltage to achieve - * This parameter can be one of the following values: - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. - * This requires VDDA equal to or higher than 2.4 V. - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V. - * This requires VDDA equal to or higher than 2.8 V. - * @retval None - */ -void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); - - MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); -} - -/** - * @brief Configure the internal voltage reference buffer high impedance mode. - * @param Mode specifies the high impedance mode - * This parameter can be one of the following values: - * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. - * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. - * @retval None - */ -void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); - - MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); -} - -/** - * @brief Tune the Internal Voltage Reference buffer (VREFBUF). - * @retval None - */ -void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); - - MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); -} - -/** - * @brief Enable the Internal Voltage Reference buffer (VREFBUF). - * @retval HAL_OK/HAL_TIMEOUT - */ -HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) -{ - uint32_t tickstart = 0; - - SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait for VRR bit */ - while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == RESET) - { - if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Disable the Internal Voltage Reference buffer (VREFBUF). - * - * @retval None - */ -void HAL_SYSCFG_DisableVREFBUF(void) -{ - CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); -} -#endif /* VREFBUF */ - -/** - * @brief Enable the I/O analog switch voltage booster - * - * @retval None - */ -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) -{ - SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); -} - -/** - * @brief Disable the I/O analog switch voltage booster - * - * @retval None - */ -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) -{ - CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c deleted file mode 100644 index 99afff61e..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c +++ /dev/null @@ -1,539 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_cortex.c - * @author MCD Application Team - * @brief CORTEX HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the CORTEX: - * + Initialization and Configuration functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - - [..] - *** How to configure Interrupts using CORTEX HAL driver *** - =========================================================== - [..] - This section provides functions allowing to configure the NVIC interrupts (IRQ). - The Cortex-M4 exceptions are managed by CMSIS functions. - - (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function. - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). - - -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. - The pending IRQ priority will be managed only by the sub priority. - - -@- IRQ priority order (sorted by highest to lowest priority): - (+@) Lowest pre-emption priority - (+@) Lowest sub priority - (+@) Lowest hardware priority (IRQ number) - - [..] - *** How to configure SysTick using CORTEX HAL driver *** - ======================================================== - [..] - Setup SysTick Timer for time base. - - (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which - is a CMSIS function that: - (++) Configures the SysTick Reload register with value passed as function parameter. - (++) Configures the SysTick IRQ priority to the lowest value (0x0F). - (++) Resets the SysTick Counter register. - (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). - (++) Enables the SysTick Interrupt. - (++) Starts the SysTick Counter. - - (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro - __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the - HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined - inside the stm32l4xx_hal_cortex.h file. - - (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function - call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. - - (+) To adjust the SysTick time base, use the following formula: - - Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) - (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function - (++) Reload Value should not exceed 0xFFFFFF - - @endverbatim - ****************************************************************************** - - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. - - ========================================================================================================================== - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ========================================================================================================================== - NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority - | | | 4 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority - | | | 3 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bit for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bit for subpriority - ========================================================================================================================== - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup CORTEX - * @{ - */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup CORTEX_Exported_Functions - * @{ - */ - - -/** @addtogroup CORTEX_Exported_Functions_Group1 - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and Configuration functions ##### - ============================================================================== - [..] - This section provides the CORTEX HAL driver functions allowing to configure Interrupts - SysTick functionalities - -@endverbatim - * @{ - */ - - -/** - * @brief Set the priority grouping field (pre-emption priority and subpriority) - * using the required unlock sequence. - * @param PriorityGroup: The priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, - * 1 bit for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, - * 0 bit for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ - NVIC_SetPriorityGrouping(PriorityGroup); -} - -/** - * @brief Set the priority of an interrupt. - * @param IRQn: External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @param PreemptPriority: The pre-emption priority for the IRQn channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority - * @param SubPriority: the subpriority level for the IRQ channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority. - * @retval None - */ -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t prioritygroup = 0x00; - - /* Check the parameters */ - assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - - prioritygroup = NVIC_GetPriorityGrouping(); - - NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); -} - -/** - * @brief Enable a device specific interrupt in the NVIC interrupt controller. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @retval None - */ -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Enable interrupt */ - NVIC_EnableIRQ(IRQn); -} - -/** - * @brief Disable a device specific interrupt in the NVIC interrupt controller. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @retval None - */ -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Disable interrupt */ - NVIC_DisableIRQ(IRQn); -} - -/** - * @brief Initiate a system reset request to reset the MCU. - * @retval None - */ -void HAL_NVIC_SystemReset(void) -{ - /* System Reset */ - NVIC_SystemReset(); -} - -/** - * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): - * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. - * @retval status: - 0 Function succeeded. - * - 1 Function failed. - */ -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) -{ - return SysTick_Config(TicksNumb); -} -/** - * @} - */ - -/** @addtogroup CORTEX_Exported_Functions_Group2 - * @brief Cortex control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK, MPU) functionalities. - - -@endverbatim - * @{ - */ - -/** - * @brief Get the priority grouping field from the NVIC Interrupt Controller. - * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) - */ -uint32_t HAL_NVIC_GetPriorityGrouping(void) -{ - /* Get the PRIGROUP[10:8] field value */ - return NVIC_GetPriorityGrouping(); -} - -/** - * @brief Get the priority of an interrupt. - * @param IRQn: External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @param PriorityGroup: the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, - * 1 bit for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, - * 0 bit for subpriority - * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority: Pointer on the Subpriority value (starting from 0). - * @retval None - */ -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - /* Get priority for Cortex-M system or device specific interrupts */ - NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); -} - -/** - * @brief Set Pending bit of an external interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @retval None - */ -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Set interrupt pending */ - NVIC_SetPendingIRQ(IRQn); -} - -/** - * @brief Get Pending Interrupt (read the pending register in the NVIC - * and return the pending bit for the specified interrupt). - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Return 1 if pending else 0 */ - return NVIC_GetPendingIRQ(IRQn); -} - -/** - * @brief Clear the pending bit of an external interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @retval None - */ -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Clear pending interrupt */ - NVIC_ClearPendingIRQ(IRQn); -} - -/** - * @brief Get active interrupt (read the active register in NVIC and return the active bit). - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) -{ - /* Return 1 if active else 0 */ - return NVIC_GetActive(IRQn); -} - -/** - * @brief Configure the SysTick clock source. - * @param CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); - if (CLKSource == SYSTICK_CLKSOURCE_HCLK) - { - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - } - else - { - SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; - } -} - -/** - * @brief Handle SYSTICK interrupt request. - * @retval None - */ -void HAL_SYSTICK_IRQHandler(void) -{ - HAL_SYSTICK_Callback(); -} - -/** - * @brief SYSTICK callback. - * @retval None - */ -__weak void HAL_SYSTICK_Callback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SYSTICK_Callback could be implemented in the user file - */ -} - -#if (__MPU_PRESENT == 1) -/** - * @brief Disable the MPU. - * @retval None - */ -void HAL_MPU_Disable(void) -{ - /* Make sure outstanding transfers are done */ - __DMB(); - - /* Disable fault exceptions */ - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - - /* Disable the MPU and clear the control register*/ - MPU->CTRL = 0U; -} - -/** - * @brief Enable the MPU. - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged accessto the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -void HAL_MPU_Enable(uint32_t MPU_Control) -{ - /* Enable the MPU */ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - - /* Enable fault exceptions */ - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; - - /* Ensure MPU settings take effects */ - __DSB(); - __ISB(); -} - -/** - * @brief Initialize and configure the Region and the memory to be protected. - * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains - * the initialization and configuration information. - * @retval None - */ -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) -{ - /* Check the parameters */ - assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); - assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); - - /* Set the Region number */ - MPU->RNR = MPU_Init->Number; - - if ((MPU_Init->Enable) != RESET) - { - /* Check the parameters */ - assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); - assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); - assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); - assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); - assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); - assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); - assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); - - MPU->RBAR = MPU_Init->BaseAddress; - MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | - ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | - ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | - ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | - ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | - ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | - ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | - ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | - ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); - } - else - { - MPU->RBAR = 0x00; - MPU->RASR = 0x00; - } -} -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CORTEX_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c deleted file mode 100644 index 9963ae866..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c +++ /dev/null @@ -1,1179 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_dma.c - * @author MCD Application Team - * @brief DMA HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access (DMA) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and errors functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable and configure the peripheral to be connected to the DMA Channel - (except for internal SRAM / FLASH memories: no initialization is - necessary). Please refer to the Reference manual for connection between peripherals - and DMA requests. - - (#) For a given Channel, program the required configuration through the following parameters: - Channel request, Transfer Direction, Source and Destination data formats, - Circular or Normal mode, Channel Priority level, Source and Destination Increment mode - using HAL_DMA_Init() function. - - Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX - thanks to: - (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ; - (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); - - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error - detection. - - (#) Use HAL_DMA_Abort() function to abort the current transfer - - -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. - - *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source - address and destination address and the Length of data to be transferred - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this - case a fixed Timeout can be configured by User depending from his application. - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. - In this case the DMA interrupt is configured - (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function to register callbacks with HAL_DMA_RegisterCallback(). - - *** DMA HAL driver macros list *** - ============================================= - [..] - Below the list of macros in DMA HAL driver. - - (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. - (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. - (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. - (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. - (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. - (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not. - - [..] - (@) You can refer to the DMA HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup DMA DMA - * @brief DMA HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup DMA_Private_Functions DMA Private Functions - * @{ - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -#if defined(DMAMUX1) -static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); -static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); -#endif /* DMAMUX1 */ - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize the DMA Channel source - and destination addresses, incrementation and data sizes, transfer direction, - circular/normal mode selection, memory-to-memory mode selection and Channel priority value. - [..] - The HAL_DMA_Init() function follows the DMA configuration procedures as described in - reference manual. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DMA according to the specified - * parameters in the DMA_InitTypeDef and initialize the associated handle. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ - uint32_t tmp = 0; - - /* Check the DMA handle allocation */ - if(hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); - assert_param(IS_DMA_MODE(hdma->Init.Mode)); - assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - - assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); - - /* Compute the channel index */ - if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) - { - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; - hdma->DmaBaseAddress = DMA1; - } - else - { - /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; - hdma->DmaBaseAddress = DMA2; - } - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Get the CR register value */ - tmp = hdma->Instance->CCR; - - /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ - tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | - DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | - DMA_CCR_DIR | DMA_CCR_MEM2MEM)); - - /* Prepare the DMA Channel configuration */ - tmp |= hdma->Init.Direction | - hdma->Init.PeriphInc | hdma->Init.MemInc | - hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - hdma->Init.Mode | hdma->Init.Priority; - - /* Write to DMA Channel CR register */ - hdma->Instance->CCR = tmp; - - -#if defined(DMAMUX1) - /* Initialize parameters for DMAMUX channel : - DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask - */ - DMA_CalcDMAMUXChannelBaseAndMask(hdma); - - if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) - { - /* if memory to memory force the request to 0*/ - hdma->Init.Request = DMA_REQUEST_MEM2MEM; - } - - /* Set peripheral request to DMAMUX channel */ - hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); - - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) - { - /* Initialize parameters for DMAMUX request generator : - DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask - */ - DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); - - /* Reset the DMAMUX request generator register*/ - hdma->DMAmuxRequestGen->RGCR = 0U; - - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - } - else - { - hdma->DMAmuxRequestGen = 0U; - hdma->DMAmuxRequestGenStatus = 0U; - hdma->DMAmuxRequestGenStatusMask = 0U; - } -#endif /* DMAMUX1 */ - -#if !defined (DMAMUX1) - - /* Set request selection */ - if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) - { - /* Write to DMA channel selection register */ - if (DMA1 == hdma->DmaBaseAddress) - { - /* Reset request selection for DMA1 Channelx */ - DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex); - - /* Configure request selection for DMA1 Channelx */ - DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); - } - else /* DMA2 */ - { - /* Reset request selection for DMA2 Channelx */ - DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex); - - /* Configure request selection for DMA2 Channelx */ - DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); - } - } - -#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ - - /* Clean callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - - /* Initialise the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - - /* Allocate lock resource and initialize it */ - hdma->Lock = HAL_UNLOCKED; - - return HAL_OK; -} - -/** - * @brief DeInitialize the DMA peripheral. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) -{ - - /* Check the DMA handle allocation */ - if (NULL == hdma ) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - /* Disable the selected DMA Channelx */ - __HAL_DMA_DISABLE(hdma); - - /* Compute the channel index */ - if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) - { - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; - hdma->DmaBaseAddress = DMA1; - } - else - { - /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; - hdma->DmaBaseAddress = DMA2; - } - - /* Reset DMA Channel control register */ - hdma->Instance->CCR = 0; - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); - -#if !defined (DMAMUX1) - - /* Reset DMA channel selection register */ - if (DMA1 == hdma->DmaBaseAddress) - { - /* DMA1 */ - DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); - } - else - { - /* DMA2 */ - DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); - } -#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ - -#if defined(DMAMUX1) - - /* Initialize parameters for DMAMUX channel : - DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ - - DMA_CalcDMAMUXChannelBaseAndMask(hdma); - - /* Reset the DMAMUX channel that corresponds to the DMA channel */ - hdma->DMAmuxChannel->CCR = 0; - - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - /* Reset Request generator parameters if any */ - if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) - { - /* Initialize parameters for DMAMUX request generator : - DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask - */ - DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); - - /* Reset the DMAMUX request generator register*/ - hdma->DMAmuxRequestGen->RGCR = 0U; - - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - } - - hdma->DMAmuxRequestGen = 0U; - hdma->DMAmuxRequestGenStatus = 0U; - hdma->DMAmuxRequestGenStatusMask = 0U; - -#endif /* DMAMUX1 */ - - /* Initialise the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state */ - hdma->State = HAL_DMA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions - * @brief Input and Output operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the source, destination address and data length and Start DMA transfer - (+) Configure the source, destination address and data length and - Start DMA transfer with interrupt - (+) Abort DMA transfer - (+) Poll for transfer complete - (+) Handle DMA interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Start the DMA Transfer. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Configure the source, destination address and the data length & clear flags*/ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - status = HAL_BUSY; - } - return status; -} - -/** - * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Configure the source, destination address and the data length & clear flags*/ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the transfer complete interrupt */ - /* Enable the transfer Error interrupt */ - if(NULL != hdma->XferHalfCpltCallback ) - { - /* Enable the Half transfer complete interrupt as well */ - __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - } - else - { - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); - } - -#ifdef DMAMUX1 - - /* Check if DMAMUX Synchronization is enabled*/ - if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) - { - /* Enable DMAMUX sync overrun IT*/ - hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; - } - - if(hdma->DMAmuxRequestGen != 0U) - { - /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ - /* enable the request gen overrun IT*/ - hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; - } - -#endif /* DMAMUX1 */ - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Remain BUSY */ - status = HAL_BUSY; - } - return status; -} - -/** - * @brief Abort the DMA Transfer. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the DMA peripheral handle */ - if(NULL == hdma) - { - return HAL_ERROR; - } - - /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - -#if defined(DMAMUX1) - /* disable the DMAMUX sync overrun IT*/ - hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; -#endif /* DMAMUX1 */ - - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - -#if defined(DMAMUX1) - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - if(hdma->DMAmuxRequestGen != 0U) - { - /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ - /* disable the request gen overrun IT*/ - hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; - - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - } - -#endif /* DMAMUX1 */ - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @brief Aborts the DMA Transfer in Interrupt mode. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(HAL_DMA_STATE_BUSY != hdma->State) - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - status = HAL_ERROR; - } - else - { - /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - -#if defined(DMAMUX1) - /* disable the DMAMUX sync overrun IT*/ - hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - if(hdma->DMAmuxRequestGen != 0U) - { - /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ - /* disable the request gen overrun IT*/ - hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; - - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - } - -#else - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); -#endif /* DMAMUX1 */ - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Call User Abort callback */ - if(hdma->XferAbortCallback != NULL) - { - hdma->XferAbortCallback(hdma); - } - } - return status; -} - -/** - * @brief Polling for transfer complete. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CompleteLevel: Specifies the DMA level complete. - * @param Timeout: Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) -{ - uint32_t temp; - uint32_t tickstart = 0; - - if(HAL_DMA_STATE_BUSY != hdma->State) - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - __HAL_UNLOCK(hdma); - return HAL_ERROR; - } - - /* Polling mode not supported in circular mode */ - if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - return HAL_ERROR; - } - - /* Get the level transfer complete flag */ - if (HAL_DMA_FULL_TRANSFER == CompleteLevel) - { - /* Transfer Complete flag */ - temp = DMA_FLAG_TC1 << hdma->ChannelIndex; - } - else - { - /* Half Transfer Complete flag */ - temp = DMA_FLAG_HT1 << hdma->ChannelIndex; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(RESET == (hdma->DmaBaseAddress->ISR & temp)) - { - if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))) - { - /* When a DMA transfer error occurs */ - /* A hardware clear of its EN bits is performed */ - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TE; - - /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - } - } - -#if defined(DMAMUX1) - /*Check for DMAMUX Request generator (if used) overrun status */ - if(hdma->DMAmuxRequestGen != 0U) - { - /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ - if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) - { - /* Disable the request gen overrun interrupt */ - hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; - - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; - } - } - - /* Check for DMAMUX Synchronization overrun */ - if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) - { - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; - } -#endif /* DMAMUX1 */ - - if(HAL_DMA_FULL_TRANSFER == CompleteLevel) - { - /* Clear the transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex); - - /* The selected Channelx EN bit is cleared (DMA is disabled and - all transfers are complete) */ - hdma->State = HAL_DMA_STATE_READY; - } - else - { - /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex); - } - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @brief Handle DMA interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval None - */ -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) -{ - uint32_t flag_it = hdma->DmaBaseAddress->ISR; - uint32_t source_it = hdma->Instance->CCR; - - /* Half Transfer Complete Interrupt management ******************************/ - if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) - { - /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - /* Disable the half transfer interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - } - /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << hdma->ChannelIndex); - - /* DMA peripheral state is not updated in Half Transfer */ - /* but in Transfer Complete case */ - - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } - } - - /* Transfer Complete Interrupt management ***********************************/ - else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) - { - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - /* Disable the transfer complete and error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - } - /* Clear the transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << hdma->ChannelIndex); - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete callback */ - hdma->XferCpltCallback(hdma); - } - } - - /* Transfer Error Interrupt management **************************************/ - else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) - { - /* When a DMA transfer error occurs */ - /* A hardware clear of its EN bits is performed */ - /* Disable ALL DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TE; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if (hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } - return; -} - -/** - * @brief Register callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CallbackID: User Callback identifer - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback: pointer to private callbacsk function which has pointer to - * a DMA_HandleTypeDef structure as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = pCallback; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = pCallback; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @brief UnRegister callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CallbackID: User Callback identifer - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = NULL; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = NULL; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = NULL; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = NULL; - break; - - case HAL_DMA_XFER_ALL_CB_ID: - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @} - */ - - - -/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DMA state - (+) Get error code - -@endverbatim - * @{ - */ - -/** - * @brief Return the DMA hande state. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL state - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) -{ - /* Return DMA handle state */ - return hdma->State; -} - -/** - * @brief Return the DMA error code. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval DMA Error Code - */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) -{ - return hdma->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Sets the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ -#if defined(DMAMUX1) - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - if(hdma->DMAmuxRequestGen != 0U) - { - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - } -#endif - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - - /* Configure DMA Channel data length */ - hdma->Instance->CNDTR = DataLength; - - /* Peripheral to Memory */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Channel destination address */ - hdma->Instance->CPAR = DstAddress; - - /* Configure DMA Channel source address */ - hdma->Instance->CMAR = SrcAddress; - } - /* Memory to Peripheral */ - else - { - /* Configure DMA Channel source address */ - hdma->Instance->CPAR = SrcAddress; - - /* Configure DMA Channel destination address */ - hdma->Instance->CMAR = DstAddress; - } -} - -#if defined(DMAMUX1) - -/** - * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ -static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) -{ - uint32_t channel_number = 0; - DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase; - - /* check if instance is not outside the DMA channel range */ - if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) - { - /* DMA1 */ - DMAMUX1_ChannelBase = DMAMUX1_Channel0; - } - else - { - /* DMA2 */ - DMAMUX1_ChannelBase = DMAMUX1_Channel7; - } - channel_number = (((uint32_t)hdma->Instance & 0xFF) - 8) / 20; - hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_ChannelBase + (hdma->ChannelIndex >> 2) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)); - hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; - hdma->DMAmuxChannelStatusMask = 1U << channel_number; -} - -/** - * @brief Updates the DMA handle with the DMAMUX request generator params - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ - -static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) -{ - uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; - - /* DMA Channels are connected to DMAMUX1 request generator blocks*/ - hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); - - hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; - - hdma->DMAmuxRequestGenStatusMask = 1U << (request - 1U); -} - -#endif /* DMAMUX1 */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_DMA_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c deleted file mode 100644 index 50b09d590..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c +++ /dev/null @@ -1,319 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_dma_ex.c - * @author MCD Application Team - * @brief DMA Extension HAL module driver - * This file provides firmware functions to manage the following - * functionalities of the DMA Extension peripheral: - * + Extended features functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The DMA Extension HAL driver can be used as follows: - - (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. - (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. - Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used - to respectively enable/disable the request generator. - - (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from - the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler. - As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be - called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project - (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -#if defined(DMAMUX1) - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup DMAEx DMAEx - * @brief DMA Extended HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private Constants ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions - * @{ - */ - -/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - - (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. - (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. - Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used - to respectively enable/disable the request generator. - -@endverbatim - * @{ - */ - - -/** - * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance). - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. - * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); - - assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity)); - assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); - assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); - assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); - - /*Check if the DMA state is ready */ - if(hdma->State == HAL_DMA_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hdma); - - /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ - MODIFY_REG( hdma->DMAmuxChannel->CCR, \ - (~DMAMUX_CxCR_DMAREQ_ID) , \ - ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ - pSyncConfig->SyncPolarity | (pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ - (pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); - - /* Process UnLocked */ - __HAL_UNLOCK(hdma); - - return HAL_OK; - } - else - { - /*DMA State not Ready*/ - return HAL_ERROR; - } -} - -/** - * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. - * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : - * contains the request generator parameters. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); - - assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); - assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); - - /* check if the DMA state is ready - and DMA is using a DMAMUX request generator block - */ - if((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U)) - { - /* Process Locked */ - __HAL_LOCK(hdma); - - /* Set the request generator new parameters*/ - hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ - ((pRequestGeneratorConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_RGxCR_GNBREQ))| \ - pRequestGeneratorConfig->Polarity; - /* Process UnLocked */ - __HAL_UNLOCK(hdma); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance). - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - /* check if the DMA state is ready - and DMA is using a DMAMUX request generator block - */ - if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) - { - - /* Enable the request generator*/ - hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance). - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - /* check if the DMA state is ready - and DMA is using a DMAMUX request generator block - */ - if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) - { - - /* Disable the request generator*/ - hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Handles DMAMUX interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. - * @retval None - */ -void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) -{ - /* Check for DMAMUX Synchronization overrun */ - if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) - { - /* Disable the synchro overrun interrupt */ - hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; - - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } - - if(hdma->DMAmuxRequestGen != 0) - { - /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ - if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) - { - /* Disable the request gen overrun interrupt */ - hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; - - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } - } -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DMAMUX1 */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c deleted file mode 100644 index ec118ec83..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c +++ /dev/null @@ -1,835 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_flash.c - * @author MCD Application Team - * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the internal FLASH memory: - * + Program operations functions - * + Memory Control functions - * + Peripheral Errors functions - * - @verbatim - ============================================================================== - ##### FLASH peripheral features ##### - ============================================================================== - - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses - to the Flash memory. It implements the erase and program Flash memory operations - and the read and write protection mechanisms. - - [..] The Flash memory interface accelerates code execution with a system of instruction - prefetch and cache lines. - - [..] The FLASH main features are: - (+) Flash memory read operations - (+) Flash memory program/erase operations - (+) Read / write protections - (+) Option bytes programming - (+) Prefetch on I-Code - (+) 32 cache lines of 4*64 bits on I-Code - (+) 8 cache lines of 4*64 bits on D-Code - (+) Error code correction (ECC) : Data in flash are 72-bits word - (8 bits added per double word) - - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH - memory of all STM32L4xx devices. - - (#) Flash Memory IO Programming functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and - HAL_FLASH_Lock() functions - (++) Program functions: double word and fast program (full row programming) - (++) There Two modes of programming : - (+++) Polling mode using HAL_FLASH_Program() function - (+++) Interrupt mode using HAL_FLASH_Program_IT() function - - (#) Interrupts and flags management functions : - (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() - (++) Callback functions are called when the flash operations are finished : - HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise - HAL_FLASH_OperationErrorCallback() - (++) Get error flag status by calling HAL_GetError() - - (#) Option bytes management functions : - (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and - HAL_FLASH_OB_Lock() functions - (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function. - In this case, a reset is generated - - [..] - In addition to these functions, this driver includes a set of macros allowing - to handle the following operations: - (+) Set the latency - (+) Enable/Disable the prefetch buffer - (+) Enable/Disable the Instruction cache and the Data cache - (+) Reset the Instruction cache and the Data cache - (+) Enable/Disable the Flash power-down during low-power run and sleep modes - (+) Enable/Disable the Flash interrupts - (+) Monitor the Flash flags status - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASH FLASH - * @brief FLASH HAL module driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define FLASH_NB_DOUBLE_WORDS_IN_ROW 64 -#else -#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32 -#endif -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Variables FLASH Private Variables - * @{ - */ -/** - * @brief Variable used for Program/Erase sectors under interruption - */ -FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASH_Private_Functions FLASH Private Functions - * @{ - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -extern void FLASH_PageErase(uint32_t Page, uint32_t Banks); -extern void FLASH_FlushCaches(void); -static void FLASH_SetErrorCode(void); -static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); -static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Functions FLASH Exported Functions - * @{ - */ - -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions - * -@verbatim - =============================================================================== - ##### Programming operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the FLASH - program operations. - -@endverbatim - * @{ - */ - -/** - * @brief Program double word or fast program of a row at a specified address. - * @param TypeProgram: Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed - * This parameter is the data for the double word program and the address where - * are stored the data for the row fast program - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t prog_bit = 0; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Deactivate the data cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; - } - else - { - pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; - } - - if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) - { - /* Program double-word (64-bit) at a specified address */ - FLASH_Program_DoubleWord(Address, Data); - prog_bit = FLASH_CR_PG; - } - else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)) - { - /* Fast program a 32 row double-word (64-bit) at a specified address */ - FLASH_Program_Fast(Address, (uint32_t)Data); - - /* If it is the last row, the bit will be cleared at the end of the operation */ - if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST) - { - prog_bit = FLASH_CR_FSTPG; - } - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the program operation is completed, disable the PG or FSTPG Bit */ - if (prog_bit != 0) - { - CLEAR_BIT(FLASH->CR, prog_bit); - } - - /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches(); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Program double word or fast program of a row at a specified address with interrupt enabled. - * @param TypeProgram: Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed - * This parameter is the data for the double word program and the address where - * are stored the data for the row fast program - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Deactivate the data cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; - } - else - { - pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; - } - - /* Set internal variables used by the IRQ handler */ - if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST) - { - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST; - } - else - { - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; - } - pFlash.Address = Address; - - /* Enable End of Operation and Error interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); - - if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) - { - /* Program double-word (64-bit) at a specified address */ - FLASH_Program_DoubleWord(Address, Data); - } - else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)) - { - /* Fast program a 32 row double-word (64-bit) at a specified address */ - FLASH_Program_Fast(Address, (uint32_t)Data); - } - - return status; -} - -/** - * @brief Handle FLASH interrupt request. - * @retval None - */ -void HAL_FLASH_IRQHandler(void) -{ - uint32_t tmp_page; - - /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB)); -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - CLEAR_BIT(FLASH->CR, FLASH_CR_MER2); -#endif - - /* Disable the FSTPG Bit only if it is the last row programmed */ - if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST) - { - CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG); - } - - /* Check FLASH operation error flags */ - if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) || -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))) -#else - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))) -#endif - { - /*Save the error code*/ - FLASH_SetErrorCode(); - - /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches() ; - - /* FLASH error interrupt user callback */ - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE) - { - HAL_FLASH_OperationErrorCallback(pFlash.Page); - } - else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE) - { - HAL_FLASH_OperationErrorCallback(pFlash.Bank); - } - else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) || - (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)) - { - HAL_FLASH_OperationErrorCallback(pFlash.Address); - } - - /*Stop the procedure ongoing*/ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - - /* Check FLASH End of Operation flag */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE) - { - /* Nb of pages to erased can be decreased */ - pFlash.NbPagesToErase--; - - /* Check if there are still pages to erase*/ - if(pFlash.NbPagesToErase != 0) - { - /* Indicate user which page has been erased*/ - HAL_FLASH_EndOfOperationCallback(pFlash.Page); - - /* Increment page number */ - pFlash.Page++; - tmp_page = pFlash.Page; - FLASH_PageErase(tmp_page, pFlash.Bank); - } - else - { - /* No more pages to Erase */ - /* Reset Address and stop Erase pages procedure */ - pFlash.Page = 0xFFFFFFFF; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - - /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches() ; - - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(pFlash.Page); - } - } - else - { - /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches() ; - - if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE) - { - /* MassErase ended. Return the selected bank */ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(pFlash.Bank); - } - else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) || - (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)) - { - /* Program ended. Return the selected address */ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(pFlash.Address); - } - - /*Clear the procedure ongoing*/ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - } - - if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) - { - /* Disable End of Operation and Error interrupts */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - } -} - -/** - * @brief FLASH end of operation interrupt callback. - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * Mass Erase: Bank number which has been requested to erase - * Page Erase: Page which has been erased - * (if 0xFFFFFFFF, it means that all the selected pages have been erased) - * Program: Address which was selected for data program - * @retval None - */ -__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ -} - -/** - * @brief FLASH operation error interrupt callback. - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * Mass Erase: Bank number which has been requested to erase - * Page Erase: Page number which returned an error - * Program: Address which was selected for data program - * @retval None - */ -__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief Management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the FLASH - memory operations. - -@endverbatim - * @{ - */ - -/** - * @brief Unlock the FLASH control register access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) - { - /* Authorize the FLASH Registers access */ - WRITE_REG(FLASH->KEYR, FLASH_KEY1); - WRITE_REG(FLASH->KEYR, FLASH_KEY2); - - /* Verify Flash is unlocked */ - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) - { - status = HAL_ERROR; - } - } - - return status; -} - -/** - * @brief Lock the FLASH control register access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - SET_BIT(FLASH->CR, FLASH_CR_LOCK); - - return HAL_OK; -} - -/** - * @brief Unlock the FLASH Option Bytes Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) -{ - if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != RESET) - { - /* Authorizes the Option Byte register programming */ - WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); - WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Lock the FLASH Option Bytes Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ - SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK); - - return HAL_OK; -} - -/** - * @brief Launch the option byte loading. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) -{ - /* Set the bit to force the option byte reloading */ - SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); - - /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time Errors of the FLASH peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Get the specific FLASH error flag. - * @retval FLASH_ErrorCode: The returned value can be: - * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) - * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag - * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag - * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag - * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag - * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag - * @arg HAL_FLASH_ERROR_NONE: No error set - * @arg HAL_FLASH_ERROR_OP: FLASH Operation error - * @arg HAL_FLASH_ERROR_PROG: FLASH Programming error - * @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error - * @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error - * @arg HAL_FLASH_ERROR_SIZ: FLASH Size error - * @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error - * @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error - * @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error - * @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error - * @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error - * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices) - * @arg HAL_FLASH_ERROR_ECCD: FLASH two ECC errors have been detected - */ -uint32_t HAL_FLASH_GetError(void) -{ - return pFlash.ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** @addtogroup FLASH_Private_Functions - * @{ - */ - -/** - * @brief Wait for a FLASH operation to complete. - * @param Timeout: maximum flash operation timeout - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) -{ - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) - { - if(Timeout != HAL_MAX_DELAY) - { - if((HAL_GetTick() - tickstart) >= Timeout) - { - return HAL_TIMEOUT; - } - } - } - - if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) || -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))) -#else - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))) -#endif - { - /*Save the error code*/ - FLASH_SetErrorCode(); - - return HAL_ERROR; - } - - /* Check FLASH End of Operation flag */ - if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - - /* If there is an error flag set */ - return HAL_OK; -} - -/** - * @brief Set the specific FLASH error flag. - * @retval None - */ -static void FLASH_SetErrorCode(void) -{ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OP; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZ; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_MIS; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_FAST; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_ECCD; - } - -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PEMPTY; - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PEMPTY); - } -#endif - - /* Clear error programming flags */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); -} - -/** - * @brief Program double-word (64-bit) at a specified address. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval None - */ -static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) -{ - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Set PG bit */ - SET_BIT(FLASH->CR, FLASH_CR_PG); - - /* Program the double word */ - *(__IO uint32_t*)Address = (uint32_t)Data; - *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); -} - -/** - * @brief Fast program a row double-word (64-bit) at a specified address. - * @param Address: specifies the address to be programmed. - * @param DataAddress: specifies the address where the data are stored. - * @retval None - */ -static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) -{ - uint8_t row_index = (2*FLASH_NB_DOUBLE_WORDS_IN_ROW); - __IO uint32_t *dest_addr = (__IO uint32_t*)Address; - __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress; - - /* Check the parameters */ - assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address)); - - /* Set FSTPG bit */ - SET_BIT(FLASH->CR, FLASH_CR_FSTPG); - - /* Disable interrupts to avoid any interruption during the loop */ - __disable_irq(); - - /* Program the double word of the row */ - do - { - *dest_addr++ = *src_addr++; - } while (--row_index != 0); - - /* Re-enable the interrupts */ - __enable_irq(); -} - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c deleted file mode 100644 index 1ba98a0c1..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c +++ /dev/null @@ -1,1305 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_flash_ex.c - * @author MCD Application Team - * @brief Extended FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the FLASH extended peripheral: - * + Extended programming operations functions - * - @verbatim - ============================================================================== - ##### Flash Extended features ##### - ============================================================================== - - [..] Comparing to other previous devices, the FLASH interface for STM32L4xx - devices contains the following additional features - - (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write - capability (RWW) - (+) Dual bank memory organization - (+) PCROP protection for all banks - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory - of all STM32L4xx devices. It includes - (#) Flash Memory Erase functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and - HAL_FLASH_Lock() functions - (++) Erase function: Erase page, erase all sectors - (++) There are two modes of erase : - (+++) Polling Mode using HAL_FLASHEx_Erase() - (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() - - (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to : - (++) Set/Reset the write protection - (++) Set the Read protection Level - (++) Program the user Option Bytes - (++) Configure the PCROP protection - - (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to : - (++) Get the value of a write protection area - (++) Know if the read protection is activated - (++) Get the value of the user Option Bytes - (++) Get the value of a PCROP area - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASHEx FLASHEx - * @brief FLASH Extended HAL module driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Variables FLASHEx Private Variables - * @{ - */ -extern FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions - * @{ - */ -extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -void FLASH_PageErase(uint32_t Page, uint32_t Banks); -static void FLASH_MassErase(uint32_t Banks); -void FLASH_FlushCaches(void); -static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); -static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel); -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig); -static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr); -static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset); -static uint32_t FLASH_OB_GetRDP(void); -static uint32_t FLASH_OB_GetUser(void); -static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr); -/** - * @} - */ - -/* Exported functions -------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions - * @{ - */ - -/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions - * @brief Extended IO operation functions - * -@verbatim - =============================================================================== - ##### Extended programming operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the Extended FLASH - programming operations Operations. - -@endverbatim - * @{ - */ -/** - * @brief Perform a mass erase or erase the specified FLASH memory pages. - * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @param[out] PageError : pointer to variable that contains the configuration - * information on faulty page in case of error (0xFFFFFFFF means that all - * the pages have been correctly erased) - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t page_index = 0; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Deactivate the cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) - { - /* Disable instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED; - } - else - { - pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED; - } - } - else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; - } - else - { - pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; - } - - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /* Mass erase to be done */ - FLASH_MassErase(pEraseInit->Banks); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* If the erase operation is completed, disable the MER1 and MER2 Bits */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); -#else - /* If the erase operation is completed, disable the MER1 Bit */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1)); -#endif - } - else - { - /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFF; - - for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++) - { - FLASH_PageErase(page_index, pEraseInit->Banks); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the PER Bit */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB)); - - if (status != HAL_OK) - { - /* In case of error, stop erase procedure and return the faulty address */ - *PageError = page_index; - break; - } - } - } - - /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches(); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. - * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Deactivate the cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) - { - /* Disable instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED; - } - else - { - pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED; - } - } - else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; - } - else - { - pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; - } - - /* Enable End of Operation and Error interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); - - pFlash.Bank = pEraseInit->Banks; - - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /* Mass erase to be done */ - pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE; - FLASH_MassErase(pEraseInit->Banks); - } - else - { - /* Erase by page to be done */ - pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE; - pFlash.NbPagesToErase = pEraseInit->NbPages; - pFlash.Page = pEraseInit->Page; - - /*Erase 1st page and wait for IT */ - FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks); - } - - return status; -} - -/** - * @brief Program Option bytes. - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); - - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Write protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_WRP) != RESET) - { - /* Configure of Write protection on the selected area */ - if(FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK) - { - status = HAL_ERROR; - } - - } - - /* Read protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET) - { - /* Configure the Read protection level */ - if(FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK) - { - status = HAL_ERROR; - } - } - - /* User Configuration */ - if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET) - { - /* Configure the user option bytes */ - if(FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK) - { - status = HAL_ERROR; - } - } - - /* PCROP Configuration */ - if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET) - { - if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr) - { - /* Configure the Proprietary code readout protection */ - if(FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr) != HAL_OK) - { - status = HAL_ERROR; - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Get the Option bytes configuration. - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that contains the - * configuration information. - * @note The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate - * which area is requested for the WRP and PCROP, else no information will be returned - * - * @retval None - */ -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) -{ - pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER); - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) || - (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB)) -#else - if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB)) -#endif - { - pOBInit->OptionType |= OPTIONBYTE_WRP; - /* Get write protection on the selected area */ - FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset)); - } - - /* Get Read protection level */ - pOBInit->RDPLevel = FLASH_OB_GetRDP(); - - /* Get the user option bytes */ - pOBInit->USERConfig = FLASH_OB_GetUser(); - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2)) -#else - if(pOBInit->PCROPConfig == FLASH_BANK_1) -#endif - { - pOBInit->OptionType |= OPTIONBYTE_PCROP; - /* Get the Proprietary code readout protection */ - FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr)); - } -} - -/** - * @} - */ - -#if defined (FLASH_CFGR_LVEN) -/** @defgroup FLASHEx_Exported_Functions_Group2 Extended specific configuration functions - * @brief Extended specific configuration functions - * -@verbatim - =============================================================================== - ##### Extended specific configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the Extended FLASH - specific configurations. - -@endverbatim - * @{ - */ - -/** - * @brief Configuration of the LVE pin of the Flash (managed by power controller - * or forced to low in order to use an external SMPS) - * @param ConfigLVE: Configuration of the LVE pin, - * This parameter can be one of the following values: - * @arg FLASH_LVE_PIN_CTRL: LVE FLASH pin controlled by power controller - * @arg FLASH_LVE_PIN_FORCED: LVE FLASH pin enforced to low (external SMPS used) - * - * @note Before enforcing the LVE pin to low, the SOC should be in low voltage - * range 2 and the voltage VDD12 should be higher than 1.08V and SMPS is ON. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_LVE_PIN(ConfigLVE)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - /* Check that the voltage scaling is range 2 */ - if (HAL_PWREx_GetVoltageRange() == PWR_REGULATOR_VOLTAGE_SCALE2) - { - /* Configure the LVEN bit */ - MODIFY_REG(FLASH->CFGR, FLASH_CFGR_LVEN, ConfigLVE); - - /* Check that the bit has been correctly configured */ - if (READ_BIT(FLASH->CFGR, FLASH_CFGR_LVEN) != ConfigLVE) - { - status = HAL_ERROR; - } - } - else - { - /* Not allow to force Flash LVE pin if not in voltage range 2 */ - status = HAL_ERROR; - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @} - */ -#endif /* FLASH_CFGR_LVEN */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** @addtogroup FLASHEx_Private_Functions - * @{ - */ -/** - * @brief Mass erase of FLASH memory. - * @param Banks: Banks to be erased - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: Bank1 to be erased - * @arg FLASH_BANK_2: Bank2 to be erased - * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased - * @retval None - */ -static void FLASH_MassErase(uint32_t Banks) -{ -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != RESET) -#endif - { - /* Check the parameters */ - assert_param(IS_FLASH_BANK(Banks)); - - /* Set the Mass Erase Bit for the bank 1 if requested */ - if((Banks & FLASH_BANK_1) != RESET) - { - SET_BIT(FLASH->CR, FLASH_CR_MER1); - } - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* Set the Mass Erase Bit for the bank 2 if requested */ - if((Banks & FLASH_BANK_2) != RESET) - { - SET_BIT(FLASH->CR, FLASH_CR_MER2); - } -#endif - } -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - else - { - SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); - } -#endif - - /* Proceed to erase all sectors */ - SET_BIT(FLASH->CR, FLASH_CR_STRT); -} - -/** - * @brief Erase the specified FLASH memory page. - * @param Page: FLASH page to erase - * This parameter must be a value between 0 and (max number of pages in the bank - 1) - * @param Banks: Bank(s) where the page will be erased - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: Page in bank 1 to be erased - * @arg FLASH_BANK_2: Page in bank 2 to be erased - * @retval None - */ -void FLASH_PageErase(uint32_t Page, uint32_t Banks) -{ - /* Check the parameters */ - assert_param(IS_FLASH_PAGE(Page)); - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if(READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) - { - CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); - } - else -#endif - { - assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); - - if((Banks & FLASH_BANK_1) != RESET) - { - CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); - } - else - { - SET_BIT(FLASH->CR, FLASH_CR_BKER); - } - } -#endif - - /* Proceed to erase the page */ - MODIFY_REG(FLASH->CR, FLASH_CR_PNB, (Page << POSITION_VAL(FLASH_CR_PNB))); - SET_BIT(FLASH->CR, FLASH_CR_PER); - SET_BIT(FLASH->CR, FLASH_CR_STRT); -} - -/** - * @brief Flush the instruction and data caches. - * @retval None - */ -void FLASH_FlushCaches(void) -{ - /* Flush instruction cache */ - if((pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_ENABLED) || - (pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) - { - /* Reset instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_RESET(); - /* Enable instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); - } - - /* Flush data cache */ - if((pFlash.CacheToReactivate == FLASH_CACHE_DCACHE_ENABLED) || - (pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) - { - /* Reset data cache */ - __HAL_FLASH_DATA_CACHE_RESET(); - /* Enable data cache */ - __HAL_FLASH_DATA_CACHE_ENABLE(); - } - - /* Reset internal variable */ - pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; -} - -/** - * @brief Configure the write protection of the desired pages. - * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase Flash memory if the CPU debug - * features are connected (JTAG or single wire) or boot code is being - * executed from RAM or System flash, even if WRP is not activated. - * @note To configure the WRP options, the option lock bit OPTLOCK must be - * cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the WRP options, the option bytes must be reloaded - * through the call of the HAL_FLASH_OB_Launch() function. - * - * @param WRPArea: specifies the area to be configured. - * This parameter can be one of the following values: - * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A - * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B - * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply for STM32L43x/STM32L44x devices) - * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply for STM32L43x/STM32L44x devices) - * - * @param WRPStartOffset: specifies the start page of the write protected area - * This parameter can be page number between 0 and (max number of pages in the bank - 1) - * - * @param WRDPEndOffset: specifies the end page of the write protected area - * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1) - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WRPAREA(WRPArea)); - assert_param(IS_FLASH_PAGE(WRPStartOffset)); - assert_param(IS_FLASH_PAGE(WRDPEndOffset)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Configure the write protected area */ - if(WRPArea == OB_WRPAREA_BANK1_AREAA) - { - MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), - (WRPStartOffset | (WRDPEndOffset << 16))); - } - else if(WRPArea == OB_WRPAREA_BANK1_AREAB) - { - MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), - (WRPStartOffset | (WRDPEndOffset << 16))); - } -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - else if(WRPArea == OB_WRPAREA_BANK2_AREAA) - { - MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), - (WRPStartOffset | (WRDPEndOffset << 16))); - } - else if(WRPArea == OB_WRPAREA_BANK2_AREAB) - { - MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), - (WRPStartOffset | (WRDPEndOffset << 16))); - } -#endif - - /* Set OPTSTRT Bit */ - SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the option byte program operation is completed, disable the OPTSTRT Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - } - - return status; -} - -/** - * @brief Set the read protection level. - * - * @note To configure the RDP level, the option lock bit OPTLOCK must be - * cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the RDP level, the option bytes must be reloaded - * through the call of the HAL_FLASH_OB_Launch() function. - * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible - * to go back to level 1 or 0 !!! - * - * @param RDPLevel: specifies the read protection level. - * This parameter can be one of the following values: - * @arg OB_RDP_LEVEL_0: No protection - * @arg OB_RDP_LEVEL_1: Read protection of the memory - * @arg OB_RDP_LEVEL_2: Full chip protection - * - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_RDP_LEVEL(RDPLevel)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Configure the RDP level in the option bytes register */ - MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel); - - /* Set OPTSTRT Bit */ - SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the option byte program operation is completed, disable the OPTSTRT Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - } - - return status; -} - -/** - * @brief Program the FLASH User Option Byte. - * - * @note To configure the user option bytes, the option lock bit OPTLOCK must - * be cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the user option bytes, the option bytes must be reloaded - * through the call of the HAL_FLASH_OB_Launch() function. - * - * @param UserType: The FLASH User Option Bytes to be modified - * @param UserConfig: The FLASH User Option Bytes values: - * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16), - * IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20), - * DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). - * - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) -{ - uint32_t optr_reg_val = 0; - uint32_t optr_reg_mask = 0; - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_USER_TYPE(UserType)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - if((UserType & OB_USER_BOR_LEV) != RESET) - { - /* BOR level option byte should be modified */ - assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV)); - - /* Set value and mask for BOR level option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV); - optr_reg_mask |= FLASH_OPTR_BOR_LEV; - } - - if((UserType & OB_USER_nRST_STOP) != RESET) - { - /* nRST_STOP option byte should be modified */ - assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP)); - - /* Set value and mask for nRST_STOP option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP); - optr_reg_mask |= FLASH_OPTR_nRST_STOP; - } - - if((UserType & OB_USER_nRST_STDBY) != RESET) - { - /* nRST_STDBY option byte should be modified */ - assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY)); - - /* Set value and mask for nRST_STDBY option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY); - optr_reg_mask |= FLASH_OPTR_nRST_STDBY; - } - - if((UserType & OB_USER_nRST_SHDW) != RESET) - { - /* nRST_SHDW option byte should be modified */ - assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW)); - - /* Set value and mask for nRST_SHDW option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW); - optr_reg_mask |= FLASH_OPTR_nRST_SHDW; - } - - if((UserType & OB_USER_IWDG_SW) != RESET) - { - /* IWDG_SW option byte should be modified */ - assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW)); - - /* Set value and mask for IWDG_SW option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW); - optr_reg_mask |= FLASH_OPTR_IWDG_SW; - } - - if((UserType & OB_USER_IWDG_STOP) != RESET) - { - /* IWDG_STOP option byte should be modified */ - assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP)); - - /* Set value and mask for IWDG_STOP option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP); - optr_reg_mask |= FLASH_OPTR_IWDG_STOP; - } - - if((UserType & OB_USER_IWDG_STDBY) != RESET) - { - /* IWDG_STDBY option byte should be modified */ - assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY)); - - /* Set value and mask for IWDG_STDBY option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY); - optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; - } - - if((UserType & OB_USER_WWDG_SW) != RESET) - { - /* WWDG_SW option byte should be modified */ - assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW)); - - /* Set value and mask for WWDG_SW option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW); - optr_reg_mask |= FLASH_OPTR_WWDG_SW; - } - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if((UserType & OB_USER_BFB2) != RESET) - { - /* BFB2 option byte should be modified */ - assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2)); - - /* Set value and mask for BFB2 option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2); - optr_reg_mask |= FLASH_OPTR_BFB2; - } - - if((UserType & OB_USER_DUALBANK) != RESET) - { -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* DUALBANK option byte should be modified */ - assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DB1M)); - - /* Set value and mask for DUALBANK option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_DB1M); - optr_reg_mask |= FLASH_OPTR_DB1M; -#else - /* DUALBANK option byte should be modified */ - assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK)); - - /* Set value and mask for DUALBANK option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK); - optr_reg_mask |= FLASH_OPTR_DUALBANK; -#endif - } -#endif - - if((UserType & OB_USER_nBOOT1) != RESET) - { - /* nBOOT1 option byte should be modified */ - assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1)); - - /* Set value and mask for nBOOT1 option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1); - optr_reg_mask |= FLASH_OPTR_nBOOT1; - } - - if((UserType & OB_USER_SRAM2_PE) != RESET) - { - /* SRAM2_PE option byte should be modified */ - assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE)); - - /* Set value and mask for SRAM2_PE option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE); - optr_reg_mask |= FLASH_OPTR_SRAM2_PE; - } - - if((UserType & OB_USER_SRAM2_RST) != RESET) - { - /* SRAM2_RST option byte should be modified */ - assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST)); - - /* Set value and mask for SRAM2_RST option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST); - optr_reg_mask |= FLASH_OPTR_SRAM2_RST; - } - -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ - defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if((UserType & OB_USER_nSWBOOT0) != RESET) - { - /* nSWBOOT0 option byte should be modified */ - assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0)); - - /* Set value and mask for nSWBOOT0 option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0); - optr_reg_mask |= FLASH_OPTR_nSWBOOT0; - } - - if((UserType & OB_USER_nBOOT0) != RESET) - { - /* nBOOT0 option byte should be modified */ - assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0)); - - /* Set value and mask for nBOOT0 option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0); - optr_reg_mask |= FLASH_OPTR_nBOOT0; - } -#endif - - /* Configure the option bytes register */ - MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val); - - /* Set OPTSTRT Bit */ - SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the option byte program operation is completed, disable the OPTSTRT Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - } - - return status; -} - -/** - * @brief Configure the Proprietary code readout protection of the desired addresses. - * - * @note To configure the PCROP options, the option lock bit OPTLOCK must be - * cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the PCROP options, the option bytes must be reloaded - * through the call of the HAL_FLASH_OB_Launch() function. - * - * @param PCROPConfig: specifies the configuration (Bank to be configured and PCROP_RDP option). - * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 - * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE - * - * @param PCROPStartAddr: specifies the start address of the Proprietary code readout protection - * This parameter can be an address between begin and end of the bank - * - * @param PCROPEndAddr: specifies the end address of the Proprietary code readout protection - * This parameter can be an address between PCROPStartAddr and end of the bank - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t reg_value = 0; - uint32_t bank1_addr; -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - uint32_t bank2_addr; -#endif - - /* Check the parameters */ - assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH)); - assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP)); - assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr)); - assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* Get the information about the bank swapping */ - if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) - { - bank1_addr = FLASH_BASE; - bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; - } - else - { - bank1_addr = FLASH_BASE + FLASH_BANK_SIZE; - bank2_addr = FLASH_BASE; - } -#else - bank1_addr = FLASH_BASE; -#endif - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) - { - /* Configure the Proprietary code readout protection */ - if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) - { - reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); - MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); - - reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); - MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); - } - else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) - { - reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); - MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); - - reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); - MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); - } - } - else -#endif - { - /* Configure the Proprietary code readout protection */ - if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) - { - reg_value = ((PCROPStartAddr - bank1_addr) >> 3); - MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); - - reg_value = ((PCROPEndAddr - bank1_addr) >> 3); - MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); - } -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) - { - reg_value = ((PCROPStartAddr - bank2_addr) >> 3); - MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); - - reg_value = ((PCROPEndAddr - bank2_addr) >> 3); - MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); - } -#endif - } - - MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP)); - - /* Set OPTSTRT Bit */ - SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the option byte program operation is completed, disable the OPTSTRT Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - } - - return status; -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * - * @param[in] WRPArea: specifies the area to be returned. - * This parameter can be one of the following values: - * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A - * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B - * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices) - * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices) - * - * @param[out] WRPStartOffset: specifies the address where to copied the start page - * of the write protected area - * - * @param[out] WRDPEndOffset: specifies the address where to copied the end page of - * the write protected area - * - * @retval None - */ -static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset) -{ - /* Get the configuration of the write protected area */ - if(WRPArea == OB_WRPAREA_BANK1_AREAA) - { - *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT); - *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16); - } - else if(WRPArea == OB_WRPAREA_BANK1_AREAB) - { - *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT); - *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16); - } -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - else if(WRPArea == OB_WRPAREA_BANK2_AREAA) - { - *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT); - *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16); - } - else if(WRPArea == OB_WRPAREA_BANK2_AREAB) - { - *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT); - *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16); - } -#endif -} - -/** - * @brief Return the FLASH Read Protection level. - * @retval FLASH ReadOut Protection Status: - * This return value can be one of the following values: - * @arg OB_RDP_LEVEL_0: No protection - * @arg OB_RDP_LEVEL_1: Read protection of the memory - * @arg OB_RDP_LEVEL_2: Full chip protection - */ -static uint32_t FLASH_OB_GetRDP(void) -{ - if ((READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_0) && - (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_2)) - { - return (OB_RDP_LEVEL_1); - } - else - { - return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP)); - } -} - -/** - * @brief Return the FLASH User Option Byte value. - * @retval The FLASH User Option Bytes values: - * For STM32L47x/STM32L48x devices : - * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), - * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), - * BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). - * For STM32L43x/STM32L44x devices : - * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), - * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), - * nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27). - */ -static uint32_t FLASH_OB_GetUser(void) -{ - uint32_t user_config = READ_REG(FLASH->OPTR); - CLEAR_BIT(user_config, FLASH_OPTR_RDP); - - return user_config; -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * - * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option). - * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 - * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE - * - * @param PCROPStartAddr [out]: specifies the address where to copied the start address - * of the Proprietary code readout protection - * - * @param PCROPEndAddr [out]: specifies the address where to copied the end address of - * the Proprietary code readout protection - * - * @retval None - */ -static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr) -{ - uint32_t reg_value = 0; - uint32_t bank1_addr; -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - uint32_t bank2_addr; -#endif - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* Get the information about the bank swapping */ - if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) - { - bank1_addr = FLASH_BASE; - bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; - } - else - { - bank1_addr = FLASH_BASE + FLASH_BANK_SIZE; - bank2_addr = FLASH_BASE; - } -#else - bank1_addr = FLASH_BASE; -#endif - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) - { - if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) - { - reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); - *PCROPStartAddr = (reg_value << 4) + FLASH_BASE; - - reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); - *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; - } - else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) - { - reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); - *PCROPStartAddr = (reg_value << 4) + FLASH_BASE; - - reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); - *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; - } - } - else -#endif - { - if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) - { - reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); - *PCROPStartAddr = (reg_value << 3) + bank1_addr; - - reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); - *PCROPEndAddr = (reg_value << 3) + bank1_addr; - } -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) - { - reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); - *PCROPStartAddr = (reg_value << 3) + bank2_addr; - - reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); - *PCROPEndAddr = (reg_value << 3) + bank2_addr; - } -#endif - } - - *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP); -} -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c deleted file mode 100644 index fbd9462a1..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c +++ /dev/null @@ -1,271 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_flash_ramfunc.c - * @author MCD Application Team - * @brief FLASH RAMFUNC driver. - * This file provides a Flash firmware functions which should be - * executed from internal SRAM - * + FLASH HalfPage Programming - * + FLASH Power Down in Run mode - * - * @verbatim - ============================================================================== - ##### Flash RAM functions ##### - ============================================================================== - - *** ARM Compiler *** - -------------------- - [..] RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate - source module. Using the 'Options for File' dialog you can simply change - the 'Code / Const' area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the - Options for Target' dialog. - - *** ICCARM Compiler *** - ----------------------- - [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". - - *** GNU Compiler *** - -------------------- - [..] RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC - * @brief FLASH functions executed from RAM - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -extern FLASH_ProcessTypeDef pFlash; - -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions -------------------------------------------------------*/ - -/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH in RAM function Exported Functions - * @{ - */ - -/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### ramfunc functions ##### - =============================================================================== - [..] - This subsection provides a set of functions that should be executed from RAM. - -@endverbatim - * @{ - */ - -/** - * @brief Enable the Power down in Run Mode - * @note This function should be called and executed from SRAM memory - * @retval None - */ -__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void) -{ - /* Enable the Power Down in Run mode*/ - __HAL_FLASH_POWER_DOWN_ENABLE(); - - return HAL_OK; - -} - -/** - * @brief Disable the Power down in Run Mode - * @note This function should be called and executed from SRAM memory - * @retval None - */ -__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void) -{ - /* Disable the Power Down in Run mode*/ - __HAL_FLASH_POWER_DOWN_DISABLE(); - - return HAL_OK; -} - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -/** - * @brief Program the FLASH DBANK User Option Byte. - * - * @note To configure the user option bytes, the option lock bit OPTLOCK must - * be cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To modify the DBANK option byte, no PCROP region should be defined. - * To deactivate PCROP, user should perform RDP changing - * - * @param DBankConfig: The FLASH DBANK User Option Byte value. - * This parameter can be one of the following values: - * @arg OB_DBANK_128_BITS: Single-bank with 128-bits data - * @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data - * - * @retval HAL status - */ -__RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) -{ - register uint32_t count, reg; - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check if the PCROP is disabled */ - reg = FLASH->PCROP1SR; - if (reg > FLASH->PCROP1ER) - { - reg = FLASH->PCROP2SR; - if (reg > FLASH->PCROP2ER) - { - /* Disable Flash prefetch */ - __HAL_FLASH_PREFETCH_BUFFER_DISABLE(); - - if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) - { - /* Disable Flash instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - - /* Flush Flash instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_RESET(); - } - - if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable Flash data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - - /* Flush Flash data cache */ - __HAL_FLASH_DATA_CACHE_RESET(); - } - - /* Disable WRP zone 1 of 1st bank if needed */ - reg = FLASH->WRP1AR; - if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> POSITION_VAL(FLASH_WRP1AR_WRP1A_STRT)) <= - ((reg & FLASH_WRP1AR_WRP1A_END) >> POSITION_VAL(FLASH_WRP1AR_WRP1A_END))) - { - MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT); - } - - /* Disable WRP zone 2 of 1st bank if needed */ - reg = FLASH->WRP1BR; - if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> POSITION_VAL(FLASH_WRP1BR_WRP1B_STRT)) <= - ((reg & FLASH_WRP1BR_WRP1B_END) >> POSITION_VAL(FLASH_WRP1BR_WRP1B_END))) - { - MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT); - } - - /* Disable WRP zone 1 of 2nd bank if needed */ - reg = FLASH->WRP2AR; - if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> POSITION_VAL(FLASH_WRP2AR_WRP2A_STRT)) <= - ((reg & FLASH_WRP2AR_WRP2A_END) >> POSITION_VAL(FLASH_WRP2AR_WRP2A_END))) - { - MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT); - } - - /* Disable WRP zone 2 of 2nd bank if needed */ - reg = FLASH->WRP2BR; - if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> POSITION_VAL(FLASH_WRP2BR_WRP2B_STRT)) <= - ((reg & FLASH_WRP2BR_WRP2B_END) >> POSITION_VAL(FLASH_WRP2BR_WRP2B_END))) - { - MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT); - } - - /* Modify the DBANK user option byte */ - MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig); - - /* Set OPTSTRT Bit */ - SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - - /* Wait for last operation to be completed */ - /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */ - count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8 / 1000); - do - { - if (count-- == 0) - { - break; - } - } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET); - - /* If the option byte program operation is completed, disable the OPTSTRT Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - - /* Set the bit to force the option byte reloading */ - SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} -#endif - -/** - * @} - */ - -/** - * @} - */ -#endif /* HAL_FLASH_MODULE_ENABLED */ - - - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c deleted file mode 100644 index 280eb31cf..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c +++ /dev/null @@ -1,568 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_gpio.c - * @author MCD Application Team - * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the General Purpose Input/Output (GPIO) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * - @verbatim - ============================================================================== - ##### GPIO Peripheral features ##### - ============================================================================== - [..] - (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually - configured by software in several modes: - (++) Input mode - (++) Analog mode - (++) Output mode - (++) Alternate function mode - (++) External interrupt/event lines - - (+) During and just after reset, the alternate functions and external interrupt - lines are not active and the I/O ports are configured in input floating mode. - - (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be - activated or not. - - (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull - type and the IO speed can be selected depending on the VDD value. - - (+) The microcontroller IO pins are connected to onboard peripherals/modules through a - multiplexer that allows only one peripheral alternate function (AF) connected - to an IO pin at a time. In this way, there can be no conflict between peripherals - sharing the same IO pin. - - (+) All ports have external interrupt/event capability. To use external interrupt - lines, the port must be configured in input mode. All available GPIO pins are - connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - - (+) The external interrupt/event controller consists of up to 39 edge detectors - (16 lines are connected to GPIO) for generating event/interrupt requests (each - input line can be independently configured to select the type (interrupt or event) - and the corresponding trigger event (rising or falling or both). Each line can - also be masked independently. - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). - - (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). - (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure - (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef - structure. - (++) In case of Output or alternate function mode selection: the speed is - configured through "Speed" member from GPIO_InitTypeDef structure. - (++) In alternate mode is selection, the alternate function connected to the IO - is configured through "Alternate" member from GPIO_InitTypeDef structure. - (++) Analog mode is required when a pin is to be used as ADC channel - or DAC output. - (++) In case of external interrupt/event selection the "Mode" member from - GPIO_InitTypeDef structure select the type (interrupt or event) and - the corresponding trigger event (rising or falling or both). - - (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority - mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using - HAL_NVIC_EnableIRQ(). - - (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). - - (#) To set/reset the level of a pin configured in output mode use - HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - - (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - - (#) During and just after reset, the alternate functions are not - active and the GPIO pins are configured in input floating mode (except JTAG - pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has - priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PH0 and PH1, respectively, when the HSE oscillator is off. - The HSE has priority over the GPIO function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIO GPIO - * @brief GPIO HAL module driver - * @{ - */ - -#ifdef HAL_GPIO_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup GPIO_Private_Defines GPIO Private Defines - * @{ - */ -#define GPIO_MODE ((uint32_t)0x00000003) -#define ANALOG_MODE ((uint32_t)0x00000008) -#define EXTI_MODE ((uint32_t)0x10000000) -#define GPIO_MODE_IT ((uint32_t)0x00010000) -#define GPIO_MODE_EVT ((uint32_t)0x00020000) -#define RISING_EDGE ((uint32_t)0x00100000) -#define FALLING_EDGE ((uint32_t)0x00200000) -#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) - -#define GPIO_NUMBER ((uint32_t)16) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ -/** - * @} - */ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) -{ - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t temp = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); - assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); - - /* Configure the port pins */ - while (((GPIO_Init->Pin) >> position) != RESET) - { - /* Get current io position */ - iocurrent = (GPIO_Init->Pin) & (1U << position); - - if(iocurrent) - { - /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameters */ - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3]; - temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); - GPIOx->AFR[position >> 3] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); - GPIOx->MODER = temp; - - /* In case of Output or Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Speed parameter */ - assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); - /* Configure the IO Speed */ - temp = GPIOx->OSPEEDR; - temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2)); - temp |= (GPIO_Init->Speed << (position * 2)); - GPIOx->OSPEEDR = temp; - - /* Configure the IO Output Type */ - temp = GPIOx->OTYPER; - temp &= ~(GPIO_OTYPER_OT0 << position) ; - temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); - GPIOx->OTYPER = temp; - } - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) - - /* In case of Analog mode, check if ADC control mode is selected */ - if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG) - { - /* Configure the IO Output Type */ - temp = GPIOx->ASCR; - temp &= ~(GPIO_ASCR_ASC0 << position) ; - temp |= (((GPIO_Init->Mode & ANALOG_MODE) >> 3) << position); - GPIOx->ASCR = temp; - } - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - - /* Activate the Pull-up or Pull down resistor for the current IO */ - temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2)); - temp |= ((GPIO_Init->Pull) << (position * 2)); - GPIOx->PUPDR = temp; - - /*--------------------- EXTI Mode Configuration ------------------------*/ - /* Configure the External Interrupt or event for the current IO */ - if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) - { - /* Enable SYSCFG Clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - temp = SYSCFG->EXTICR[position >> 2]; - temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); - temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))); - SYSCFG->EXTICR[position >> 2] = temp; - - /* Clear EXTI line configuration */ - temp = EXTI->IMR1; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - { - temp |= iocurrent; - } - EXTI->IMR1 = temp; - - temp = EXTI->EMR1; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - { - temp |= iocurrent; - } - EXTI->EMR1 = temp; - - /* Clear Rising Falling edge configuration */ - temp = EXTI->RTSR1; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) - { - temp |= iocurrent; - } - EXTI->RTSR1 = temp; - - temp = EXTI->FTSR1; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) - { - temp |= iocurrent; - } - EXTI->FTSR1 = temp; - } - } - - position++; - } -} - -/** - * @brief De-initialize the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Configure the port pins */ - while ((GPIO_Pin >> position) != RESET) - { - /* Get current io position */ - iocurrent = (GPIO_Pin) & (1U << position); - - if (iocurrent) - { - /*------------------------- GPIO Mode Configuration --------------------*/ - /* Configure IO in Analog Mode */ - GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2)); - - /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - - /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2)); - - /* Configure the default value IO Output Type */ - GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; - - /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2)); - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) - - /* Deactivate the Control bit of Analog mode for the current IO */ - GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position); - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - - /*------------------------- EXTI Mode Configuration --------------------*/ - /* Clear the External Interrupt or Event for the current IO */ - - tmp = SYSCFG->EXTICR[position >> 2]; - tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); - if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) - { - tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); - SYSCFG->EXTICR[position >> 2] &= ~tmp; - - /* Clear EXTI line configuration */ - EXTI->IMR1 &= ~((uint32_t)iocurrent); - EXTI->EMR1 &= ~((uint32_t)iocurrent); - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR1 &= ~((uint32_t)iocurrent); - EXTI->FTSR1 &= ~((uint32_t)iocurrent); - } - } - - position++; - } -} - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions - * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Read the specified input port pin. - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_PIN_x where x can be (0..15). - * @retval The input port pin value. - */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - GPIO_PinState bitstatus; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) - { - bitstatus = GPIO_PIN_SET; - } - else - { - bitstatus = GPIO_PIN_RESET; - } - return bitstatus; -} - -/** - * @brief Set or clear the selected data port bit. - * - * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState: specifies the value to be written to the selected bit. - * This parameter can be one of the GPIO_PinState enum values: - * @arg GPIO_PIN_RESET: to clear the port pin - * @arg GPIO_PIN_SET: to set the port pin - * @retval None - */ -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_PIN_ACTION(PinState)); - - if(PinState != GPIO_PIN_RESET) - { - GPIOx->BSRR = (uint32_t)GPIO_Pin; - } - else - { - GPIOx->BRR = (uint32_t)GPIO_Pin; - } -} - -/** - * @brief Toggle the specified GPIO pin. - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the pin to be toggled. - * @retval None - */ -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->ODR ^= GPIO_Pin; -} - -/** -* @brief Lock GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the port bits to be locked. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = GPIO_LCKR_LCKK; - - /* Check the parameters */ - assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Apply lock key write sequence */ - tmp |= GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - - if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) - { - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Handle EXTI interrupt request. - * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. - * @retval None - */ -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) -{ - /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) - { - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); - HAL_GPIO_EXTI_Callback(GPIO_Pin); - } -} - -/** - * @brief EXTI line detection callback. - * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. - * @retval None - */ -__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(GPIO_Pin); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_GPIO_EXTI_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - - -/** - * @} - */ - -#endif /* HAL_GPIO_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c deleted file mode 100644 index 63d38c339..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c +++ /dev/null @@ -1,4868 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_i2c.c - * @author MCD Application Team - * @brief I2C HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Inter Integrated Circuit (I2C) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The I2C HAL driver can be used as follows: - - (#) Declare a I2C_HandleTypeDef handle structure, for example: - I2C_HandleTypeDef hi2c; - - (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: - (##) Enable the I2Cx interface clock - (##) I2C pins configuration - (+++) Enable the clock for the I2C GPIOs - (+++) Configure I2C pins as alternate function open-drain - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the I2Cx interrupt priority - (+++) Enable the NVIC I2C IRQ Channel - (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel - (+++) Enable the DMAx interface clock using - (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx channel - (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on - the DMA Tx or Rx channel - - (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, - Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - - (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. - - (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() - - (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() - - *** Polling mode IO MEM operation *** - ===================================== - [..] - (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() - - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - - *** Interrupt mode IO sequential operation *** - ============================================== - [..] - (@) These interfaces allow to manage a sequential transfer with a repeated start condition - when a direction change during transfer - [..] - (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode - (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition - (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT()) - (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer - if no direction change and without a final stop condition in both cases - (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer - if no direction change and with a final stop condition in both cases - - (+) Differents sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - *** Interrupt mode IO MEM operation *** - ======================================= - [..] - (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - *** DMA mode IO MEM operation *** - ================================= - [..] - (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - - - *** I2C HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in I2C HAL driver. - - (+) __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode - (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt - - [..] - (@) You can refer to the I2C HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup I2C I2C - * @brief I2C HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup I2C_Private_Define I2C Private Define - * @{ - */ -#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ -#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ -#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ - -#define MAX_NBYTE_SIZE 255U -#define SlaveAddr_SHIFT 7U -#define SlaveAddr_MSK 0x06U - -/* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ -#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ - - -/* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (0x00000001U) -#define I2C_XFER_RX_IT (0x00000002U) -#define I2C_XFER_LISTEN_IT (0x00000004U) - -#define I2C_XFER_ERROR_IT (0x00000011U) -#define I2C_XFER_CPLT_IT (0x00000012U) -#define I2C_XFER_RELOAD_IT (0x00000012U) - -/* Private define Sequential Transfer Options default/reset value */ -#define I2C_NO_OPTION_FRAME (0xFFFF0000U) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ - ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmatx->Instance)->CNDTR)) : \ - ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmarx->Instance)->CNDTR))) - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -/* Private functions to handle DMA transfer */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAError(DMA_HandleTypeDef *hdma); -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); - -/* Private functions to handle IT transfer */ -static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); - -/* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); - -/* Private functions for I2C transfer IRQ handler */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); - -/* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); - -/* Private functions to centralize the enable/disable of Interrupts */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); - -/* Private functions to flush TXDR register */ -static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); - -/* Private functions to handle start, restart or stop a transfer */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Functions I2C Exported Functions - * @{ - */ - -/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - deinitialize the I2Cx peripheral: - - (+) User must Implement HAL_I2C_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_I2C_Init() to configure the selected device with - the selected configuration: - (++) Clock Timing - (++) Own Address 1 - (++) Addressing mode (Master, Slave) - (++) Dual Addressing mode - (++) Own Address 2 - (++) Own Address 2 Mask - (++) General call mode - (++) Nostretch mode - - (+) Call the function HAL_I2C_DeInit() to restore the default configuration - of the selected I2Cx peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the I2C according to the specified parameters - * in the I2C_InitTypeDef and initialize the associated handle. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if (hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); - assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); - assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); - assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); - assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); - assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); - assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); - - if (hi2c->State == HAL_I2C_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hi2c->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_I2C_MspInit(hi2c); - } - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ - /* Configure I2Cx: Frequency range */ - hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; - - /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ - /* Disable Own Address1 before set the Own Address1 configuration */ - hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - - /* Configure I2Cx: Own Address1 and ack own address1 mode */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); - } - else /* I2C_ADDRESSINGMODE_10BIT */ - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); - } - - /*---------------------------- I2Cx CR2 Configuration ----------------------*/ - /* Configure I2Cx: Addressing Master mode */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - hi2c->Instance->CR2 = (I2C_CR2_ADD10); - } - /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ - hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); - - /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ - /* Disable Own Address2 before set the Own Address2 configuration */ - hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; - - /* Configure I2Cx: Dual mode and Own Address2 */ - hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); - - /*---------------------------- I2Cx CR1 Configuration ----------------------*/ - /* Configure I2Cx: Generalcall and NoStretch mode */ - hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); - - /* Enable the selected I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - return HAL_OK; -} - -/** - * @brief DeInitialize the I2C peripheral. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if (hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the I2C Peripheral Clock */ - __HAL_I2C_DISABLE(hi2c); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_I2C_MspDeInit(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_RESET; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Release Lock */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Initialize the I2C MSP. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the I2C MSP. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the I2C data - transfers. - - (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_I2C_Master_Transmit() - (++) HAL_I2C_Master_Receive() - (++) HAL_I2C_Slave_Transmit() - (++) HAL_I2C_Slave_Receive() - (++) HAL_I2C_Mem_Write() - (++) HAL_I2C_Mem_Read() - (++) HAL_I2C_IsDeviceReady() - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_I2C_Master_Transmit_IT() - (++) HAL_I2C_Master_Receive_IT() - (++) HAL_I2C_Slave_Transmit_IT() - (++) HAL_I2C_Slave_Receive_IT() - (++) HAL_I2C_Mem_Write_IT() - (++) HAL_I2C_Mem_Read_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_I2C_Master_Transmit_DMA() - (++) HAL_I2C_Master_Receive_DMA() - (++) HAL_I2C_Slave_Transmit_DMA() - (++) HAL_I2C_Slave_Receive_DMA() - (++) HAL_I2C_Mem_Write_DMA() - (++) HAL_I2C_Mem_Read_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2C_MemTxCpltCallback() - (++) HAL_I2C_MemRxCpltCallback() - (++) HAL_I2C_MasterTxCpltCallback() - (++) HAL_I2C_MasterRxCpltCallback() - (++) HAL_I2C_SlaveTxCpltCallback() - (++) HAL_I2C_SlaveRxCpltCallback() - (++) HAL_I2C_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmits in master mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - } - - while (hi2c->XferCount > 0U) - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives in master mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } - - while (hi2c->XferCount > 0U) - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* If 10bit addressing mode is selected */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Wait until DIR flag is set Transmitter mode */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - while (hi2c->XferCount > 0U) - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - } - - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in blocking mode - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Wait until DIR flag is reset Receiver mode */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - while (hi2c->XferCount > 0U) - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Store Last receive data if any */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferCount--; - } - - if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) - { - return HAL_TIMEOUT; - } - else - { - return HAL_ERROR; - } - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferCount--; - } - - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - if (hi2c->XferSize > 0U) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - if (hi2c->XferSize > 0U) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in blocking mode to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - do - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - - } - while (hi2c->XferCount > 0U); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in blocking mode from a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } - - do - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - while (hi2c->XferCount > 0U); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be read - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Checks if target device is ready for communication. - * @note This function is used with Memory devices - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param Trials Number of trials - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - __IO uint32_t I2C_Trials = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - do - { - /* Generate Start */ - hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set or a NACK flag is set*/ - tickstart = HAL_GetTick(); - while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) - { - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - - /* Check if the NACKF flag has not been set */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) - { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - - /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials++ == Trials) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - } - while (I2C_Trials < Trials); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode = 0U; - uint32_t xferrequest = I2C_GENERATE_START_WRITE; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; - - /* If size > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - /* If transfer direction not change, do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) - { - xferrequest = I2C_NO_STARTSTOP; - } - - /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode = 0U; - uint32_t xferrequest = I2C_GENERATE_START_READ; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; - - /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - /* If transfer direction not change, do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) - { - xferrequest = I2C_NO_STARTSTOP; - } - - /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave RX state to TX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; - - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave TX state to RX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; - - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Enable the Address listen mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Enable the Address Match interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Disable the Address listen mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp; - - /* Disable Address listen mode only if a transfer is not ongoing */ - if (hi2c->State == HAL_I2C_STATE_LISTEN) - { - tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; - hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - /* Disable the Address Match interrupt */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) -{ - if (hi2c->Mode == HAL_I2C_MODE_MASTER) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Set State at HAL_I2C_STATE_ABORT */ - hi2c->State = HAL_I2C_STATE_ABORT; - - /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ - /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ - I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - return HAL_OK; - } - else - { - /* Wrong usage of abort function */ - /* This function should be used only in case of abort monitored by master device */ - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ - -/** - * @brief This function handles I2C event interrupt request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - /* Get current IT Flags and IT sources value */ - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - - /* I2C events treatment -------------------------------------*/ - if (hi2c->XferISR != NULL) - { - hi2c->XferISR(hi2c, itflags, itsources); - } -} - -/** - * @brief This function handles I2C error interrupt request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - - /* I2C Bus error interrupt occurred ------------------------------------*/ - if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); - } - - /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); - } - - /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); - } - - /* Call the Error Callback in case of Error detected */ - if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) - { - I2C_ITError(hi2c, hi2c->ErrorCode); - } -} - -/** - * @brief Master Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Master Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterRxCpltCallback could be implemented in the user file - */ -} - -/** @brief Slave Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Slave Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Slave Address Match callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION - * @param AddrMatchCode Address Match Code - * @retval None - */ -__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - UNUSED(TransferDirection); - UNUSED(AddrMatchCode); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AddrCallback() could be implemented in the user file - */ -} - -/** - * @brief Listen Complete callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ListenCpltCallback() could be implemented in the user file - */ -} - -/** - * @brief Memory Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Memory Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief I2C error callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief I2C abort callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AbortCpltCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @brief Peripheral State, Mode and Error functions - * -@verbatim - =============================================================================== - ##### Peripheral State, Mode and Error functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the I2C handle state. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL state - */ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) -{ - /* Return I2C handle state */ - return hi2c->State; -} - -/** - * @brief Returns the I2C Master, Slave, Memory or no mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL mode - */ -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) -{ - return hi2c->Mode; -} - -/** -* @brief Return the I2C error code. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. -* @retval I2C Error Code -*/ -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) -{ - return hi2c->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup I2C_Private_Functions - * @{ - */ - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - uint16_t devaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - /* No need to generate STOP, it is automatically done */ - /* Error callback will be send during stop flag treatment */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferSize--; - hi2c->XferCount--; - } - else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - else - { - /* Call TxCpltCallback() if no stop mode is set */ - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSequentialCplt(hi2c); - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - } - else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - if (hi2c->XferCount == 0U) - { - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Generate a stop condition in case of no transfer option */ - if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } - else - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSequentialCplt(hi2c); - } - } - } - else - { - /* Wrong size Status regarding TC flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - - if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - /* Process locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0*/ - /* So clear Flag NACKF only */ - if (hi2c->XferCount == 0U) - { - if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ - (hi2c->State == HAL_I2C_STATE_LISTEN)) - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); - } - else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - else - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) - { - if (hi2c->XferCount > 0U) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - - if ((hi2c->XferCount == 0U) && \ - (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) - { - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - } - else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) - { - I2C_ITAddrCplt(hi2c, ITFlags); - } - else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) - { - /* Write data to TXDR only if XferCount not reach "0" */ - /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Datas have already been sent */ - /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if (hi2c->XferCount > 0U) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - } - else - { - if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) - { - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - } - } - - /* Check if STOPF is set */ - if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - uint16_t devaddress = 0U; - uint32_t xfermode = 0U; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* No need to generate STOP, it is automatically done */ - /* But enable STOP interrupt, to treat it */ - /* Error callback will be send during stop flag treatment */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - /* Disable TC interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); - - if (hi2c->XferCount != 0U) - { - /* Recover Slave address */ - devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Prepare the new XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Set the new XferSize in Nbytes register */ - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Enable DMA Request */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - /* Process locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0 */ - /* So clear Flag NACKF only */ - if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for write request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -{ - I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for read request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -{ - I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TC flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - return HAL_OK; -} - -/** - * @brief I2C Address complete process callback. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - uint8_t transferdirection = 0U; - uint16_t slaveaddrcode = 0U; - uint16_t ownadd1code = 0U; - uint16_t ownadd2code = 0U; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(ITFlags); - - /* In case of Listen state, need to inform upper layer of address match code event */ - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) - { - transferdirection = I2C_GET_DIR(hi2c); - slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); - ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); - ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); - - /* If 10bits addressing mode is selected */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) - { - slaveaddrcode = ownadd1code; - hi2c->AddrEventCount++; - if (hi2c->AddrEventCount == 2U) - { - /* Reset Address Event counter */ - hi2c->AddrEventCount = 0U; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - else - { - slaveaddrcode = ownadd2code; - - /* Disable ADDR Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - /* else 7 bits addressing mode is selected */ - else - { - /* Disable ADDR Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - /* Else clear address flag only */ - else - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - } -} - -/** - * @brief I2C Master sequential complete process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) -{ - /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* No Generate Stop, to permit restart mode */ - /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; - hi2c->XferISR = NULL; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterTxCpltCallback(hi2c); - } - /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; - hi2c->XferISR = NULL; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterRxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Slave sequential complete process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) -{ - /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - - if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Tx complete callback to inform upper layer of the end of transmit process */ - HAL_I2C_SlaveTxCpltCallback(hi2c); - } - - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Rx complete callback to inform upper layer of the end of receive process */ - HAL_I2C_SlaveRxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Master complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Reset handle parameters */ - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = NULL; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - - if ((ITFlags & I2C_FLAG_AF) != RESET) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set acknowledge error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MemTxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterTxCpltCallback(hi2c); - } - } - /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MemRxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MasterRxCpltCallback(hi2c); - } - } -} - -/** - * @brief I2C Slave complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* If a DMA is ongoing, Update handle size context */ - if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || - ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) - { - hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); - } - - /* All data are not transferred, so set error code accordingly */ - if (hi2c->XferCount != 0U) - { - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Store Last receive data if any */ - if (((ITFlags & I2C_FLAG_RXNE) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - - if ((hi2c->XferSize > 0U)) - { - hi2c->XferSize--; - hi2c->XferCount--; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - if (hi2c->State == HAL_I2C_STATE_LISTEN) - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); - } - } - else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - HAL_I2C_ListenCpltCallback(hi2c); - } - /* Call the corresponding callback to inform upper layer of End of Transfer */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Slave Rx Complete callback */ - HAL_I2C_SlaveRxCpltCallback(hi2c); - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Slave Tx Complete callback */ - HAL_I2C_SlaveTxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Listen complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Reset handle parameters */ - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - /* Store Last receive data if any */ - if (((ITFlags & I2C_FLAG_RXNE) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - - if ((hi2c->XferSize > 0U)) - { - hi2c->XferSize--; - hi2c->XferCount--; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - - /* Disable all Interrupts*/ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - HAL_I2C_ListenCpltCallback(hi2c); -} - -/** - * @brief I2C interrupts error process. - * @param hi2c I2C handle. - * @param ErrorCode Error code to handle. - * @retval None - */ -static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) -{ - /* Reset handle parameters */ - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferCount = 0U; - - /* Set new error code */ - hi2c->ErrorCode |= ErrorCode; - - /* Disable Interrupts */ - if ((hi2c->State == HAL_I2C_STATE_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) - { - /* Disable all interrupts, except interrupts related to LISTEN state */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* keep HAL_I2C_STATE_LISTEN if set */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = I2C_Slave_ISR_IT; - } - else - { - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* If state is an abort treatment on goind, don't change state */ - /* This change will be do later */ - if (hi2c->State != HAL_I2C_STATE_ABORT) - { - /* Set HAL_I2C_STATE_READY */ - hi2c->State = HAL_I2C_STATE_READY; - } - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = NULL; - } - - /* Abort DMA TX transfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); - } - } - /* Abort DMA RX transfer if any */ - else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); - } - } - else if (hi2c->State == HAL_I2C_STATE_ABORT) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_AbortCpltCallback(hi2c); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_ErrorCallback(hi2c); - } -} - -/** - * @brief I2C Tx data register flush process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) -{ - /* If a pending TXIS flag is set */ - /* Write a dummy data in TXDR to clear it */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) - { - hi2c->Instance->TXDR = 0x00U; - } - - /* Flush TX register if not empty */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); - } -} - -/** - * @brief DMA I2C master transmit process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* If last transfer, enable STOP interrupt */ - if (hi2c->XferCount == 0U) - { - /* Enable STOP interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - } - /* else prepare a new DMA transfer and enable TCReload interrupt */ - else - { - /* Update Buffer pointer */ - hi2c->pBuffPtr += hi2c->XferSize; - - /* Set the XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); - } -} - -/** - * @brief DMA I2C slave transmit process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ -} - -/** - * @brief DMA I2C master receive process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* If last transfer, enable STOP interrupt */ - if (hi2c->XferCount == 0U) - { - /* Enable STOP interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - } - /* else prepare a new DMA transfer and enable TCReload interrupt */ - else - { - /* Update Buffer pointer */ - hi2c->pBuffPtr += hi2c->XferSize; - - /* Set the XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); - } -} - -/** - * @brief DMA I2C slave receive process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ -} - -/** - * @brief DMA I2C communication error callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAError(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); -} - -/** - * @brief DMA I2C communication abort callback - * (To be called at end of DMA Abort procedure). - * @param hdma DMA handle. - * @retval None - */ -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Reset AbortCpltCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if (hi2c->State == HAL_I2C_STATE_ABORT) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_AbortCpltCallback(hi2c); - } - else - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_ErrorCallback(hi2c); - } -} - -/** - * @brief This function handles I2C Communication Timeout. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Flag Specifies the I2C flag to check. - * @param Status The new Flag status (SET or RESET). - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) - { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) - { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - /* Check if an RXNE is pending */ - /* Store Last receive data if any */ - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) - { - /* Return HAL_OK */ - /* The Reading of data from RXDR will be done in caller function */ - return HAL_OK; - } - else - { - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - - /* Check for the Timeout */ - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief This function handles Acknowledge failed detection during an I2C Communication. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - /* Wait until STOP Flag is reset */ - /* AutoEnd should be initiate after AF */ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - - /* Clear NACKF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - return HAL_OK; -} - -/** - * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). - * @param hi2c I2C handle. - * @param DevAddress Specifies the slave address to be programmed. - * @param Size Specifies the number of bytes to be programmed. - * This parameter must be a value between 0 and 255. - * @param Mode New state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg @ref I2C_RELOAD_MODE Enable Reload mode . - * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. - * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. - * @param Request New state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. - * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). - * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. - * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. - * @retval None - */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_TRANSFER_MODE(Mode)); - assert_param(IS_TRANSFER_REQUEST(Request)); - - /* update CR2 register */ - MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); -} - -/** - * @brief Manage the enabling of Interrupts. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0U; - - if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) - { - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - } - else - { - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK, and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; - } - - if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; - } - - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - } - - /* Enable interrupts only at the end */ - /* to avoid the risk of I2C interrupt handle execution before */ - /* all interrupts requested done */ - __HAL_I2C_ENABLE_IT(hi2c, tmpisr); - - return HAL_OK; -} - -/** - * @brief Manage the disabling of Interrupts. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0U; - - if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Disable TC and TXI interrupts */ - tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) - { - /* Disable NACK and STOP interrupts */ - tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - } - - if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Disable TC and RXI interrupts */ - tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) - { - /* Disable NACK and STOP interrupts */ - tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - } - - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Disable ADDR, NACK and STOP interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - - /* Disable interrupts only at the end */ - /* to avoid a breaking situation like at "t" time */ - /* all disable interrupts request are not done */ - __HAL_I2C_DISABLE_IT(hi2c, tmpisr); - - return HAL_OK; -} - -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c deleted file mode 100644 index bd4e329dd..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c +++ /dev/null @@ -1,355 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_i2c_ex.c - * @author MCD Application Team - * @brief I2C Extended HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of I2C Extended peripheral: - * + Extended features functions - * - @verbatim - ============================================================================== - ##### I2C peripheral Extended features ##### - ============================================================================== - - [..] Comparing to other previous devices, the I2C interface for STM32L4xx - devices contains the following additional features - - (+) Possibility to disable or enable Analog Noise Filter - (+) Use of a configured Digital Noise Filter - (+) Disable or enable wakeup from Stop mode(s) - (+) Disable or enable Fast Mode Plus - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure Noise Filter and Wake Up Feature - (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() - (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() - (#) Configure the enable or disable of I2C Wake Up Mode using the functions : - (++) HAL_I2CEx_EnableWakeUp() - (++) HAL_I2CEx_DisableWakeUp() - (#) Configure the enable or disable of fast mode plus driving capability using the functions : - (++) HAL_I2CEx_EnableFastModePlus() - (++) HAL_I2CEx_DisableFastModePlus() - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup I2CEx I2CEx - * @brief I2C Extended HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions - * @{ - */ - -/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure Noise Filters - (+) Configure Wake Up Feature - (+) Configure Fast Mode Plus - -@endverbatim - * @{ - */ - -/** - * @brief Configure I2C Analog noise filter. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param AnalogFilter New state of the Analog filter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Reset I2Cx ANOFF bit */ - hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); - - /* Set analog filter bit*/ - hi2c->Instance->CR1 |= AnalogFilter; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configure I2C Digital noise filter. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) -{ - uint32_t tmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Get the old register value */ - tmpreg = hi2c->Instance->CR1; - - /* Reset I2Cx DNF bits [11:8] */ - tmpreg &= ~(I2C_CR1_DNF); - - /* Set I2Cx DNF coefficient */ - tmpreg |= DigitalFilter << 8U; - - /* Store the new register value */ - hi2c->Instance->CR1 = tmpreg; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Enable I2C wakeup from Stop mode(s). - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) -{ - /* Check the parameters */ - assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Enable wakeup from stop mode */ - hi2c->Instance->CR1 |= I2C_CR1_WUPEN; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Disable I2C wakeup from Stop mode(s). - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) -{ - /* Check the parameters */ - assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Enable wakeup from stop mode */ - hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Enable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus Selects the pin. - * This parameter can be one of the @ref I2CEx_FastModePlus values - * @note For I2C1, fast mode plus driving capability can be enabled on all selected - * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently - * on each one of the following pins PB6, PB7, PB8 and PB9. - * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. - * @note For all I2C2 pins fast mode plus driving capability can be enabled - * only by using I2C_FASTMODEPLUS_I2C2 parameter. - * @note For all I2C3 pins fast mode plus driving capability can be enabled - * only by using I2C_FASTMODEPLUS_I2C3 parameter. - * @note For all I2C4 pins fast mode plus driving capability can be enabled - * only by using I2C_FASTMODEPLUS_I2C4 parameter. - * @retval None - */ -void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) -{ - /* Check the parameter */ - assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - - /* Enable SYSCFG clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Enable fast mode plus driving capability for selected pin */ - SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); -} - -/** - * @brief Disable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus Selects the pin. - * This parameter can be one of the @ref I2CEx_FastModePlus values - * @note For I2C1, fast mode plus driving capability can be disabled on all selected - * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently - * on each one of the following pins PB6, PB7, PB8 and PB9. - * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. - * @note For all I2C2 pins fast mode plus driving capability can be disabled - * only by using I2C_FASTMODEPLUS_I2C2 parameter. - * @note For all I2C3 pins fast mode plus driving capability can be disabled - * only by using I2C_FASTMODEPLUS_I2C3 parameter. - * @note For all I2C4 pins fast mode plus driving capability can be disabled - * only by using I2C_FASTMODEPLUS_I2C4 parameter. - * @retval None - */ -void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) -{ - /* Check the parameter */ - assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - - /* Enable SYSCFG clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Disable fast mode plus driving capability for selected pin */ - CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c deleted file mode 100644 index 6aed000b8..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c +++ /dev/null @@ -1,1675 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pcd.c - * @author MCD Application Team - * @brief PCD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The PCD HAL driver can be used as follows: - - (#) Declare a PCD_HandleTypeDef handle structure, for example: - PCD_HandleTypeDef hpcd; - - (#) Fill parameters of Init structure in HCD handle - - (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) - - (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: - (##) Enable the PCD/USB Low Level interface clock using - (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - (##) Initialize the related GPIO clocks - (##) Configure PCD pin-out - (##) Configure PCD NVIC interrupt - - (#)Associate the Upper USB device stack to the HAL PCD Driver: - (##) hpcd.pData = pdev; - - (#)Enable PCD transmission and reception: - (##) HAL_PCD_Start(); - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup PCD PCD - * @brief PCD HAL module driver - * @{ - */ - -#ifdef HAL_PCD_MODULE_ENABLED - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** - * USB_OTG_CORE VERSION ID - */ -#define USB_OTG_CORE_ID_310A 0x4F54310A -#define USB_OTG_CORE_ID_320A 0x4F54320A - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup PCD_Private_Macros PCD Private Macros - * @{ - */ -#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) -#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) -/** - * @} - */ - -/* Private functions prototypes ----------------------------------------------*/ -/** @defgroup PCD_Private_Functions PCD Private Functions - * @{ - */ -#if defined (USB_OTG_FS) -static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); -#endif /* USB_OTG_FS */ -#if defined (USB) -static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); -#endif /* USB */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup PCD_Exported_Functions PCD Exported Functions - * @{ - */ - -/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the PCD according to the specified - * parameters in the PCD_InitTypeDef and initialize the associated handle. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) -{ - uint32_t index = 0U; - - /* Check the PCD handle allocation */ - if(hpcd == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); - - if(hpcd->State == HAL_PCD_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hpcd->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_PCD_MspInit(hpcd); - } - - hpcd->State = HAL_PCD_STATE_BUSY; - - /* Disable the Interrupts */ - __HAL_PCD_DISABLE(hpcd); - - /*Init the Core (common init.) */ - USB_CoreInit(hpcd->Instance, hpcd->Init); - - /* Force Device Mode*/ - USB_SetCurrentMode(hpcd->Instance , USB_DEVICE_MODE); - - /* Init endpoints structures */ - for (index = 0; index < hpcd->Init.dev_endpoints ; index++) - { - /* Init ep structure */ - hpcd->IN_ep[index].is_in = 1; - hpcd->IN_ep[index].num = index; - hpcd->IN_ep[index].tx_fifo_num = index; - /* Control until ep is activated */ - hpcd->IN_ep[index].type = EP_TYPE_CTRL; - hpcd->IN_ep[index].maxpacket = 0; - hpcd->IN_ep[index].xfer_buff = 0; - hpcd->IN_ep[index].xfer_len = 0; - } - - for (index = 0; index < 15 ; index++) - { - hpcd->OUT_ep[index].is_in = 0; - hpcd->OUT_ep[index].num = index; - hpcd->IN_ep[index].tx_fifo_num = index; - /* Control until ep is activated */ - hpcd->OUT_ep[index].type = EP_TYPE_CTRL; - hpcd->OUT_ep[index].maxpacket = 0; - hpcd->OUT_ep[index].xfer_buff = 0; - hpcd->OUT_ep[index].xfer_len = 0; - } - - /* Init Device */ - USB_DevInit(hpcd->Instance, hpcd->Init); - - hpcd->USB_Address = 0; - - hpcd->State= HAL_PCD_STATE_READY; - - /* Activate LPM */ - if (hpcd->Init.lpm_enable ==1) - { - HAL_PCDEx_ActivateLPM(hpcd); - } - /* Activate Battery charging */ - if (hpcd->Init.battery_charging_enable ==1) - { - HAL_PCDEx_ActivateBCD(hpcd); - } - USB_DevDisconnect (hpcd->Instance); - return HAL_OK; -} - -/** - * @brief DeInitializes the PCD peripheral. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) -{ - /* Check the PCD handle allocation */ - if(hpcd == NULL) - { - return HAL_ERROR; - } - - hpcd->State = HAL_PCD_STATE_BUSY; - - /* Stop Device */ - HAL_PCD_Stop(hpcd); - - /* DeInit the low level hardware */ - HAL_PCD_MspDeInit(hpcd); - - hpcd->State = HAL_PCD_STATE_RESET; - - return HAL_OK; -} - -/** - * @brief Initializes the PCD MSP. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes PCD MSP. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the PCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Start The USB OTG Device. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - USB_DevConnect (hpcd->Instance); - __HAL_PCD_ENABLE(hpcd); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Stop The USB OTG Device. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - __HAL_PCD_DISABLE(hpcd); - USB_StopDevice(hpcd->Instance); - USB_DevDisconnect (hpcd->Instance); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} -#if defined (USB_OTG_FS) -/** - * @brief Handles PCD interrupt request. - * @param hpcd: PCD handle - * @retval HAL status - */ -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t index = 0U, ep_intr = 0U, epint = 0U, epnum = 0U; - uint32_t fifoemptymsk = 0U, temp = 0U; - USB_OTG_EPTypeDef *ep = NULL; - uint32_t hclk = 80000000; - - /* ensure that we are in device mode */ - if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) - { - /* avoid spurious interrupt */ - if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) - { - return; - } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) - { - /* incorrect mode, acknowledge the interrupt */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); - } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) - { - epnum = 0; - - /* Read in the device interrupt bits */ - ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); - - while (ep_intr) - { - if (ep_intr & 0x1) - { - epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum); - - if (( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); - - /* setup/out transaction management for Core ID 310A */ - if (USBx->GSNPSID == USB_OTG_CORE_ID_310A) - { - if (!(USBx_OUTEP(0)->DOEPINT & (0x1 << 15))) - { - if (hpcd->Init.dma_enable == 1) - { - hpcd->OUT_ep[epnum].xfer_count = - hpcd->OUT_ep[epnum].maxpacket - - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - - hpcd->OUT_ep[epnum].xfer_buff += - hpcd->OUT_ep[epnum].maxpacket; - } - - HAL_PCD_DataOutStageCallback(hpcd, epnum); - - if (hpcd->Init.dma_enable == 1) - { - if (!epnum && !hpcd->OUT_ep[epnum].xfer_len) - { - /* this is ZLP, so prepare EP0 for next setup */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); - } - } - } - - /* Clear the SetPktRcvd flag*/ - USBx_OUTEP(0)->DOEPINT |= (0x1 << 15) | (0x1 << 5); - } - else - { - if (hpcd->Init.dma_enable == 1) - { - hpcd->OUT_ep[epnum].xfer_count = - hpcd->OUT_ep[epnum].maxpacket - - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; - } - - HAL_PCD_DataOutStageCallback(hpcd, epnum); - - if (hpcd->Init.dma_enable == 1) - { - if (!epnum && !hpcd->OUT_ep[epnum].xfer_len) - { - /* this is ZLP, so prepare EP0 for next setup */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); - } - } - } - } - - if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) - { - /* Inform the upper layer that a setup packet is available */ - HAL_PCD_SetupStageCallback(hpcd); - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); - } - - if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); - } - -#ifdef USB_OTG_DOEPINT_OTEPSPR - /* Clear Status Phase Received interrupt */ - if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); - } -#endif /* USB_OTG_DOEPINT_OTEPSPR */ - } - epnum++; - ep_intr >>= 1; - } - } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) - { - /* Read in the device interrupt bits */ - ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); - - epnum = 0; - - while ( ep_intr ) - { - if (ep_intr & 0x1) /* In ITR */ - { - epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum); - - if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) - { - fifoemptymsk = 0x1 << epnum; - USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); - - if (hpcd->Init.dma_enable == 1) - { - hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; - } - - HAL_PCD_DataInStageCallback(hpcd, epnum); - - if (hpcd->Init.dma_enable == 1) - { - /* this is ZLP, so prepare EP0 for next setup */ - if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0)) - { - /* prepare to rx more setup packets */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); - } - } - } - if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); - } - if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); - } - if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); - } - if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); - } - if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) - { - PCD_WriteEmptyTxFifo(hpcd , epnum); - } - } - epnum++; - ep_intr >>= 1; - } - } - - /* Handle Resume Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) - { - /* Clear the Remote Wake-up Signaling */ - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - - if(hpcd->LPM_State == LPM_L1) - { - hpcd->LPM_State = LPM_L0; - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); - } - else - { - HAL_PCD_ResumeCallback(hpcd); - } - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); - } - - /* Handle Suspend Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) - { - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) - { - - HAL_PCD_SuspendCallback(hpcd); - } - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); - } - - /* Handle LPM Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); - if( hpcd->LPM_State == LPM_L0) - { - hpcd->LPM_State = LPM_L1; - hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ; - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); - } - else - { - HAL_PCD_SuspendCallback(hpcd); - } - } - - /* Handle Reset Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) - { - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - USB_FlushTxFifo(hpcd->Instance , 0x10); - - for (index = 0; index < hpcd->Init.dev_endpoints ; index++) - { - USBx_INEP(index)->DIEPINT = 0xFF; - USBx_OUTEP(index)->DOEPINT = 0xFF; - } - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK |= 0x10001; - - if(hpcd->Init.use_dedicated_ep1) - { - USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); - USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); - } - else - { -#ifdef USB_OTG_DOEPINT_OTEPSPR - USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM); -#else - USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); -#endif /* USB_OTG_DOEPINT_OTEPSPR */ - USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); - } - - /* Set Default Address to 0 */ - USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; - - /* setup EP0 to receive SETUP packets */ - USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); - } - - /* Handle Enumeration done Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) - { - USB_ActivateSetup(hpcd->Instance); - hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; - - hpcd->Init.speed = USB_OTG_SPEED_FULL; - hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; - - /* The USBTRD is configured according to the tables below, depending on AHB frequency - used by application. In the low AHB frequency range it is used to stretch enough the USB response - time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access - latency to the Data FIFO */ - - /* Get hclk frequency value */ - hclk = HAL_RCC_GetHCLKFreq(); - - if((hclk >= 14200000)&&(hclk < 15000000)) - { - /* hclk Clock Range between 14.2-15 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 15000000)&&(hclk < 16000000)) - { - /* hclk Clock Range between 15-16 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 16000000)&&(hclk < 17200000)) - { - /* hclk Clock Range between 16-17.2 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 17200000)&&(hclk < 18500000)) - { - /* hclk Clock Range between 17.2-18.5 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 18500000)&&(hclk < 20000000)) - { - /* hclk Clock Range between 18.5-20 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 20000000)&&(hclk < 21800000)) - { - /* hclk Clock Range between 20-21.8 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 21800000)&&(hclk < 24000000)) - { - /* hclk Clock Range between 21.8-24 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 24000000)&&(hclk < 27700000)) - { - /* hclk Clock Range between 24-27.7 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 27700000)&&(hclk < 32000000)) - { - /* hclk Clock Range between 27.7-32 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else /* if(hclk >= 32000000) */ - { - /* hclk Clock Range between 32-80 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - HAL_PCD_ResetCallback(hpcd); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); - } - - /* Handle RxQLevel Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) - { - USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - temp = USBx->GRXSTSP; - - ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; - - if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) - { - if((temp & USB_OTG_GRXSTSP_BCNT) != 0) - { - USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4); - ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - } - } - else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) - { - USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8); - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - } - USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } - - /* Handle SOF Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) - { - HAL_PCD_SOFCallback(hpcd); - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); - } - - /* Handle Incomplete ISO IN Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) - { - HAL_PCD_ISOINIncompleteCallback(hpcd, epnum); - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); - } - - /* Handle Incomplete ISO OUT Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) - { - HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum); - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); - } - - /* Handle Connection event Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) - { - HAL_PCD_ConnectCallback(hpcd); - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); - } - - /* Handle Disconnection event Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) - { - temp = hpcd->Instance->GOTGINT; - - if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) - { - HAL_PCD_DisconnectCallback(hpcd); - } - hpcd->Instance->GOTGINT |= temp; - } - } -} - -#endif /* USB_OTG_FS */ - -#if defined (USB) -/** - * @brief This function handles PCD interrupt request. - * @param hpcd: PCD handle - * @retval HAL status - */ -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) -{ - uint32_t wInterrupt_Mask = 0; - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) - { - /* servicing of the endpoint correct transfer interrupt */ - /* clear of the CTR flag into the sub */ - PCD_EP_ISR_Handler(hpcd); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); - HAL_PCD_ResetCallback(hpcd); - HAL_PCD_SetAddress(hpcd, 0); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) - { - - hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE); - - /*set wInterrupt_Mask global variable*/ - wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM; - - /*Set interrupt mask*/ - hpcd->Instance->CNTR = wInterrupt_Mask; - - /* enable L1REQ interrupt */ - if (hpcd->Init.lpm_enable ==1) - { - wInterrupt_Mask |= USB_CNTR_L1REQM; - - /* Enable LPM support and enable ACK answer to LPM request*/ - USB_TypeDef *USBx = hpcd->Instance; - hpcd->lpm_active = ENABLE; - hpcd->LPM_State = LPM_L0; - - USBx->LPMCSR |= (USB_LPMCSR_LMPEN); - USBx->LPMCSR |= (USB_LPMCSR_LPMACK); - } - - if(hpcd->LPM_State == LPM_L1) - { - hpcd->LPM_State = LPM_L0; - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); - } - - HAL_PCD_ResumeCallback(hpcd); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) - { - /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - - /* Force low-power mode in the macrocell */ - hpcd->Instance->CNTR |= USB_CNTR_FSUSP; - hpcd->Instance->CNTR |= USB_CNTR_LPMODE; - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) - { - HAL_PCD_SuspendCallback(hpcd); - } - } - - /* Handle LPM Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ); - if( hpcd->LPM_State == LPM_L0) - { - /* Force suspend and low-power mode before going to L1 state*/ - hpcd->Instance->CNTR |= USB_CNTR_LPMODE; - hpcd->Instance->CNTR |= USB_CNTR_FSUSP; - - hpcd->LPM_State = LPM_L1; - hpcd->BESL = (hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >>2 ; - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); - } - else - { - HAL_PCD_SuspendCallback(hpcd); - } - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); - HAL_PCD_SOFCallback(hpcd); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF)) - { - /* clear ESOF flag in ISTR */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); - } -} -#endif /* USB */ - -/** - * @brief Data OUT stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ -__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_DataOutStageCallback could be implemented in the user file - */ -} - -/** - * @brief Data IN stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ -__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_DataInStageCallback could be implemented in the user file - */ -} -/** - * @brief Setup stage callback. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_SetupStageCallback could be implemented in the user file - */ -} - -/** - * @brief USB Start Of Frame callback. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_SOFCallback could be implemented in the user file - */ -} - -/** - * @brief USB Reset callback. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ResetCallback could be implemented in the user file - */ -} - -/** - * @brief Suspend event callback. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_SuspendCallback could be implemented in the user file - */ -} - -/** - * @brief Resume event callback. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ResumeCallback could be implemented in the user file - */ -} - -/** - * @brief Incomplete ISO OUT callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ -__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file - */ -} - -/** - * @brief Incomplete ISO IN callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ -__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file - */ -} - -/** - * @brief Connection event callback. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ConnectCallback could be implemented in the user file - */ -} - -/** - * @brief Disconnection event callback. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_DisconnectCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the PCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Connect the USB device. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - USB_DevConnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Disconnect the USB device. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - USB_DevDisconnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Set the USB Device address. - * @param hpcd: PCD handle - * @param address: new device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) -{ - __HAL_LOCK(hpcd); - hpcd->USB_Address = address; - USB_SetDevAddress(hpcd->Instance, address); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} -/** - * @brief Open and configure an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param ep_mps: endpoint max packet size - * @param ep_type: endpoint type - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) -{ - HAL_StatusTypeDef ret = HAL_OK; - PCD_EPTypeDef *ep = NULL; - - if ((ep_addr & 0x80) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; - ep->maxpacket = ep_mps; - ep->type = ep_type; - - __HAL_LOCK(hpcd); - USB_ActivateEndpoint(hpcd->Instance , ep); - __HAL_UNLOCK(hpcd); - return ret; - -} - - -/** - * @brief Deactivate an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep = NULL; - - if ((ep_addr & 0x80) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; - - __HAL_LOCK(hpcd); - USB_DeactivateEndpoint(hpcd->Instance , ep); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - - -/** - * @brief Receive an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the reception buffer - * @param len: amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) -{ - PCD_EPTypeDef *ep = NULL; - - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - - /*setup and start the Xfer */ - ep->xfer_buff = pBuf; - ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; - - if ((ep_addr & 0x7F) == 0 ) - { - USB_EP0StartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); - } - else - { - USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); - } - - return HAL_OK; -} - -/** - * @brief Get Received Data Size. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval Data Size - */ -uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count; -} -/** - * @brief Send an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the transmission buffer - * @param len: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) -{ - PCD_EPTypeDef *ep = NULL; - - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - - /*setup and start the Xfer */ - ep->xfer_buff = pBuf; - ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 1; - ep->num = ep_addr & 0x7F; - - if ((ep_addr & 0x7F) == 0 ) - { - USB_EP0StartXfer(hpcd->Instance,ep, hpcd->Init.dma_enable); - } - else - { - USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); - } - - return HAL_OK; -} - -/** - * @brief Set a STALL condition over an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep = NULL; - - if ((0x80 & ep_addr) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - ep->is_stall = 1; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - - __HAL_LOCK(hpcd); - USB_EPSetStall(hpcd->Instance , ep); - if((ep_addr & 0x7F) == 0) - { - USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); - } - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Clear a STALL condition over in an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep = NULL; - - if ((0x80 & ep_addr) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - ep->is_stall = 0; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - - __HAL_LOCK(hpcd); - USB_EPClearStall(hpcd->Instance , ep); - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Flush an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - __HAL_LOCK(hpcd); - - if ((ep_addr & 0x80) == 0x80) - { - USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F); - } - else - { - USB_FlushRxFifo(hpcd->Instance); - } - - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Activate remote wakeup signalling. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - return(USB_ActivateRemoteWakeup(hpcd->Instance)); -} - -/** - * @brief De-activate remote wakeup signalling. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - return(USB_DeActivateRemoteWakeup(hpcd->Instance)); -} -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the PCD handle state. - * @param hpcd: PCD handle - * @retval HAL state - */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) -{ - return hpcd->State; -} -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup PCD_Private_Functions - * @{ - */ -#if defined (USB_OTG_FS) -/** - * @brief Check FIFO for the next packet to be loaded. - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - USB_OTG_EPTypeDef *ep = NULL; - int32_t len = 0U; - uint32_t len32b = 0; - uint32_t fifoemptymsk = 0; - - ep = &hpcd->IN_ep[epnum]; - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - - - len32b = (len + 3) / 4; - - while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b && - ep->xfer_count < ep->xfer_len && - ep->xfer_len != 0) - { - /* Write the FIFO */ - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - len32b = (len + 3) / 4; - - USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); - - ep->xfer_buff += len; - ep->xfer_count += len; - } - - if(len <= 0) - { - fifoemptymsk = 0x1 << epnum; - USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - - } - - return HAL_OK; -} -#endif /* USB_OTG_FS */ - -#if defined (USB) -/** - * @brief This function handles PCD Endpoint interrupt request. - * @param hpcd: PCD handle - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) -{ - PCD_EPTypeDef *ep = NULL; - uint16_t count = 0; - uint8_t epindex = 0; - __IO uint16_t wIstr = 0; - __IO uint16_t wEPVal = 0; - - /* stay in loop while pending interrupts */ - while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) - { - /* extract highest priority endpoint number */ - epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); - - if (epindex == 0) - { - /* Decode and service control endpoint interrupt */ - - /* DIR bit = origin of the interrupt */ - if ((wIstr & USB_ISTR_DIR) == 0) - { - /* DIR = 0 */ - - /* DIR = 0 => IN int */ - /* DIR = 0 implies that (EP_CTR_TX = 1) always */ - PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); - ep = &hpcd->IN_ep[0]; - - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff += ep->xfer_count; - - /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, 0); - - - if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) - { - hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); - hpcd->USB_Address = 0; - } - - } - else - { - /* DIR = 1 */ - - /* DIR = 1 & CTR_RX => SETUP or OUT int */ - /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ - ep = &hpcd->OUT_ep[0]; - wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if ((wEPVal & USB_EP_SETUP) != 0) - { - /* Get SETUP Packet*/ - ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - USB_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); - /* SETUP bit kept frozen while CTR_RX = 1*/ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - - /* Process SETUP Packet*/ - HAL_PCD_SetupStageCallback(hpcd); - } - - else if ((wEPVal & USB_EP_CTR_RX) != 0) - { - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - /* Get Control Data OUT Packet*/ - ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - - if (ep->xfer_count != 0) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - ep->xfer_buff+=ep->xfer_count; - } - - /* Process Control Data OUT Packet*/ - HAL_PCD_DataOutStageCallback(hpcd, 0); - - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); - } - } - } - else - { - /* Decode and service non control endpoints interrupt */ - - /* process related endpoint register */ - wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); - if ((wEPVal & USB_EP_CTR_RX) != 0) - { - /* clear int flag */ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); - ep = &hpcd->OUT_ep[epindex]; - - /* OUT double Buffering*/ - if (ep->doublebuffer == 0) - { - count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); - } - } - else - { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) - { - /*read from endpoint BUF0Addr buffer*/ - count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); - } - } - else - { - /*read from endpoint BUF1Addr buffer*/ - count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); - } - } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); - } - /*multi-packet on the NON control OUT endpoint*/ - ep->xfer_count+=count; - ep->xfer_buff+=count; - - if ((ep->xfer_len == 0) || (count < ep->maxpacket)) - { - /* RX COMPLETE */ - HAL_PCD_DataOutStageCallback(hpcd, ep->num); - } - else - { - HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); - } - - } /* if((wEPVal & EP_CTR_RX) */ - - if ((wEPVal & USB_EP_CTR_TX) != 0) - { - ep = &hpcd->IN_ep[epindex]; - - /* clear int flag */ - PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - - /* IN double Buffering*/ - if (ep->doublebuffer == 0) - { - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - } - } - else - { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX) - { - /*read from endpoint BUF0Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); - } - } - else - { - /*read from endpoint BUF1Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); - } - } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); - } - /*multi-packet on the NON control IN endpoint*/ - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff+=ep->xfer_count; - - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, ep->num); - } - else - { - HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); - } - } - } - } - return HAL_OK; -} -#endif /* USB */ - -/** - * @} - */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* HAL_PCD_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c deleted file mode 100644 index 8a3cc9a34..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c +++ /dev/null @@ -1,523 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pcd_ex.c - * @author MCD Application Team - * @brief PCD Extended HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Extended features functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup PCDEx PCDEx - * @brief PCD Extended HAL module driver - * @{ - */ - -#ifdef HAL_PCD_MODULE_ENABLED - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions - * @{ - */ - -/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @brief PCDEx control functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Update FIFO configuration - -@endverbatim - * @{ - */ -#if defined (USB_OTG_FS) -/** - * @brief Set Tx FIFO - * @param hpcd: PCD handle - * @param fifo: The number of Tx fifo - * @param size: Fifo size - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) -{ - uint8_t index = 0; - uint32_t Tx_Offset = 0; - - /* TXn min size = 16 words. (n : Transmit FIFO index) - When a TxFIFO is not used, the Configuration should be as follows: - case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) - --> Txm can use the space allocated for Txn. - case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) - --> Txn should be configured with the minimum space of 16 words - The FIFO is used optimally when used TxFIFOs are allocated in the top - of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. - When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ - - Tx_Offset = hpcd->Instance->GRXFSIZ; - - if(fifo == 0) - { - hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset; - } - else - { - Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; - for (index = 0; index < (fifo - 1); index++) - { - Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16); - } - - /* Multiply Tx_Size by 2 to get higher performance */ - hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset; - } - - return HAL_OK; -} - -/** - * @brief Set Rx FIFO - * @param hpcd: PCD handle - * @param size: Size of Rx fifo - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) -{ - hpcd->Instance->GRXFSIZ = size; - - return HAL_OK; -} - -/** - * @brief Activate LPM feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = ENABLE; - hpcd->LPM_State = LPM_L0; - USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; - USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; -} - -/** - * @brief Deactivate LPM feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = DISABLE; - USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; - USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; -} - -/** - * @brief Handle BatteryCharging Process. - * @param hpcd: PCD handle - * @retval HAL status - */ -void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t tickstart = HAL_GetTick(); - - /* Start BCD When device is connected */ - if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS) - { - /* Enable DCD : Data Contact Detect */ - USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; - - /* Wait Detect flag or a timeout is happen*/ - while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > 1000) - { - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); - return; - } - } - - /* Right response got */ - HAL_Delay(100); - - /* Check Detect flag*/ - if (USBx->GCCFG & USB_OTG_GCCFG_DCDET) - { - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); - } - - /*Primary detection: checks if connected to Standard Downstream Port - (without charging capability) */ - USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN; - USBx->GCCFG |= USB_OTG_GCCFG_PDEN; - HAL_Delay(100); - - if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET)) - { - /* Case of Standard Downstream Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); - } - else - { - /* start secondary detection to check connection to Charging Downstream - Port or Dedicated Charging Port */ - USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN; - USBx->GCCFG |= USB_OTG_GCCFG_SDEN; - HAL_Delay(100); - - if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET) - { - /* case Dedicated Charging Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); - } - else - { - /* case Charging Downstream Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); - } - } - /* Battery Charging capability discovery finished */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); - } -} - -/** - * @brief Activate BatteryCharging feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->battery_charging_active = ENABLE; - USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN); - - return HAL_OK; -} - -/** - * @brief Deactivate BatteryCharging feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = DISABLE; - USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); - return HAL_OK; -} -#endif /* USB_OTG_FS */ - -#if defined (USB) -/** - * @brief Configure PMA for EP - * @param hpcd : Device instance - * @param ep_addr: endpoint address - * @param ep_kind: endpoint Kind - * USB_SNG_BUF: Single Buffer used - * USB_DBL_BUF: Double Buffer used - * @param pmaadress: EP address in The PMA: In case of single buffer endpoint - * this parameter is 16-bit value providing the address - * in PMA allocated to endpoint. - * In case of double buffer endpoint this parameter - * is a 32-bit value providing the endpoint buffer 0 address - * in the LSB part of 32-bit value and endpoint buffer 1 address - * in the MSB part of 32-bit value. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, - uint16_t ep_addr, - uint16_t ep_kind, - uint32_t pmaadress) - -{ - PCD_EPTypeDef *ep = NULL; - - /* initialize ep structure*/ - if ((0x80 & ep_addr) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - /* Here we check if the endpoint is single or double Buffer*/ - if (ep_kind == PCD_SNG_BUF) - { - /*Single Buffer*/ - ep->doublebuffer = 0; - /*Configure te PMA*/ - ep->pmaadress = (uint16_t)pmaadress; - } - else /*USB_DBL_BUF*/ - { - /*Double Buffer Endpoint*/ - ep->doublebuffer = 1; - /*Configure the PMA*/ - ep->pmaaddr0 = pmaadress & 0xFFFF; - ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16; - } - - return HAL_OK; -} - -/** - * @brief Activate BatteryCharging feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_TypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = ENABLE; - - USBx->BCDR |= (USB_BCDR_BCDEN); - /* Enable DCD : Data Contact Detect */ - USBx->BCDR |= (USB_BCDR_DCDEN); - - return HAL_OK; -} - -/** - * @brief Deactivate BatteryCharging feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_TypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = DISABLE; - - USBx->BCDR &= ~(USB_BCDR_BCDEN); - return HAL_OK; -} - -/** - * @brief Handle BatteryCharging Process. - * @param hpcd: PCD handle - * @retval HAL status - */ -void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) -{ - USB_TypeDef *USBx = hpcd->Instance; - uint32_t tickstart = HAL_GetTick(); - - /* Wait Detect flag or a timeout is happen*/ - while ((USBx->BCDR & USB_BCDR_DCDET) == 0) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > 1000) - { - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); - return; - } - } - - HAL_Delay(300); - - /* Data Pin Contact ? Check Detect flag */ - if (USBx->BCDR & USB_BCDR_DCDET) - { - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); - } - /* Primary detection: checks if connected to Standard Downstream Port - (without charging capability) */ - USBx->BCDR &= ~(USB_BCDR_DCDEN); - USBx->BCDR |= (USB_BCDR_PDEN); - HAL_Delay(300); - - /* If Charger detect ? */ - if (USBx->BCDR & USB_BCDR_PDET) - { - /* Start secondary detection to check connection to Charging Downstream - Port or Dedicated Charging Port */ - USBx->BCDR &= ~(USB_BCDR_PDEN); - USBx->BCDR |= (USB_BCDR_SDEN); - HAL_Delay(300); - - /* If CDP ? */ - if (USBx->BCDR & USB_BCDR_SDET) - { - /* Dedicated Downstream Port DCP */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); - } - else - { - /* Charging Downstream Port CDP */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); - - /* Battery Charging capability discovery finished - Start Enumeration*/ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); - } - } - else /* NO */ - { - /* Standard Downstream Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); - } -} - -/** - * @brief Activate LPM feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) -{ - - USB_TypeDef *USBx = hpcd->Instance; - hpcd->lpm_active = ENABLE; - hpcd->LPM_State = LPM_L0; - - USBx->LPMCSR |= (USB_LPMCSR_LMPEN); - USBx->LPMCSR |= (USB_LPMCSR_LPMACK); - - - return HAL_OK; -} - -/** - * @brief Deactivate LPM feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) -{ - USB_TypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = DISABLE; - - USBx->LPMCSR &= ~ (USB_LPMCSR_LMPEN); - USBx->LPMCSR &= ~ (USB_LPMCSR_LPMACK); - - return HAL_OK; -} - -#endif /* USB */ - -/** - * @brief Send LPM message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message - * @retval HAL status - */ -__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(msg); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCDEx_LPM_Callback could be implemented in the user file - */ -} - -/** - * @brief Send BatteryCharging message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message - * @retval HAL status - */ -__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(msg); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCDEx_BCD_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* HAL_PCD_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c deleted file mode 100644 index 3f5877b4d..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c +++ /dev/null @@ -1,674 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pwr.c - * @author MCD Application Team - * @brief PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Initialization/de-initialization functions - * + Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup PWR PWR - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup PWR_Private_Defines PWR Private Defines - * @{ - */ - -/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask - * @{ - */ -#define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */ -#define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */ -#define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */ -#define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */ -/** - * @} - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the HAL PWR peripheral registers to their default reset values. - * @retval None - */ -void HAL_PWR_DeInit(void) -{ - __HAL_RCC_PWR_FORCE_RESET(); - __HAL_RCC_PWR_RELEASE_RESET(); -} - -/** - * @brief Enable access to the backup domain - * (RTC registers, RTC backup data registers). - * @note After reset, the backup domain is protected against - * possible unwanted write accesses. - * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain. - * In order to set or modify the RTC clock, the backup domain access must be - * disabled. - * @note LSEON bit that switches on and off the LSE crystal belongs as well to the - * back-up domain. - * @retval None - */ -void HAL_PWR_EnableBkUpAccess(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_DBP); -} - -/** - * @brief Disable access to the backup domain - * (RTC registers, RTC backup data registers). - * @retval None - */ -void HAL_PWR_DisableBkUpAccess(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); -} - - - - -/** - * @} - */ - - - -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @brief Low Power modes configuration functions - * -@verbatim - - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - - [..] - *** PVD configuration *** - ========================= - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a - threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register). - - (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower - than the PVD threshold. This event is internally connected to the EXTI - line16 and can generate an interrupt if enabled. This is done through - __HAL_PVD_EXTI_ENABLE_IT() macro. - (+) The PVD is stopped in Standby mode. - - - *** WakeUp pin configuration *** - ================================ - [..] - (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. - The polarity of these pins can be set to configure event detection on high - level (rising edge) or low level (falling edge). - - - - *** Low Power modes configuration *** - ===================================== - [..] - The devices feature 8 low-power modes: - (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on. - (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on. - (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on. - (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on. - (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on. - (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode. - (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on. - (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off. - (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off. - - - *** Low-power run mode *** - ========================== - [..] - (+) Entry: (from main run mode) - (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. - - (+) Exit: - (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only - then can the system clock frequency be increased above 2 MHz. - - - *** Sleep mode / Low-power sleep mode *** - ========================================= - [..] - (+) Entry: - The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API - in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. - (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). - (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode). - In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand. - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - - (+) WFI Exit: - (++) Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) or any wake-up event. - - (+) WFE Exit: - (++) Any wake-up event such as an EXTI line configured in event mode. - - [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, - the MCU is in Low-power Run mode. - - *** Stop 0, Stop 1 and Stop 2 modes *** - =============================== - [..] - (+) Entry: - The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's: - (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode(). - (++) HAL_PWREx_EnterSTOP2Mode() for mode 2. - (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only): - (++) PWR_MAINREGULATOR_ON - (++) PWR_LOWPOWERREGULATOR_ON - (+) Exit (interrupt or event-triggered, specified when entering STOP mode): - (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction - (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction - - (+) WFI Exit: - (++) Any EXTI Line (Internal or External) configured in Interrupt mode. - (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts - when programmed in wakeup mode. - (+) WFE Exit: - (++) Any EXTI Line (Internal or External) configured in Event mode. - - [..] - When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode - depending on the LPR bit setting. - When exiting Stop 2 mode, the MCU is in Run mode. - - *** Standby mode *** - ==================== - [..] - The Standby mode offers two options: - (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode). - SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers - and Standby circuitry. - (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled). - SRAM and register contents are lost except for the RTC registers, RTC backup registers - and Standby circuitry. - - (++) Entry: - (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. - SRAM1 and register contents are lost except for registers in the Backup domain and - Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. - To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API - to set RRS bit. - - (++) Exit: - (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, - external reset in NRST pin, IWDG reset. - - [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset. - - - *** Shutdown mode *** - ====================== - [..] - In Shutdown mode, - voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared. - SRAM and registers contents are lost except for backup domain registers. - - (+) Entry: - The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API. - - (+) Exit: - (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, - external reset in NRST pin. - - [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset. - - - *** Auto-wakeup (AWU) from low-power mode *** - ============================================= - [..] - The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event or a time-stamp event, without depending on - an external interrupt (Auto-wakeup mode). - - (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes - - - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to - configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. - - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to configure the RTC to detect the tamper or time stamp event using the - HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. - - (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to - configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function. - -@endverbatim - * @{ - */ - - - -/** - * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD). - * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD - * configuration information. - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage thresholds corresponding to each - * detection level. - * @retval None - */ -HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) -{ - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); - assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); - - /* Set PLS bits according to PVDLevel value */ - MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel); - - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) - { - __HAL_PWR_PVD_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) - { - __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - } - - return HAL_OK; -} - - -/** - * @brief Enable the Power Voltage Detector (PVD). - * @retval None - */ -void HAL_PWR_EnablePVD(void) -{ - SET_BIT(PWR->CR2, PWR_CR2_PVDE); -} - -/** - * @brief Disable the Power Voltage Detector (PVD). - * @retval None - */ -void HAL_PWR_DisablePVD(void) -{ - CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); -} - - - - -/** - * @brief Enable the WakeUp PINx functionality. - * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable. - * This parameter can be one of the following legacy values which set the default polarity - * i.e. detection on high level (rising edge): - * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 - * - * or one of the following value where the user can explicitly specify the enabled pin and - * the chosen polarity: - * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW - * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW - * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW - * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW - * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW - * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. - * @retval None - */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) -{ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); - - /* Specifies the Wake-Up pin polarity for the event detection - (rising or falling edge) */ - MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); - - /* Enable wake-up pin */ - SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); - - -} - -/** - * @brief Disable the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. - * This parameter can be one of the following values: - * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 - * @retval None - */ -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) -{ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - - CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); -} - - -/** - * @brief Enter Sleep or Low-power Sleep mode. - * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode. - * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode. - * This parameter can be one of the following values: - * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode) - * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) - * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet - * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set - * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the - * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register. - * Additionally, the clock frequency must be reduced below 2 MHz. - * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must - * be done before calling HAL_PWR_EnterSLEEPMode() API. - * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in - * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API. - * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction - * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction - * @note When WFI entry is used, tick interrupt have to be disabled if not desired as - * the interrupt wake up source. - * @retval None - */ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); - - /* Set Regulator parameter */ - if (Regulator == PWR_MAINREGULATOR_ON) - { - /* If in low-power run mode at this point, exit it */ - if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) - { - HAL_PWREx_DisableLowPowerRunMode(); - } - /* Regulator now in main mode. */ - } - else - { - /* If in run mode, first move to low-power run mode. - The system clock frequency must be below 2 MHz at this point. */ - if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET) - { - HAL_PWREx_EnableLowPowerRunMode(); - } - } - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select SLEEP mode entry -------------------------------------------------*/ - if(SLEEPEntry == PWR_SLEEPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - -} - - -/** - * @brief Enter Stop mode - * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running - * on devices where only "Stop mode" is mentioned with main or low power regulator ON. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated - * only to the peripheral requesting it. - * SRAM1, SRAM2 and register contents are preserved. - * The BOR is available. - * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1). - * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. - * @note When the voltage regulator operates in low power mode (Stop 1), an additional - * startup delay is incurred when waking up. - * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption - * is higher although the startup time is reduced. - * @param Regulator: Specifies the regulator state in Stop mode. - * This parameter can be one of the following values: - * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON) - * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON) - * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction. - * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction. - * @retval None - */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - - if(Regulator == PWR_LOWPOWERREGULATOR_ON) - { - HAL_PWREx_EnterSTOP1Mode(STOPEntry); - } - else - { - HAL_PWREx_EnterSTOP0Mode(STOPEntry); - } -} - -/** - * @brief Enter Standby mode. - * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched - * off. The voltage regulator is disabled, except when SRAM2 content is preserved - * in which case the regulator is in low-power mode. - * SRAM1 and register contents are lost except for registers in the Backup domain and - * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. - * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API - * to set RRS bit. - * The BOR is available. - * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. - * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and - * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the - * same. - * These states are effective in Standby mode only if APC bit is set through - * HAL_PWREx_EnablePullUpPullDownConfig() API. - * @retval None - */ -void HAL_PWR_EnterSTANDBYMode(void) -{ - /* Set Stand-by mode */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - - - -/** - * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. - * @retval None - */ -void HAL_PWR_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - - -/** - * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * @retval None - */ -void HAL_PWR_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - - - -/** - * @brief Enable CORTEX M4 SEVONPEND bit. - * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_EnableSEVOnPend(void) -{ - /* Set SEVONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - - -/** - * @brief Disable CORTEX M4 SEVONPEND bit. - * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_DisableSEVOnPend(void) -{ - /* Clear SEVONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - - - - - -/** - * @brief PWR PVD interrupt callback - * @retval None - */ -__weak void HAL_PWR_PVDCallback(void) -{ - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_PWR_PVDCallback can be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c deleted file mode 100644 index 1c08c0fef..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c +++ /dev/null @@ -1,1399 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pwr_ex.c - * @author MCD Application Team - * @brief Extended PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Extended Initialization and de-initialization functions - * + Extended Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup PWREx PWREx - * @brief PWR Extended HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) -#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */ -#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */ -#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) -#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x00000003) /* PH0/PH1 */ -#elif defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000FFFF) /* PH0..PH15 */ -#endif - -#if defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define PWR_PORTI_AVAILABLE_PINS ((uint32_t)0x00000FFF) /* PI0..PI11 */ -#endif - -/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines - * @{ - */ - -/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask - * @{ - */ -#define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */ -#define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */ -#define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */ -#define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */ -/** - * @} - */ - -/** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value - * @{ - */ -#define PWR_FLAG_SETTING_DELAY_US 50 /*!< Time out value for REGLPF and VOSF flags setting */ -/** - * @} - */ - - - -/** - * @} - */ - - - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions - * @{ - */ - -/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Initialization and de-initialization functions ##### - =============================================================================== - [..] - -@endverbatim - * @{ - */ - - -/** - * @brief Return Voltage Scaling Range. - * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2 - * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable) - */ -uint32_t HAL_PWREx_GetVoltageRange(void) -{ -#if defined(PWR_CR5_R1MODE) - if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) - { - return PWR_REGULATOR_VOLTAGE_SCALE2; - } - else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE) - { - /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */ - return PWR_REGULATOR_VOLTAGE_SCALE1; - } - else - { - return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST; - } -#else - return (PWR->CR1 & PWR_CR1_VOS); -#endif -} - - - -/** - * @brief Configure the main internal regulator output voltage. - * @param VoltageScaling: specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption. - * This parameter can be one of the following values: - @if STM32L4S9xx - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode, - * typical output voltage at 1.2 V, - * system frequency up to 120 MHz. - @endif - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, - * typical output voltage at 1.2 V, - * system frequency up to 80 MHz. - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, - * typical output voltage at 1.0 V, - * system frequency up to 26 MHz. - * @note When moving from Range 1 to Range 2, the system frequency must be decreased to - * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. - * When moving from Range 2 to Range 1, the system frequency can be increased to - * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. For - * some devices, the system frequency can be increased up to 120 MHz. - * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be - * cleared before returning the status. If the flag is not cleared within - * 50 microseconds, HAL_TIMEOUT status is reported. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) -{ - uint32_t wait_loop_index = 0; - - assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); - -#if defined(PWR_CR5_R1MODE) - if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) - { - /* If current range is range 2 */ - if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) - { - /* Make sure Range 1 Boost is enabled */ - CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); - - /* Set Range 1 */ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Wait until VOSF is cleared */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) - { - wait_loop_index--; - } - if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) - { - return HAL_TIMEOUT; - } - } - /* If current range is range 1 normal or boost mode */ - else - { - /* Enable Range 1 Boost (no issue if bit already reset) */ - CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); - } - } - else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) - { - /* If current range is range 2 */ - if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) - { - /* Make sure Range 1 Boost is disabled */ - SET_BIT(PWR->CR5, PWR_CR5_R1MODE); - - /* Set Range 1 */ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Wait until VOSF is cleared */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) - { - wait_loop_index--; - } - if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) - { - return HAL_TIMEOUT; - } - } - /* If current range is range 1 normal or boost mode */ - else - { - /* Disable Range 1 Boost (no issue if bit already set) */ - SET_BIT(PWR->CR5, PWR_CR5_R1MODE); - } - } - else - { - /* Set Range 2 */ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); - /* No need to wait for VOSF to be cleared for this transition */ - /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ - } - -#else - - /* If Set Range 1 */ - if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) - { - if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1) - { - /* Set Range 1 */ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Wait until VOSF is cleared */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) - { - wait_loop_index--; - } - if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) - { - return HAL_TIMEOUT; - } - } - } - else - { - if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2) - { - /* Set Range 2 */ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); - /* No need to wait for VOSF to be cleared for this transition */ - } - } -#endif - - return HAL_OK; -} - - -/** - * @brief Enable battery charging. - * When VDD is present, charge the external battery on VBAT thru an internal resistor. - * @param ResistorSelection: specifies the resistor impedance. - * This parameter can be one of the following values: - * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor - * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor - * @retval None - */ -void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) -{ - assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); - - /* Specify resistor selection */ - MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); - - /* Enable battery charging */ - SET_BIT(PWR->CR4, PWR_CR4_VBE); -} - - -/** - * @brief Disable battery charging. - * @retval None - */ -void HAL_PWREx_DisableBatteryCharging(void) -{ - CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); -} - - -#if defined(PWR_CR2_USV) -/** - * @brief Enable VDDUSB supply. - * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. - * @retval None - */ -void HAL_PWREx_EnableVddUSB(void) -{ - SET_BIT(PWR->CR2, PWR_CR2_USV); -} - - -/** - * @brief Disable VDDUSB supply. - * @retval None - */ -void HAL_PWREx_DisableVddUSB(void) -{ - CLEAR_BIT(PWR->CR2, PWR_CR2_USV); -} -#endif /* PWR_CR2_USV */ - -#if defined(PWR_CR2_IOSV) -/** - * @brief Enable VDDIO2 supply. - * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. - * @retval None - */ -void HAL_PWREx_EnableVddIO2(void) -{ - SET_BIT(PWR->CR2, PWR_CR2_IOSV); -} - - -/** - * @brief Disable VDDIO2 supply. - * @retval None - */ -void HAL_PWREx_DisableVddIO2(void) -{ - CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); -} -#endif /* PWR_CR2_IOSV */ - - -/** - * @brief Enable Internal Wake-up Line. - * @retval None - */ -void HAL_PWREx_EnableInternalWakeUpLine(void) -{ - SET_BIT(PWR->CR3, PWR_CR3_EIWF); -} - - -/** - * @brief Disable Internal Wake-up Line. - * @retval None - */ -void HAL_PWREx_DisableInternalWakeUpLine(void) -{ - CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); -} - - - -/** - * @brief Enable GPIO pull-up state in Standby and Shutdown modes. - * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in - * pull-up state in Standby and Shutdown modes. - * @note This state is effective in Standby and Shutdown modes only if APC bit - * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. - * @note The configuration is lost when exiting the Shutdown mode due to the - * power-on reset, maintained when exiting the Standby mode. - * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding - * PDy bit of PWR_PDCRx register is cleared unless it is reserved. - * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input - * parameter at the same time are set. - * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H - * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. - * @param GPIONumber: Specify the I/O pins numbers. - * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to set - * several bits for a given port in a single API call. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) -{ - assert_param(IS_PWR_GPIO(GPIO)); - assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - - switch (GPIO) - { - case PWR_GPIO_A: - SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); - CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); - break; - case PWR_GPIO_B: - SET_BIT(PWR->PUCRB, GPIONumber); - CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); - break; - case PWR_GPIO_C: - SET_BIT(PWR->PUCRC, GPIONumber); - CLEAR_BIT(PWR->PDCRC, GPIONumber); - break; -#if defined(GPIOD) - case PWR_GPIO_D: - SET_BIT(PWR->PUCRD, GPIONumber); - CLEAR_BIT(PWR->PDCRD, GPIONumber); - break; -#endif -#if defined(GPIOE) - case PWR_GPIO_E: - SET_BIT(PWR->PUCRE, GPIONumber); - CLEAR_BIT(PWR->PDCRE, GPIONumber); - break; -#endif -#if defined(GPIOF) - case PWR_GPIO_F: - SET_BIT(PWR->PUCRF, GPIONumber); - CLEAR_BIT(PWR->PDCRF, GPIONumber); - break; -#endif -#if defined(GPIOG) - case PWR_GPIO_G: - SET_BIT(PWR->PUCRG, GPIONumber); - CLEAR_BIT(PWR->PDCRG, GPIONumber); - break; -#endif - case PWR_GPIO_H: - SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); -#if defined (STM32L496xx) || defined (STM32L4A6xx) - CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); -#else - CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); -#endif - break; -#if defined(GPIOI) - case PWR_GPIO_I: - SET_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); - CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); - break; -#endif - default: - return HAL_ERROR; - } - - return HAL_OK; -} - - -/** - * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. - * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O - * in pull-up state in Standby and Shutdown modes. - * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input - * parameter at the same time are reset. - * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H - * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. - * @param GPIONumber: Specify the I/O pins numbers. - * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to reset - * several bits for a given port in a single API call. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) -{ - assert_param(IS_PWR_GPIO(GPIO)); - assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - - switch (GPIO) - { - case PWR_GPIO_A: - CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); - break; - case PWR_GPIO_B: - CLEAR_BIT(PWR->PUCRB, GPIONumber); - break; - case PWR_GPIO_C: - CLEAR_BIT(PWR->PUCRC, GPIONumber); - break; -#if defined(GPIOD) - case PWR_GPIO_D: - CLEAR_BIT(PWR->PUCRD, GPIONumber); - break; -#endif -#if defined(GPIOE) - case PWR_GPIO_E: - CLEAR_BIT(PWR->PUCRE, GPIONumber); - break; -#endif -#if defined(GPIOF) - case PWR_GPIO_F: - CLEAR_BIT(PWR->PUCRF, GPIONumber); - break; -#endif -#if defined(GPIOG) - case PWR_GPIO_G: - CLEAR_BIT(PWR->PUCRG, GPIONumber); - break; -#endif - case PWR_GPIO_H: - CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); - break; -#if defined(GPIOI) - case PWR_GPIO_I: - CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); - break; -#endif - default: - return HAL_ERROR; - } - - return HAL_OK; -} - - - -/** - * @brief Enable GPIO pull-down state in Standby and Shutdown modes. - * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in - * pull-down state in Standby and Shutdown modes. - * @note This state is effective in Standby and Shutdown modes only if APC bit - * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. - * @note The configuration is lost when exiting the Shutdown mode due to the - * power-on reset, maintained when exiting the Standby mode. - * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding - * PUy bit of PWR_PUCRx register is cleared unless it is reserved. - * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input - * parameter at the same time are set. - * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H - * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. - * @param GPIONumber: Specify the I/O pins numbers. - * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to set - * several bits for a given port in a single API call. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) -{ - assert_param(IS_PWR_GPIO(GPIO)); - assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - - switch (GPIO) - { - case PWR_GPIO_A: - SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); - CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); - break; - case PWR_GPIO_B: - SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); - CLEAR_BIT(PWR->PUCRB, GPIONumber); - break; - case PWR_GPIO_C: - SET_BIT(PWR->PDCRC, GPIONumber); - CLEAR_BIT(PWR->PUCRC, GPIONumber); - break; -#if defined(GPIOD) - case PWR_GPIO_D: - SET_BIT(PWR->PDCRD, GPIONumber); - CLEAR_BIT(PWR->PUCRD, GPIONumber); - break; -#endif -#if defined(GPIOE) - case PWR_GPIO_E: - SET_BIT(PWR->PDCRE, GPIONumber); - CLEAR_BIT(PWR->PUCRE, GPIONumber); - break; -#endif -#if defined(GPIOF) - case PWR_GPIO_F: - SET_BIT(PWR->PDCRF, GPIONumber); - CLEAR_BIT(PWR->PUCRF, GPIONumber); - break; -#endif -#if defined(GPIOG) - case PWR_GPIO_G: - SET_BIT(PWR->PDCRG, GPIONumber); - CLEAR_BIT(PWR->PUCRG, GPIONumber); - break; -#endif - case PWR_GPIO_H: -#if defined (STM32L496xx) || defined (STM32L4A6xx) - SET_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); -#else - SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); -#endif - CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); - break; -#if defined(GPIOI) - case PWR_GPIO_I: - SET_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); - CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); - break; -#endif - default: - return HAL_ERROR; - } - - return HAL_OK; -} - - -/** - * @brief Disable GPIO pull-down state in Standby and Shutdown modes. - * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O - * in pull-down state in Standby and Shutdown modes. - * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input - * parameter at the same time are reset. - * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H - * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. - * @param GPIONumber: Specify the I/O pins numbers. - * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to reset - * several bits for a given port in a single API call. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) -{ - assert_param(IS_PWR_GPIO(GPIO)); - assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - - switch (GPIO) - { - case PWR_GPIO_A: - CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); - break; - case PWR_GPIO_B: - CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); - break; - case PWR_GPIO_C: - CLEAR_BIT(PWR->PDCRC, GPIONumber); - break; -#if defined(GPIOD) - case PWR_GPIO_D: - CLEAR_BIT(PWR->PDCRD, GPIONumber); - break; -#endif -#if defined(GPIOE) - case PWR_GPIO_E: - CLEAR_BIT(PWR->PDCRE, GPIONumber); - break; -#endif -#if defined(GPIOF) - case PWR_GPIO_F: - CLEAR_BIT(PWR->PDCRF, GPIONumber); - break; -#endif -#if defined(GPIOG) - case PWR_GPIO_G: - CLEAR_BIT(PWR->PDCRG, GPIONumber); - break; -#endif - case PWR_GPIO_H: -#if defined (STM32L496xx) || defined (STM32L4A6xx) - CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); -#else - CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); -#endif - break; -#if defined(GPIOI) - case PWR_GPIO_I: - CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); - break; -#endif - default: - return HAL_ERROR; - } - - return HAL_OK; -} - - - -/** - * @brief Enable pull-up and pull-down configuration. - * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in - * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. - * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding - * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). - * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there - * is no conflict when setting PUy or PDy bit. - * @retval None - */ -void HAL_PWREx_EnablePullUpPullDownConfig(void) -{ - SET_BIT(PWR->CR3, PWR_CR3_APC); -} - - -/** - * @brief Disable pull-up and pull-down configuration. - * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in - * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. - * @retval None - */ -void HAL_PWREx_DisablePullUpPullDownConfig(void) -{ - CLEAR_BIT(PWR->CR3, PWR_CR3_APC); -} - - - -/** - * @brief Enable SRAM2 content retention in Standby mode. - * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in - * Standby mode and its content is kept. - * @retval None - */ -void HAL_PWREx_EnableSRAM2ContentRetention(void) -{ - SET_BIT(PWR->CR3, PWR_CR3_RRS); -} - - -/** - * @brief Disable SRAM2 content retention in Standby mode. - * @note When RRS bit is reset, SRAM2 is powered off in Standby mode - * and its content is lost. - * @retval None - */ -void HAL_PWREx_DisableSRAM2ContentRetention(void) -{ - CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); -} - - -#if defined(PWR_CR1_RRSTP) -/** - * @brief Enable SRAM3 content retention in Stop 2 mode. - * @note When RRSTP bit is set, SRAM3 is powered by the low-power regulator in - * Stop 2 mode and its content is kept. - * @retval None - */ -void HAL_PWREx_EnableSRAM3ContentRetention(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_RRSTP); -} - - -/** - * @brief Disable SRAM3 content retention in Stop 2 mode. - * @note When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode - * and its content is lost. - * @retval None - */ -void HAL_PWREx_DisableSRAM3ContentRetention(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP); -} -#endif /* PWR_CR1_RRSTP */ - -#if defined(PWR_CR3_DSIPDEN) -/** - * @brief Enable pull-down activation on DSI pins. - * @retval None - */ -void HAL_PWREx_EnableDSIPinsPDActivation(void) -{ - SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); -} - - -/** - * @brief Disable pull-down activation on DSI pins. - * @retval None - */ -void HAL_PWREx_DisableDSIPinsPDActivation(void) -{ - CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); -} -#endif /* PWR_CR3_DSIPDEN */ - -#if defined(PWR_CR2_PVME1) -/** - * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. - * @retval None - */ -void HAL_PWREx_EnablePVM1(void) -{ - SET_BIT(PWR->CR2, PWR_PVM_1); -} - -/** - * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. - * @retval None - */ -void HAL_PWREx_DisablePVM1(void) -{ - CLEAR_BIT(PWR->CR2, PWR_PVM_1); -} -#endif /* PWR_CR2_PVME1 */ - - -#if defined(PWR_CR2_PVME2) -/** - * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V. - * @retval None - */ -void HAL_PWREx_EnablePVM2(void) -{ - SET_BIT(PWR->CR2, PWR_PVM_2); -} - -/** - * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V. - * @retval None - */ -void HAL_PWREx_DisablePVM2(void) -{ - CLEAR_BIT(PWR->CR2, PWR_PVM_2); -} -#endif /* PWR_CR2_PVME2 */ - - -/** - * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V. - * @retval None - */ -void HAL_PWREx_EnablePVM3(void) -{ - SET_BIT(PWR->CR2, PWR_PVM_3); -} - -/** - * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V. - * @retval None - */ -void HAL_PWREx_DisablePVM3(void) -{ - CLEAR_BIT(PWR->CR2, PWR_PVM_3); -} - - -/** - * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V. - * @retval None - */ -void HAL_PWREx_EnablePVM4(void) -{ - SET_BIT(PWR->CR2, PWR_PVM_4); -} - -/** - * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V. - * @retval None - */ -void HAL_PWREx_DisablePVM4(void) -{ - CLEAR_BIT(PWR->CR2, PWR_PVM_4); -} - - - - -/** - * @brief Configure the Peripheral Voltage Monitoring (PVM). - * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the - * PVM configuration information. - * @note The API configures a single PVM according to the information contained - * in the input structure. To configure several PVMs, the API must be singly - * called for each PVM used. - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage thresholds corresponding to each - * detection level and to each monitored supply. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) -{ - /* Check the parameters */ - assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); - assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); - - - /* Configure EXTI 35 to 38 interrupts if so required: - scan thru PVMType to detect which PVMx is set and - configure the corresponding EXTI line accordingly. */ - switch (sConfigPVM->PVMType) - { -#if defined(PWR_CR2_PVME1) - case PWR_PVM_1: - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVM1_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVM1_EXTI_DISABLE_IT(); - __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); - __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) - { - __HAL_PWR_PVM1_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) - { - __HAL_PWR_PVM1_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) - { - __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) - { - __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); - } - break; -#endif /* PWR_CR2_PVME1 */ - -#if defined(PWR_CR2_PVME2) - case PWR_PVM_2: - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVM2_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVM2_EXTI_DISABLE_IT(); - __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); - __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) - { - __HAL_PWR_PVM2_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) - { - __HAL_PWR_PVM2_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) - { - __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) - { - __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); - } - break; -#endif /* PWR_CR2_PVME2 */ - - case PWR_PVM_3: - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVM3_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVM3_EXTI_DISABLE_IT(); - __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); - __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) - { - __HAL_PWR_PVM3_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) - { - __HAL_PWR_PVM3_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) - { - __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) - { - __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); - } - break; - - case PWR_PVM_4: - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVM4_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVM4_EXTI_DISABLE_IT(); - __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); - __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) - { - __HAL_PWR_PVM4_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) - { - __HAL_PWR_PVM4_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) - { - __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) - { - __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); - } - break; - - default: - return HAL_ERROR; - - } - - - return HAL_OK; -} - - - -/** - * @brief Enter Low-power Run mode - * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. - * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the - * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register. - * Additionally, the clock frequency must be reduced below 2 MHz. - * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must - * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. - * @retval None - */ -void HAL_PWREx_EnableLowPowerRunMode(void) -{ - /* Set Regulator parameter */ - SET_BIT(PWR->CR1, PWR_CR1_LPR); -} - - -/** - * @brief Exit Low-power Run mode. - * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that - * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode - * returns HAL_TIMEOUT status). The system clock frequency can then be - * increased above 2 MHz. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) -{ - uint32_t wait_loop_index = 0; - - /* Clear LPR bit */ - CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); - - /* Wait until REGLPF is reset */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))) - { - wait_loop_index--; - } - if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) - { - return HAL_TIMEOUT; - } - - return HAL_OK; -} - - -/** - * @brief Enter Stop 0 mode. - * @note In Stop 0 mode, main and low voltage regulators are ON. - * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated - * only to the peripheral requesting it. - * SRAM1, SRAM2 and register contents are preserved. - * The BOR is available. - * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. - * @note By keeping the internal regulator ON during Stop 0 mode, the consumption - * is higher although the startup time is reduced. - * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction - * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction - * @retval None - */ -void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Stop 0 mode with Main Regulator */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - - -/** - * @brief Enter Stop 1 mode. - * @note In Stop 1 mode, only low power voltage regulator is ON. - * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated - * only to the peripheral requesting it. - * SRAM1, SRAM2 and register contents are preserved. - * The BOR is available. - * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. - * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode. - * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction - * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction - * @retval None - */ -void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Stop 1 mode with Low-Power Regulator */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - - -/** - * @brief Enter Stop 2 mode. - * @note In Stop 2 mode, only low power voltage regulator is ON. - * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped, the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability - * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after - * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only - * to the peripheral requesting it. - * SRAM1, SRAM2 and register contents are preserved. - * The BOR is available. - * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode. - * Otherwise, Stop 1 mode is entered. - * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. - * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction - * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction - * @retval None - */ -void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) -{ - /* Check the parameter */ - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Set Stop mode 2 */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - - - - - -/** - * @brief Enter Shutdown mode. - * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched - * off. The voltage regulator is disabled and Vcore domain is powered off. - * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain. - * The BOR is not available. - * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. - * @retval None - */ -void HAL_PWREx_EnterSHUTDOWNMode(void) -{ - - /* Set Shutdown mode */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - - - - -/** - * @brief This function handles the PWR PVD/PVMx interrupt request. - * @note This API should be called under the PVD_PVM_IRQHandler(). - * @retval None - */ -void HAL_PWREx_PVD_PVM_IRQHandler(void) -{ - /* Check PWR exti flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) - { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - - /* Clear PVD exti pending bit */ - __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); - } - /* Next, successively check PVMx exti flags */ -#if defined(PWR_CR2_PVME1) - if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET) - { - /* PWR PVM1 interrupt user callback */ - HAL_PWREx_PVM1Callback(); - - /* Clear PVM1 exti pending bit */ - __HAL_PWR_PVM1_EXTI_CLEAR_FLAG(); - } -#endif /* PWR_CR2_PVME1 */ -#if defined(PWR_CR2_PVME2) - if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET) - { - /* PWR PVM2 interrupt user callback */ - HAL_PWREx_PVM2Callback(); - - /* Clear PVM2 exti pending bit */ - __HAL_PWR_PVM2_EXTI_CLEAR_FLAG(); - } -#endif /* PWR_CR2_PVME2 */ - if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET) - { - /* PWR PVM3 interrupt user callback */ - HAL_PWREx_PVM3Callback(); - - /* Clear PVM3 exti pending bit */ - __HAL_PWR_PVM3_EXTI_CLEAR_FLAG(); - } - if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET) - { - /* PWR PVM4 interrupt user callback */ - HAL_PWREx_PVM4Callback(); - - /* Clear PVM4 exti pending bit */ - __HAL_PWR_PVM4_EXTI_CLEAR_FLAG(); - } -} - - -#if defined(PWR_CR2_PVME1) -/** - * @brief PWR PVM1 interrupt callback - * @retval None - */ -__weak void HAL_PWREx_PVM1Callback(void) -{ - /* NOTE : This function should not be modified; when the callback is needed, - HAL_PWREx_PVM1Callback() API can be implemented in the user file - */ -} -#endif /* PWR_CR2_PVME1 */ - -#if defined(PWR_CR2_PVME2) -/** - * @brief PWR PVM2 interrupt callback - * @retval None - */ -__weak void HAL_PWREx_PVM2Callback(void) -{ - /* NOTE : This function should not be modified; when the callback is needed, - HAL_PWREx_PVM2Callback() API can be implemented in the user file - */ -} -#endif /* PWR_CR2_PVME2 */ - -/** - * @brief PWR PVM3 interrupt callback - * @retval None - */ -__weak void HAL_PWREx_PVM3Callback(void) -{ - /* NOTE : This function should not be modified; when the callback is needed, - HAL_PWREx_PVM3Callback() API can be implemented in the user file - */ -} - -/** - * @brief PWR PVM4 interrupt callback - * @retval None - */ -__weak void HAL_PWREx_PVM4Callback(void) -{ - /* NOTE : This function should not be modified; when the callback is needed, - HAL_PWREx_PVM4Callback() API can be implemented in the user file - */ -} - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c deleted file mode 100644 index 06a9b2665..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c +++ /dev/null @@ -1,1730 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rcc.c - * @author MCD Application Team - * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Reset and Clock Control (RCC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### RCC specific features ##### - ============================================================================== - [..] - After reset the device is running from Multiple Speed Internal oscillator - (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache - and I-Cache are disabled, and all peripherals are off except internal - SRAM, Flash and JTAG. - - (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses: - all peripherals mapped on these busses are running at MSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in analog mode, except the JTAG pins which - are assigned to be used for debug purpose. - - [..] - Once the device started from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB busses prescalers - (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals which clocks are not - derived from the System clock (SAIx, RTC, ADC, USB OTG FS/SDMMC1/RNG) - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup RCC RCC - * @brief RCC HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup RCC_Private_Constants RCC Private Constants - * @{ - */ -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define MSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCC_Private_Macros RCC Private Macros - * @{ - */ -#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 - -#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ - (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__))) -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup RCC_Private_Functions RCC Private Functions - * @{ - */ -static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -static uint32_t RCC_GetSysClockFreqFromPLLSource(void); -#endif -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the internal and external oscillators - (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 - and APB2). - - [..] Internal/external clock and PLL configuration - (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ. - It can be used to generate the clock for the USB OTG FS (48 MHz). - The number of flash wait states is automatically adjusted when MSI range is updated with - HAL_RCC_OscConfig() and the MSI is used as System clock source. - - (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC - clock source. - - (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also optionally as RTC clock source. - - (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source. - - (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks: - (++) The first output is used to generate the high speed system clock (up to 80MHz). - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). - (++) The third output is used to generate an accurate clock to achieve - high-quality audio performance on SAI interface. - - (+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks: - (++) The first output is used to generate SAR ADC1 clock. - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). - (++) The Third output is used to generate an accurate clock to achieve - high-quality audio performance on SAI interface. - - (+) PLLSAI2 (clocked by HSI , HSE or MSI) providing up to two independent output clocks: - (++) The first output is used to generate SAR ADC2 clock. - (++) The second output is used to generate an accurate clock to achieve - high-quality audio performance on SAI interface. - - (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs - (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to HSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) - exception vector. - - (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or - main PLL clock (through a configurable prescaler) on PA8 pin. - - [..] System, AHB and APB busses clocks configuration - (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, - HSE and main PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. - - -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: - - (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSAI2) or - from an external clock mapped on the SAI_CKIN pin. - You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. - (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 31. - You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function - to configure this clock. - (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz - to work correctly, while the SDMMC1 and RNG peripherals require a frequency - equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1 - through PLLQ divider. You have to enable the peripheral clock and use - HAL_RCCEx_PeriphCLKConfig() function to configure this clock. - (+@) IWDG clock which is always the LSI clock. - - - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz. - The clock source frequency should be adapted depending on the device voltage range - as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter. - - @endverbatim - - Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices - +--------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |--------------------------------------| - | | voltage range 1 | voltage range 2 | - | | 1.2 V | 1.0 V | - |-----------------|-------------------|------------------| - |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 | - |-----------------|-------------------|------------------| - |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 | - |-----------------|-------------------|------------------| - |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 | - +--------------------------------------------------------+ - - Table 2. HCLK clock frequency for other STM32L4 devices - +-------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |-------------------------------------| - | | voltage range 1 | voltage range 2 | - | | 1.2 V | 1.0 V | - |-----------------|------------------|------------------| - |0WS(1 CPU cycles)| 0 < HCLK <= 16 | 0 < HCLK <= 6 | - |-----------------|------------------|------------------| - |1WS(2 CPU cycles)| 16 < HCLK <= 32 | 6 < HCLK <= 12 | - |-----------------|------------------|------------------| - |2WS(3 CPU cycles)| 32 < HCLK <= 48 | 12 < HCLK <= 18 | - |-----------------|------------------|------------------| - |3WS(4 CPU cycles)| 48 < HCLK <= 64 | 18 < HCLK <= 26 | - |-----------------|------------------|------------------| - |4WS(5 CPU cycles)| 64 < HCLK <= 80 | 18 < HCLK <= 26 | - +-------------------------------------------------------+ - * @{ - */ - -/** - * @brief Reset the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - MSI ON and used as system clock source - * - HSE, HSI, PLL, PLLSAI1 and PLLISAI2 OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 OFF - * - All interrupts disabled - * - All interrupt and reset flags cleared - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_DeInit(void) -{ - uint32_t tickstart = 0; - - /* Set MSION bit */ - SET_BIT(RCC->CR, RCC_CR_MSION); - - /* Insure MSIRDY bit is set before writing default MSIRANGE value */ - /* Get start tick */ - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set MSIRANGE default value */ - MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6); - - /* Reset CFGR register (MSI is selected as system clock source) */ - CLEAR_REG(RCC->CFGR); - - /* Update the SystemCoreClock global variable for MSI as system clock source */ - SystemCoreClock = MSI_VALUE; - - /* Configure the source of time base considering new system clock settings */ - if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) - { - return HAL_ERROR; - } - - /* Insure MSI selected as system clock source */ - /* Get start tick */ - tickstart = HAL_GetTick(); - - /* Wait till system clock source is ready */ - while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */ -#if defined(RCC_PLLSAI2_SUPPORT) - - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON); - -#else - - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON); - -#endif /* RCC_PLLSAI2_SUPPORT */ - - /* Insure PLLRDY, PLLSAI1RDY and PLLSAI2RDY (if present) are reset */ - /* Get start tick */ - tickstart = HAL_GetTick(); - -#if defined(RCC_PLLSAI2_SUPPORT) - - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) - -#else - - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) - -#endif - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Reset PLLCFGR register */ - CLEAR_REG(RCC->PLLCFGR); - SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 ); - - /* Reset PLLSAI1CFGR register */ - CLEAR_REG(RCC->PLLSAI1CFGR); - SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N_4 ); - -#if defined(RCC_PLLSAI2_SUPPORT) - - /* Reset PLLSAI2CFGR register */ - CLEAR_REG(RCC->PLLSAI2CFGR); - SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N_4 ); - -#endif /* RCC_PLLSAI2_SUPPORT */ - - /* Reset HSEBYP bit */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - - /* Disable all interrupts */ - CLEAR_REG(RCC->CIER); - - /* Clear all interrupt flags */ - WRITE_REG(RCC->CICR, 0xFFFFFFFFU); - - /* Clear all reset flags */ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); - - return HAL_OK; -} - -/** - * @brief Initialize the RCC Oscillators according to the specified parameters in the - * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC Oscillators. - * @note The PLL is not disabled when used as system clock. - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this macro. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(RCC_OscInitStruct != NULL); - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - - /*----------------------------- MSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) - { - /* Check the parameters */ - assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); - assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); - assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); - - /* When the MSI is used as system clock it will not be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) ) - { - if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) - { - return HAL_ERROR; - } - - /* Otherwise, just the calibration and MSI range change are allowed */ - else - { - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ - if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) - { - /* First increase number of wait states update if necessary */ - if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) - { - return HAL_ERROR; - } - - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - } - else - { - /* Else, keep current flash latency while decreasing applies */ - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - - /* Decrease number of wait states update if necessary */ - if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) - { - return HAL_ERROR; - } - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; - - /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick (TICK_INT_PRIORITY); - } - } - else - { - /* Check the MSI State */ - if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) - { - /* Enable the Internal High Speed oscillator (MSI). */ - __HAL_RCC_MSI_ENABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - - } - else - { - /* Disable the Internal High Speed oscillator (MSI). */ - __HAL_RCC_MSI_DISABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - - /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) - { - if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - { - return HAL_ERROR; - } - } - else - { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - - /* Check the HSE State */ - if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) - { - if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) - { - /* When HSI is used as system clock it will not be disabled */ - if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - } - else - { - /* Check the HSI State */ - if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is disabled */ - while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - { - FlagStatus pwrclkchanged = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Update LSE configuration in Backup Domain control register */ - /* Requires to enable write access to Backup Domain of necessary */ - if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR1, PWR_CR1_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - - /* Check the LSE State */ - if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is disabled */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Restore clock configuration if changed */ - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } -#if defined(RCC_HSI48_SUPPORT) - /*------------------------------ HSI48 Configuration -----------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); - - /* Check the LSI State */ - if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) - { - /* Enable the Internal Low Speed oscillator (HSI48). */ - __HAL_RCC_HSI48_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI48 is ready */ - while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (HSI48). */ - __HAL_RCC_HSI48_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI48 is disabled */ - while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } -#endif /* RCC_HSI48_SUPPORT */ - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - - if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) - { - /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { - if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); - assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); - assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); - assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the main PLL clock source, multiplication and division factors. */ - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - RCC_OscInitStruct->PLL.PLLM, - RCC_OscInitStruct->PLL.PLLN, - RCC_OscInitStruct->PLL.PLLP, - RCC_OscInitStruct->PLL.PLLQ, - RCC_OscInitStruct->PLL.PLLR); - - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - - /* Enable PLL System Clock output. */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Disable all PLL outputs to save power if no PLLs on */ - if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) -#if defined(RCC_PLLSAI2_SUPPORT) - && - (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) -#endif /* RCC_PLLSAI2_SUPPORT */ - ) - { - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); - } - -#if defined(RCC_PLLSAI2_SUPPORT) - __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK); -#else - __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK); -#endif /* RCC_PLLSAI2_SUPPORT */ - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - else - { - return HAL_ERROR; - } - } - return HAL_OK; -} - -/** - * @brief Initialize the CPU, AHB and APB busses clocks according to the specified - * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC peripheral. - * @param FLatency FLASH Latency - * This parameter can be one of the following values: - * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle - * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle - * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles - * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles - * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles - @if STM32L4S9xx - * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles - * @arg FLASH_LATENCY_6 FLASH 6 Latency cycles - * @arg FLASH_LATENCY_7 FLASH 7 Latency cycles - * @arg FLASH_LATENCY_8 FLASH 8 Latency cycles - * @arg FLASH_LATENCY_9 FLASH 9 Latency cycles - * @arg FLASH_LATENCY_10 FLASH 10 Latency cycles - * @arg FLASH_LATENCY_11 FLASH 11 Latency cycles - * @arg FLASH_LATENCY_12 FLASH 12 Latency cycles - * @arg FLASH_LATENCY_13 FLASH 13 Latency cycles - * @arg FLASH_LATENCY_14 FLASH 14 Latency cycles - * @arg FLASH_LATENCY_15 FLASH 15 Latency cycles - @endif - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated by HAL_RCC_GetHCLKFreq() function called within this function - * - * @note The MSI is used by default as system clock source after - * startup from Reset, wake-up from STANDBY mode. After restart from Reset, - * the MSI frequency is set to its default value 4 MHz. - * - * @note The HSI can be selected as system clock source after - * from STOP modes or in case of failure of the HSE used directly or indirectly - * as system clock (if the Clock Security System CSS is enabled). - * - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source is ready. - * - * @note You can use HAL_RCC_GetClockConfig() function to know which clock is - * currently used as system clock source. - * - * @note Depending on the device voltage range, the software has to set correctly - * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above "Initialization/de-initialization functions") - * @retval None - */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) -{ - uint32_t tickstart = 0; -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t pllfreq = 0; - uint32_t hpre = RCC_SYSCLK_DIV1; -#endif - - /* Check the parameters */ - assert_param(RCC_ClkInitStruct != NULL); - assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); - assert_param(IS_FLASH_LATENCY(FLatency)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ - - /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != FLatency) - { - return HAL_ERROR; - } - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* PLL is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) - { - return HAL_ERROR; - } -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */ - /* Compute target PLL output frequency */ - pllfreq = RCC_GetSysClockFreqFromPLLSource(); - - /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ - if((pllfreq > 80000000U) && - (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)) - || - ((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)))) - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); - hpre = RCC_SYSCLK_DIV2; - } -#endif - } - else - { - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* MSI is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) - { - /* Check the MSI ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) - { - return HAL_ERROR; - } - } - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */ - pllfreq = HAL_RCC_GetSysClockFreq(); - - /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ - if(pllfreq > 80000000U) - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); - hpre = RCC_SYSCLK_DIV2; - } -#endif - - } - - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - else - { - /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */ - if(hpre == RCC_SYSCLK_DIV2) - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); - } - } -#endif - - /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; - - /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick (TICK_INT_PRIORITY); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to: - - (+) Ouput clock to MCO pin. - (+) Retrieve current clock frequencies. - (+) Enable the Clock Security System. - -@endverbatim - * @{ - */ - -/** - * @brief Select the clock source to output on MCO pin(PA8). - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCOx specifies the output direction for the clock source. - * For STM32L4xx family this parameter can have only one value: - * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). - * @param RCC_MCOSource specifies the clock source to output. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO - * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee - * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source - @if STM32L443xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 - @endif - * @param RCC_MCODiv specifies the MCO prescaler. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 no division applied to MCO clock - * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock - * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock - * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock - * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock - * @retval None - */ -void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) -{ - GPIO_InitTypeDef GPIO_InitStruct; - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCOx)); - assert_param(IS_RCC_MCODIV(RCC_MCODiv)); - assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - - /* MCO Clock Enable */ - __MCO1_CLK_ENABLE(); - - /* Configue the MCO1 pin in alternate function mode */ - GPIO_InitStruct.Pin = MCO1_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Alternate = GPIO_AF0_MCO; - HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); - - /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv )); -} - -/** - * @brief Return the SYSCLK frequency. - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is MSI, function returns values based on MSI - * Value as defined by the MSI range. - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), - * HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * - * @note Each time SYSCLK changes, this function must be called to update the - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * - * @retval SYSCLK frequency - */ -uint32_t HAL_RCC_GetSysClockFreq(void) -{ - uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U; - uint32_t sysclockfreq = 0U; - - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI))) - { - /* MSI or PLL with MSI source used as system clock source */ - - /* Get SYSCLK source */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) - { /* MSISRANGE from RCC_CSR applies */ - msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; - } - else - { /* MSIRANGE from RCC_CR applies */ - msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; - } - /*MSI frequency range in HZ*/ - msirange = MSIRangeTable[msirange]; - - if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) - { - /* MSI used as system clock source */ - sysclockfreq = msirange; - } - } - else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) - { - /* HSI used as system clock source */ - sysclockfreq = HSI_VALUE; - } - else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) - { - /* HSE used as system clock source */ - sysclockfreq = HSE_VALUE; - } - - if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) - { - /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); - pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; - - switch (pllsource) - { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - break; - - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - break; - - case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ - default: - pllvco = (msirange / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - break; - } - pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; - sysclockfreq = pllvco/pllr; - } - - return sysclockfreq; -} - -/** - * @brief Return the HCLK frequency. - * @note Each time HCLK changes, this function must be called to update the - * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. - * @retval HCLK frequency in Hz - */ -uint32_t HAL_RCC_GetHCLKFreq(void) -{ - return SystemCoreClock; -} - -/** - * @brief Return the PCLK1 frequency. - * @note Each time PCLK1 changes, this function must be called to update the - * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK1 frequency in Hz - */ -uint32_t HAL_RCC_GetPCLK1Freq(void) -{ - /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); -} - -/** - * @brief Return the PCLK2 frequency. - * @note Each time PCLK2 changes, this function must be called to update the - * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK2 frequency in Hz - */ -uint32_t HAL_RCC_GetPCLK2Freq(void) -{ - /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); -} - -/** - * @brief Configure the RCC_OscInitStruct according to the internal - * RCC configuration registers. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - /* Check the parameters */ - assert_param(RCC_OscInitStruct != NULL); - - /* Set all possible values for the Oscillator type parameter ---------------*/ -#if defined(RCC_HSI48_SUPPORT) - RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ - RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; -#else - RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ - RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; -#endif /* RCC_HSI48_SUPPORT */ - - /* Get the HSE configuration -----------------------------------------------*/ - if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP) - { - RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; - } - else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON) - { - RCC_OscInitStruct->HSEState = RCC_HSE_ON; - } - else - { - RCC_OscInitStruct->HSEState = RCC_HSE_OFF; - } - - /* Get the MSI configuration -----------------------------------------------*/ - if(READ_BIT(RCC->CR, RCC_CR_MSION) == RCC_CR_MSION) - { - RCC_OscInitStruct->MSIState = RCC_MSI_ON; - } - else - { - RCC_OscInitStruct->MSIState = RCC_MSI_OFF; - } - - RCC_OscInitStruct->MSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos; - RCC_OscInitStruct->MSIClockRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE); - - /* Get the HSI configuration -----------------------------------------------*/ - if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION) - { - RCC_OscInitStruct->HSIState = RCC_HSI_ON; - } - else - { - RCC_OscInitStruct->HSIState = RCC_HSI_OFF; - } - - RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos; - - /* Get the LSE configuration -----------------------------------------------*/ - if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) - { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; - } - else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON) - { - RCC_OscInitStruct->LSEState = RCC_LSE_ON; - } - else - { - RCC_OscInitStruct->LSEState = RCC_LSE_OFF; - } - - /* Get the LSI configuration -----------------------------------------------*/ - if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION) - { - RCC_OscInitStruct->LSIState = RCC_LSI_ON; - } - else - { - RCC_OscInitStruct->LSIState = RCC_LSI_OFF; - } - -#if defined(RCC_HSI48_SUPPORT) - /* Get the HSI48 configuration ---------------------------------------------*/ - if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) - { - RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; - } - else - { - RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; - } -#else - RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; -#endif /* RCC_HSI48_SUPPORT */ - - /* Get the PLL configuration -----------------------------------------------*/ - if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; - } - else - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; - } - RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; - RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); - RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U); -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#else - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) - { - RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17; - } - else - { - RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV7; - } -#endif /* RCC_PLLP_DIV_2_31_SUPPORT */ -} - -/** - * @brief Configure the RCC_ClkInitStruct according to the internal - * RCC configuration registers. - * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that - * will be configured. - * @param pFLatency Pointer on the Flash Latency. - * @retval None - */ -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) -{ - /* Check the parameters */ - assert_param(RCC_ClkInitStruct != NULL); - assert_param(pFLatency != NULL); - - /* Set all possible values for the Clock type parameter --------------------*/ - RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - /* Get the SYSCLK configuration --------------------------------------------*/ - RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1); - - /* Get the APB2 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U); - - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY); -} - -/** - * @brief Enable the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. - * @note The Clock Security System can only be cleared by reset. - * @retval None - */ -void HAL_RCC_EnableCSS(void) -{ - SET_BIT(RCC->CR, RCC_CR_CSSON) ; -} - -/** - * @brief Handle the RCC Clock Security System interrupt request. - * @note This API should be called under the NMI_Handler(). - * @retval None - */ -void HAL_RCC_NMI_IRQHandler(void) -{ - /* Check RCC CSSF interrupt flag */ - if(__HAL_RCC_GET_IT(RCC_IT_CSS)) - { - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CSSCallback(); - - /* Clear RCC CSS pending bit */ - __HAL_RCC_CLEAR_IT(RCC_IT_CSS); - } -} - -/** - * @brief RCC Clock Security System interrupt callback. - * @retval none - */ -__weak void HAL_RCC_CSSCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RCC_CSSCallback should be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup RCC_Private_Functions - * @{ - */ -/** - * @brief Update number of Flash wait states in line with MSI range and current - voltage range. - * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11 - * @retval HAL status - */ -static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) -{ - uint32_t vos = 0; - uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ - - if(__HAL_RCC_PWR_IS_CLK_ENABLED()) - { - vos = HAL_PWREx_GetVoltageRange(); - } - else - { - __HAL_RCC_PWR_CLK_ENABLE(); - vos = HAL_PWREx_GetVoltageRange(); - __HAL_RCC_PWR_CLK_DISABLE(); - } - - if(vos == PWR_REGULATOR_VOLTAGE_SCALE1) - { - if(msirange > RCC_MSIRANGE_8) - { - /* MSI > 16Mhz */ - if(msirange > RCC_MSIRANGE_10) - { - /* MSI 48Mhz */ - latency = FLASH_LATENCY_2; /* 2WS */ - } - else - { - /* MSI 24Mhz or 32Mhz */ - latency = FLASH_LATENCY_1; /* 1WS */ - } - } - /* else MSI <= 16Mhz default FLASH_LATENCY_0 0WS */ - } - else - { -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - if(msirange >= RCC_MSIRANGE_8) - { - /* MSI >= 16Mhz */ - latency = FLASH_LATENCY_2; /* 2WS */ - } - else - { - if(msirange == RCC_MSIRANGE_7) - { - /* MSI 8Mhz */ - latency = FLASH_LATENCY_1; /* 1WS */ - } - /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ - } -#else - if(msirange > RCC_MSIRANGE_8) - { - /* MSI > 16Mhz */ - latency = FLASH_LATENCY_3; /* 3WS */ - } - else - { - if(msirange == RCC_MSIRANGE_8) - { - /* MSI 16Mhz */ - latency = FLASH_LATENCY_2; /* 2WS */ - } - else if(msirange == RCC_MSIRANGE_7) - { - /* MSI 8Mhz */ - latency = FLASH_LATENCY_1; /* 1WS */ - } - /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ - } -#endif - } - - __HAL_FLASH_SET_LATENCY(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != latency) - { - return HAL_ERROR; - } - - return HAL_OK; -} - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -/** - * @brief Compute SYSCLK frequency based on PLL SYSCLK source. - * @retval SYSCLK frequency - */ -static uint32_t RCC_GetSysClockFreqFromPLLSource(void) -{ - uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U; - uint32_t sysclockfreq = 0U; - - if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) - { - /* Get MSI range source */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) - { /* MSISRANGE from RCC_CSR applies */ - msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; - } - else - { /* MSIRANGE from RCC_CR applies */ - msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; - } - /*MSI frequency range in HZ*/ - msirange = MSIRangeTable[msirange]; - } - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); - pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; - - switch (pllsource) - { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - break; - - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - break; - - case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ - default: - pllvco = (msirange / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - break; - } - - pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; - sysclockfreq = pllvco/pllr; - - return sysclockfreq; -} -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c deleted file mode 100644 index 7c31e73fb..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c +++ /dev/null @@ -1,3358 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rcc_ex.c - * @author MCD Application Team - * @brief Extended RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities RCC extended peripheral: - * + Extended Peripheral Control functions - * + Extended Clock management functions - * + Extended Clock Recovery System Control functions - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup RCCEx RCCEx - * @brief RCC Extended HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Constants RCCEx Private Constants - * @{ - */ -#define PLLSAI1_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define PLLSAI2_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ - -#define DIVIDER_P_UPDATE 0U -#define DIVIDER_Q_UPDATE 1U -#define DIVIDER_R_UPDATE 2U - -#define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define LSCO_GPIO_PORT GPIOA -#define LSCO_PIN GPIO_PIN_2 -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup RCCEx_Private_Functions RCCEx Private Functions - * @{ - */ -static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider); - -#if defined(RCC_PLLSAI2_SUPPORT) - -static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider); - -#endif /* RCC_PLLSAI2_SUPPORT */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions - * @{ - */ - -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - [..] - (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including - the backup registers) are set to their reset values. - -@endverbatim - * @{ - */ -/** - * @brief Initialize the RCC extended peripherals clocks according to the specified - * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains a field PeriphClockSelection which can be a combination of the following values: - * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock - * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock - @if STM32L462xx - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1) - @endif - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1) - @endif - * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock - @if STM32L462xx - * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) - @endif - @if STM32L4S9xx - * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) - @endif - * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock - * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) - @endif - @if STM32L4S9xx - * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) - @endif - * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock - @if STM32L443xx - * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) - @endif - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) - @endif - * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART2 USART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART3 USART1 peripheral clock - @if STM32L462xx - * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) - @endif - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) - * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) - * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) - @endif - @if STM32L4S9xx - * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) - * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral kernel clock (only for devices with DFSDM1) - * @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO DFSDM1 peripheral audio clock (only for devices with DFSDM1) - * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (only for devices with LTDC) - * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock (only for devices with DSI) - * @arg @ref RCC_PERIPHCLK_OSPI OctoSPI peripheral clock (only for devices with OctoSPI) - @endif - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source: in this case the access to Backup domain is enabled. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tmpregister = 0; - uint32_t tickstart = 0U; - HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ - HAL_StatusTypeDef status = HAL_OK; /* Final status */ - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*-------------------------- SAI1 clock source configuration ---------------------*/ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection)); - - switch(PeriphClkInit->Sai1ClockSelection) - { - case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ - /* Enable SAI Clock output generated form System PLL . */ -#if defined(RCC_PLLSAI2_SUPPORT) - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); -#else - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK); -#endif /* RCC_PLLSAI2_SUPPORT */ - /* SAI1 clock source config set later after clock selection check */ - break; - - case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/ - /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE); - /* SAI1 clock source config set later after clock selection check */ - break; - -#if defined(RCC_PLLSAI2_SUPPORT) - - case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/ - /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */ - ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE); - /* SAI1 clock source config set later after clock selection check */ - break; - -#endif /* RCC_PLLSAI2_SUPPORT */ - - case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/ -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - /* SAI1 clock source config set later after clock selection check */ - break; - - default: - ret = HAL_ERROR; - break; - } - - if(ret == HAL_OK) - { - /* Set the source of SAI1 clock*/ - __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - -#if defined(SAI2) - - /*-------------------------- SAI2 clock source configuration ---------------------*/ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection)); - - switch(PeriphClkInit->Sai2ClockSelection) - { - case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ - /* Enable SAI Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); - /* SAI2 clock source config set later after clock selection check */ - break; - - case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/ - /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE); - /* SAI2 clock source config set later after clock selection check */ - break; - - case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/ - /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */ - ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE); - /* SAI2 clock source config set later after clock selection check */ - break; - - case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/ -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - /* SAI2 clock source config set later after clock selection check */ - break; - - default: - ret = HAL_ERROR; - break; - } - - if(ret == HAL_OK) - { - /* Set the source of SAI2 clock*/ - __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } -#endif /* SAI2 */ - - /*-------------------------- RTC clock source configuration ----------------------*/ - if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) - { - FlagStatus pwrclkchanged = RESET; - - /* Check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - /* Enable Power Clock */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR1, PWR_CR1_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == RESET) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - ret = HAL_TIMEOUT; - break; - } - } - - if(ret == HAL_OK) - { - /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ - tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); - - if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - /* Restore the Content of BDCR register */ - RCC->BDCR = tmpregister; - } - - /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ - if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - ret = HAL_TIMEOUT; - break; - } - } - } - - if(ret == HAL_OK) - { - /* Apply new RTC clock source selection */ - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - else - { - /* set overall return value */ - status = ret; - } - - /* Restore clock configuration if changed */ - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - - /*-------------------------- USART1 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - { - /* Check the parameters */ - assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); - - /* Configure the USART1 clock source */ - __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - } - - /*-------------------------- USART2 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - { - /* Check the parameters */ - assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); - - /* Configure the USART2 clock source */ - __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); - } - -#if defined(USART3) - - /*-------------------------- USART3 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) - { - /* Check the parameters */ - assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); - - /* Configure the USART3 clock source */ - __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); - } - -#endif /* USART3 */ - -#if defined(UART4) - - /*-------------------------- UART4 clock source configuration --------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) - { - /* Check the parameters */ - assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); - - /* Configure the UART4 clock source */ - __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); - } - -#endif /* UART4 */ - -#if defined(UART5) - - /*-------------------------- UART5 clock source configuration --------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) - { - /* Check the parameters */ - assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); - - /* Configure the UART5 clock source */ - __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); - } - -#endif /* UART5 */ - - /*-------------------------- LPUART1 clock source configuration ------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) - { - /* Check the parameters */ - assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); - - /* Configure the LPUAR1 clock source */ - __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); - } - - /*-------------------------- LPTIM1 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) - { - assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); - __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); - } - - /*-------------------------- LPTIM2 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) - { - assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection)); - __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); - } - - /*-------------------------- I2C1 clock source configuration ---------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); - - /* Configure the I2C1 clock source */ - __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - } - -#if defined(I2C2) - - /*-------------------------- I2C2 clock source configuration ---------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); - - /* Configure the I2C2 clock source */ - __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); - } - -#endif /* I2C2 */ - - /*-------------------------- I2C3 clock source configuration ---------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); - - /* Configure the I2C3 clock source */ - __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); - } - -#if defined(I2C4) - - /*-------------------------- I2C4 clock source configuration ---------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); - - /* Configure the I2C4 clock source */ - __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); - } - -#endif /* I2C4 */ - -#if defined(USB_OTG_FS) || defined(USB) - - /*-------------------------- USB clock source configuration ----------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) - { - assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); - __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); - - if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) - { - /* Enable PLL48M1CLK output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - } - else - { - if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) - { - /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - - if(ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } - } - } - } - -#endif /* USB_OTG_FS || USB */ - -#if defined(SDMMC1) - - /*-------------------------- SDMMC1 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1)) - { - assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); - __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); - - if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */ - { - /* Enable PLL48M1CLK output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - } -#if defined(RCC_CCIPR2_SDMMCSEL) - else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLP) /* PLL "P" ? */ - { - /* Enable PLLSAI3CLK output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); - } -#endif - else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1) - { - /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - - if(ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } - } - } - -#endif /* SDMMC1 */ - - /*-------------------------- RNG clock source configuration ----------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) - { - assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); - __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); - - if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) - { - /* Enable PLL48M1CLK output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - } - else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1) - { - /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - - if(ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } - } - } - - /*-------------------------- ADC clock source configuration ----------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) - { - /* Check the parameters */ - assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); - - /* Configure the ADC interface clock source */ - __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); - - if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) - { - /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE); - - if(ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } - } - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) - - else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2) - { - /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ - ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); - - if(ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } - } - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ - - } - -#if defined(SWPMI1) - - /*-------------------------- SWPMI1 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) - { - /* Check the parameters */ - assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); - - /* Configure the SWPMI1 clock source */ - __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); - } - -#endif /* SWPMI1 */ - -#if defined(DFSDM1_Filter0) - - /*-------------------------- DFSDM1 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) - { - /* Check the parameters */ - assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); - - /* Configure the DFSDM1 interface clock source */ - __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); - } - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /*-------------------------- DFSDM1 audio clock source configuration -------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) - { - /* Check the parameters */ - assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); - - /* Configure the DFSDM1 interface audio clock source */ - __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); - } - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) - - /*-------------------------- LTDC clock source configuration --------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) - { - /* Check the parameters */ - assert_param(IS_RCC_LTDCCLKSOURCE(PeriphClkInit->LtdcClockSelection)); - - /* Disable the PLLSAI2 */ - __HAL_RCC_PLLSAI2_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) - { - ret = HAL_TIMEOUT; - break; - } - } - - if(ret == HAL_OK) - { - /* Configure the LTDC clock source */ - __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection); - - /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ - ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); - } - - if(ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } - } - -#endif /* LTDC */ - -#if defined(DSI) - - /*-------------------------- DSI clock source configuration ---------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) - { - /* Check the parameters */ - assert_param(IS_RCC_DSICLKSOURCE(PeriphClkInit->DsiClockSelection)); - - /* Configure the DSI clock source */ - __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection); - - if(PeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLLSAI2) - { - /* PLLSAI2 input clock, parameters M, N & Q configuration and clock output (PLLSAI2ClockOut) */ - ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_Q_UPDATE); - - if(ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } - } - } - -#endif /* DSI */ - -#if defined(OCTOSPI1) || defined(OCTOSPI2) - - /*-------------------------- OctoSPIx clock source configuration ----------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) - { - /* Check the parameters */ - assert_param(IS_RCC_OSPICLKSOURCE(PeriphClkInit->OspiClockSelection)); - - /* Configure the OctoSPI clock source */ - __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); - - if(PeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL) - { - /* Enable PLL48M1CLK output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - } - } - -#endif /* OCTOSPI1 || OCTOSPI2 */ - - return status; -} - -/** - * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * returns the configuration information for the Extended Peripherals - * clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, I2C4, LPUART, - * USART1, USART2, USART3, UART4, UART5, RTC, ADCx, DFSDMx, SWPMI1, USB, SDMMC1 and RNG). - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - /* Set all possible values for the extended clock type parameter------------*/ - -#if defined(STM32L431xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L432xx) || defined(STM32L442xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L433xx) || defined(STM32L443xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L451xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L452xx) || defined(STM32L462xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L471xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L496xx) || defined(STM32L4A6xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L4R5xx) || defined(STM32L4S5xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI; - -#elif defined(STM32L4R7xx) || defined(STM32L4S7xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC; - -#elif defined(STM32L4R9xx) || defined(STM32L4S9xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_DSI; - -#endif /* STM32L431xx */ - - /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ - - PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos; -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U; -#else - PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - PeriphClkInit->PLLSAI1.PLLSAI1N = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; - PeriphClkInit->PLLSAI1.PLLSAI1P = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos) << 4U) + 7U; - PeriphClkInit->PLLSAI1.PLLSAI1Q = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) * 2U; - PeriphClkInit->PLLSAI1.PLLSAI1R = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) * 2U; - -#if defined(RCC_PLLSAI2_SUPPORT) - - /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/ - - PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source; -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - PeriphClkInit->PLLSAI2.PLLSAI2M = (READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U; -#else - PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M; -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - PeriphClkInit->PLLSAI2.PLLSAI2N = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; - PeriphClkInit->PLLSAI2.PLLSAI2P = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) >> RCC_PLLSAI2CFGR_PLLSAI2P_Pos) << 4U) + 7U; -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) - PeriphClkInit->PLLSAI2.PLLSAI2Q = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) * 2U; -#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ - PeriphClkInit->PLLSAI2.PLLSAI2R = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)>> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) * 2U; - -#endif /* RCC_PLLSAI2_SUPPORT */ - - /* Get the USART1 clock source ---------------------------------------------*/ - PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); - /* Get the USART2 clock source ---------------------------------------------*/ - PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); - -#if defined(USART3) - /* Get the USART3 clock source ---------------------------------------------*/ - PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); -#endif /* USART3 */ - -#if defined(UART4) - /* Get the UART4 clock source ----------------------------------------------*/ - PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); -#endif /* UART4 */ - -#if defined(UART5) - /* Get the UART5 clock source ----------------------------------------------*/ - PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); -#endif /* UART5 */ - - /* Get the LPUART1 clock source --------------------------------------------*/ - PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); - - /* Get the I2C1 clock source -----------------------------------------------*/ - PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); - -#if defined(I2C2) - /* Get the I2C2 clock source ----------------------------------------------*/ - PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); -#endif /* I2C2 */ - - /* Get the I2C3 clock source -----------------------------------------------*/ - PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); - -#if defined(I2C4) - /* Get the I2C4 clock source -----------------------------------------------*/ - PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); -#endif /* I2C4 */ - - /* Get the LPTIM1 clock source ---------------------------------------------*/ - PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); - - /* Get the LPTIM2 clock source ---------------------------------------------*/ - PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); - - /* Get the SAI1 clock source -----------------------------------------------*/ - PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); - -#if defined(SAI2) - /* Get the SAI2 clock source -----------------------------------------------*/ - PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); -#endif /* SAI2 */ - - /* Get the RTC clock source ------------------------------------------------*/ - PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); - -#if defined(USB_OTG_FS) || defined(USB) - /* Get the USB clock source ------------------------------------------------*/ - PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); -#endif /* USB_OTG_FS || USB */ - -#if defined(SDMMC1) - /* Get the SDMMC1 clock source ---------------------------------------------*/ - PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); -#endif /* SDMMC1 */ - - /* Get the RNG clock source ------------------------------------------------*/ - PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); - - /* Get the ADC clock source ------------------------------------------------*/ - PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); - -#if defined(SWPMI1) - /* Get the SWPMI1 clock source ---------------------------------------------*/ - PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE(); -#endif /* SWPMI1 */ - -#if defined(DFSDM1_Filter0) - /* Get the DFSDM1 clock source ---------------------------------------------*/ - PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Get the DFSDM1 audio clock source ---------------------------------------*/ - PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) - /* Get the LTDC clock source -----------------------------------------------*/ - PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); -#endif /* LTDC */ - -#if defined(DSI) - /* Get the DSI clock source ------------------------------------------------*/ - PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); -#endif /* DSI */ - -#if defined(OCTOSPI1) || defined(OCTOSPI2) - /* Get the OctoSPIclock source --------------------------------------------*/ - PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); -#endif /* OCTOSPI1 || OCTOSPI2 */ -} - -/** - * @brief Return the peripheral clock frequency for peripherals with clock source from PLLSAIs - * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk Peripheral clock identifier - * This parameter can be one of the following values: - * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock - * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock - @if STM32L462xx - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM) - @endif - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM) - @endif - * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock - @if STM32L462xx - * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) - @endif - @if STM32L4S9xx - * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) - @endif - * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock - * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) - @endif - @if STM32L4S9xx - * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) - @endif - * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock - @if STM32L443xx - * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) - @endif - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) - @endif - * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART2 USART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART3 USART1 peripheral clock - @if STM32L462xx - * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) - @endif - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) - * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) - * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) - @endif - @if STM32L4S9xx - * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) - * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral kernel clock (only for devices with DFSDM1) - * @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO DFSDM1 peripheral audio clock (only for devices with DFSDM1) - * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (only for devices with LTDC) - * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock (only for devices with DSI) - * @arg @ref RCC_PERIPHCLK_OSPI OctoSPI peripheral clock (only for devices with OctoSPI) - @endif - * @retval Frequency in Hz - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ - uint32_t frequency = 0U; - uint32_t srcclk = 0U; - uint32_t pllvco = 0U, plln = 0U, pllp = 0U; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); - - if(PeriphClk == RCC_PERIPHCLK_RTC) - { - /* Get the current RTC source */ - srcclk = __HAL_RCC_GET_RTC_SOURCE(); - - /* Check if LSE is ready and if RTC clock selection is LSE */ - if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Check if LSI is ready and if RTC clock selection is LSI */ - else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - { - frequency = LSI_VALUE; - } - /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ - else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) - { - frequency = HSE_VALUE / 32U; - } - /* Clock not enabled for RTC*/ - else - { - frequency = 0U; - } - } - else - { - /* Other external peripheral clock source than RTC */ - - /* Compute PLL clock input */ - if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) /* MSI ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) - { - /*MSI frequency range in HZ*/ - pllvco = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else - { - pllvco = 0U; - } - } - else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - pllvco = HSI_VALUE; - } - else - { - pllvco = 0U; - } - } - else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) - { - pllvco = HSE_VALUE; - } - else - { - pllvco = 0U; - } - } - else /* No source */ - { - pllvco = 0U; - } - -#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - - switch(PeriphClk) - { -#if defined(SAI2) - - case RCC_PERIPHCLK_SAI1: - case RCC_PERIPHCLK_SAI2: - - if(PeriphClk == RCC_PERIPHCLK_SAI1) - { - srcclk = __HAL_RCC_GET_SAI1_SOURCE(); - - if(srcclk == RCC_SAI1CLKSOURCE_PIN) - { - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - } - /* Else, PLL clock output to check below */ - } - else /* RCC_PERIPHCLK_SAI2 */ - { - srcclk = __HAL_RCC_GET_SAI2_SOURCE(); - - if(srcclk == RCC_SAI2CLKSOURCE_PIN) - { - frequency = EXTERNAL_SAI2_CLOCK_VALUE; - } - /* Else, PLL clock output to check below */ - } - -#else - - case RCC_PERIPHCLK_SAI1: - - if(PeriphClk == RCC_PERIPHCLK_SAI1) - { - srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL); - - if(srcclk == RCC_SAI1CLKSOURCE_PIN) - { - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - } - /* Else, PLL clock output to check below */ - } - -#endif /* SAI2 */ - - if(frequency == 0U) - { -#if defined(SAI2) - if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL)) - { - if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET) - { - /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - frequency = (pllvco * plln) / pllp; - } - } - else if(srcclk == 0U) /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */ - { - if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#endif - /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - frequency = (pllvco * plln) / pllp; - } - } -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI)) - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - } -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#else - if(srcclk == RCC_SAI1CLKSOURCE_PLL) - { - if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != RESET) - { - /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - - frequency = (pllvco * plln) / pllp; - } - else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - /* HSI automatically selected as clock source if PLLs not enabled */ - frequency = HSI_VALUE; - } - else - { - /* No clock source */ - frequency = 0U; - } - } - else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1) - { - if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#endif - /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - - frequency = (pllvco * plln) / pllp; - } - else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - /* HSI automatically selected as clock source if PLLs not enabled */ - frequency = HSI_VALUE; - } - else - { - /* No clock source */ - frequency = 0U; - } - } -#endif /* SAI2 */ - -#if defined(RCC_PLLSAI2_SUPPORT) - - else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2)) - { - if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET) - { -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLLSAI2 Source) / PLLSAI2M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); -#endif - /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */ - plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; -#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - frequency = (pllvco * plln) / pllp; - } - } - -#endif /* RCC_PLLSAI2_SUPPORT */ - - else - { - /* No clock source */ - frequency = 0U; - } - } - break; - -#if defined(USB_OTG_FS) || defined(USB) - - case RCC_PERIPHCLK_USB: - -#endif /* USB_OTG_FS || USB */ - - case RCC_PERIPHCLK_RNG: - -#if defined(SDMMC1) && !defined(RCC_CCIPR2_SDMMCSEL) - - case RCC_PERIPHCLK_SDMMC1: - -#endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */ - - srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); - - if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) - { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else - { - frequency = 0U; - } - } - else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; - } - } - else if(srcclk == RCC_CCIPR_CLK48SEL_0) /* PLLSAI1 ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#endif - /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; - } - } -#if defined(RCC_HSI48_SUPPORT) - else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */ - { - frequency = HSI48_VALUE; - } - else /* No clock source */ - { - frequency = 0U; - } -#else - else /* No clock source */ - { - frequency = 0U; - } -#endif /* RCC_HSI48_SUPPORT */ - break; - -#if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL) - - case RCC_PERIPHCLK_SDMMC1: - - if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)) /* PLL "P" ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - frequency = (pllvco * plln) / pllp; - } - else - { - frequency = 0U; - } - } - else /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */ - { - srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); - - if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) - { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else - { - frequency = 0U; - } - } - else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL "Q" ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; - } - } - else if(srcclk == RCC_CCIPR_CLK48SEL_0) /* PLLSAI1 ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#endif - /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; - } - } - else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */ - { - frequency = HSI48_VALUE; - } - else /* No clock source */ - { - frequency = 0U; - } - } - break; - -#endif /* SDMMC1 && RCC_CCIPR2_SDMMCSEL */ - - case RCC_PERIPHCLK_USART1: - /* Get the current USART1 source */ - srcclk = __HAL_RCC_GET_USART1_SOURCE(); - - if(srcclk == RCC_USART1CLKSOURCE_PCLK2) - { - frequency = HAL_RCC_GetPCLK2Freq(); - } - else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART1 */ - else - { - frequency = 0U; - } - break; - - case RCC_PERIPHCLK_USART2: - /* Get the current USART2 source */ - srcclk = __HAL_RCC_GET_USART2_SOURCE(); - - if(srcclk == RCC_USART2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART2 */ - else - { - frequency = 0U; - } - break; - -#if defined(USART3) - - case RCC_PERIPHCLK_USART3: - /* Get the current USART3 source */ - srcclk = __HAL_RCC_GET_USART3_SOURCE(); - - if(srcclk == RCC_USART3CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART3 */ - else - { - frequency = 0U; - } - break; - -#endif /* USART3 */ - -#if defined(UART4) - - case RCC_PERIPHCLK_UART4: - /* Get the current UART4 source */ - srcclk = __HAL_RCC_GET_UART4_SOURCE(); - - if(srcclk == RCC_UART4CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for UART4 */ - else - { - frequency = 0U; - } - break; - -#endif /* UART4 */ - -#if defined(UART5) - - case RCC_PERIPHCLK_UART5: - /* Get the current UART5 source */ - srcclk = __HAL_RCC_GET_UART5_SOURCE(); - - if(srcclk == RCC_UART5CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for UART5 */ - else - { - frequency = 0U; - } - break; - -#endif /* UART5 */ - - case RCC_PERIPHCLK_LPUART1: - /* Get the current LPUART1 source */ - srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); - - if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPUART1 */ - else - { - frequency = 0U; - } - break; - - case RCC_PERIPHCLK_ADC: - - srcclk = __HAL_RCC_GET_ADC_SOURCE(); - - if(srcclk == RCC_ADCCLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI1) - { - if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#endif - /* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U); - } - } -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) - else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI2) - { - if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET) - { -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLLSAI2 Source) / PLLSAI2M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); -#endif - /* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */ - plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U); - } - } -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ - /* Clock not enabled for ADC */ - else - { - frequency = 0U; - } - break; - -#if defined(DFSDM1_Filter0) - - case RCC_PERIPHCLK_DFSDM1: - /* Get the current DFSDM1 source */ - srcclk = __HAL_RCC_GET_DFSDM1_SOURCE(); - - if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2) - { - frequency = HAL_RCC_GetPCLK2Freq(); - } - else - { - frequency = HAL_RCC_GetSysClockFreq(); - } - break; - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - - case RCC_PERIPHCLK_DFSDM1AUDIO: - /* Get the current DFSDM1 audio source */ - srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); - - if(srcclk == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) - { - frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); - } - else if((srcclk == RCC_DFSDM1AUDIOCLKSOURCE_MSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))) - { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else if((srcclk == RCC_DFSDM1AUDIOCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for DFSDM1 audio source */ - else - { - frequency = 0U; - } - break; - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* DFSDM1_Filter0 */ - - case RCC_PERIPHCLK_I2C1: - /* Get the current I2C1 source */ - srcclk = __HAL_RCC_GET_I2C1_SOURCE(); - - if(srcclk == RCC_I2C1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C1 */ - else - { - frequency = 0U; - } - break; - -#if defined(I2C2) - - case RCC_PERIPHCLK_I2C2: - /* Get the current I2C2 source */ - srcclk = __HAL_RCC_GET_I2C2_SOURCE(); - - if(srcclk == RCC_I2C2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C2 */ - else - { - frequency = 0U; - } - break; - -#endif /* I2C2 */ - - case RCC_PERIPHCLK_I2C3: - /* Get the current I2C3 source */ - srcclk = __HAL_RCC_GET_I2C3_SOURCE(); - - if(srcclk == RCC_I2C3CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C3 */ - else - { - frequency = 0U; - } - break; - -#if defined(I2C4) - - case RCC_PERIPHCLK_I2C4: - /* Get the current I2C4 source */ - srcclk = __HAL_RCC_GET_I2C4_SOURCE(); - - if(srcclk == RCC_I2C4CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_I2C4CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C4 */ - else - { - frequency = 0U; - } - break; - -#endif /* I2C4 */ - - case RCC_PERIPHCLK_LPTIM1: - /* Get the current LPTIM1 source */ - srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); - - if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if((srcclk == RCC_LPTIM1CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - { - frequency = LSI_VALUE; - } - else if((srcclk == RCC_LPTIM1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if ((srcclk == RCC_LPTIM1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM1 */ - else - { - frequency = 0U; - } - break; - - case RCC_PERIPHCLK_LPTIM2: - /* Get the current LPTIM2 source */ - srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); - - if(srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if((srcclk == RCC_LPTIM2CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - { - frequency = LSI_VALUE; - } - else if((srcclk == RCC_LPTIM2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if ((srcclk == RCC_LPTIM2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM2 */ - else - { - frequency = 0U; - } - break; - -#if defined(SWPMI1) - - case RCC_PERIPHCLK_SWPMI1: - /* Get the current SWPMI1 source */ - srcclk = __HAL_RCC_GET_SWPMI1_SOURCE(); - - if(srcclk == RCC_SWPMI1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if((srcclk == RCC_SWPMI1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for SWPMI1 */ - else - { - frequency = 0U; - } - break; - -#endif /* SWPMI1 */ - -#if defined(OCTOSPI1) || defined(OCTOSPI2) - - case RCC_PERIPHCLK_OSPI: - /* Get the current OctoSPI clock source */ - srcclk = __HAL_RCC_GET_OSPI_SOURCE(); - - if(srcclk == RCC_OSPICLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_OSPICLKSOURCE_MSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))) - { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else if(srcclk == RCC_OSPICLKSOURCE_PLL) - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) - { - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); - /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; - } - } - /* Clock not enabled for OctoSPI */ - else - { - frequency = 0U; - } - break; - -#endif /* OCTOSPI1 || OCTOSPI2 */ - - default: - break; - } - } - - return(frequency); -} - -/** - * @} - */ - -/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions - * @brief Extended Clock management functions - * -@verbatim - =============================================================================== - ##### Extended clock management functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the - activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS, - Low speed clock output and clock after wake-up from STOP mode. -@endverbatim - * @{ - */ - -/** - * @brief Enable PLLSAI1. - * @param PLLSAI1Init pointer to an RCC_PLLSAI1InitTypeDef structure that - * contains the configuration information for the PLLSAI1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) -{ - uint32_t tickstart = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */ - assert_param(IS_RCC_PLLSAI1SOURCE(PLLSAI1Init->PLLSAI1Source)); - assert_param(IS_RCC_PLLSAI1M_VALUE(PLLSAI1Init->PLLSAI1M)); - assert_param(IS_RCC_PLLSAI1N_VALUE(PLLSAI1Init->PLLSAI1N)); - assert_param(IS_RCC_PLLSAI1P_VALUE(PLLSAI1Init->PLLSAI1P)); - assert_param(IS_RCC_PLLSAI1Q_VALUE(PLLSAI1Init->PLLSAI1Q)); - assert_param(IS_RCC_PLLSAI1R_VALUE(PLLSAI1Init->PLLSAI1R)); - assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1Init->PLLSAI1ClockOut)); - - /* Disable the PLLSAI1 */ - __HAL_RCC_PLLSAI1_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI1 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* Configure the PLLSAI1 Multiplication factor N */ - /* Configure the PLLSAI1 Division factors M, P, Q and R */ - __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1M, PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R); -#else - /* Configure the PLLSAI1 Multiplication factor N */ - /* Configure the PLLSAI1 Division factors P, Q and R */ - __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R); -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - /* Configure the PLLSAI1 Clock output(s) */ - __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut); - - /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ - __HAL_RCC_PLLSAI1_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI1 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - } - - return status; -} - -/** - * @brief Disable PLLSAI1. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) -{ - uint32_t tickstart = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* Disable the PLLSAI1 */ - __HAL_RCC_PLLSAI1_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI1 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - /* Disable the PLLSAI1 Clock outputs */ - __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN); - - /* Reset PLL source to save power if no PLLs on */ - if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) -#if defined(RCC_PLLSAI2_SUPPORT) - && - (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) -#endif /* RCC_PLLSAI2_SUPPORT */ - ) - { - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); - } - - return status; -} - -#if defined(RCC_PLLSAI2_SUPPORT) - -/** - * @brief Enable PLLSAI2. - * @param PLLSAI2Init pointer to an RCC_PLLSAI2InitTypeDef structure that - * contains the configuration information for the PLLSAI2 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) -{ - uint32_t tickstart = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */ - assert_param(IS_RCC_PLLSAI2SOURCE(PLLSAI2Init->PLLSAI2Source)); - assert_param(IS_RCC_PLLSAI2M_VALUE(PLLSAI2Init->PLLSAI2M)); - assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N)); - assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P)); -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) - assert_param(IS_RCC_PLLSAI2Q_VALUE(PLLSAI2Init->PLLSAI2Q)); -#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ - assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R)); - assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut)); - - /* Disable the PLLSAI2 */ - __HAL_RCC_PLLSAI2_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI2 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) - /* Configure the PLLSAI2 Multiplication factor N */ - /* Configure the PLLSAI2 Division factors M, P, Q and R */ - __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R); -#elif defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* Configure the PLLSAI2 Multiplication factor N */ - /* Configure the PLLSAI2 Division factors M, P and R */ - __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R); -#elif defined(RCC_PLLSAI2Q_DIV_SUPPORT) - /* Configure the PLLSAI2 Multiplication factor N */ - /* Configure the PLLSAI2 Division factors P, Q and R */ - __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R); -#else - /* Configure the PLLSAI2 Multiplication factor N */ - /* Configure the PLLSAI2 Division factors P and R */ - __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R); -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ - /* Configure the PLLSAI2 Clock output(s) */ - __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut); - - /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/ - __HAL_RCC_PLLSAI2_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - } - - return status; -} - -/** - * @brief Disable PLLISAI2. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) -{ - uint32_t tickstart = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* Disable the PLLSAI2 */ - __HAL_RCC_PLLSAI2_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - /* Disable the PLLSAI2 Clock outputs */ -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) - __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2QEN|RCC_PLLSAI2CFGR_PLLSAI2REN); -#else - __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2REN); -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ - - /* Reset PLL source to save power if no PLLs on */ - if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) - && - (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) - ) - { - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); - } - - return status; -} - -#endif /* RCC_PLLSAI2_SUPPORT */ - -/** - * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock. - * @param WakeUpClk Wakeup clock - * This parameter can be one of the following values: - * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection - * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection - * @note This function shall not be called after the Clock Security System on HSE has been - * enabled. - * @retval None - */ -void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) -{ - assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); - - __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); -} - -/** - * @brief Configure the MSI range after standby mode. - * @note After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). - * @param MSIRange MSI range - * This parameter can be one of the following values: - * @arg @ref RCC_MSIRANGE_4 Range 4 around 1 MHz - * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz - * @arg @ref RCC_MSIRANGE_6 Range 6 around 4 MHz (reset value) - * @arg @ref RCC_MSIRANGE_7 Range 7 around 8 MHz - * @retval None - */ -void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange) -{ - assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange)); - - __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange); -} - -/** - * @brief Enable the LSE Clock Security System. - * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled - * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC - * clock with HAL_RCCEx_PeriphCLKConfig(). - * @retval None - */ -void HAL_RCCEx_EnableLSECSS(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; -} - -/** - * @brief Disable the LSE Clock Security System. - * @note LSE Clock Security System can only be disabled after a LSE failure detection. - * @retval None - */ -void HAL_RCCEx_DisableLSECSS(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; - - /* Disable LSE CSS IT if any */ - __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); -} - -/** - * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. - * @note LSE Clock Security System Interrupt is mapped on RTC EXTI line 19 - * @retval None - */ -void HAL_RCCEx_EnableLSECSS_IT(void) -{ - /* Enable LSE CSS */ - SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; - - /* Enable LSE CSS IT */ - __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); - - /* Enable IT on EXTI Line 19 */ - __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); - __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); -} - -/** - * @brief Handle the RCC LSE Clock Security System interrupt request. - * @retval None - */ -void HAL_RCCEx_LSECSS_IRQHandler(void) -{ - /* Check RCC LSE CSSF flag */ - if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) - { - /* RCC LSE Clock Security System interrupt user callback */ - HAL_RCCEx_LSECSS_Callback(); - - /* Clear RCC LSE CSS pending bit */ - __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); - } -} - -/** - * @brief RCCEx LSE Clock Security System interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_LSECSS_Callback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file - */ -} - -/** - * @brief Select the Low Speed clock source to output on LSCO pin (PA2). - * @param LSCOSource specifies the Low Speed clock source to output. - * This parameter can be one of the following values: - * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source - * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source - * @retval None - */ -void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) -{ - GPIO_InitTypeDef GPIO_InitStruct; - FlagStatus pwrclkchanged = RESET; - FlagStatus backupchanged = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); - - /* LSCO Pin Clock Enable */ - __LSCO_CLK_ENABLE(); - - /* Configue the LSCO pin in analog mode */ - GPIO_InitStruct.Pin = LSCO_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct); - - /* Update LSCOSEL clock source in Backup Domain control register */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - { - HAL_PWR_EnableBkUpAccess(); - backupchanged = SET; - } - - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); - - if(backupchanged == SET) - { - HAL_PWR_DisableBkUpAccess(); - } - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } -} - -/** - * @brief Disable the Low Speed clock output. - * @retval None - */ -void HAL_RCCEx_DisableLSCO(void) -{ - FlagStatus pwrclkchanged = RESET; - FlagStatus backupchanged = RESET; - - /* Update LSCOEN bit in Backup Domain control register */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - { - /* Enable access to the backup domain */ - HAL_PWR_EnableBkUpAccess(); - backupchanged = SET; - } - - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); - - /* Restore previous configuration */ - if(backupchanged == SET) - { - /* Disable access to the backup domain */ - HAL_PWR_DisableBkUpAccess(); - } - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } -} - -/** - * @brief Enable the PLL-mode of the MSI. - * @note Prior to enable the PLL-mode of the MSI for automatic hardware - * calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig(). - * @retval None - */ -void HAL_RCCEx_EnableMSIPLLMode(void) -{ - SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ; -} - -/** - * @brief Disable the PLL-mode of the MSI. - * @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled. - * @retval None - */ -void HAL_RCCEx_DisableMSIPLLMode(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN) ; -} - -/** - * @} - */ - -#if defined(CRS) - -/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions - * @brief Extended Clock Recovery System Control functions - * -@verbatim - =============================================================================== - ##### Extended Clock Recovery System Control functions ##### - =============================================================================== - [..] - For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows: - - (#) In System clock config, HSI48 needs to be enabled - - (#) Enable CRS clock in IP MSP init which will use CRS functions - - (#) Call CRS functions as follows: - (##) Prepare synchronization configuration necessary for HSI48 calibration - (+++) Default values can be set for frequency Error Measurement (reload and error limit) - and also HSI48 oscillator smooth trimming. - (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate - directly reload value with target and sychronization frequencies values - (##) Call function HAL_RCCEx_CRSConfig which - (+++) Resets CRS registers to their default values. - (+++) Configures CRS registers with synchronization configuration - (+++) Enables automatic calibration and frequency error counter feature - Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the - periodic USB SOF will not be generated by the host. No SYNC signal will therefore be - provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock - precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs - should be used as SYNC signal. - - (##) A polling function is provided to wait for complete synchronization - (+++) Call function HAL_RCCEx_CRSWaitSynchronization() - (+++) According to CRS status, user can decide to adjust again the calibration or continue - application if synchronization is OK - - (#) User can retrieve information related to synchronization in calling function - HAL_RCCEx_CRSGetSynchronizationInfo() - - (#) Regarding synchronization status and synchronization information, user can try a new calibration - in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. - Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), - it means that the actual frequency is lower than the target (and so, that the TRIM value should be - incremented), while when it is detected during the upcounting phase it means that the actual frequency - is higher (and that the TRIM value should be decremented). - - (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go - through CRS Handler (CRS_IRQn/CRS_IRQHandler) - (++) Call function HAL_RCCEx_CRSConfig() - (++) Enable CRS_IRQn (thanks to NVIC functions) - (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) - (++) Implement CRS status management in the following user callbacks called from - HAL_RCCEx_CRS_IRQHandler(): - (+++) HAL_RCCEx_CRS_SyncOkCallback() - (+++) HAL_RCCEx_CRS_SyncWarnCallback() - (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() - (+++) HAL_RCCEx_CRS_ErrorCallback() - - (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). - This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) - -@endverbatim - * @{ - */ - -/** - * @brief Start automatic synchronization for polling mode - * @param pInit Pointer on RCC_CRSInitTypeDef structure - * @retval None - */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) -{ - uint32_t value = 0; - - /* Check the parameters */ - assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); - assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); - assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); - assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); - assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); - assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); - - /* CONFIGURATION */ - - /* Before configuration, reset CRS registers to their default values*/ - __HAL_RCC_CRS_FORCE_RESET(); - __HAL_RCC_CRS_RELEASE_RESET(); - - /* Set the SYNCDIV[2:0] bits according to Prescaler value */ - /* Set the SYNCSRC[1:0] bits according to Source value */ - /* Set the SYNCSPOL bit according to Polarity value */ - value = (pInit->Prescaler | pInit->Source | pInit->Polarity); - /* Set the RELOAD[15:0] bits according to ReloadValue value */ - value |= pInit->ReloadValue; - /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ - value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); - WRITE_REG(CRS->CFGR, value); - - /* Adjust HSI48 oscillator smooth trimming */ - /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ - MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); - - /* START AUTOMATIC SYNCHRONIZATION*/ - - /* Enable Automatic trimming & Frequency error counter */ - SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); -} - -/** - * @brief Generate the software synchronization event - * @retval None - */ -void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) -{ - SET_BIT(CRS->CR, CRS_CR_SWSYNC); -} - -/** - * @brief Return synchronization info - * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure - * @retval None - */ -void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) -{ - /* Check the parameter */ - assert_param(pSynchroInfo != NULL); - - /* Get the reload value */ - pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); - - /* Get HSI48 oscillator smooth trimming */ - pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); - - /* Get Frequency error capture */ - pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); - - /* Get Frequency error direction */ - pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); -} - -/** -* @brief Wait for CRS Synchronization status. -* @param Timeout Duration of the timeout -* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization -* frequency. -* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. -* @retval Combination of Synchronization status -* This parameter can be a combination of the following values: -* @arg @ref RCC_CRS_TIMEOUT -* @arg @ref RCC_CRS_SYNCOK -* @arg @ref RCC_CRS_SYNCWARN -* @arg @ref RCC_CRS_SYNCERR -* @arg @ref RCC_CRS_SYNCMISS -* @arg @ref RCC_CRS_TRIMOVF -*/ -uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) -{ - uint32_t crsstatus = RCC_CRS_NONE; - uint32_t tickstart = 0U; - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait for CRS flag or timeout detection */ - do - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - crsstatus = RCC_CRS_TIMEOUT; - } - } - /* Check CRS SYNCOK flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) - { - /* CRS SYNC event OK */ - crsstatus |= RCC_CRS_SYNCOK; - - /* Clear CRS SYNC event OK bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); - } - - /* Check CRS SYNCWARN flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) - { - /* CRS SYNC warning */ - crsstatus |= RCC_CRS_SYNCWARN; - - /* Clear CRS SYNCWARN bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); - } - - /* Check CRS TRIM overflow flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) - { - /* CRS SYNC Error */ - crsstatus |= RCC_CRS_TRIMOVF; - - /* Clear CRS Error bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); - } - - /* Check CRS Error flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) - { - /* CRS SYNC Error */ - crsstatus |= RCC_CRS_SYNCERR; - - /* Clear CRS Error bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); - } - - /* Check CRS SYNC Missed flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) - { - /* CRS SYNC Missed */ - crsstatus |= RCC_CRS_SYNCMISS; - - /* Clear CRS SYNC Missed bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); - } - - /* Check CRS Expected SYNC flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) - { - /* frequency error counter reached a zero value */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); - } - } while(RCC_CRS_NONE == crsstatus); - - return crsstatus; -} - -/** - * @brief Handle the Clock Recovery System interrupt request. - * @retval None - */ -void HAL_RCCEx_CRS_IRQHandler(void) -{ - uint32_t crserror = RCC_CRS_NONE; - /* Get current IT flags and IT sources values */ - uint32_t itflags = READ_REG(CRS->ISR); - uint32_t itsources = READ_REG(CRS->CR); - - /* Check CRS SYNCOK flag */ - if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET)) - { - /* Clear CRS SYNC event OK flag */ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); - - /* user callback */ - HAL_RCCEx_CRS_SyncOkCallback(); - } - /* Check CRS SYNCWARN flag */ - else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET)) - { - /* Clear CRS SYNCWARN flag */ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); - - /* user callback */ - HAL_RCCEx_CRS_SyncWarnCallback(); - } - /* Check CRS Expected SYNC flag */ - else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET)) - { - /* frequency error counter reached a zero value */ - WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); - - /* user callback */ - HAL_RCCEx_CRS_ExpectedSyncCallback(); - } - /* Check CRS Error flags */ - else - { - if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET)) - { - if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET) - { - crserror |= RCC_CRS_SYNCERR; - } - if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET) - { - crserror |= RCC_CRS_SYNCMISS; - } - if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET) - { - crserror |= RCC_CRS_TRIMOVF; - } - - /* Clear CRS Error flags */ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC); - - /* user error callback */ - HAL_RCCEx_CRS_ErrorCallback(crserror); - } - } -} - -/** - * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_SyncOkCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System Error interrupt callback. - * @param Error Combination of Error status. - * This parameter can be a combination of the following values: - * @arg @ref RCC_CRS_SYNCERR - * @arg @ref RCC_CRS_SYNCMISS - * @arg @ref RCC_CRS_TRIMOVF - * @retval none - */ -__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(Error); - - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file - */ -} - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/** @addtogroup RCCEx_Private_Functions - * @{ - */ - -/** - * @brief Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s). - * @param PllSai1 pointer to an RCC_PLLSAI1InitTypeDef structure that - * contains the configuration parameters N & P & optionally M as well as PLLSAI1 output clock(s) - * @param Divider divider parameter to be updated - * - * @note PLLSAI1 is temporary disable to apply new parameters - * - * @retval HAL status - */ -static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider) -{ - uint32_t tickstart = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */ - /* P, Q and R dividers are verified in each specific divider case below */ - assert_param(IS_RCC_PLLSAI1SOURCE(PllSai1->PLLSAI1Source)); - assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M)); - assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N)); - assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut)); - - /* Check that PLLSAI1 clock source and divider M can be applied */ - if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) - { - /* PLL clock source and divider M already set, check that no request for change */ - if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source) - || - (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE) -#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - || - (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M) -#endif - ) - { - status = HAL_ERROR; - } - } - else - { - /* Check PLLSAI1 clock source availability */ - switch(PllSai1->PLLSAI1Source) - { - case RCC_PLLSOURCE_MSI: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY)) - { - status = HAL_ERROR; - } - break; - case RCC_PLLSOURCE_HSI: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY)) - { - status = HAL_ERROR; - } - break; - case RCC_PLLSOURCE_HSE: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) - { - status = HAL_ERROR; - } - break; - default: - status = HAL_ERROR; - break; - } - - if(status == HAL_OK) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* Set PLLSAI1 clock source */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source); -#else - /* Set PLLSAI1 clock source and divider M */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos); -#endif - } - } - - if(status == HAL_OK) - { - /* Disable the PLLSAI1 */ - __HAL_RCC_PLLSAI1_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI1 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { - if(Divider == DIVIDER_P_UPDATE) - { - assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P)); -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - - /* Configure the PLLSAI1 Division factor M, P and Multiplication factor N*/ -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV | RCC_PLLSAI1CFGR_PLLSAI1M, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | - ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); -#else - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1M, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | - ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ - -#else - /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/ -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)); -#else - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)); -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ - -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - } - else if(Divider == DIVIDER_Q_UPDATE) - { - assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q)); -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* Configure the PLLSAI1 Division factor M, Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1M, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | - ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); -#else - /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)); -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - } - else - { - assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R)); -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* Configure the PLLSAI1 Division factor M, R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1M, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | - ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); -#else - /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)); -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - } - - /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ - __HAL_RCC_PLLSAI1_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI1 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { - /* Configure the PLLSAI1 Clock output(s) */ - __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut); - } - } - } - - return status; -} - -#if defined(RCC_PLLSAI2_SUPPORT) - -/** - * @brief Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s). - * @param PllSai2 pointer to an RCC_PLLSAI2InitTypeDef structure that - * contains the configuration parameters N & P & optionally M as well as PLLSAI2 output clock(s) - * @param Divider divider parameter to be updated - * - * @note PLLSAI2 is temporary disable to apply new parameters - * - * @retval HAL status - */ -static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider) -{ - uint32_t tickstart = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */ - /* P, Q and R dividers are verified in each specific divider case below */ - assert_param(IS_RCC_PLLSAI2SOURCE(PllSai2->PLLSAI2Source)); - assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M)); - assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N)); - assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut)); - - /* Check that PLLSAI2 clock source and divider M can be applied */ - if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) - { - /* PLL clock source and divider M already set, check that no request for change */ - if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source) - || - (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE) -#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - || - (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M) -#endif - ) - { - status = HAL_ERROR; - } - } - else - { - /* Check PLLSAI2 clock source availability */ - switch(PllSai2->PLLSAI2Source) - { - case RCC_PLLSOURCE_MSI: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY)) - { - status = HAL_ERROR; - } - break; - case RCC_PLLSOURCE_HSI: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY)) - { - status = HAL_ERROR; - } - break; - case RCC_PLLSOURCE_HSE: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) - { - status = HAL_ERROR; - } - break; - default: - status = HAL_ERROR; - break; - } - - if(status == HAL_OK) - { -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* Set PLLSAI2 clock source */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source); -#else - /* Set PLLSAI2 clock source and divider M */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos); -#endif - } - } - - if(status == HAL_OK) - { - /* Disable the PLLSAI2 */ - __HAL_RCC_PLLSAI2_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI2 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { - if(Divider == DIVIDER_P_UPDATE) - { - assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P)); -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - - /* Configure the PLLSAI2 Division factor M, P and Multiplication factor N*/ -#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV | RCC_PLLSAI2CFGR_PLLSAI2M, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | - ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); -#else - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2M, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | - ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); -#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ - -#else - /* Configure the PLLSAI2 Division factor P and Multiplication factor N*/ -#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)); -#else - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)); -#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ - -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - } -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) - else if(Divider == DIVIDER_Q_UPDATE) - { - assert_param(IS_RCC_PLLSAI2Q_VALUE(PllSai2->PLLSAI2Q)); -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* Configure the PLLSAI2 Division factor M, Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2M, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | - ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); -#else - /* Configure the PLLSAI2 Division factor Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)); -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - } -#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ - else - { - assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R)); -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* Configure the PLLSAI2 Division factor M, R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2M, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | - ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); -#else - /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)); -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - } - - /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/ - __HAL_RCC_PLLSAI2_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { - /* Configure the PLLSAI2 Clock output(s) */ - __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut); - } - } - } - - return status; -} - -#endif /* RCC_PLLSAI2_SUPPORT */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c deleted file mode 100644 index 469c6af21..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c +++ /dev/null @@ -1,527 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rng.c - * @author MCD Application Team - * @brief RNG HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Random Number Generator (RNG) peripheral: - * + Initialization/de-initialization functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The RNG HAL driver can be used as follows: - - (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro - in HAL_RNG_MspInit(). - (#) Activate the RNG peripheral using HAL_RNG_Init() function. - (#) Wait until the 32-bit Random Number Generator contains a valid - random data using (polling/interrupt) mode. - (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup RNG RNG - * @brief RNG HAL module driver. - * @{ - */ - -#ifdef HAL_RNG_MODULE_ENABLED - - - -/* Private types -------------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup RNG_Private_Constants RNG_Private_Constants - * @{ - */ -#define RNG_TIMEOUT_VALUE 2 -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup RNG_Exported_Functions - * @{ - */ - -/** @addtogroup RNG_Exported_Functions_Group1 - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the RNG according to the specified parameters - in the RNG_InitTypeDef and create the associated handle - (+) DeInitialize the RNG peripheral - (+) Initialize the RNG MSP (MCU Specific Package) - (+) DeInitialize the RNG MSP - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the RNG peripheral and initialize the associated handle. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) -{ - /* Check the RNG handle allocation */ - if(hrng == NULL) - { - return HAL_ERROR; - } - - assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); -#if defined(RNG_CR_CED) - assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection)); -#endif /* defined(RNG_CR_CED) */ - - if(hrng->State == HAL_RNG_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrng->Lock = HAL_UNLOCKED; - - /* Init the low level hardware */ - HAL_RNG_MspInit(hrng); - } - - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - -#if defined(RNG_CR_CED) - /* Clock Error Detection configuration */ - MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); -#endif /* defined(RNG_CR_CED) */ - - /* Enable the RNG Peripheral */ - __HAL_RNG_ENABLE(hrng); - - /* Initialize the RNG state */ - hrng->State = HAL_RNG_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitialize the RNG peripheral. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) -{ - /* Check the RNG handle allocation */ - if(hrng == NULL) - { - return HAL_ERROR; - } - -#if defined(RNG_CR_CED) - /* Clear Clock Error Detection bit */ - CLEAR_BIT(hrng->Instance->CR, RNG_CR_CED); -#endif /* defined(RNG_CR_CED) */ - - /* Disable the RNG Peripheral */ - CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN); - - /* Clear RNG interrupt status flags */ - CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS); - - /* DeInit the low level hardware */ - HAL_RNG_MspDeInit(hrng); - - /* Update the RNG state */ - hrng->State = HAL_RNG_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hrng); - - /* Return the function status */ - return HAL_OK; -} - -/** - * @brief Initialize the RNG MSP. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval None - */ -__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_MspInit must be implemented in the user file. - */ -} - -/** - * @brief DeInitialize the RNG MSP. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval None - */ -__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_MspDeInit must be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @addtogroup RNG_Exported_Functions_Group2 - * @brief Management functions. - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Get the 32 bit Random number - (+) Get the 32 bit Random number with interrupt enabled - (+) Handle RNG interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Generate a 32-bit random number. - * @note Each time the random number data is read the RNG_FLAG_DRDY flag - * is automatically cleared. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @param random32bit: pointer to generated random number variable if successful. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit) -{ - uint32_t tickstart = 0; - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(hrng); - - /* Check RNS peripheral state */ - if(hrng->State == HAL_RNG_STATE_READY) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if data register contains valid random data */ - while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE) - { - hrng->State = HAL_RNG_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - - return HAL_TIMEOUT; - } - } - - /* Get a 32bit Random number */ - hrng->RandomNumber = hrng->Instance->DR; - *random32bit = hrng->RandomNumber; - - hrng->State = HAL_RNG_STATE_READY; - } - else - { - status = HAL_ERROR; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - - return status; -} - -/** - * @brief Generate a 32-bit random number in interrupt mode. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(hrng); - - /* Check RNG peripheral state */ - if(hrng->State == HAL_RNG_STATE_READY) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - - /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ - __HAL_RNG_ENABLE_IT(hrng); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Handle RNG interrupt request. - * @note In the case of a clock error, the RNG is no more able to generate - * random numbers because the PLL48CLK clock is not correct. User has - * to check that the clock controller is correctly configured to provide - * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). - * The clock error has no impact on the previously generated - * random numbers, and the RNG_DR register contents can be used. - * @note In the case of a seed error, the generation of random numbers is - * interrupted as long as the SECS bit is '1'. If a number is - * available in the RNG_DR register, it must not be used because it may - * not have enough entropy. In this case, it is recommended to clear the - * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable - * the RNG peripheral to reinitialize and restart the RNG. - * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS - * or CEIS are set. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval None - - */ -void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) -{ - /* RNG clock error interrupt occurred */ - if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_ERROR; - - HAL_RNG_ErrorCallback(hrng); - - /* Clear the clock error flag */ - __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI); - - } - - /* Check RNG data ready interrupt occurred */ - if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET) - { - /* Generate random number once, so disable the IT */ - __HAL_RNG_DISABLE_IT(hrng); - - /* Get the 32bit Random number (DRDY flag automatically cleared) */ - hrng->RandomNumber = hrng->Instance->DR; - - if(hrng->State != HAL_RNG_STATE_ERROR) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_READY; - - /* Data Ready callback */ - HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber); - } - } -} - -/** - * @brief Return generated random number in polling mode (Obsolete). - * @note Use HAL_RNG_GenerateRandomNumber() API instead. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval random value - */ -uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng) -{ - if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK) - { - return hrng->RandomNumber; - } - else - { - return 0; - } -} - - -/** - * @brief Return a 32-bit random number with interrupt enabled (Obsolete). - * @note Use HAL_RNG_GenerateRandomNumber_IT() API instead. - * @param hrng: RNG handle - * @retval 32-bit random number - */ -uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) -{ - uint32_t random32bit = 0; - - /* Process locked */ - __HAL_LOCK(hrng); - - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - /* Get a 32bit Random number */ - random32bit = hrng->Instance->DR; - - /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ - __HAL_RNG_ENABLE_IT(hrng); - - /* Return the 32 bit random number */ - return random32bit; -} - - - -/** - * @brief Read latest generated random number. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval random value - */ -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) -{ - return(hrng->RandomNumber); -} - -/** - * @brief Data Ready callback in non-blocking mode. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @param random32bit: generated random value - * @retval None - */ -__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - UNUSED(random32bit); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_ReadyDataCallback must be implemented in the user file. - */ -} - -/** - * @brief RNG error callback. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval None - */ -__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_ErrorCallback must be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @addtogroup RNG_Exported_Functions_Group3 - * @brief Peripheral State functions. - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Return the RNG handle state. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval HAL state - */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) -{ - /* Return RNG handle state */ - return hrng->State; -} - -/** - * @} - */ - -/** - * @} - */ - - -#endif /* HAL_RNG_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c deleted file mode 100644 index 73ffaf2f1..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c +++ /dev/null @@ -1,1539 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rtc.c - * @author MCD Application Team - * @brief RTC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) peripheral: - * + Initialization - * + Calendar (Time and Date) configuration - * + Alarms (Alarm A and Alarm B) configuration - * + WakeUp Timer configuration - * + TimeStamp configuration - * + Tampers configuration - * + Backup Data Registers configuration - * + RTC Tamper and TimeStamp Pins Selection - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### RTC Operating Condition ##### - =============================================================================== - [..] The real-time clock (RTC) and the RTC backup registers can be powered - from the VBAT voltage when the main VDD supply is powered off. - To retain the content of the RTC backup registers and supply the RTC - when VDD is turned off, VBAT pin can be connected to an optional - standby voltage supplied by a battery or by another source. - - ##### Backup Domain Reset ##### - =============================================================================== - [..] The backup domain reset sets all RTC registers and the RCC_BDCR register - to their reset values. - A backup domain reset is generated when one of the following events occurs: - (#) Software reset, triggered by setting the BDRST bit in the - RCC Backup domain control register (RCC_BDCR). - (#) VDD or VBAT power on, if both supplies have previously been powered off. - (#) Tamper detection event resets all data backup registers. - - ##### Backup Domain Access ##### - =================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted write - accesses. - - [..] To enable access to the RTC Domain and RTC registers, proceed as follows: - (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for - PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32) - (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro. - - ##### How to use RTC Driver ##### - =================================================================== - [..] - (#) Enable the RTC domain access (see description in the section above). - (#) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. - - *** Time and Date configuration *** - =================================== - [..] - (#) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() - and HAL_RTC_SetDate() functions. - (#) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. - - *** Alarm configuration *** - =========================== - [..] - (#) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. - You can also configure the RTC Alarm with interrupt mode using the - HAL_RTC_SetAlarm_IT() function. - (#) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. - - ##### RTC and low power modes ##### - =================================================================== - [..] The MCU can be woken up from a low power mode by an RTC alternate - function. - [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - These RTC alternate functions can wake up the system from the Stop and - Standby low power modes. - [..] The system can also wake up from low power modes without depending - on an external interrupt (Auto-wakeup mode), by using the RTC alarm - or the RTC wakeup events. - [..] The RTC provides a programmable time base for waking up from the - Stop or Standby mode at regular intervals. - Wakeup from STOP and Standby modes is possible only when the RTC clock source - is LSE or LSI. - - @endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup RTC RTC - * @brief RTC HAL module driver - * @{ - */ - -#ifdef HAL_RTC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Functions RTC Exported Functions - * @{ - */ - -/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provide functions allowing to initialize and configure the - RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable - RTC registers Write protection, enter and exit the RTC initialization mode, - RTC registers synchronization check and reference clock detection enable. - (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. - It is split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler. - (++) When both prescalers are used, it is recommended to configure the - asynchronous prescaler to a high value to minimize power consumption. - (#) All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - (#) To configure the RTC Calendar, user application should enter - initialization mode. In this mode, the calendar counter is stopped - and its value can be updated. When the initialization sequence is - complete, the calendar restarts counting after 4 RTCCLK cycles. - (#) To read the calendar through the shadow registers after Calendar - initialization, calendar update or after wakeup from low power modes - the software must first clear the RSF flag. The software must then - wait until it is set again before reading the calendar, which means - that the calendar registers have been correctly copied into the - RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function - implements the above software sequence (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the RTC according to the specified parameters - * in the RTC_InitTypeDef structure and initialize the associated handle. - * @param hrtc: RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) -{ - /* Check the RTC peripheral state */ - if(hrtc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); - assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); - assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap)); - assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); - assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); - - if(hrtc->State == HAL_RTC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrtc->Lock = HAL_UNLOCKED; - - /* Initialize RTC MSP */ - HAL_RTC_MspInit(hrtc); - } - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - else - { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); - /* Set RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); - - /* Configure the RTC PRER */ - hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - } - - hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP); - hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; - } -} - -/** - * @brief DeInitialize the RTC peripheral. - * @param hrtc: RTC handle - * @note This function doesn't reset the RTC Backup Data registers. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - hrtc->Instance->TR = (uint32_t)0x00000000; - hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); - /* Reset All CR bits except CR[2:0] */ - hrtc->Instance->CR &= RTC_CR_WUCKSEL; - - tickstart = HAL_GetTick(); - - /* Wait till WUTWF flag is set and if Time out is reached exit */ - while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - - /* Reset all RTC CR register bits */ - hrtc->Instance->CR &= (uint32_t)0x00000000; - hrtc->Instance->WUTR = RTC_WUTR_WUT; - hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF)); - hrtc->Instance->ALRMAR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBR = (uint32_t)0x00000000; - hrtc->Instance->SHIFTR = (uint32_t)0x00000000; - hrtc->Instance->CALR = (uint32_t)0x00000000; - hrtc->Instance->ALRMASSR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000; - - /* Reset ISR register and exit initialization mode */ - hrtc->Instance->ISR = (uint32_t)0x00000000; - - /* Reset Tamper configuration register */ - hrtc->Instance->TAMPCR = 0x00000000; - - /* Reset Option register */ - hrtc->Instance->OR = 0x00000000; - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* De-Initialize RTC MSP */ - HAL_RTC_MspDeInit(hrtc); - - hrtc->State = HAL_RTC_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Initialize the RTC MSP. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the RTC MSP. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTC_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions - * @brief RTC Time and Date functions - * -@verbatim - =============================================================================== - ##### RTC Time and Date functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Time and Date features - -@endverbatim - * @{ - */ - -/** - * @brief Set RTC current time. - * @param hrtc: RTC handle - * @param sTime: Pointer to Time structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if(Format == RTC_FORMAT_BIN) - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(sTime->Hours)); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(sTime->Hours)); - } - assert_param(IS_RTC_MINUTES(sTime->Minutes)); - assert_param(IS_RTC_SECONDS(sTime->Seconds)); - - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ - (((uint32_t)sTime->TimeFormat) << 16)); - } - else - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(sTime->Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - tmpreg = (((uint32_t)(sTime->Hours) << 16) | \ - ((uint32_t)(sTime->Minutes) << 8) | \ - ((uint32_t)sTime->Seconds) | \ - ((uint32_t)(sTime->TimeFormat) << 16)); - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Set the RTC_TR register */ - hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Clear the bits to be configured */ - hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK); - - /* Configure the RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - __HAL_UNLOCK(hrtc); - - return HAL_OK; - } -} - -/** - * @brief Get RTC current time. - * @param hrtc: RTC handle - * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned - * with input format (BIN or BCD), also SubSeconds field returning the - * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler - * factor to be used for second fraction ratio computation. - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds - * value in second fraction ratio with time unit following generic formula: - * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit - * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers to ensure consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers until Current date is read - * to ensure consistency between the time and date values. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get subseconds structure field from the corresponding register*/ - sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); - - /* Get SecondFraction structure field from the corresponding register field*/ - sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); - - /* Get the TR register */ - tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); - - /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) - { - /* Convert the time structure parameters to Binary format */ - sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); - sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); - sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); - } - - return HAL_OK; -} - -/** - * @brief Set RTC current date. - * @param hrtc: RTC handle - * @param sDate: Pointer to date structure - * @param Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) -{ - uint32_t datetmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) - { - sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); - } - - assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); - - if(Format == RTC_FORMAT_BIN) - { - assert_param(IS_RTC_YEAR(sDate->Year)); - assert_param(IS_RTC_MONTH(sDate->Month)); - assert_param(IS_RTC_DATE(sDate->Date)); - - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ - ((uint32_t)sDate->WeekDay << 13)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); - datetmpreg = RTC_Bcd2ToByte(sDate->Month); - assert_param(IS_RTC_MONTH(datetmpreg)); - datetmpreg = RTC_Bcd2ToByte(sDate->Date); - assert_param(IS_RTC_DATE(datetmpreg)); - - datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ - (((uint32_t)sDate->Month) << 8) | \ - ((uint32_t)sDate->Date) | \ - (((uint32_t)sDate->WeekDay) << 13)); - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Set the RTC_DR register */ - hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY ; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; - } -} - -/** - * @brief Get RTC current date. - * @param hrtc: RTC handle - * @param sDate: Pointer to Date structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers to ensure consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers until Current date is read. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) -{ - uint32_t datetmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get the DR register */ - datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); - sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) - { - /* Convert the date structure parameters to Binary format */ - sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); - sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); - sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); - } - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions - * @brief RTC Alarm functions - * -@verbatim - =============================================================================== - ##### RTC Alarm functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Alarm feature - -@endverbatim - * @{ - */ -/** - * @brief Set the specified RTC Alarm. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) -{ - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(sAlarm->Alarm)); - assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if(Format == RTC_FORMAT_BIN) - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); - } - assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); - assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); - } - - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - else - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - - /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Alarm register */ - if(sAlarm->Alarm == RTC_ALARM_A) - { - /* Disable the Alarm A interrupt */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Sub Second register */ - hrtc->Instance->ALRMASSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(hrtc); - } - else - { - /* Disable the Alarm B interrupt */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm B Sub Second register */ - hrtc->Instance->ALRMBSSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMB_ENABLE(hrtc); - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set the specified RTC Alarm with Interrupt. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the HAL_RTC_DeactivateAlarm()). - * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) -{ - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(sAlarm->Alarm)); - assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if(Format == RTC_FORMAT_BIN) - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); - } - assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); - assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); - } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - else - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Alarm register */ - if(sAlarm->Alarm == RTC_ALARM_A) - { - /* Disable the Alarm A interrupt */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* Clear flag alarm A */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Sub Second register */ - hrtc->Instance->ALRMASSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(hrtc); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA); - } - else - { - /* Disable the Alarm B interrupt */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* Clear flag alarm B */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm B Sub Second register */ - hrtc->Instance->ALRMBSSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMB_ENABLE(hrtc); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB); - } - - /* RTC Alarm Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate the specified RTC Alarm. - * @param hrtc: RTC handle - * @param Alarm: Specifies the Alarm. - * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALARM(Alarm)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - if(Alarm == RTC_ALARM_A) - { - /* AlarmA */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) - { - if( (HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - else - { - /* AlarmB */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB); - - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Get the RTC Alarm value and masks. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Date structure - * @param Alarm: Specifies the Alarm. - * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) -{ - uint32_t tmpreg = 0, subsecondtmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(Alarm)); - - if(Alarm == RTC_ALARM_A) - { - /* AlarmA */ - sAlarm->Alarm = RTC_ALARM_A; - - tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); - } - else - { - sAlarm->Alarm = RTC_ALARM_B; - - tmpreg = (uint32_t)(hrtc->Instance->ALRMBR); - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); - } - - /* Fill the structure with the read parameters */ - /* ALRMAR/ALRMBR registers have same mapping) */ - sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16); - sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8); - sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; - sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); - - if(Format == RTC_FORMAT_BIN) - { - sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); - sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); - sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - } - - return HAL_OK; -} - -/** - * @brief Handle Alarm interrupt request. - * @param hrtc: RTC handle - * @retval None - */ -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) -{ - /* Clear the EXTI's line Flag for RTC Alarm */ - __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); - - /* As alarms are sharing the same EXTI line, exit when no more pending Alarm event */ - while(((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)) || - ((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET))) - { - /* Get the AlarmA interrupt source enable status and pending flag status*/ - if((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)) - { - /* Clear the AlarmA interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* AlarmA callback */ - HAL_RTC_AlarmAEventCallback(hrtc); - } - - /* Get the AlarmB interrupt source enable status and pending flag status*/ - if((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)) - { - /* Clear the AlarmB interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - /* AlarmB callback */ - HAL_RTCEx_AlarmBEventCallback(hrtc); - } - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Alarm A callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTC_AlarmAEventCallback could be implemented in the user file - */ -} - -/** - * @brief Handle AlarmA Polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Alarm interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Wait for RTC Time and Date Synchronization - -@endverbatim - * @{ - */ - -/** - * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc: RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) -{ - uint32_t tickstart = 0; - - /* Clear RSF flag */ - hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; - - tickstart = HAL_GetTick(); - - /* Wait the registers to be synchronised */ - while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Get RTC state - -@endverbatim - * @{ - */ -/** - * @brief Return the RTC handle state. - * @param hrtc: RTC handle - * @retval HAL state - */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) -{ - /* Return RTC handle state */ - return hrtc->State; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Functions RTC Private functions - * @{ - */ -/** - * @brief Enter the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc: RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) -{ - uint32_t tickstart = 0; - - /* Check if the Initialization mode is set */ - if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; - - tickstart = HAL_GetTick(); - /* Wait till RTC is in INIT state and if Time out is reached exit */ - while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - - -/** - * @brief Convert a 2 digit decimal to BCD format. - * @param Value: Byte to be converted - * @retval Converted byte - */ -uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint32_t bcdhigh = 0; - - while(Value >= 10) - { - bcdhigh++; - Value -= 10; - } - - return ((uint8_t)(bcdhigh << 4) | Value); -} - -/** - * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted - * @retval Converted word - */ -uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint32_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); -} - -/** - * @} - */ - -#endif /* HAL_RTC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c deleted file mode 100644 index 31a6fe7de..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c +++ /dev/null @@ -1,1875 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rtc_ex.c - * @author MCD Application Team - * @brief Extended RTC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) Extended peripheral: - * + RTC Time Stamp functions - * + RTC Tamper functions - * + RTC Wake-up functions - * + Extended Control functions - * + Extended RTC features functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (+) Enable the RTC domain access. - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. - - *** RTC Wakeup configuration *** - ================================ - [..] - (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() - function. You can also configure the RTC Wakeup timer with interrupt mode - using the HAL_RTCEx_SetWakeUpTimer_IT() function. - (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() - function. - - *** Outputs configuration *** - ============================= - [..] The RTC has 2 different outputs: - (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B - and WaKeUp signals. - To output the selected RTC signal, use the HAL_RTC_Init() function. - (+) RTC_CALIB: this output is 512Hz signal or 1Hz. - To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function. - (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on - the RTC_OR register. - (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is - automatically configured in output alternate function. - - *** Smooth digital Calibration configuration *** - ================================================ - [..] - (+) Configure the RTC Original Digital Calibration Value and the corresponding - calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib() - function. - - *** TimeStamp configuration *** - =============================== - [..] - (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function. - You can also configure the RTC TimeStamp with interrupt mode using the - HAL_RTCEx_SetTimeStamp_IT() function. - (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() - function. - - *** Internal TimeStamp configuration *** - =============================== - [..] - (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function. - User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG. - (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() - function. - - *** Tamper configuration *** - ============================ - [..] - (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge - or Level according to the Tamper filter (if equal to 0 Edge else Level) - value, sampling frequency, NoErase, MaskFlag, precharge or discharge and - Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper - with interrupt mode using HAL_RTCEx_SetTamper_IT() function. - (+) The default configuration of the Tamper erases the backup registers. To avoid - erase, enable the NoErase field on the RTC_TAMPCR register. - - *** Backup Data Registers configuration *** - =========================================== - [..] - (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() - function. - (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() - function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup RTCEx RTCEx - * @brief RTC Extended HAL module driver - * @{ - */ - -#ifdef HAL_RTC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT) -#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS |\ - (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ - (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE |\ - (uint32_t)RTC_TAMPCR_TAMP1IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\ - (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF |\ - (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF) -#elif defined(RTC_TAMPER1_SUPPORT) -#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS |\ - (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ - (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE |\ - (uint32_t)RTC_TAMPCR_TAMP1IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\ - (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF) -#elif defined(RTC_TAMPER3_SUPPORT) -#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS |\ - (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ - (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE |\ - (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF |\ - (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF) -#else -#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS |\ - (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ - (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE |\ - (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF) -#endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions - * @{ - */ - - -/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions - * @brief RTC TimeStamp and Tamper functions - * -@verbatim - =============================================================================== - ##### RTC TimeStamp and Tamper functions ##### - =============================================================================== - - [..] This section provide functions allowing to configure TimeStamp feature - -@endverbatim - * @{ - */ - -/** - * @brief Set TimeStamp. - * @note This API must be called before enabling the TimeStamp feature. - * @param hrtc: RTC handle - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the - * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the - * falling edge of the related pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. - * The RTC TimeStamp Pin is per default PC13, but for reasons of - * compatibility, this parameter is required. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); - assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - tmpreg|= TimeStampEdge; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set TimeStamp with Interrupt. - * @param hrtc: RTC handle - * @note This API must be called before enabling the TimeStamp feature. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the - * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the - * falling edge of the related pin. - * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. - * The RTC TimeStamp Pin is per default PC13, but for reasons of - * compatibility, this parameter is required. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); - assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - tmpreg |= TimeStampEdge; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - - /* Enable IT timestamp */ - __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); - - /* RTC timestamp Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate TimeStamp. - * @param hrtc: RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) -{ - uint32_t tmpreg = 0; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set Internal TimeStamp. - * @note This API must be called before enabling the internal TimeStamp feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the internal Time Stamp Enable bits */ - __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate Internal TimeStamp. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the internal Time Stamp Enable bits */ - __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Get the RTC TimeStamp value. - * @param hrtc: RTC handle - * @param sTimeStamp: Pointer to Time structure - * @param sTimeStampDate: Pointer to Date structure - * @param Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) -{ - uint32_t tmptime = 0, tmpdate = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); - sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; - - /* Fill the Date structure fields with the read parameters */ - sTimeStampDate->Year = 0; - sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) - { - /* Convert the TimeStamp structure parameters to Binary format */ - sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); - sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); - sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); - - /* Convert the DateTimeStamp structure parameters to Binary format */ - sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); - sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); - sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); - } - - /* Clear the TIMESTAMP Flags */ - __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_ITSF); - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - - return HAL_OK; -} - -/** - * @brief Set Tamper. - * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc: RTC handle - * @param sTamper: Pointer to Tamper Structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); - assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); - assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Configure the tamper trigger */ - if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) - { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); - } - - if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) - { - sTamper->NoErase = 0; -#if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; - } -#endif /* RTC_TAMPER3_SUPPORT */ - } - - if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) - { - sTamper->MaskFlag = 0; -#if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; - } -#endif /* RTC_TAMPER3_SUPPORT */ - } - - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ - (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ - (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK); - - hrtc->Instance->TAMPCR |= tmpreg; - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set Tamper with interrupt. - * @note By calling this API we force the tamper interrupt for all tampers. - * @param hrtc: RTC handle - * @param sTamper: Pointer to RTC Tamper. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); - assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); - assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Configure the tamper trigger */ - if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) - { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); - } - - if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) - { - sTamper->NoErase = 0; -#if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; - } -#endif /* RTC_TAMPER3_SUPPORT */ - } - - if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) - { - sTamper->MaskFlag = 0; -#if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; - } -#endif /* RTC_TAMPER3_SUPPORT */ - } - - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ - (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ - (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK); - - hrtc->Instance->TAMPCR |= tmpreg; - - /* RTC Tamper Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate Tamper. - * @param hrtc: RTC handle - * @param Tamper: Selected tamper pin. - * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) -{ - assert_param(IS_RTC_TAMPER(Tamper)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the selected Tamper pin */ - hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper); - -#if defined(RTC_TAMPER1_SUPPORT) - if ((Tamper & RTC_TAMPER_1) != 0) - { - /* Disable the Tamper1 interrupt */ - hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1)); - } -#endif /* RTC_TAMPER1_SUPPORT */ - if ((Tamper & RTC_TAMPER_2) != 0) - { - /* Disable the Tamper2 interrupt */ - hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2)); - } -#if defined(RTC_TAMPER3_SUPPORT) - if ((Tamper & RTC_TAMPER_3) != 0) - { - /* Disable the Tamper3 interrupt */ - hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3)); - } -#endif /* RTC_TAMPER3_SUPPORT */ - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Handle TimeStamp interrupt request. - * @param hrtc: RTC handle - * @retval None - */ -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); - - /* As Tampers and TimeStamp are sharing the same EXTI line, exit when no more pending event */ - while( - ((__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET) && (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)) -#if defined(RTC_TAMPER1_SUPPORT) - || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)) -#endif /* RTC_TAMPER1_SUPPORT */ - || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)) -#if defined(RTC_TAMPER3_SUPPORT) - || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)) -#endif /* RTC_TAMPER3_SUPPORT */ - ) - { - - /* Get the TimeStamp interrupt source enable status and pending flag status */ - if((__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET) && (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)) - { - /* TIMESTAMP callback */ - HAL_RTCEx_TimeStampEventCallback(hrtc); - - /* Clear the TIMESTAMP interrupt pending bit (this will clear timestamp time and date registers) */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - } - -#if defined(RTC_TAMPER1_SUPPORT) - /* Get the Tamper1 interrupt source enable status and pending flag status */ - if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)) - { - /* Clear the Tamper1 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - - /* Tamper1 callback */ - HAL_RTCEx_Tamper1EventCallback(hrtc); - } -#endif /* RTC_TAMPER1_SUPPORT */ - - /* Get the Tamper2 interrupt source enable status and pending flag status */ - if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)) - { - /* Clear the Tamper2 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - - /* Tamper2 callback */ - HAL_RTCEx_Tamper2EventCallback(hrtc); - } - -#if defined(RTC_TAMPER3_SUPPORT) - /* Get the Tamper3 interrupts source enable status and pending flag status */ - if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)) - { - /* Clear the Tamper3 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); - - /* Tamper3 callback */ - HAL_RTCEx_Tamper3EventCallback(hrtc); - } -#endif /* RTC_TAMPER3_SUPPORT */ - - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief TimeStamp callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file - */ -} - -#if defined(RTC_TAMPER1_SUPPORT) -/** - * @brief Tamper 1 callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file - */ -} -#endif /* RTC_TAMPER1_SUPPORT */ - -/** - * @brief Tamper 2 callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file - */ -} - -#if defined(RTC_TAMPER3_SUPPORT) -/** - * @brief Tamper 3 callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file - */ -} -#endif /* RTC_TAMPER3_SUPPORT */ - -/** - * @brief Handle TimeStamp polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) - { - if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) - { - /* Clear the TIMESTAMP OverRun Flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - - /* Change TIMESTAMP state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -#if defined(RTC_TAMPER1_SUPPORT) -/** - * @brief Handle Tamper 1 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} -#endif /* RTC_TAMPER1_SUPPORT */ - -/** - * @brief Handle Tamper 2 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -#if defined(RTC_TAMPER3_SUPPORT) -/** - * @brief Handle Tamper 3 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} -#endif /* RTC_TAMPER3_SUPPORT */ - -/** - * @} - */ - -/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions - * @brief RTC Wake-up functions - * -@verbatim - =============================================================================== - ##### RTC Wake-up functions ##### - =============================================================================== - - [..] This section provide functions allowing to configure Wake-up feature - -@endverbatim - * @{ - */ - -/** - * @brief Set wake up timer. - * @param hrtc: RTC handle - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) - { - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; - - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set wake up timer with interrupt. - * @param hrtc: RTC handle - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) - { - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - /* Disable the Wake-Up timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* Clear flag Wake-Up */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; - - /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); - - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); - - /* Configure the Interrupt in the RTC_CR register */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); - - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate wake up timer counter. - * @param hrtc: RTC handle - * @retval HAL status - */ -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Disable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); - - tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Get wake up timer counter. - * @param hrtc: RTC handle - * @retval Counter value - */ -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) -{ - /* Get the counter value */ - return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief Handle Wake Up Timer interrupt request. - * @param hrtc: RTC handle - * @retval None - */ -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Clear the EXTI's line Flag for RTC WakeUpTimer */ - __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); - - /* Get the pending status of the WAKEUPTIMER Interrupt */ - if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET) - { - /* Clear the WAKEUPTIMER interrupt pending bit */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - /* WAKEUPTIMER callback */ - HAL_RTCEx_WakeUpTimerEventCallback(hrtc); - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Wake Up Timer callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file - */ -} - -/** - * @brief Handle Wake Up Timer Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - } - - /* Clear the WAKEUPTIMER Flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - - -/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Write a data in a specified RTC Backup data register - (+) Read a data in a specified RTC Backup data register - (+) Set the Coarse calibration parameters. - (+) Deactivate the Coarse calibration parameters - (+) Set the Smooth calibration parameters. - (+) Configure the Synchronization Shift Control Settings. - (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Enable the RTC reference clock detection. - (+) Disable the RTC reference clock detection. - (+) Enable the Bypass Shadow feature. - (+) Disable the Bypass Shadow feature. - -@endverbatim - * @{ - */ - -/** - * @brief Write a data in a specified RTC Backup data register. - * @param hrtc: RTC handle - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Read data from the specified RTC Backup data Register. - * @param hrtc: RTC handle - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval Read value - */ -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @brief Set the Smooth calibration parameters. - * @param hrtc: RTC handle - * @param SmoothCalibPeriod: Select the Smooth Calibration Period. - * This parameter can be can be one of the following values : - * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. - * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. - * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. - * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. - * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses - * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field - * SmoothCalibMinusPulsesValue must be equal to 0. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* check if a calibration is pending*/ - if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) - { - tickstart = HAL_GetTick(); - - /* check if a calibration is pending*/ - while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - - /* Configure the Smooth calibration settings */ - hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Configure the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc: RTC handle - * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. - * This parameter can be one of the following values : - * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. - * @arg RTC_SHIFTADD1S_RESET: No effect. - * @param ShiftSubFS: Select the number of Second Fractions to substitute. - * This parameter can be one any value from 0 to 0x7FFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - tickstart = HAL_GetTick(); - - /* Wait until the shift is completed*/ - while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Check if the reference clock detection is disabled */ - if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - } - else - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: RTC handle - * @param CalibOutput : Select the Calibration output Selection . - * This parameter can be one of the following values: - * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. - * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) -{ - /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Clear flags before config */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; - - /* Configure the RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)CalibOutput; - - __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Enable the RTC reference clock detection. - * @param hrtc: RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Disable the RTC reference clock detection. - * @param hrtc: RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Enable the Bypass Shadow feature. - * @param hrtc: RTC handle - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set the BYPSHAD bit */ - hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Disable the Bypass Shadow feature. - * @param hrtc: RTC handle - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) RTC Alarm B callback - (+) RTC Poll for Alarm B request - -@endverbatim - * @{ - */ - -/** - * @brief Alarm B callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file - */ -} - -/** - * @brief Handle Alarm B Polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Alarm Flag */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RTC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c deleted file mode 100644 index f60505f99..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c +++ /dev/null @@ -1,5675 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_tim.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer (TIM) peripheral: - * + Time Base Initialization - * + Time Base Start - * + Time Base Start Interruption - * + Time Base Start DMA - * + Time Output Compare/PWM Initialization - * + Time Output Compare/PWM Channel Configuration - * + Time Output Compare/PWM Start - * + Time Output Compare/PWM Start Interruption - * + Time Output Compare/PWM Start DMA - * + Time Input Capture Initialization - * + Time Input Capture Channel Configuration - * + Time Input Capture Start - * + Time Input Capture Start Interruption - * + Time Input Capture Start DMA - * + Time One Pulse Initialization - * + Time One Pulse Channel Configuration - * + Time One Pulse Start - * + Time Encoder Interface Initialization - * + Time Encoder Interface Start - * + Time Encoder Interface Start Interruption - * + Time Encoder Interface Start DMA - * + Commutation Event configuration with Interruption and DMA - * + Time OCRef clear configuration - * + Time External Clock configuration - @verbatim - ============================================================================== - ##### TIMER Generic features ##### - ============================================================================== - [..] The Timer features include: - (#) 16-bit up, down, up/down auto-reload counter. - (#) 16-bit programmable prescaler allowing dividing (also on the fly) the - counter clock frequency either by any factor between 1 and 65536. - (#) Up to 4 independent channels for: - (++) Input Capture - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending on the selected feature: - (++) Time Base : HAL_TIM_Base_MspInit() - (++) Input Capture : HAL_TIM_IC_MspInit() - (++) Output Compare : HAL_TIM_OC_MspInit() - (++) PWM generation : HAL_TIM_PWM_MspInit() - (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() - (++) Encoder mode output : HAL_TIM_Encoder_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - Initialization function of this driver: - (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base - (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an - Output Compare signal. - (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a - PWM signal. - (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an - external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. - (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. - - (#) Activate the TIM peripheral using one of the start functions depending from the feature used: - (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() - (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() - (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() - (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() - (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() - (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). - - (#) The DMA Burst is managed with the two following functions: - HAL_TIM_DMABurst_WriteStart() - HAL_TIM_DMABurst_ReadStart() - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup TIM TIM - * @brief TIM HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); -static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig); -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @defgroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions - * -@verbatim - ============================================================================== - ##### Time Base functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM base. - (+) De-initialize the TIM base. - (+) Start the Time Base. - (+) Stop the Time Base. - (+) Start the Time Base and enable interrupt. - (+) Stop the Time Base and disable interrupt. - (+) Start the Time Base and enable DMA transfer. - (+) Stop the Time Base and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Time base Unit according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Set the Time Base configuration */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the TIM Base peripheral - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Base MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Base_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize TIM Base MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Base_MspDeInit could be implemented in the user file - */ -} - - -/** - * @brief Starts the TIM Base generation. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in interrupt mode. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Enable the TIM Update interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in interrupt mode. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Disable the TIM Update interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in DMA mode. - * @param htim TIM handle - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to peripheral. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); - - /* Enable the TIM Update DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in DMA mode. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions - * -@verbatim - ============================================================================== - ##### Time Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Output Compare. - (+) De-initialize the TIM Output Compare. - (+) Start the Time Output Compare. - (+) Stop the Time Output Compare. - (+) Start the Time Output Compare and enable interrupt. - (+) Stop the Time Output Compare and disable interrupt. - (+) Start the Time Output Compare and enable DMA transfer. - (+) Stop the Time Output Compare and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Output Compare according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the Output Compare */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the TIM peripheral - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Output Compare MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize TIM Output Compare MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Output Compare signal generation. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM OC handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions - * -@verbatim - ============================================================================== - ##### Time PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM OPWM. - (+) De-initialize the TIM PWM. - (+) Start the Time PWM. - (+) Stop the Time PWM. - (+) Start the Time PWM and enable interrupt. - (+) Stop the Time PWM and disable interrupt. - (+) Start the Time PWM and enable DMA transfer. - (+) Stop the Time PWM and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM PWM Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the PWM */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the TIM peripheral - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize TIM PWM MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the PWM signal generation. - * @param htim TIM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode. - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim TIM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Output Capture/Compare 3 request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions - * -@verbatim - ============================================================================== - ##### Time Input Capture functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Input Capture. - (+) De-initialize the TIM Input Capture. - (+) Start the Time Input Capture. - (+) Stop the Time Input Capture. - (+) Start the Time Input Capture and enable interrupt. - (+) Stop the Time Input Capture and disable interrupt. - (+) Start the Time Input Capture and enable DMA transfer. - (+) Stop the Time Input Capture and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Input Capture Time base according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the input capture */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the TIM peripheral - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM INput Capture MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize TIM Input Capture MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Input Capture measurement. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement on in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions - * -@verbatim - ============================================================================== - ##### Time One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM One Pulse. - (+) De-initialize the TIM One Pulse. - (+) Start the Time One Pulse. - (+) Stop the Time One Pulse. - (+) Start the Time One Pulse and enable interrupt. - (+) Stop the Time One Pulse and disable interrupt. - (+) Start the Time One Pulse and enable DMA transfer. - (+) Stop the Time One Pulse and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM One Pulse Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() - * @param htim TIM OnePulse handle - * @param OnePulseMode Select the One pulse mode. - * This parameter can be one of the following values: - * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. - * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_OPM_MODE(OnePulseMode)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OnePulse_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the One Pulse Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Reset the OPM Bit */ - htim->Instance->CR1 &= ~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - htim->Instance->CR1 |= OnePulseMode; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the TIM One Pulse - * @param htim TIM One Pulse handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_OnePulse_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize TIM One Pulse MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM One Pulse signal generation. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions - * -@verbatim - ============================================================================== - ##### Time Encoder functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Encoder. - (+) De-initialize the TIM Encoder. - (+) Start the Time Encoder. - (+) Stop the Time Encoder. - (+) Start the Time Encoder and enable interrupt. - (+) Stop the Time Encoder and disable interrupt. - (+) Start the Time Encoder and enable DMA transfer. - (+) Stop the Time Encoder and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Encoder Interface and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() - * @param htim TIM Encoder Interface handle - * @param sConfig TIM Encoder Interface configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) -{ - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_Encoder_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Reset the SMS bits */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = htim->Instance->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = htim->Instance->CCER; - - /* Set the encoder Mode */ - tmpsmcr |= sConfig->EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); - - /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ - tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); - tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); - tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - htim->Instance->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - htim->Instance->CCER = tmpccer; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - - -/** - * @brief DeInitialize the TIM Encoder interface - * @param htim TIM Encoder handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Encoder_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Encoder Interface MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize TIM Encoder Interface MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Enable the encoder interface channels */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - } - break; - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - } - break; - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - } - break; - } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - } - break; - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - } - break; - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - } - break; - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Enable the encoder interface channels */ - /* Enable the capture compare Interrupts 1 and/or 2 */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - else if(Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 and 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1 The destination Buffer address for IC1. - * @param pData2 The destination Buffer address for IC2. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - } - break; - - case TIM_CHANNEL_ALL: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); - - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - default: - break; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - else if(Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 and 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ -/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * -@verbatim - ============================================================================== - ##### IRQ handler management ##### - ============================================================================== - [..] - This section provides Timer IRQ handler function. - -@endverbatim - * @{ - */ -/** - * @brief This function handles TIM interrupts requests. - * @param htim TIM handle - * @retval None - */ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) -{ - /* Capture compare 1 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) - { - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - } - /* Capture compare 2 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 3 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 4 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* TIM Update event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); - HAL_TIM_PeriodElapsedCallback(htim); - } - } - /* TIM Break input event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); - HAL_TIMEx_BreakCallback(htim); - } - } - /* TIM Trigger detection event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); - HAL_TIM_TriggerCallback(htim); - } - } - /* TIM commutation event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); - HAL_TIMEx_CommutationCallback(htim); - } - } -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. - (+) Configure External Clock source. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master and the Slave synchronization. - (+) Configure the DMA Burst Mode. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM Output Compare Channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM Output Compare handle - * @param sConfig TIM Output Compare configuration structure - * @param Channel TIM Channels to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef* sConfig, - uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 1 in Output Compare */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 2 in Output Compare */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 3 in Output Compare */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_5: - { - /* Check the parameters */ - assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 5 in Output Compare */ - TIM_OC5_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_6: - { - /* Check the parameters */ - assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 6 in Output Compare */ - TIM_OC6_SetConfig(htim->Instance, sConfig); - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture Channels according to the specified - * parameters in the TIM_IC_InitTypeDef. - * @param htim TIM IC handle - * @param sConfig TIM Input Capture configuration structure - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (Channel == TIM_CHANNEL_1) - { - /* TI1 Configuration */ - TIM_TI1_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->ICPrescaler; - } - else if (Channel == TIM_CHANNEL_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); - } - else if (Channel == TIM_CHANNEL_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - TIM_TI3_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC3PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - htim->Instance->CCMR2 |= sConfig->ICPrescaler; - } - else - { - /* TI4 Configuration */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - TIM_TI4_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC4PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM PWM handle - * @param sConfig TIM PWM configuration structure - * @param Channel TIM Channels to be configured - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef* sConfig, - uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the Channel 1 in PWM mode */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the Channel 2 in PWM mode */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; - } - break; - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the Channel 3 in PWM mode */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the Channel 4 in PWM mode */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; - } - break; - - case TIM_CHANNEL_5: - { - /* Check the parameters */ - assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - - /* Configure the Channel 5 in PWM mode */ - TIM_OC5_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel5*/ - htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_6: - { - /* Check the parameters */ - assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - - /* Configure the Channel 5 in PWM mode */ - TIM_OC6_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel6 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode << 8; - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse Channels according to the specified - * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim TIM One Pulse handle - * @param sConfig TIM One Pulse configuration structure - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) -{ - TIM_OC_InitTypeDef temp1; - - /* Check the parameters */ - assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); - assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - - if(OutputChannel != InputChannel) - { - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Extract the Ouput compare configuration from sConfig structure */ - temp1.OCMode = sConfig->OCMode; - temp1.Pulse = sConfig->Pulse; - temp1.OCPolarity = sConfig->OCPolarity; - temp1.OCNPolarity = sConfig->OCNPolarity; - temp1.OCIdleState = sConfig->OCIdleState; - temp1.OCNIdleState = sConfig->OCNIdleState; - - switch (OutputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_OC1_SetConfig(htim->Instance, &temp1); - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_OC2_SetConfig(htim->Instance, &temp1); - } - break; - default: - break; - } - - switch (InputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write - * This parameters can be on of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc TIM DMA Request sources - * This parameters can be on of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t* BurstBuffer, uint32_t BurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((BurstBuffer == 0 ) && (BurstLength > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_COM: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_TRIGGER: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - default: - break; - } - /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM DMA Burst mode - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); - } - break; - case TIM_DMA_CC1: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); - } - break; - case TIM_DMA_CC2: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); - } - break; - case TIM_DMA_CC3: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); - } - break; - case TIM_DMA_CC4: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); - } - break; - case TIM_DMA_COM: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); - } - break; - case TIM_DMA_TRIGGER: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); - } - break; - default: - break; - } - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read - * This parameters can be on of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc TIM DMA Request sources - * This parameters can be on of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((BurstBuffer == 0 ) && (BurstLength > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_COM: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_TRIGGER: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - default: - break; - } - - /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the DMA burst reading - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); - } - break; - case TIM_DMA_CC1: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); - } - break; - case TIM_DMA_CC2: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); - } - break; - case TIM_DMA_CC3: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); - } - break; - case TIM_DMA_CC4: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); - } - break; - case TIM_DMA_COM: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); - } - break; - case TIM_DMA_TRIGGER: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); - } - break; - default: - break; - } - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Generate a software event - * @param htim TIM handle - * @param EventSource specifies the event source. - * This parameter can be one of the following values: - * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source - * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EVENTSOURCE_COM: Timer COM event source - * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source - * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source - * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_EVENT_SOURCE(EventSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the event sources */ - htim->Instance->EGR = EventSource; - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the OCRef clear feature - * @param htim TIM handle - * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @arg TIM_Channel_5: TIM Channel 5 - * @arg TIM_Channel_6: TIM Channel 6 - * @retval None - */ -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel) -{ - uint32_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - switch (sClearInputConfig->ClearInputSource) - { - case TIM_CLEARINPUTSOURCE_NONE: - { - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Clear the OCREF clear selection bit */ - tmpsmcr &= ~TIM_SMCR_OCCS; - - /* Clear the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set TIMx_SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - - case TIM_CLEARINPUTSOURCE_OCREFCLR: - { - /* Clear the OCREF clear selection bit */ - htim->Instance->SMCR &= ~TIM_SMCR_OCCS; - } - break; - - case TIM_CLEARINPUTSOURCE_ETR: - { - /* Check the parameters */ - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - - /* Set the OCREF clear selection bit */ - htim->Instance->SMCR |= TIM_SMCR_OCCS; - } - break; - - default: - break; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; - } - } - break; - case TIM_CHANNEL_2: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; - } - else - { - /* Disable the OCREF clear feature for Channel 2 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; - } - } - break; - case TIM_CHANNEL_3: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; - } - else - { - /* Disable the OCREF clear feature for Channel 3 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; - } - } - break; - case TIM_CHANNEL_4: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; - } - else - { - /* Disable the OCREF clear feature for Channel 4 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; - } - } - break; - case TIM_CHANNEL_5: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE; - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE; - } - } - break; - case TIM_CHANNEL_6: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE; - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE; - } - } - break; - default: - break; - } - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the clock source to be used - * @param htim TIM handle - * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that - * contains the clock source information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) -{ - uint32_t tmpsmcr = 0; - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); - - /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - htim->Instance->SMCR = tmpsmcr; - - switch (sClockSourceConfig->ClockSource) - { - case TIM_CLOCKSOURCE_INTERNAL: - { - assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - } - break; - - case TIM_CLOCKSOURCE_ETRMODE1: - { - /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - /* Reset the SMS and TS Bits */ - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - /* Select the External clock mode1 and the ETRF trigger */ - tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - - case TIM_CLOCKSOURCE_ETRMODE2: - { - /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Enable the External clock mode2 */ - htim->Instance->SMCR |= TIM_SMCR_ECE; - } - break; - - case TIM_CLOCKSOURCE_TI1: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - } - break; - - case TIM_CLOCKSOURCE_TI2: - { - /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI2 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI2_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - } - break; - - case TIM_CLOCKSOURCE_TI1ED: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - } - break; - - case TIM_CLOCKSOURCE_ITR0: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); - } - break; - - case TIM_CLOCKSOURCE_ITR1: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); - } - break; - - case TIM_CLOCKSOURCE_ITR2: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); - } - break; - - case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); - } - break; - - default: - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Selects the signal connected to the TI1 input: direct from CH1_input - * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim TIM handle. - * @param TI1_Selection Indicate whether or not channel 1 is connected to the - * output of a XOR gate. - * This parameter can be one of the following values: - * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input - * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 - * pins are connected to the TI1 input (XOR combination) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) -{ - uint32_t tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Reset the TI1 selection */ - tmpcr2 &= ~TIM_CR2_TI1S; - - /* Set the TI1 selection */ - tmpcr2 |= TI1_Selection; - - /* Write to TIMxCR2 */ - htim->Instance->CR2 = tmpcr2; - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); - - /* Disable Trigger Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; - } - -/** - * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) - { - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); - - /* Enable Trigger Interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; - } - -/** - * @brief Read the captured value from Capture Compare unit - * @param htim TIM handle. - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval Captured value - */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpreg = 0; - - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Return the capture 1 value */ - tmpreg = htim->Instance->CCR1; - - break; - } - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Return the capture 2 value */ - tmpreg = htim->Instance->CCR2; - - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Return the capture 3 value */ - tmpreg = htim->Instance->CCR3; - - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Return the capture 4 value */ - tmpreg = htim->Instance->CCR4; - - break; - } - - default: - break; - } - - __HAL_UNLOCK(htim); - return tmpreg; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * -@verbatim - ============================================================================== - ##### TIM Callbacks functions ##### - ============================================================================== - [..] - This section provides TIM callback functions: - (+) Timer Period elapsed callback - (+) Timer Output Compare callback - (+) Timer Input capture callback - (+) Timer Trigger callback - (+) Timer Error callback - -@endverbatim - * @{ - */ - -/** - * @brief Period elapsed callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file - */ - -} -/** - * @brief Output Compare callback in non-blocking mode - * @param htim TIM OC handle - * @retval None - */ -__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file - */ -} -/** - * @brief Input Capture callback in non-blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_IC_CaptureCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_TriggerCallback could be implemented in the user file - */ -} - -/** - * @brief Timer error callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Base handle state. - * @param htim TIM Base handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM OC handle state. - * @param htim TIM Ouput Compare handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM PWM handle state. - * @param htim TIM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Input Capture handle state. - * @param htim TIM IC handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM One Pulse Mode handle state. - * @param htim TIM OPM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode handle state. - * @param htim TIM Encoder handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @} - */ - -/** - * @brief TIM DMA error callback - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMAError(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_ErrorCallback(htim); -} - -/** - * @brief TIM DMA Delay Pulse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - - HAL_TIM_PWM_PulseFinishedCallback(htim); - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} -/** - * @brief TIM DMA Capture complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - - HAL_TIM_IC_CaptureCallback(htim); - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Period Elapse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_PeriodElapsedCallback(htim); -} - -/** - * @brief TIM DMA Trigger callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_TriggerCallback(htim); -} - -/** - * @brief Time Base configuration - * @param TIMx TIM peripheral - * @param Structure TIM Base configuration structure - * @retval None - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) -{ - uint32_t tmpcr1 = 0; - tmpcr1 = TIMx->CR1; - - /* Set TIM Time Base Unit parameters ---------------------------------------*/ - if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - { - /* Select the Counter Mode */ - tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - tmpcr1 |= Structure->CounterMode; - } - - if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - { - /* Set the clock division */ - tmpcr1 &= ~TIM_CR1_CKD; - tmpcr1 |= (uint32_t)Structure->ClockDivision; - } - - /* Set the auto-reload preload */ - tmpcr1 &= ~TIM_CR1_ARPE; - tmpcr1 |= (uint32_t)Structure->AutoReloadPreload; - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = (uint32_t)Structure->Period ; - - /* Set the Prescaler value */ - TIMx->PSC = (uint32_t)Structure->Prescaler; - - if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = Structure->RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediately */ - TIMx->EGR = TIM_EGR_UG; -} - -/** - * @brief Time Ouput Compare 1 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~TIM_CCMR1_OC1M; - tmpccmrx &= ~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= OC_Config->OCPolarity; - - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) - { - /* Check parameters */ - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; - } - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS1; - tmpcr2 &= ~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= OC_Config->OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= OC_Config->OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 2 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR1_OC2M; - tmpccmrx &= ~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4); - - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 4); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; - - } - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS2; - tmpcr2 &= ~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 2); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 3 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC3M; - tmpccmrx &= ~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8); - - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; - } - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS3; - tmpcr2 &= ~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 4); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 4 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC4M; - tmpccmrx &= ~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12); - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS4; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 6); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Ouput Compare 5 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, - TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the output: Reset the CCxE Bit */ - TIMx->CCER &= ~TIM_CCER_CC5E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR3; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~(TIM_CCMR3_OC5M); - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC5P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 16); - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS5; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 8); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR3 */ - TIMx->CCMR3 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR5 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Ouput Compare 6 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, - TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the output: Reset the CCxE Bit */ - TIMx->CCER &= ~TIM_CCER_CC6E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR3; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~(TIM_CCMR3_OC6M); - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)~TIM_CCER_CC6P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 20); - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS6; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 10); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR3 */ - TIMx->CCMR3 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR6 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) -{ - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the Trigger Selection Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source */ - tmpsmcr |= sSlaveConfig->InputTrigger; - - /* Reset the slave mode Bits */ - tmpsmcr &= ~TIM_SMCR_SMS; - /* Set the slave mode */ - tmpsmcr |= sSlaveConfig->SlaveMode; - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Configure the trigger prescaler, filter, and polarity */ - switch (sSlaveConfig->InputTrigger) - { - case TIM_TS_ETRF: - { - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI1F_ED: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = htim->Instance->CCER; - htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); - - /* Write to TIMx CCMR1 and CCER registers */ - htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - - } - break; - - case TIM_TS_TI1FP1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI1 Filter and Polarity */ - TIM_TI1_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI2FP2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI2 Filter and Polarity */ - TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_ITR0: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR1: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR2: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - default: - break; - } -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 - * (on channel2 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) - { - tmpccmr1 &= ~TIM_CCMR1_CC1S; - tmpccmr1 |= TIM_ICSelection; - } - else - { - tmpccmr1 |= TIM_CCMR1_CC1S_0; - } - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI1. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= TIM_ICPolarity; - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 - * (on channel1 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8); - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI2. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC3S; - tmpccmr2 |= TIM_ICSelection; - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - * @retval None - */ -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8); - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx to select the TIM peripheral - * @param InputTriggerSource The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) -{ - uint32_t tmpsmcr = 0; - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source and the slave mode*/ - tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. - * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. - * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. - * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. - * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. - * @param ExtTRGFilter External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) -{ - uint32_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @param ChannelState: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_TIM_CHANNELS(Channel)); - - tmp = TIM_CCER_CC1E << Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint32_t)(ChannelState << Channel); -} - - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c deleted file mode 100644 index 754c1a711..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c +++ /dev/null @@ -1,2243 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_tim_ex.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer Extended peripheral: - * + Time Hall Sensor Interface Initialization - * + Time Hall Sensor Interface Start - * + Time Complementary signal break and dead time configuration - * + Time Master and Slave synchronization configuration - * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) - * + Time OCRef clear configuration - * + Timer remapping capabilities configuration - @verbatim - ============================================================================== - ##### TIMER Extended features ##### - ============================================================================== - [..] - The Timer Extended features include: - (#) Complementary outputs with programmable dead-time for : - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to - interconnect several timers together. - (#) Break input to put the timer output signals in reset state or in a known state. - (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for - positioning purposes - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending on the selected feature: - (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - initialization function of this driver: - (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutationEvent(): to use the - Timer Hall Sensor Interface and the commutation event with the corresponding - Interrupt and DMA request if needed (Note that One Timer is used to interface - with the Hall sensor Interface and another Timer should be used to use - the commutation event). - - (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() - (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). - - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** -*/ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup TIMEx TIMEx - * @brief TIM Extended HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define BDTR_BKF_SHIFT (16) -#define BDTR_BK2F_SHIFT (20) -#define TIMx_ETRSEL_MASK ((uint32_t)0x0003C000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); - -/* Private functions ---------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions - * @{ - */ - -/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * -@verbatim - ============================================================================== - ##### Timer Hall Sensor functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure TIM HAL Sensor. - (+) De-initialize TIM HAL Sensor. - (+) Start the Hall Sensor Interface. - (+) Stop the Hall Sensor Interface. - (+) Start the Hall Sensor Interface and enable interrupts. - (+) Stop the Hall Sensor Interface and disable interrupts. - (+) Start the Hall Sensor Interface and enable DMA transfers. - (+) Stop the Hall Sensor Interface and disable DMA transfers. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. - * @param htim TIM Encoder Interface handle - * @param sConfig TIM Hall Sensor configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) -{ - TIM_OC_InitTypeDef OC_Config; - - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIMEx_HallSensor_MspInit(htim); - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ - TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->IC1Prescaler; - - /* Enable the Hall sensor interface (XOR function of the three inputs) */ - htim->Instance->CR2 |= TIM_CR2_TI1S; - - /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1F_ED; - - /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; - - /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ - OC_Config.OCFastMode = TIM_OCFAST_DISABLE; - OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; - OC_Config.OCMode = TIM_OCMODE_PWM2; - OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; - OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; - OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; - OC_Config.Pulse = sConfig->Commutation_Delay; - - TIM_OC2_SetConfig(htim->Instance, &OC_Config); - - /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 - register to 101 */ - htim->Instance->CR2 &= ~TIM_CR2_MMS; - htim->Instance->CR2 |= TIM_TRGO_OC2REF; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the TIM Hall Sensor interface - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIMEx_HallSensor_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Hall Sensor MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize TIM Hall Sensor MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Hall Sensor Interface. - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall sensor Interface. - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Enable the capture compare Interrupts 1 event */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts event */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM Hall Sensor handle - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Set the DMA Input Capture 1 Callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel for Capture 1*/ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - - /* Enable the capture compare 1 Interrupt */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - - /* Disable the capture compare Interrupts 1 event */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * -@verbatim - ============================================================================== - ##### Timer Complementary Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary Output Compare/PWM. - (+) Stop the Complementary Output Compare/PWM. - (+) Start the Complementary Output Compare/PWM and enable interrupts. - (+) Stop the Complementary Output Compare/PWM and disable interrupts. - (+) Start the Complementary Output Compare/PWM and enable DMA transfers. - (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM OC handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: -{ - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * -@verbatim - ============================================================================== - ##### Timer Complementary PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary PWM. - (+) Stop the Complementary PWM. - (+) Start the Complementary PWM and enable interrupts. - (+) Stop the Complementary PWM and disable interrupts. - (+) Start the Complementary PWM and enable DMA transfers. - (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode on the - * complementary output - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode on the complementary - * output - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * -@verbatim - ============================================================================== - ##### Timer Complementary One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM One Pulse signal generation on the complementary - * output. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) - { - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Enable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation on the complementary - * output. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - /* Enable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure the commutation event in case of use of the Hall sensor interface. - (+) Configure Output channels for OC and PWM mode. - - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master synchronization. - (+) Configure timer remapping capabilities. - (+) Enable or disable channel grouping - -@endverbatim - * @{ - */ - -/** - * @brief Configure the TIM commutation event sequence. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with interrupt. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Enable the Commutation Interrupt Request */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with DMA. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Enable the Commutation DMA Request */ - /* Set the DMA Commutation Callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; - - /* Enable the Commutation DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in master mode. - * @param htim TIM handle. - * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that - * contains the selected trigger output (TRGO) and the Master/Slave - * mode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef * sMasterConfig) -{ - uint32_t tmpcr2; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); - assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ - if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); - - /* Clear the MMS2 bits */ - tmpcr2 &= ~TIM_CR2_MMS2; - /* Select the TRGO2 source*/ - tmpcr2 |= sMasterConfig->MasterOutputTrigger2; - } - - /* Reset the MMS Bits */ - tmpcr2 &= ~TIM_CR2_MMS; - /* Select the TRGO source */ - tmpcr2 |= sMasterConfig->MasterOutputTrigger; - - /* Reset the MSM Bit */ - tmpsmcr &= ~TIM_SMCR_MSM; - /* Set master mode */ - tmpsmcr |= sMasterConfig->MasterSlaveMode; - - /* Update TIMx CR2 */ - htim->Instance->CR2 = tmpcr2; - - /* Update TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param htim TIM handle - * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig) -{ - uint32_t tmpbdtr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); - assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); - assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); - assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); - assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); - assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); - assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - - /* Set the BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); - MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); - MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT)); - - if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); - assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); - assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); - - /* Set the BREAK2 input related BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT)); - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); - } - - /* Set TIMx_BDTR */ - htim->Instance->BDTR = tmpbdtr; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the break input source. - * @param htim TIM handle. - * @param BreakInput Break input to configure - * This parameter can be one of the following values: - * @arg TIM_BREAKINPUT_BRK: Timer break input - * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input - * @param sBreakInputConfig Break input source configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, - uint32_t BreakInput, - TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) - -{ - uint32_t tmporx = 0; - uint32_t bkin_enable_mask = 0; - uint32_t bkin_polarity_mask = 0; - uint32_t bkin_enable_bitpos = 0; - uint32_t bkin_polarity_bitpos = 0; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_BREAKINPUT(BreakInput)); - assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); - assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) - { - assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); - } -#else - assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - - /* Check input state */ - __HAL_LOCK(htim); - - switch(sBreakInputConfig->Source) - { - case TIM_BREAKINPUTSOURCE_BKIN: - { - bkin_enable_mask = TIM1_OR2_BKINE; - bkin_enable_bitpos = 0; - bkin_polarity_mask = TIM1_OR2_BKINP; - bkin_polarity_bitpos = 9; - } - break; - case TIM_BREAKINPUTSOURCE_COMP1: - { - bkin_enable_mask = TIM1_OR2_BKCMP1E; - bkin_enable_bitpos = 1; - bkin_polarity_mask = TIM1_OR2_BKCMP1P; - bkin_polarity_bitpos = 10; - } - break; - case TIM_BREAKINPUTSOURCE_COMP2: - { - bkin_enable_mask = TIM1_OR2_BKCMP2E; - bkin_enable_bitpos = 2; - bkin_polarity_mask = TIM1_OR2_BKCMP2P; - bkin_polarity_bitpos = 11; - } - break; - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - case TIM_BREAKINPUTSOURCE_DFSDM1: - { - bkin_enable_mask = TIM1_OR2_BKDF1BK0E; - bkin_enable_bitpos = 8; - } - break; -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - - default: - break; - } - - switch(BreakInput) - { - case TIM_BREAKINPUT_BRK: - { - /* Get the TIMx_OR2 register value */ - tmporx = htim->Instance->OR2; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set the break input polarity */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } - - /* Set TIMx_OR2 */ - htim->Instance->OR2 = tmporx; - } - break; - case TIM_BREAKINPUT_BRK2: - { - /* Get the TIMx_OR3 register value */ - tmporx = htim->Instance->OR3; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set the break input polarity */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } - - /* Set TIMx_OR3 */ - htim->Instance->OR3 = tmporx; - } - break; - default: - break; - } - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIMx Remapping input capabilities. - * @param htim TIM handle. - * @param Remap: specifies the TIM remapping source. - * - @if STM32L486xx - * For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4): - * - * field1 can have the following values: - * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog) - * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 - * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 - * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 - * - * field2 can have the following values: - * @arg TIM_TIM1_ETR_ADC3_NONE: TIM1_ETR is not connected to any ADC3 AWD (analog watchdog) - * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 - * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 - * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3 - * - * field3 can have the following values: - * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO - * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output - * - * field4 can have the following values: - * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output - * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output - * @note When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant - @endif - @if STM32L443xx - * For TIM1, the parameter is a combination of 3 fields (field1 | field2 | field3): - * - * field1 can have the following values: - * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog) - * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 - * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 - * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 - * - * field2 can have the following values: - * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO - * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output - * - * field3 can have the following values: - * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output - * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output - * - * @note When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant - * - @endif - @if STM32L486xx - * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3): - * - * field1 can have the following values: - * @arg TIM_TIM2_ITR1_TIM8_TRGO: TIM2_ITR1 is connected to TIM8_TRGO - * @arg TIM_TIM2_ITR1_OTG_FS_SOF: TIM2_ITR1 is connected to OTG_FS SOF - * - * field2 can have the following values: - * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO - * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE - * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output - * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output - * - * field3 can have the following values: - * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO - * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output - * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output - * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output - @endif - @if STM32L443xx - * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3): - * - * field1 can have the following values: - * @arg TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1 - * @arg TIM_TIM2_ITR1_USB_SOF: TIM2_ITR1 is connected to USB SOF - * - * field2 can have the following values: - * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO - * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE - * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output - * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output - * - * field3 can have the following values: - * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO - * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output - * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output - * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output - * - @endif - @if STM32L486xx - * For TIM3, the parameter is a combination 2 fields(field1 | field2): - * - * field1 can have the following values: - * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO - * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output - * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output - * @arg TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output - * - * field2 can have the following values: - * @arg TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO - * @arg TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output - * - @endif - @if STM32L486xx - * For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3): - * - * field1 can have the following values: - * @arg TIM_TIM8_ETR_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD (analog watchdog) - * @arg TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1 - * @arg TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2 - * @arg TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3 - * - * field2 can have the following values: - * @arg TIM_TIM8_ETR_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD (analog watchdog) - * @arg TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1 - * @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2 - * @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3 - * - * field3 can have the following values: - * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO - * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output - * - * field4 can have the following values: - * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output - * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output - * @note When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant - * - @endif - * For TIM15, the parameter is a combination of 3 fields (field1 | field2): - * - * field1 can have the following values: - * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO - * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE - * - * field2 can have the following values: - * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection - * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively - * @arg TIM_TIM15_ENCODERMODE_TIM3: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively - * @arg TIM_TIM15_ENCODERMODE_TIM4: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively - * - @if STM32L486xx - * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO - * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI - * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE - * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt - * - @endif - @if STM32L443xx - * For TIM16, the parameter can have the following values: - * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO - * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI - * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE - * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt - * @arg TIM_TIM16_TI1_MSI: TIM16 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock) - * @arg TIM_TIM16_TI1_HSE_32: TIM16 TI1 is connected to HSE div 32 (note that HSE div 32 must be selected as RTC clock source) - * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO - * - @endif - @if STM32L486xx - * For TIM17, the parameter can have the following values: - * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO - * @arg TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock) - * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32 - * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO - @endif - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) -{ - uint32_t tmpor1 = 0; - uint32_t tmpor2 = 0; - - __HAL_LOCK(htim); - - /* Check parameters */ - assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); - assert_param(IS_TIM_REMAP(Remap)); - - /* Set ETR_SEL bit field (if required) */ - if (IS_TIM_ETRSEL_INSTANCE(htim->Instance)) - { - tmpor2 = htim->Instance->OR2; - tmpor2 &= ~TIMx_ETRSEL_MASK; - tmpor2 |= (Remap & TIMx_ETRSEL_MASK); - - /* Set TIMx_OR2 */ - htim->Instance->OR2 = tmpor2; - } - - /* Set other remapping capabilities */ - tmpor1 = Remap; - tmpor1 &= ~TIMx_ETRSEL_MASK; - - /* Set TIMx_OR1 */ - htim->Instance->OR1 = tmpor1; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Group channel 5 and channel 1, 2 or 3 - * @param htim TIM handle. - * @param Channels specifies the reference signal(s) the OC5REF is combined with. - * This parameter can be any combination of the following values: - * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC - * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF - * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF - * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) -{ - /* Check parameters */ - assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_GROUPCH5(Channels)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Clear GC5Cx bit fields */ - htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1); - - /* Set GC5Cx bit fields */ - htim->Instance->CCR5 |= Channels; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions - * @brief Extended Callbacks functions - * -@verbatim - ============================================================================== - ##### Extended Callbacks functions ##### - ============================================================================== - [..] - This section provides Extended TIM callback functions: - (+) Timer Commutation callback - (+) Timer Break callback - -@endverbatim - * @{ - */ - -/** - * @brief Hall commutation changed callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_CommutationCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Break detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_BreakCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions - * @brief Extended Peripheral State functions - * -@verbatim - ============================================================================== - ##### Extended Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Hall Sensor interface handle state. - * @param htim TIM Hall Sensor handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @} - */ - -/** - * @brief TIM DMA Commutation callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIMEx_CommutationCallback(htim); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param ChannelNState specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. - * @retval None - */ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) -{ - uint32_t tmp = 0; - - tmp = TIM_CCER_CC1NE << Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << Channel); -} - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c deleted file mode 100644 index 8aa955c85..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c +++ /dev/null @@ -1,3448 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_uart.c - * @author MCD Application Team - * @brief UART HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The UART HAL driver can be used as follows: - - (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). - (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: - (++) Enable the USARTx interface clock. - (++) UART pins configuration: - (+++) Enable the clock for the UART GPIOs. - (+++) Configure these UART pins as alternate function pull-up. - (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() - and HAL_UART_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (++) UART interrupts handling: - -@@- The specific UART interrupts (Transmission complete interrupt, - RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) - are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() - inside the transmit and receive processes. - (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() - and HAL_UART_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware - flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. - - (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) - in the huart handle AdvancedInit structure. - - (#) For the UART asynchronous mode, initialize the UART registers by calling - the HAL_UART_Init() API. - - (#) For the UART Half duplex mode, initialize the UART registers by calling - the HAL_HalfDuplex_Init() API. - - (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers - by calling the HAL_LIN_Init() API. - - (#) For the UART Multiprocessor mode, initialize the UART registers - by calling the HAL_MultiProcessor_Init() API. - - (#) For the UART RS485 Driver Enabled mode, initialize the UART registers - by calling the HAL_RS485Ex_Init() API. - - [..] - (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), - also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by - calling the customized HAL_UART_MspInit() API. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup UART UART - * @brief HAL UART module driver - * @{ - */ - -#ifdef HAL_UART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup UART_Private_Constants UART Private Constants - * @{ - */ -#if defined(USART_CR1_FIFOEN) -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ - USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ -#else -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ -#endif - -#if defined(USART_CR1_FIFOEN) -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \ - USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ -#else -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ -#endif - -#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ -#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ - -#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ -#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup UART_Private_Functions - * @{ - */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart); -static void UART_EndRxTransfer(UART_HandleTypeDef *huart); -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAError(DMA_HandleTypeDef *hdma); -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); -static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); -#if defined(USART_CR1_FIFOEN) -static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); -static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); -#endif -static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); -static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); -static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); -#if defined(USART_CR1_FIFOEN) -static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); -static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); -#endif - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in asynchronous mode. - (+) For the asynchronous mode the parameters below can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - (++) Hardware flow control - (++) Receiver/transmitter modes - (++) Over Sampling Method - (++) One-Bit Sampling Method - (+) For the asynchronous mode, the following advanced features can be configured as well: - (++) TX and/or RX pin level inversion - (++) data logical level inversion - (++) RX and TX pins swap - (++) RX overrun detection disabling - (++) DMA disabling on RX error - (++) MSB first on communication line - (++) auto Baud rate detection - [..] - The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API - follow respectively the UART asynchronous, UART Half duplex, UART LIN mode - and UART multiprocessor mode configuration procedures (details for the procedures - are available in reference manual). - -@endverbatim - - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible UART formats are listed in the - following table. - - Table 1. UART frame format. - +-----------------------------------------------------------------------+ - | M1 bit | M0 bit | PCE bit | UART frame | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 0 | | SB | 8 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 0 | | SB | 9 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 0 | | SB | 7 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - +-----------------------------------------------------------------------+ - - * @{ - */ - -/** - * @brief Initialize the UART mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) - { - /* Check the parameters */ - assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); - } - else - { - /* Check the parameters */ - assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); - } - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In asynchronous mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Initialize the half-duplex mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check UART instance */ - assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In half-duplex mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Initialize the LIN mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart UART handle. - * @param BreakDetectLength Specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection - * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check the LIN UART instance */ - assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - /* Check the Break detection length parameter */ - assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - - /* LIN mode limited to 16-bit oversampling only */ - if(huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - return HAL_ERROR; - } - /* LIN mode limited to 8-bit data length */ - if(huart->Init.WordLength != UART_WORDLENGTH_8B) - { - return HAL_ERROR; - } - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In LIN mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); - - /* Set the USART LIN Break detection length. */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Initialize the multiprocessor mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart UART handle. - * @param Address UART node address (4-, 6-, 7- or 8-bit long). - * @param WakeUpMethod Specifies the UART wakeup method. - * This parameter can be one of the following values: - * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection - * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark - * @note If the user resorts to idle line detection wake up, the Address parameter - * is useless and ignored by the initialization function. - * @note If the user resorts to address mark wake up, the address length detection - * is configured by default to 4 bits only. For the UART to be able to - * manage 6-, 7- or 8-bit long addresses detection, the API - * HAL_MultiProcessorEx_AddressLength_Set() must be called after - * HAL_MultiProcessor_Init(). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check the wake up method parameter */ - assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In multiprocessor mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) - { - /* If address mark wake up method is chosen, set the USART address node */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); - } - - /* Set the wake up method by setting the WAKE bit in the CR1 register */ - MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief DeInitialize the UART peripheral. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - huart->Instance->CR1 = 0x0U; - huart->Instance->CR2 = 0x0U; - huart->Instance->CR3 = 0x0U; - - /* DeInit the low level hardware */ - HAL_UART_MspDeInit(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_RESET; - huart->RxState = HAL_UART_STATE_RESET; - - /* Process Unlock */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Initialize the UART MSP. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_MspInit can be implemented in the user file - */ -} - -/** - * @brief DeInitialize the UART MSP. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_MspDeInit can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group2 IO operation functions - * @brief UART Transmit/Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the UART asynchronous - and Half duplex data transfers. - - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected - - (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() - - (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() - - (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() - - (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() - - (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() - - (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. - Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - - -@- In the Half duplex communication, it is forbidden to run the transmit - and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. - -@endverbatim - * @{ - */ - -/** - * @brief Send an amount of data in blocking mode. - * @note When FIFO mode is enabled, writing a data in the TDR register adds one - * data to the TXFIFO. Write operations to the TDR register are performed - * when TXFNF flag is set. From hardware perspective, TXFNF flag and - * TXE are mapped on the same bit-field. - * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp; - uint32_t tickstart = 0U; - - /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - while(huart->TxXferCount > 0U) - { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - tmp = (uint16_t*) pData; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); - pData += 2U; - } - else - { - huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU); - } - huart->TxXferCount--; - } - - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO - * is not empty. Read operations from the RDR register are performed when - * RXFNE flag is set. From hardware perspective, RXFNE flag and - * RXNE are mapped on the same bit-field. - * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp; - uint16_t uhMask; - uint32_t tickstart = 0; - - /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - uhMask = huart->Mask; - - /* as long as data have to be received */ - while(huart->RxXferCount > 0U) - { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - tmp = (uint16_t*) pData ; - *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - pData +=2U; - } - else - { - *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); - } - huart->RxXferCount--; - } - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in interrupt mode. - * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - huart->TxISR = NULL; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - -#if defined(USART_CR1_FIFOEN) - /* Configure Tx interrupt processing */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - /* Set the Tx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->TxISR = UART_TxISR_16BIT_FIFOEN; - } - else - { - huart->TxISR = UART_TxISR_8BIT_FIFOEN; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the TX FIFO threshold interrupt */ - SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - } - else -#endif - { - /* Set the Tx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->TxISR = UART_TxISR_16BIT; - } - else - { - huart->TxISR = UART_TxISR_8BIT; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the Transmit Data Register Empty interrupt */ -#if defined(USART_CR1_FIFOEN) - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); -#else - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); -#endif - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in interrupt mode. - * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - huart->RxXferCount = Size; - huart->RxISR = NULL; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - -#if defined(USART_CR1_FIFOEN) - /* Configure Rx interrupt processing*/ - if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) - { - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->RxISR = UART_RxISR_16BIT_FIFOEN; - } - else - { - huart->RxISR = UART_RxISR_8BIT_FIFOEN; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - } - else -#endif - { - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->RxISR = UART_RxISR_16BIT; - } - else - { - huart->RxISR = UART_RxISR_8BIT; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ -#if defined(USART_CR1_FIFOEN) - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); -#else - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); -#endif - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in DMA mode. - * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Set the UART DMA transfer complete callback */ - huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmatx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmatx->XferAbortCallback = NULL; - - /* Enable the UART transmit DMA channel */ - HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size); - - /* Clear the TC flag in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in DMA mode. - * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Set the UART DMA transfer complete callback */ - huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmarx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pause the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) - { - /* Disable the UART DMA Tx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) - { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Rx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Resume the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - if(huart->gState == HAL_UART_STATE_BUSY_TX) - { - /* Enable the UART DMA Tx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - if(huart->RxState == HAL_UART_STATE_BUSY_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the UART DMA Rx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Stop the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / - HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ - - /* Stop UART DMA Tx request if ongoing */ - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel */ - if(huart->hdmatx != NULL) - { - HAL_DMA_Abort(huart->hdmatx); - } - - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if(huart->hdmarx != NULL) - { - HAL_DMA_Abort(huart->hdmarx); - } - - UART_EndRxTransfer(huart); - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = NULL; - - HAL_DMA_Abort(huart->hdmatx); - } - } - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = NULL; - - HAL_DMA_Abort(huart->hdmarx); - } - } - - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - -#if defined(USART_CR1_FIFOEN) - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } -#endif - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* Reset Handle ErrorCode to No Error */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = NULL; - - HAL_DMA_Abort(huart->hdmatx); - } - } - - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - -#if defined(USART_CR1_FIFOEN) - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } -#endif - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = NULL; - - HAL_DMA_Abort(huart->hdmarx); - } - } - - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) -{ - uint32_t abortcplt = 1U; - - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ - /* DMA Tx Handle is valid */ - if(huart->hdmatx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. - Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; - } - else - { - huart->hdmatx->XferAbortCallback = NULL; - } - } - /* DMA Rx Handle is valid */ - if(huart->hdmarx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. - Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; - } - else - { - huart->hdmarx->XferAbortCallback = NULL; - } - } - - /* Disable the UART DMA Tx request if enabled */ - if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable DMA Tx at UART level */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmatx != NULL) - { - /* UART Tx DMA Abort callback has already been initialised : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) - { - huart->hdmatx->XferAbortCallback = NULL; - } - else - { - abortcplt = 0U; - } - } - } - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmarx != NULL) - { - /* UART Rx DMA Abort callback has already been initialised : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - huart->hdmarx->XferAbortCallback = NULL; - abortcplt = 1U; - } - else - { - abortcplt = 0U; - } - } - } - - /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1U) - { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Clear ISR function pointers */ - huart->RxISR = NULL; - huart->TxISR = NULL; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - -#if defined(USART_CR1_FIFOEN) - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } -#endif - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; - - /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) - { - /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ - huart->hdmatx->XferAbortCallback(huart->hdmatx); - } - } - else - { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - - /* Clear TxISR function pointers */ - huart->TxISR = NULL; - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ - HAL_UART_AbortTransmitCpltCallback(huart); - } - } - else - { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - - /* Clear TxISR function pointers */ - huart->TxISR = NULL; - -#if defined(USART_CR1_FIFOEN) - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } -#endif - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ - HAL_UART_AbortTransmitCpltCallback(huart); - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; - - /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear RxISR function pointer */ - huart->pRxBuffPtr = NULL; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ - HAL_UART_AbortReceiveCpltCallback(huart); - } - } - else - { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear RxISR function pointer */ - huart->pRxBuffPtr = NULL; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ - HAL_UART_AbortReceiveCpltCallback(huart); - } - - return HAL_OK; -} - -/** - * @brief Handle UART interrupt request. - * @param huart UART handle. - * @retval None - */ -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) -{ - uint32_t isrflags = READ_REG(huart->Instance->ISR); - uint32_t cr1its = READ_REG(huart->Instance->CR1); - uint32_t cr3its = READ_REG(huart->Instance->CR3); - uint32_t errorflags; - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); - if (errorflags == RESET) - { - /* UART in mode Receiver ---------------------------------------------------*/ -#if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) -#else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) -#endif - { - if (huart->RxISR != NULL) {huart->RxISR(huart);} - return; - } - } - - /* If some errors occur */ -#if defined(USART_CR1_FIFOEN) - if( (errorflags != RESET) - && ( (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) ) -#else - if( (errorflags != RESET) - && ( ((cr3its & USART_CR3_EIE) != RESET) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) -#endif - { - /* UART parity error interrupt occurred -------------------------------------*/ - if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); - - huart->ErrorCode |= HAL_UART_ERROR_PE; - } - - /* UART frame error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); - - huart->ErrorCode |= HAL_UART_ERROR_FE; - } - - /* UART noise error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); - - huart->ErrorCode |= HAL_UART_ERROR_NE; - } - - /* UART Over-Run interrupt occurred -----------------------------------------*/ -#if defined(USART_CR1_FIFOEN) - if( ((isrflags & USART_ISR_ORE) != RESET) - &&( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || - ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET))) -#else - if( ((isrflags & USART_ISR_ORE) != RESET) - &&( ((cr1its & USART_CR1_RXNEIE) != RESET) || - ((cr3its & USART_CR3_EIE) != RESET))) -#endif - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - - huart->ErrorCode |= HAL_UART_ERROR_ORE; - } - - /* Call UART Error Call back function if need be --------------------------*/ - if(huart->ErrorCode != HAL_UART_ERROR_NONE) - { - /* UART in mode Receiver ---------------------------------------------------*/ -#if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) -#else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) -#endif - { - if (huart->RxISR != NULL) {huart->RxISR(huart);} - } - - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) - { - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ - UART_EndRxTransfer(huart); - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if(huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - - /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Call user error callback */ - HAL_UART_ErrorCallback(huart); - } - } - else - { - /* Call user error callback */ - HAL_UART_ErrorCallback(huart); - } - } - else - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ - HAL_UART_ErrorCallback(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; - } - } - return; - - } /* End if some error occurs */ - - /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ - if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); - /* Set the UART state ready to be able to start again the process */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - HAL_UARTEx_WakeupCallback(huart); - return; - } - - /* UART in mode Transmitter ------------------------------------------------*/ -#if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) - && ( ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) - || ((cr3its & USART_CR3_TXFTIE) != RESET)) ) -#else - if(((isrflags & USART_ISR_TXE) != RESET) - && ((cr1its & USART_CR1_TXEIE) != RESET)) -#endif - { - if (huart->TxISR != NULL) {huart->TxISR(huart);} - return; - } - - /* UART in mode Transmitter (transmission end) -----------------------------*/ - if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) - { - UART_EndTransmit_IT(huart); - return; - } - -#if defined(USART_CR1_FIFOEN) - /* UART TX Fifo Empty occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) - { - HAL_UARTEx_TxFifoEmptyCallback(huart); - return; - } - - /* UART RX Fifo Full occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) - { - HAL_UARTEx_RxFifoFullCallback(huart); - return; - } -#endif -} - -/** - * @brief Tx Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_TxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Tx Half Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_TxHalfCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_RxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Half Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_RxHalfCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART error callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_ErrorCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Receive Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions - * @brief UART control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the UART. - (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode - (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode - (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode - (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode - (+) UART_SetConfig() API configures the UART peripheral - (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features - (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization - (+) UART_Wakeup_AddressConfig() API configures the wake-up from stop mode parameters - (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter - (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver - (+) HAL_LIN_SendBreak() API transmits the break characters -@endverbatim - * @{ - */ - -/** - * @brief Enable UART in mute mode (does not mean UART enters mute mode; - * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Enable USART mute mode by setting the MME bit in the CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_MME); - - huart->gState = HAL_UART_STATE_READY; - - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Disable UART mute mode (does not mean the UART actually exits mute mode - * as it may not have been in mute mode at this very moment). - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable USART mute mode by clearing the MME bit in the CR1 register */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); - - huart->gState = HAL_UART_STATE_READY; - - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Enter UART mute mode (means UART actually enters mute mode). - * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. - * @param huart UART handle. - * @retval None - */ -void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) -{ - __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); -} - -/** - * @brief Enable the UART transmitter and disable the UART receiver. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_TE); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enable the UART receiver and disable the UART transmitter. - * @param huart UART handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_RE); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - - -/** - * @brief Transmit break characters. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Send break characters */ - SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief UART Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Error functions ##### - ============================================================================== - [..] - This subsection provides functions allowing to : - (+) Return the UART handle state. - (+) Return the UART handle error code - -@endverbatim - * @{ - */ - -/** - * @brief Return the UART handle state. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. - * @retval HAL state - */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) -{ - uint32_t temp1= 0x00U, temp2 = 0x00U; - temp1 = huart->gState; - temp2 = huart->RxState; - - return (HAL_UART_StateTypeDef)(temp1 | temp2); -} - -/** -* @brief Return the UART handle error code. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. -* @retval UART Error Code -*/ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) -{ - return huart->ErrorCode; -} -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup UART_Private_Functions UART Private Functions - * @{ - */ - -/** - * @brief Configure the UART peripheral. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg = 0x00000000U; - UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; - uint16_t brrtemp = 0x0000U; - uint32_t usartdiv = 0x00000000U; - HAL_StatusTypeDef ret = HAL_OK; - uint32_t lpuart_ker_ck_pres = 0x00000000U; - - /* Check the parameters */ - assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); - if(UART_INSTANCE_LOWPOWER(huart)) - { - assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); - } - else - { - assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); - assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); - } - - assert_param(IS_UART_PARITY(huart->Init.Parity)); - assert_param(IS_UART_MODE(huart->Init.Mode)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); - assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); -#if defined(USART_PRESC_PRESCALER) - assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); -#endif - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure - * the UART Word Length, Parity, Mode and oversampling: - * set the M bits according to huart->Init.WordLength value - * set PCE and PS bits according to huart->Init.Parity value - * set TE and RE bits according to huart->Init.Mode value - * set OVER8 bit according to huart->Init.OverSampling value */ - tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - - /*-------------------------- USART CR2 Configuration -----------------------*/ - /* Configure the UART Stop Bits: Set STOP[13:12] bits according - * to huart->Init.StopBits value */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure - * - UART HardWare Flow Control: set CTSE and RTSE bits according - * to huart->Init.HwFlowCtl value - * - one-bit sampling method versus three samples' majority rule according - * to huart->Init.OneBitSampling (not applicable to LPUART) - * - set TXFTCFG bit according to huart->Init.TxFifoThreshold value - * - set RXFTCFG bit according to huart->Init.RxFifoThreshold value */ - tmpreg = (uint32_t)huart->Init.HwFlowCtl; - - if (!(UART_INSTANCE_LOWPOWER(huart))) - { - tmpreg |= huart->Init.OneBitSampling; - } - MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - -#if defined(USART_PRESC_PRESCALER) - /*-------------------------- USART PRESC Configuration -----------------------*/ - /* Configure - * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ - MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); -#endif - - /*-------------------------- USART BRR Configuration -----------------------*/ - UART_GETCLOCKSOURCE(huart, clocksource); - - /* Check LPUART instance */ - if(UART_INSTANCE_LOWPOWER(huart)) - { - /* Retrieve frequency clock */ - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: -#if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq()/UARTPrescTable[huart->Init.ClockPrescaler]); -#else - lpuart_ker_ck_pres = HAL_RCC_GetPCLK1Freq(); -#endif - break; - case UART_CLOCKSOURCE_HSI: -#if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE/UARTPrescTable[huart->Init.ClockPrescaler]); -#else - lpuart_ker_ck_pres = (uint32_t)HSI_VALUE; -#endif - break; - case UART_CLOCKSOURCE_SYSCLK: -#if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq()/UARTPrescTable[huart->Init.ClockPrescaler]); -#else - lpuart_ker_ck_pres = HAL_RCC_GetSysClockFreq(); -#endif - break; - case UART_CLOCKSOURCE_LSE: -#if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE/UARTPrescTable[huart->Init.ClockPrescaler]); -#else - lpuart_ker_ck_pres = (uint32_t)LSE_VALUE; -#endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; - } - - /* if proper clock source reported */ - if (lpuart_ker_ck_pres != 0U) - { - /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ - if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || - (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) - { - ret = HAL_ERROR; - } - else - { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_HSI: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_SYSCLK: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_LSE: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; - } - - /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */ - if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) - { - huart->Instance->BRR = usartdiv; - } - else - { - ret = HAL_ERROR; - } - } /* if ( (tmpreg < (3 * huart->Init.BaudRate) ) || (tmpreg > (4096 * huart->Init.BaudRate) )) */ - } /* if (tmpreg != 0) */ - } - /* Check UART Over Sampling to set Baud Rate Register */ - else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_PCLK2: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_HSI: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_SYSCLK: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_LSE: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; - } - - /* USARTDIV must be greater than or equal to 0d16 */ - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - { - brrtemp = usartdiv & 0xFFF0U; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - huart->Instance->BRR = brrtemp; - } - else - { - ret = HAL_ERROR; - } - } - else - { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_PCLK2: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_HSI: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_SYSCLK: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_LSE: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; - } - - /* USARTDIV must be greater than or equal to 0d16 */ - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - { - huart->Instance->BRR = usartdiv; - } - else - { - ret = HAL_ERROR; - } - } - -#if defined(USART_CR1_FIFOEN) - /* Initialize the number of data to process during RX/TX ISR execution */ - huart->NbTxDataToProcess = 1; - huart->NbRxDataToProcess = 1; -#endif - - /* Clear ISR function pointers */ - huart->RxISR = NULL; - huart->TxISR = NULL; - - return ret; -} - -/** - * @brief Configure the UART peripheral advanced features. - * @param huart UART handle. - * @retval None - */ -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) -{ - /* Check whether the set of advanced features to configure is properly set */ - assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); - - /* if required, configure TX pin active level inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - } - - /* if required, configure RX pin active level inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - } - - /* if required, configure data inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - } - - /* if required, configure RX/TX pins swap */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - } - - /* if required, configure RX overrun detection disabling */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - { - assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); - MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - } - - /* if required, configure DMA disabling on reception error */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - { - assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); - MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - } - - /* if required, configure auto Baud rate detection scheme */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - { - assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); - assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - /* set auto Baudrate detection parameters if detection is enabled */ - if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - { - assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - } - } - - /* if required, configure MSB first on communication line */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - { - assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - } -} - -/** - * @brief Check the UART Idle State. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) -{ - uint32_t tickstart = 0U; - - /* Initialize the UART ErrorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - /* Check if the Transmitter is enabled */ - if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } - /* Check if the Receiver is enabled */ - if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } - - /* Initialize the UART State */ - huart->gState= HAL_UART_STATE_READY; - huart->RxState= HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Handle UART Communication Timeout. - * @param huart UART handle. - * @param Flag Specifies the UART flag to check - * @param Status Flag status (SET or RESET) - * @param Tickstart Tick start value - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is set */ - while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); -#endif - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - - -/** - * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; -} - - -/** - * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndRxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Reset RxIsr function pointer */ - huart->RxISR = NULL; -} - - -/** - * @brief DMA UART transmit process complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - - /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) - { - huart->TxXferCount = 0U; - - /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - /* DMA Circular mode */ - else - { - HAL_UART_TxCpltCallback(huart); - } -} - -/** - * @brief DMA UART transmit process half complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - - HAL_UART_TxHalfCpltCallback(huart); -} - -/** - * @brief DMA UART receive process complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - - /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) - { - huart->RxXferCount = 0U; - - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - } - - HAL_UART_RxCpltCallback(huart); -} - -/** - * @brief DMA UART receive process half complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - - HAL_UART_RxHalfCpltCallback(huart); -} - -/** - * @brief DMA UART communication error callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - - /* Stop UART DMA Tx request if ongoing */ - if ( (huart->gState == HAL_UART_STATE_BUSY_TX) - &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) ) - { - huart->TxXferCount = 0U; - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - if ( (huart->RxState == HAL_UART_STATE_BUSY_RX) - &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ) - { - huart->RxXferCount = 0U; - UART_EndRxTransfer(huart); - } - - huart->ErrorCode |= HAL_UART_ERROR_DMA; - HAL_UART_ErrorCallback(huart); -} - -/** - * @brief DMA UART communication abort callback, when initiated by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - huart->RxXferCount = 0U; - huart->TxXferCount = 0U; - - HAL_UART_ErrorCallback(huart); -} - -/** - * @brief DMA UART Tx communication abort callback, when initiated by user - * (To be called at end of DMA Tx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Rx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); - - huart->hdmatx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if(huart->hdmarx != NULL) - { - if(huart->hdmarx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - -#if defined(USART_CR1_FIFOEN) - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } -#endif - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -} - - -/** - * @brief DMA UART Rx communication abort callback, when initiated by user - * (To be called at end of DMA Rx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Tx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); - - huart->hdmarx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if(huart->hdmatx != NULL) - { - if(huart->hdmatx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -} - - -/** - * @brief DMA UART Tx communication abort callback, when initiated by user by a call to - * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) - * (This callback is executed at end of DMA Tx Abort procedure following user abort request, - * and leads to user Tx Abort Complete callback execution). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - - huart->TxXferCount = 0U; - -#if defined(USART_CR1_FIFOEN) - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } -#endif - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -} - -/** - * @brief DMA UART Rx communication abort callback, when initiated by user by a call to - * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) - * (This callback is executed at end of DMA Rx Abort procedure following user abort request, - * and leads to user Rx Abort Complete callback execution). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -} - -/** - * @brief TX interrrupt handler for 7 or 8 bits data word length . - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) -{ - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - if(huart->TxXferCount == 0) - { - /* Disable the UART Transmit Data Register Empty Interrupt */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); -#else - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); -#endif - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - else - { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); - huart->TxXferCount--; - } - } -} - -/** - * @brief TX interrrupt handler for 9 bits data word length. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) -{ - uint16_t* tmp; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - if(huart->TxXferCount == 0) - { - /* Disable the UART Transmit Data Register Empty Interrupt */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); -#else - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); -#endif - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - else - { - tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - huart->pTxBuffPtr += 2; - huart->TxXferCount--; - } - } -} - -#if defined(USART_CR1_FIFOEN) -/** - * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) -{ - uint8_t nb_tx_data; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - for(nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) - { - if(huart->TxXferCount == 0U) - { - /* Disable the TX FIFO threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - break; /* force exit loop */ - } - else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) - { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); - huart->TxXferCount--; - } - } - } -} - -/** - * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) -{ - uint16_t* tmp; - uint8_t nb_tx_data; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - for(nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) - { - if(huart->TxXferCount == 0U) - { - /* Disable the TX FIFO threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - break; /* force exit loop */ - } - else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) - { - tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); - huart->pTxBuffPtr += 2U; - huart->TxXferCount--; - } - } - } -} -#endif - -/** - * @brief Wrap up transmission in non-blocking mode. - * @param huart pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable the UART Transmit Complete Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - /* Tx process is ended, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Cleat TxISR function pointer */ - huart->TxISR = NULL; - - HAL_UART_TxCpltCallback(huart); -} - -/** - * @brief RX interrrupt handler for 7 or 8 bits data word length . - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) -{ - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - - /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); - - if(--huart->RxXferCount == 0) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - HAL_UART_RxCpltCallback(huart); - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} - -/** - * @brief RX interrrupt handler for 9 bits data word length . - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) -{ - uint16_t* tmp; - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - - /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - tmp = (uint16_t*) huart->pRxBuffPtr ; - *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr +=2; - - if(--huart->RxXferCount == 0) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - HAL_UART_RxCpltCallback(huart); - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} - -#if defined(USART_CR1_FIFOEN) -/** - * @brief RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) -{ - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - uint8_t nb_rx_data; - - /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) - { - for(nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); - huart->RxXferCount--; - - if(huart->RxXferCount == 0U) - { - /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - HAL_UART_RxCpltCallback(huart); - } - } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was - disabled (i.e. one interrupt per received frame). - */ - if (((huart->RxXferCount != 0U)) && (huart->RxXferCount < huart->NbRxDataToProcess)) - { - /* Disable the UART RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - - /* Update the RxISR function pointer */ - huart->RxISR = UART_RxISR_8BIT; - - /* Enable the UART Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} - -/** - * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) -{ - uint16_t* tmp; - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - uint8_t nb_rx_data; - - /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) - { - for(nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - tmp = (uint16_t*) huart->pRxBuffPtr ; - *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr +=2; - huart->RxXferCount--; - - if(huart->RxXferCount == 0U) - { - /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - HAL_UART_RxCpltCallback(huart); - } - } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was - disabled (i.e. one interrupt per received frame). - */ - if (((huart->RxXferCount != 0U)) && (huart->RxXferCount < huart->NbRxDataToProcess)) - { - /* Disable the UART RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - - /* Update the RxISR function pointer */ - huart->RxISR = UART_RxISR_16BIT; - - /* Enable the UART Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} -#endif - -/** - * @} - */ - -#endif /* HAL_UART_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c deleted file mode 100644 index 363a37943..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c +++ /dev/null @@ -1,900 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_uart_ex.c - * @author MCD Application Team - * @brief Extended UART HAL module driver. - * This file provides firmware functions to manage the following extended - * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - * - @verbatim - ============================================================================== - ##### UART peripheral extended features ##### - ============================================================================== - - (#) Declare a UART_HandleTypeDef handle structure. - - (#) For the UART RS485 Driver Enable mode, initialize the UART registers - by calling the HAL_RS485Ex_Init() API. - - (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. - - -@- When USART operates in FIFO mode, FIFO mode must be enabled prior - starting RX/TX transfers. Also RX/TX FIFO thresholds must be - configured prior starting RX/TX transfers. - - (#) Slave mode enabling/disabling and NSS pin configuration. - - -@- When USART operates in Slave mode, Slave mode must be enabled prior - starting RX/TX transfers. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup UARTEx UARTEx - * @brief UART Extended HAL module driver - * @{ - */ - -#ifdef HAL_UART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup UARTEx_Private_Functions UARTEx Private Functions - * @{ - */ -static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); -#if defined(USART_CR1_FIFOEN) -static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); -#endif -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions - * @{ - */ - -/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Extended Initialization and Configuration Functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in asynchronous mode. - (+) For the asynchronous mode the parameters below can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - (++) Hardware flow control - (++) Receiver/transmitter modes - (++) Over Sampling Method - (++) One-Bit Sampling Method - (+) For the asynchronous mode, the following advanced features can be configured as well: - (++) TX and/or RX pin level inversion - (++) data logical level inversion - (++) RX and TX pins swap - (++) RX overrun detection disabling - (++) DMA disabling on RX error - (++) MSB first on communication line - (++) auto Baud rate detection - [..] - The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration - procedures (details for the procedures are available in reference manual). - -@endverbatim - - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible UART formats are listed in the - following table. - - Table 1. UART frame format. - +-----------------------------------------------------------------------+ - | M1 bit | M0 bit | PCE bit | UART frame | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 0 | | SB | 8 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 0 | | SB | 9 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 0 | | SB | 7 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - +-----------------------------------------------------------------------+ - - * @{ - */ - -/** - * @brief Initialize the RS485 Driver enable feature according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart UART handle. - * @param Polarity Select the driver enable polarity. - * This parameter can be one of the following values: - * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high - * @arg @ref UART_DE_POLARITY_LOW DE signal is active low - * @param AssertionTime Driver Enable assertion time: - * 5-bit value defining the time between the activation of the DE (Driver Enable) - * signal and the beginning of the start bit. It is expressed in sample time - * units (1/8 or 1/16 bit time, depending on the oversampling rate) - * @param DeassertionTime Driver Enable deassertion time: - * 5-bit value defining the time between the end of the last stop bit, in a - * transmitted message, and the de-activation of the DE (Driver Enable) signal. - * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the - * oversampling rate). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) -{ - uint32_t temp = 0x0; - - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - /* Check the Driver Enable UART instance */ - assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); - - /* Check the Driver Enable polarity */ - assert_param(IS_UART_DE_POLARITY(Polarity)); - - /* Check the Driver Enable assertion time */ - assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); - - /* Check the Driver Enable deassertion time */ - assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, CORTEX */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DEM); - - /* Set the Driver Enable polarity */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); - - /* Set the Driver Enable assertion and deassertion times */ - temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); - temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); - MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @} - */ - -/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions - * @brief Extended functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of Wakeup and FIFO mode related callback functions. - - (#) Wakeup from Stop mode Callback: - (+) HAL_UARTEx_WakeupCallback() - - (#) TX/RX Fifos Callbacks: - (+) HAL_UARTEx_RxFifoFullCallback() - (+) HAL_UARTEx_TxFifoEmptyCallback() - -@endverbatim - * @{ - */ - -/** - * @brief UART wakeup from Stop mode callback. - * @param huart UART handle. - * @retval None - */ - __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_WakeupCallback can be implemented in the user file. - */ -} - -#if defined(USART_CR1_FIFOEN) -/** - * @brief UART RX Fifo full callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. - */ -} - -/** - * @brief UART TX Fifo empty callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. - */ -} -#endif - -/** - * @} - */ - -/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides the following functions: - (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode - (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality - (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address - detection length to more than 4 bits for multiprocessor address mark wake up. - (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode - trigger: address match, Start Bit detection or RXNE bit status. - (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode - (+) HAL_UARTEx_DisableStopMode() API disables the above functionality - (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt - (+) HAL_UARTEx_EnableSPISlaveMode() API enables the SPI slave mode - (+) HAL_UARTEx_DisableSPISlaveMode() API disables the SPI slave mode - (+) HAL_UARTEx_ConfigNSS API configures the Slave Select input pin (NSS) - (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode - (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode - (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold - (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold - -@endverbatim - * @{ - */ - - - - -/** - * @brief By default in multiprocessor mode, when the wake up method is set - * to address mark, the UART handles only 4-bit long addresses detection; - * this API allows to enable longer addresses detection (6-, 7- or 8-bit - * long). - * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, - * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. - * @param huart UART handle. - * @param AddressLength This parameter can be one of the following values: - * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address - * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check the address length parameter */ - assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the address length */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Set Wakeup from Stop mode interrupt flag selection. - * @note It is the application responsibility to enable the interrupt used as - * usart_wkup interrupt source before entering low-power mode. - * @param huart UART handle. - * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. - * This parameter can be one of the following values: - * @arg @ref UART_WAKEUP_ON_ADDRESS - * @arg @ref UART_WAKEUP_ON_STARTBIT - * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart = 0; - - /* check the wake-up from stop mode UART instance */ - assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); - /* check the wake-up selection parameter */ - assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the wake-up selection scheme */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); - - if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) - { - UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); - } - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - status = HAL_TIMEOUT; - } - else - { - /* Initialize the UART State */ - huart->gState = HAL_UART_STATE_READY; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return status; -} - - -/** - * @brief Enable UART Stop Mode. - * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Set UESM bit */ - SET_BIT(huart->Instance->CR1, USART_CR1_UESM); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Disable UART Stop Mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear UESM bit */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -#if defined(USART_CR2_SLVEN) -/** - * @brief Enable the SPI slave mode. - * @note When the UART operates in SPI slave mode, it handles data flow using - * the serial interface clock derived from the external SCLK signal - * provided by the external master SPI device. - * @note In SPI slave mode, the UART must be enabled before starting the master - * communications (or between frames while the clock is stable). Otherwise, - * if the UART slave is enabled while the master is in the middle of a - * frame, it will become desynchronized with the master. - * @note The data register of the slave needs to be ready before the first edge - * of the communication clock or before the end of the ongoing communication, - * otherwise the SPI slave will transmit zeros. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableSlaveMode(UART_HandleTypeDef *huart) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* In SPI slave mode mode, the following bits must be kept cleared: - - LINEN and CLKEN bit in the USART_CR2 register - - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - /* Enable SPI slave mode */ - SET_BIT(huart->Instance->CR2, USART_CR2_SLVEN); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->SlaveMode = UART_SLAVEMODE_ENABLE; - - huart->gState = HAL_UART_STATE_READY; - - /* Enable UART */ - __HAL_UART_ENABLE(huart); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Disable the SPI slave mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableSlaveMode(UART_HandleTypeDef *huart) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Disable SPI slave mode */ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_SLVEN); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->SlaveMode = UART_SLAVEMODE_ENABLE; - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Configure the Slave Select input pin (NSS). - * @note Software NSS management: SPI slave will always be selected and NSS - * input pin will be ignored. - * @note Hardware NSS management: the SPI slave selection depends on NSS - * input pin. The slave is selected when NSS is low and deselected when - * NSS is high. - * @param huart UART handle. - * @param NSSConfig NSS configuration. - * This parameter can be one of the following values: - * @arg @ref UART_NSS_HARD - * @arg @ref UART_NSS_SOFT - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSConfig) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); - assert_param(IS_UART_NSS(NSSConfig)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Program DIS_NSS bit in the USART_CR2 register */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} -#endif - -#if defined(USART_CR1_FIFOEN) -/** - * @brief Enable the FIFO mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Enable FIFO mode */ - SET_BIT(tmpcr1, USART_CR1_FIFOEN); - huart->FifoMode = UART_FIFOMODE_ENABLE; - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - /* Determine the number of data to process during RX/TX ISR execution */ - UARTEx_SetNbDataToProcess(huart); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Disable the FIFO mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Enable FIFO mode */ - CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); - huart->FifoMode = UART_FIFOMODE_DISABLE; - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Set the TXFIFO threshold. - * @param huart UART handle. - * @param Threshold TX FIFO threshold value - * This parameter can be one of the following values: - * @arg @ref UART_TXFIFO_THRESHOLD_1_8 - * @arg @ref UART_TXFIFO_THRESHOLD_1_4 - * @arg @ref UART_TXFIFO_THRESHOLD_1_2 - * @arg @ref UART_TXFIFO_THRESHOLD_3_4 - * @arg @ref UART_TXFIFO_THRESHOLD_7_8 - * @arg @ref UART_TXFIFO_THRESHOLD_8_8 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); - assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Update TX threshold configuration */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); - - /* Determine the number of data to process during RX/TX ISR execution */ - UARTEx_SetNbDataToProcess(huart); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Set the RXFIFO threshold. - * @param huart UART handle. - * @param Threshold RX FIFO threshold value - * This parameter can be one of the following values: - * @arg @ref UART_RXFIFO_THRESHOLD_1_8 - * @arg @ref UART_RXFIFO_THRESHOLD_1_4 - * @arg @ref UART_RXFIFO_THRESHOLD_1_2 - * @arg @ref UART_RXFIFO_THRESHOLD_3_4 - * @arg @ref UART_RXFIFO_THRESHOLD_7_8 - * @arg @ref UART_RXFIFO_THRESHOLD_8_8 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) -{ - uint32_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); - assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Update RX threshold configuration */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); - - /* Determine the number of data to process during RX/TX ISR execution */ - UARTEx_SetNbDataToProcess(huart); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup UARTEx_Private_Functions - * @{ - */ - -/** - * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. - * @param huart UART handle. - * @param WakeUpSelection UART wake up from stop mode parameters. - * @retval None - */ -static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) -{ - assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); - - /* Set the USART address length */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); - - /* Set the USART address node */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); -} - -#if defined(USART_CR1_FIFOEN) -/** - * @brief Calculate the number of data to process in RX/TX ISR. - * @note The RX FIFO depth and the TX FIFO depth is extracted from - * the UART configuration registers. - * @param huart UART handle. - * @retval None - */ -void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) -{ - uint8_t rx_fifo_depth; - uint8_t tx_fifo_depth; - uint8_t rx_fifo_threshold; - uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; - uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; - - if (huart->FifoMode == UART_FIFOMODE_DISABLE) - { - huart->NbTxDataToProcess = 1; - huart->NbRxDataToProcess = 1; - } - else - { - rx_fifo_depth = 8; /* RX Fifo size */ - tx_fifo_depth = 8; /* TX Fifo size */ - rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); - tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - huart->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold])/denominator[tx_fifo_threshold]; - huart->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold])/denominator[rx_fifo_threshold]; - } -} -#endif - -/** - * @} - */ - -#endif /* HAL_UART_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c deleted file mode 100644 index 6c4a08326..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c +++ /dev/null @@ -1,2397 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_ll_usb.c - * @author MCD Application Team - * @brief USB Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization/de-initialization functions - * + I/O operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. - - (#) Call USB_CoreInit() API to initialize the USB Core peripheral. - - (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @defgroup USB_LL USB Low Layer - * @brief Low layer module for USB_FS and USB_OTG_FS drivers - * @{ - */ -#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -/** @addtogroup STM32L4xx_LL_USB_DRIVER - * @{ - */ - - - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -#if defined (USB_OTG_FS) -/** @defgroup USB_LL_Private_Functions USB Low Layer Private Functions - * @{ - */ -static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); -/** - * @} - */ -#endif /* USB_OTG_FS */ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions - * @{ - */ - -/** @defgroup LL_USB_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization/de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ -/*============================================================================== - USB OTG FS peripheral available on STM32L475xx, STM32L476xx, STM32L485xx and - STM32L486xx devices -==============================================================================*/ -#if defined (USB_OTG_FS) -/** - * @brief Initializes the USB Core - * @param USBx: USB Instance - * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(cfg); - - /* Select FS Embedded PHY */ - USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - - /* Reset after a PHY select and set Host mode */ - USB_CoreReset(USBx); - - /* Deactivate the power down*/ - USBx->GCCFG = USB_OTG_GCCFG_PWRDWN; - - return HAL_OK; -} - -/** - * @brief USB_EnableGlobalInt - * Enables the controller's Global Int in the AHB Config reg - * @param USBx: Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) -{ - USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; - return HAL_OK; -} - - -/** - * @brief USB_DisableGlobalInt - * Disable the controller's Global Int in the AHB Config reg - * @param USBx: Selected device - * @retval HAL status -*/ -HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) -{ - USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; - return HAL_OK; -} - -/** - * @brief USB_SetCurrentMode : Set functional mode - * @param USBx: Selected device - * @param mode: current core mode - * This parameter can be one of these values: - * @arg USB_OTG_DEVICE_MODE: Peripheral mode - * @arg USB_OTG_HOST_MODE: Host mode - * @arg USB_OTG_DRD_MODE: Dual Role Device mode - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode) -{ - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); - - if ( mode == USB_HOST_MODE) - { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; - } - else if ( mode == USB_DEVICE_MODE) - { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; - } - HAL_Delay(50); - - return HAL_OK; -} - -/** - * @brief USB_DevInit : Initializes the USB_OTG controller registers - * for device mode - * @param USBx: Selected device - * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - uint32_t index = 0; - - /*Activate VBUS Sensing B */ - USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; - - if (cfg.vbus_sensing_enable == 0) - { - /* Deactivate VBUS Sensing B */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN; - - /* B-peripheral session valid override enable*/ - USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; - USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; - } - - /* Restart the Phy Clock */ - USBx_PCGCCTL = 0; - - /* Device mode configuration */ - USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; - - /* Set Full speed phy */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL); - - /* Flush the FIFOs */ - USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */ - USB_FlushRxFifo(USBx); - - /* Clear all pending Device Interrupts */ - USBx_DEVICE->DIEPMSK = 0; - USBx_DEVICE->DOEPMSK = 0; - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK = 0; - - for (index = 0; index < cfg.dev_endpoints; index++) - { - if ((USBx_INEP(index)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) - { - USBx_INEP(index)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK); - } - else - { - USBx_INEP(index)->DIEPCTL = 0; - } - - USBx_INEP(index)->DIEPTSIZ = 0; - USBx_INEP(index)->DIEPINT = 0xFF; - } - - for (index = 0; index < cfg.dev_endpoints; index++) - { - if ((USBx_OUTEP(index)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) - { - USBx_OUTEP(index)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK); - } - else - { - USBx_OUTEP(index)->DOEPCTL = 0; - } - - USBx_OUTEP(index)->DOEPTSIZ = 0; - USBx_OUTEP(index)->DOEPINT = 0xFF; - } - - USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); - - if (cfg.dma_enable == 1) - { - /*Set threshold parameters */ - USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6); - USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN); - - index= USBx_DEVICE->DTHRCTL; - } - - /* Disable all interrupts. */ - USBx->GINTMSK = 0; - - /* Clear any pending interrupts */ - USBx->GINTSTS = 0xBFFFFFFF; - - /* Enable the common interrupts */ - if (cfg.dma_enable == DISABLE) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } - - /* Enable interrupts matching to the Device mode ONLY */ - USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\ - USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\ - USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\ - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - - if(cfg.Sof_enable) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; - } - - if (cfg.vbus_sensing_enable == ENABLE) - { - USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); - } - - return HAL_OK; -} - - -/** - * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO - * @param USBx: Selected device - * @param num: FIFO number - * This parameter can be a value from 1 to 15 - 15 means Flush all Tx FIFOs - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num) -{ - uint32_t count = 0; - - USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); - - do - { - if (++count > 200000) - { - return HAL_TIMEOUT; - } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); - - return HAL_OK; -} - - -/** - * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx: Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t count = 0; - - USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; - - do - { - if (++count > 200000) - { - return HAL_TIMEOUT; - } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); - - return HAL_OK; -} - -/** - * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register - * depending the PHY type and the enumeration speed of the device. - * @param USBx: Selected device - * @param speed: device speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode - * @retval Hal status - */ -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) -{ - USBx_DEVICE->DCFG |= speed; - return HAL_OK; -} - -/** - * @brief USB_GetDevSpeed :Return the Dev Speed - * @param USBx: Selected device - * @retval speed : device speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode - */ -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) -{ - uint8_t speed = 0; - - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) - { - speed = USB_OTG_SPEED_HIGH; - } - else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)|| - ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ)) - { - speed = USB_OTG_SPEED_FULL; - } - else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) - { - speed = USB_OTG_SPEED_LOW; - } - - return speed; -} - -/** - * @brief Activate and configure an endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - if (ep->is_in == 1) - { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); - - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) - { - USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - } - - } - else - { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); - - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) - { - USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP)); - } - } - return HAL_OK; -} -/** - * @brief Activate and configure a dedicated endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - static __IO uint32_t debug = 0; - - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) - { - USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - } - - - debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); - } - else - { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) - { - USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); - - debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE); - debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL; - debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); - } - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); - } - - return HAL_OK; -} -/** - * @brief De-activate and de-initialize an endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; - } - else - { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; - } - return HAL_OK; -} - -/** - * @brief De-activate and de-initialize a dedicated endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - } - else - { - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - } - return HAL_OK; -} - -/** - * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) -{ - uint16_t pktcnt = 0; - - /* IN endpoint */ - if (ep->is_in == 1) - { - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - if (ep->type == EP_TYPE_ISOC) - { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); - } - } - if (ep->type != EP_TYPE_ISOC) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num; - } - } - - if (ep->type == EP_TYPE_ISOC) - { - if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) - { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; - } - else - { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; - } - } - - /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - - if (ep->type == EP_TYPE_ISOC) - { - USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma); - } - } - else /* OUT endpoint */ - { - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (ep->xfer_len == 0) - { - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; - } - else - { - pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); ; - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); - } - - if (ep->type == EP_TYPE_ISOC) - { - if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) - { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; - } - else - { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; - } - } - /* EP enable */ - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); - } - return HAL_OK; -} - -/** - * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(dma); - - /* IN endpoint */ - if (ep->is_in == 1) - { - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - - if(ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - } - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - } - - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num); - } - - /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - } - else /* OUT endpoint */ - { - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (ep->xfer_len > 0) - { - ep->xfer_len = ep->maxpacket; - } - - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); - - /* EP enable */ - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); - } - return HAL_OK; -} - -/** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated - * with the EP/channel - * @param USBx: Selected device - * @param src: pointer to source buffer - * @param ch_ep_num: endpoint or host channel number - * @param len: Number of bytes to write - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(dma); - - uint32_t count32b= 0 , index= 0; - count32b = (len + 3) / 4; - for (index = 0; index < count32b; index++, src += 4) - { - USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src); - } - return HAL_OK; -} - -/** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated - * with the EP/channel - * @param USBx: Selected device - * @param src: source pointer - * @param ch_ep_num: endpoint or host channel number - * @param len: Number of bytes to read - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval pointer to destination buffer - */ -void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) -{ - uint32_t index=0; - uint32_t count32b = (len + 3) / 4; - - for ( index = 0; index < count32b; index++, dest += 4 ) - { - *(__packed uint32_t *)dest = USBx_DFIFO(0); - - } - return ((void *)dest); -} - -/** - * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) -{ - if (ep->is_in == 1) - { - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0) - { - USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); - } - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; - } - else - { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0) - { - USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); - } - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; - } - return HAL_OK; -} - - -/** - * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - if (ep->is_in == 1) - { - USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) - { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - else - { - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) - { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - return HAL_OK; -} - -/** - * @brief USB_StopDevice : Stop the USB device mode - * @param USBx: Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t index; - - /* Clear Pending interrupt */ - for (index = 0; index < 15 ; index++) - { - USBx_INEP(index)->DIEPINT = 0xFF; - USBx_OUTEP(index)->DOEPINT = 0xFF; - } - USBx_DEVICE->DAINT = 0xFFFFFFFF; - - /* Clear interrupt masks */ - USBx_DEVICE->DIEPMSK = 0; - USBx_DEVICE->DOEPMSK = 0; - USBx_DEVICE->DAINTMSK = 0; - - /* Flush the FIFO */ - USB_FlushRxFifo(USBx); - USB_FlushTxFifo(USBx , 0x10 ); - - return HAL_OK; -} - -/** - * @brief USB_SetDevAddress : Stop the USB device mode - * @param USBx: Selected device - * @param address: new device address to be assigned - * This parameter can be a value from 0 to 255 - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address) -{ - USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD); - USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ; - - return HAL_OK; -} - -/** - * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down - * @param USBx: Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) -{ - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ; - HAL_Delay(3); - - return HAL_OK; -} - -/** - * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx: Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) -{ - USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ; - HAL_Delay(3); - - return HAL_OK; -} - -/** - * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx: Selected device - * @retval HAL status - */ -uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t tmpreg = 0; - - tmpreg = USBx->GINTSTS; - tmpreg &= USBx->GINTMSK; - return tmpreg; -} - -/** - * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx: Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t tmpreg; - tmpreg = USBx_DEVICE->DAINT; - tmpreg &= USBx_DEVICE->DAINTMSK; - return ((tmpreg & 0xffff0000) >> 16); -} - -/** - * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx: Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t tmpreg; - tmpreg = USBx_DEVICE->DAINT; - tmpreg &= USBx_DEVICE->DAINTMSK; - return ((tmpreg & 0xFFFF)); -} - -/** - * @brief Returns Device OUT EP Interrupt register - * @param USBx: Selected device - * @param epnum: endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device OUT EP Interrupt register - */ -uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) -{ - uint32_t tmpreg; - tmpreg = USBx_OUTEP(epnum)->DOEPINT; - tmpreg &= USBx_DEVICE->DOEPMSK; - return tmpreg; -} - -/** - * @brief Returns Device IN EP Interrupt register - * @param USBx: Selected device - * @param epnum: endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device IN EP Interrupt register - */ -uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) -{ - uint32_t tmpreg = 0, msk = 0, emp = 0; - - msk = USBx_DEVICE->DIEPMSK; - emp = USBx_DEVICE->DIEPEMPMSK; - msk |= ((emp >> epnum) & 0x1) << 7; - tmpreg = USBx_INEP(epnum)->DIEPINT & msk; - return tmpreg; -} - -/** - * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx: Selected device - * @param interrupt: interrupt flag - * @retval None - */ -void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) -{ - USBx->GINTSTS |= interrupt; -} - -/** - * @brief Returns USB core mode - * @param USBx: Selected device - * @retval return core mode : Host or Device - * This parameter can be one of these values: - * 0 : Host - * 1 : Device - */ -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) -{ - return ((USBx->GINTSTS ) & 0x1); -} - - -/** - * @brief Activate EP0 for Setup transactions - * @param USBx: Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) -{ - /* Set the MPS of the IN EP based on the enumeration speed */ - USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; - - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) - { - USBx_INEP(0)->DIEPCTL |= 3; - } - USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; - - return HAL_OK; -} - - -/** - * @brief Prepare the EP0 to start the first control setup - * @param USBx: Selected device - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @param psetup: pointer to setup packet - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(psetup); - - USBx_OUTEP(0)->DOEPTSIZ = 0; - USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8); - USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; - - return HAL_OK; -} - -/** - * @brief USB_HostInit : Initializes the USB OTG controller registers - * for Host mode - * @param USBx: Selected device - * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - uint32_t index = 0; - - /* Restart the Phy Clock */ - USBx_PCGCCTL = 0; - - /* Disable the FS/LS support mode only */ - if((cfg.speed == USB_OTG_SPEED_FULL)&& - (USBx != USB_OTG_FS)) - { - USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; - } - else - { - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); - } - - /* Make sure the FIFOs are flushed. */ - USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */ - USB_FlushRxFifo(USBx); - - /* Clear all pending HC Interrupts */ - for (index = 0; index < cfg.Host_channels; index++) - { - USBx_HC(index)->HCINT = 0xFFFFFFFF; - USBx_HC(index)->HCINTMSK = 0; - } - - /* Enable VBUS driving */ - USB_DriveVbus(USBx, 1); - - HAL_Delay(200); - - /* Disable all interrupts. */ - USBx->GINTMSK = 0; - - /* Clear any pending interrupts */ - USBx->GINTSTS = 0xFFFFFFFF; - - /* set Rx FIFO size */ - USBx->GRXFSIZ = (uint32_t )0x80; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80); - USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0); - - /* Enable the common interrupts */ - if (cfg.dma_enable == DISABLE) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } - - /* Enable interrupts matching to the Host mode ONLY */ - USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\ - USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\ - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - - return HAL_OK; -} - -/** - * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the - * HCFG register on the PHY type and set the right frame interval - * @param USBx: Selected device - * @param freq: clock frequency - * This parameter can be one of these values: - * HCFG_48_MHZ : Full Speed 48 MHz Clock - * HCFG_6_MHZ : Low Speed 6 MHz Clock - * @retval HAL status - */ -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq) -{ - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); - USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS); - - if (freq == HCFG_48_MHZ) - { - USBx_HOST->HFIR = (uint32_t)48000; - } - else if (freq == HCFG_6_MHZ) - { - USBx_HOST->HFIR = (uint32_t)6000; - } - return HAL_OK; -} - -/** -* @brief USB_OTG_ResetPort : Reset Host Port - * @param USBx: Selected device - * @retval HAL status - * @note (1)The application must wait at least 10 ms - * before clearing the reset bit. - */ -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) -{ - __IO uint32_t hprt0 = 0; - - hprt0 = USBx_HPRT0; - - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); - HAL_Delay (10); /* See Note #1 */ - USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); - return HAL_OK; -} - -/** - * @brief USB_DriveVbus : activate or de-activate vbus - * @param state: VBUS state - * This parameter can be one of these values: - * 0 : VBUS Active - * 1 : VBUS Inactive - * @retval HAL status -*/ -HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) -{ - __IO uint32_t hprt0 = 0; - - hprt0 = USBx_HPRT0; - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 )) - { - USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); - } - if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 )) - { - USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); - } - return HAL_OK; -} - -/** - * @brief Return Host Core speed - * @param USBx: Selected device - * @retval speed : Host speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode - */ -uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) -{ - __IO uint32_t hprt0 = 0; - - hprt0 = USBx_HPRT0; - return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); -} - -/** - * @brief Return Host Current Frame number - * @param USBx: Selected device - * @retval current frame number -*/ -uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) -{ - return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); -} - -/** - * @brief Initialize a host channel - * @param USBx: Selected device - * @param ch_num : Channel number - * This parameter can be a value from 1 to 15 - * @param epnum: Endpoint number - * This parameter can be a value from 1 to 15 - * @param dev_address: Current device address - * This parameter can be a value from 0 to 255 - * @param speed: Current device speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode - * @param ep_type: Endpoint Type - * This parameter can be one of these values: - * @arg EP_TYPE_CTRL: Control type - * @arg EP_TYPE_ISOC: Isochronous type - * @arg EP_TYPE_BULK: Bulk type - * @arg EP_TYPE_INTR: Interrupt type - * @param mps: Max Packet Size - * This parameter can be a value from 0 to32K - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) -{ - - /* Clear old interrupt conditions for this host channel. */ - USBx_HC(ch_num)->HCINT = 0xFFFFFFFF; - - /* Enable channel interrupts required for this transfer. */ - switch (ep_type) - { - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_STALLM |\ - USB_OTG_HCINTMSK_TXERRM |\ - USB_OTG_HCINTMSK_DTERRM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_NAKM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - } - break; - - case EP_TYPE_INTR: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_STALLM |\ - USB_OTG_HCINTMSK_TXERRM |\ - USB_OTG_HCINTMSK_DTERRM |\ - USB_OTG_HCINTMSK_NAKM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - } - - break; - case EP_TYPE_ISOC: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_ACKM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); - } - break; - } - - /* Enable the top level host channel interrupt. */ - USBx_HOST->HAINTMSK |= (1 << ch_num); - - /* Make sure host channel interrupts are enabled. */ - USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; - - /* Program the HCCHAR register */ - USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\ - (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\ - ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\ - (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\ - ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\ - (mps & USB_OTG_HCCHAR_MPSIZ)); - - if (ep_type == EP_TYPE_INTR) - { - USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; - } - - return HAL_OK; -} - -/** - * @brief Start a transfer over a host channel - * @param USBx: Selected device - * @param hc: pointer to host channel structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL state - */ -#if defined (__CC_ARM) /*!< ARM Compiler */ -#pragma O0 -#elif defined (__GNUC__) /*!< GNU Compiler */ -#pragma GCC optimize ("O0") -#endif /* __CC_ARM */ -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) -{ - uint8_t is_oddframe = 0; - uint16_t len_words = 0; - uint16_t num_packets = 0; - uint16_t max_hc_pkt_count = 256; - uint32_t tmpreg = 0; - - /* Compute the expected number of packets associated to the transfer */ - if (hc->xfer_len > 0) - { - num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet; - - if (num_packets > max_hc_pkt_count) - { - num_packets = max_hc_pkt_count; - hc->xfer_len = num_packets * hc->max_packet; - } - } - else - { - num_packets = 1; - } - if (hc->ep_is_in) - { - hc->xfer_len = num_packets * hc->max_packet; - } - - /* Initialize the HCTSIZn register */ - USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\ - ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID); - - if (dma) - { - /* xfer_buff MUST be 32-bits aligned */ - USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff; - } - - is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1; - USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; - USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29); - - /* Set host channel enable */ - tmpreg = USBx_HC(hc->ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc->ch_num)->HCCHAR = tmpreg; - - if (dma == 0) /* Slave mode */ - { - if((hc->ep_is_in == 0) && (hc->xfer_len > 0)) - { - switch(hc->ep_type) - { - /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - len_words = (hc->xfer_len + 3) / 4; - - /* check if there is enough space in FIFO space */ - if(len_words > (USBx->HNPTXSTS & 0xFFFF)) - { - /* need to process data in nptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; - } - break; - /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - len_words = (hc->xfer_len + 3) / 4; - /* check if there is enough space in FIFO space */ - if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; - } - break; - - default: - break; - } - - /* Write packet into the Tx FIFO. */ - USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0); - } - } - - return HAL_OK; -} - -/** - * @brief Read all host channel interrupts status - * @param USBx: Selected device - * @retval HAL state - */ -uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) -{ - return ((USBx_HOST->HAINT) & 0xFFFF); -} - -/** - * @brief Halt a host channel - * @param USBx: Selected device - * @param hc_num: Host Channel number - * This parameter can be a value from 1 to 15 - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) -{ - uint32_t count = 0; - - /* Check for space in the request queue to issue the halt. */ - if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18))) - { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - - if ((USBx->HNPTXSTS & 0xFFFF) == 0) - { - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; - do - { - if (++count > 1000) - { - break; - } - } - while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - else - { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - } - } - else - { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - - if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0) - { - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; - do - { - if (++count > 1000) - { - break; - } - } - while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - else - { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - } - } - - return HAL_OK; -} - -/** - * @brief Initiate Do Ping protocol - * @param USBx: Selected device - * @param hc_num: Host Channel number - * This parameter can be a value from 1 to 15 - * @retval HAL state - */ -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) -{ - uint8_t num_packets = 1; - uint32_t tmpreg = 0; - - USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - USB_OTG_HCTSIZ_DOPING; - - /* Set host channel enable */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; - - return HAL_OK; -} - -/** - * @brief Stop Host Core - * @param USBx: Selected device - * @retval HAL state - */ -HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) -{ - uint8_t index; - uint32_t count = 0; - uint32_t value = 0; - - USB_DisableGlobalInt(USBx); - - /* Flush FIFO */ - USB_FlushTxFifo(USBx, 0x10); - USB_FlushRxFifo(USBx); - - /* Flush out any leftover queued requests. */ - for (index = 0; index <= 15; index++) - { - value = USBx_HC(index)->HCCHAR; - value |= USB_OTG_HCCHAR_CHDIS; - value &= ~USB_OTG_HCCHAR_CHENA; - value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(index)->HCCHAR = value; - } - - /* Halt all channels to put them into a known state. */ - for (index = 0; index <= 15; index++) - { - value = USBx_HC(index)->HCCHAR ; - value |= USB_OTG_HCCHAR_CHDIS; - value |= USB_OTG_HCCHAR_CHENA; - value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(index)->HCCHAR = value; - - USBx_HC(index)->HCCHAR = value; - do - { - if (++count > 1000) - { - break; - } - } - while ((USBx_HC(index)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - - /* Clear any pending Host interrupts */ - USBx_HOST->HAINT = 0xFFFFFFFF; - USBx->GINTSTS = 0xFFFFFFFF; - USB_EnableGlobalInt(USBx); - return HAL_OK; -} - -/** - * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) -{ - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) - { - /* active Remote wakeup signalling */ - USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; - } - return HAL_OK; -} - -/** - * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) -{ - /* active Remote wakeup signalling */ - USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); - return HAL_OK; -} - -#endif /* USB_OTG_FS */ - -/*============================================================================== - USB Device FS peripheral available on STM32L432xx, STM32L433xx, STM32L442xx) - and STM32L443xx devices -==============================================================================*/ -#if defined (USB) -/** - * @brief Initializes the USB Core - * @param USBx: USB Instance - * @param cfg : pointer to a USB_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(cfg); - - return HAL_OK; -} - -/** - * @brief USB_EnableGlobalInt - * Enables the controller's Global Int in the AHB Config reg - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) -{ - uint32_t winterruptmask = 0; - - /* Set winterruptmask variable */ - winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; - - /* Set interrupt mask */ - USBx->CNTR |= winterruptmask; - - return HAL_OK; -} - -/** - * @brief USB_DisableGlobalInt - * Disable the controller's Global Int in the AHB Config reg - * @param USBx : Selected device - * @retval HAL status -*/ -HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) -{ - uint32_t winterruptmask = 0; - - /* Set winterruptmask variable */ - winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; - - /* Clear interrupt mask */ - USBx->CNTR &= ~winterruptmask; - - return HAL_OK; -} - -/** - * @brief USB_SetCurrentMode : Set functional mode - * @param USBx : Selected device - * @param mode : current core mode - * This parameter can be one of the these values: - * @arg USB_DEVICE_MODE: Peripheral mode mode - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(mode); - - return HAL_OK; -} - -/** - * @brief USB_DevInit : Initializes the USB controller registers - * for device mode - * @param USBx : Selected device - * @param cfg : pointer to a USB_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(cfg); - - /* Init Device */ - /*CNTR_FRES = 1*/ - USBx->CNTR = USB_CNTR_FRES; - - /*CNTR_FRES = 0*/ - USBx->CNTR = 0; - - /*Clear pending interrupts*/ - USBx->ISTR = 0; - - /*Set Btable Address*/ - USBx->BTABLE = BTABLE_ADDRESS; - - return HAL_OK; -} - -/** - * @brief USB_FlushTxFifo : Flush a Tx FIFO - * @param USBx : Selected device - * @param num : FIFO number - * This parameter can be a value from 1 to 15 - 15 means Flush all Tx FIFOs - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(num); - - return HAL_OK; -} - -/** - * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - - return HAL_OK; -} - -/** - * @brief Activate and configure an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) -{ - /* initialize Endpoint */ - switch (ep->type) - { - case EP_TYPE_CTRL: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_CONTROL); - break; - case EP_TYPE_BULK: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_BULK); - break; - case EP_TYPE_INTR: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_INTERRUPT); - break; - case EP_TYPE_ISOC: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_ISOCHRONOUS); - break; - default: - break; - } - - PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); - - if (ep->doublebuffer == 0) - { - if (ep->is_in) - { - /*Set the endpoint Transmit buffer address */ - PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - /* Configure NAK status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - else - { - /*Set the endpoint Receive buffer address */ - PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); - /*Set the endpoint Receive buffer counter*/ - PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); - PCD_CLEAR_RX_DTOG(USBx, ep->num); - /* Configure VALID status for the Endpoint*/ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - } - } - /*Double Buffer*/ - else - { - /*Set the endpoint as double buffered*/ - PCD_SET_EP_DBUF(USBx, ep->num); - /*Set buffer address for double buffered mode*/ - PCD_SET_EP_DBUF_ADDR(USBx, ep->num,ep->pmaaddr0, ep->pmaaddr1); - - if (ep->is_in==0) - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - /* Reset value of the data toggle bits for the endpoint out*/ - PCD_TX_DTOG(USBx, ep->num); - - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - else - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - PCD_RX_DTOG(USBx, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - } - } - - return HAL_OK; -} - -/** - * @brief De-activate and de-initialize an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) -{ - if (ep->doublebuffer == 0) - { - if (ep->is_in) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - else - { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - } - } - /*Double Buffer*/ - else - { - if (ep->is_in==0) - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - /* Reset value of the data toggle bits for the endpoint out*/ - PCD_TX_DTOG(USBx, ep->num); - - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - else - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - PCD_RX_DTOG(USBx, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - } - } - - return HAL_OK; -} - -/** - * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep, uint8_t dma) -{ - uint16_t pmabuffer = 0; - uint32_t len = ep->xfer_len; - - /* IN endpoint */ - if (ep->is_in == 1) - { - /*Multi packet transfer*/ - if (ep->xfer_len > ep->maxpacket) - { - len=ep->maxpacket; - ep->xfer_len-=len; - } - else - { - len=ep->xfer_len; - ep->xfer_len =0; - } - - /* configure and validate Tx endpoint */ - if (ep->doublebuffer == 0) - { - USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, len); - PCD_SET_EP_TX_CNT(USBx, ep->num, len); - } - else - { - /* Write the data to the USB endpoint */ - if (PCD_GET_ENDPOINT(USBx, ep->num)& USB_EP_DTOG_TX) - { - /* Set the Double buffer counter for pmabuffer1 */ - PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr1; - } - else - { - /* Set the Double buffer counter for pmabuffer0 */ - PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr0; - } - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, len); - PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); - } - - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); - } - else /* OUT endpoint */ - { - /* Multi packet transfer*/ - if (ep->xfer_len > ep->maxpacket) - { - len=ep->maxpacket; - ep->xfer_len-=len; - } - else - { - len=ep->xfer_len; - ep->xfer_len =0; - } - - /* configure and validate Rx endpoint */ - if (ep->doublebuffer == 0) - { - /*Set RX buffer count*/ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); - } - else - { - /*Set the Double buffer counter*/ - PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - } - - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - } - - return HAL_OK; -} - -/** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated - * with the EP/channel - * @param USBx : Selected device - * @param src : pointer to source buffer - * @param ch_ep_num : endpoint or host channel number - * @param len : Number of bytes to write - * @retval HAL status - */ -HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(src); - UNUSED(ch_ep_num); - UNUSED(len); - - return HAL_OK; -} - -/** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated - * with the EP/channel - * @param USBx : Selected device - * @param dest : destination pointer - * @param len : Number of bytes to read - * @retval pointer to destination buffer - */ -void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(dest); - UNUSED(len); - - return ((void *)NULL); -} - -/** - * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep) -{ - if (ep->num == 0) - { - /* This macro sets STALL status for RX & TX*/ - PCD_SET_EP_TXRX_STATUS(USBx, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); - } - else - { - if (ep->is_in) - { - PCD_SET_EP_TX_STATUS(USBx, ep->num , USB_EP_TX_STALL); - } - else - { - PCD_SET_EP_RX_STATUS(USBx, ep->num , USB_EP_RX_STALL); - } - } - return HAL_OK; -} - -/** - * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) -{ - if (ep->is_in) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); - } - else - { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - } - return HAL_OK; -} - -/** - * @brief USB_StopDevice : Stop the usb device mode - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) -{ - /* disable all interrupts and force USB reset */ - USBx->CNTR = USB_CNTR_FRES; - - /* clear interrupt status register */ - USBx->ISTR = 0; - - /* switch-off device */ - USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); - - return HAL_OK; -} - -/** - * @brief USB_SetDevAddress : Stop the usb device mode - * @param USBx : Selected device - * @param address : new device address to be assigned - * This parameter can be a value from 0 to 255 - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address) -{ - if(address == 0) - { - /* set device address and enable function */ - USBx->DADDR = USB_DADDR_EF; - } - - return HAL_OK; -} - -/** - * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx) -{ - /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ - USB->BCDR |= USB_BCDR_DPPU; - - return HAL_OK; -} - -/** - * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx) -{ - /* Disable DP Pull-Down bit*/ - USB->BCDR &= ~(USB_BCDR_DPPU); - - return HAL_OK; -} - -/** - * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadInterrupts (USB_TypeDef *USBx) -{ - uint32_t tmpreg = 0; - - tmpreg = USBx->ISTR; - return tmpreg; -} - -/** - * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - - return (0); -} - -/** - * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - - return (0); -} - -/** - * @brief Returns Device OUT EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device OUT EP Interrupt register - */ -uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(epnum); - - return (0); -} - -/** - * @brief Returns Device IN EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device IN EP Interrupt register - */ -uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(epnum); - - return (0); -} - -/** - * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx : Selected device - * @param interrupt : interrupt flag - * @retval None - */ -void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(interrupt); -} - -/** - * @brief Prepare the EP0 to start the first control setup - * @param USBx : Selected device - * @param psetup : pointer to setup packet - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t dma ,uint8_t *psetup) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(psetup); - UNUSED(dma); - - return HAL_OK; -} - -/** - * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) -{ - USBx->CNTR |= USB_CNTR_RESUME; - - return HAL_OK; -} - -/** - * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) -{ - USBx->CNTR &= ~(USB_CNTR_RESUME); - return HAL_OK; -} - -/** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx : pointer to USB register. - * @param pbUsrBuf : pointer to user memory area. - * @param wPMABufAddr : address into PMA. - * @param wNBytes : number of bytes to be copied. - * @retval None - */ -void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) -{ - uint32_t n = (wNBytes + 1) >> 1; - uint32_t i; - uint16_t temp1, temp2; - uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); - - for (i = n; i != 0; i--) - { - temp1 = (uint16_t) * pbUsrBuf; - pbUsrBuf++; - temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; - *pdwVal++ = temp2; - pbUsrBuf++; - } -} - -/** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx : pointer to USB register. -* @param pbUsrBuf : pointer to user memory area. - * @param wPMABufAddr : address into PMA. - * @param wNBytes : number of bytes to be copied. - * @retval None - */ -void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) -{ - uint32_t n = (wNBytes + 1) >> 1; - uint32_t i; - uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); - for (i = n; i != 0; i--) - { - *(uint16_t*)pbUsrBuf++ = *pdwVal++; - pbUsrBuf++; - } -} -#endif /* USB */ -/** - * @} - */ -/** - * @} - */ - -#if defined (USB_OTG_FS) -/** @addtogroup USB_LL_Private_Functions - * @{ - */ -/** - * @brief Reset the USB Core (needed after USB clock settings change) - * @param USBx : Selected device - * @retval HAL status - */ -static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t count = 0; - - /* Wait for AHB master IDLE state. */ - do - { - if (++count > 200000) - { - return HAL_TIMEOUT; - } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0); - - /* Core Soft Reset */ - count = 0; - USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; - - do - { - if (++count > 200000) - { - return HAL_TIMEOUT; - } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); - - return HAL_OK; -} -/** - * @} - */ -#endif /* USB_OTG_FS */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/main.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/main.h deleted file mode 100644 index bc58edc54..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/main.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - ****************************************************************************** - * @file : main.h - * @brief : Header for main.c file. - * This file contains the common defines of the application. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MAIN_H__ -#define __MAIN_H__ - -/* Includes ------------------------------------------------------------------*/ - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private define ------------------------------------------------------------*/ - -#define B1_Pin GPIO_PIN_13 -#define B1_GPIO_Port GPIOC -#define USART_TX_Pin GPIO_PIN_2 -#define USART_TX_GPIO_Port GPIOA -#define USART_RX_Pin GPIO_PIN_3 -#define USART_RX_GPIO_Port GPIOA -#define LD2_Pin GPIO_PIN_5 -#define LD2_GPIO_Port GPIOA -#define TMS_Pin GPIO_PIN_13 -#define TMS_GPIO_Port GPIOA -#define TCK_Pin GPIO_PIN_14 -#define TCK_GPIO_Port GPIOA -#define SWO_Pin GPIO_PIN_3 -#define SWO_GPIO_Port GPIOB - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* USER CODE BEGIN Private defines */ - -/* USER CODE END Private defines */ - -#ifdef __cplusplus - extern "C" { -#endif -void _Error_Handler(char *, int); - -#define Error_Handler() _Error_Handler(__FILE__, __LINE__) -#ifdef __cplusplus -} -#endif - -#endif /* __MAIN_H__ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/stm32l4xx_hal_conf.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/stm32l4xx_hal_conf.h deleted file mode 100644 index ebd1f3195..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/stm32l4xx_hal_conf.h +++ /dev/null @@ -1,430 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_conf.h - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2018 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_CONF_H -#define __STM32L4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "main.h" -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ - -#define HAL_MODULE_ENABLED -/*#define HAL_ADC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_CAN_MODULE_ENABLED */ -/*#define HAL_COMP_MODULE_ENABLED */ -/*#define HAL_CRC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_DAC_MODULE_ENABLED */ -/*#define HAL_DCMI_MODULE_ENABLED */ -/*#define HAL_DMA2D_MODULE_ENABLED */ -/*#define HAL_DFSDM_MODULE_ENABLED */ -/*#define HAL_DSI_MODULE_ENABLED */ -/*#define HAL_FIREWALL_MODULE_ENABLED */ -/*#define HAL_GFXMMU_MODULE_ENABLED */ -/*#define HAL_HCD_MODULE_ENABLED */ -/*#define HAL_HASH_MODULE_ENABLED */ -/*#define HAL_I2S_MODULE_ENABLED */ -/*#define HAL_IRDA_MODULE_ENABLED */ -/*#define HAL_IWDG_MODULE_ENABLED */ -/*#define HAL_LTDC_MODULE_ENABLED */ -/*#define HAL_LCD_MODULE_ENABLED */ -/*#define HAL_LPTIM_MODULE_ENABLED */ -/*#define HAL_NAND_MODULE_ENABLED */ -/*#define HAL_NOR_MODULE_ENABLED */ -/*#define HAL_OPAMP_MODULE_ENABLED */ -/*#define HAL_OSPI_MODULE_ENABLED */ -/*#define HAL_OSPI_MODULE_ENABLED */ -#define HAL_PCD_MODULE_ENABLED -/*#define HAL_QSPI_MODULE_ENABLED */ -/*#define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RNG_MODULE_ENABLED -#define HAL_RTC_MODULE_ENABLED -/*#define HAL_SAI_MODULE_ENABLED */ -/*#define HAL_SD_MODULE_ENABLED */ -/*#define HAL_SMBUS_MODULE_ENABLED */ -/*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ -/*#define HAL_SRAM_MODULE_ENABLED */ -/*#define HAL_SWPMI_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ -/*#define HAL_TSC_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/*#define HAL_USART_MODULE_ENABLED */ -/*#define HAL_WWDG_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_I2C_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED - -/* ########################## Oscillator Values adaptation ####################*/ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal Multiple Speed oscillator (MSI) default value. - * This value is the default MSI range value after Reset. - */ -#if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)48000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. - * This internal oscillator is mainly dedicated to provide a high precision clock to - * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. - * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency - * which is subject to manufacturing process variations. - */ -#if !defined (HSI48_VALUE) - #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. - The real value my vary depending on manufacturing process variations.*/ -#endif /* HSI48_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ - -/** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for SAI1 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source - * frequency. - */ -#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI1 External clock source in Hz*/ -#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ - -/** - * @brief External clock source for SAI2 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source - * frequency. - */ -#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI2 External clock source in Hz*/ -#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ - -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver - * Activated: CRC code is present inside driver - * Deactivated: CRC code cleaned from driver - */ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32l4xx_hal_rcc.h" - #include "stm32l4xx_hal_rcc_ex.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32l4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32l4xx_hal_dma.h" - #include "stm32l4xx_hal_dma_ex.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32l4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32l4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32l4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32l4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32l4xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32l4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32l4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32l4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32l4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32l4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32l4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_FIREWALL_MODULE_ENABLED - #include "stm32l4xx_hal_firewall.h" -#endif /* HAL_FIREWALL_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32l4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32l4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32l4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32l4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32l4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l4xx_hal_lcd.h" -#endif /* HAL_LCD_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32l4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32l4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_OPAMP_MODULE_ENABLED - #include "stm32l4xx_hal_opamp.h" -#endif /* HAL_OPAMP_MODULE_ENABLED */ - -#ifdef HAL_OSPI_MODULE_ENABLED - #include "stm32l4xx_hal_ospi.h" -#endif /* HAL_OSPI_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32l4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32l4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32l4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32l4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32l4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_SWPMI_MODULE_ENABLED - #include "stm32l4xx_hal_swpmi.h" -#endif /* HAL_SWPMI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_TSC_MODULE_ENABLED - #include "stm32l4xx_hal_tsc.h" -#endif /* HAL_TSC_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32l4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32l4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32l4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_GFXMMU_MODULE_ENABLED - #include "stm32l4xx_hal_gfxmmu.h" -#endif /* HAL_GFXMMU_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/stm32l4xx_it.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/stm32l4xx_it.h deleted file mode 100644 index 5c1492527..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/stm32l4xx_it.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_it.h - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * - * COPYRIGHT(c) 2018 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_IT_H -#define __STM32L4xx_IT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" -#include "main.h" -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void SysTick_Handler(void); -void OTG_FS_IRQHandler(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_IT_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/usb_device.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/usb_device.h deleted file mode 100644 index b1ac621b3..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/usb_device.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - ****************************************************************************** - * @file : usb_device.h - * @version : v2.0_Cube - * @brief : Header for usb_device.c file. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_DEVICE__H__ -#define __USB_DEVICE__H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx.h" -#include "stm32l4xx_hal.h" -#include "usbd_def.h" - -/* USER CODE BEGIN INCLUDE */ - void MX_USB_DEVICE_DeInit(void); - -/* USER CODE END INCLUDE */ - -/** @addtogroup USBD_OTG_DRIVER - * @{ - */ - -/** @defgroup USBD_DEVICE USBD_DEVICE - * @brief Device file for Usb otg low level driver. - * @{ - */ - -/** @defgroup USBD_DEVICE_Exported_Variables USBD_DEVICE_Exported_Variables - * @brief Public variables. - * @{ - */ - -/** USB device core handle. */ -extern USBD_HandleTypeDef hUsbDeviceFS; - -/** - * @} - */ - -/** @defgroup USBD_DEVICE_Exported_FunctionsPrototype USBD_DEVICE_Exported_FunctionsPrototype - * @brief Declaration of public functions for Usb device. - * @{ - */ - -/** USB Device initialization function. */ -void MX_USB_DEVICE_Init(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USB_DEVICE__H__ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/usbd_cdc_if.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/usbd_cdc_if.h deleted file mode 100644 index 2a4f7dad4..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/usbd_cdc_if.h +++ /dev/null @@ -1,158 +0,0 @@ -/** - ****************************************************************************** - * @file : usbd_cdc_if.h - * @version : v2.0_Cube - * @brief : Header for usbd_cdc_if.c file. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CDC_IF_H__ -#define __USBD_CDC_IF_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_cdc.h" - -/* USER CODE BEGIN INCLUDE */ - -/* USER CODE END INCLUDE */ - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @brief For Usb device. - * @{ - */ - -/** @defgroup USBD_CDC_IF USBD_CDC_IF - * @brief Usb VCP device module - * @{ - */ - -/** @defgroup USBD_CDC_IF_Exported_Defines USBD_CDC_IF_Exported_Defines - * @brief Defines. - * @{ - */ -/* USER CODE BEGIN EXPORTED_DEFINES */ - -/* USER CODE END EXPORTED_DEFINES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_Types USBD_CDC_IF_Exported_Types - * @brief Types. - * @{ - */ - -/* USER CODE BEGIN EXPORTED_TYPES */ - -/* USER CODE END EXPORTED_TYPES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_Macros USBD_CDC_IF_Exported_Macros - * @brief Aliases. - * @{ - */ - -/* USER CODE BEGIN EXPORTED_MACRO */ - -/* USER CODE END EXPORTED_MACRO */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables - * @brief Public variables. - * @{ - */ - -/** CDC Interface callback. */ -extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; - -/* USER CODE BEGIN EXPORTED_VARIABLES */ - -/* USER CODE END EXPORTED_VARIABLES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_FunctionsPrototype USBD_CDC_IF_Exported_FunctionsPrototype - * @brief Public functions declaration. - * @{ - */ - -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); - -/* USER CODE BEGIN EXPORTED_FUNCTIONS */ - -/* USER CODE END EXPORTED_FUNCTIONS */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_CDC_IF_H__ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/usbd_conf.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/usbd_conf.h deleted file mode 100644 index a884e818a..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/usbd_conf.h +++ /dev/null @@ -1,204 +0,0 @@ -/** - ****************************************************************************** - * @file : usbd_conf.h - * @version : v2.0_Cube - * @brief : Header for usbd_conf.c file. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CONF__H__ -#define __USBD_CONF__H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include -#include -#include -#include "stm32l4xx.h" -#include "stm32l4xx_hal.h" - -/* USER CODE BEGIN INCLUDE */ - -/* USER CODE END INCLUDE */ - -/** @addtogroup USBD_OTG_DRIVER - * @brief Driver for Usb device. - * @{ - */ - -/** @defgroup USBD_CONF USBD_CONF - * @brief Configuration file for Usb otg low level driver. - * @{ - */ - -/** @defgroup USBD_CONF_Exported_Variables USBD_CONF_Exported_Variables - * @brief Public variables. - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CONF_Exported_Defines USBD_CONF_Exported_Defines - * @brief Defines for configuration of the Usb device. - * @{ - */ - -/*---------- -----------*/ -#define USBD_MAX_NUM_INTERFACES 1 -/*---------- -----------*/ -#define USBD_MAX_NUM_CONFIGURATION 1 -/*---------- -----------*/ -#define USBD_MAX_STR_DESC_SIZ 512 -/*---------- -----------*/ -#define USBD_SUPPORT_USER_STRING 0 -/*---------- -----------*/ -#define USBD_DEBUG_LEVEL 0 -/*---------- -----------*/ -#define USBD_LPM_ENABLED 1 -/*---------- -----------*/ -#define USBD_SELF_POWERED 1 - -/****************************************/ -/* #define for FS and HS identification */ -#define DEVICE_FS 0 - -/** - * @} - */ - -/** @defgroup USBD_CONF_Exported_Macros USBD_CONF_Exported_Macros - * @brief Aliases. - * @{ - */ - -/* Memory management macros */ - -/** Alias for memory allocation. */ -#define USBD_malloc (uint32_t *)USBD_static_malloc - -/** Alias for memory release. */ -#define USBD_free USBD_static_free - -/** Alias for memory set. */ -#define USBD_memset /* Not used */ - -/** Alias for memory copy. */ -#define USBD_memcpy /* Not used */ - -/** Alias for delay. */ -#define USBD_Delay HAL_Delay - -/* DEBUG macros */ - -#if (USBD_DEBUG_LEVEL > 0) -#define USBD_UsrLog(...) printf(__VA_ARGS__);\ - printf("\n"); -#else -#define USBD_UsrLog(...) -#endif - -#if (USBD_DEBUG_LEVEL > 1) - -#define USBD_ErrLog(...) printf("ERROR: ") ;\ - printf(__VA_ARGS__);\ - printf("\n"); -#else -#define USBD_ErrLog(...) -#endif - -#if (USBD_DEBUG_LEVEL > 2) -#define USBD_DbgLog(...) printf("DEBUG : ") ;\ - printf(__VA_ARGS__);\ - printf("\n"); -#else -#define USBD_DbgLog(...) -#endif - -/** - * @} - */ - -/** @defgroup USBD_CONF_Exported_Types USBD_CONF_Exported_Types - * @brief Types. - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CONF_Exported_FunctionsPrototype USBD_CONF_Exported_FunctionsPrototype - * @brief Declaration of public functions for Usb device. - * @{ - */ - -/* Exported functions -------------------------------------------------------*/ -void *USBD_static_malloc(uint32_t size); -void USBD_static_free(void *p); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_CONF__H__ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/usbd_desc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/usbd_desc.h deleted file mode 100644 index fb856014f..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Inc/usbd_desc.h +++ /dev/null @@ -1,156 +0,0 @@ -/** - ****************************************************************************** - * @file : usbd_desc.h - * @version : v2.0_Cube - * @brief : Header for usbd_desc.c file. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_DESC__H__ -#define __USBD_DESC__H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - -/* USER CODE BEGIN INCLUDE */ - -/* USER CODE END INCLUDE */ - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_DESC USBD_DESC - * @brief Usb device descriptors module. - * @{ - */ - -/** @defgroup USBD_DESC_Exported_Defines USBD_DESC_Exported_Defines - * @brief Defines. - * @{ - */ - -/* USER CODE BEGIN EXPORTED_DEFINES */ - -/* USER CODE END EXPORTED_DEFINES */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_TypesDefinitions USBD_DESC_Exported_TypesDefinitions - * @brief Types. - * @{ - */ - -/* USER CODE BEGIN EXPORTED_TYPES */ - -/* USER CODE END EXPORTED_TYPES */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_Macros USBD_DESC_Exported_Macros - * @brief Aliases. - * @{ - */ - -/* USER CODE BEGIN EXPORTED_MACRO */ - -/* USER CODE END EXPORTED_MACRO */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_Variables USBD_DESC_Exported_Variables - * @brief Public variables. - * @{ - */ - -/** Descriptor for the Usb device. */ -extern USBD_DescriptorsTypeDef FS_Desc; - -/* USER CODE BEGIN EXPORTED_VARIABLES */ - -/* USER CODE END EXPORTED_VARIABLES */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_FunctionsPrototype USBD_DESC_Exported_FunctionsPrototype - * @brief Public functions declaration. - * @{ - */ - -/* USER CODE BEGIN EXPORTED_FUNCTIONS */ - -/* USER CODE END EXPORTED_FUNCTIONS */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_DESC__H__ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h deleted file mode 100644 index d937b2e81..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h +++ /dev/null @@ -1,179 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_cdc.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief header file for the usbd_cdc.c file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_CDC_H -#define __USB_CDC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup usbd_cdc - * @brief This file is the Header file for usbd_cdc.c - * @{ - */ - - -/** @defgroup usbd_cdc_Exported_Defines - * @{ - */ -#define CDC_IN_EP 0x81 /* EP1 for data IN */ -#define CDC_OUT_EP 0x01 /* EP1 for data OUT */ -#define CDC_CMD_EP 0x82 /* EP2 for CDC commands */ - -/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ -#define CDC_DATA_HS_MAX_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */ -#define CDC_DATA_FS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ -#define CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */ - -#define USB_CDC_CONFIG_DESC_SIZ 67 -#define CDC_DATA_HS_IN_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE -#define CDC_DATA_HS_OUT_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE - -#define CDC_DATA_FS_IN_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE -#define CDC_DATA_FS_OUT_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE - -/*---------------------------------------------------------------------*/ -/* CDC definitions */ -/*---------------------------------------------------------------------*/ -#define CDC_SEND_ENCAPSULATED_COMMAND 0x00 -#define CDC_GET_ENCAPSULATED_RESPONSE 0x01 -#define CDC_SET_COMM_FEATURE 0x02 -#define CDC_GET_COMM_FEATURE 0x03 -#define CDC_CLEAR_COMM_FEATURE 0x04 -#define CDC_SET_LINE_CODING 0x20 -#define CDC_GET_LINE_CODING 0x21 -#define CDC_SET_CONTROL_LINE_STATE 0x22 -#define CDC_SEND_BREAK 0x23 - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ - -/** - * @} - */ -typedef struct -{ - uint32_t bitrate; - uint8_t format; - uint8_t paritytype; - uint8_t datatype; -}USBD_CDC_LineCodingTypeDef; - -typedef struct _USBD_CDC_Itf -{ - int8_t (* Init) (void); - int8_t (* DeInit) (void); - int8_t (* Control) (uint8_t, uint8_t * , uint16_t); - int8_t (* Receive) (uint8_t *, uint32_t *); - -}USBD_CDC_ItfTypeDef; - - -typedef struct -{ - uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4]; /* Force 32bits alignment */ - uint8_t CmdOpCode; - uint8_t CmdLength; - uint8_t *RxBuffer; - uint8_t *TxBuffer; - uint32_t RxLength; - uint32_t TxLength; - - __IO uint32_t TxState; - __IO uint32_t RxState; -} -USBD_CDC_HandleTypeDef; - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern USBD_ClassTypeDef USBD_CDC; -#define USBD_CDC_CLASS &USBD_CDC -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, - USBD_CDC_ItfTypeDef *fops); - -uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff, - uint16_t length); - -uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff); - -uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev); - -uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USB_CDC_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c deleted file mode 100644 index b2ca5f164..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c +++ /dev/null @@ -1,925 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_cdc.c - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief This file provides the high layer firmware functions to manage the - * following functionalities of the USB CDC Class: - * - Initialization and Configuration of high and low layer - * - Enumeration as CDC Device (and enumeration for each implemented memory interface) - * - OUT/IN data transfer - * - Command IN transfer (class requests management) - * - Error management - * - * @verbatim - * - * =================================================================== - * CDC Class Driver Description - * =================================================================== - * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices - * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus - * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007" - * This driver implements the following aspects of the specification: - * - Device descriptor management - * - Configuration descriptor management - * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN) - * - Requests management (as described in section 6.2 in specification) - * - Abstract Control Model compliant - * - Union Functional collection (using 1 IN endpoint for control) - * - Data interface class - * - * These aspects may be enriched or modified for a specific user application. - * - * This driver doesn't implement the following aspects of the specification - * (but it is possible to manage these features with some modifications on this driver): - * - Any class-specific aspect relative to communication classes should be managed by user application. - * - All communication classes other than PSTN are not managed - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_cdc.h" -#include "usbd_desc.h" -#include "usbd_ctlreq.h" - - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_CDC - * @brief usbd core module - * @{ - */ - -/** @defgroup USBD_CDC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_CDC_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_CDC_Private_Macros - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_CDC_Private_FunctionPrototypes - * @{ - */ - - -static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, - uint8_t epnum); - -static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, - uint8_t epnum); - -static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev); - -static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length); - -static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length); - -static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); - -static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); - -uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length); - -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = -{ - USB_LEN_DEV_QUALIFIER_DESC, - USB_DESC_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x01, - 0x00, -}; - -/** - * @} - */ - -/** @defgroup USBD_CDC_Private_Variables - * @{ - */ - - -/* CDC interface class callbacks structure */ -USBD_ClassTypeDef USBD_CDC = -{ - USBD_CDC_Init, - USBD_CDC_DeInit, - USBD_CDC_Setup, - NULL, /* EP0_TxSent, */ - USBD_CDC_EP0_RxReady, - USBD_CDC_DataIn, - USBD_CDC_DataOut, - NULL, - NULL, - NULL, - USBD_CDC_GetHSCfgDesc, - USBD_CDC_GetFSCfgDesc, - USBD_CDC_GetOtherSpeedCfgDesc, - USBD_CDC_GetDeviceQualifierDescriptor, -}; - -/* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ - 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ - - /*---------------------------------------------------------------------------*/ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0x10, /* bInterval: */ - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; - - -/* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ - 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ - - /*---------------------------------------------------------------------------*/ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0x10, /* bInterval: */ - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; - -__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, - USB_CDC_CONFIG_DESC_SIZ, - 0x00, - 0x02, /* bNumInterfaces: 2 interfaces */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT , /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0xFF, /* bInterval: */ - - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00 /* bInterval */ -}; - -/** - * @} - */ - -/** @defgroup USBD_CDC_Private_Functions - * @{ - */ - -/** - * @brief USBD_CDC_Init - * Initialize the CDC interface - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, - uint8_t cfgidx) -{ - uint8_t ret = 0; - USBD_CDC_HandleTypeDef *hcdc; - - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - /* Open EP IN */ - USBD_LL_OpenEP(pdev, - CDC_IN_EP, - USBD_EP_TYPE_BULK, - CDC_DATA_HS_IN_PACKET_SIZE); - - /* Open EP OUT */ - USBD_LL_OpenEP(pdev, - CDC_OUT_EP, - USBD_EP_TYPE_BULK, - CDC_DATA_HS_OUT_PACKET_SIZE); - - } - else - { - /* Open EP IN */ - USBD_LL_OpenEP(pdev, - CDC_IN_EP, - USBD_EP_TYPE_BULK, - CDC_DATA_FS_IN_PACKET_SIZE); - - /* Open EP OUT */ - USBD_LL_OpenEP(pdev, - CDC_OUT_EP, - USBD_EP_TYPE_BULK, - CDC_DATA_FS_OUT_PACKET_SIZE); - } - /* Open Command IN EP */ - USBD_LL_OpenEP(pdev, - CDC_CMD_EP, - USBD_EP_TYPE_INTR, - CDC_CMD_PACKET_SIZE); - - - pdev->pClassData = USBD_malloc(sizeof (USBD_CDC_HandleTypeDef)); - - if(pdev->pClassData == NULL) - { - ret = 1; - } - else - { - hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - /* Init physical Interface components */ - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); - - /* Init Xfer states */ - hcdc->TxState =0; - hcdc->RxState =0; - - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_HS_OUT_PACKET_SIZE); - } - else - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_FS_OUT_PACKET_SIZE); - } - - - } - return ret; -} - -/** - * @brief USBD_CDC_Init - * DeInitialize the CDC layer - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, - uint8_t cfgidx) -{ - uint8_t ret = 0; - - /* Open EP IN */ - USBD_LL_CloseEP(pdev, - CDC_IN_EP); - - /* Open EP OUT */ - USBD_LL_CloseEP(pdev, - CDC_OUT_EP); - - /* Open Command IN EP */ - USBD_LL_CloseEP(pdev, - CDC_CMD_EP); - - - /* DeInit physical Interface components */ - if(pdev->pClassData != NULL) - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); - USBD_free(pdev->pClassData); - pdev->pClassData = NULL; - } - - return ret; -} - -/** - * @brief USBD_CDC_Setup - * Handle the CDC specific requests - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - static uint8_t ifalt = 0; - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - case USB_REQ_TYPE_CLASS : - if (req->wLength) - { - if (req->bmRequest & 0x80) - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, - (uint8_t *)hcdc->data, - req->wLength); - USBD_CtlSendData (pdev, - (uint8_t *)hcdc->data, - req->wLength); - } - else - { - hcdc->CmdOpCode = req->bRequest; - hcdc->CmdLength = req->wLength; - - USBD_CtlPrepareRx (pdev, - (uint8_t *)hcdc->data, - req->wLength); - } - - } - else - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, - (uint8_t*)req, - 0); - } - break; - - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - &ifalt, - 1); - break; - - case USB_REQ_SET_INTERFACE : - break; - } - - default: - break; - } - return USBD_OK; -} - -/** - * @brief USBD_CDC_DataIn - * Data sent on non-control IN endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - if(pdev->pClassData != NULL) - { - - hcdc->TxState = 0; - - return USBD_OK; - } - else - { - return USBD_FAIL; - } -} - -/** - * @brief USBD_CDC_DataOut - * Data received on non-control Out endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - /* Get the received data length */ - hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum); - - /* USB data will be immediately processed, this allow next USB traffic being - NAKed till the end of the application Xfer */ - if(pdev->pClassData != NULL) - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); - - return USBD_OK; - } - else - { - return USBD_FAIL; - } -} - - - -/** - * @brief USBD_CDC_DataOut - * Data received on non-control Out endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - if((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFF)) - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, - (uint8_t *)hcdc->data, - hcdc->CmdLength); - hcdc->CmdOpCode = 0xFF; - - } - return USBD_OK; -} - -/** - * @brief USBD_CDC_GetFSCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) -{ - *length = sizeof (USBD_CDC_CfgFSDesc); - return USBD_CDC_CfgFSDesc; -} - -/** - * @brief USBD_CDC_GetHSCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) -{ - *length = sizeof (USBD_CDC_CfgHSDesc); - return USBD_CDC_CfgHSDesc; -} - -/** - * @brief USBD_CDC_GetCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length) -{ - *length = sizeof (USBD_CDC_OtherSpeedCfgDesc); - return USBD_CDC_OtherSpeedCfgDesc; -} - -/** -* @brief DeviceQualifierDescriptor -* return Device Qualifier descriptor -* @param length : pointer data length -* @retval pointer to descriptor buffer -*/ -uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length) -{ - *length = sizeof (USBD_CDC_DeviceQualifierDesc); - return USBD_CDC_DeviceQualifierDesc; -} - -/** -* @brief USBD_CDC_RegisterInterface - * @param pdev: device instance - * @param fops: CD Interface callback - * @retval status - */ -uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, - USBD_CDC_ItfTypeDef *fops) -{ - uint8_t ret = USBD_FAIL; - - if(fops != NULL) - { - pdev->pUserData= fops; - ret = USBD_OK; - } - - return ret; -} - -/** - * @brief USBD_CDC_SetTxBuffer - * @param pdev: device instance - * @param pbuff: Tx Buffer - * @retval status - */ -uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff, - uint16_t length) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - hcdc->TxBuffer = pbuff; - hcdc->TxLength = length; - - return USBD_OK; -} - - -/** - * @brief USBD_CDC_SetRxBuffer - * @param pdev: device instance - * @param pbuff: Rx Buffer - * @retval status - */ -uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - hcdc->RxBuffer = pbuff; - - return USBD_OK; -} - -/** - * @brief USBD_CDC_DataOut - * Data received on non-control Out endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - if(pdev->pClassData != NULL) - { - if(hcdc->TxState == 0) - { - /* Tx Transfer in progress */ - hcdc->TxState = 1; - - /* Transmit next packet */ - USBD_LL_Transmit(pdev, - CDC_IN_EP, - hcdc->TxBuffer, - hcdc->TxLength); - - return USBD_OK; - } - else - { - return USBD_BUSY; - } - } - else - { - return USBD_FAIL; - } -} - - -/** - * @brief USBD_CDC_ReceivePacket - * prepare OUT Endpoint for reception - * @param pdev: device instance - * @retval status - */ -uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - /* Suspend or Resume USB Out process */ - if(pdev->pClassData != NULL) - { - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_HS_OUT_PACKET_SIZE); - } - else - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_FS_OUT_PACKET_SIZE); - } - return USBD_OK; - } - else - { - return USBD_FAIL; - } -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h deleted file mode 100644 index 013a5c14a..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h +++ /dev/null @@ -1,167 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_core.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief Header file for usbd_core.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CORE_H -#define __USBD_CORE_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_conf.h" -#include "usbd_def.h" -#include "usbd_ioreq.h" -#include "usbd_ctlreq.h" - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_CORE - * @brief This file is the Header file for usbd_core.c file - * @{ - */ - - -/** @defgroup USBD_CORE_Exported_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ -#define USBD_SOF USBD_LL_SOF -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_FunctionsPrototype - * @{ - */ -USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id); -USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass); - -USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); -USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); - -USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup); -USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata); -USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata); - -USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed); -USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev); - -USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); -USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); - -USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev); - -/* USBD Low Level Driver */ -USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_DeInit (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Stop (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_OpenEP (USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_mps); - -USBD_StatusTypeDef USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr); -USBD_StatusTypeDef USBD_LL_Transmit (USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t size); - -USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t size); - -uint32_t USBD_LL_GetRxDataSize (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -void USBD_LL_Delay (uint32_t Delay); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_CORE_H */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h deleted file mode 100644 index bf8825227..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_req.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief Header file for the usbd_req.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_REQUEST_H -#define __USB_REQUEST_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_REQ - * @brief header file for the usbd_req.c file - * @{ - */ - -/** @defgroup USBD_REQ_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Exported_Types - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_REQ_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_REQ_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_REQ_Exported_FunctionsPrototype - * @{ - */ - -USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); - - -void USBD_CtlError (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); - -void USBD_ParseSetupRequest (USBD_SetupReqTypedef *req, uint8_t *pdata); - -void USBD_GetString (uint8_t *desc, uint8_t *unicode, uint16_t *len); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USB_REQUEST_H */ - -/** - * @} - */ - -/** -* @} -*/ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h deleted file mode 100644 index 8fbe81e4a..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h +++ /dev/null @@ -1,330 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_def.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief General defines for the usb device library - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_DEF_H -#define __USBD_DEF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_conf.h" - -/** @addtogroup STM32_USBD_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_DEF - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_DEF_Exported_Defines - * @{ - */ - -#ifndef NULL -#define NULL 0 -#endif - - -#define USB_LEN_DEV_QUALIFIER_DESC 0x0A -#define USB_LEN_DEV_DESC 0x12 -#define USB_LEN_CFG_DESC 0x09 -#define USB_LEN_IF_DESC 0x09 -#define USB_LEN_EP_DESC 0x07 -#define USB_LEN_OTG_DESC 0x03 -#define USB_LEN_LANGID_STR_DESC 0x04 -#define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09 - -#define USBD_IDX_LANGID_STR 0x00 -#define USBD_IDX_MFC_STR 0x01 -#define USBD_IDX_PRODUCT_STR 0x02 -#define USBD_IDX_SERIAL_STR 0x03 -#define USBD_IDX_CONFIG_STR 0x04 -#define USBD_IDX_INTERFACE_STR 0x05 - -#define USB_REQ_TYPE_STANDARD 0x00 -#define USB_REQ_TYPE_CLASS 0x20 -#define USB_REQ_TYPE_VENDOR 0x40 -#define USB_REQ_TYPE_MASK 0x60 - -#define USB_REQ_RECIPIENT_DEVICE 0x00 -#define USB_REQ_RECIPIENT_INTERFACE 0x01 -#define USB_REQ_RECIPIENT_ENDPOINT 0x02 -#define USB_REQ_RECIPIENT_MASK 0x03 - -#define USB_REQ_GET_STATUS 0x00 -#define USB_REQ_CLEAR_FEATURE 0x01 -#define USB_REQ_SET_FEATURE 0x03 -#define USB_REQ_SET_ADDRESS 0x05 -#define USB_REQ_GET_DESCRIPTOR 0x06 -#define USB_REQ_SET_DESCRIPTOR 0x07 -#define USB_REQ_GET_CONFIGURATION 0x08 -#define USB_REQ_SET_CONFIGURATION 0x09 -#define USB_REQ_GET_INTERFACE 0x0A -#define USB_REQ_SET_INTERFACE 0x0B -#define USB_REQ_SYNCH_FRAME 0x0C - -#define USB_DESC_TYPE_DEVICE 1 -#define USB_DESC_TYPE_CONFIGURATION 2 -#define USB_DESC_TYPE_STRING 3 -#define USB_DESC_TYPE_INTERFACE 4 -#define USB_DESC_TYPE_ENDPOINT 5 -#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 -#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 -#define USB_DESC_TYPE_BOS 0x0F - -#define USB_CONFIG_REMOTE_WAKEUP 2 -#define USB_CONFIG_SELF_POWERED 1 - -#define USB_FEATURE_EP_HALT 0 -#define USB_FEATURE_REMOTE_WAKEUP 1 -#define USB_FEATURE_TEST_MODE 2 - -#define USB_DEVICE_CAPABITY_TYPE 0x10 - -#define USB_HS_MAX_PACKET_SIZE 512 -#define USB_FS_MAX_PACKET_SIZE 64 -#define USB_MAX_EP0_SIZE 64 - -/* Device Status */ -#define USBD_STATE_DEFAULT 1 -#define USBD_STATE_ADDRESSED 2 -#define USBD_STATE_CONFIGURED 3 -#define USBD_STATE_SUSPENDED 4 - - -/* EP0 State */ -#define USBD_EP0_IDLE 0 -#define USBD_EP0_SETUP 1 -#define USBD_EP0_DATA_IN 2 -#define USBD_EP0_DATA_OUT 3 -#define USBD_EP0_STATUS_IN 4 -#define USBD_EP0_STATUS_OUT 5 -#define USBD_EP0_STALL 6 - -#define USBD_EP_TYPE_CTRL 0 -#define USBD_EP_TYPE_ISOC 1 -#define USBD_EP_TYPE_BULK 2 -#define USBD_EP_TYPE_INTR 3 - - -/** - * @} - */ - - -/** @defgroup USBD_DEF_Exported_TypesDefinitions - * @{ - */ - -typedef struct usb_setup_req -{ - - uint8_t bmRequest; - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -}USBD_SetupReqTypedef; - -struct _USBD_HandleTypeDef; - -typedef struct _Device_cb -{ - uint8_t (*Init) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx); - uint8_t (*DeInit) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx); - /* Control Endpoints*/ - uint8_t (*Setup) (struct _USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req); - uint8_t (*EP0_TxSent) (struct _USBD_HandleTypeDef *pdev ); - uint8_t (*EP0_RxReady) (struct _USBD_HandleTypeDef *pdev ); - /* Class Specific Endpoints*/ - uint8_t (*DataIn) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); - uint8_t (*DataOut) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); - uint8_t (*SOF) (struct _USBD_HandleTypeDef *pdev); - uint8_t (*IsoINIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); - uint8_t (*IsoOUTIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); - - uint8_t *(*GetHSConfigDescriptor)(uint16_t *length); - uint8_t *(*GetFSConfigDescriptor)(uint16_t *length); - uint8_t *(*GetOtherSpeedConfigDescriptor)(uint16_t *length); - uint8_t *(*GetDeviceQualifierDescriptor)(uint16_t *length); -#if (USBD_SUPPORT_USER_STRING == 1) - uint8_t *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev ,uint8_t index, uint16_t *length); -#endif - -} USBD_ClassTypeDef; - -/* Following USB Device Speed */ -typedef enum -{ - USBD_SPEED_HIGH = 0, - USBD_SPEED_FULL = 1, - USBD_SPEED_LOW = 2, -}USBD_SpeedTypeDef; - -/* Following USB Device status */ -typedef enum { - USBD_OK = 0, - USBD_BUSY, - USBD_FAIL, -}USBD_StatusTypeDef; - -/* USB Device descriptors structure */ -typedef struct -{ - uint8_t *(*GetDeviceDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetLangIDStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetManufacturerStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetProductStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetSerialStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetConfigurationStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetInterfaceStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); -#if (USBD_LPM_ENABLED == 1) - uint8_t *(*GetBOSDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); -#endif -} USBD_DescriptorsTypeDef; - -/* USB Device handle structure */ -typedef struct -{ - uint32_t status; - uint32_t total_length; - uint32_t rem_length; - uint32_t maxpacket; -} USBD_EndpointTypeDef; - -/* USB Device handle structure */ -typedef struct _USBD_HandleTypeDef -{ - uint8_t id; - uint32_t dev_config; - uint32_t dev_default_config; - uint32_t dev_config_status; - USBD_SpeedTypeDef dev_speed; - USBD_EndpointTypeDef ep_in[15]; - USBD_EndpointTypeDef ep_out[15]; - uint32_t ep0_state; - uint32_t ep0_data_len; - uint8_t dev_state; - uint8_t dev_old_state; - uint8_t dev_address; - uint8_t dev_connection_status; - uint8_t dev_test_mode; - uint32_t dev_remote_wakeup; - - USBD_SetupReqTypedef request; - USBD_DescriptorsTypeDef *pDesc; - USBD_ClassTypeDef *pClass; - void *pClassData; - void *pUserData; - void *pData; -} USBD_HandleTypeDef; - -/** - * @} - */ - - - -/** @defgroup USBD_DEF_Exported_Macros - * @{ - */ -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) - -#define LOBYTE(x) ((uint8_t)(x & 0x00FF)) -#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8)) -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) - - -#if defined ( __GNUC__ ) - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ -#endif /* __GNUC__ */ - - -/* In HS mode and when the DMA is used, all variables and data structures dealing - with the DMA during the transaction process should be 4-bytes aligned */ - -#if defined (__GNUC__) /* GNU Compiler */ - #define __ALIGN_END __attribute__ ((aligned (4))) - #define __ALIGN_BEGIN -#else - #define __ALIGN_END - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #elif defined (__TASKING__) /* TASKING Compiler */ - #define __ALIGN_BEGIN __align(4) - #endif /* __CC_ARM */ -#endif /* __GNUC__ */ - - -/** - * @} - */ - -/** @defgroup USBD_DEF_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_DEF_Exported_FunctionsPrototype - * @{ - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_DEF_H */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h deleted file mode 100644 index b476307c5..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h +++ /dev/null @@ -1,128 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_ioreq.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief Header file for the usbd_ioreq.c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_IOREQ_H -#define __USBD_IOREQ_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" -#include "usbd_core.h" - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_IOREQ - * @brief header file for the usbd_ioreq.c file - * @{ - */ - -/** @defgroup USBD_IOREQ_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Exported_Types - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_IOREQ_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_IOREQ_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype - * @{ - */ - -USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, - uint8_t *buf, - uint16_t len); - -USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev); - -USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev); - -uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , - uint8_t epnum); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_IOREQ_H */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c deleted file mode 100644 index 0158829c5..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c +++ /dev/null @@ -1,565 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_core.c - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief This file provides all the USBD core functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" - -/** @addtogroup STM32_USBD_DEVICE_LIBRARY -* @{ -*/ - - -/** @defgroup USBD_CORE -* @brief usbd core module -* @{ -*/ - -/** @defgroup USBD_CORE_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBD_CORE_Private_Defines -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USBD_CORE_Private_Macros -* @{ -*/ -/** -* @} -*/ - - - - -/** @defgroup USBD_CORE_Private_FunctionPrototypes -* @{ -*/ - -/** -* @} -*/ - -/** @defgroup USBD_CORE_Private_Variables -* @{ -*/ - -/** -* @} -*/ - -/** @defgroup USBD_CORE_Private_Functions -* @{ -*/ - -/** -* @brief USBD_Init -* Initializes the device stack and load the class driver -* @param pdev: device instance -* @param pdesc: Descriptor structure address -* @param id: Low level core index -* @retval None -*/ -USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) -{ - /* Check whether the USB Host handle is valid */ - if(pdev == NULL) - { - USBD_ErrLog("Invalid Device handle"); - return USBD_FAIL; - } - - /* Unlink previous class*/ - if(pdev->pClass != NULL) - { - pdev->pClass = NULL; - } - - /* Assign USBD Descriptors */ - if(pdesc != NULL) - { - pdev->pDesc = pdesc; - } - - /* Set Device initial State */ - pdev->dev_state = USBD_STATE_DEFAULT; - pdev->id = id; - /* Initialize low level driver */ - USBD_LL_Init(pdev); - - return USBD_OK; -} - -/** -* @brief USBD_DeInit -* Re-Initialize th device library -* @param pdev: device instance -* @retval status: status -*/ -USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev) -{ - /* Set Default State */ - pdev->dev_state = USBD_STATE_DEFAULT; - - /* Free Class Resources */ - pdev->pClass->DeInit(pdev, pdev->dev_config); - - /* Stop the low level driver */ - USBD_LL_Stop(pdev); - - /* Initialize low level driver */ - USBD_LL_DeInit(pdev); - - return USBD_OK; -} - - -/** - * @brief USBD_RegisterClass - * Link class driver to Device Core. - * @param pDevice : Device Handle - * @param pclass: Class handle - * @retval USBD Status - */ -USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) -{ - USBD_StatusTypeDef status = USBD_OK; - if(pclass != 0) - { - /* link the class to the USB Device handle */ - pdev->pClass = pclass; - status = USBD_OK; - } - else - { - USBD_ErrLog("Invalid Class handle"); - status = USBD_FAIL; - } - - return status; -} - -/** - * @brief USBD_Start - * Start the USB Device Core. - * @param pdev: Device Handle - * @retval USBD Status - */ -USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev) -{ - - /* Start the low level driver */ - USBD_LL_Start(pdev); - - return USBD_OK; -} - -/** - * @brief USBD_Stop - * Stop the USB Device Core. - * @param pdev: Device Handle - * @retval USBD Status - */ -USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev) -{ - /* Free Class Resources */ - pdev->pClass->DeInit(pdev, pdev->dev_config); - - /* Stop the low level driver */ - USBD_LL_Stop(pdev); - - return USBD_OK; -} - -/** -* @brief USBD_RunTestMode -* Launch test mode process -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev) -{ - return USBD_OK; -} - - -/** -* @brief USBD_SetClassConfig -* Configure device and start the interface -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status -*/ - -USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) -{ - USBD_StatusTypeDef ret = USBD_FAIL; - - if(pdev->pClass != NULL) - { - /* Set configuration and Start the Class*/ - if(pdev->pClass->Init(pdev, cfgidx) == 0) - { - ret = USBD_OK; - } - } - return ret; -} - -/** -* @brief USBD_ClrClassConfig -* Clear current configuration -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status: USBD_StatusTypeDef -*/ -USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) -{ - /* Clear configuration and De-initialize the Class process*/ - pdev->pClass->DeInit(pdev, cfgidx); - return USBD_OK; -} - - -/** -* @brief USBD_SetupStage -* Handle the setup stage -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) -{ - - USBD_ParseSetupRequest(&pdev->request, psetup); - - pdev->ep0_state = USBD_EP0_SETUP; - pdev->ep0_data_len = pdev->request.wLength; - - switch (pdev->request.bmRequest & 0x1F) - { - case USB_REQ_RECIPIENT_DEVICE: - USBD_StdDevReq (pdev, &pdev->request); - break; - - case USB_REQ_RECIPIENT_INTERFACE: - USBD_StdItfReq(pdev, &pdev->request); - break; - - case USB_REQ_RECIPIENT_ENDPOINT: - USBD_StdEPReq(pdev, &pdev->request); - break; - - default: - USBD_LL_StallEP(pdev , pdev->request.bmRequest & 0x80); - break; - } - return USBD_OK; -} - -/** -* @brief USBD_DataOutStage -* Handle data OUT stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata) -{ - USBD_EndpointTypeDef *pep; - - if(epnum == 0) - { - pep = &pdev->ep_out[0]; - - if ( pdev->ep0_state == USBD_EP0_DATA_OUT) - { - if(pep->rem_length > pep->maxpacket) - { - pep->rem_length -= pep->maxpacket; - - USBD_CtlContinueRx (pdev, - pdata, - MIN(pep->rem_length ,pep->maxpacket)); - } - else - { - if((pdev->pClass->EP0_RxReady != NULL)&& - (pdev->dev_state == USBD_STATE_CONFIGURED)) - { - pdev->pClass->EP0_RxReady(pdev); - } - USBD_CtlSendStatus(pdev); - } - } - } - else if((pdev->pClass->DataOut != NULL)&& - (pdev->dev_state == USBD_STATE_CONFIGURED)) - { - pdev->pClass->DataOut(pdev, epnum); - } - return USBD_OK; -} - -/** -* @brief USBD_DataInStage -* Handle data in stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev ,uint8_t epnum, uint8_t *pdata) -{ - USBD_EndpointTypeDef *pep; - - if(epnum == 0) - { - pep = &pdev->ep_in[0]; - - if ( pdev->ep0_state == USBD_EP0_DATA_IN) - { - if(pep->rem_length > pep->maxpacket) - { - pep->rem_length -= pep->maxpacket; - - USBD_CtlContinueSendData (pdev, - pdata, - pep->rem_length); - - /* Prepare endpoint for premature end of transfer */ - USBD_LL_PrepareReceive (pdev, - 0, - NULL, - 0); - } - else - { /* last packet is MPS multiple, so send ZLP packet */ - if((pep->total_length % pep->maxpacket == 0) && - (pep->total_length >= pep->maxpacket) && - (pep->total_length < pdev->ep0_data_len )) - { - - USBD_CtlContinueSendData(pdev , NULL, 0); - pdev->ep0_data_len = 0; - - /* Prepare endpoint for premature end of transfer */ - USBD_LL_PrepareReceive (pdev, - 0, - NULL, - 0); - } - else - { - if((pdev->pClass->EP0_TxSent != NULL)&& - (pdev->dev_state == USBD_STATE_CONFIGURED)) - { - pdev->pClass->EP0_TxSent(pdev); - } - USBD_CtlReceiveStatus(pdev); - } - } - } - if (pdev->dev_test_mode == 1) - { - USBD_RunTestMode(pdev); - pdev->dev_test_mode = 0; - } - } - else if((pdev->pClass->DataIn != NULL)&& - (pdev->dev_state == USBD_STATE_CONFIGURED)) - { - pdev->pClass->DataIn(pdev, epnum); - } - return USBD_OK; -} - -/** -* @brief USBD_LL_Reset -* Handle Reset event -* @param pdev: device instance -* @retval status -*/ - -USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) -{ - /* Open EP0 OUT */ - USBD_LL_OpenEP(pdev, - 0x00, - USBD_EP_TYPE_CTRL, - USB_MAX_EP0_SIZE); - - pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; - - /* Open EP0 IN */ - USBD_LL_OpenEP(pdev, - 0x80, - USBD_EP_TYPE_CTRL, - USB_MAX_EP0_SIZE); - - pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; - /* Upon Reset call user call back */ - pdev->dev_state = USBD_STATE_DEFAULT; - - if (pdev->pClassData) - pdev->pClass->DeInit(pdev, pdev->dev_config); - - - return USBD_OK; -} - - - - -/** -* @brief USBD_LL_Reset -* Handle Reset event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) -{ - pdev->dev_speed = speed; - return USBD_OK; -} - -/** -* @brief USBD_Suspend -* Handle Suspend event -* @param pdev: device instance -* @retval status -*/ - -USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) -{ - pdev->dev_old_state = pdev->dev_state; - pdev->dev_state = USBD_STATE_SUSPENDED; - return USBD_OK; -} - -/** -* @brief USBD_Resume -* Handle Resume event -* @param pdev: device instance -* @retval status -*/ - -USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) -{ - pdev->dev_state = pdev->dev_old_state; - return USBD_OK; -} - -/** -* @brief USBD_SOF -* Handle SOF event -* @param pdev: device instance -* @retval status -*/ - -USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) -{ - if(pdev->dev_state == USBD_STATE_CONFIGURED) - { - if(pdev->pClass->SOF != NULL) - { - pdev->pClass->SOF(pdev); - } - } - return USBD_OK; -} - -/** -* @brief USBD_IsoINIncomplete -* Handle iso in incomplete event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - return USBD_OK; -} - -/** -* @brief USBD_IsoOUTIncomplete -* Handle iso out incomplete event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - return USBD_OK; -} - -/** -* @brief USBD_DevConnected -* Handle device connection event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) -{ - return USBD_OK; -} - -/** -* @brief USBD_DevDisconnected -* Handle device disconnection event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) -{ - /* Free Class Resources */ - pdev->dev_state = USBD_STATE_DEFAULT; - pdev->pClass->DeInit(pdev, pdev->dev_config); - - return USBD_OK; -} -/** -* @} -*/ - - -/** -* @} -*/ - - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c deleted file mode 100644 index 49330c667..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c +++ /dev/null @@ -1,782 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_req.c - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief This file provides the standard USB requests following chapter 9. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ctlreq.h" -#include "usbd_ioreq.h" - - -/** @addtogroup STM32_USBD_STATE_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_REQ - * @brief USB standard requests module - * @{ - */ - -/** @defgroup USBD_REQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_FunctionPrototypes - * @{ - */ -static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_SetAddress(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_SetConfig(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_GetConfig(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_GetStatus(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_SetFeature(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_ClrFeature(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static uint8_t USBD_GetLen(uint8_t *buf); - -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Functions - * @{ - */ - - -/** -* @brief USBD_StdDevReq -* Handle standard usb device requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req) -{ - USBD_StatusTypeDef ret = USBD_OK; - - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - - USBD_GetDescriptor (pdev, req) ; - break; - - case USB_REQ_SET_ADDRESS: - USBD_SetAddress(pdev, req); - break; - - case USB_REQ_SET_CONFIGURATION: - USBD_SetConfig (pdev , req); - break; - - case USB_REQ_GET_CONFIGURATION: - USBD_GetConfig (pdev , req); - break; - - case USB_REQ_GET_STATUS: - USBD_GetStatus (pdev , req); - break; - - - case USB_REQ_SET_FEATURE: - USBD_SetFeature (pdev , req); - break; - - case USB_REQ_CLEAR_FEATURE: - USBD_ClrFeature (pdev , req); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - - return ret; -} - -/** -* @brief USBD_StdItfReq -* Handle standard usb interface requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req) -{ - USBD_StatusTypeDef ret = USBD_OK; - - switch (pdev->dev_state) - { - case USBD_STATE_CONFIGURED: - - if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) - { - pdev->pClass->Setup (pdev, req); - - if((req->wLength == 0)&& (ret == USBD_OK)) - { - USBD_CtlSendStatus(pdev); - } - } - else - { - USBD_CtlError(pdev , req); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - return USBD_OK; -} - -/** -* @brief USBD_StdEPReq -* Handle standard usb endpoint requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req) -{ - - uint8_t ep_addr; - USBD_StatusTypeDef ret = USBD_OK; - USBD_EndpointTypeDef *pep; - ep_addr = LOBYTE(req->wIndex); - - /* Check if it is a class request */ - if ((req->bmRequest & 0x60) == 0x20) - { - pdev->pClass->Setup (pdev, req); - - return USBD_OK; - } - - switch (req->bRequest) - { - - case USB_REQ_SET_FEATURE : - - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - USBD_LL_StallEP(pdev , ep_addr); - } - break; - - case USBD_STATE_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - USBD_LL_StallEP(pdev , ep_addr); - - } - } - pdev->pClass->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - case USB_REQ_CLEAR_FEATURE : - - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - USBD_LL_StallEP(pdev , ep_addr); - } - break; - - case USBD_STATE_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr & 0x7F) != 0x00) - { - USBD_LL_ClearStallEP(pdev , ep_addr); - pdev->pClass->Setup (pdev, req); - } - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - case USB_REQ_GET_STATUS: - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if ((ep_addr & 0x7F) != 0x00) - { - USBD_LL_StallEP(pdev , ep_addr); - } - break; - - case USBD_STATE_CONFIGURED: - pep = ((ep_addr & 0x80) == 0x80) ? &pdev->ep_in[ep_addr & 0x7F]:\ - &pdev->ep_out[ep_addr & 0x7F]; - if(USBD_LL_IsStallEP(pdev, ep_addr)) - { - pep->status = 0x0001; - } - else - { - pep->status = 0x0000; - } - - USBD_CtlSendData (pdev, - (uint8_t *)&pep->status, - 2); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - default: - break; - } - return ret; -} -/** -* @brief USBD_GetDescriptor -* Handle Get Descriptor requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - uint16_t len; - uint8_t *pbuf; - - - switch (req->wValue >> 8) - { -#if (USBD_LPM_ENABLED == 1) - case USB_DESC_TYPE_BOS: - pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); - break; -#endif - case USB_DESC_TYPE_DEVICE: - pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); - break; - - case USB_DESC_TYPE_CONFIGURATION: - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - pbuf = (uint8_t *)pdev->pClass->GetHSConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_CONFIGURATION; - } - else - { - pbuf = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_CONFIGURATION; - } - break; - - case USB_DESC_TYPE_STRING: - switch ((uint8_t)(req->wValue)) - { - case USBD_IDX_LANGID_STR: - pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_MFC_STR: - pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_PRODUCT_STR: - pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_SERIAL_STR: - pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_CONFIG_STR: - pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_INTERFACE_STR: - pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); - break; - - default: -#if (USBD_SUPPORT_USER_STRING == 1) - pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue) , &len); - break; -#else - USBD_CtlError(pdev , req); - return; -#endif - } - break; - case USB_DESC_TYPE_DEVICE_QUALIFIER: - - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - pbuf = (uint8_t *)pdev->pClass->GetDeviceQualifierDescriptor(&len); - break; - } - else - { - USBD_CtlError(pdev , req); - return; - } - - case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - pbuf = (uint8_t *)pdev->pClass->GetOtherSpeedConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; - break; - } - else - { - USBD_CtlError(pdev , req); - return; - } - - default: - USBD_CtlError(pdev , req); - return; - } - - if((len != 0)&& (req->wLength != 0)) - { - - len = MIN(len , req->wLength); - - USBD_CtlSendData (pdev, - pbuf, - len); - } - -} - -/** -* @brief USBD_SetAddress -* Set device address -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetAddress(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - uint8_t dev_addr; - - if ((req->wIndex == 0) && (req->wLength == 0)) - { - dev_addr = (uint8_t)(req->wValue) & 0x7F; - - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlError(pdev , req); - } - else - { - pdev->dev_address = dev_addr; - USBD_LL_SetUSBAddress(pdev, dev_addr); - USBD_CtlSendStatus(pdev); - - if (dev_addr != 0) - { - pdev->dev_state = USBD_STATE_ADDRESSED; - } - else - { - pdev->dev_state = USBD_STATE_DEFAULT; - } - } - } - else - { - USBD_CtlError(pdev , req); - } -} - -/** -* @brief USBD_SetConfig -* Handle Set device configuration request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetConfig(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - - if (cfgidx > USBD_MAX_NUM_CONFIGURATION ) - { - USBD_CtlError(pdev , req); - } - else - { - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if (cfgidx) - { - pdev->dev_config = cfgidx; - pdev->dev_state = USBD_STATE_CONFIGURED; - if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL) - { - USBD_CtlError(pdev , req); - return; - } - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - case USBD_STATE_CONFIGURED: - if (cfgidx == 0) - { - pdev->dev_state = USBD_STATE_ADDRESSED; - pdev->dev_config = cfgidx; - USBD_ClrClassConfig(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - - } - else if (cfgidx != pdev->dev_config) - { - /* Clear old configuration */ - USBD_ClrClassConfig(pdev , pdev->dev_config); - - /* set new configuration */ - pdev->dev_config = cfgidx; - if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL) - { - USBD_CtlError(pdev , req); - return; - } - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - } -} - -/** -* @brief USBD_GetConfig -* Handle Get device configuration request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetConfig(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - - if (req->wLength != 1) - { - USBD_CtlError(pdev , req); - } - else - { - switch (pdev->dev_state ) - { - case USBD_STATE_ADDRESSED: - pdev->dev_default_config = 0; - USBD_CtlSendData (pdev, - (uint8_t *)&pdev->dev_default_config, - 1); - break; - - case USBD_STATE_CONFIGURED: - - USBD_CtlSendData (pdev, - (uint8_t *)&pdev->dev_config, - 1); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - } -} - -/** -* @brief USBD_GetStatus -* Handle Get Status request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetStatus(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - - - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - case USBD_STATE_CONFIGURED: - -#if ( USBD_SELF_POWERED == 1) - pdev->dev_config_status = USB_CONFIG_SELF_POWERED; -#else - pdev->dev_config_status = 0; -#endif - - if (pdev->dev_remote_wakeup) - { - pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; - } - - USBD_CtlSendData (pdev, - (uint8_t *)& pdev->dev_config_status, - 2); - break; - - default : - USBD_CtlError(pdev , req); - break; - } -} - - -/** -* @brief USBD_SetFeature -* Handle Set device feature request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetFeature(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - - if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) - { - pdev->dev_remote_wakeup = 1; - pdev->pClass->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - } - -} - - -/** -* @brief USBD_ClrFeature -* Handle clear device feature request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_ClrFeature(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - case USBD_STATE_CONFIGURED: - if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) - { - pdev->dev_remote_wakeup = 0; - pdev->pClass->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - } - break; - - default : - USBD_CtlError(pdev , req); - break; - } -} - -/** -* @brief USBD_ParseSetupRequest -* Copy buffer into setup structure -* @param pdev: device instance -* @param req: usb request -* @retval None -*/ - -void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) -{ - req->bmRequest = *(uint8_t *) (pdata); - req->bRequest = *(uint8_t *) (pdata + 1); - req->wValue = SWAPBYTE (pdata + 2); - req->wIndex = SWAPBYTE (pdata + 4); - req->wLength = SWAPBYTE (pdata + 6); - -} - -/** -* @brief USBD_CtlError -* Handle USB low level Error -* @param pdev: device instance -* @param req: usb request -* @retval None -*/ - -void USBD_CtlError( USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - USBD_LL_StallEP(pdev , 0x80); - USBD_LL_StallEP(pdev , 0); -} - - -/** - * @brief USBD_GetString - * Convert Ascii string into unicode one - * @param desc : descriptor buffer - * @param unicode : Formatted string buffer (unicode) - * @param len : descriptor length - * @retval None - */ -void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) -{ - uint8_t idx = 0; - - if (desc != NULL) - { - *len = USBD_GetLen(desc) * 2 + 2; - unicode[idx++] = *len; - unicode[idx++] = USB_DESC_TYPE_STRING; - - while (*desc != '\0') - { - unicode[idx++] = *desc++; - unicode[idx++] = 0x00; - } - } -} - -/** - * @brief USBD_GetLen - * return the string length - * @param buf : pointer to the ascii string buffer - * @retval string length - */ -static uint8_t USBD_GetLen(uint8_t *buf) -{ - uint8_t len = 0; - - while (*buf != '\0') - { - len++; - buf++; - } - - return len; -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c deleted file mode 100644 index 093afad86..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c +++ /dev/null @@ -1,236 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_ioreq.c - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief This file provides the IO requests APIs for control endpoints. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_IOREQ - * @brief control I/O requests module - * @{ - */ - -/** @defgroup USBD_IOREQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Functions - * @{ - */ - -/** -* @brief USBD_CtlSendData -* send data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be sent -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len) -{ - /* Set EP0 State */ - pdev->ep0_state = USBD_EP0_DATA_IN; - pdev->ep_in[0].total_length = len; - pdev->ep_in[0].rem_length = len; - /* Start the transfer */ - USBD_LL_Transmit (pdev, 0x00, pbuf, len); - - return USBD_OK; -} - -/** -* @brief USBD_CtlContinueSendData -* continue sending data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be sent -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len) -{ - /* Start the next transfer */ - USBD_LL_Transmit (pdev, 0x00, pbuf, len); - - return USBD_OK; -} - -/** -* @brief USBD_CtlPrepareRx -* receive data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be received -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len) -{ - /* Set EP0 State */ - pdev->ep0_state = USBD_EP0_DATA_OUT; - pdev->ep_out[0].total_length = len; - pdev->ep_out[0].rem_length = len; - /* Start the transfer */ - USBD_LL_PrepareReceive (pdev, - 0, - pbuf, - len); - - return USBD_OK; -} - -/** -* @brief USBD_CtlContinueRx -* continue receive data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be received -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len) -{ - - USBD_LL_PrepareReceive (pdev, - 0, - pbuf, - len); - return USBD_OK; -} -/** -* @brief USBD_CtlSendStatus -* send zero lzngth packet on the ctl pipe -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev) -{ - - /* Set EP0 State */ - pdev->ep0_state = USBD_EP0_STATUS_IN; - - /* Start the transfer */ - USBD_LL_Transmit (pdev, 0x00, NULL, 0); - - return USBD_OK; -} - -/** -* @brief USBD_CtlReceiveStatus -* receive zero lzngth packet on the ctl pipe -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev) -{ - /* Set EP0 State */ - pdev->ep0_state = USBD_EP0_STATUS_OUT; - - /* Start the transfer */ - USBD_LL_PrepareReceive ( pdev, - 0, - NULL, - 0); - - return USBD_OK; -} - - -/** -* @brief USBD_GetRxCount -* returns the received data length -* @param pdev: device instance -* @param ep_addr: endpoint address -* @retval Rx Data blength -*/ -uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , uint8_t ep_addr) -{ - return USBD_LL_GetRxDataSize(pdev, ep_addr); -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Nucleo-L476RG.elf.launch b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Nucleo-L476RG.elf.launch deleted file mode 100644 index b2828f8b8..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Nucleo-L476RG.elf.launch +++ /dev/null @@ -1,67 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Nucleo-L476RG.ioc b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Nucleo-L476RG.ioc deleted file mode 100644 index fa582a92f..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Nucleo-L476RG.ioc +++ /dev/null @@ -1,227 +0,0 @@ -#MicroXplorer Configuration settings - do not modify -File.Version=6 -KeepUserPlacement=false -Mcu.Family=STM32L4 -Mcu.IP0=NVIC -Mcu.IP1=RCC -Mcu.IP2=RNG -Mcu.IP3=RTC -Mcu.IP4=SYS -Mcu.IP5=USART2 -Mcu.IP6=USB_DEVICE -Mcu.IP7=USB_OTG_FS -Mcu.IPNb=8 -Mcu.Name=STM32L476R(C-E-G)Tx -Mcu.Package=LQFP64 -Mcu.Pin0=PC13 -Mcu.Pin1=PC14-OSC32_IN (PC14) -Mcu.Pin10=PA13 (JTMS-SWDIO) -Mcu.Pin11=PA14 (JTCK-SWCLK) -Mcu.Pin12=PB3 (JTDO-TRACESWO) -Mcu.Pin13=VP_RNG_VS_RNG -Mcu.Pin14=VP_RTC_VS_RTC_Activate -Mcu.Pin15=VP_RTC_VS_RTC_Calendar -Mcu.Pin16=VP_SYS_VS_Systick -Mcu.Pin17=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS -Mcu.Pin2=PC15-OSC32_OUT (PC15) -Mcu.Pin3=PH0-OSC_IN (PH0) -Mcu.Pin4=PH1-OSC_OUT (PH1) -Mcu.Pin5=PA2 -Mcu.Pin6=PA3 -Mcu.Pin7=PA5 -Mcu.Pin8=PA11 -Mcu.Pin9=PA12 -Mcu.PinsNb=18 -Mcu.ThirdPartyNb=0 -Mcu.UserConstants= -Mcu.UserName=STM32L476RGTx -MxCube.Version=4.25.0 -MxDb.Version=DB.4.0.250 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:false\:false -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:false\:false -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:false -NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:false -PA11.Mode=Device_Only -PA11.Signal=USB_OTG_FS_DM -PA12.Mode=Device_Only -PA12.Signal=USB_OTG_FS_DP -PA13\ (JTMS-SWDIO).GPIOParameters=GPIO_Label -PA13\ (JTMS-SWDIO).GPIO_Label=TMS -PA13\ (JTMS-SWDIO).Locked=true -PA13\ (JTMS-SWDIO).Mode=Trace_Asynchronous_SW -PA13\ (JTMS-SWDIO).Signal=SYS_JTMS-SWDIO -PA14\ (JTCK-SWCLK).GPIOParameters=GPIO_Label -PA14\ (JTCK-SWCLK).GPIO_Label=TCK -PA14\ (JTCK-SWCLK).Locked=true -PA14\ (JTCK-SWCLK).Mode=Trace_Asynchronous_SW -PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK -PA2.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode -PA2.GPIO_Label=USART_TX -PA2.GPIO_Mode=GPIO_MODE_AF_PP -PA2.GPIO_PuPd=GPIO_NOPULL -PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PA2.Locked=true -PA2.Mode=Asynchronous -PA2.Signal=USART2_TX -PA3.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode -PA3.GPIO_Label=USART_RX -PA3.GPIO_Mode=GPIO_MODE_AF_PP -PA3.GPIO_PuPd=GPIO_NOPULL -PA3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH -PA3.Locked=true -PA3.Mode=Asynchronous -PA3.Signal=USART2_RX -PA5.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP -PA5.GPIO_Label=LD2 [green Led] -PA5.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_PP -PA5.GPIO_PuPd=GPIO_NOPULL -PA5.GPIO_Speed=GPIO_SPEED_FREQ_LOW -PA5.Locked=true -PA5.Signal=GPIO_Output -PB3\ (JTDO-TRACESWO).GPIOParameters=GPIO_Label -PB3\ (JTDO-TRACESWO).GPIO_Label=SWO -PB3\ (JTDO-TRACESWO).Locked=true -PB3\ (JTDO-TRACESWO).Mode=Trace_Asynchronous_SW -PB3\ (JTDO-TRACESWO).Signal=SYS_JTDO-SWO -PC13.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI -PC13.GPIO_Label=B1 [Blue PushButton] -PC13.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING -PC13.GPIO_PuPd=GPIO_NOPULL -PC13.Locked=true -PC13.Signal=GPXTI13 -PC14-OSC32_IN\ (PC14).Locked=true -PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator -PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN -PC15-OSC32_OUT\ (PC15).Locked=true -PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator -PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT -PCC.Checker=true -PCC.Line=STM32L4x6 -PCC.MCU=STM32L476R(C-E-G)Tx -PCC.PartNumber=STM32L476RGTx -PCC.Seq0=0 -PCC.Series=STM32L4 -PCC.Temperature=25 -PCC.Vdd=3.0 -PH0-OSC_IN\ (PH0).Locked=true -PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN -PH1-OSC_OUT\ (PH1).Locked=true -PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT -PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=true -ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=3 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=false -ProjectManager.CustomerFirmwarePackage=C\:/Users/Stefanth/STM32Cube/Repository/STM32Cube_FW_L4_V1.11.0 -ProjectManager.DefaultFWLocation=true -ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32L476RGTx -ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.11.0 -ProjectManager.FreePins=false -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x200 -ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=1 -ProjectManager.MainLocation=Src -ProjectManager.PreviousToolchain=TrueSTUDIO -ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=Nucleo-L476RG.ioc -ProjectManager.ProjectName=Nucleo-L476RG -ProjectManager.StackSize=0xf000 -ProjectManager.TargetToolchain=TrueSTUDIO -ProjectManager.ToolChainLocation= -ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-true,3-MX_RNG_Init-RNG-false-HAL-true,4-MX_RTC_Init-RTC-false-HAL-true,5-MX_USART2_UART_Init-USART2-false-HAL-true,6-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-true -RCC.ADCFreq_Value=64000000 -RCC.AHBFreq_Value=80000000 -RCC.APB1Freq_Value=80000000 -RCC.APB1TimFreq_Value=80000000 -RCC.APB2Freq_Value=80000000 -RCC.APB2TimFreq_Value=80000000 -RCC.CK48CLockSelection=RCC_USBCLKSOURCE_MSI -RCC.CortexFreq_Value=80000000 -RCC.DFSDMFreq_Value=80000000 -RCC.FCLKCortexFreq_Value=80000000 -RCC.FamilyName=M -RCC.HCLKFreq_Value=80000000 -RCC.HSE_VALUE=8000000 -RCC.HSI_VALUE=16000000 -RCC.I2C1Freq_Value=80000000 -RCC.I2C2Freq_Value=80000000 -RCC.I2C3Freq_Value=80000000 -RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CK48CLockSelection,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,LCDFreq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSIClockRange,MSI_VALUE,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PREFETCH_ENABLE,PWRFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value -RCC.LCDFreq_Value=32768 -RCC.LPTIM1Freq_Value=80000000 -RCC.LPTIM2Freq_Value=80000000 -RCC.LPUART1Freq_Value=80000000 -RCC.LSCOPinFreq_Value=32000 -RCC.LSI_VALUE=32000 -RCC.MCO1PinFreq_Value=80000000 -RCC.MSIClockRange=RCC_MSIRANGE_11 -RCC.MSI_VALUE=48000000 -RCC.PLLN=10 -RCC.PLLPoutputFreq_Value=22857142.85714286 -RCC.PLLQoutputFreq_Value=80000000 -RCC.PLLRCLKFreq_Value=80000000 -RCC.PLLSAI1PoutputFreq_Value=18285714.285714287 -RCC.PLLSAI1QoutputFreq_Value=64000000 -RCC.PLLSAI1RoutputFreq_Value=64000000 -RCC.PLLSAI2PoutputFreq_Value=18285714.285714287 -RCC.PLLSAI2RoutputFreq_Value=64000000 -RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSI -RCC.PREFETCH_ENABLE=1 -RCC.PWRFreq_Value=80000000 -RCC.RNGFreq_Value=48000000 -RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE -RCC.RTCFreq_Value=32768 -RCC.SAI1Freq_Value=18285714.285714287 -RCC.SAI2Freq_Value=18285714.285714287 -RCC.SDMMCFreq_Value=48000000 -RCC.SWPMI1Freq_Value=80000000 -RCC.SYSCLKFreq_VALUE=80000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.UART4Freq_Value=80000000 -RCC.UART5Freq_Value=80000000 -RCC.USART1Freq_Value=80000000 -RCC.USART2Freq_Value=80000000 -RCC.USART3Freq_Value=80000000 -RCC.USBFreq_Value=48000000 -RCC.VCOInputFreq_Value=16000000 -RCC.VCOOutputFreq_Value=160000000 -RCC.VCOSAI1OutputFreq_Value=128000000 -RCC.VCOSAI2OutputFreq_Value=128000000 -RTC.Format=RTC_FORMAT_BIN -RTC.IPParameters=Format -SH.GPXTI13.0=GPIO_EXTI13 -SH.GPXTI13.ConfNb=1 -USART2.IPParameters=VirtualMode-Asynchronous,Mode,WordLength -USART2.Mode=MODE_TX -USART2.VirtualMode-Asynchronous=VM_ASYNC -USART2.WordLength=WORDLENGTH_8B -USB_DEVICE.CLASS_NAME_FS=CDC -USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS -USB_DEVICE.VirtualMode=Cdc -USB_DEVICE.VirtualModeFS=Cdc_FS -USB_OTG_FS.IPParameters=VirtualMode -USB_OTG_FS.VirtualMode=Device_Only -VP_RNG_VS_RNG.Mode=RNG_Activate -VP_RNG_VS_RNG.Signal=RNG_VS_RNG -VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled -VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate -VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar -VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar -VP_SYS_VS_Systick.Mode=SysTick -VP_SYS_VS_Systick.Signal=SYS_VS_Systick -VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Mode=CDC_FS -VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_FS -board=NUCLEO-L476RG -boardIOC=true diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Nucleo-L476RG.pdf b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Nucleo-L476RG.pdf deleted file mode 100644 index 4e56c3045d7f85381774793b7377e6c29b2b5cb2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 249470 zcmeFYWmp|+(kR*l2m}r8uEE_c!6CSNumoGUOOOPDyCi6WySuvvx8Ux<-A^Zb&wR7z zJag|o^PPL|`7vuf&02K#TdS(x@~Wm%6q8_NW#T}fT3s6+N8li3A+<5GAQcc`mN2(+ zG__}zurhQs6*D!qF)?L+ZEF3_(TtRnn?p#*!O`B-5Q5;EoT8@Zkj{eXwWTpHc?(dJ ziEJA~_ClPC#=dw};p^37Y3CbzKWtjkk_4@>p`fhKI~?>4;$5AwBn!fv)Fiu`ic!o`M|skY+e`HIUt844KI4G(}X7%G~jVjap&KQ@FJYFA1&7xotjfwAdg-F`UBc z>94ADNe4BGe&uZc4BMG~Xx!@z~ayh*Vqn4cw2ku8_g@*xoMf6M!uFW@q8cecM^(dteNw4)tXNFLNl2-wdeIf9N!^6>`H%7H;#$DzSgy zWbm?>VCUm-DZgi6ews5>`569*S{|R)s_Zc>cW30?lBf!`9K%#n%PO(}hgHQ^kGK_Y zfcyv(UN0i8{3i|l^BAA@_~3z$gRQ6<@B52;Z$zn^wH|@uF&Ga7Q)`ny1qu8H3LXO6 z9|8!HyxPXm4YzV(Lh$!wkwX zDYL4nt0O71Gz7fu)t{fDe|}2qF-w3De+f1#DeG^L5^SXGzrF~8FA%gn_-mw`zpu!d znwT5DvT@a60srOXbdQ6Fo0skH+V}Y5aT$0nBOxsTKs^BfDDVwD&HQ}7K%4m?4Ff<}XS>;yV|>Jb{9SegXpx3kw4S-t7fm2Vl@((aBg}KE+Tngd?}Z zWb=*s22b&-tPM+f^oWw($lmW60yYjV9zGQ{4ebj$4o)s^9$r3CF>wh=DQOuMRW)@D zO)YI>6Vtcv%*-tu9G#q9T;1G1eDn|a6c`j79TOWDpYZuhVtPhqR(4KqUVeE+WmR=e zZC!nPM`u@ePj6rU*!aZc)bx*;*_G9`^^MJ~?Va7@lhd>Fi_5F)n_qN60nmSt1^)em zuz#Wp4W#P{3=A|3+%LMIp16PqG#U&n8S7K@mr8Jkb{OPrzVMi@qP~^2J)>Y(KEg7x zA4R~X_G!2^tFAJZLmP7`VKlP4_|g&+#7~{6_}< zBLn}Df&a+Be`Mg_lz~D6tTs1?m4?rS@$VuV#n=4gqNSflz0M7b3NY))UALE{C;}i# zx=de8vmSwV>1^4RFod<&;aris=#RiVX;Z=|+#hsUP6n)ZgQ4(nP&!c!$P0>4;+X&9 z5Vzx=SvG%dFNK4rIqhI95XqP9)VdW8C7=qeQth!_L}n~doNA2QY#PQI`Q06GN7+h# z0{tAyKA86FlmC;Cit_=58nbDxM_}ecJK#uov?R%j*$?%*vk+@&MC=Kie8#KNJ3YkV zl^G?g=yRBhL(T?~3b)9@-Z7t#L_Kee0K6gAAzJ8&BhwinIuEspVk~2Z?Eb;Q$=p_J zyt|#oudF=-C{oaH2h-UaWZ4Qu_YLw5YN?D|yC;@5rJVWQ@fQPxVVJeEM7W`(-)XN?H}u5DsbRZeYM`Nlu6e?h8Yi+p#QSV>M9)~kBs3Q1)q4dphFt=segOC zyZkA?j>S*r_*v)B)Jaj1vEs9WwGCI5jzm>ZXiAdg>#0S3>`v}epdEHQ@Mvaz_=5lc z&|i9b^<$Kj^m(1RMS|?a6{6Mf*&)jSI)71g3JKCDdwo4hs*k`5=a~1_lFlR0hIRM| z;O996kCyV`)2ABXZ+B}NJ57?EW=Sb+jWMmt9kgL$oB4%SK=lz>@CdklThQsTvrgAAvR1va7?FZYv+F zvk2tqUWIYRIpNzlBYdrp00y4(QWPl?QDF^;9wT;4KbI6h&X+|BCZd$XKaPw2g-)cT zd&~pIAnI*>%fmBf;j2l&u~LKi5kN%j_^fmhvPR|-(T{IB8j1Ojh#)D0mY{V+c$X1G zTxa-!Q+W&X=MN%5tU<}Og(tFsWT%|)vu?_m?B*Iuc`k4A5joxm>3SiGl;B*S3->`=~fCqZxpnHacG^*EbaX^CN^4vrzO=(8dwM8 zk|+F6;1uCx#T}qmQ9sF#R4i5cF9>9f9fbO%cMry*9RSZVcq!m)yZHYn7IKq>pW&q9 z%33H@j%Cu0gN(?&{4YjK!dw+C?@(w_OfW6rJ}Im>9fcuYzIIHGbusC;i|G96?6iJK zf~z9gVme_IyxS{0%=qm(okafXj{j7P?-A(66Ru`T|0qiwkAr;`*gYP;ap^OVY8Q&u zqrKtzbdhMPQN<(g%9kle7e|V*i25_T2~re#j1TH~*0Y>^eDi{g9Rh+mFNyZWn=vKE zs!mG=Wt7lDHq>+1s$~Gh2bC`E|B{$-y#E6@I-&TlMazdT zkv{Pe_;@P%a8LqDtSl(8awN|^`JDYz?=zWpHkc9|O<=LPtiDFr0&;kLxcmXM&^iCB zY6dvQYT%|}H4;%;Qo8%kWdLdkuj@%a%#$$H%6YFLrOn|ey`qYcMGWy2GdAzBzil-g z=IMrCE0RgpDL0{uwC>xr)b%u!Bfd{i3Z^e0eFOxmKWzqj@vj{n4!Vbh?Kfu_+IX4M z#?P*D#=n4*P{)Hi;XK`H-=~*4&IzqTY*KpNrIfAtR1J3>DcRkc&`Xeh`=eMeXE>*- zIFy>|8-Nd>3nBWKZuwui>;K+)IL^FBp!X3-e*}IoJpzw_#H@Ok@virY@OH}uV#^~i zS{<8^O7`4f!1P_#(yodKRP8NkCDA+DdSyGwsWbfulZ zS3Lry#VLNv8a2-p?jboV>j&ov2KLLi(^xUmFN`OC_{%P9e*u&{vCl8`m zoZx+Ou< zk*d4(b}+>7x4N8%cxYGr4`N}^4{g;TXhutmQcp$!u4brFn%a0C!-&^4@1i9T@&&Ti zV_LDYYzoY$U7jq?DOM#qJpU|C*#F&_r(>CLpO^4#(}&l?`ek9sgsdjY6I&EVXqR{86enz#)Bv_x(u7Exm3QoJ5W}NKK(wy0E?{wiV-GU+eFe(_-#6No zFj5%*jIGK-*a( zj^dlT8}Z%rgHo_I*7ML_@BI+hp;5vN;kbQU*Hj-c3){W(Hj+H_tWQAQxq`t3-#LYY zjWS9)Z|8e>C_;HstrTf^x(~r$s3^*BKgt|^xom*iI7Vq<#i+<$3RIBOg?mJc5N8HY zL@1TTKj^?8LKaV`7O3j`v&9JQHF%+;u7iP1$4B6rR>S*z40K0g=5f>0WI3Qfy=wR+ zP-!<5uZzpI(tV)^$tAMlp!oqrR)mby^+>opav#=n>Gis?${o|H#K}3e@l&KO#F85m z(Uj1E!!|+7{z`*uDDy|)e4pgOkABigR`X|N5#J*9mncp>;iu-Q8k;8+1H26Gmz*2* zFv9TO<6gT=slEG_^5HV@A7A(uV)=v~D}{u-l;N z9jGwJJI0TIp`P#~AhVL!U1sDYIsWmxwF<$f_&Lm|$gJZ^Rv4nXA>MAf_yQN$gOqoS z4Ts`Wh3Pafo_${UEL)?o5$#PMw*8M>?t<{)?mvJr)0y_vq`mvw6zYPb9`TCMZ2k7Z zFD8@>!RcHkM(iDc>XEB)TfsD+vd%6a`JAi`Y*y2pfb-8eyN3w2pMl0{O(~6UD2zvd zcOZvP6o08q)^C+5`DYo_!O@n_u*;Pdcu(G3Rc)#mecbuXcjyH0=G{7|K`p(!Bm!gx9haB}MXD~>N_-+#1nDju9Afh62BQ z0$)_$))KA75hgI~1aV^9y`VjrBNJn&8GZ63-s-soeBU~83N7@2<3GqF-NHp2#4EFZ zTD|;r4#4(;nk=nRYA2?37%ojF548Wih@d8yn1S1brd>wI+0@4J`h->;CCoq66VOX_`DMEj;+jqnA`x$aH2jlH+gY2ENZ+@n-g9r@T7gwxh)0OoYB~kCKu;=cPC) zG5_$LzV3E9&66USd(5fEM0p@T8J(A8dqg8+dQ34Uj<)Yy>h?9q{Prv5g{*5>OeO6k ze@rD2@XP-v2jLXRbBc$MN8k;p`S%3ox*Pl1W!yoW5myq2%*OX;HeSuE@aY(CtUh`5 zv+6VhntgqUr%1%L+vmd9BxeS$)`PfTuD?emAMVTT})v@XL~eTDYHe3M!=WI3(Pq0i8mcycj2*V|GP zuH%q540AAyX@229N0;v}{Uj}NL+PZw-i>0M{OIB{M^Ll}MZpZ8Ou|#!pVOlW{C!m6 zt24X;n@urnAIaH|GQ<~6<{3Fo;lrTgV{t<*E8}2rX5lGq6)1{SMxNfk?HIQ7_tDoK zKni;s6=WmROZ}={f=74IM-?^Zu==SL9%S`OG^1)bo`TEW{ZsVYAS0tu*vRs@H)w&@ z@V8CkqAM6Hbxx>cocxw4GD8QVK!{qr)YjVw51A-|k|8Qvg~48jM4-wB6wULcd#68~ zr>J-KVDX;I=HRyquF&|C!Ft=%ln_$5{&?ZoX8;~!pEaCY(Ic?_{+9=<`Q^b1QJ?QR zhpl>qxY?X72pLpTWk_AJb&x8M%5CUlh!=rcd9iz#nGF^*!{>MNNO0IL~C8>pJ=*X_>|#VRd$nN;!z$ z*_Dn+W=hve@q8Zb(mi;804s0M+wH+;z+HSZmD3D1tT-!sZkVAou=gc|qnE(b5XvYt z%Y-slu?v;4Tj#H~GM^Yth#*1n1Vg2|ZldsDodv#1%Ou>{?6NWsqyKJI1Lki26K}zd z_gyS~%gxRoan+gFJIe@i*W~KY)~|PRDL&7RQitobl&@LDFqn{#2JnY3#lG1h-PNId zwj#%%(-@9YVK(NLix#hvOBN*){*=t2y0EC-b`(1(nJEy~B&xbRvyC9SUr*mCiswk(Xk20=3&KlyV-Cj)*N&nCA6N8LM2TW0a|v`?jL|h*G9HIbd;2q#;k@@_ju=|nMDB&* zyunYgeW}Tr){oJ?n$KmCN=VPQEx&(%-;=kxC491XC$aFI+xY@#Q|B|2Y4j|XlO$;m zieko^85~bUv&4afbf*yPBM^CcU)cf%v+fXs>FzS3oWv;=(RX%Fo_P-7j;15rzTyZD z=~j~3Y160s2bn`1-BYuH2R zBxs4KGr`edfMtQMyUU`LzNpjYV8yAmznSD|hbjOYr%G3lD@@iK)@(SJ5iQ8ZjB5Tt z>I+RdUsFtGp6xr7K`%Uq#%Rq0#+aBP%Ne2291Dh}74#cJyFgj1fKuQlUOBF~V8op^ZcW1R-Q#VR%7$C4!o!AayHRU?GL*dV_{iDVEX_7|cYBkp1`fwRy zTdowq|6~{&S`>6&WPL)IU%o3vU{m&{6UFEGQ#t~rw~qiqr5W?jv6I=={_dF-=ULP* z8((>MSu_d5CD?e25VOaVM8;am^=E$KsEkixShZ!eHU=6>t@*(h_S%q@UrA?4+YuFX zP^Z0vzAw3#34*aZ@V=1vnJNjLyC;H=zP(5?##uxxtM{}UG02*jC#Txq$ZW1JGI<}` zmJavLaWrZ+-Cv_gx|WYNj?bL%zTwA(Ef&Fq*&r3XKXogM)j||2m)ej(fme15J?+8f z_)C%#3nkm>qK_4#I(b0Sp}2>il~Nmh$s*xdsk)dI`VqC>{j0GL)HbXoXW)1vZ?+C1 zq6d=2g~ElUIZ{-&_6=8iG#ud;F7OW8haRKzW+=k0P*-bD^kwwa*d~E`b<^BMyp}rK zTL}g(y6X?ZFII35h-$L2p*wCg#}51l6E2EACD7Kf2Rs6DA;P?r$%NsJ#zeW$zDL>? zs3@Tv=>zVJqv>QmJH!h5tUj)S?i$j0vK}ZQG_#GOc5WA+SgxTxvK2E3zp%W-(-#r? zvZp)!p|GVA!qMO<<2}-`A80yfqElT`H|IND;=ao{F|{_Hahg7X-!9ep(Lj7tu)$`o z<~tpHpQ3BGC<^^%)ke~^v!`03zhv=YQ}e#CfgDQ23f!G<)$lDs+C8;j6MEy}U;l5q z<32LnZlTy?@jjRUORFuU>B02InY8J_!2g>EJ$N}PWZ2H=ajrhLR;mmBZpBiQDF}@Q(k?-KX-UaTFXEtJ%H=AMMyJ_2Y4t}RM+brb93){d84k!>c1 zi98w6w3Kg%r9@fZBG^mfwyqVXSs%mG5Wkpk+k1#GAAWe5eiw1|+Ea%85nwL!-eJJ9 z=h>$iU#qPRcEgv}1Hu)3U=cj>9?sp*cG?Rmc)Pg9w%^Xl_kM4P(P{Q4uRG>S-;VBK zi=dt`Tyt_15S@urSQ*Bgqn@hV7n*IK?yL`Wt{$aS{N^`Vo$iBa(h=hWN0T^y>bP`$ z28Lm+U^8ybG1dCZBOsLEeTCU_XI=6`xvEaB>B-N$`;1lL8~iGgJ2)@^U*k-=U=*>4 zwh-;)iJg@N=$v7*PJ;{f=S+GQqIC|>X za(xQMsDF^_R&Q{3z39CRwjYk`fi^v%YfiXkJ#Qr(Cf$l_=eq>WxZ0DlUO%!&0P2#r zBE|S2Kn{d7=Y5N0y`{by z*L9wc~BO(jh2|w8#+Y!8GuPwOzWZc!#{$H860~AwuZpc z&l9j56*l=Q`Are5jR^b0c(M1$K(6;vh`|H9>RROl`Go#G=e>v?ul?}G+=-r%`dWVv zIsB(PxcM!c!LgSA0x{+`tMQv|?O$}4(s~u>Jp$hn6d!>W5dXK|Y9abNXw=8pUk5<6 zGx~m`O-%l?A9ZEW;`dU0@8#c11@`G5JWITf7`?9+0F#+Vz|#DJ>q5PmY=WYuCd?>E zpuo6F^$pVJa#x~Vn`+CJGqzol%hkC@AawE(;0Gg%H2S4GM1u!z=`C~N(+!VDz}FJ& zMr=c4^Lt4!iXV;}Ou&vOFg)nBP)$);3l!Ru270%84MFZ}ejyzH2t3^BfSb|u_tl`| z>E038r}>Q)>#y$9TV3fwJ#xxL@)px@%}u5CIV1sVB2+YIQ@Eqea_-yoN)Qx!b+URd32pH|{1aT^t?s|U zRraT|bqQ6z#!x_&NopjIIg!R}UMle(>GOUB-ZQpbO^VtHRX7I5xCY<HWPgVQRztQsA}_9Nr-*JaB^BLUOw11#Syyg}Za1$vGxgCy4Jk z_f{M?2882m`kaDvBIpSN$w`h#9Fn|eL7@O)E&U0qg3e}pBpx~E+)Cfz9N z`9Dh;*U*~Q_)o~sBF~pze`v@0T*}|IL*F^#4+8Oj@6RZx9qpjWg;oJ~KoM49U*S2( zI1uUIj8loYRc3s7IIiD}BM&OI`adc4)M=&n_0cchfqwEA@4`UPIAERq7i=H8N5JCh z!$W}V;q5V45bVw;2wAZHr5ebm4EDcF?Y!Zd?Y3)31+DNWPVb@7mMyT*|0gEOZa3U_ zR|a4c(E{u{0-J`T`it<(A!^Nk2=i!#ih=zDg6zp$5ndS-Kd z1V-(@5mHOwoJZfo(9v$ARFt&ASk)2>)k+j`L&(5YTO)3~F*-Uk_+enryNHUiu)uTQ zJ9FjbQDRO^o**~2A@>Tgz^!<*ruoYoCGyV{C`4p$hvt!Md){ZHy?z)!wz&r!748TJ zz(QKp`Yh4HP}(Y2OO<{0`0GSB5k;3*6?1qvsT1}>h^Weir^MGOs z=Kb26m4lLc(-nZ~6_4;W2%RSy1)Qr?+eN^S8C%r;p+$ z9?bH7e|LqLYxN$lSZl59`9k`HlE$q{Vo2jYnfNgT>QLwc8=SC=q;2bp+QI znOobkw0-AGBdKq3l$DX0>{9sy7_Yx}wOj_W5T3Mx-H^%@8KQR*Ws{6k;(iy4{DD&< z(6CNOP;C@ELfJk{O5(;dS2~G zrN5pUt!*i=YPjDG^lu%aDrqZt*$`(Se~=EzOOG}iH@}WTc*?ue79}ifEP_p&e}OY~ zlbQnYen<1g(g|G-ai7AT1y&vv?8a0X`5_K6l8h*|(PD-U zdL%#O30*W5e*1=)7xrBPWfE?l%yw9JHko_<%v<4`E9qmL@H1JjvT)hD5h9fo`Xwm@ zhxAPCR#JpE36i{+4Q|EAMaug!Ezns{xegh$*|fsD2*Tx`vIn2iN5Duz*g9_*L!?Yk zoI9hWKRxWsB@?5hHNs|HC8ll!FK*;MAkSf925HTWzHBq@U4B<&s&7_GPC4sT)zma0*M!eA zDJ}HnNnoMCdTd?XO?6AJW5o{{yU?#=UUI{DmU+Y(xfaf)4cfa2(o~fj`n(7XXk`4j zPo8d2P&%Kj8yr=2HwgKmW*_kVwbxJr0ES-{-()-H~V9G{mDzfk&`+hzc{>nc0rt7ha-$Z zxdSi8daW)l&fY!xC3H)bWUd8rp}tO~Z68)v1&(^0b7i<{34$B&WWjwi7bY`3+6O@f zocT%;rvflzm48i>%>plIGrvBG4yFY%)00GCsW4*!rC*n4U;H`~{Kw_r3zVdPUH-KI z91|Z7c@Vu!JKuwQ@MknAylPn&28(q1rQX}hBXHs?{BxGfco}*fP8@9J39PZzmGLX# zCLi*<3+;T|x`kQwKIHfl&$cf(4x@`=ePo2Ktr@T43GSYAc|q$_%8!{cGejSFG}#>H zu*Pq8J|L@8U~Ec9t|vnEl3va_s14?ctg-OE$Fz$}_MKpPUG%I1%8s(GBu)It+;;oB zg(}?@Wj1-Nk!T)*0Qc#LP}_^yJcEG;+%fJl!s9EMRk3%YcOv=KJC^HRS-VP|$7Dvi z$N4a}h&79Fc?AjD5ua?ZuiuSTb?fZCG_`#i^8VWj!BL}l&&~Auo6~9Ez^8G`*v;XC z0?av$hZS^*XohHS5Q5-C(2}3qu0KcRDYChGc}E4-=c~bR!SAZ&Dsjyry=L=v`Wh>@ zl8lC(r>ZHXlHl!w z3Flj_52l44N)l_F5YTYSotf3^gPqDV_lD$B-BiWQ6|y}2PA*zE)Pt~S;6zr7r6O^3 z8OX7OI=g*hHpVXPlBp-nH!og}_C%{N|GicG(}iKckB{)k>s2tY?1{YMv5%nAf~-EWJY|<$i6RvRUnLGE++L2$0D5uB)lxfPcXy>YCq~T@QCgoB2AO{d ztxbGhma^{pOIhO)AF4>YkHDPn=((4-Vq;6~(Z;OUs8*(P302{uv4nMvTU2Ed5nOUI zHe6)uhAqjv<-N{e%bm(3&2ziFo$?M!2Gj%uNwb*1AIbjh^0fk`L?`s4xnEH!$2=*D z=C*IF7swx;6*4kRxiUM!B+tttcQt0dyq(reK$BvPg(8iK5i1xRaPu&mg{%*aX?nw3Z8o6<1E&Pc@O{QB_vrmL@RCljVGV6=#snfE z4)(@D>OVbOx##Wb%19Sd8WB=^+T1^4pXe>j_Ba$v=9w2K%uV!;N)n~(vX$`yfm<-P zn$Emf+h>Y!%qxg{a-CoQ5<|2vT!d4p7p|D)4tnZ^5=~`SL z4U8@8q3&kSBaq7X=>hpG7)Q}@3Ev%02p>V<9sx3q;aa_gA^xS3YZCIEMctuH?&ib0 z@CYdnS%MBb#yfsv`(i(AMsmCFkeUtSA1Rsdjmp2p^m((;zEg^Y%RcD5MQQO@`T^=_ z510tHRg&EKtCcWek79nWPo~?i8Pt3A?3G8{E&2L;@)SPgemab>sX4I3yuFh3qMKv) z)gHuPH$>YVCPKBLZiXhoowt=n==D3_>6#rq`M5kSi+UtxOWSe*7q(BKBwyId)+m+1@{d#qN*`;a$-Ag9Wg22t z%s`tCI)Ps%{|_eswrziz{ND?Lf1CW@3lyQGK_`HfhI9AnSJ!?D^&UaHMeEqR*ZuIJ z=?z#b%KD1@2q5q5=U;_y_H)fJ)N_u22Ct4Zem>(p64V`i6~6eY*+q?uwovBH#L2K7 zy?KqD#MGwpv#^v*#eN{nb>X3qxV^ETNcmR!n5gi^GlsIroDTzYwA=acaEL*oIO?xE;ey<590LA znJW5;+EA?_HANZErrQuK*q1+qKPA%^4>c-0U>Kl-qoGsZz;YU*!h=Z0Kc6Ump{%@U zcjw(3vHzOnG-Hnb`yKBw-FU|X`q6!Jj>UjQJ)}G+{Y@tnerVjyhou_#jm#_mB1zZk zOYNzwH>@q+-&WOXfCJnisuX*}V`T#DndYhN$Mg7B7)gS>#&x&Oy?##iMxYp;*2>%bs1!O1db9*jcaEDNnvmyc{k z_H?^i0-b0p2laLIUTt2$Z&g)-ExUaf^e%yN7_Z}xq5C4o!gQJIClbicmls@MEbCzC zMgqpN7#(cZU@S`(AW1=*8izF%W9V)zG;T?lzDYvvWF1ZOrsG?;{IhkFwIblnQgK;k z2tCzwPHl`zqpWFNZOtdAQnWsbIQZbqDB{U^lxKLuGE3tSroy6G`XU+2i$$3M0lN(U z*5#jSDno9qd#V`i?tC-D79;a=gk5-HUF&1DwD$gb^W_j43Ul0jDM!l%z6H_|X2^bQ zgTQ`n7w2AYCxCLwR=Vs$Q}fy$O2(WMVxT^yJgx=d5@Zt#paiFo4r=E3mkRt~+rA)0zPg%fk6|NEWi z2PbW~Fhosmdm?yzz*JQc@wg7(Sroyo1KUi9St2fX9xYryVR>}jz?(={yw$4A`i6zw z8?U86W{C3lF49C-#=*9*#M&0vxHQ_e=@b|WAhhV$N#AhTt|`95 z@S<7&$ULx$gjyf>UO^r0Y7i^%%v#sdHl47>eoF_hXo_w_2TjOi%Rc7AWM(ic`~w^; zv*5aIY}PST?rZ$X00$KeVSod+2sJSBc2lXVClATStF(%VoQ`dfD@!}7zUe?a8p4oL zI1n`iQ38!ycGl%`%$k+q^j84r*OXAvBH^wvqmaXsO!oy(1U zVtwXCH#{lJylgqW&IbxnK2s)m_ zF=&RmbhGbI<+1NUa>3~BLZXo=QS?QWV@RY6Mzm|hR3YNMm-TYJ9)`LW3(Z3Zm~WohFm=|!Url1pu)xYp zHSvpdKI%$}#FzBx+vBwn!eQ(cP|$@rX+4=@n_cY%R^<4{B}W@ zvA;dkpJ~c350yRoI}iE8L;YTm9xMYUCBGM70?L0&Q|LY#oDesF^HG|@XD=-7-*tiU z0XU?2@c|6Z<9#?PL(GcrOieLICF$<{&f8@+Fw67V4&F#S6&WV4=NF_N+fp&7D8qSS zV?|k8Rp}Dv*?#+~;00yq^LdPsQ(bpy7m~mt?f%6BH@Ucetg33aAN07B<@uSueiC-` zE?wrNQ|MzlYNJkVNQK3F_Yrn|x@&37f`hJCKl&!?KX_AYInYY4GUe5|WxY>yJZxDv zlg{dRdvjiR+@N6M(|KD8cNis2LAcJnva=JS?F~7G!hx!U7&echcf5cgyk!Umps5+c zKST|Q2#VyY%RvN+>V;|ra`j;zfgr&i_}d!PbFa%9LAM(Xn4?o0DdC3Uy9nxR^uolA z9LkoCtp^Fc&7^nUru6z7#xMPycpzI};ZB8L9_lP1Hlk98*=4zY+V7)HT(I`LHsLY} zA$b46ZL67{W!B;~z=vHc!VBzh3y|Di>W{B5a@+Xc@gnaxblE-q0wL%jk97nSm_j~3 zRAc>Wy`irwv{lxR0Q)wZw>iFb^6F|_&0!I^0VFsJ7A#lnY7TV=K7m5IB&WKwf( zQa}6+$xCPD*+Yr>g8Q1M&P!0PQgxi`8zz5}jxQqS`L##kH!WNqSYi{`Nthf)W{fiN4HeFhN^ zoAB08`cc6T!wl!%XvN71_(KKWL~#`hl0x5dbac{E>GPsO^S9>|B?4cn4KMZ$vF|tq zaeu7z@IjZdel27Y&GF>IG(aL+BI>f6#Bw7g92aef51_aHHy;-J^P%hE$*KZIbb2>t zZSS)n&(F$;<}@x|g;&q;E4(I*$E(aV1Xok29|83=QEVJ`ZO*D&ImQWcwxg1noY%gj zq#G$3xHQOfcmQ_hu}~Col1;8xUMgbz3xqDDXlV+h4Ka(X0py~n&``oPEW&1n(UqF& z&x5v0W=Nx5Sjl5Duaa3=^KleWVIo;9iIHhkM(3m&L*y)Htk8E6Kc|0z9(wB-Rs6gG zsH)F|#s!m4t60BU(Zw-u5F)OfqYm(v%OMhud0x zb?_?o0%k4|0gS0sFArw|T(F}@%1f*CdI$R6QHsx$Xi|I0>HQkUEN#oI0wgjfi%cU7 zx;ne{Q*k*cp0p{k$knZ z&^C*=0BJ6?gT053BlZK`=z&pf3e6YDo6!DCW$gh%SUBbK@{e{8JG}c!B_U_dzF7;N zT=hBevresXAx|l+Ou1ReG}oW-a1Ihdt0z7y;#d&6=#cj{j;Cjo+2uuB4|dHAqxf-H zE||M(?;U2#QZ*`Wd9$Nn9&3@ZrPI4$(FLdT{>IXvB z*VEB%$}b$q=Va8WkQBeb>xu`c!@Zx!;@#0H><=9JiKS{1Z3`3=<8oRGKAn?jINCVh z&nOJz(;l$0kD!PP5T(r3^21teC0b8)a^y0-O>rT`YT5B-3&hflnZD|R zA5*@>mN8)7Wkkq@P)<}aV`^I@xU0@Os>id>VWny&_ntH|#+}SGE3K!>KbzuVmbYmCnLDqeDiHI7G%suLp<_8P{iJrg;xL}CxdItM07l5c=A zgz&StG77J5w5=pG@%d?3!Ho3m{cxzYz*Oi$iA~_9aG7Jt%~P#MV96hxMJaMiZw-tw zpPIV3RN^`_TT`RFF+o^#HPp-|-_RF}B&Yk<8FFgs%hQUh58t=2FVju0GZTuA=pU5S z8(BQEP7)U=;JZZPFOFXkCQd`nGP&DcXtD+ISUTdtJO5R8L?!-Ov^8ha8(p$Mk!-wl zb30wpM_wId9sqYwZFB#WZiRsYJ~3-ysORKRk_Tq1FZ77-;+{Tx?3{p6<)wd7F}h^< zrsDC3Q)+bq6OZM!ZOfg!;Zy{@(TfQS4;i~O$FxOl(Cez3{WoidGJnf2F~QQ~uVm60 zOeVn`ek7~l{1x*x$^tlYT1j$)SqT(nF;%S6(~Cl2wtm*2V0(R&7{{ZGUw#8UsITx; zlZR23X_^H`L9W%Eo+ZbMw(!rr$=R6>Y;naL8y-sEZoYG@ zCi6n=LLBA!PPMztnwpv_W8%(5y}-A~^Dce-VXn2CP1WT!->(Ztd-m`LOVVWDw~XuFZxC&{ylBDNaE;Xe4 z8(ho83WGyJaqV*kmdED;d0fqN?!r}@VB3rk3>TT=z?qN%;oGB@75&>~g=?BreDLuX zwUUQm?PG)sup|DD9i5Cg8Re~p{hQPwQC`_u2mbw=BpjTnixj(+qQGeA=d9e?fJgqox83%elk-g<%|%hnsnP4_ zV(JoXuwEB8B7fp(k^%DGaB=1Ilm^88@&4RXyQbZt>|#k3q3PtWNCFC5dihq!6y}FKA#SUh?q3Bmxtk zy4+QdbY%(jD|GTJBfZ}Z(aiQhebnJDkC}f#NFu7#vBrqLCjCJr+%f}V+XiVXOO_T= zWnt}B@d(S|Rg_>KewtAlp)}Dbhh5~7HIUr_c}G<)DNxoJT^T`uaa;Wc%kx`ka!QZy z68^OKl;be!mAd9Wb@ZXa=unyiY-5z$D0|OyX1vI2tNu~r7(d+eZ4rKcf;}&pA^ryS zw*jx08?D0HNc{?-V890h3TqqnG6wAgWG;Q*xJB!HDoufmbZSa}35GvHU>W*pVw7i| zN>($mD{;<3FB9vO=Bm{=cp_G=sYjrhiSzuux(`RapH zO^9;T{=u6>b1kl(O*cvb>r4|A9U8bqV8?OLXk0@Jf0C&^o6VYG(}&9)>lDicg)j8t zJik66*fEU!zVPr}BCj%5s)UY~K2L^Go7TD-txv2?qvQf-Or`-56w?9cTwZ0-i|vuVT z#vr>^tL1=d^i<0T)2bY|qfMcb(s~$Vj;3_dP(5|N_6V+zdF=fETX-<$d>5kA&$%A0Y`-t8YyY4lSq zt@0qy+((z9sg2f}wi?47YIT-?8%jBj(V?o+v(%mZRy{>EZa8il4ik=RO zY(g?M18J?$wdn;v+61eTZRZ!7<_D68wsVL3x?lOQhoS&GW3|W%s>htwC2lAw`GdB5 zB_XbmtN@}SgdYSM@MKT~pZDjbNnyA6LjZR{`!sa&aBt`ZQA&H^Bs;S}iqB#$NuT{v zx(ESWzxOJwy=dPE>&=2Cmw}G18 zJ0_fQ<~-xE31U6Cc|sZ$0u>L>_hrYt?+C$Et{2n0ohZ*896J5*x#jxFx6j-FZlFH zBt4DZIL!!THU4NxlCWeW$Y{dwvxJvS5=SpMDS~jo0Wp~u$10khrEEB*4(zWk*{DgN z&t6?|ej%i97d7D?TvgNq5&FW|G+|C@AJ(92cYgO&VMXQBAS;Ph7+vh@xN~{1#?IHR zm}Re|So5qC$$OhK6O$NyC& zHtzQFeS5d(CxjM&ie^D#QnvuZ1|MgzIaAMJZ_mTSB)Os=wIz^9^=CTYW#A;Q6pQ(- zLff5CH#v1xz51hStg@Pqk~kOGH2ixr@Na4PuPmGEcis)AFTXDTPRoBecIn>>z%FC- z-_mk%u)zE~Ems7ahBe;j`>0^kP%oeLj{pFy#)8%4r+QDE8eTIDK7?_j=`zq9ir>j$ z`b0o7_I}L#r5>-rq4O(mfA>e;e*8~)yXF5)-mWjfIxxGPFsOTd*R3Yll!4o#=5kGF z{jd88($opaNqbWj-TQ*k&=?1;B+cTKp$?HtpK`LamTT~l!#eHChfW6x3k}Gs1N)bq zZ?~rRMo@6HEnRyK^nSW2cdCXR!kgbuE-r-XffG9dPN;VTFG1;5J8VW|sqys`m^$tw zgnM1hni)Y0Klv@KlOrjHTCfJ6<$wuwR~t(Z@GD4ISLk^lc%L2@dD5CgARlp}YT(wfd|oMVY{@ zq&vm(z2Up@ul`%1Uh%VHij>L-*wM=Jh$gwqj_0V32e~C|pE}(eXV(TT^DH#*Wp=r^ zMs+LITTIQe0v4J*X_LM?yl7Lz#L@Rb(`yNGLJVUUjrMpIVtXoTL(p5N`Mo^TqxS&k z{Z9|Yr&U<}f#;f>-@Zw&BKE1D3?3LaK5zXW%)ND3mEG1ZzGw_2luijzQluM1N<@@y zq*-(~EJC^j1f)S)x*H@Ur4gjNyL)*izP|f=efRh6ea`t^`*)o`xGq@NnmqG)o;l|j z;~w|82W_R%VlbAVLs9Mxt}YyoN`98G4CA;j?S7YBF+@vi@p41N3N>|V%1L^+NT|Qu zq;}+fvZzm5guW6CamK}snVT3MX5%uaYKS|vh+ySAZo5GkA@-E$Np88PY}OJ10fFC|^~4CN->AT$dDP~`=qpVvjKz2QRe?*X5?4(4!wwS)e9(VTlI!nOLxzbDjA<2!~soEs9&xm+dAV zwPnpt-GT4RJXzn6sf;rmM_n-*F8(~L7dhy`@qf-pF3!7@OV=_Mm+^7}R89_M`A!oC zD0O%QsjS$m0{L7+sG#lnE0i(Yc*1S-thh0~h;8J`WMJiu)IWs}c~imNn{zZB)g&7e z4U-5j2Z&mCNGFS9UpwF6C^~?2UW~0n%`RW3YiPxDnNu6y-dMg$6276=J4-XM6!F*^ z$)4?sxz*XAl-svWWpeWXcX~v5@L30O_}J5`MeFoXBLwmm9=UbD*ZcZX-jrYGd1GZc zt%6y_^04DQJCS$kYSx^mrZ>!te?Y|RhcXl;w-$z|LlUsWIN3JQxZrnB?eZ~XluHKY zLw2Yw_1(h7@5wMkaIpG3Ly7m0LCk3kV$(14nlpd!;bm{}7nHn`uID6NEOar%l90vQ zdWM84D3!YfQ6?CzR*bVIKJpPZFkb2Mmrnzvb`;R~P>~{~1#kvJB2=%EOsO;NK4?6r z#lbFXOsxGnDNZ;w6#Bl>oqmuZU1BAA;j2-!!L!oXacXm4q3joKm^1AnYibPt6|bk< zRvIif;hL-HFTZt5iff3NnUSXEU9paoQ<8IJ!U^&U-$C>L7N*U@XOhB)fA^~7neQ!! z8fKcZY_fZVhQTFaj}dz19A0lI9g!M$OGQyuL&psRmL*auA{_L@M0N1ksb{+qYgbaJ zAxyC!*UmX71WUKxBJM90WFZ7#(nD@pJI;wCA%#YTFRU)dG+R4y9Q1ZN89oX{k5i(H zdCiIiAnsQ(NaZF*6v2;Y&qrumjdZGZP2cqp zN#2VYdAPcMUED2_E53BC zOTg8vx9Ww)=t?(4OBxOwEieQT#om={5JR|yJFfUx-fO3$X}L6Ccb9Zgl3GVqY#)V_sIj@u80e2s^ar3|q zb84loMUDpjM3+KZ}%;iZ1KbE%&*x`TYQ}h2Bup2&s=aspc(k&S1$PHfWV&?|L1^L2=bJ` z<5`-yauETPV=1Li09hxwM%ImBhmVX9Tc2pO&(j-}RMsZR>0A4lnI+lZY-2b5ltb|* zJi&o*XW^{x>O{AVgVQn!rYU$CES$$k~@ z?ng*CTyzc$WTbDpyKa#sp1Ss6Ns8%CT)TFPn0Kw<;V<$%Z zx}}rCeXhn5W35A^QNdj~n`?&a#3erRNCV35QGKhd2%oBci6lv&LipR~=oI_td^*)K zry_MM03}}z{{it}0o0$N)4OoV72n29T)++g7+v%DR9SncW4gY#jtnvBZv0rqj@e~{ zSV3B*s_{tkt&Xv9b)F{@12vCVyVgY>E$*YQoAB4srkBT!d%BPakBjY>-+BvGDUPI~ z_kA~ua1i;$Y(Rq+>WBZ9jf)+@1vlM)ZsFZCCjEV+k91V%4o)snuOYnF9D&CF_S{~7 zh{P(@&$dOTqF)xO%k~L(sj4c%>1ObpgT&XT!AS`1>?93@gZhJcwnL_CW^V$ceIG4` zN<1wXs1SX#u(ZIvQg1RKL?A9ce0ch?yq~%3f|vSs8*eSQd1AVufdTVM4mV@uyO-8B zefW8{RrzdbdX~2{#S>GQ$=0Y1oCw`@I%5ndP|s|d<_p2UF-Z}KwV*x5Xth7F;fXC^ z$7Vm^@vy9hidf2!bD;6r#1*(w-O1pKai@sjo#@2YwlOd)_mz;3$f4G>VfetbvfMY_ z#_#<6A!2#HPyYK#S+!?WCOOYa-z2aiD>t=UM6(ePkhnoj8O#oQc*dK11(`-hsD1BE zz8rpq7@YJHLTdcw9-z|wpZzG^{dj62Up)M=zAjqL|E_F95-+V$^Mq4rm#iKgf@%Bx zu4?KVcOHukO}rK&k1=pV-LvEv?RY}Kv=-DAnclhLwK z!}4+{`xJ|5=oVP>YqB$^=$%8)Ir_Ioa*^$ia&2aEayoR$;&*__iw+tc)pr(+}kkG z7^&mWT|1BQyW1Kkuj;cX``y1`jQm4H)uT#to2t9Pc0IO$h=f+KraBXJ_-!b2P_QJJ zW0Y=4ip@NXI(kqjm#q2a*DmGgo9?gMGrvR_tHuN}vP;#|neos|5pD(cF}&1s(!}dJ zGo5+3FGGvGO`;?z3ei1%*>+8L@B=)BYr4Y(ASwX5gE4`grKRwiyZ{BPBkKpm>K5h| zgKv%VQp5e((Io$h@&65Mrnxy&fWq%19VHw|I@d=(uE(3EJBN z*c|TA{p#p#msP+e4$pjc!Dhn1OqV8JnG&|6SK0MgGN+swb8=$BF@j%UdV5t1YBlkc zruIpxWNZ_0hN}m%zq98kAvdn>CfP$!IgkVBu_l1oM8A507AUx~4!b03`T^-WKTXb= zx5!skJtC3MQ;vWkGusKtu7AoIkerqhbJPRYuH;}E!YewnbF z6Uxt5If5_A%X-=`QR%vhq_WHTq0B0AvzkoDP{pUPfw}gt#ch}baD>w%-bh%-%^`S$ zA&3Qa3agq$TQFZTPNg?eea)eHR1wJbURFsM1eX6~%y3gv*JMq2>hPfNf*mAg-G)hJ zUh<<=-$SrynI@{)L+&fCi#IxT>RL1`@obaXC--%U7erXCIG$sobjfip3!`G@+PoKx z`SoC=hFDFRAz!zmB0$HN#Yc1t?q+O!U7qlkzGdbR6GUu-uswNL^WC|fbMQJAp@OHM zWHKC1q|i@2oa+Aw^RG$5zry_MT>C#f0^_4sVQ`Tctv}*?h|$_HK2LNbMtK^K^ddui zf5D=BU75XhE!BPb1T33SzYP2HFyEc&?dDsA-xdy*>gwtmgqh=+qbWu8#9mycFAyNT zDc}_GlTH3&$rM8`&Q+XHtoGJ#X$I5Y_w^`=8M$VAF}!aNb_oY{9NrRwXBt8nr6nU~ zd3BFWY_!>1A`}~D8sGS&s@7@LX=a!`rRA2_ zk)e-sHu35qZwcSFHROzomL2mL2Ed+`W35Xf5Vd!$3zlAjY8Jr~utf&J7I}rHrQ~|! z2ZZ{dMeF!xIVdxiQYZi0kV8zA4{Dzq$V?m;Ly7Ge z&+(5R>xeWw_Kx>7%hBF4Oq&$3Kd3N?Hx-TAu$lH>k^{f>s{D9%j-p00@wCmT)Z=g$PK=J8_HieWcA9L#i*eb+;mHkud zP?0rNA(zf#8!09dF2)aoH&Xq83>uk;S)3uL!bU+N==`=qMC7dy2aWgQeAyjxq%nNsz?cEBtosJDH;_tgvZv-E%(v|;7{r`g|`iuJiGc@>vQ*%ud{e|}ZWRa%f zU;1u0Zj6%ya%io*E{GAPMt{W!LilFPhD9UD$0v8ysw=Q#-}p;X=1z^LnaSoykGCU1 zSIX_q!~EHAkz!NED{#n8O@A=m*;xoh+gIdYnj!>psf66Go8&yCZIZ|?m@jGG-KsUI z_5YF{iZe2<@|{PWC`BYA0SG83gnT(!T~ zJJ6^35Gi@sRRQ)O9JSo|o`e>No zqO#V-4Pd^{RWKly(UzBj4HYi_WoC~kl?4VG7M^4I23>5_qb@C4Kj9`Tn=_dev7l~m zIev&8WiJq@D8`tW`l`LU)cZtu)tH_ceOh#mpWh$}dZcC|r7vNwfo$bub}t0|VT#!U z8rgQM&m?h!b&>K7Cd30D)mv>ZiaE!oja)lD10^QRNwV8NV18}k+7iMn+wFU6kxx}q z(a+{||DC?tCQDd|!h z9|H6RGFRuJ1kG<3F}#t(HzM0$W9Oq*LL{(O*cm=xKW%Km4$%sk3RU;E;x!yK#bs?Q zD0|A79PY?pJtpQpE~HMmlhq_ZUNN#$K(^;Fp_cMhJ22Xym&bnggk)j5HVjmlT)P}Q zf7o$NjgRXGMsaycMIjf~WKUYrEg-q45Lffzwa$AHD++Z$P_m!=i2FD1o??gM5|9SUX?J|g6bmx3i;Eo`BfYB96}ci+b0It z#ZSn?c25GuMlUT zaO5F9`RW0-s0S>M9%a&hx=)Q}FMl83yBmv3APOv6bO&F-RrNu^T~ucHgKC*g4A_Oh zEvL@369?Ea1jMD9K|%zLyMB(kaGxGv2qB=(d)_2# zm-aHU4+Hj{ZuD9rR5rH(@D3xK<_a%RRDmhYNV((npOh7^4)doHz>Iy`F~~j@_hsp8 zG4}mx|NEfM1TrDn#UVt6J2c9^(07K14{uh5!J|clNW}lN<*Q&fzcCp9}HR-1Eh zuw^o1Y%QHp@s}kI&6 z!4m5sH&U>-cjwfg2OZ4tv=I)|2lXTAuh==!*tQ;e-_s0}MfVl)jhnd%GRD8?XGg1^2sq&yvXNjFx6--nXJje@C|#uzc)< z#CO{;Ojz>^NdSW+wRs`2M^~3M0ohw3h#in5#E5w2%Ne00AA(?Dz;zQ%Rz_PB>62DN z)+Y_k&MLNj)-8jnvb)VI-`}|7ZjcE8rII=p$}cC|32G};J`~Zjp^nJz+=av`H#WDD z&d;X@DL+asD!;E3Ql2%Oh&xA}o~Bnb%AeCHe&&g7{qo*zguZeonHDpyDMz0j2@9s) zC)Vg~$6X%cvMh~RDVJ`>pq$s$A_s%BImVBESsk-9<;_b6OJ`eN2lAHPg21}kdEcz% zb-Xw|i~Y~ODu|uo)m4x}9Z28656I&?sPR9e-=EayU)j{_x*Y`q5R9_hfznIB&|j7P zHl9X)>08jaF%5jO=aBFH_lL9g)af(226`C`85HO4pEM08DMt&-ZtGWG+*f`3xVuXuWhCjEitbW9TDgUsozNRwNK1sRIph9As z+Lr|jlE(B+XP;C4BB%eZ(5ER{{o)X6%gx*+CWJQ-TGCzCReGL+-%(Nzp8sewqvcBnlEOKI$4z`&q+9Rv-aQ*^ z7_JHU;PXnd*~^hMH@!e@{vM0Eqi9MJTQni_Cia5e?YzuwEMc^4s&a@8)Gp(}yEut~ zqcoj&L3TceQX^!_1V}$sLSnt2nel8l9roSjuOEM#AgP_h`Xp>_Qpr+N;xh%7#H#Tv zE_d=7HU3srj`!gVdLnX2%i@t zPe&4F_93Of*yaE!HiB$KpKH9~XRhM9c=`IoqaSi7SzDeFPdf5OvU`C4PWV{|+C)T4 zvaqI}|9(etTk!TG-KXGa+7!h4QR!l7&KDIWVNk3#tdfGM);nrsE3|tlx8#2n%j!6$ zwRFytvUc1lo@{k!xlg)xBI8PSdWe>wQ)j$AIN!D{rIsD{Xn|LQxbg=?ZKmE0L0zUb zgy)8>V>#v&O)C!aWc%%PoBc3ZOs-ANS7zyL5VJB2g6iE<+O2xVOCc zed)XCOHK^|j6>6Y<;)59eUGp{{Q8xq22DuFm&w#%OR>Qs&Gd(z?Tz;k0Mvq0E>mt2 zzP4VaM!gu`X^0T!{$XOR*Ca5fkSXc-e12O9oJLS(W+COpg^4&RUZsYH$}<1#2q!!m z#(q35!sBHRev3Jv!9adHza^8V*5=Vy7iDHq!tKYmFi#o|G_^b5de?FcRem|ZjcW1_6a|~}aCNw6+7^y9zD+YU;23;Iv6)DsZ z-jgKpAdRB++uf>Xl@DdB89dt8HQTFm7CkigBj~DWBe0a19Zgs@`RRI<{Bpe>{Ily- zT)In8rk1?P|Je6^GbPbWgK5;~XKI`)BnuWVonN7Rw6(#=W6U`9`B_ni}6x)$b8zrhOF+@0O_ zt6Op6a0oE_t^LT26M&+5hzT-3l7Oq+mYcb&epmGrzh&eETk`fEG`f@8`jMg-_QPu} z^}WC)!QaP^%KT3FgslEY(W1D$mCK-8Kth^P@CQWdenIrV^R(_EG>tim?K9t4+h9A8 z`81)bMkivuN)^;?lx`#}iUeh$i{=f5ERIap6y%MB?wz`yQBP*)E>D!sdPld%;Uht; z$Ifc3RA6IpW&n1N!FHi&0PD{F8=gms7fIBf*_vy}o+QO8!b`=a(;BT4{5hJsLYUvp zc*~mnUk@j!oY`l0^oBPqTmw1An}0c6&~u3%?of`{l{H$QJl*0fj?$yOA|nB6Ja6{G zX34|kia9TXj$ub2R`kS$y!xlgBZN+>FO;3cB|KPNU6#V6=1Mry<*eW9ou*R6-Y{?VneOD+u z0Q9E;i={L>1%v!lf<5{C)(n8bq^>0cYKNIEDgbgbzhGd0Hi$owRMokV^63!l+mEiy zML!^6SHfxVP3+EEIPwDdNxNW-^Bmh1&xU-xl$u1GB!P!z`dehr>f-*}!Eq=2RMJ5b zgJyY@+{$t&)o1a!WLbpN3HCh@jRMyBm+6eIe9=OMu}%~O6jxtba4>~zN(*x?d3pAB z{GF30>RueLo&^pdi{O~cPAM-GcaFoRE*KzO`|Tp2?6$mB+gdE2Nt8tH!R z4@fV4V4>meog`B}TJx`@desJ1Z(1GZtTyEzT^fPb5P?m5f&p8uygFaM7CNp!d+c?i z6QexV`p(y2oQFuhAmPz&lQ#if^D?8N>EmOaUD&?~BR8I-lZp>8-_EE`tn6WpB`rc# zPKfl}dHt(6>^jGNUB~<@7Y+)Vp9`Mdo`Q|m37+4Jvd$3)cy@g9`H3IMwMKZbv&9pG zAS@IFVFr(X0oCPy1*)B?Jl56LY5wxx3W`S7$Y5Ko=*7b3Xs#G2|# zlJL?2@ls{Tjds`D=QkmfAAthMf9j{eq&<0`f%)of84$+;Nj24f?K@>7eJxAI+OS9& zpSe|An`#3!r%5{h`t%)8W{|k;_-xvPw|M<=+VXNutnHK{@gpyjn4!u$H=8V0NKm`( z(_!gtHEFl;9E9U&Kqb>3M6kITeNU&H(ssi+@{2}=EHfmbIcHJ~AYS(_{e<0#(lH)pd(h>UQ={rR+jXX4B-^bqDYhGjvqe zo!xxW?JH_DD@j;_=|XUJPdd3-^dhV!`67%he)FN^5x!`F#LnnE=J`d~4~S%HF35E? z0w>^Se21-QdUDHdp5IOI+_77kGQ@0c?vOai7w<4@9Pmjot5jj85bz6@@b-(X^-^x75z zydxz8VTxiZh_;(cAjCajzBUArG};~yRU~n!lbDd;ZhvA+C>l~IzljnY&mH7K1ZrSc z7ce+ev7axK^uB8OQUqIZJ2k`LI~p7krh$;LzDm+P1$I)r4XN^qq{TLrmM+hG5nZ}w z`AICJ{eXooIA^$_b+C~IYG{DpHNO#Dl?3*>VQghLeT+T-_k>7Qyc*n|k#K>Wv~6WeR321_JLKk9zvjxjZF*`K5Z_Iewq`MHY9C?Z=Q#uvM_k$XEiuo1 z3JMrahkHj>%}G4Avu-0mW|1amUHVZ0s@Lk~eEcm%#KNT3o2CZqdlNw?EvYl8V;rTo zvf-cH;{Q4*&8lk~!D7Hgu$XK-T(Nth{#`>8232k+O+~b96MGa*SN93)bND6oh|Stb z4za|s!_B}TDwY6`n=^I+?IPb#Qf?mp(~0)`(KZQ?f&cbwV=LPj+hh+Dn4ULr;Am!L zz`jAP;8H7Z_DP{+LV4DV@3`Q6@Ij!&zSQiB@4S>vzGp~qtM=(;0Aim>6m>g+Qe`$?Qg1L}OnQgJ%X zPkGKM60EPGdz*{e(g+d5U_zm?tRirxRjJ#J^_JsP5sUKg5e`)>$u+UG$cT46ZWJU{ zZc9D99_*k|#$TzjiSX+Mlj2_et1XcR zr`K%UC`iFoRs~8J2EC||qzZpt@;Crc*o4u7U!gAjCwmvzkO>6dxTL#Z9bn)kEiR)% zWjjqOy-49z-$bHYZ+q0|I0_fSf_;~J34D|9#&oW?jaHV21W1KVOza-`rJ|c}!H1AA zSTJMBJDxyZ?CS}k$tolCh>ehAMxZajZjR+d#p=F2b!zP^Lu?gYvY_LGo_QH6wAY(msidams!O# zdIN~!@}7pl8vwpAsQl;v)=~fGL5ejxq&>CTGT<)8Z0!SdP>Q_%S+fez)De4=`Rqq` zd+1+gheV8Q;|Xu4pXA5aJ9n8WNz`I@Q;k0-o1gnAAK}VHwS-0p(dAyQ?lObe*$X_X zEUq0f$KgKFoEGI%zk{pKBx2Jh+)kKf>`pycPS0FahYvNb%%x;-kx!?`5<;LpNU|E5 zuBM9^88?~8&d=}fWXr?7N1~UU53vRAT{tv9Cw{*2h7E3+Ws7w`LvSww2K^&TPF;e< zZ}j;x(!;hIJiW{FXAjDtK@t@kw6XOkhOwxarz1~P)H~gdAI?FU9NzB_EmMcq3nr?# z-I7%?Tfm#^={~b!v!=@B%$$`#TQ@=yBgYZq;|6^QbP1xBwS6Ci*$-j|bnBn;MLd2i z$&LHwv|x%))XENVQrwUx2G};tCp6=aKN}L>W*sR}YKeOvLpjY>5uqc&k}=63hCoZf z33;<`%+b%z!e2&jN^SD)#e+xK-#%~n%8HYo&3o{0*O?h-idPhm_vHlDhY>~Xw`#w{ zRInDa<}u7yAiF=PZ}O}fuLtX_KRpE_5y2LADv2C7mCmUcJ|_7#dUT7NR~nIN_@< zZ>GDe4dt8Lz;!5i-nz) z!8?&9&9`_FX&oY6NS>7MfLc0yjexrcU~FK^{+1P}f&De7`Himj|K|X7)?ha+Pe+7R zbBy5ucQj>5e6|VRC_?q$^R5XMm18%kheA4XrdMmD^)XQ6}_ilcgCz+ zNh6Yr(EQRWY+i0niD}0!yG|H7*SA&c*|1G%vEYl%60o(M-2LWN=IqGq;=?(=;Zu@> z^|TY%XZE`n%##$^KX#+W;Pn?jK&EoO+bg2rgh0wg!aql4vK?UxI zq8}0G4w#NU7)$k{uE0L?>6nTn(DZQN@1>I_Ze5KLWqONOu{S1VVVpzEW?4JCO|eZ& zZ8K8+{5fQYflqpFgVf;IMT)cB-y(ujao*sTkF@8VfrRj0*3MPPYyfqHB=yk)a3lZ7 z)BO*>{EYO1K%@tj`_qU51ulS^GlPevxd#LbU!l(Ure5RZCO>gQ@wh9(UT(2tLp951A@2lihgoY|V~A8l%2U ziIvg`LG@Xz&?_QI)O)B@&@T|9ACP~UD^eR`m%7N8d5WXa!kE7udcs8IUvQ?7a@Iu4 zEAej5lBL(CjbgVR*jFsojY^*E;iRFjj!Y4wodzgKWo9>55I)>yS#1fOMHKv7)cI|d z>|Yii87llnZ0JW5{!g|zR6hw(6q)~+VlD}-8*@tKp_rR9I0fBdWdV^g!y~#(&GEshoRQ^$`|aL=okI+DH*!79 z*!Wpd@AI6Ezw&d1&1kH0GE;?zcO0dM_IPpi?s z9|Ao5cYJWrNuRbZ860;I?y)xG7^@k_%2s?9>eVm@GCW5ze1eL%)}csu65AV}mxIHj zLhIm7H*59KsVtk z29DG5WvP6sRcBz5Ccmt-$TkV>H*}btcF+!*8oeXEM;?2Vhe{-K9V@Z0tR&H&6RFsd zn?xzm(eB@vZqtENglEeA42g>eEccwL_<~B!w^pebK1?S&V%9xG5|T`3N`tz`Y5C*0 zNJ!Tqu;m_wQ1L5uV{d}qD6pG9AhvIYX2gdcK=W-2v2NVlM3tt4O9zb_ZwGH_>3^P& zMGc#E$*p31GjPaFTUBwPCsFY_qJI(c1LEKzb=$CzYZba{ByhWWm?`gm|Dj<`nLKm> zkLA+yppw>{d)zSv1M@d9L1D;|=|;Zmt+@>s|8!r+vTnTy?t8gZ=sF$pQtIuk*vV*LQ}v)k+dVq_%gX-mCR?$# z^(-M~=}W{E*g&^(wT>}o;*{)`UEH#n_Tl%#-3N}xV`*=3e8%r#r5JJ>@S;6PMhz-} z)wmgpBOi5PBcVmlnVurCUpZ*L%rNgmpsuh5`u!JxQFhNPL59d?M0igL4~MpN-c z^lH^v%*>4xNArbedl;LI=5^JjE)R9Zs`jn7sbk}Lu_dW2x%pp&M0_VU`8PHaVt3^5 zyDo0i-$wkKwDChE>;EWMrH~BPQPg;h1AO#r2Chl`-lTP-&xaP|gEEH-*%INq&o5-x zAL!r;)84!>YoCJ2G2kkl-30v4-0s}&ZoNVGZ6gmQW9@L~2Mp`lR)Le^IE z9PM(IDMIfRjdr!A3cHaVefMDL2GG`ILfnHr#wZ}gJ>vY;D!ZF^wek(Z_6vE0mi5Mc zjt$UI_2`;Xr+95ktpBtnx4sa4uB>hte&ablBUhtT`5{;QzNpu)g187?XKM^RHv=<7 z!7b#lO&ByhKYdZ6HP7Xj#x|t#j{<<7aoqSHq?iBuee+Y^^rhh0Ep^x^dgI|Ex+yuC zfBf+fNll_YsYMyOwf&&d#IN_A_&RC?LL*-1gg&zbrrQ$!K%D(%PXSo??it7jlGJOe*Q9_?a9&Bm4oGaCZ3aK5-m&2rIt|a&H42jaQtAt%83* z^3H6A8mxLmvrdDgzmW+WonR8(hwRf;}&<4kMmR+Gn%tK-QP+nDss#F^w}wq1t-^ z)h9_FkLg@I%gf-)Ecbd~PuK}byR3gXBN7K$eN$gqlQd7DH+|eo6$6=5_OMENI~$tF zs-E>lPf~zXOPn${O+WmU=*KMPguCPYW~i5m&E<9gU)oZhtQl-OvASt? z*X@y3Q<10}&HFg9q)4&U8SB=2cep3rH5ck__f4YZ9OG1iE!(s57p5YK8q5hD?lIO< z-%YTEnDZ&P#FphNFeFU6Ma_vz;;kiidrZVIgr7{eWQm?D_41lP;k0etF`BAj?f`O! zHEmmu3Xl|)C8i`xmP+Cil079$qgcEnjK=+mGmZg0fFse&!ou#Zg;*%NtW2g*f!9^{ zG&d*9@K7s2OT#*t>%wWP_a+0<66VLzLb^) zafuObcKvfq?2L*ac8%Z{;)3mGm$OOm0RBn^IW4HKm^v&75V%lY1Hw0 z;pU!;4*O{}2#MpShHM7w$CF^@EBP)HhfKftbn%h^sUt5$=c02!7G*dU^aT_WQT3G=;FF*Jop6luU3j0Q39?y&(Xi8-*VADdRA6S7yB;p{=Wy7;3G^Ssx4>}F zwfMT>?_Y=8C;w%*EErz z2kw?f&(Fy((SYIPXXhZ3_xacGG%#GT@h`)HH=LZSbqR(ug)#r-4-dvc1)0Bo5ZOHp ziWf)0yNv$<2}-$T8zuMKC+Yh~n15UfV0H7Wh*LE3KR>Ae7r*{wjl-Dy-~gP^9$TOQ zt{hzA*}QF{7tvl1a7ECFCQ65#Gyvrw@Vr*h!*emG+0&(Jw4y>d>Zf zn~d;430p(O{|MmLe!FC)R*lLVP&2NHsN>XvCQYB2EkU(9ZuW|_acubqLxjc!R3VN3 zJ{pWB((*i__eLr3&WJ^H3Zx!vbs3^Cf7*dmAhBf4O;*kr6`f&{@91Vw3Z*I^Os}Y_ z@oy_;$kXOyn*Dy&ZL99uy%XfDUa1rpuRdc`SrN(bqPUy)^Xq$2H28YK))L4O5MJ>Y z2tv31pMrgvTU9X{18lhub91tMAE|Oa5t8S5Z)evwE3QB)od5ix@jR5>z-i`^juepQ zFl-LMvRGh)HKz{2R^N;Y@>;-IH3LL-kBkL78WwG?WH3PTdEtbr7oa7t)*25Vn&RE2MLace|p1u?5S4Tl&5XyMh2FN%-&V|ca))|MP&b=JCUK#(T# zmK?KARs6jEE@;rT1Rf%8B${8HsMY+9GWp8EFJA==mN`pId2yzCF(Z>=UN409tg>!L zHA7+h3gzVaD{%k8PeuzH($BAOe?aazzkIkNIHw7ES~;yIpOOOt7r`gzFmJxsnG@oC z{i~aWRv1+`+#c~}MCr(V<>%z;t8hLnG|pqjgLP1j!kcRx05e}s{Bb@{c+glGCyH+8 z;mjS!Ao;<(BXo+v5#nqdTTB;}6|9We*_#ruBm2?v#D|=^A>H@T5g?=yN5`0#C zGAj2l>a1SI;DMgEpUltd+TK(hPE;KoF4s&Ew@gzE+qw|PJK8ppjO=y9Z!e-jUx^9% z&n`?3s!oVr<)({aLB=!QQQIxg^Bl^c2o*ari)csmWKBfKT-m5@G>t|%ato}aM$az= zrmrwv7ZK@Q|@dKg&?%NdHcWG+>(b`cgTY2Tsv%OehU8e^#;S|?5Svt7PXEj!j z>gH9AAqantJ9A|VGOYtd`gTd4ec<8U1rKlK*FVYCbd+ngf8Dw-nt{#O%CS+gFH;Xh zSt2izVy%)*j|!FZ@?mg(2G}M&Fjs5pYzQl=7Cv>NpP-7)Z?V=)FotjNpw+#5toW*h z%m2Vz5jKamCwO@P%1Ssu7eWmU zb>H76=)qkGijQQjrhrp}L<4peyXHaDG*w9`Z3O?r0Q38m8kG@lYkJDVKOmphVhE4> zRFAs4fGu1YYzNx_29IhHA~VT66=_w?j55p?CW|hb5{gW5sYXK4zs>3&#>H+3$07$i z)|M(sru&VL#aZ#V(@PeQVk=D zLY&-Iye`G{Nn|LY&!ns{YPM=4ccduW(%~C_K6-E0KOX&!j6BX))T?CMLQN_nx96#P zF`PBaDW$X423yzn8gjCp)Fk+#Zj)fS1RDOfLOi(0PnD)=55e1ia^1z#w2o??c*|Pj z0re0{tGl^M!Q#Y4d8KY&R8kDf&l73$Td$)7{JFx;$jJ`~NUwxankPPb&YPNHZ{4{2 z=~C@#>-u;DZsG#F-0M@j`4EnA?qztpzKg%vXQ@ufDTZ8}B<;28Hn-Bz43{t3j-_y6 zyvAePp+_1!v1yC$593dpQVU&Xnq>gFI1DoZ%uuVJP{p&t*Qk^2#jpSOX4bevO z!9&g2vp6Y}xxDTk89bVON)CU930Bm1Ch&em87<^xSPIeyiyl(7Ut;fGs0z>y8`KU* zG_f6-(7N#`M2Lrv-0;I`Rx%hNhGC4_adQ-!%eo9KRpuKyeb@Nd*Y zq^<@gScgMP+OvU+ zGypk+LX(-Ro6{wSjJ(o~QunHBO?;t35#J{n5Fu*FAu})vB%h`&O*{_1@6q`KzKkCsIl2EyVkDdm(rc@s}DpxnH5&PVpLbrur;31jfagKfDHkamkSKz(dzmEVRNxaEvGpy z&oLhNDTrkB$s=+Nx*ehM`GBp2VB`g)AYPt6i#j2~kzhGGHK!qej+Z`18|y23F4uz) zHS4_ab?mlNE<)mWv$IyAC~r*q9hDUK4D#YeGE$*(s*)sBeO_PtEMGi?>z1vy7LYuI zU{*QtA*7kvnAz=~NV!Pl>3Xu~N+@ljF=C=oa^8xJL)eB)_wSm*zPj991VUpdJ zq@dM%yHBEPKG(rb;&~^?#>H@VR4n;r(S_UiT1746iW&%7$z(ltOoodEz&7@G0HL#NeY#(}qQ11WwCWoZ zt*_+M9^K<63lgcu0^$JHlcFl_lfqksD11^f#rtC+>~ci&7t9-tlW%^l$1^Wc_|VW4 z$!&dA$5=_yQ1p&XlcIih0=7awXN;-d9U4>9f$zGDx3gyrTxH z5n0r=js1t#@==5tmwo%9L0UMSR-ams#wbP24i&GI@;7DtuM!!hX+Hv8yviDJ&%u089npEZts#JY+|E)*+% zvyt_8zq2*Y-H&Bw6eDEoOzQ2m^DJQOi<=0Ryw6BLTzv5vb*kO_9g3hrZDqsY;YPgV zLK50HTcC*7^nQMy!cx47vZzij-^5w?TZnH`^lJubHl-kg6R~Y!f^{mYE-C~E$#4(e zn?n)GhP&HQ3`EJt31*+ZV>`URS~)jWx$pous^>(K5ds_WLgppszz#}A&rDS2|6=bg z;PP6MebEmK?(QzZ-JRe;g9Hc=+}$DYA;H}>NC*eb3Pbsmb?0k^6t&l%H~|ZS8zOZUmq)9tB+Fl z|27KM8-O7L|CL-Y7;nD85k;Ep#e^+$nK0hBWSsP?yu?^1BClD=yEfLqj(+$CKYvRv z8-0bWmsR!0`)oGj*spS+B{?=sxJ_x7#5K(tfo;;Qd@`@a=ckkLp==j3d7 z+xNzcnYuLE;Ld|HbUc(y3^2K--!xpM#1C1c`RLA9!HKW{!5?@IE~dR^nd~@A?qC}X zW4L+~1}R|}HQAb9A7}`!=ahQ?BBmN%o2gYM>wjb@e5pSu)OA@YUO(|l;YoM=Rp(G* zyC!;uffRK38IO0_FHeDNb+6;aCk`{`uCyo0$}tJwr|qE6P*Rd*M8RWO?B4Bi+SB-nh}vd#)7sudO6K=r<1E!5StcJ23(7!B*}Lc#V3Znx zMpaqR#~R5fRz!iO_w*4l>{`AXexo!sJ+&xzc))gTL32vSMuYAcZ{)_!N0}Z zqbRF%os@aRSuq3|#=b27GYcdgRe6?xZj$W~nhFO)oTbq8#> zgYc|3D9j@)*l&8b$zv1sK^2hdog^P1AAjj5k>aO=GBYf5sMzMNn2YSPPIiU#%_VSC zQf%~S2*nvh7qqPe;QIuIw%eWG7Mg*g;_I51?wPw^^uKAa6Nc;$B^zCZ_@fHSeFyO$ zKCdPtGDsI_>;~!8;ZS~V(!X>8)MH}H$(wH=O{YR~?`(&9pM4`rz%HHUnot*c+$^W_ zAa;IdI)0E?KEB;&9xB;^8XJ(|Me-KSLBan~Na^#f&7`a~l$C4ouvIj@l&&Q92Ys{G z`bBq(O4|O2n-h77UB{qFS$=#SwNQx%3 zxcmIT4q^9HH^`1&)G^`^gz)lkJ?4o=N9*eH%~Q=bo#hA2ylKVgwT-FTNa3e;&hnj1 z3&)Z$l|x@@tmptyeVL({oAn8F$r;J*5+Gv4C3;-|YWx_#u9K07AB$M8Q*q-7by;I` zq(Zsv2231TFvQ#9l_t80ma-EB*xj`XEL-GA(o+&5u%1VnLDPk5n$U zx#Wp{9h6b(nrLcAJ7Ovb%=9nE-csJ4(a63LGM~K&2$$lF7OlyYiy|=**H3F zlnX&w6jcQ4i^o_}g?3Wg#GNK2L;XO046d@xFZ{X%ht>tBrgpKydq)Zldso4L%Ib*< zbFDGG#t;rhHvck;85||EPoW_NOXiPD7BFHd0-$=40;k&YgMs7j-@w;tgLeW8%3FKh zZ7c8id~kQ27g)TSFAsK&zj5nP2dH4YT1crWCDPU%spkL;|8{D+ABfDH2D9`o(gEvm zzs96bJ+Q*dmFGU9DZv7^tRjG_l_t_hnh(N=$0a&>&F)rGtd!LsOg}Rf4}lDyEI^7E z(taA-QRMS(Y(1C)EOY*DPAU9TQ6<6^0^jOx^J>TDn@%pU8QRRWtFAo)i^$#7W>w8ePsh_{ttc7i~jj1IqGS%nm?Br#A;*GXu1R7Lgt6 z2in+DG}IqYMEAO}4VB=B!m88PsmeYJVZ zD-lTAyh3_pZ#Ajpe@{QXW4lB!76G@vga0wyvKoZvR}YFQhCizDR09KuCL)i43aCKD z-!H%p30J2M%mF=r^1aAP?qJvEr@88q;ilTOw%uqvnQ0a@3%K}R{z#2pU=QgjFw&y) zS5WKa_84()9&yc!3aCZ}UVeS@l2}!O^zgpDvE zP?3a>@?)qL9+5xXD}PkJ!hh(|ub4?^#d@x$x2}mur=B+GUAZ014`;Xq=TDJkS_!mL zszrSn(Vq5d4l!Yqu2h^cVBizDT0gSa%#us{WqCRJJN{Wpth6E2HtEy{)fhnv@Jm@! z%$2r3A+u?xqWAYYAW0l|&GaZLZzE}TawfMp$ikYQl*13PmwesX3D=5!MPm-FiYiThXM$sEe}qt5oV z?)&_Vc)SO=PLUz zYG>s}dVTJ_4-w9GW&zUx{0e~4fz2s$k1GLq2LVghgV9p{_^%lDj}s7Ry+ug42>R@+t_8sd*C5B~iNytp zr(r^2uFddTv%e27dSIXHRJj}gL&^i}$`cHLvGVW7JL-<+cUvMX@W2m8eG&3*?zfr_1Ncvr#?p7S{is!O8){Z~U}EAnNQo`nGe1wU5tlKVXiUxO}jTox>m0QF3!Y z%BQ=0I=4@4X4K{*dkJfE$s++jb2_T*%H8p2m z({Zw?6XDY4PIT<$c%3-ny5h_5W%OS%?H^_sPKd$X_bOD zU;+H(Wq;3U6aQtA&j;9?8>!n?gk*zI#WF?@%PH6?zJ#XtL{XkZGvI&4E-uo)=Pt-$ zi6je{diTp~{xbDi{519MyB+l|tyBny|0K7~82sb7Q6>GC1E93z#bwO`i&dlm2dsAG zl-bm_H_ozJU6X*Dp78r3%XRZrBLlioQLuAk$4#s0bnd6{&$o`2FFJ)*rZ|t-WsK-b zedbYE;e{$M1Xr91vi^QfrXoQ+E-UNO#Caqb%gLlgC5oMWRvLjK2F)x6n=ym*$2!E` zI7Iw}jpg$@c!KHEZ^X+g1H3u<8=63$g+3%wS+^W>#I~JZi3q zzaW2y-!{^A`c^N?!U&4bHEJ3=RQ@$mOg7RAM3#Xj!&m`|44vzp610C8srbKh zza~@3b=Y^1+>|X@O|7ohn~z(FE)LWMP^kzdCOUB-!rKE`zWK?SEUUE3`T{G@Ty10- zPEBP=8!M7h^X4neqyo~mQ`^W%RSBJ`X72zjED^$FHssHT02`j1 zxO`sJ?R8mKg0-lUbP*IEUxkj73Z*cFg@M&sr&z8JyvgxQ`P+LIoAc+1worHfI zQu@EsQ2(80)xEsty&4Z!{T0Tw<;XK^D2)=dK-(1qyY3ek!!IjDCRdN0g~_LxYwb{w zMQew|&y*V~!&b=>Ix#-b^Tlkwse&v)9yj9S1rZw)SdY2qe+Q|VDp9Nr%q?PJHUNR5 z*aVI65*41vB#>emU}tJ>Z_E zkE%aXr`;Me~8`%ESTqxLbMkNYt_#OE3O~(Qu7NXdLsH;Fv>VIWoIZN;O zuEq=jc6Z`Lso^Cxccorl^@7MdOc=sNXy2ad^3NXZEU@^*dG?RO!3u!9Dc|ZkDAgDl z-r?}Zh_$XiJ0<4@1snDI=oov@YkMtosO;mmIn>~?rL7gkQ^6_*_?Cmpng|s{e>ZIL zVns!{OeO8v(r6?}6C6MIkCWt+21&A}Rt;KO)Ug|8G3Dc;gkKx_d!J`$wEof+|DzN2 z|4&}W?z8eVO>`(3Wg6|QIPgff-8-tDtxrFVaAGXJM@^35cj#fLc<;+D$Y$hJ;O?_D zw~YryHs zxj6~u4TvhLNF9SHNqQZ!dPQUxmtMeG`1%##+~lmO-J)s3pup&Qn|Q8V8iz@aFO6PO zX*dr73(MOLl3iI8QJpYp2~ckH5bPUwsmi=KG_6}?yj~cR?M z4@F!Rr<7&RJ2sS`^uB!@dLvw6bs1CjYN4Ng;ouCzG*g0}xQ%6y++{tAKeM*}B?+P! zX;2Jx#${}JNi~rhqyf2v1Gy%cHA}VJ7@b3K;{u>5QvWEDgr6uY`zskXZmF zvBi67Y~!iGw{-EP;zQo9?wd(4Qz~j%F5$2)c`^+gD56`hEAyIdB(7rQ8v1TMA~{(w zPqNl}=N7av+sq_=JSBwEt>zi^1e9A|Ynuvqo*Va+&+NU?^W<2Y^hxEj=O&sjh00iT zQn5b#+*W)>9HlkyfFXhtu!Ozm!@1`#V(XPK<*9Oc<^!69)&2O7eB%BKp8z&V*x5Rp z*g89r{a~Fci<*bM35&9UnF))kiIbg+qmhXdaFep5ozV*uXEGfYn{wb@=A_e65ga2$~Y`v(_L-(Kqlm63}7PQ6P!NeN40(p9Vg#i=bnutR=~Osp=AAEliBH(VvjX&JKL5VP`Lsq4uRR zV1R_6iY;q;KTbezsKfSzEY!vZ>up&MRULN8k1P$*M8`#6>S@TOWo0%}Cw^5%_v8PL zhCvpp{4Sh2by*oBho2?37$p04mq=3C7n)r+K6JWkA2|C)B?_5VzT>>dyC^#W+yHOR z?+;1k0HtEwgFTfDlq1WDCb_Mx;*Ad!Lqz}w)S|M?|9K_IEdLD202KGO%wMsb?2a8E zPj)s;6eMfSKszzeU-K8*CM-6MwPWQ#vY$1eA!R6Z)D`l$)PTw&iDJyp(ZT6R0Jm$v z1GIGiAiVYmalf;rmSTcH4)~t(8X>Fl8&LdGolCh5ouO?j08FmiPp7VT6I}wAd>u_~vBtQTSC&Bp$7!8DANBUR{}sOQ2$vCBuE)U9eMh)90~&lAZK_Td3K=X3>f~# zG%KyH)3w+wdd=`+I*=RZy^9~IP#ZeJpZXkhQ>}DfZO8&)^H!rB9;sgso`~Y zh`B$+{m2N}uc1OIM!-6Uq7K{W2MJfSoftEbi!&jBv#&4BR@_+tFGS%BHqEW7;q4xDE zkUJTBD;ZXr4a|JkmV6j#Iy5$itOeGEdl6h*Oh!-O)X~NaI!c=;c6` z{+;Dr3|Cbi{?fgfj}3}y_!dt*>R^myVmQ`G=UH;_u&qb_z}hKiv-{jb>rGX?HBT3$ zNnXn;Y;W_y!NcO&#PFj}{V+36bTcha{#51V7sZj=nfKPw%+~7lm&5`*uo5d}{eOH28 zR_Z-CWfI3bNj)T92(3JG`#qWvm#DI$kD6X4qkDZqxys9vL`5C)IO?CQcdax@>DFvNN5mQ%bcaO?f|_QeyM&b zr1FxMLbQQ`+)fu%$6ZdjK8kG^|EAdoYqPnk48h?zah_I}{)08wiYELDDOGB%iMWi( zR)oB~l-DUT1R6W&0ek%0kar2auRMdaTnMO#Zbgy3u6EyiEWs|2-5Ov@CL({Q*CNp7 z^Kf_jPBWbl8qI3r8<)7?+Se>;)Y0_)wVU4h-0cUS`Ufk~`dkTTF6ugVKE#Yl^tXtK zxYWYPmL8w@lh$q*gZBqM+2R@tupPMj3LBYHBxpUrm~L#IoVaLiw_8g?JZC&r$MqP= zH`dEr-12hK;S4FaBMM z5`2TA4)fQP&ytIo5MqPNRXq;4NA>%=l1Z)SNENNs#?P{h-1{sE;HTeYtonSKCr3kb zNxy*p5b)X+UQ_KgJk9&mUx#;F{W@mrAN&6gh?LxOa@?bRc@3ta*l%sVX&qjhZ@ zjtIKs1eA+<$v6Vs^+d`vf-8h|KlxM>3998r1odgn*r6j|e2g(-+g&AN9+V}KYwt{p z6noWAWc4viQBfQ5`?}UFlArGx5t2n=fC(2)E(*$;r#3=(O@RLnTL`Y;%s2JfRWx(j zpqCul#$9nk3m%50`kKMXRt~L?ivpBi$aE`ywmoLT>$fvE3!Qx9Wds+x5@P{O!;_&2Yb5pp{WbKi{!lZLvrN%vr5;;>oRflD z06#neUMk6DuK0Qck_0p`hwe>FylXu#f1xAvHhlslu5lJq+Add(N1BLl_N(Tvt>^UosTYsp_PZQ+QY552P(xfAw(XK4)LDkN{ zQp`pOqg7ib&0ObAj9uK^p5G4d-frL?MNOdu6c+ZoBrEsRQma|C8|U<9KczwJ+d$*) z-3U>~9G>R6F+86v@nz_Gp41{=g*6d}w4g52-9yG)6dW16RaO%4y&SB?q}leaMc|5* zQ|`N%QCH@=M;AN1WQDyZxU@W&Lb{)X*@?0gL$IPU+AgHiqYS&3k&EfNT{mdb6DiF> zFZ^Y-w$rmt?P@hgMky$vkc%2osCw9{<)OGmn)E*GOTS@{;ZmgvyO#hLxAkQt9`<;? zP_=&D3LUgqg*rqtZZp^r9ZoZy#WbBjOR$0KJsQ>)5cVSFgzgc$%m_lO9QtfJJ7qDC z)^DWG0Y8?8!u@vrN>2jqF$1a8QZ=8;o<{8fCt;s^1^V`Qf347FjCOnQVsrIm zZ^|y0*+yDoAKwY1+L9|zHl1A|a4CYWLQ-0p`sJMv6xwcO2Cv~$Zi_@Lq?A~n=mEcm z>Fa>(+_N*Tv$Tjy5*SHN^1WBtHH#zQY}+X`q&>FcW#Jd+dg-)V@u#mqr~&G2+Z&=B ziuUMM8Uaz}g&q&KDevn?1S>OegjSX$F6O0CIM;ia42L;bKICj&5bA_2!JKsscn21I zm(%>-N_-_${wU^imzbT*QhiacaOvJQd-+CG2eM z?QDOj6TE-b_}F;3S^3!hPzS!xeqRBh$w|pdfgm73APC?e==(fK0tENu3G5RXI9OO% zcz8GjBrIekL_{Qf3`|rkVggbUVge!}GAd?TG73gYA|g7Tr;My@oSdAbw0uIm?1Ic3 zoa{d`fq;jHM?yrxLq^79Cnq9j|F{3Xw}a5(plM(dpdctfkmwLl=n&t#K%_uDVIY3{ z1KhNK`-6alf`)kl3kQ#Y2;5MM27-iuf`WvGf`NgC2JZF-u7jY_VKB(q#GYWP7{F3E zV6pqf=D<;kS9V~ljvZ5R7&`jHBjDiT;S*5P(9%7n=j7t%;pO9(cqS<&Eh8)ULQP#m z^QD%yk+F%XnYo3fle3Gfo4bc+z}vu};E>R;xcG#`q~w&;wD-9m^70D`i;AnNYijH2 z8ycHFcXoC6^!D`+j89BXP0!4Jom*X7-`L#R{%CJnE*AtIkT0Ro@bf@>g zDHWm8Hu6X8sWDNag5-6jn*);@)Z^U2lY;xps{7z;O-&$tZl->u$aZb=hREk=mY%G$ zxxrJ?Rb5>yhyf2D&hMbiY5f=g%u2A006c2N(gzN70ZMuLzbz$m6dwqd^4pCpe-v0Y zh!{%SGPxe(Uw1`8cg%L0lIsJ;$9H zuHWvrY?K#&(53Q6{TNDs*rETwEv32zye@x)Xi4w}XIw`D`f`S2kaL=S5&P6XhP!9a z*Nv!hMRj5Ck)Fd{9YcX;>>_WTQ*};o3m%$@5^az@2-X&KkeMG?-ZrCu3Y(Mj2UCCU zS{PP(KnQ|i+X+b<<~d{fDC913AtR z-e=knw|mGPOBp4Uix4)T6>4xV0m2-1^2`cv(aGCw%F76T7PG_uaeMcG*hp`&|lO>g?ACnmEQLX^{@$_sBqmT@}~WomKK^ zv=)x5WiO2}iqsGJFcp?LrA~n%BtRe@%TpWP;wOM?utM-)Y$x zD-ffrhQ>RJKiGP5nP;&^if)l*TxU|tfRfQcxRugX{w(8^b!fq8GqNd7bNoAqEzix! z=${NJ`k?p|ifJ2!@okm56y4f)iCt?;Y@1t~mvp+rnRrCo^<~x;pIB;D+}zf4Tz8UJTytUpWncjx#& zIrb;V{-@=LKl|AK_xl*v>N_Rnme#h~NhBNUN+>$EQL+b5P5D;^L2VnxGvK|73$Cdz z5Wl1M!ZNKd-{7tTKGcDa3c7;&yYUZWuX>}w8~Ol_H0}+T^9i_E=}HpB|MOAE-@hZZ zGCYd&16IF^$M{a|#N<41pY$srrzyZ$*4;|=pYI;hXBK!`Gili81*a3R!j0GuLA2}1 zb{uG_S|vMqY>m^t%zbCXE|gH-m(Ti@&3=1}cYTHv;>*~p<;%r|E0`Xl!#CkfMj{ zAE5wo3Re`Tu=o?;qj7&f4_*-fpE!H`a`P9MVtPWpw6%dHGZ1HNNesVn#N;GMMQf(% z{p>DUCxzTtKW5uuwucT`ArTobQRY-CPNNrZ*8^6Tj7ebARJR)jLOV%H%I(DLhz9e7SWbO`-@8 zLqTZ;8n}<2^!A|!=piBBpx8x_-N9;gesG_X&arFVB(SE&jN;>J+Nv#{Dz|;uI&MT=u3S0S07IL z@(&IDO!*S%?dH;>Y0a^1?>?sqzpwN6vQRIhU==@pHHa9}2g)&it)=)xjEYEO7|Z&J zP;d}uEAvhHzUtN!GdI?}jU}nA&5&Sl5#5i{rNb zl7jFDRd5p>#N~GWVl~Ch5*elvtmL*QC0|#SyIHIEQ<@qEu`^W3UE#5*ftE46$!{ zW*BJWJE-;z8Zoh;WI@+}pNLDThX*K*qfRVSc4NB?a9#OqvsIO z%tuU80AcJ)KhSAbob~V3#k|(qP+rY0h&^e`ljn?Or?T)MgWb)cYD{um|Dm*!X*ifSK5%Om0-UKES6tdYI?&Q}CnjMMXv! z$lTMOk4i)6qIhYKRgAHo0k1yxveSu*Pawf~-ypM~Owir45A*IoKI=C06(BM|lxTSt zgmAXv=(t}HHXKBDP;keS%i@hFiOsZ<9!GzLh!y}42Raga0eRz9R)i06TS#U%6N_;W zT{ynp)|S>NZ_k%~>0LUg%GNZ#8ml4-XJ>PwAgKkoIj^uU<%H75$kBo4gN->YEtz)Y zXHBY=4-@xL(W6`oU!bU6qi9`1H%;*2-kP)q$&jX&E+5pQF%BEJR^H@4l?B{?96S8) zmqi4#Ru{E77$Xr&8AHkOG@Kc;?|h}eY%eR#d0bECdyx-{yNMzh#4aT^ZD}bjg9%0V z;VEf_9Q3y!p+8Q9e<7PnKO#t_VSjFlzKc>*C==r7FlO({frG!07+`!=o6=FL;pRr0#~19x>)C(pG6LF%6%{~2 zs20V$@&xc4EP3K|lsHv}kb;OC#Wo9QolqyZtas}^>U1-mhrTxHdwG~AX>`K|dn~kD zwi$exmsDxAb))yjkLO^q{>oyWBDLfjOW_br&&IDndw{`iU$|e12`@?%BDC{`Zse)k?mAPh;8&zGIzb4 zVEvgPxS4L(Ah*Z^7Q-k$$|$W5l8A)7FcQe~!OHyhR)7Z#_tm9_gE)24W;&mD4!V?9 z6VU|}$%CX3Fv&6q#=m;VeWAs4m=~t=7UxcP0HWt$78DzQdZ&?iQQLbt{mvU&N%+E>7T^gD= zb8l8nWRAi^27S40pyL*fSqr91zPj7g+|@PJwy34ahf<}po-o=veT=vuPOleq3JV(i zjApS@Ak-4WG?f}t+g=Be$5{GgpXda@B0mtH<*zze4q-B^wrb{Ms>luuo_o#%N&$@E zI8U6S8v0fUW}sQ2i30k#hGgIGa^F%gyg@RxAApA7tSZb36$J7Rp~A+Ql|+RJVa*DQS?lt-DxDveg(VA zgXH+=@xWYu6h92&zw6d!PWPbBTRch@bYIAPkzowU2Sp554EO|RxH~=ii`+meJ<>#y zK1!ovfafb7!@0i9yjmAeS8=fUDm0^(b^2+Wky_iLW?a+CY^-)+yKR;Cc>4hwdUkXphDURVUgUR7f-BhIH7>R zN@f@e2o$FTMHKto#!XsYKD}$%RyzSny8n!!Cw*(+ zMR|dNowo`5sFed=+*91#r}$4wm8bj!0Bj6Vm_J_1=D$jo8~5yAPiPvCXbT$4tNsx7 zevvB+N-aYR+=C9~tv31J@{6PsXVfbijojO^20=Z-MBGh{{v?Bzl({z@$xNn=Ft`(A zWBGp_rAIBZkc!w-kU}`pALzl$P+;WZ;V&Ol68n=W)LgiDN)mTW10vN+};eY44Qu@}m^nC^QLAW1U4BA)*O~j7fYlpCM?J z_6tJ#&ovPrbkNolZYl$#3tmB#75e}~iDEc8tk!F<+LHO)+|Dp0@nanKnO&-zt$ApS zjksEL(>2*f+K#iX`bDhJ2DwOesCu0>@uBF=>@CuLLyu#@r24#8 zD%G_g3XD@#;y_0i_wHboG*8hZ}L(weXzAYGXQ!J;Z$;k7MSbZK8gnf-*D z79!;FsupB72H2N=!0DFNKit|q(ntRQ3e>T?J72z62g2BBiab<+_kdpFlMW~yxpx4V z%k=!?1JHM{MTudsN56xtmT%|5%YfVHT8X@TbJ{7swoQ7RLV#fm+#IT-w>jj+A0zAc zQ6??O;9$qdETe^%Ls<^jEh`C9zoS|{NBg1u0xR$u-7hKnDJ%%h{dn*f@$JVOKB2c~_nP+o z$KG(~cr)rHyH6v5pqQN*kZh}eMe?c78C8VMsIsRx?I9q1=W}GaP{Oh)Eig{U=y$|>sE!>QbRvPWP=#>!DkM<^UMW`QzuW#Qffyf z4K(~$VYuy5y3Ft8RolrGz^R!pfYL@%XAZ>&Ox^~;kF7xCeHpJ|8?g)krtMDD2Tx!H z$jLKThLDl2Wx|4hSzr>1?0V`uF4YIW6UX-ajO9CMdv5+a2oe}cAw>nLHV2!j9Sj7x zWG?Oag+4Pp4^W5TBLJY{x(OsW2n@DMV6e3Z{ow7dkN#pw_$84IHPi+SM=QH~IJ-xR zXm$Yl+qMMZHx6%!QIz|J#=)-�>uJ~PN-Avubh4$Nc+c0O8V4QkrV<0}T^vkqu zV6Xso0t4C~gCz_E8_)vy@{2D4-O85@d;)m=69XzX&N=x0N4&<+zo^(~M?X~T`dmQ8 zM$-SW_6NJ`KL)mv0>Qux0ghVPhJm_(MOWZ60HVY64dD52ks+n;$(MfUrgp%3-j3IH zoi_j8mrVqSD%SRZ=qd6D>i!+7#4QkjD$yAOq=P3ck2H1PvXPXoC0c;?{j*ko^6Jli z_2(G;H)n?E6WGo&M9m50yv%n1By=kFr!hNIzjoLdIH)oLmQE$)Z_UKk!;7C+ZtA5y zMhl5yH+2I6vlU=oJmqzde_RBgYXOlUO?9mlPMFKwEONc;5Zh?29*QV?x;j?QCbI@g z!B#+I=s>&sLg`2BMeT@USve-{u{)JVwWjK*M0MzOsv{5YM zqDj@gM0Pw`6fNdC9ZFQF%;IiD0%(H`>)B;W2Vg)~`BDail7$1*@91BXAKhhJ=YSbB z_tCTj69$+jSAdm>{0�rH1OlqGg-0PN<>(qUyAi%U6sTyd-r#>S(<6C?)N044IEJ zC!`Mu%Qwo=_jEsfr_UtFb+Z+@#sUw?qbo1~EAKHrIQGkoPzkW~uCKP;c><7xhJRO$ zlHxt>I6E(CA;3!3=l^QMWu@wZXscQfKL0vy;AUAvSB_4&6U(XW z;kxO}wv+pYqO-1xlITsV^Z=XgBKGGRx5u`MYgnV1+w<=rmZ38sMDg6@jN8Q0LWdO= z!RB;<0o+^8sC~G|InfR1o2nP)f{tG5hzgj!%Cnruk-E$_IW@6mhZhF4^USKR1}j@W z<8VKZEHI~vPB3gW4Z}(I@F4)}Gq+#ZwC(8tA`Qo&-Fb9Kz5Ond?G{ESaSQ8>8-oAA z^S~`~m3S+NS_sBq1p7|Dg0I&`-O2rVT8q2450TkcqqXwHT@FKG^GNdXjGIAjtKm2R z^ym34oi=Q0zg2mXp5Sr!;zVGr`=RyN;z#I1wCwXiXnUdSqgO85on?mGog~!iQab5_ z>5Y_?3n>lMv!6HX4eW^}F0T-6}T;mi+}KeKI+%EXuQSFE9ITY%u5d zo1emIAnD38!%+rl&-ybwi1gyl^^~BL8NAmK7ni3gCK!tnwlIzua*bY9S8Lw|^xp@p z!z-GBexi!bK9lIrvJ5?Ak}ggTE;g7*SV6K{>v#vJF%I)wQ!0`q0T(~p^?!WlQ$hy! z^#hPvGy1z$CFL(V^-tNY+Ad~p({{i8b&~`t>E!4>`~2;v1 zOS=3BUmWWra(k`6F*V@c`6%@iyq5vKg{zRK{|<7$;pki=y`tTXfVBVMD+`rQQQ1LBM$pNRJsTz&bvlJKaWf%R_g0b? z^t$lPsg%<2s6>z0EkQZh=vGmyHlk@P1U=AitK&u=pBI{|aYlIoC7n7QT z>r*C^CLA|;B$Xgj6ZOv5#3@Yg7JxWkaNC*4O4JEwxxEg~B($+Fv!m_$uuS;R8R7Xx zp`$%VvO3|JrY8Ft*+Q>~%GyTcU&kC|y<ly-Xy?Ic zVwk)?kgim&?kI3xTGAHUq!@dNOh3o-sr6xjot}F#WCbdzqn{)|I2hXtSZp!Ql~8c& zrFdorfuJMDJP6=9+kl<^%Zd;YP4;_{<6xOFMiUEYH_rg6&)g>SSc+mD>Ld>%p2iUJ zt9C)8vl{#Xuk=G%j;uFogtZ@csoyw{GCIN*j5puON7rg~IMmyv6MS0O#>d}#K509n zG+|ruPM)cSg@H~mrdSbnQxq@U%B5_VhT+V7`qpN9C>+!0JcXUV9`CH}WUic2CiCUG za$#Iwac(w56pXh2>ALJ>p0^YnS%7NGfDAJ`B?XA}D^x`Sm`&ZSH17Ggj@bN|lBa!? z9vjM#(@<7C!>c9X*G$v$2@P@7FW1~4G>k|N!q2#|Z0Y%U$&9$#UOKqD%3!#!&T#Rr z#YrVnDpA3uW_i%RX~}eC?GA$P-HU`H4Q8GUIkd4~s?S=;3asFUpbGY{8`&NPb`9w6FWY>-} zD0CG+0*D%v#Aaw4B=nv$Spj-qlNdTP;R16g5m6Xnzsb1TbJ7bSUi>n!A)?(^!f%^O zyt^QCg&P~oyddFt65Z75w>PRS>g=qcd5I))c31RcBP?rO`saiwLCvpMWgq-d!0T5p zfOTa@q{o-5u(VE7@Qxdr5xMof-Ba`rii=E zu5eb&$jN%T2maX=6Fv~uVlZTZ2P%i6ag^j5-KC6Xp}S~_vV%W{_T8q`g7`VDKgZ0j zz>HX)yDAfpTx}J9Q1;_910L#$Y~FKad-@z^P5T`q1buib4vQHc1ozCV8sOx3u`D-y-{eSx+swrq8W$6(mnaIWVT5;7 zJ6Mlz!f^Xh-$vy8J^yNp+41;Qm*-SMU2=KSiMWO=b2*7boDzuCaQjQlL!RU}4gG47a77VA!cVpXlU1v97$U`y`Q^O^!_%$8 zt2CC3-_=(og91&gBS<=zBS|5zy*cNZ_($gU^&~8unD(z6iqJXB@I$2WMci$u;&}T= zT0pM2Z6`N>GZAof8(2=S?VMkyZivoEY=sW6-jL=Hg*84z<1Am_egb-M{dW)n$Y1_W z{X`9C*aw zy&n-M;?z~-eRF1KKfD1%XlSs{5~jKdlGy?l&n)a_*Z6)5dhLEJr>dA}PN`?GixN*M z=P4Q)?4DS+&yrmybbM*CH=)fkHp_H!k*tT1 zlBI^EYr}MP+_szq!n@ErAFn)f-7F5%ZRok2y$5`+bzHG~uVBSJ175C9p8vXH6dw^* z$c}F>`%U_Zb93(;+ZWQ9sFpPSnTrSSbujS$CTiw+TeRB5>(($nO4(!qY7jfgTOtg0 z6lv&aaY>zG0-CfrsYt8W6E_D4E1wo~i+I)h=W>C!c98K}#gtILj-}Cp6~A62^+Hp5 zo|zF*GK9)u!OH;Br@SyB{bh)RcS4F|%=^qM&2{ktH2z`~+$bn`_8!oh0&54{M=y_q zLu>Zn-t098vUQWJG^g}r7{|b_Yc26i2ugc6*gAJj=GEa~N`)3Ihiim=J2>5N)OE}5 zSZ7+^AV^T5YYxoc}VR{uN{w(y?X6Bh&F>DbCq~d$4Q} zVImWBoL)}}9V~PaEfPmBcJNv&l+HAhAPW&@)soh-B-i2siJnoHVi`q=KkAS)o{*=8 zdR7ouN(*|v1%^elopo)4S*932c7tSw%oSqN3hST^FWCmfc$)V7$Z}F!^hH_Xd0X<$ z&NWzDzpnX&B)DKsXHjpD-=(&8;LzWqJQhPGVpEpaz#o;Qmin=_z@o|05|@W^zlzg} zuq$7mwGjgHEp(kMUOU(D@~ow&T^IbtwX>FsmsJ@T6K-D;b<)?^LF}&50HZ@#viQUe z=ltt;fk|1bI(NQIogk8t?blqW=Zvx#sO6WCC%GT zwpKp4VRAo5$4o7wpT96PolwH~{=>#=lE#8aeFe6f0OcCG>W7s2j0Q|I5ECda172Msm zkPzGhBxrE=!rci32=4Cg4wbia?(K7v)8};eeXrl|e&2idkEAH7*n8Ekwbz<+j4{Wg zpaxS>zWzjUU;cDn7@%|`&FU`cJNTFkPprnkos{yL=;yFEA{zy+nR^RK_nZ#)h68uZ zue?&%VF&VYA#yvAW3cPybybmZy6LbP(YpxTLai@PI*u*KGM`ex&7P8OFZ1>UZ??w1 z2kvEwBG;l1@kEbYVpNY9t4a)YpYS_<(=mIoelPi6{-@;7VmaZ@aQ>tx6PKL52Qr5` zA%>7BN5mv4x|rz9rz?kBm-3aWr?*y^64q~iX#`!yF?fY~X%1_X1A2qS<5vG2NH_D} z(jkQo{Y2&b4GI1?JmTsc!zSbc2I_%5wHk4O9+6N0Nk)of=&P?}vNlSOArF!_OYyA& zdU2NR+XSmDN5-aw=QF~j;!9Brw~M2YLtwudh1UkwYav)8kskjc97c ziivUz?;fYk6Xd?tgz#ZLmL%=jAiU9_-}Pb`nHqyZS|Wb_<6n+c;6~GoQB`4CQC|^9 z5w2UOjHb|~&^4~>%eFv?@Q_|3F;5E8*W4NOqF@^0%X4t~>N{u~4#<2K0rXQR6MFQL zOCz??Z>ui0u$s7`!X6~XCoTs$iPEebH2VQ4Tw25Cn@`mWa(2zQ$fQl??_vy;&Y{Ec z9B0~m(D3)c$7L(vhkLalU+SKw(BYwaU@!El@t=X|iK{nEDV+wsgWRgv(WR9q!uAVn zmqp*kO+({Sr~1$Y74sz@imw5R#+9T1lA4yYm8N)D9VCHwKCEP?hq-YKpU9-2 zYj@V+=||ef5_Cyq9gJMxL5kq3KaCFQ7#kkZs#_wpZLf%y#_d~jYAcG6-n>kC>26=` zU~oW{8czj6(oC2;f&^!l9u|dleKeMy(~wMuPFWenJzudGii5|a^9g_M3hyU6a(x9i zF{Go^#5XQf#-1hW$eD#4_(--Ps3@ASIQ{Vy#+MfeOo^C$u7j_FZ@S2+lNxNQ(o88Y zKd7OaWI(y@V@|d2B36qf&#snTpQoAMxj_=pn@hmQ#zhJ`W*mDO2a8p;p3a^W0UL+YsBm2|X>)Q0+iXb2raeFjWX?7UVOIqi?5sINtx<;)9~*TB{-w zTT%kwmF5xVrI61ijw-zF(G&B&F#LfbuTI0fPSm2gj^QiARmK~rp?_rQ%&jGveRq)q z(MHhX@F}0?t1o)Z`1YOFW{Ngte3Gq7pFkAM0>VO~61QAmg_ioa>3th6{XKK$X4`Gk zHL-H8$fwcq(rR)NpM`m(twpdAd>I&!OxR2-jotWG5MZ@M`3USh8AtS%CkfEwR z@M#}R2yM&@-CQ>Vl;>lOjoX{h?Km#myiSKp)TpEL_^3o7J>s`_lmFj%Gs`IKk(i^iW!|I~s(a%WV}HYHgVhvb zAb+IWb;RfF%kIVEu;nLA4im8cIu!;iq0!n4g$s9wMK{%41s&6U0=yLTZ%-QHn&#gL+Kg%TwM5?yhWuG2d;loQ#yBh z;>rHC)QEH=DiOgqB$_!{P59Ka{;LPjX_6*`(0JSYiVDQ%F`?167mZu&EPzit1R!81 zrG!qS=c_j1AKhR;u5Ke>x8wjPxeE|w8^=O7hmgzsuFT6 zD`o!XsA}FkN}teZ0k-Kf3r9;{O>=hMAb;_ad-wNlr36;-(R$_L%Ilw5ytRrTSas}2 zRkfDuoFof|HOCGN{?)nGVH8a{cUdNN?%KKxRy6k3p6o~r{GtO>xM{MG zxPFVc4X(^l7o;RVqOra{K!%0As;0?6aEqT*i5iY5GvHnVVfGXmM!gluAJa)h}9 zN<}y8J5S6zxE-V4ZbdW&VBjcBOQyTVJ}Br^7TzhJC~*dVrWh*$PWTT@<oA)WI(liE!`x19Vr92T0lI!1`M*_h{ORK# zgOiy;8GE2_AQ8|v5RmX}QFnqYhyDRQ`3LF}4!4!wn(|qz5*2w{8G8}$_JL%1ZM^1a z!DA{@BbyD*_Uq%)zLZ6SaJ-UYt-O)dap`Ax)*TObB9 z{NFJg{qJ@7m*)csSC|KN?hYBLIUnPT{dJ>Q%y^s4N1$U_9HI-JSuJ;Fc#5O2#Mn;#8tndmQ1 zfD>-nZeW@E$tme}Hgv4{vJkS32;6VLoe|s(`wYG!Dt9rs_~3OSR|s*u>zF71w(k(b zKT*BqZcitMak+S`Bth_4e6BxkEr@4>A1-*N*d0bse(eKUH4|Dc`wq&*hlyuzf>k*# zf>fl%@GnTw?Wdc8Gyo8ARF~Z0J^lSO86h$g`;~XR-$8FI*~N_47c~jFNOvNZ$>qkO zSu$^|WTj0V_Y(qN z>zb|37ASZlKk6Z1jviN(r(#rBMylI57oEY zu-}f75xfMORym?RZwuG1qNN=v0aBk}4<7g8NevCt>5c>~8y=>p!bC%D{}(YNQ8n;9 zOJ&^@LyUOdm2U4Yn$Th6)#f3|$TzQc+u4z%9-n0M2PWH}u&nx1jxJY}FgHBQcPVE^ zBjpkwonINKuSXDj_THq8$>244()%u141AJt!|Jv)Yh&Enari5zIL_84V9OI6A$0!F z%TppiFa6?>u`8^2dY)8;uyD6?vf5h%C+1NP$w7=Onm9{jhQQVo_y7>M;5*$kFGdLk zH*o1P9sqjuIL0RfOAJ;9nkHV|#IN9#pAtKbGr;k�(Z0%Plj5W-h_1*e*txyLWVF z(bAZ^m$p>iv8>{srd?E57ng{j%z|Wt?uBNDu(t>e7$?L9M$}=*RhaRss9t92@PZj0zk%qmIP2R%fIIBxTYJ&mN@vJY*@@i_s-6 zZ_g8;H-9t4f!fm`L{azNyq|TSXFY1Ps{%bV`XSOTHc6y_%b;5k=Ls0tdS$FH9~HyE zVa+PKO?iunGH(>1))+Gqj!Qjb%TKznCNS`3&-s#FuDp!NHL7)&h0x782ldG!z53m= zAr^gTRYSYcT>8m7(Wud^_E86KQtwU46zmX%jry8eXRCki#l2xe@hI*;IUT@265fX^ z?6dYyurU|f!>=4wnGlm<;;1QCdC=Q&)o#npzd~Ll+t55=4Cz`JAIk#Z^PSUL>ldT^ znAYd0Mf5k6ubZ2o;#Fm=-PVuQZMK^fQ&353DX?vL7gZJl9J|K%iv2rFrkD%&iKe$F zrPdK_eNimXdzA{{eOkBFcp<(V^ys25KJ2K(<0S|rIhD@zzwJhNsv0Z#0kn$*_qfUr zsKqgEpXL}yb}s_!G|+gyIvv2nW5^>)Pe+U7nXct`hWE>rPUCd$PGS09%V1d)t{@tbDZeHNOIMK915m$b^dmVcp zB_-`L{qJVN<*aH3^(2t9jQ_++MtLNasy2!(g0-xlqj9$CBD)RC^pU#1iBXl2k;Rut z6x{(ia3T+K(uuot+|t=IeOGG)mM&bqgatEWcxv$5l`1Z5*YlzTdUe%x8FqtQjeY^& z;HSm*Hb3D`@IP8hMK%XPcBxXYrL1)Kz;oKX- zc2O8jI8DX`;zDX5E{uk3Q8&8sLb~@00O6VD!5v*(BT4xOx-r{?y6Wu+dhQ~{Fhn{l z0PM&B@<1z>4A}cd;AC(`LYMvIGbzBvkX9lO;6~KRD3UFLoZtpHp%Pz}qyQDlt9MC2|!oXtik=N54dYy%8`9FEeMhs<&xDcSix zGcK5rqB>d`-O|)oS&Hy(Q1;na;xh9Uo+J4BB=I{)n0@bJ#-2e<)*b@jxk;(zINWdfSJbUh+z6*%3hsy-VmLsm=H-V^? zBOaJGJ26M|MJqG(s8a0xf&+-AzOT;X8EtMOadgwQ43eBz!#}`no~rWbJ1@8AXnZP5>)7@RbcHy=d`dHS7N4Sb(#rrJ5Z{+`$22Kq6q>?K$-<=p;Wy9s)pIb7r8_ z@Eg*0?bc7%xmi(d7t6=CkRumb)FhnQ>6S6LfN3%@PT4$lOmONPWa-u zR~|-*yTQV=DPq#oBTH%eZo6Fr9chAZp>CL9vl`+Kr$SxdLAm-Msr&2~2gId&H7IJv zq$mAK2Fv??S)rMS+S3wVM>?jQ)m&!z8iUd%diu?_rjG`w7ebL{Sz;zQCYhYVI`F!w z&{UZJcvZ=NxuR#v^s+e}9nl(z>bUVGkq(>9JLf>k@`|#A>4>R*rO%oy(UTKT<+->_ zQDKoizL)IgD3g1NV0JyXm4}#Z+Di`+eN#*38H@9ehE&x+VVmmb+ri-q!jT0tJPijy z%d@q{LW32L<9xI`sm$uS>INU<%9LkIR?#n)KER$-Kne635-yZ##M~>K*&htB>VoR+8z$q>O~%Ej~aJAuo@1EhzBxUjMo>E>^t-Vn<-b(U`h0;08QiV-Tt?Er@@5yR-2Dz}1&?YCa?bDtIck;Luo6D06V&GV3Z6c|W_t89m^7v1pKlAz4s4$b$Bk!WV7m zp#&t^Jndh=Q%oJf4Z?e0vid>#3oZp>Bi2;V`o`mp2;!Jt`%rHQ3jH)(@ULY$Lx3*0 zXJuLL1_&00jOvJXl1$#1F)`ND)@{eYRA<-T707TVyxOz4=B!V;_=g2Q6Qb(Qf=@;m zISfW4PK)F%JTa{mkHm7Ip+AZ-%B}MrHF-kw@K>I5E8zrY@wFqK@TPC7!MP)5IU9y zgyi7cz}lY7E>w{%4K~t@9FKEsOx9<$F8d zL1MwV;{M{x=_3{H#X-$$+CfPLA~e%xTNc;Q`ebw*1+4)2KR_UVrsRhEHAJvWAp(~8 z7;PZpX&#+W{hi(+ss1|@)}HLAAY!BwmM1ia1KR$Rxy<4q1dvYgur?rD%#1r*-2yPG zx{^D8>*mvZjk9DtP8rn>2HSv9tN_@(7NM-Sa)({LntcUmDhzlQ<@B7KFi;&SeV`aS@bo0?7@-N~S#mLyAL_|cm$PwsQg?Cb zoRu{^-5gSBSfg93$7}*DD*Q?3La}%Y7|_0+uW?O`V;i9)ctLvv@LN&nZU^icmU?@e z&0i14r30Iy!|uRWB$(&80g+LNNpzfteU48pR!B-MQn*(S>BW@j{NX`paN5?l^hIne z5tq`A9zAI>8_+8sihDx#JzwCDaOrMYD~t`mk9G`W-h-xBoi{FU>Dkjr(X}SZG_^cp?d$KY5TaA^TO94#eA!PDZJFv_z7u9thsowem zuwrR!04%msn3x*}`sY*~;q=0-pC+uX6Nr-Vpf>bE8o+jE3e1Qy$Yy8J1JIA=!!iZY zHmq(5eMiW*etG~%HY0cUG`!NBz5|))chvG50-NcC?OdN@)_hTB%){Ys20;ti7Ja90 zy`pd7BHOtMam4h-kE^os!KfjDD|F;&Wegx0oZmrb{g7Cd zG0Uum;Q6_SP&u10mRTe$*?mtDI(+z>v4%R1=v-wfVR+E}g@{|X_?st#Hx-b@m#IMM zmA&AT;o{2Vr&Ahp?Pgs{PSI*;84p@ZL5};#JX@)`qr%G^*sK+cR&>wrANa&X3_zR9 zfq=c93x)uE{hbPTQO0*u&4*9qV07MWJ5N?bnQdvO_E)Q+HGIXNMJ@*IaxU3!)pmC6 z%yVEp6|mifODtdy$CWr2OT91xc9tNa%Y0CGG&$2e0i%;>m1GD%GtsrleT4kA~P_UCPb3l>W-TvlX{7Zk=7 z>A_d0@fUj$0H}|-Xg+N68N*!y*zDRnQqO_yG`-(}qmOk*!#c>(yk3TQuT=Yr54G&6<;ZsjYmvJ9A}LsIppWk64JW&?KU0sY?=p8 zcszy_xFkqJqY)}oxK~^ou5eexFdn#4xY|9cS(<#W-A#&U_LH(7=ck`>{n}*qCt!%= zCmd=YnIeFoE&d91sfb>&JZ^nQ`R2*2G!EW&Tsd2D&j;_0^1Lq$F5M({ZWAI}7w64^ zz(i32s-NFMmLz_8rgS()To1r~fU;jtE!b2Ym`L7zx8d(=_rNd-a`f+@nF(0PFQd>_ z)fjD%&YYXuT+s6!8JPVJGLvF!e9jG&?w=Hy48`*BNEK*+&4hX<#En(*6BL4-8@&4V z8-npv-IANb&Ni*i_Fk;Wjxg%hY3idl5r4(rS5%?sK=&h{xQbhL#0Idq&*37I9vZ7H|r&fZSWpeU$i)6Lkicvn@ z!+$l5*8O^fp)j;k;+f9Hko7ej$&SQs1%906=*6-ClXPDgqH|?zj2wxgdVNaYjwjMa%K{QD$zJne*?(qWNIG&pARp)UkL^h4l zm{r!b@;YMRx-1MQCUNm^Qhg42n#;;#*-@N%c`i=o=909MtDeKfXO6v4X$BVPJ1(^6 z&v_8*o#J@~<6YfJ_r?>A1x8KurPh4Z$51G8^;qE$R^1Z{OqakIle~>7epxf+WrokE zy54c3^t9~wN_-n0UzmU#e{%z0@4<{@%ko`<4_d}ArUe?Iyp=;iaVST)SmvIxU zr>f3e-}(=MuK_TG$I^P4sRV%COf{SQtqq;6&8dJz&?3RI8ZGKRv96jEZ)g;(lx3zz zBU&zSI<_edBMCviFNyT-;x3&V-B&ogO*c z6~+uO#(3l}xUlInVA{BiqA!u7^E(|i2ROt@zkT_@BI5}|a<|FM@v(ik8-8j$urz?k zrXiY;)|&w)>)`64#4b5ZO{h)QZd6QeDN|K3?lFH1G-(wr)s8;>2s6l$@9|RiP~q-A zzDljyNA0giORrzAAS#!7>C^~*+@LhsBw|6sh)KpMKOcfnPu< zxtBGm>?HcWhyNb3tlC+@n_GqGdDRNfM@|{%omJsav*XmJG_aoQ>HDX0b5CQ{lG^q= zg)QCTe#FkCmoB zF+$(k)KaZvOXV65y-fsHk0Xpo*y3PXZN9Te;G|e;MdqfY@WrIf<<7os_zohTIYoql zvtV~}jO9l;Az6pveva(N_h}ldOiTL95o?0gU$}~{O=C!JfF5GW9T`E9!#qT*)|qKG z(_M1a7!Rc(&)%Mlc@$bLBxi=r@ZD{n`ebgU_YyzOnMRc))OgAtd%ObN$pxYJFeyo& z!oG}nR7Knfj_Avs$APJBj0QZ~ST2s?<|f!j#$k~B?;zTXYripw4rIOQK=cDqO4f46 zghN*~k!NG%GqQplGez=+aHoj5Y^S3dgJLfo*RG3qXX=%M_f2`T+Wb?t$9W9kvzK|g ztIR4Vd>wcg_7_Xb10>y{EQ9vhGo5Gy?{0g+y4(Uc*ALB|rss+I)QXB$)E4~_Y|~Gb z;X#;f(L?5I*9)gNJ_i>`gFl%iPW+4sJNzvRgzIzpd#7+!mcO@C6vp@ooc&wq49^V6 z(;~xxC>UG-q;-dYL}3ejj5Q&&a|St0AsYRR)+oZ1-2}zb{5sT05%sYgWe~Z9?*e0T zg*L(IV>L!K+nk1!wJi&x-v`QUkYb@7Xx}!~%I{V1#B`I6CgF_`Bw>TaG!rmV@o=&z zR)-C&FR62NC>6_Z_<7$aKyV!7uPAodxm^1s++3$_tismG`*P_8$VElim0)9M&?_!@ zV#mI57pUaY7b*}RuZNYu-tq#;QLn@A-V=J4zvM^xf6R}R{=}jT2l$=w4)_>d=xm(% zj-WD4{d(foPwvh!c{csm{1-X(Ft)`ZzxU^EPDK_|8oX$fq9swFrdh$JhUF z|0gf|v>$|{N|Hd9T;$RXhJC9(X(*}Ky_&N9c(p0{74$K6*I)~ z6k{4=rW{pahO_Ho8Wr`S%EjXc8P)n}>9q&HzFXp!0!9LSDrcBP3_z#mtpQ*Fd-Eag zchDEye(;ql3;_`KJo=}9ml2P7I}B_<03ty}G6qzSLKfwK(3zKrJ_P{8$N>u+3}9zC zh8!uUT$3fIUv>+_2CI)f7NFKwQx$=i+j4pNVMJ_op~<`Red*07f*rj@YU;go6VlFO zGi8%QKkmz4ePR9_nIQSu0``AoRr~X4>7fkx2n7o5QUfkQS+*);dM<@R=TCS=*_)L2 zk_t;Zh6P7!!#?`UOSSpBkmkZ$1$O{ftw0tKA$kI!BEkja)-2-k74+ch0=Tw^a?amD zUH_(c$^09S_1_uSz4HP~j=6VH!t&A|4Cf`a3Xod6hYJWfZXw;ppMb&^z%2L>vGk#BJyvT}&_l&sJzMx!5T(l_Y zq<$8xyLRC{Rj~!umXQK%%u%v{O&K7WyDy#$u=dx@u=~ZpQOB77>kL24Dp!=?WDyy& zx;`6x6ehpucRl}p^y-ZC}zQMv}@FUNr)b)fz{I!-zZpre) zd=UH%(MrzUWe&vDwE1MDL+FyG1~?!NBeH$iD0?b)D_NScG5TFUbixdPv@&4^bh_Fd zURMMqpX%3`SSGR5k2bv+Z(iavTf1@KmzM_4WgXK|mDPWGolkxdQdy^4ks=_G_J?Et z;VGj~amS1_8N_+%0G}e5?->*0-t_v>lw}gWxNC^S<9jZC=s9T&0`liO9Q}eYDX8>j zI@dwYYl8&Dr(w@n%B|!(m=85O$oRWoWW7HF5C@H< z`HJj$ut{75h7V&_uXbZgaMwC+0=6jn>ht5|MBCZSs1p*rClwqJ%$*n)XNe&8PD@!- ze4mv5&uR)Ene?Lxk-7pGjjbuI;gRYgdyHH#H`et~+q~h>df;xG>4Lihk$v{1_1FJ08~pstoaQUv{8ICiBb!pBG!?INT8GV zlN2d$ER|0SA#F+<5;}qf6}Io^tB|3ZZQxj#e|^rU_mYEmqxYZh_r`$gXUpLA$TBzb zIP7Xmu+)lRK}8f${6_`rSZfDw=QTX%udd&4_<3drTAtRdS5|785+cTajwGy^F62!9 zyn50-?#&xa|LN#8rgOR)Y6wk=HT1=?1PMCR>_f0OCPB|dVVGhsY(l**uD8p{_r9up zNMGR6?5?=Tf%mQZH{#?y-1UR>#sYRl(`wdPQYOGwl)`ArPAyv0=N&~-v}A$(G+502 zS>uS;oX1J)T0eC`Z<7iRX?PA+EML%|hST`M_&Ms9eQn$_0jKMT1o_9MNA7U75yEVv zH%hS~5MUu>k6^n4#|wTvJ$YVp>$HDojwxMM20Fy!q~l8s=I&-Bpi07wk^Cs>8a z+*vpKH37xn0^xr*9=r)jmw~N7=vs%UCf@txSX7O?x{G5lS~>~KxC>sW`wJEkrD5

x_ScFgq01UHo944uiKSK$sAiUsn?RdAO1b8Y9<~z^xnZ9+Lagh?~;M5Ur&~ zzn6tix%63;7nAS)zFOkz(a%91Kmqqsh7_JPbyba6*wjgickZB-%V*RS<3OQ}2>@>U z0dNNM|1wy=4o=G@l_TtKo(fIz`l-_U4-gqcA5FlgaUjMA@6twnZdM&;>IfpJ8l?`> z?z`*H(vGd@0g8}9hMs6Eyd zKDH#QZY!t^VAwn33iE2t>Rgpx?Qc5fI9}aYwMZfMYu)hM62|yP*Cab9@N}&<8nv%p zlLvjOvRb_uSEgN8t`~#V%jP-T_1KQUi#~aEjo#z=H9dQh_k_xA+^uvrF8tvFnb^iJ~{ib*Q!x#JX*J1u99sUQG>Gto>{bB;QAcS=9} z%1?Y6v~db}M)Cs$gH`i2!-S}oh1>d%&>F}PYJt!i$PfrC0&L4^F) zhZc|qXrCR9!cYx3)C6MF)SW8TPrM)=@4%GtAsV~?JLq0c6 z-wdTL^08OqXOGC#jO=RgIX>*S`u2!hbiHaElyvJ|El!b?QaL#Ru*LuIm~!_6tzi9k zU!@<3(A$?Z{=H`R7pu*b>-8V$5|C%q0O=BtXAs(cyxc}kE6UX^cpcc3-*{JPws8I<#P|zK>{yMzqnX!v6RenPj?~q`>Geh*O*kh)0 z_5kL{jzc?_Ej1v3FX3mm(D|~*lv!n>0!LEk-yXPvR*1{?c#<{b!uCSUMnW3g2g96q zYV^7Qz{RW;FtL`)8?_P36{vI|Q&BOMMS%gY#iaBG$|pVbk8j~pi{_lQ$N0GxHxHPi zdk<8jmaFek3~64K*9f~Zv?3j7B{>b^>mSC2#)vXRYH59WAWg)vwmN}8<&6xU=QDVi z;WtwK1`sZ^v1O8@r(#N(7!8MdsYdaaF!v?-)CTE>&)(J$bRm)o0WtHcV7Auve$moZ zTJ<;{smAhIo4RP`^hX0d+yt36^;e4^4CnBgP9WX!kI(8Ix1BOg=scZpDw`9J8&9k% z;G-egxL^5UwG2M|ei70kjrVsDTe~||>)80x8GYQR2k+r6vSqfP@3l~nBsAw-T1yUR zhiej3`>#MXsoPoZ;Zpl9COJ}Vai9nJq2v<@!eW{LdFiy+N+AL z*^!Jx@_@AWD2u+w4V@At|WReWbNj~=B!6Vih zlH3znuIdh1syzg-j-Wk8CPe6SX^!R;T#qwhNgH@<+_Ekk+exK>78sfFhs0-2(zFS> z`1UBVx1BNcWOw<}xwIyP2cx6s^SDF1Q2Ktn@zM62xvM6Fd*X&*Ha=e@DvH(Q0`L1< ziU&Otim|mZTh}Cjj3D?7f+n{VB7K$K6udsJ8K$@`SykshRU1izLw7)R=%swNo}1H= ztif(-Rrp!5JMhU!L(Se=v~smeL+f!KRWB>h*{ng;G~30A&*b#e8KKI}n-RU=WbDS(Kb6EQFs?V>deH4*hF;r-r;KG(bH(41A5-dp zg)TAAcxt>TKc3#1E7lH|&{mX>hGo8($3jbU5?A%GuVb+r5PrbwvNEAKp*+fXYl-MT zS|N~9pf{m%C`ZH)7cH*DZ;&G|>i314&Xr;;WC39l|Af6_dX^!~$y&PIonK;*?vcyW z6=XA?y}`UZh6dhmE@5Zxi6gdanyAuGgR9;~P*iOg=~I@W#&O?dglF~w?at&*V0GwM z5RLDk__NWu|BN$#^~U{wr|ZJ6ux;TlEpa~l4J-bC{P+<$p?A!KC(FEIMk;Tbad0Y# zr630SD0J09fN#7K2QJmw)Y>#%yVDZErmIvCkK+Myuls{ikIe4X+skOeQkByw*oUO&*c-ME$2RIARn`NZ9?4_~x zc2H1Y!wJYD!_R&jYdhzuX~4IpzQs>So}DPdO>Qi1Ier;U@M*>)u%zmB9LaME{rP-T zFXYr$<5nER?){uRr2AA70k4nOqOy!A^y6ie1- zaX?)9q%SWl-|ysUABrRJZ7lHs$sAvUb&JKt_bKBOqlbZe*>$AZTPxTgAZJL zQ&>j+`a_`GTcOH?zq(l((VBG~GRu;VU^1}f&5T+SpB3YG-Sj%r9hB3lmm2Ac&lWWz z|BAJ-K2yy@b$V-he(hiRwMpsq&3RnAcwb9*E?Iifn`RLz-{7a2&;OQt{{EO}j{hAr zr9lnLSaWSQsE&p(JI&oFRk8Vnt`yT_@hdG%5PQWo2q#8pGAJz5Fx4Q zIztaV?a3KuRC`oc2MAt${wc(ZJE-O2rvRI5967zi-%B-^YLcsDfVetipj^Y0eilg# zooU3$Oo4BPG;hBOR>=dAJeZ=L zj+3jaj{tcJ@d_3w_80I$+?cIDdKx7UJKv-N9*uw|bA9PwFy;U6*KquY{1W%;pD=pz z@VS4YO#3oSg_*b0%Ug8pcXq>$d_7*NX979K|7V?c{uSBsKY9=M0?}oL(&5?MM_=md z5gkIqy3y5<^@i|!AKS`b_9~I2evIbc8VzEEQJ5B%0Spzk4)KRdlf_WZW8IU6QQ~sF zsW{{Vr!JQwPyKccqq>=r;jIe7pg7_$Y3dKpRMqB0!y7o=64Fyp%j5`!0^yXplB%#Y z+ujQ?+_P)-+404Biv~9y-3Szh_mH36dC^b_;p|nSI7~r{Fpkfdt>R|Pw5Jag^^FM? zp0(?G?d%G;A8IY&H*nH4hN-NJnByGpho$M$#$2?B(46s;SSurwkbRl~Qlm%hYs8L~ zBda+Cf6`Q>~M@UxaozOC8s%M^v-nCASIaT$GuMNwjWxaYQ%9<9TUWS{( zlx3ZAo<-(dDbG{eui4Zz?xOpda%vm=*XOlA($UdpBlk*KcIOfld|A9h;;XFFBzave z$_}Z1 zpEjl3sMUoC$%qt*3En8r+j1 ztG1UA0vU~RhGy5gc|pCq$@KY|G9EL}dygg*KJV2f8(w36RRQ-SA+^dO4-vX4^~4>% zL?6SC3wK8cn?*u*w#o;DhHtUE!dmHraN-%1`w{??|x%C?^HBJVWf!DbzLpO&eU z(X@oWu4e@gM!poHj~-#I5D#K4|InQm`Nkd4+{OZ^jeq|$S&17|4Cw*4gU_)ccT_b+ zbsZBztISI!H}{2L(OU9Ib2xv_x&6+U|MWUR6a5il#Cs0```m>J6eSBd+c^CeczzXT ze-G!SzGl>|W9j^9^|}{P?5g&evJY~ReO<}UM$CCVv-2`%r*&FlS~l&%_Id=n@?GR) zp(7rQ*{z0FkzJN6cKN(z@=}7?-aP&0%h>@L+mV``R2u%!sD0PnVr($O1_1?mcgd25 z{AKgYBeJBv>;saNR(fCK#c88gD8@t7K5sM1Ct_*qE%gz`wRbx`mxp} zmc`@Bk+VHw>0|1XrRcVOlu$c;QwzHsib&CWm^rVuD~aPPMy!}9l}#x_%L^Q6OE0dS z3l)mzuVmYMtSbuoSf1D6E7P~Um=bRlu%BE(sxxUT%-9!TGE^+oJtD-Ky|iRrX|xXX zmG*uhIp}HhGWS*TJBzl6_{)1KQUkK4-Y!h^_Y3#<_03I5&P|QEVj)%@EuWv-5nwf& z%tRuIoNGC1q~uOJu9e#O4n<8nQ>=mL;K-(Q6N=1>Uz0s{hkpj)qDR1%?5q3$a`Kz1 z6<|{(w_47ux^ieg7<|#8a*KJi6ey@ zkVUp?P+lPfOn54WK947f?ijDq{o%R0YOZWXMclmFcJ^*j{Pe086 z`ANNU1`scGcv0D&#Ut{iqgmK=cPaBnsF7}wNN$dqLtfOE*6I#{+KEyNKBPTUFnLev4#E&2D{!d1WHLA#_L?Bm5A!fqym~ z|KadJ{(CbfarzbTQUokI^!Wn(Sv>4RTdj;{S5W3WZP?+IWMZtuX$AI8RIF!p@;L6)UjWsaAqh|2i}l)$MRJb6Te5$54Djsw<>p#xkrj+G~?>*%8>T3-=SCS z3EC6%{0xwBm8=xic;%bQQ)-=Q|6gnz=+lbbRRI-BcRS=9xOnNE*8Z0Zmxh2Et%5|Z zr4d;8vM2;uMpQff+Pmme`AZ}Ah*iH}e_(Z0A8_6!uG3%OS0-qBymgRw7kj$*>ZuTv zY6S0SoSC}#A+~A&6B~3f_Fk?~I|@<%I&8d-XvK_t`o)b$lYFYzqSxTM1vfZmf^QVhGz6>$L(!HG`5SIICa{&5OyHeb);xP#tmysZa<0 z^LDbtyy?62FD0K%SHj+v(IZl!%njJNJ-olCNk(>rm>T3T(Of3|&fhp1O-o{}X;m+0 zjXzvM)NdQnE(QD2lGfj9&+5sjh4l3F7pv?E*<+%`G6as+6U@YF63qA#jrqfX0Be2@ zT}M;L+*UW5y0|qB`ZpNkQ6Z%~QOB$9d6Hm96YRcp- zOVe1PweCc*f1#jP#<|+tP}g84s-CD!3{f=DizT-cjmX>Q;cCm;ipS#@_}}IR*ERc@ zrx8pxv2L%{U_b^17amZq$qb-#wde;IK#F!V5b4q_qL!VqqFh>48Lk|}WYp*_!D4{H z8M$#OYct8cLC~5Xb-5!Y$jD1l?W8~z7pXO^RXGjkU}yxVPu_VU(nHG^fIGO|1V3uY z;f@-CSy}#gT;=e6HJNgfx%sM3DQ`Rp22QAPHliS=KZ~Yjp#E6+5MmOTqx9yRtP$fy z&8%7|1T!zY$Z-aSd=+%|qkcYWD&pbh`~B^2=0vWwQ1R$>a%lFYveyasfD&40%y4>Y zrx!^j9TUeL9d>`2M_0?we(?SD4@s=%Y*)5;$&ALRdoU%wE864IeK9a&JXM6 zJBYr(DfCfz?Rsjl2lI_r7*b58S=koei?PL8-}$jXm_Ju=$!>px*I`l>;_Ab$ZvHDstGBfqtCYy(S$q_y4_*rM@Ceb^AMB|edI;8W zUW*m2mm$Q}sbIq)M#NBxKZ#~wv*xjoO7cdMm|IUAv1Yz}q6q->fXycPBNHyX3DxK3 zZWg5)`g^QdvlakW*Cf&g<4D90XAj~C3DI}gt8-9^(kjk4haM+2g!_nWjqz?o+XlCU zEP1q{@ZXu?)t38Cqtb@A>(RB+oUvw~tYh0?Jh*u~S{KkBGAE&3HIX@?8=+jq!f(Wf zO~Di`*#Xrt{)!SAUhhMQ9&K7QVGbh&D$zQ4*~*~fr-?UPyB25C^da>gSKmZ!BB)%r z`96?@yR4U5c{n4+B^H`hY@G-u>$+4a2-Fw!+1$huqu78jX1tCDFlAYR?e$W8rTw~c zZD_PzLzdXkzfPJ2tAfYLrd*l=O$vsdQ9|~qy^X8-nyF%GCwjbUL;1$CXdO?4jy>J3 zUi2P{Wv_jBhf(y_og+A_y}4u)@Lzbbvy2gD>B*R%H40Ptc%2qUrTCshzSH%s^PVAh z*Yoy-8h-uE!gJeM$?>u|({6=FvpA9~fj9(CjICco_9hZ~M+Hfzw6x`@-z|4NgYMK* zJ`8Q{=Rx=qJy&+&rVo1iAb4S^L*sSn>?Xd7oAS1)Ob+yLYbV}L{^~0{T6K>L&syD) zFEb!#2P)6J$tTtT9nNUoQS1jh(+f^T^=%@7{vK$;_4u9v-f=a`18)(8$oq4VYPP{! z=05Rl37Hx+QA>{D_jkvS`9caV^^cVmxv<|ByxKpmFJT;6r&?+Dl#_<&fDgq+|A151 z{^A4pJC5}S)BY6ZGbz|+v3_^+F>^N{Dn`9csB>u^qrFN0(;kUPOaVXY@34ROuq*i0 zG(uAeu4_kQy(Gsa#ob-cs48xrfFkfEftdZ{82vJm-K*!G&w1^Y9=(}JFCXC`eQ~42 zYg6T)U0WJHf_U+8k5#h1)JqE`;G$-LzC=b&=7h)ry-5r%Q`5K)F3G+cC__2pNI4h8 zjXo!y7%H6JM^Aq?kQg6fEmKrMNm};ehx6Paa>>~pL??5aq5A!Tih1HzaRT3$I7&Kk z{z_6DONB^*W6z!7Zw+sXrP5`n*VFi|pQz;|=XP2VAtfzki#&Xw*D7CMJ4?Xzg1#0S z^KztPxwoJ3-7%rj!zotRaJLFwSK84Lsc(Vu7J82ycmHn zw?i7p!Kr7*G{bvV7FM*r8``Og)L3m=neGd1lBg{W z2fX`_XLros>Y;f`Diang{EVWS`nUyW{8S1KbS@J*0Mr)VfasImyHQLj1+W0n+e*?HP~<0Q~O$s>sy)A8Tcr**YH| zzA9lpnATvW<;S4TyuP2aYz0WB&|EJrbpI?=UN~mi7Cmcfj0TwlNXhRBt~V2^RrVT^ z)y4+llI0)q{s6g;G?qU`tPLPg06IqNAnHgHQ7|F!@X=A;MdnmP#16J3b~{S~M{r;Dx0v{F66a`PpF~RqIQcE+$#Z9JO$OR&+*0 zuf#pQvZfozVaDe;fhEGsB=k)lbHNNn0L{*4^o(lT(9lvhvEziBn89XS!|V=CGd*WC z!O7w^9)wn4)79mjyz1MKERl;DZ;lVTldBJ$H&V3gQ1ND@*IMh;Y%GkzF$D!qsmJIE zUuUisFjxoEQmF#SZffd3(+`1+|ELA|$6u7>>O(}vU5VQ_v+IdTAnoD~H`aQwy+;{! zcDsq_1RR2JM6Z;>Zq3^+0?T#zjsXY51vclS8j);)PE=cTAv}Or@T>EyE8g{NdVIEn z@j1cB*UDY%#@w$XNhz1{6NRz3yJ5g%83d9rpDzKnblBf^e<#F9|1JfQ-4hHX67{bD ziH=ptJ^-djNx2dRfW=>~(Dc{s-?=Y;lY9`gNjU-LR60P?!Oj4_v4H?s-MylvBGLfR zp@dLd0Sp6JZ$-cT%oCWC`&FC|lv+*EOo2t~>y#edi86`)`g=7?j=(`VdeUZQZtF@< z9kV~L2%sj*bcmVB?brlaCPk-A$|=^)6i72N4Af4_t3gSnWc1P}sIh+c0lT(jmm)^t<`?k|sHI(?azNGj}h zmU=FZUIcFz{0a=PzzBo_M19NOP{4uR!0T+MfY=*ApaawQPpIzRdcxgI$}M&RFb1dM zXfrb-@cQ^~szfiz`2WQFXydIeEa8V-RzP+8PlJ|AX`Y4spNwZCz_pa-Fx0GZt_E1O zbu|J->|^PrjZ2gx@H#sH1t>BTd!r z4Ww0*jsc9EJT7f>A&1cuvzOzVmNdPQ(`(Zlg|4Nwe(g4q_mgdHxlEC>#uK1GB_Z+n zpl@-blh>Y5dnjI}hRUr7EiyXBqw@kP!FBIzD0}N z^Ro-m9=SZoGU_q+9`(?<)t0pGZzwC1boe(UioyGhE5laT>kHkvrlQB}W+`V|BnZ!+ zCf$l?22~wkpnYnH0 z=UWlz=u1xcV6hS(3yhlK>M3{DN_VJW@u3QoW&OP$=ig1+sv<&hzJEBstE=x#T-je) zJE#p!8yt-Sk1UTZ4eRYc{-!`6A9L07nUc7}AeqZ`Z2HHj{hcbD#Ej(paH=9CUp2FU zzJ;YG%4$xW41+=%Og3O)*Z6Ysel7ggP4vzQ7$c>4wevN3J{5i};~hIDPS%fM&X%MR zegG06V*huIu>O6UtpC$niLK6<71$Q`_$QuOp)YGM3z7oAzCljQXmm}Uo%|8=YT z@EK|NPh|V@pLUwRYZw1l$ad+zyX04G^RBN-!Ua8^cB?XmI;)<;Xp@nE!kA%p_YR=w6b6<7SxaO(;sL9MK&&0DLsp#(AY> z#N1yI()DV2ZIA0bisii#YWcgDURc=FNE;Ql2Zt9r#vVFQ{i7F%QN)NQKl>CvO7UYj zbKlJBZIaENMtPY3v4oq8Q|>|+SCaOMYI#{mY^RjFuj3U;EGU_uh&sBjps|SkQq)Nz z4H)XfZgK0Uhuv+K<}3|}qEGhu_Uym9nZ4EcL`edUc*Es0>J62X886@a&^o`RVdel` z7kQ_7QeK)!Nib^UKuJB;y1`4*7Be@ zUQYI@Gv*u}9SE~T@hgzTG0Ns-lPH@@X4KMtE`koa7T^Aq-+Rg7O$1_s@`H5jD%wm) z+{S@d*is+;9bA8675BD(Lv0*(nwP{kZy%kaTyw)C33?1M^r{AAX&J?JL!^=%!%z)lOVh7poM3JaVg+Iq(c*un5tXu1!Ij7P!(K zt|MLfy!DE+%aWY$-4sjd16exG)#1I3OHJwt-A00j>hZnBiPT|K?kg@*NVu|Gtt-K7_`Zf8ZpyuR-d92 zVQX$4a&nsZ_Mb{6=@dJl#W!^yc%R_1IyK7QC-;IbkN{q|EK_ zI^M8jdbHtF;%fUkw6gIm?@qLr9;jbS*|?%AK2i*R8)@TmQw=0z%QUZ)+S(Trgy7Cz z$;oFX+GFTJnFHS%lEy}@*{*0S)J^US6{7|(+IbD6^0wgmUASde^XqRZEkDj>3Yuzt zA)Q#{Lo$29fqQt?(I=a2s*#MJ&?>Yy;cvfD(*V{akiw;nNQq=;e3@!=JWMS3+#1we zx7MhCiKX;?rF8um;C`Ro? z^9v`G#OJ zKY8mMMe>cVJoo)rEwLkz926YKyY+k*SoAsPSLWI_b6oM^_e(bqV!DY88} zp29G09~&6OHW4|}R{yxt#XvGRj;|INDY&->EW+5}hd`>KIpmk^T5_h>|4t(#%KaI) zZQ@J`f&06%rdnbYqz<&R;JyEVROx?!FNmbmUbj533-IdEy`7+LMAe>c#ymasSBb(; z!ZTL&GMzR?vUAI}Dr0G&C-3IYt6ve^wpxkTp%l@0)KH#it63{8Xo!z)MCpx&Hc(ac z7HiJPbQb5w+xIifdU~^=d>W0RL#1`1I%YO(xzLEMWg#IsK$#VUwciUiYkA0#_2vBR zE6szg1sJ6L#<24v7wv-l&@&X!r=DF@$4AyKJ1UzKXs_po4%w-hDz)szqH`|B94NbZ1=j4s$y$RF_1ptdfL# zR!gt!mG@Fly($_T$3|q9`t_7)piq8b9TADicflog3$LPJ{!spfvimX_!74OveQ2&=L#vI; z)D2Oi>JqKfqK)WzvQp@>=}N98B9W^F-Gk*Qp%vsl%oQ!oHgGsb`CN_fVk&2eL`u9u zxeDI)Cfa3ZZgIYam3Spc%FRyZPe(-sLcO_i0*sb61W`+ zkL0+Cs<@uo6=0whb*$1%oL!QtL8%%1#dY0#GAU%=X~hgey1w(c!|o2^{Ap=LpM)yn zQcjJEDA-{HDfy>r;+ri66s*VdF=o{d&xDE@erg{@CFt73Bxv+$5TWhDWFp2U`HDn;oqd5#T1?o6l9w!?|t7yv>u1D%e#0>_J1^I#BNuWe@h+scw zqq?6=J63`9jO{}Uow-H%72A}NPJUQ-d%=RG1c5g$RzG*5OTEJf_YLpqS!t+&ur9jB zdr0-6HU|<7(?&9v6Smu#kY50CnhRw=K$YZ>h1uYt2Bce18sT~0qdaLcSa<>{AW>|< zW~g{cW(1yoz50TGgLHM#ZX!_5YNzoE12B5*|DZ(mWM02q$TIDDR#Lti7jK4kUyKQ= zm$e~wwaQ3hqTO(%y<1P*KHG8)0k(@>dl^$+dnEQ1tSUGMOe1gW8ujLIJ~qG8xIWPE z@iD^LGRxPmoh2~?nL{(>50G+Bc^~)9^L^c~+#>nNWk%5LD2ZX9`TiatVyz$DSHP0+7q3Yt$|bX<1`&7JSVMzFiJZ&gxHN zxlFH9T*A@~41^_0Zu4V4v;9~Qb}*O;(+k~@Eve^!zl_VhXN~1@ymunS|JGsUpo$hF zC5v|R9ABJ=9m#Yfjv<`HDsIAZByr=C5}B`gD_4Rb+Nd~%+_yoA5lnOMB{7(@8{oYxxKS2pL$YRBNLh!ky6PcMHKNBqqlvG z1@1$tcJjWKnH_6O=tHK}-ct3+h0Hd6U5w0%*#n(Si#Fv*B_<42Ap#8zg>wC>ca$DA zRXXk+8^T0DNw&H)>6RSCY|?zfNigOzDx(DsGj_1DgV_k>xu|wwe5tDuUkkvhTne@T zw=dP1VGx%WQ9yQ>Eysm)cbk>9rUmzO4a963;@&d{?~|%(!UR!*H+z;E_#of*L3Mtw zB$ZB~Q)yt(Tgx}rlwR$c1nLt_(@fC@L{rv^SL6uW6O`Zp&F{uKAdu~k2cYbU>#KV$ zK$TlqwvGgK8f6GhQvI;B{Z~`^xlciC)PhtP0^2QAhk^wPSncD~PpSi{gvOUun}Yiz zo1TbQ-SkItSghF;SLxaK1UF1Z}wTTzH!h*QO0{}0|eWQF;5}UC%5%C_hj1EjKkAle+ z&j+C%ibNkC`&E?1S?puN_~dHFq0jb4Yd;<0ttw~PZqQl&Xu96&aao43L5WA%?1R2o zTGD#O%#X{&KWVjpDuvtb(tJuuc~m@29e)IAJrAG*pYK7*W#rgD|3Fv8#lEL3IPkjn z1^Qqda;Z5^6}1*jb@Pk0IJMRZH_aoDS$pberR7>g1pp`6P1M zqg~d}g6Hv*cO(%FCy&W6?sLejBKNszkL|IsuZ_G?^@s*^t183YOS@>jTO&FjzxHiv z*IcD$)^g{~dKC0fMvvLIMpk=SDqQB$(KN}-pd*jD6xdFlzyBf`*Kbu z0DAjC31n-&2l{Wvcxnd7E|Wyqze-rYFAJ14o^FJOKOs_Q`++ar`!bqlk7GxdO6=V6 zcwXA^Xg^+Hp8j12l4g!UXyTrJcT59%sIcBqbf4e%%1WnN{m(Gg{kP@ue9)j3y3j0x zC*t17VT)D`{b>9$M~Wpm+ZV*|-2|fNw;8n+*qq0o26Pu4kc&mFBEL>kY!j-%t8`V*1s`SjMa)GC`4V z7^tBifBMTzoE?+g;$G4*7jAPp6R3`x+|X5li*`A4a&&Rn&pX0F}0EE-ps#P_c zwtdJOC^5`FCYJcf$~btSj0>rKsUnQ5a|0vvOWT{M=6H$DQWgyknQY;`qNlzIo*ZqI z#59bHs}3ts+A)>IQxN)wT8jYg3R^|N0asToEJzfPO!|#CZlcv=V`XfGwRM4(5uzME zwDQRCW=wQ?9Z;3>82HoRj0F5G^?oBX0pWEa`qL3jm*$sk?Q~CO&CCFcSD#ekWogVF zg=0ku*$j@w{|%M=J4*S>{sXO8?GbmmJl$#21(^3i*EBF#${dw&07+1W<2;&a1TBER zLV%1CkP-B?=h2XBl>)DOTXuOA2F{W7f8+h2RbJsCRCg|Tum}H{G%Nu0tL_2ed)V*0 zwdBv-oZ$o20O+!C8-54m2sc&$nJoAfK{8?j$X(uFxKa)SDh>bIW==~Fv%G6$(7-+r(|ZlWL#To07S0Wya27o^2N!^h;ctN%SF|<-fgy|F`E`f)PxHI~ zZ2gy8^PhL)_jf~QzhZ@z{blv{s_(UB-cUEm8b87P7`|!-cz5c_7^rgq037ezCX}mB zl7t4}DWpJ0Id{&xxUbghr#F_U5E;t}doLB_XCShI&NFUu&!|F`BrYdlxPkK??pt}p zNyLMgq06@&c8?}0%dM|WTu(w~{O7D*i!dy=EE_Zm3HjXbS<~81F^d;j2_Wdv{eGM5 zTtH2p8x*C@?6|GOMP-l$uw0<7uy6HswQbP@2bP)h8yh|iio}4Q@yc!`tB0{jfj}r3 zo^inBT05mL6NGj2q3jO0P;}J{;7}GZr`$cb|9#9$ib>ifXPfwSqv zpuCQ#JNVfnkkY)!Sl&MuvpCx;_W1#9g|Lb%d1CxI^a}Ya%b=b)ypH6jL-i)-5MeN0xs2rJZ>5onE@+q{chIU~2M-PKa7NUd zA^H)cle8aBsQd>cRqEHk!4`f~yZVM0@V~hby(C}&vc`YT2>*7o7J@w)s()|04AOnr zUAb5JhR$MuB7pK6mD~d{)KE#6ZYWp6v>)d#448qesAZ8KN=@9e~=3nHW>jViOhA&U(b%AB42S-H|( zp7Lp)U1+WCv#ZM((R+vES8yRvtD)^7=LiE2($00r==e~}s>K{#0;U5UQbm}Ube7sr zr<2=LK-{5`6*%vxozAT8q^6w1`*S;<1s=BTwhvPK0-33pALigds+G0zpa*_r?@{{) z2;mBWFT?;T|DDHck#M{YWSM4Ws2xi#CQ@Ag=s+QIBhBj~w6&w7=(*ss_VIV!f@vY| zrn}|1lKP_R_HS@4PaWhM&#p1xJJ+)dzhA@9PqFl?Ef`RD56rni-*U0)e4yqhpXd_a zW6JnJ$X2};P!b&kmOa^iyN>Pt6ek-Sk)!^1!bGHmstt0kQCpfS=I2!!%1x#U17DI2 zMP3nw+*>TU5J8$KO3SOf;OCnd@knllGz@(`V0)!o-+1w9XKzc43XLfG_op!oH`@kS zBjH2?cYt;@a80Q=I$_$YzQNNSffe8M)kh1`E00CWE2|kBxr~kmvbUkWG!JhfR?9s* zSZ*jEf~>nMzq0oGJm+V~F5;bcR$X5|(VwtnXNm7#8lP;a6R`C+*cW)w7~)`%xk4TZ z0s3>*tMyjN*UCXtjYGgaULph>ClPhPq?U4LF8bTvrfJUgoFzaW*9T|KoB*EglA_x` zWmXnV0CByr-}Y+Y1m;!a^CHIuY^x+#lrP5z^@Qp_=EpHxzK}KCs+svbJ-Nwj_`@l{ zo?Y^5md!WKe8=6V@k`lHZ2kLmdu2(lF!cguNvRk^*~%0ajtPrLqh7cB-#$q>qnUso zas#V;>0ftraR@yutKgmRKd+0{kS}bxftYa2f%!|J`yU`qHcPCc?l?-Do$LEM(6}Si zQi)|iI0gscEZr#5O5KO7Qgxxsmp{nKK>>s>DT;0YMg2cOBId)<-Iz zmn)S{rF?%{BmI;%%S%nU%>IX!1yTQHV=MW2%2GmI5EU}~xduhjigoIt;@CSyrbaK` zKF5P*VkNh<-r*-#=AB)n_R1guM~s<~z%?PoohP~5B=``m@)FoW4WT6&WifTeczsWY z9{&-sZ;@tJQW+#aJQB8!$^OO3Q1ltYSz(y$L`4Bql0DB9e`~|tNT$zoK?s19uY5tU zyI;G?=I<~1sCojNB`nu$Tt%jktwU2+_1*1g zbP)Y4dT+EUoh+DM-eNJG=#h6u&5Md`oux>G@MUNc3}(asd9k3a}{hG>Ezd*-| zB#_lqc+u?EWv@#gNyygZpv5Hy6o5#lJ_rqLCHcT0dh(a!+R*uL{&4_F0nG64JB*zo zRY|`4n{V6yGe;p7k#>6S?|TOAF*)96-Cd7i_#v#N{F4zURzer2cLEtn%0}6 z#ve*p_AupmA0~_tnSu;DDiAdX^hAX9QMz%fq?7W~B5&b#%p?K9Qx$*GM z#CQ?ZX=(5N^0c_WpRVK_sp~^nG1S$;fOM)I0He=VpBB9nCOaq)k>E>UE4}_`W(qi) zF5}Z0b5Okd){jZ+)$*VL%J6EU@GJ?l&;dt#N3Pm$9%rb9P)cJy7pzQ1$#+uohOt8> zWR^8^@M+lYjR?V#C+PWGri(37!(}Df#=Mm>i8Pjkx%K0m~4N8!cVdCD(i|Uo<0)Q>o zbjXMHXgQ~{VPdR~hnaEyTkmFwR;1UG+b;QoK-Af?Z2 zaaheN`cnkz;WT7q}EH)Z{n_>Po-~7~f%UystpLCbkh3l}`U_r#4 zw~z5ljS8x-=)=BlSgJt{Q}e00N_Q@4)qOLsKbZU^0RD9ezwd$Jo(K4wdO-@WSCmUM z_a+s1TNGcd;l|f}iR3)SZy*FvObx>~N9s{k{Hyf-nPai==H`C_1$c+Cs^kVr#rzS$Fz&mI_X}r}@>W~Zaaor^trrNoYB}i6&F8A| z{etW&H&lpb!9zY$d0H9)VQcXUV!fI#YHcUOe9^QmtJkt9*F6)t} zbZ_)DVBOnoleNC_IjQ^6C(p-3iZW4Tg;hVU3ju>F^WEv->#qR>?J+_jtt#y%*0>2} zJ?c250!Sqj0#9=nCiXu^Z(zBtKg2~^wN zx00ihiCm(-Y<;a0LsKo}b**I>A&Fc(N3Rs`KNJVq-g_FoU$k|(OLGXv84ydaU#Foq zADX8C51o9|F}In#i`l*-7Jkpy{2poLV<{`&>9So*YtC>Wsmdd%!0ECe_|46y)9O{dXu=lG3Beqnm|dF80M4G z2N)uUMWc?JuFr|uFAcRKp^YSZItn(d6%EVvDrLl+9p|Pg=D|l@3@A1E&_+^ojVNag z)%ZCJ3rmw5nb7ge-jSEEuhylE>Y&@y6&CJ=Kr4mYMm$!>lUrQ5^!jb~fRn3-9vKn= zZ0v6$LNaaRzM=)! zabUiow3t;Sp`;Wxk9D&8Vs8b+<3l=C{`I;q%8GzRVZ6z?#UO_Ba@^WUret`kJ8AU& zM3ZNeD9(-lzG64omkoKs2&=U?OE+mHF$OU=&0w8tL$37}r z)V%RcMNcEgxv}-gJobZu#|wc|tgi8?Mg7amkBlecZ)J6Re_)5d^qDU(L-3BTjRJ3B zg?2?g&0$!>Y2!3k3!z$P0m*?=+d82Rw*yMi+$jlsr|62q3GrQj-Bq1v!>M+^z%JDk z!4fkLV{>Tqdu$XNM(4zL+)3N>Se@)~6`O|jkF7}Np=UGKhz3c!&xaGY!SM%o4v4R{ zwSU8g!khmKuJ*qa4bu1oOaa&nXY;ss-rXhglHl^AN}HMKS0N3s17 z`<$hFLoc&hKc#}KIdUzonc`B+;Wji`o_7$af_BKkXY_11hy zOaHfzXnxxRxS*Q+*B*Yc**g03=Guwi%AxYo#u<88ZU)^Vz7lnG0ze?}r;n8h;q8-6 z(EvjqvYFg%szjyiFFIP-(|*ga7QWBS{425Ye;&*7C&l|ek39NMHfxcciZ4%3cI9#QElU+AV}ErR5y~nN;bI*3Q(;4h^gAmu*PFz#9ggW6MZs;9_HRz~9o5kLOA^a0)lUy|vCAWN%Q6^^N5 zu_7SdKl3<*aIf1_mbOTH z!#)JtRA@d4dVbT>a?YGGuPa+0mi!>uyOthaMyw&ls99{JJ2^o2P;e){*N{?#i%IxE zqko(hgEo=82sZGE4Oo1>C;`MktiW`3HcvRfZ(hokGB;crcAR5Xs+u5x;aBZ;H^kW%Aqf7lJ?Kl{lsq>kxte1cYAQJ zj()-;atK2BdrkO2NY&l7{$VQCoBz%>bqyszZ5vpg7oNa3+cR#sS`hBA#)DxXwV*_) z(n1N~mW2gtGhFTa#1=`P zG`&jv#m|T&+~5OPDYqE#!$QA6(AtuxxSgFq;8F5Ybb>vuZ?h-p%GD+%hZlb<-gO(6 zQy89p=QmzU%+NBQ3EI(x5h4v(SzRpwl@*=`2*STMi3W$nD0?5az}8)eRom7D zBhIy}XFGBP^pqM*w;qR#^#Hf*87bO|aTnUjs9WGzy61gPNkSw-@Ss@#kOVo2@RwXq z&Fd8H^Y*!aRZkEmIxL8 z2-NJ$F@gMB{^t`@=_C2t@<#6lVIn9kuqJ^=D}qg#krOQ(L5*B3O8TWB;3-Jz$I{YX zx(rmB-z70m58vL~$b-()FYMh>AiT$EF7Z=Vq<=k4Zimw0W}qy*%z{sKaQEzW5p*LNjyCe}|SYdPpw{ z6qMmmAiVf!F0oSpFFkbNhlnNM-l8iVW+4Xd4t~HJk8kCnGdIEqq?c~HvDP{kH;M;L zVmEfA?bgnl(41UrGjdpd5AXLRGwi$zJppx1$3-uVXW$%6+iwP+Ms2->Ksx;^|^ zY~uvT+j)wi-RQY!_)b55sD`qqj44RNu9p14yEc#!B{D^RWZ!D3F-1np%78R*Sq^{r z(Z+s>PH1*^fzDs7Hz0xK`5S31J(Toaversz^wR`t!-70NcWW-klfbQSsn{?PVRLiD zo9=WH)Oz_0xWKE!Uh5 z{kPBEG`QF^kI~ubC|&_te~!a+rGD~^wswy;NMGc0wnNL)YZ)irte8-IQBU8t*flgC zo@@Cw-D6Jwxq~otd~*^%q?0pDr8?p?H%8T5dA9Ao&|Ehv!X!obNhFmZDKJ`qIzSV$ zl6Zxm-{@G~iJnk?t70?SwTqX^0Z&9Ny0cllPB*p+}m;%cxBFof4gJ}B3z`3x_rCVIv=)pNaThqElJu+tg|Vfy5> z7a^ry>Eq+iBHoYDDHLq-eLux^!qMAgnzRIsB=@0B`Aw)_fr^@HCS7E(1>sgd+i^4y zi{&c-X}*7^=#YQeMrFz-11)aE>)dBdeW2Zr=YdAFzlz7Z1%$);>ixIPDEuh)>QX(g>7 z<(CerDxPUpS;jJc?U2b;H0QjeZZPAGro*J1?L;x(XTKePCzHsm*bS~2*%_LZ$k+<` zO2x4??$=b7poV-U%^+$=x-+0y!P^j>mHs+rytuivPWDL$sq+4UOQ=xP>_yIIp~Sb2 z%EJ`D-EoJCLqs&FI=GD^u$%Yf;TibHDvgAiSu*tyj~2B8v-HR=wRpw!_|y}Y=a|ae z+HaK6(E}FyaKXS5{gE+Su_%qrlM(cyExf7vAdEb52gqI#Vu_NI_Ca?h&~n0Mz> zWD1#)2S`ZOG|tFk&s}(PBtdVXdf0(#*y~0~3Z&2TWP{Y_(DA|3@wz0f_leU|dSWfu zWF?XJ7B{|S>tEVQjDgWc?O{SkZ*{|ig5HEn)mztj{aCa=Ef8Wv#&Tnp<9=3I;fKPE z9^OW(y9!DLz4Q>9#2)?#d9{SP(b*aOS=Nzh z9j1DfZq67n4O)5$%BTTaq7q4vdi96}J3ZIz6h!H9Kq@=S>(=%K7cS{JfmM56qIUmG z-PRJFEikuK@m(Ta%;pctaL2b{bwV^>~w z5KvuI%lzf&;5O(8fDfAi{f)wZVNR!F{3~_4NI^g~MW=pi<2k<49bHvHZrdQRcw%4H zzrkccL_)^Lels95b`C>`^#K7Az?B`!(XNPI7QI5@zjFctI;kx4L39RR_$r?0-A4dp zJ}uNvTh_-~fF{!qR$%GM?mj7&i;mIcyIQDMM|o>+yla>2!8GBwU$A#tDZ3H)G(o*F z^wBisMk@==8%{2rL@Q0CF%^@y_V6dZ!K zYwI|VH|j39422BfYMY&y4Q@TlzGqoP7cd&2)wBBQrYyx$Ht##}FmE3^z&G$)UQmou zY8WkKe|0q17@sZ?{#`2w^^p5y{I0ShOHW7I3Ys%Dz*FLK)Iqr2d$d9E1B2e^dvR-yY$UfuJTwi7C!x^o*!RH*l*`|2uP z<2%YPO$xLpiF|p2w3b6VU6hp=V%=B>0?5rEJ>7Lkp`k8wlRaFIWxhr}OAn+9 zexQ+bh31NfkYZZtDLT9xm8x388kQv$h;t*HRqbdafdw5 z)iEc~g-p-O^JDpg)v?pCkbDvsX(ZGO5#-w=W)m?HY>`#?io;1ty@ocfeg=;M-wtv4 zPIC@?d7*N=@}xmtb+|IXk?JP#xj)dGK2U5UDA7p^+3}a&saewnaz8nr!WJi?OUnI1 z_S{aH#$O3%-`@^u?NwmRrHiQ(p4z-s`MB!qg-H|b0gZv~9pQY{N!22K_R3|lipk+l zD~bYCu6(F9;On&6p?norO+cEXRXO|qs6Rz%F0M+?yE-`fW~>mppM@1|`Hgf6Z9`if zC%E?KeKZ$nKjc;z`o$5kjbzT8Z!*ftDL?S zgX33Z?{^U=q1vYBOzRXIdb=Wp3w97WoI)_|dqM=$M2&0AsNZOj$(p>|1(?V&bca&H z>N4&OnJt0|u+{vbFPT~g8*%iir0*o1m>IC8dmo4*>DuPJ)PKJ)e0ut{e=pj&?ua^p zH9=p;Oyl9Kjx-hv@vziT%v*t{QaJy@m^_R@(ALx+DXjbAw@}8MSf0>@6c2t3_@pPb z(fiTbIs-LS%q+~iTuM1VwwDB;O}<|JQv8!P$(87JVKb;+akw6nE;=itCpf-jY_@8K z8t8>$#ag{4rZ&*aow&Ms{@Jy_1Aoslbp-MK-7LIwB>Nu>czuJw0U-8^_}cPcIPx^Q zN2+E!JdGBm#bw_5j|=x#T%3A>Kg$eyPwv}I&{C4GGH#LQ{JzH0is$>zi)2ad2KiDL z9Y4K4@kH?T-5S#rV@n~X2+Af@aRMQQ6?T0FVEGcRKson+t@7{>wTFN8Z+?T7QZj-O z6^XRHt+Kp;M4k5WC_ZO$(gUb!V6{TCPG_8?tk#!GSB0^LRXu3)q2%K)LWjHS93P3= zK{p*fo1AiXX$c7l0ljr{bsXYD?QK|fn>`T_9&n0g3P0DvJED8^J;N6qnSxRq$ z@tSjD)qsn@BSB?rrEWLsu@})_yG$pF=(7^>b@-ehRoH?*XieKiDSyr|N_hO#V7!cb zU9yySRsLw-0+s^Do(8{CZ$5onZ8vgRJy0l^J3dd<5Qy=z@{`=b6$Q%vVo?`4Hb3al znW~?2bV%c@HhwlNcVu`DRpq0KXEhauxSS+W?_ZXpzY?d6|I*ql(C$6LR#jS>d&y{M zMrTUO^r*`))KeKfi71ly628%+21HK4x+M1I1Mb!FPh0|6XZ%YY?Jpl>{7-Aen4Ie1 zOMwB-C9%%YU+%st%A$z2fq%6)Q~3(-{D<$_7wE8vGVJ@D!(FhY)cbkIpvJ4Eb<6%{ zYsb^MW0R!M4#oC0BY%KQTJCOAZZV_&)N%R65zTJ8Fpny`Rrf*HS=z&z%0vqEI6`h? zN4{B0y4xQ{5yy$x>$SDS6Uc=rDW&0B2^OW_SlU8SiYb#_?^kFRn;&Th7(gK#%p#3E z;KFUVbB8xNj@(@%#_g3k{1OO5mC*|TI>2B1D!*+1|DmnTxv{;>v=&Qma%wgp=8gVo zo-E!yhGa#-+!utG>B*0)iObAL%=kfF7Jix?6O=_eV&u*3FvB+2QTE(z@DRj>S{tH6 zs2|7WyfJddYlpy7x(?fEyd?VrG@c<1j5RH-DL?rh>3#ORb9xQ0ZB>Fw%i*V=ZH6*1 z+q&f-Jtrp5|DF7ihJ+q$83w+d=}1=3n)O~X{G>gN)u9m{9Yqi8=wk8U7q(4+P@%m& zijLK9BF|@K7&#I8ofYx>UfC^%bL`7gZF3EB-@p#bX0t+aTLwn=vDwy$u<+>3%m}aH zI`Ztm{G^)3$1KmE78xc3ai<-PLV!-^TK<1?tV!rWIv%pj%M^K<^PFw$4j=MnWVc=(QRoMDZh54{x`>~_9hetp@ zi-q<^YV7z`7Ire&F6jn+|I5VykrewUSGR4rv4^l~AnqO}Pg}i1P#5$gYV=Z1@SXs@ zSRqA{zrLi6tA1+%zna2|+*m5^+v{LzBb$h6^2LAQa4X%yohVCN+`Q6cx_P$AQS%WK=YQo$b%JFOQ`CXXIfr&{~6HjpM$- zy0C8CySb}&k1}Z>+o$U}o?bI2+%5z=&w@kg+p_AdbtPdiZkc!w&Y*r+up3X9fbFXLRViaK8`R44!55Vx4MG`~kwcKRhE*JkGxRK5#^(f$!Xp z7(a@p7i`i$mzqobV^*v~&s*-`Q|9R5QU90_-(i?2+`m#Bhh*tNx8L@Y+xBfn1?P>Z%KL7_R82QY= zS98Pi=3#O{lfyO)cz9xrFQRsfu8^0R|)Sne^c`}|EG1yPj!B- zdZ24RdJkZnhw#nOpV$rH9F~BnYx)C}p;}>z;-^6EVJKM@ip?yMzs(h(C~Ch94GHs^ zcmNK+{BWTZDvMT_!Mjxh@vR-9p40C$En(hEs$7h*@x~-0-NdoF)HIPvK{RUs>J}QT ziqn?qI?)qsZwSKE?^U1QRMc}4d~^XfmvWc;j-waAo@SdovnsZT+_8r^9dv^4Pc2lD zG1b{6QfdHLuY6W|1SPVRdMUToUbg;c5L5#cx=aehKpoI79wpG__;cI!{TXEsK0!9B z`VDI=?^bUW=NHwyi5vX~P-O6PTVnO`Gh`W%1SZ}2%~=xt+If-H_Z}&~<)*{V3yl|Y zuZ8?1@6Fmjip);S-H`tt-vb%RYUC#=(`0$Mm>RZj9FF2OQUKeE&q`WPE|uEC3what z^^hDLCE8#z&?~NzJb#GJTXUb9(P)at7H0&Kh~kGLJc0VKMTGhe>iR4ro<8y!(U70S zvrb;0?9SNf_3Ru-F;te;@7}6@9rM%Ueq5Uq-vN&blUK@YXVJ>YK|`MCpk6$J>qs~` zXzIT;^!oYz!p8(E6CxzkIr#&C{yj04b`UGyUV&rwccz z;=r&T_+#9x1c($n|LY_sCbVrshjygc)ue_X902yzDVx@lh*y?U1v(OFWfq67jV< z9CTb|Ed&yNphSpd`wJBJD=dc`C_lXZTW9+B>@NPJZA@D!$M?&C{)h?SYk?K&@G=(B zjrJMD9s8xqT^s=Jz2IB8*n&5Eva0;sZ8)Nc=P8If01e0>FHoZm6fneV4g4g;6pVDK zw)uOoo>p7y*F6l$^Pj?gtviFdh-=WNo&p&uh>L-QV&aa^yni~W;j|^$Uza_NWk=V)U@AeU_lEuH8VLV`vU3w5Qih~) z*D@6!wS!M zs1CuptROXtBy!MPb5=aWV6t|lPE3GpcS|z=%>f}s3-3XH(OMrZ{ zg1xJ$@;K~H8!DC(-)dU-d^B2~_grscx9WULgu;h(A&oXm!OX;gcqYglGKZ_?T^@rCXCft~@4PbLgHHhv3@PfC zxzK^}OQR zHpM(v*Qk^5MJ~9n^iMDq`413$?b83(WXNwhm!V%z&xrT|pvDBii{;q`!9!6!+FN$MbP_4<}b$GT3o^)0}7j) zTiOHco=3(eCmhyBosXsG4ibYeKM;PgU#lRW>Ykd?_9q4khQeHe6TbfeIx->Mn|Rtl z9VjOU$!f$w+G#v102~ne-(7+q^OuBZ%3ARNHfI}j2lS28DCo2o2o3NaDFc;VpFNi| z0}u;+WZGx}7q=Lr^-}AUYKxWZd!)MfN~0!XZxp@WGEJY>bQ%W^_i^+)jqZ-0^jJlL zW5ljWSznfaBnJXafiBfAQYbFs6ADWEKr>(XmA7awL4Pm07UCOjwhDPGvAWo{4rKG@ z>M3t*bms`+`XK<(7jk{2c`|lsCh~y}F(0P&ah`LAMOAaZ%DESlpeS}7Cv&&cm=?4r z>o6V*$bS>r24K@79*(`F4R#_30hxvHi2yV z?Ge*FMHn9&OdK?Znhn1xpZy;$?&~F3<0#V$em}{Ajo9Fp;F0xbpaM_K#ut zf4}C1LP~owQAKsk{7P#r4|nStU8vk;bc9zEDsktdBLEU##wCRt%$g7KHnfJp-c=E= zGh=S(uFAHCkpC2R$Z|W`?7S7v<^QBQzHQ3FYGkAd*5xuoy$OFP*=a)_+3NYx^2(#_ z1)SjW!Ny)PKpp41F?s^bG0P^T^FG!n{y(e3lg(4ki&{oLR23{YJYRiDhIcF0hyRe{ zeyj21z1^3GE|h~+qtw$R0O_4q816rzJ=UTv2gfNN!DYkH4A7mt;*Z(oKC#<-!!tm* zL!Ojq{bSt9!Os1>@*+~J2i46`VVGO&pq{JPep=Hg_>f74cff!AnqV_;8TL4zii}*) zAvz+k(w4v6w=VgNYCh+1`D~vKkUn9%@t4(I85_Ib>0{pMYeYd~MG=cFg+zBBC2h%c}ce#dMJ3kl>^Qz*{!?It|1B&=CLle`M z0qaj#Me{mQqfS)0pN(1ZQC*eT8R@Q#0L?DaDt&OA&V(ST7YHWP7*_yZ8{U*@wC7ZGbE7m@vRnk#CCa!x+ z1Sn^qWXin}=JDVyib!S~=8{xPk+c=qPU>ME`i||Yg6_un49`!%le{6!O)?^vM=th9 z=N1FFKL5gLD21jCxgpl|@~NCHhcDl@;zJ&Jf!ZKz*Aew{i?qhQzg1nJM*bDoVke`3 z&O@PJa!J{my^56LRsDsnL52S*vzlr^kqA1c;=*gyDGpURRhMiPqU0;tj`$`zFV71|>_yPaagS(K-Kt69@Z8~z2spX6Mb zQ?aD{@wJ30@+gxzcgW|}Z)PpK(>3K@dKQ)2GX%IjWO4|IgZxB{%Cb^JrMpuVDkv&W zG@NMtR7oZnoS1r`b1}G^k^OA0*^85S<|3hrcn$PCQG-CHkQ?pdn4|$~pt@K;>bbu& z)@7Owk;Z2Cyp@Qu>J(A(L@4^BwDeEJ{@33>-I4#@E%|?U45y-51Dl$1JPbMH>X`&w z9OLIcng4jWT+5=pYq}9&W+z2vCJKE z^M4*)A8vC#&-1AoQ7&&t3hGhkqa*#n59ps>&NpPqD%5-axZENjz%I2(%fpsY(V`ga zBt327IkoyutLVUZcGoxP;JDjx<`H>o-rRIHOjX|mGLfsmP=uSfgxaP}0up-AgmmR- zNyW838;jBKZuHhNVk9N%7#_6jald0yLBX`j%M}zw-85Q3YXpRuZ?CI4mF0 z+}J?w&L$r6yQdzp_xCmceskb$N{g732+O$*FAt4MkJyKVtS#1CY=&I#4{i^wv)_YE zzaTt(6MME)A=Kfd8VZqB!PvK#OpK>(0;FD+)m%TSd)e^TUb1|g)PH5c|D5&-#Wk&K z=TL2COV;5Nol8IPEyfy9I3omS%=T3v&l=5mxA}z`dU%bEe^7_)oRU1mh>hdheyC2BOW&DIL$^_}4fd|Hycb#`s&&GZn zU1xn>d8XB9r|-7}7Kjvf86kcwzx6F|>pU3Qc3{rqNLHri^hKkf$D()D)49u+&uK(o zh)9WU-Z121idT3yM5dX_YVP{mEKIA(Od}f!-dP; zytWl!G{O55bU6x60vW?*TYrLbx|ziWeMD7>k_|5s1HR3FNOJu>=xQt0UlmzJN0h=Ln6J;XoFq_lU>}U-FKf41 zZb&AEZXj#Nx|X0C%^b8zt7}lwr{eE2NZQ!Yp?>C2`ut6)WRb3azn^QaZ&qz$Y`5sF zvuAvkruPDP(Xq1)^8qRbRU)@&g&m4r{{T*wr$9$mtDTGj)(0>M&%+7emDjAssT~hb z#)V}E$sZG4 z=djnCkmk7rvHNa4AaQDU-(~0du=F+-U0G)H=Vci!5)s%3#T9bl#%Y{qdw)~c+_?h^ zV~K=&3Wi~7z{=Zd;USzU2Hq^uTyj_0oyNvtpeIcMYWDHJhSf4qcePu#|aN) z8*^M9jB;Mze~jM5ktM`fa;;M4r=!0WiNEbEWH}Yd%3Z?@DyI_FcimO!PLR;c7 zHs?i6jeJ7ZSJ=`VGdHInu1p<{T5|z1pBFA0G=5daZ89~1nDX1p6lhz?&%To1-+^z^ zN6tMEe@q!D`Z(BmQsFA`%+PK|1?)VMq63**QGZmnT}^ax^D5LcFp}C@mdCQeVlW`j z+X}#>E}|2#?@|vl9nbLqjPxi0<}PrLg%<~WJb(oN*Zv=)qOxJI<2=_=8t*U&ZGY2g zNOqNIUoh$}L{>QB%H>dr_NYfqINAaGaZ${3kCti`}xatfX|hk1yv^!gPly1<#? z_TB505{C&#U5Q8>GqlFO=eBH$b*wg#OT#3f_j|DU2$@NfeqP}bQsmld3{9xygLPqn zzZX?v-n<%U{clqhS&OnrrD2;cuxe{98ezaZdw! zj=qc|pOs_luc1r14Qx=jats~yzjS=?gmJ@_KhOV>gtI31?(=t>f$`~dVpaEeGrzs3 zOUI>|!GR$>In3%s%V((IdYZ|yH*ugoZ-Jw6`v*p*Hk;KwGD2tPpvG;6Ah%#lVNa?c z9&kPR*jeBTT}IU5`Pg9qmljKvBlCfYC-MD zDfXVvk-sw1>E@T*wyG5PVNgH^CI3xJ4nhNtDIaBYXl?_GU!9&K4gyA20C0>+t+K^ynIy8D-QBPrmNXV)|jTU({+C!+eePj zut{U4k*ddz3p8lCCT=D3*;TqMzqDry_0T3Or>(wBRUfQa`^bA^r{NFu08lg%6L^Q3 zE8?`H8chqE1LO`L@rZ;@_^Mu7ls zZ{Om_(3DpK2BGwN*2qP+%lpsh9s-+SiK8m*!9pKZYlfzJ7IjT2xUCklMGMX=h)Hel zbrN3ydU~0bX>)?gvmuR8;LS6N!6PVB9iclq6lb$5n$G*}>*s^qa3Y_JY3qChgTAaZ zSfK{FP4L5TPbRK}HyT0^rfN5%Q>9712|ZRABF-)j0;5ecYb@?}nnf=x39~TvE#I26 z6TaFTS6(SWF#V4(|9{WQ{j(JCzeESDys4(VSJ1Tpwpn`lSeC}4z3ZCTZUI2Upr+&{ z_l0$+g;GYDQ$<1?Bfosule#^0(KJCe4xiTLty+w-+_CJ-^qM~!E&aP!&uN-R7VESI z&{A%uVm--2|7dbhupDi9zz6Y8yYA1f-?pvJ%_(6S>Dp8M&-tE^X!1M}(p?6k4Hym! zE>H;q|6=b?0?l3V!vSW0wAepjYP)5}lcI*sQ0iv^S$PRE0sWrZBxZ#DB5rEdcOO!& z#%U_@RS|9_k)!$w%@Nv8yl#U)-{y-SiuF@+;&sl%YOK#)-P*G0{_S0XSo>|{3!og* z2k26Mahnh3(jR6AYNL7|r@g<|g8N#|`pQY9U*ry3ed*>+@jaowk8WX;jfF8~!62N< z!1z1r#I@5(G9j$bU+;nYzK6LO1GaP@OY-k;n^SerD!fWIvk|FT<3l#3siFUtHe4zQ z$%p4cDQTjkE@n%bMp7a!!OT+(URK0+=5kzkt|-$$ZBm7%Fg-ov7?13OI$6?Y_FmHZ zROQDJjbPCgPyWmM7ipEY13w_S({u|m=nw1s0=q|?yO*PO6Yzpzk`lBfZNRMPtcUNHG&rZ9F2yw zrZgc+0SIM>h4mG6e zAf`)Q}$e_DMxA$%GzcaH2RBjfDsL-gI}sofE~JTppS--uNtoB{52 zultND63_6b)9lnBXl3zA;w6qgIJ^Yq!@%ag|ITt?f9NEiS9OF3K{K((OU#@S*WjJR# zVXw7soi0B9iLo{$6L)#*LKvjtZ-T>n*Q(cOQls>};3jcJ$NIXp=yQQ^ZJ@Fzu zE(Qb|t604p3kO!?CMW%8Vt-E$jg!iYEXARFeF?f`*Oo+bRcD`9eG=ckSvI~COsPF5 zZ#?4!R9ER^7P=cWeP2MEQvhA;^o0DuQ)O4HR|8HE4s*t0^eJ3-YMPPZljGd+ z8sb~g0QxE%`fRJAem$!WlUdS1*Z4&l`2vu1okPH*;I9n;KvaE5>~wo1w$lk{fzX?v zS2^d#KPvU;5dazG63kEKwi+nYh5%Psq!>C6WzvcO4Z*q^0e_Hbm>p1FGg$(U15pVN zP__fKSDc-n96ERFe}d8hNtvJs&Z>aA1anUT5-6!pV!X&^@{gtbpZ072{ohx*U*n#D zvO`3y;bznwH|i=5?RO&NX&c@wkF)9)Am*&{`GThM%YK6XC5-z+&<4``|M1TeK;+$6 zjv0@r<{13)P`m{QNUJB{{&1`2mB*on$djsbKT1peMo%iwElZ{NY>>FT05mk@`dFmv zF9N)pgxjMjuBCC3p$fGqM?xf0iGJVY|LYn%nwmjFVYq0yNbY9>oZ%f9Y+lWa!!5p* ztu^(VxmEnJO`U-vYZCg=P5~k&cd@^^QAfQ!-cyt+0i!@iWD!ilf?QHVEqvZ#?`u0J ztY&8f1w2OzccO!c-GYv~w0yy&-_tMwq1cRO0%0`s3yRJ3a1VpMX$h;6 zCnxx4Yz)tHFea15`7rX7eKtEt9UdG>(JS>~lK%{Ov@L@9gx*uOC7Bk&G~eMJ2z`&S zh(8ux-B`B}rpw4znXa=m$ zKuR$&RfVjJm1G}LOaP7I03Z$kG5T&J{%q#|z`Fh&%l%KsuG!CkH8ar=SQ0vC=Cuuq zLp!(3=K&@9CC}{Nzbi7!=Gra6CU7S2U`pC2?g!=bNtz~Sv~_1*++m)FyB}AxZ=sA~ zvEVJ^SlDNRTOQss!mSxc#l9%l5LyY?qg=$+9~Yt5hgVmg!RWPw<^pPV$;zsas68e4 z5d&;>-BAZ8Xs)hs`!ObQ1}UjjX;{wT!<>*w9LqW_Ltwwq82<>-QDo?8EbJDKg=LEr zIvTAlrKIrfcB8=81G!He>isV7CA+Mw>|-fq!p$vS7?i`Os$_Ip>?E&! zokw+HgS_ODJY$m6{c!t*-zn>bcw*GUj$@%$N#H+EC?Fm4c9Zc9&xdgC1m9vqn(*1mehAHJ*cN zl#Bz1aOS&7jGGC5Tr$EylPEkPL(4hXY{HAN+2=9}^1#*6ANP7X6D-9n{0^DxRN&U+Kimme)_ zk_{Z}>CM%NlsV;vT_8n2MmPpP3dgiqHwaxxWxri{DHhKYXh=3>qWO8EOgAlAD2*CT zXKRZIB%h$lB zyx*TDT;Q)-DmBseEho1t_fcSyED!+4uGqmkf&2c2lvYo+iHSxzLpQ@dx&{!jUH=ua zO=3+T_5Myh2aXAwjL(GjjIYpvEq*e2mbZ-aGywCW#IbYBYpU~*7zhLkSjzf7idw@$ zt8#jx%KgzsdO0@aRSVx&g_V68;9;fj^`gt$)!Dv0L0{gF28&dD>UIA?1sS;g`UwXK z{mr$GDF5Bn(@80!n8y>FjJYHMjQ(m7_$kPh)f1Ks9O|Y~ubL~^(KHpox2UV&dH&8T z-?oUNU$Ls+_}wl6Y+U|BbWpQg<`aUxF>?CawmAkH8`%SPrITJ{#)JvuekSFWb5;4Mev96P`}!gl?tX%ORu zq}9dvg~U@tERhZRFnS9l7PyMriU7pv7AOxi@0@9^S)No&XT|jOE+aEoJHO_8ILm=5 zu`U8OTxU-A+hRBAMw9Rb)Z&_kDlieixUXsux?g|f^0dB|Wx3@AGiT`nxJ}DL?B*&G z)<$<;G?LDg)bEN(yr@*-ZFpo-qqyr=Zm=ZxL>|vTMo0ANr)Fe2WCS{-mJ;qgsDK|g zu8v%|kC~u^(?>lek&Zf{s24=9Py`!w=!eNbRoi*`(Fz(~sfr%^Q6Z29ri-cO3_(>KGgVRk109^kxTeE!Ka#f-QBHP zNe)*Ig7b%->ybWMXTo-gGwX6hWgSc4x$B>x(6fmQUD_oW@!k2%%&+j_x05Tl|Bd)h z2^35_7XdUja2H4u0nXA!8EUykQ;Yz0!Z-GG%F*smT^`86E)x?-(SOffZJy0h$CGXt zUi#ILTwdxZ8o70v7j1Kbv=lX36yTxbJ;v1wib;<6){rr3+zknhb|Meo>Abfrw?hP! zo=!V7%C*P$?>m_s2>Ayf&bGyo!kU#ftK7{~4vxK*Aqz`&tHRcUCgy2zBN9Z85xL|a zaFf3vMMI1{p{%5A+u*+bLNz0s%A5XQjX2|rdpsU<-&{UE+)Z|1mGy%b;Cr}`eaU_E z)wSQ{YuUNJ(y7&Zi__?umX5eR0>RPVD94%}hb&EETlxh$U8$-kW_7_56cPAsV0~~p z@<)JB4@BU;MNj+I_Mc@JZSFzEFlwI1J2({6LQ<*1i<&Jx)!i6BEwqVKfLvGXP~}c7 zi_FT_7GxO@QoMZAmmq^Y^NDbpbuls~;?8+3lp0uyASO*y$kIpMgHPB zJ^Dx)g+1|=^<0J>qbJFeJ{3cVCY0yw8fOZ-QLeU_@3L8Qdh}j+a#9aK0t%^i_IEtF z6q%|{nq?F=Z-!lc;RW(o^bV2p)Qp7uHpK{}*K=^k(WVHR+FE&=zAmCH$)d)YiLp*8 zW1)A`xsgB{=K42V^d9U9l(aMM<+;BdxzuwJI|=!GB|(EW@6JQsm30;a(ZZtzvY6G* zH;_q#;HEpXs z?;8|z{J0=^b5NRhJBF8GP$tkU_AWuqoeWV)ogDnH9IbQchNcTyaXqX~ctQRFwMz>+(cga?;+rQ`$)zFND1 z2j6Tv{{&&zW8&Jn?AchcEz!ywgg9X)ZvPNqX`U}u6DLs#aW^KgiLbs|Z6Nuv8R`1j zjP0SGUo4EOwL|DP^5vXE)@3G#JV}!(b@=vBeGvA2-;ww;z>(re2=f*OBnF-3fWfiN z0(ktg>EXfnG#A58w|3Tiri#|iB3XdNDw>RlC?b#HO`Rj3v+^=@Ip&L2e;5_}URAcr zhitbG@VF@P`!(6BR>I`fzHJZ1z~&(~w|0FA?u-5X16bhp{}JE+>vIb3mAhf!%FdJh zpP*>at2q|acJOm+9A^hhN>T*>#h1>0b1$$~Yy!z9P3wd0xZ^ceI~q!SG}}KH@n$Q6 zo^)xGA(?hWXQ(dnYSr&-{ zcN)cZD(CSQJ}Bf;O;yKwevdWblfFD!^0?<@eMy(b$s;KeXF_wo5Tg)jQb%OOR>SR1 z2>u3S$4~4?Ghq*(_qjX0s6)X?6-~C$`}~F^1d}|=voCvZ zmN6vyc^1`VFK@wdK#!|cQ}48%Y?AmNU-7-8+ES2*SKDeamANu!iB|;gzyyPCmM?|u zP&mG@rrwpR-4Uhs(}0O@FntVn1WydNhBTa}h6zXrPTZZ} zknQD+NyZCBZ@uMimSZD7PY-Fj?SY|7QUU1RRdt!Jj?GocU36XjIrquaaCeP!on2zW z?KZa{0nvw1JWm8nm3}C#Z&N(1cqnYNUqxu=!SiT*T|WsAe?qT-wjKLxMel;l8ws4`HBtV8=3+A+4-VspnAotVpugQXJ8$$YUT`U^{6 zEOo!35I#*)208Qu@tIsyE;@M}r2J4b#vLWUYPD~*BdmlxXF`zw%tiAeDv8v)UmUQr z0+71_wg+FbXlZA`o#IM8@1db?rMc|m{f%Q@2S$D>4heG*jy%`VYGG!QP!LTJ+)ll} zZ0SC7?;UyAkq7QasQ|olkr|f)Man2vs@M^& zFNLO_FLXYH?7&5lV3o0RWitv@u&SKII7G!az3ykabyc#Y&5xp ziAKx4t9HAA6>dV>#iD&xj!lX&NT!=`DUB<>?f6ib%q87+YWot(_x#Ry`cx1?pC9+- zqKr>30is;PO`wiXw1S7WFItF!4zywC%rOkdK+nz(Ojak~lRAi}B&wgm0Jm9D!jj4X zrx9j57f$^9=eZn9hptvK8VSC#`w_r^^G+eNyC z$7Xi63iOYTliW=JyVQSpg-*#rd*vkjEmvyy` zgjb9)xeQ2%DfMIT)(K$mXaO+i|4yrm@P})`zZt~+4Z8?9kpY+buhsziIX6E+Ek8j% zVi$T--q$c`V0f?&PE=n8s2mUD_k)0xWG;vrH~|DfyR;Pb$E0t?^W)%;2FH;<`LSmMC{+sVEg7`A(MaqF=qx$jAkHWKLdZa%zteHsmghH2QTg3 zWHk=1<3|w=yN6GS z`d|YYQl&J=E&VF7bosm2q*U2*TSr?-loY|3LMCRL0dj~i>ZSuv{F<%5qv+TqxhF?aND76lpL|a=c@?vhwL05 z+M?Eq6qKl*Bk@;m92W?s+@Q9%DYy!qZnh;NFq;L{M zWHiIpRrCce;j8^WYak>wAPZcq${Ocx9_YOc*8==4Z#B^Mc@TqAVrqZ*93sBPV$LasSU33A89uQcu=*7!-WPbwZt~WyRMI!f>ChLYwe@Mx8L`-ewg!xrAGSEw!V)nwDX}s zXU?_-QAuyCpT=*C5t{g=Up%ANFJ2JjcK(dfnY?S1F4nYcFygS~pg=@tgAe(p^iI4m zo?y7$fe?{i_)=sRPqkhiS?g=rKKbck&gClk17U;hZ-aU`+kX~x3$hW%W@NugpFJvanm+uImD>@^cu{tdPQ%t z$J_y;^x3$MlSQ?R^}2MgL9Q({o5j!TflfCCN}sUwzA#t5)q1A~5o7TDs_|L@&A%D( zO-yiZr1)g+tiDF1+^1MIS4G33+9%510{&JxmDZE8sYG|#VTE=^sm4W?lSh`5?t3g*vk-y?$*7?`z@Fy`3JCcVVadr(J8Y@8v9aY$ zt#UW%L$1lT9tGS|f|7b00g_{vzo*6b#Kq>LuKrkDqii%TPMkskkeZ<4o&7@1@146p(Yc8=$RhY+hL0*2#$)8V=h0>9c z0NEknsRP_P;RXBNvA5T3En#ydV8MI9i`d}$-<|-&jl}>@$O2;8U&zwrrLZjYK4rQ4 zKtn7m;QM#$ib}p7U*#ItxhsM|_p*0Gw~n2x;^P#)5wjJ=%Fh0ET7j0IGA*kK+yP8p zLgL>R#J@`^azjK4pB~9|A?Fq42XRb)4J3*9s!s?NE27ODAyf3Ii;_7M#A)uLo~zXT z4l&A{Y>3IQvNen934Q#Omr^Jq3IoZf|K+)MIS{Gz_!?!Dutd*H)AV8w>f4ZF8%C6R zX)*>SQSVR}X_zqxNgI$slBp)^o7vE}1RXNHq*q1;;lr43(7fO>vkK@wBNyS{@ut|2 z)_X!6G8t?~t`100^6~AD=|Q*hgJXhQvqG^?ZSd#S^#{4PdSC_#MTO%iV%K__>Oos? zg545h8f-2*1i8ak_cSe=_~>=zkT{xHrei<1d+g-YrZ+~hYPbBT4s&9Izz)QxcH1q{ z9BJ#K3z-E;d#tDt&dPn0lZtJxzOKERK61*{!k}t-XQ8^n6^dw;INrfKt@G(~Tf)@p zw%$H{g02Zgc~2E*+e}ocXc#gir%Xt;a8-~)ONXQ!A^7pDQN_rZ=tp-+iQVZq5P9oX z*38B!nHpiLSzbAPbR zi>)!b#Ob$?`pxXUwjxR4q%B0b*5N~=1`WS?0|2!IByNxj0I}foHts%`x1(vrPosuV z6}9mcntv^G&BG8?#iYPU5*8$jci_gADAMU=X>mg>YGrz1oB|Qw^z!#O(fuBLR3WAwE;+s7zN66CGEHh#9=jRLHta!WiG<)t?(Rv-$kt%X zp{Me+cLhrDl^dKz!Eha9nxS!;7@Lu4wpztoX*z&i-?ot#`AE<|6>*pD_)SD#AkM#jZC1wr1?_ z1E30wf!hC>Y_5R~4d8iS_FhzSVn2zYLC!7=;)tz$^+Wruzj2|DCBWWhhhW~ilYicv zX88(xy2p=~iU+6vM_p&MragvK6v9B&f)UU7>7F|i3ke)r0k)QU7|wwr{aSf)Q8fo7 ziuRqCpXg2L;y;nPwUh&Z)OMElE#z!Mp95V%PXRyD-=1G^FG+rE02ujm14uThBPp|N z!P2l@Q7_&A&dWMHWFbBdhjy1fm;NH7vQ7xrPmt>_ph7JKf(vWdMA&_b*bVxx6;d3( zJmr*%ys?)`#SNFpf$BNYs&Ki&`WuLhH?&Rb`s%INGLQp&u>lZri~4NOJQv2oJT$cu zHsa@UY}vVhJ7v$zaw7_PRf_dYMKG!-+*#tU6nNL=xmQ?g7I?KPDZhX z+kj34Zi9#f$tk4qf|5M89*s>B9s1cT<$|sE9Jvmusz6Zul6-ul78I40Ty_59<^=$2Pj^V@z`%N8<)NI&SU4Izl8kfb84Kw z^7<%Y=Y_b#6^1QGY;)bOP$Q1rg|f8Ni-M!Y{rJg25Qq9-m3Gtb?_w%9D3m4l=>hC{ zDd#|srC3*}t|P0BizLBRT^?F4Bn8xSJHx?;G&y(jPWl>f+Q0h=lP@NdpKk)NLSPD% zaTf1?@J}T)tff3TQ@NSUxClI}AEkei7188rTVjpcVjzoITcONy-Pl!pmm+r;BoBhK zOCrMJF#j>DR%&!EFfI94kxt>+W%H@O>-&EP9Y8ShXGUi5d2H+MS+NH&2|p+O1eq+2 zKM*-+JBgkJplf(h6@OL#NA{(yIVObG3vyBECCp#{D>GxoCyE$r8l3ldv@e_r&Y1hi z#0ju*dL>F+eu9`yV6N)+B?VGsGo~qfvfKkTBvVE0I7*aXWr`NEzo4am8(!33dF(G= zzPuOTQM;^P(&;CDHZV4|9-rdJz{tDx%?x3u>P{!YI-9{vm)e8zdpG5qZ^1$lF~?KH z2l6bASoP{?SQQ%gSQ3cXGuQ)#myE2v#+buCq9JB1H;G3qSgaOGF#)KoNORPPQE1O* zpBhcAu&@*~MHiVznGjjn5I*RJo86?>$On@lcWBInn!E>312l7c)3SY?Gpa%U^TgX3 zxjEWV`TBBw?a#A%LxfZy?rUjHRopkpj>vSEWmmP{o>z~uCoftytVhaeWO&tszI~$p zBy3sc-DTb~`KYLZ&xS6!zRx9sH0CH#b&6cn7>l{B5Oqe7!yxe_v(bE(lxhq?*7@zuVeIrV7`gr%m zgH%KsU{YEF^rL^yG^Sw986JrOW(S8tR0lyn;^aT|1Kmm-=m=r%Sp9 zd&#`KSMkPQ%z|md6-Nr=3J~b#BN{6dyySBJ(;TLUO@9Jz?*pg%yH3ECIV%kM69jZ2 zn+5cn@nKgMVbGf;@LCbTg3_F>h@YJrThUdPz^12wY2^F{a@lCB)p}_t4trYigA@uA zZzmq51CBMnBxRibuh5#vu;+4v`I2>+>0U(R)o~FnfI$07uE`MdY~opFwwV%l%KzB2Fl&k(uR?w-B~T(oeSHq>0;*C?)7@lZAcZ2JcV+)aq?=_vjfk`ju$s zqBcJi3P>mpnx(%&IOL61WvLmLjBYF;eaDbX+Pb#*bmB_*o#Q8{+^H*sYV9UlSPRHD zSDc2ul`0m6gBE#GD0|MR)s%coK}$E-GFaPD*5CT%n07(RcI99kojy2g9;uw;Juen$ zK_M{CM`E{qOMbkk%?zd_wYx00Z(TDMYc?nrD%XbydiQQjR~KaaS%+mfSaHg8*;7ik z(zA`hfdC_bs2Q(KxrBY8aUAPwf<{aW6x~~heIhek0_jUX`S3x8b9SO{K;PTgaAyBX zm`rKY^gZLQSV~IzH&#(r-RBLZHqWYJY3ATYB+~I^%!OZX#GwHgJ7emGgGKe)R&tKl zO75ZOGhsewLu)nT@JB;7O>jN6P9C@4zE}<}e=)&LOn5R_DWd1Vi>eCA>TPHjs;w5z z7v?i1j1Re}2*CLXQk>x-Ww`K0!!VWGErX%<`b?1<1;OYEN@Q zdBVz)AcMM{*QWzO%)tILt)`RnBh1?v_U>1_2mFaEmhV47HwXm3q9|hB z0-gwA;`P`&0`6EST;#7z5{9*g2A*gs1b;&_hAM#^ENlHGHkdHcb!B}@((sW#NVgDp zPPq+|WqOtX{p8SpbUvV_%fdjw4%ais7cNTty>&E7YmQgznL)7Xkw`~6GE+zrVZXry zvUJhGomL%TfFKMtNX9w#9J6GfG3@P6&<@{E&}-nXztYRgh4THl3gPy`*6-+@!qT!? zazUPf3ld}OTo=2I2BaK%;D_W^hMyoLFx$x2;?vjXP{8MmzRJyw^}a_>Im7!Z#VaD^ ziT%6-p_U~!1E>)svH%jy{xTcQ_o`vGQgqsSim>~GMKVG7jA9i@>5%(*TXo%CschY zm@eC;eR#tZn3UhLM!3cV;Ut%g)~at2&Un8Al8voP7KJtW)3#N^CnF4n&{gU7MD~Yk z!;+$!lNcs9nYlxc2N9=>ovfoAVlq1$%GJk+oZ(Lu84yikFe}ZB#pjK9TACyghVwZY z9Md?lM=e%wp2NT>H`+?x^-Jf4R4lVe%TbNd|OT)s(D@_KxqJ zhBWgU!yx1_LZ#{Wx8Yk+VjXY4qZ;`V-CLZB1pKqbjX3_7XIz)Kpu*!QJQ)!=5@|M&dU)oH^uO^f7%zqDF{)6hOn8=>&$rKqAaCTU94F(i0LOuR`(_C`ihpYPK1HvxZtYQy ze3YVZDBp;!wx=vPAK`t=KC+9V)kX)ds=2=Y8hgk48SQIjE=PH|Te95Kc}UBxF#LS_ zRY$4e%Yvgsn#OXHx8{$NJcm#&RwEY3SI9Q%>_wj$F)aqP9zJUPap7xqM|$xiQLsjU zmiIU|8))sU+;|QY|ADQCau0ma`oKCaQ8&YKNy>^YGZ=Msja4y`M66hj7KPNuDdM78 zFXFgnRO9!aDjPY%D%j8O9lV_RtKbSa>IuNqI2hfzQ51fL`7##6$k@i0bmSRN6nk1h z{G4YJ7L$Ar%>W)k4IhS&@Fpo;h{G|NgO^S=#7|?EZRC@Lu%!T^btIwXtD)otedJ8+ z^p8m^jq~TzC&qJID~rZ=(-*K-QYAb!x!1qLJ_b7l>&3IeQZ9h;&7{q_o)lv8L=stG zfBbt_)wpJ7Q7y!Cz=qxf!QiWz?l$lh1DPGkQ>jYPpIfMRLhjyNKNkj8vZv0a^g=yk zWqo=!kcX_oJIz90^G0=f2E|gVc=H$Wkxx0^Qodi7IocE^@f0{&cQ8{`V%7gxSKB&u zlrH2Mybc8Tgb`e&FCMuOTc{{M7U&|SvcaV@G*fdb2av8F)$|twt{&0Sb&Kg@Fsg=_ z=W1T^#?9$3M{rjbytAAxJ*O&;svM{rjW2dsE!4-v(Vqo#_IQke_;(SkG&~&eFUsN3 z+f%7KhwR=1=wC38G1ih!*K4qFFC8mT7>kFe=r|*`aexAyD&l+ljRYOMx{PnXE&FzKDFVw*z;uV#21_afl z4@nQvBigt=GCRO3`pm$b2AC!C2yk!4oH-7p`m)IlWfeN=T3Yd)S4Pnf30&b#b+sq~ zW|Zi6NN%wAplGT94CzO!O){H>Q%P6JpqtO5-qGGX7AF+Rr5R*uw2=iu(%2?;u4(&A zyymzr##G0YlNT%fWjPyUo2R`-qpuHaixsma#e8s1qWd2ax>H>7G$L_{qyGMjM=)Vu zD(*})dQ^cEH%&lXM_kKqhF#cZ9M^M zy1_VlIw4&zxQi`K5uHsy^>J|7d68{9VF^?`L6WFk9A2-7$+tCujV(Sx?Cui$fX;Y; zC5u!FK>E~Z;7eeSyL+aJ)bIy9`xm17KX{DfcWUuG!+P~C5zpG)!GqFY%%5L`e1MMq zca>4=b3vj0{+vQWeKQn3|)(Bri} zEY#*DMY|B!r)JLQM%qHS*I8V0qEt5_I#`}D>0HswKVmg%AH;r!KTO{bis9dlfaJ%r z@0mT{6c66$D+^I!2y#74)5(XLp&o zKvRoArsg(H;{^^l6eHljV)t6;vq3fVVjo;WZU^<6D~2nd=~l0vt!aL)v%yxIdi1sw zqKr9COakric+UUbs-B~M8bA8Uxp6|leP7~07|e(6;f%pdCQ8_WX=vyeEe2_aGL{bT zeKA39koBRKwxOo%j&A_33S-X9q3!FV*)XdwEAJq_{|O=vD!44}VPU1lk)({rlzE8- z##T_PJnZq@Yl)Z46~>gvvGr)DT748nvYF6djyot8z7yB|*9X#{Q3CX1`Co+cgnTfM z&IjUdPdZ`%heWUpr9^!DBIq5zkZh5Y?LQ?XI^}PpApO>t4 zsD+SLS3kIv$MmS=%>daxrQ%=ZczK?qqWVcGkr@s}h92v)M^>U=F3SWB3+KF=IL5(l zzJ2ry^3FA(2yFewlQR6{FVE+q&5qRD@h2BXMatQIvgx9*>w^ia`$ez{@1&qtJnX zGtqo(>VTqc9 zQV;=oZyzHp4^Vs${J%j-#>QJh?gjO^lE`kB9rE0LTP{qOJ zfpZ1E%$%1OP$tI+&|oIqMwT$#ms$Xun)vo{c`rrHaM+{Bn58fg%Q8mCe<3TV? z=obXaP-jj?#n{_t_F@M^0NNxKTu)vEve37wqn%%JI)=@AV&!9#r;ymn(NJw|@)OY{ ze%Z;f1D4E3{SUtVKsB_(&@oBjU%u*+zM#3^xf&If#4u5h*gKfm9joB%AEQ4F*sBzJ z4j>|9ALG7@*+y*K>Ay`piZ34OF$>92nQMhG*=lyA+w^kZuU%LV6|s7zJMci(%B(~l zsyD>$o_3z)kpn8Fe;sQ}NozNSLGNQ>NB_$0Db^7CV{TOcW+A?pL50~`NV zCp3K2rp9*Oh{-`2$Q$qRBzuxI+R2w*Za1ySvj^kU($=E}gHk*Is*N?Q`yT&%V#|$q$~c+0}H- zs;-*zo#P$v7`4`b-dz^V&~maGmY05HZ@}t1EZ_}*>ryfVnzH`C&!GRl{nEh=#->ys z48KvYs7`~Psj7%(Lq;TCD65D$X@ztI)cp3Fy+{AHc9b*jhm)u zPtunRZ*19-eR(EV{Ng~+*EC#XYi!x`5j)mzbPWM=i6fBgm(h5~`!}7_o)o7Wnz(R> z-Vil}3Xc8)<06OM(D}0YUjE2e$SCM;V(WoK0(xMswHNXGlD*PZKK5isXf^TE@rEvf zwl=D#KrOCnxP{nBS3$eX0FbFJ1^00t-g#2S)8CPSFECCrE{eCSMNHll+j3wp&4rk{ z@p?LS<@*_wIi*s7?teXg{$9Ny^nlGkt=rD@V?wZe-VbAUlqVj9YUH3)Lelp361AWi z;1z)+SwJaqw!$8T#i zx!0eDf_Lv$k{>i9h1M70Qa)COx@AQ&`lIkT{LMduF_y=T&}vV|jJig8G_7|Z+^(V= zHhqMP1a&=Y;}=y}lDCs=z>?WFg->v2{J4N9>d)}w|Kt^E;EfGJR>=d=@DrqNVDN9% zVSi-tftZh?_OBFx>oK%Yi-zYkiE*X>k){ySi;D@2iSYt`#) zQI4@H!^sSbbOZ)s64g*J8PB0)Ac5-Tc$Al_+7aM>AjRx#;mYOTvVKq@p z)T}Adu`7vp@H{J$Hdg16;NuR;nhaYa{Vn9kmlPA#!=-y6ty??bn^WjzA^2YhlKXWa zhn{fn@qxfJS?TYSqP!_NomkXM)Cg9Xb*dgP>KepdO)q*+bEqT4*L!czRkmbe=d>K0 zw?FFb@HU0;Xa#eV(piwA{TQQGRr_1Mun6|0g!ZXn(hbv-f$e;kWZu|eDUn&igFN0p z{o_%mpG{FyRRChZ`$_x{jstqj+~+a%+D74#av0Swr>gWgbnLpv>eTJKvjDis$c(}0 zcDy1j?W|d3Qq?JWrPN_}gM|&=qqf@+vHU3yQ=>Za8nLGRE;gHAmDPb^9}AP>F;AVd zODdLTaD*=I329w=3bta3CFy%{1~$b?6cku@ihbPXrVQq1Vr z&c=?ArAI3tqlQ*o?4{^)ApqM(2?z57)#j5R&*x!Wi3k_>p^}jv*)|jp3J_1Y#>mT5 zL#}UIE0c5 zU(pGScw473^)g#U1aM4aOTWW;5UMyVr`nK)&9*l#V~@~J(qf)Kcbe89C~-=~({_mo z43s2On)m_~i1oFD{|G|FrLn*5H}7a$hakn8nFp+`&@wDcE5s_);5fy_q`eUkD7_6Q zras%HM!Y*kg8e?L{$6b1R`h$z6{+Z7A0$-x3DPQ?fIsr_#I8;4HsLLM(dFKsfmuB& z6!!W?sf&ACw7PeG)6(E;4NhbH*AueZ@#!(%GBbLbz-SqxH!69+B=84f`8}J&S;0lC zI-Irshb)hKGeFR8z4o(dy~F^jU9*3008X0XxzroC+TNnAqnGpm`tz<7kwJEdKmsJQ zfYs`6t!;RI*y++^#M+2yU96rrgmZ(3h85X%z@7nnYe+rPk0KU{bZo*+W*SE3WaDH* zCqE8B>sk6f;E9^eo7PK{)>2R4tpM)7EOXr{t-Yid`n?FA=i}Em2aT$VCMy)0n-Q?N-D|Iv z?cpa25`tng6Vgo&@0sDTCaT?Qr=Zr=SSOeasIcN0k59H%DUuB$l-8cH<);)>l2-ea zRU@lmt__z?G%7?cVAzNjCQKCbSnZ_Xyf`FIdBgrx$&TH=GN#dljhUra#0aC=sCsVx zyQ`}vY75_(vGyqZTf#<~o@+3sj#dj?k3q{Gx__;jbw>t9fPCjY*avYuYu z>+i2WK=-NvLq5;+F6e_@_;g7+cF=V9F09?SI3}w{@QeXTlb;&NCtx+I^SYkY9b_Nh$_1!&ATO zfOqTTKXz4SH$zWsICz()f%OE|UZJybq!7-~vR@Ef+{4EPvTt|jdK$cQFFz>SKJq12 ze&p9l_R|{0lp#bHUe0myTFyPsz`hloV{_m$ztO)C8 z!51>IaxZ0?oriisxRt|_iCgOQeJgh6a=bC`UA;w-ont{&KtX=OKF>iR@~SN&C96eWniV)WF&@<)FzuGyeQ*@E7nZ+fPsd zdLsbiLhro909rJi+xt5}GGRQz0NZ`W)oMDPK+w+qnj&7qI(}V9e8QXJ;+7G52AYK) z0Us`v`@La+?YzC70>K(cw$B=2IN6WCSLyz?lk@~&v!ATSZw<{!qMi#6!p9flj?L3X zV5Os%bkIv+EZadU0SGlfp66B6-<#D{!?KimO2Ox7F={V-A?Tzec%<510r$WPwJLB` zgi3eV{4@gEw$=K#v#8IpDci+2c$!%2KCxi?18ED0Z9KZTRc9;`k<(uU@fgkbBb;SV)NTlnsvTHwc z+O4PY&_D=8L+DM7aK(y1K(_l{Vdc)bAiS8&baKC`E)KUMTOpT}C{b-gawqLWLARi*RZA4y4vzdP9nHo&4&uH_n<m$qxP>#i9bWy|Mz7~Yl?{fjbQShM*2u$e~*u~4t1Y}y>;R*7KS%l2mQ{- zx2X!vNA*ABA4`J+c_u61+03y03Hq45F9bcsPX9p&+hV#%`jI`Na>%u%H8cdH+Ejtt z10Vvq&?fVZ(#jo5-fg$d)t9@~tMSeJg4^$#uPrZlB_@FtpyW272au_Fp3-`aJ`5aS8!dGeX(YvYp%8jAh_KzeaFp;LQ3^u_ z$b&b!l*&pd!}YZRY~C)c^q!cc#t-m#^EWpF=e)E`fG;3_Uy%LjJu7?@{KqMQe;wx6 zIa%Cx+uBoQB{`lExNvXC3c>ALzmo%dSux{0T+4gd8K29;>SE?*rDAqic*VcC@SMv709R+`R;`AE&Bf*-h99KY(hys1lO$FB|l}9NO9Qp9XIZkfyyR z?ERRMO=G7C=e@zMbLN;g@1hq**u^Ek|E=32d2)b%j}R~Yie8hwUP*f1LM zt!C@0j)Vf)M#0Xb?-(sF@q8X%7ORr|llJF80)3Oz4;x$IMovF8be20BtT%@Vhaqd; zgEr(TMG-XIVQPAeL>IIOwbf@)^;#5VS1)TMZk45c}($%btZ)=qvymX*d#r z(e}w-r0uG=#;nI`I-xS0G6}QKgSTK_)qqF(!kko|4cs8N%;|yl;yy0D$jy-lL$X;~ zrp@YXL*?{iJ?-R8y$_t`PfXlmhTaj2p<@kkt4Q7}nx#Gw(1y+?j3VBnSvG@QPL?`L ztsCCfaBR-cHIB@(O2|1!kZ6FrJIfgyxmjh)6;~cYT5LX?>(Sl~4O98L?*=G-*<_1I>L~V~W|$&PnXX5=C|v8ie|H7X zKZ1@i_1w= ze%Goc_9d-sPW@z01={yRUyqXN7Ro)GyuL%NE@zqetM>(&V;mV)x*~@!2X0n~RR)c) z&Q6i*uN+Db#3-&CZEP!s9q6wf0VXWfEiY*t(46kpFH}|m(Dptg*r3#0cSfYUXn=7j z<=lQ`$n|2hh1tszz4ZK<;g2&P;J#2n@TboK7~wzrKP&#_P3$)g{$T~}=S0J-!xhUe z^bpdB5fTv3m{*i9o1E6PgH{KmK(ESumiJ@m$2kRpC;sj97=hbzx7@_C@9|m=Ypj{X zBQ`$XR;nO+qY%EOtw$_BK|S?Xw{l*mI90+M2cQFoH9Cj!*R+CM>4m;e^7cHMfhei60s z6XbT+jjgr1AA!ge*soriE{>CSjHOM}p|gn3WH;feb?B3(0dd>Uq1U_>$`TCBta{6NVm$c^blipCJ37t@?6 z%CdQQ%UM(25OXH3*>1P>G1E%-TV{-@QEt8Q(`dea;gYpbLCt-KHqn*qskPF#6fLyJ zdb=LHV($3cN8My!EVr;I2hlZO5ylKedv1i|R42VYT0Y}+<*HfCs4c6TVocfdaFM3P zZ~5L)VJ8NC*mr9)VVP-Fo4!WY{1XIY_f)?XnDXt-(oxF$t{YSxG<1PiJ=__Rv&7d= zb{~s#LDERuVp9x1e5-IQGwq_MVY$Z6o&zTK(Uum!YrLw5cW;Ey?}_t`RIf0DlYs#N z2e{};rfNS$nd z3VGW{JosSQV4fV=kFOFnRvRU*SLW-S-Tp0?4PkYhP7gpTbe5usR)kkW3mk>X2fZ^k{~xJ*DKIqX%z0KruToUKF12yrVmP`57l3X;z1B1pi`akgW(SP9Sd_O_u?9EKT1oR0Ez>DR! zt&Ly=YCk~0)eIs)O1}#;+x}-;^|$Rm_ub6{ZnTeqn!>0(JuUzT{Kt0OtNOH2$=3QB zyEqvXQ9-13loD*?S3Ai~NxTc&6WRUeik^hLeu?H!Y7*C-RNKV7RcBUa&oX{#EZ9Sh z=e+=|)F05AdHLJ6#t3AMJcQ$QRaIjPv6_BgEQB$upP!B7sv_nK#wLv^4q_T@E2R29 zjDOz9yI={nC8Vm?OX|d6gc3soq+=rM_zer(%BO$(#=m`g_yt)wEW<=A#&@yNTyUH8 z=`*uh&JCtm@O4Mt)WM-`^*zR@7YVSmZF-;nM?px!%#LEi8>iv`==Zt0tTcBR44nPJ z=wIE2xODA1hmea`I!W z<`xqo9au506;b&ZY8mM11mI0blWMQhar=%epx84}gxia4MPqpBQ4>CIFvWJlNawDt ziP=~t_DrZr1GV)U9%b6xd0=D`hc;p2)B++J@fA{R@~{@05Yrb(Ti@8F3e(6hb#g87 zho{$0s68XJz7uTyc-%ma?W?$CZos!!o>OzvbWRNN6JDqduW=bwYQC|sk4(a) zPdftNhRjf(PXblG0} z+W>d|pL5aeKc}bZsOjof(VJnPmc(yRr`&9-)_Jn$g0d!jd7H6njUJ6W=E8fJJnPkl zCEkC|bpPs0{u%VJ_mH?2v3nC4Tt}%WTR$rXDU!B5rq|mMHJc>856Xe^A^CZ>t=0Z( zzWl<^A*5D4RsG~n35HdhrioT=mu*CU`F`@OD4dX4sh%mTI$eXgbu2__Ditqm=_hEL z!#7`KEege2bT%Y+%198a0#*>b<4I{TIiyBpa_@oEA{hS4YeTd3!zqX6Ru`FjZ4Rc0 zJ%?R>wI$~_%lP6H<*x(b&JS>S`ov{`_<*pgwsg(iP!AAPpwjoHus$ENir${kg)hSw z^z;PF9iU>od$L$NW2}1#Dm3=5+ex=IsaFr`2CnO7TGxE;zTD-N*&9~aV;DU}Xr^ca!mTze-{Did4=1F3toj`= zmSAdj)wK^PunJq#(Xc&uJmv6eXGX*zz^E$}^}SUuvy0!GlEhF&88i4w(iQpvkYyRY z9Rar|f6Z@fh>BQVrXUDk)rZb>B z>GLUkst@5DCt3AfD?~d3;WS&*9-W-`_9gb|EcYdoYm1S=7B3!Fb!XG;JGRLR;`?E| z_Mh^SAppK@_IBTDK#0+=h?#A_d|4Uj9B>LYZ&9Dq` z5l<0}KwudQ-DYeCQnBv=4hs|ypany~r?Ja51%Kvn{->`fM8A`eigrH|XT!ImA&=g!%RIwO&^7c8Ta6|*Z9R8BFp#4i4PxoQFu_w$`!zTD>qEe zR1OKzx~PA^!8hO4gNFXtP+PI7A+t**)>0Df1@jc@4xCUYISsHTlAxseM_$72Z9stX z5u?7Zyk#P&RKZELC%A>Bo6J6WxL1IL>^V!v&IiFbxu@6XM01KQk-842`=S?l1FE|h#o^oc zlZw;N#sOgxdgWpR19wqEY%Z5)ui(I9VhC`DP!HPAzr6#H9VnV{Slw{pqFvmez3ddb z{GMaI0E1f2ID2``#_MP+Zxz}b!o@k_8DLEvRRBKxnt#_YitzmkMA!l4-*ZPdv?>gS zGocp1Q5~Tx?J|>ubrqnPPi?~DZv+Ctx88$@RfI+}002=7g3lJA^fCwU)`69#`>68t zo}R*#8sxQks1CjSbN_%o5_EETxPnpOlzAnmE2Y4ue=*aPYk{#pETTFhv{(gSa4lDt zs298h_k>*niG4OFAh8cD7RPdm+&;%tSkN`FhvfAdiK(oCE3-V`+z^nOwvj__gd{Ok z1N*n~2rf-J^Hw>7;@1vXXl=aH%gYm&Odb&NJAb+#wBfP1Ts<@G9rm5WER=EynXejCfad+uG!oJmb?j79iC>W91VQX6brHtyBU zl=5cQWr{M746Tx^K%!f%6laR#yGGYlK=<~%!F#6LX(st`BdQaYUOaKR(z$0fv)gme(e*AtuaT-}FZ7u0L5Qjf0z0(B691;Ho65LtuX+XzAGvu{A0p4qO; zrBlmwYlsGnDURIZzG{)K2A6!SH}@*I!*#k{~i7_fyWt?HY3(zUCp!`pQ`*imhgO{u^3%&hF23^(e>= zEFS*hK6@7Vgr=v(Iwb-qrTQ`stR$H=!78+ENP|@ww{v}9y7k&uPy8^)w?%E)bvY!) zNor0s2~lh5#YIm%F9hhe&moo^L=%g8EPd}}1yNGB?0IIB%|731y-vcW=toqLqLV_q zyd$x7`!eq3R@HnS9CjcGf6=2ehF^8|%9~mtn3Dc^?ZU?POw7LVUMQ{qL9&f9+?BnyOBD<7Nj{O6ekMup3H@NinR_ zXT5^bAGoQ>p^!3oX~u6iMC4$+mhluHsl+&UE0pmha9>xwFVJ?ZF{nF$h4--48Y~(u z$q4FkzdruHOdZSO$|e`Aof{Fqy4K>|EtVDs20Ta9Pxp0aIz?4Cq4`%8FH5Y9zwER@ zO$?#4P3hP7i#`>40l$2Rz{Q<6uo%fm-eeA4e_lBSAceF_UsK~geWH}9jiHV2y z4R#;>`^>{78?__fg&R!+nix$)MDDpt%{dR_4MI)AIf+HudToD%;&qIO3~gH>59y=~ zX}8(d@Ve|c@|_mY&lEGJ$v*>d@Y|{wQQA4jIddfCCtoLxXKf$H3U>~{XpzCZ%g=D* zqT(z3ydvdbAf3pL5yB8acu(M6;s@P4}O4O%I@vT@`@%h$)l zgg;-k8t-FMhbi8b%+pv8BPu`FcGR@MW{H`TlUeB~Kk zV@>cHw+Ct>_g89tvT!S1=Z>*3OjUelS*Zv6tT>YNl)RAMW{s(LhXwPU*hA6w5OTIY z2D=_Pr~dWj+}bG}b3L1lha)RaJ#Xv5OX5*COzAL?{IzllW77+Xbjz_WNF?8bgr`2} z+$_8K^9=pG^9vy+?0svDXo@~-IKrb)-SQYk$w!!$gt=zH+>=lkt*l}A+vO&wVJ#o} z=P_9plQ7cE7v=cKv3{NM}33Aoq`AzrwpD`9-$MIhUw^05qBcl-p!~}hYU9IPMDt8REuwSCi zq5sieM{@+jaZNm>#`|-()lRIRpg~1zSgBq|$+y?x#&~a3dv)vop2K-Qqdt_HIYP!x z;VY0UZfd3h7s4xd8>ZXUPFzycejPgBbU7dWgunA3;NGgZqq9pS&+rhiBnR^XkqH}u zFkuZ_`6ozzGHAFg@!Q}&TWv6z7NarEQuGSGWkYbag^@|<+~|Gt zSfZvxLaaV5Hdf9xbom~Tk+PHCjAOrpi34iIeTGN@Sx0~Ahuq2-C=v<7rJ;BtLCuo} zosR4>t5mxCVtA?^tTkVegw53b_nd0Ul^CqoHubqt&D3vM3h`$;-h5!wA1hYbgGqbL z`OZNretcetO0PwD+9M8cbe1ATZ>PQSf5lC$7XyHvK1c~T5j6yWRCJB+J*L*lr$TvSTkerV9v?y~mZ7;}r^pZvrE|&*?~TY>T)N0lS^fFeE~Dr3dBO4; z$b+@+`y*Yc%%jV@sV6S*8rIUk9Zv3VElJPB!V=)g{EI{W_x-B+5b*&9;~v+$JzJe* zF%Sj*c*u8V!0l`}}fDkQX zH!ew%Zgvd5Lk9{$2^9gFHGxl37ZCQ7On{FxxBxP=CQz?3x}P{2g8F(49n{9~hpFQ0(mamS^K>*RjZLwSTZL(}l-Pg7qR=+6XCHPO2N^EP*l0dFCz7rcvil*U;FI zJn}6|Da^U(QH&X@a35Q(#MT1kaCz?s0ADNxG7YCp#W0Bhby0z;@sVTNAPf0t?lZe- zn#}DRvFM)SqQ{}%*^6l_pK7@b-1f7jR;Ih$VW3ol^nh^`IkJ{~Fk|OYPx!(41Z!b< zBBL^hFxWMzD&o~z2VOb4o{>!s6=LJ<`zNy1ujOc<5dg z(kJT~cX+vtxah$$Tw7NF(~Rzmv(}~iZQ!DxFw=6Ol%3css`>!L%yvmc=m)c47G7dY zWS-gt+VYrN120qTZ^vkX62r6Pt-CXZh{wURd&FRY-obD{+i>vLcrwvG^KC&6Pv_~X zfs|Bdrkd~p&b`8i;g|U@fRkr)xWn;Uon5C4YH9R*4K?AF!h(_M%i_pmkh0E!lfD_e z3Mtar)&2HuKRi#*qoM}h{a|Y=y*zJeF1DgP-^T{)h9Rcu3%v*=e&2L7^Yr|?HKyJ3 zwn4%lnW+1U@nCu{bj0=@uE_|?MI}EQ|3F5AXx4@)Grb5R;nn@*gQYZAO{1N6`_!W4 z?HIE&(Zgkc^p37DkCKmVaSw@^Dp~nRn<@llf#DclZTUZ4$^ZN3kek<+a!4zKNpt(I z%;S6Nu7e!D>4dqg8T;DNLojy)Ah?KynWe{|3@pRyH`xe(GC2gc8L$}iQmMX7NBCX; z*<8#<_7huQdt9_O$b}tZX9u%mxOw*4v}%gM^Zr&ui#)0?I7oBs%#hl^@m} zCdoOc>Gl5k7cqrQlS%V%Xm0K)+kHxTb7ZO0lZ!aSf%nU}?MDX1#P`L{XCWjSb+tyN zwIw)GSmGZaX`mJAEC=%~SvP!CqvvZte5c|IdQpH|vY750k7T09+8{8a%twlnmU9Zr zaM3x3dmMHTuZJ99EUn+CzRA8$gC-EC=F~#DlSo}=Fyzy|j?+c3s$ZxFWG`!bq)b`NZ-gzBk+Exc$e(2-=HoNqq zwMQ-a0Kv(>-*O}YJr&h5@BlORq+;B>00U#HB;nVIQoA!90Riri{AkZ|Qqs6VR=@ox zZ;Z6Wa6h{3hb2EFb{|u&wL-2OIpIoRaSAr}94LK0DQFW6zPy~gxW2-Ty2EKoTa}umezBH*bO-s^0t}HRa~4pG~d)2<lrto9@f zs-`r{|9^P5m85Z16YF%KiV-Rex$bes=}XI`F5Q2A~S^FSo1w9qBvfU+=?M z-pXpU-~}^xKOrz~j1yZRAsY=&(uxFJ<5@Bi*BIn;U-kzjL5F8k-_t}2_Z{k~%6)qp zv-RX9r_(GU-~hpBigPea9{ODUSe9jxou*LK;T8&{RL{-<7hKlX(9AqQ)#tnva5@Em ztt`5no(NhMLVW|dSWxuWm>B#=F}?cgK~vDB6vS=o%#lVTP0$Ib{w~&@9=sF&vLls%$~F{a9?@1kJ40>y?qojNwbCOihRIz06Z|h zhPNy-8?WM^D@i~&6uf4cEihKoa=NO4b}I4DH$4`<0y>zt;LDfwoa?Gd#&d-i(BmJk zfnK6qky%aI#S@tT)g#ZjdbgEqnDjA3Tu6;Es3gm$zNc4>r6WvVK1QoWGOwaM7BIEb_n-JPmQe!sCCt z^^Gxv;#x~Qee25iz0!C@p~3EGj+Ic&$qwCg@$EuA|G3ST18cq$F^c_=!^ldC@H)Z# zTWz_}s)aX?>wN^)Lq+uGTY5d?<2fD=7j#}2vd~L7D5DtwvSDTH}NfWFrgOlUff3WCG`pa4uG!N0qEMOB=O@9l|-^gAKKBJNxVbf zJ=L;5$zd5N)M^Sx(Vd@DN zud_Tb!mkezVfTUTDCr>o*9GpEyP|xb%&#{-rJt!+qDBk`&q(|7^{t6C{fE1knrOL6 z`e_X60l0%NP)F0f_UYMv7qQd!=%#0k0f~-;NqXFCu6~BwMWb}<2-n>(AI=3=p%X)f z;!QnII$o53`p42$w{?`?0n_w`niSMWDuS6d6l&qU^h243-yxfMdX45$LwX-V?eEtK z_pFCwU7vtOduj}nM>Y%==bASvB|r2Kg^QU%z6KjL1>A>w1@`c0NOVIv!p{|7bA0kH z*witOr7JJlVBiwz1N{Wy2xk|#3gjiSxGnHdeE5cE=2(m~dE)4UE8wh6?@|{)Ua!fj z@=ZsOXB6$=vx68WzBEODJWa8m?Nu*B_{FHm=&O8Popo6_gkzC4k^UqD{oaf~2MF!u zKlRE1f()Qn9v~Bg$FUnrRK zviQGO)DsTG9$nAIc98wn_ZqJGOM@}O>Ic>1uta(1@O5q4%gdEh+u1MW6}fHlrV2M z6NWaK1fyJy4_NaOesPytSheorBzwVfUxqouh_Z=3J3Sf5oPiT7eN&N6GJExr0sm?` zLiCzLQ6=D<&@Ivwi?D~po5Cq(U*pV2V&{jv4TtC%JH@^scb7gYMnanzJ$-nqHm{=dERm3% z8G8mty9~yVp*~flDEe*tI*8c5&xSnU9{u3!-m&Q?rG%HRqvo=$xeqIm<(s1X0}s`! zi-~lf)tn!{3!$?`Iu&8KVEV!Yvs?lm|L&+e59+?@Uh`)c&ys)H)fgJ6%g4^cZj2KqeT}Z)T)Wh>$Q~ERMja-Fb1u{8DEk|vBV7DN_Wz)KZ>}rIv;gFsZh?_5pv*NAF?fo zHZsEfa^5X?)1fsR)5DQ9d3qE=!`-&0_Iz)(MYVlSss~rOY0PiOp_)yJ|Ec}vqx(6J zXjzrDPbqLj-Ne*73*h>Oi#jrbyJ1FoFX6uWr&}c8APehcz8!bC>EkDFvTGAwStdk| zH9kmqg;7fJU?jbxmQ7#~K1?2b^Mv;E$d=^>XLsK#zO)SLTudM7%o$aE(`CY`{OScn z5J3+l*Bwt}xn%wX@&KnZO~p{kz^B2}eVi$YLhl7GC*MgaB?d}Vo9Y<)t3iH2^?nE9 z6y8i0>WfHW!sz6wqxt5ciQJBkuPS6Z{iq*u9NnMb&r+QB_^{bqCce>S;v@{dFUJf; zzDIvl7?LyJYsXH`;QBF;HqpY}*7fRR+@-l6v&t81!P$qolbv>?G8S=ru?p{EorQ`( zAHSN_iHuf@z1oReQ1r1sx3Uetc^&(hQv-sUgas1AkI0`C-`Vd;vGEX2go=OY?LQAe zwV)~hyu@XsIYaUX+4{!ig=#J$EMiQ|&zQ-rM7D%?hndP|zUh5-*K?nY?xou86GE1H zP@;eoH}7jQTMBZvwozK|s_l@~gqFb%SR19DY>l8RgZXr>HCBS$7`<)C`wkR}+Qx<* z589QH3`(3a2Ed%Gcd0hSAzUU;yEQwerOeqKseE%zpk(>Rs(I7+r@8Ji8$8{$th_@@ z7^}ts;142@CSLn(}C84I1c`C)=sMH`g*H2q51``{+~Q>0uO z4a86xz`Z7SxHqOr7 z88xM*k1{5HhTpD45a-M&%Aq3-v#z_4jbNSBe!Sp#8O%O zYt-(<9Q=50p7Tu)Pt4^QdM=^djd|yw6_D3Wu=gEM2I$9nsdn2tUZ-Ci4$;%i7$>Fp z`$-lD@1gk}ILeQJMa9}GWq4Uk(g>0t@?pO_Urn!;ETtebh!Etp@xTXKy89X!8HeVe0CU%haZ-^xl!=Aq zhQB`CKmC*Yw>R{$te(~0j@A?kMIK>t$1eYsQuKQHx3q5)yFnFUk2<2T?7KM!1R-(XNcz^Zeff9O9~dfm z5)P?a9d!kW&Am6l-1jif+1vhsEZpPmnq7$VUe)P~uI}=J&L}tJz~vi@`VW&*;kF&o ziFs?mWdBs%;Z1T+EVZ{ecCV+LMXp0fr>lgf1r%A}QWV_Xbmg+0MU=S;$B_@Vl832C zo2pX>tyh40FfdgguoF%7tJqAHIH_N5Pe?hh+uMj=_e{Lr1g2jdz-9G=I2yuFRuex<_| z`qtB7Jwk1wXJMZw2Ox)YI1#+XiPTVt8f+!pH#JW#FSM}skBjr48p9CJU9z6_Xn334 z{Z3Ge>g7sfqyyhgYMSu1>CArmtyd=EF{#5vBcfV!3n86IeKz257h5bQ%$Oas&akoH zgZot~1N}Lu=?WUkYxsi%_}K6MzOWBn*1ww-{i=EfqEW!(_w-j`jRv;5cGx-Ju*n4+{V(%La+x8`avoYs@5ddU{z4 zHC>?RLmq@zzV;#*hjtm5D>f+z{|oTN6!g}B`nPR~k)0CnEWX*>RAO=`DR z1<4a+MPZb07^qwR%YFji^Lpt9@#HfD%23hO@{ciMP6e=%X2zD~EKiI*ALYovJvDli zy*vnzj6(;g=qKh)Ow%AJJ&fqW3_gWkL>;%;k(Wgnn&o8q=MHHSv$Y;cRo8%jI$xwy z>Y5+txQ^4C_s^4e_xkyRl@3XU@X##u4_`CEvo`J2vnwyw!<9pJJ(!VJa#Vca`X5M9N-v|d6rWt2g5x_RT#VhAv#T>H9l3*dc zD%mg0fYPfAn#!u&oH_l@WXVvEEK@7=49!?9bGiZ@j8o088<8{FiRHWrS^cq2t}>MB zGP&q91F(u-9-NWvmB2ESMV{(|6DvW2Z0G7DQsQ;p`u{~K<3CpS&JVj&gEp{zJU+Y) z17_UWj-Q~%|6hWe8YzdDm(&MQo7UC8mm%sk0hA%|67|p@HbC(JGI^OzIPDVI$@6QA zYD%A-kH9!Rlt-qclSe062Sat{Jq>Ip5GW-+0tC9d9`ubLxhX*rt&=}Nkc^yp1;&-~ z?pUd4(^&U`Hq(5F{g@zv;<>H*eFB#r;1qN;R=S=LqG`&e7qU%+y2tI&A(nzC4c@kxW zB{EV2_dJWhuLEZsZh#)FYgDnlw#b6(eXysUCqd&>Amv*uf2zf>kxJpB`!p^TO~ixk zv*?n)CSLR#nxR`n)o$zM6_B$nS-&EyV8txH%NwNrv1oB3fUQH6Vq15-#JD?*<=D_< z`A#fIo>lu?{cgwO6BIB?nOV7fxN<9F@upHMMf&Kp_DIPFrFcx%yislZSt%?16VPBA zmdY}v=!{_0+QQAcd&!ItPrHrSxWNKFyVesD(05Fs{(edoR!1jo!|PKmQCRu3Cji?1 z*avVfe{3M3rn+eeWW=j$5vW3d>!$up(Hf;LCN}FPE+-r_#Zc6{bg%y~f%?JIy^v0t zc9XhT^hJ*^OvedT5}cF#X3djJoUb))6;NaOf|Lc!|go>1YP}n^^*1E^QH#VvU(otB5UqaoWAFwpLz_vZ|_&fD$d^8NW><2ndEqs>tPGauGm<@8C(Pp`N&_EkM@VNZ1E@lk{I*rZlJAen?iT z@7Y6kN?T%+SkOsUg4lA}(MLLa@(dYBF4Q@{q&Rxhwm-{{R4!wpQtGK|*1VGNz;lAv z-1D|>lJr};6=3KavF7P$*+c6BHhXZzn{OP+Lw-XLnT|o+d|tRAnFq zioX9H*GvD0c5*_omM=qDr0JqWud@^en)0Oxsxxlgm&DC=<&I^1fienx{~t^@U!mWn zkCFWZ3i4!k=`b|0ih1vepsN275f-al%2XZq)dAqvk&_1i9oPU0Y+V3Atp$Wa=@Gz< zfI$qsbq`$iM#jCCh4qgDD$zed6tD&!Nh(OrEpdeXM%}aki$YcS8VO}cyZBOwMEbhH zW}FGp=aOaJj*|vC6T3kE2zsBZn^+|W;|hQS8}nCQ7F5Ha=b6Jx`GppXyi6DcV=|X_ z&9q)4k_bnrh>uGWY1FWzSp3-?GYZ{uhhnq3n(Gu7hhGf(+yfBQy(#s}W(m{;=%!S& z%0H&954jVq0OG3t7vhS-c0&fe#@>PcngwN?mc@@Gib}ilJ58V*y-EKUd2bySRr{}t z4+5fqAP7o#Nq55tNC`-HcX#I?2+Bxzhja{G0#ec`-CY9GUE^>0*7p5=-@VU1*Y!Jp z>~sE@i^cp(lzg#p0u`D3oxUa z2WvDb9OI>ZY^cI2fxazbXX7>EH{roQElKntX4F!R6;-*>VShR5v(?{T&!`@{9t1c{ z2)I)tqF+h!8GsJvlB;NaUeCcI-*U`q>5VJzF9!Jw3vaeBN3|`-zLgd3a9Fy*IG0PT z4e(P)+f(kLn->~+-MH+0%e7?`*mVm2U`~_vQB$)|BpOeZkeDOf>JCSh$K6TkUm5^( z_6xmzlE>y|<(=>iLRJF=9F7{FIk?x3RU2Tqvv?uq4nd(?ot+DvVO<}&%mVwP#S zc$=bxX5uo!j-2_Nj8ntFWaa!rLv4!%;TMEd<<#$iD5n+EDg~eejQk6(2}&mf43K7K z6m>|K>PX-{q4$LdJ%grb&%%^8dpkIA2*=mEX-PW-NF9eKOSG&Q9N;et3>pxb(9#`u z@-N@jpW%0c^!`?g2?Pk=@+K*hBr=SR9iJ{Gm9pqzV`ic~S$Ek22Z2mrc{##eCayQ^ zi+yk{ZQdw^6V}c;5}WA54l&DoC~^1(_G@A1jw=edLo}9Ao(jV9!Qz=kOlApwT07ZE+#Le zwEalx>bJh>`x=;wuk*N-AOsUpFV(dbK&3(Ni4l;TFSkyMMj$<%e^vyZ-BL8T-`-l2 zUh)B@%(ZGrJ3~HXxC^lMfhjF;0c{rr6s*-@1m=p5gmS_=N9L9)n+Hnu@vI12^h2$1 zRqZce)bE_nvl|i=n$oxV29)rWkCih9rZSD7pyE785B)H_9_WRnpHQgPzOj}vIA%)e z7nfV~Mqf4tJLUe}!~%*%L!B#0WJ#Oh$JDXB9@E-u&UUmeEj$N=NTIi%{QZAEE(!qHF~MzY`Qq-2erGB$|? z5pC_zpBLxr$rR4+JQWt}MOP9vPV2izO0bc8bn~TekyC5e{V8I{Xz;7JCbj}x>k&V2b@R-51&L%#>N4|Q%2CzEZiLm&H=t<& zg~5C!rC;b3!x0rbZ&R{l$huJgALgQhWZ&AfbI+iamWJMRn3|MaW52VL*;|3f^|RUN zFV?cQlP5oh$0HI-jM;rZU}0t!%+WmG3p2Bv#!8K$^zWYW0!V&&x7B&PUT5dhdpf~> zfKn@86dxrbuH~m=gJ+%OzjEd zN}@TAleUqz&0uCkC!-X6)7o1Asou{zEG@P!8}`nde|b3Xnegl*EgB{IUNj%ZGml7w zdIJNaAST4vQ`>6WQoDZTx0mNXK(7h?21WN`u!M2;_` z85IRX9g5IMGfUC{hL%@CA2Mc@A;XoBB_L7*=m&FoZf|Js?!dQlriJx4_xR#@H)rva zU-p$bw^HWv_etkgOViGLu9TRdXG`a$T3*BPmPV<3XDoB`+WzWX{^lBTne2X^vvjgY z`rAR2^FnZ{m>tw(lKIxb<|Lh)lhk4OVMT@#9%BGcy>NJM zi#8^+AX_srALlWbLjBH}J-~a)O14%qP_>E*h>a^>a_?;h4VY#PBUIWovNAQ87~RTu zCogv;cfy{cu_5DPBr6n8&qIuykG_o>A=sOhqSSJ1*b(A1HVY7O)3r*v8cFD9#6|(k zQ-xfFGkeT7*mP?a`?SY7X2x;LQE$S%yp9euuL$P9kf79QtJFNJ`-p_Z2$|)n?*h$2 zM)~j%1H1K=wZMlFWigCm-#_xvguAH*b&&`)KIlj_HacYGy&ko=t{J@he)O910V1cN zkqIw`dN5VUeO7m7(C}w*@1mWjPC8vAiw0!`#oadRU7DYi-t4;cEEYA3|;Xq{8h% z0VX@?ia6;zm_p4YODXf7aTEaTFxFwKj*45SexrL6kaZ>5H^axfE5n^%tR?PB$rU!> z(2t`%$@2lJmN0Cv5npdD_1cNK)%pqu98OMv@X>z{XyP4r7TRmbZkpWBdnx+ysdBKv zXZH-P+@~$L-64=Fiun1DId6b~Y!M%)4DUOu{1i(0mLvewi~#BgrH4Q^tuuQ7P331g z4S0#U+a%N~&-Q3gja1vH7a$p|7D|8Arhic@I}3>%=s(w3(}`wvLX8@mt){{-b|j?l zQQ0%o@%J_{F+ahLj$fn%T_xwm%NsS=1d?76eMO4g#@22%3{-Cp7wU{fe!JI8^(Jwc z=pv6NxO#^Ccq3x4Lr+T(nw!l>)sX7YQR^gxl1pBDgcXWB!C8LSJ7z+841||3y4s^> z34ukHe&!b~RVLjVKuSUjlx#~TTi0h_>ffXg;h#Z;e+opw;X4gm>L;?i03WPXz*KmmsYY7nhjdeO45>5;8}?fw~&^QwHyK9BQD%Q zw`gWi%a#JiPp(iud)rbST`5LwQiaYv>{@;;Li#!uG!d-Lhd3SdV#cg);igdN73m5% zYhPe8DDIZ${hT{hVMi427xD|zsjNMfJwprQ;HL&d;kp5-dq~Ellkrn&evs=kAWsO; z==|i%zQ?y2K8up9Hb?N>jCTlBVCPDxE#ZB?!Gg;kts@x7ecg5s1kYSPm&) z11NGmwWVvKv%++1`lpDUKr-V`EDr&TV#_O+Xo^QeZ7S}xxR2xc)Y%%!&rmoK^j`tD z;+{Obkrw_zYrNz$3mkj~zW$zZ&GZk%Vt?fh{((dH*KO#liP&u9u@oVA$SmPf_^reF zv?pA|3nlK6csZ7F&Z(Uo9ZMIZkr1sR`9~UE4>ZrjG7hZjm~PiI(V{JrU8eM{;=3mH z!CS?mx!1;}95VKK+viZV*}hp^vH;2ub+R=f6d%kURlHj^V?w)U1cl%|tErcMl}cs7 zC93^sVal`x{IFiqs2Cgs;=84HK72x-J6C6>d)bbSQhL$8`YyCOunI)-7OPLWU3fkE zUOU#!X|^cKX@f@^d#z5o27ZUq!8Rjq?Ctt2fz4BI6TWJ29~`9FGrXZ>nSoLL1B7nr z?%eI^$<TgU zh(6ff?uN-wmq&kPcsISG?Svj@z&2LjNnKOaNt!@%jCSAMbuQHjgpytjlJw?I?{0N$?~{;6SFuR+450(2_>6!16&1U%>vwf>>+``-V?cmMNK$v1CqmM$MD z{2e6=LyKs+RF!n1t++p{TU{Mj=%1K7CnJtv$URaU56H-ur&v1B0WyZm&g?P-!~E6n zA0%Be!AA<13Gi1enl4*y%p;vRdTu3gC*e4LxJ1FtUpJ_|EwkBrDR6}(Zp||OY+T13 zH%gAC%1m6)xu+7x*M@@RE0P@v(47rj0cL1e@1)Q!f;y`dF$2(xX4qja0wV3SLp)qOgi>7q=%fO$kIL6&o(p8rCYv{I|Hg5-9Hn=fBU3>lwtaA2x^gZ317jS=>-9oj(2qoKa&S6Z;%ybWknr?XXi?R{a(fDMI{A zNF1c|SIQxUDg?)tD!h>3-oStZ4n|ILz>-2`qpG!azh@wJk#U?h6?!DA?{5Wr?Hd7a zLuametk%~^Wn^d>vN2Gng*krFZO126-B_#+FH_Ao&X!4H5x8jROOo?49wy2_tnmZy zDU8t_pNzQ+nlC2Yyl$1l0o&D{m?@0VCO4*%1W9cv>j5H1)X|)cVid{88 z?&A0sFjrtLb2uV^6YZR^72!I{*U6~fo`1RIwkUflBijq?4t+?g>?UhV+H93smX+Bw$iZU zitM%W-9cWlU@1`bfqZv95x4PnpWV{A(8(6kbam6>BY8uIPwdY4*lg(@7k1CO8Ty{1 z-*(R*oo)Kl{*Go<{wudi|2ZvHO|kN2{-!`u;zr_i%woxZ8}RsVz(|ej;A~gxf)dlw z#W7T$877lBjc5_%IR6MDr^V)p^4IinzXNBS1+XGw_OKre2`O-oT|z-Qv+%bf_ zY5JX7Dgq@{XwF*R13uCqHF)RPZSebU%6$j8@i3(np2GttcXV%(tx12%fK9lN$Q}#9 ztn3R@btt#&F$!5lx8K&aDjt_60F~C$!6KlTWpA)04-FQK3GmSK7}opLt+~%wEyV3% z+VIKR)5NLZcu6Wxxvh;F4m`bEZjG~03(D8oCn4Z4|Kfxy^SdgPpU!NsiVn2Qa+H zwv3b-;sMS7RA0zyB&;dMO7+_T3h{aR+%vDbH>!;ziQ?uimycdNGI^}aXqgtC8?ePo z7IB2D#g6%Y4YdA2a(K*Z?RwnEI!!|Ih7wuF);iUvNZ>8X0jXbxj#0JEcf-m@8_yZH zSSX3AGL*c(A{YHHJhWfEwSRj5e+7lC-9|Vzfiy18Q9K#?1jDa_43p6h@<1{K^+f(( zILFF!N<)Y1v>?Odq!)*fFj8B<#mo4~VggiNTh7tsug*WfFL8VW#^AodE!vE%&zDd| z=i4v__sjfAa1v2F`{%#v-yrAT-gE+1168=q5-43BL6+`?JKk_B+}Hv{D!{Vm8*!BT z=X(gU-aqf}&8_&`K5YQ;3d-fk`JDXKO&}bO`uQIw!|ZTwlYPD`e|7zH58(x1RImcT zv7+wR2CUD*BftbA%7Ne3q<_(xKSVN^l%Q1;mzy)iuG>~gH!E?s{O!J+=jkk(-Y!&l zFwZl?u-0rmKj9+23O_Ge;%$&X3R5%>i|UX_nd(2yHG%hvI2qo6>H#t^g6l=x1;*O__n*3?l|Y-7+Vag+ z=1!hS53uOPoFW#M4DWrzBsCguA$$&Q z_vcs(IC8lp_Z3hKU!7I6*rcJR25sWHlp3C{VFqva$sgvz7Xchee|#>GC{Tg~fg~A|L!azm1JrblJ;qqr zN6SY6FPQngh|DLe!Xwys zroB{8nZ7moB&TI9a7Vr=o|Y|Umuu2$gBjJ3>J0^*76Kl)<=Ew);tV5JU+S85#dOD* zqw!bND?VM(hGs{kV`NTNzD%HARK>{ZE2<+iSOY2msCV>n|Dn5ZW~MPYE7f6aCG{$f z7@>`iB#nW_*I0JcbsHnQU{*7PN!jpIn(;!g&6*=VK#mOh_N}DlQrd;|`q6gFB~Heg z5!KK;^dI+i-U2HhI3pE3gz^tecuLOYdIA< zkOPXR?plvWlY1T$WM4rWYAqg(brPV z`G&3P01K35zSVU9KDIP|Xt@!0g`U*40%FtOj!yUYDn_x201CewIhN=HQ&SDm!6e=#uUcqU z*$corGUyPHG zHhTKyFkv~;TT^0;l~gaq$+pogXK}}2m=)V%bHe#o^&1hU=Eae`<&u>1HA45TjUl#S z*~y84lkH@hT%NhG_1bUyB|C2--y$*Cg1k?O2-HW{YHPW^l`3r>12Ba85hhq(@+Jpj zuS3|)R0g4wh~QTA3zGIC=FcS(@`>M%AL){@ex&iKmFog1B=p#&1YL`2YvFa}4f@x! zTejj(A*({7boLw8B8(q=&pm8SW2sV$B0p4Uu=UcGA%50}YJaeQBKD;5`{x=wOS-|K=JC2jzxPxcn-cUJx|D7~w9=7f4PWL%z}YV=qiDIFq+a6}2@YR-*&CxvEzQOW5CnOnE^;#TPOkylyhqOiy1%=0xTt~7Vz0h z_$d%;KBE1pl1+f4205QdxX1@q8cXnHGPt&+TKG)TJq<>K6$o*q9XQzZZi<^Flnw7ytK6 zx4dnURhaQE!0xm8EiLtRN4Rm7eb|dKmN~9uPW^Q#!ZVyHh-T0glOvKs?v#93Nfp<0 z)s4y?ZefBqY5iOJw5)Q^wR|l({f@d}$1TeXWl5V!w%0+}>`_&G_>tvI)h+^FMj6@= z{mD0X5Pi>u5e+-cut(!XQ z9&y<=aeGAFAt96T+>t^cXl4xmW~Q4AVOMnO`lMV4;~2UIsXG&Vl|n=A8fC-G-CZuZ ziBN^Vkm}yOrloJwFqxoO&2|^h;Gk;HWH${zbR(tTBEAlvKMC?>xr1nh&rW}%DxJ ziWVslf%w-aB$!|KKw}it%@)P+OEs)`ASd&1(R41tmaFd&a&2ENNuDV(mziv?!AGLI zaBtEc<(6vZmaU50AeQ1Di1wS2P3Tthf)iu|_=Z<+9>~urU!e-UeRozsc&hen&JMg) z_;Z5}|7H}wI@;f7%PTXi_Gx*hQkigy(2;>y! zb1d}y2yk0Q1Y4Hwp0}^+ANa+3(~wLMaH=8*W-M|M5AM!&g-hHG6$W-ILv=!P6**o* za|?Fdl7-W!>PmO-u@@e%dg4{Fsv;;nrHZ}}I#4aSmC0Gku71W68@3Te6(F^Mi$UmA z8IVKLVLtnDGq?sf#&cDUy^lfN{Zqo8;#CDTEOiP)IU=#dY5-+`kIc1Lu4slP+ty&r zw&7D)E|f+Bsi4cb8zuc6O5isKPvrhsHKIkPQG@FGhR7w)r(@Mm__wDXRm7TxwEKPq zN9^B>M|osRrKrOPWI`Sd9pM?at(HI)J!5$&#`w0Xr+^3B>tyn$9uvT3xo!p6kw3InODp@)D&7I@L2<_6 zzG2GsKx(@fFa>|4#=JnK?UII6xlY*|s^7pQXKGV$3ABhm%0>+fkCXu7rl^25_-7y` z_!WSU|Lj`Lrzy02noE+tzquTEu!&W z>%HbRXz-eRQ%uMCbpUmvwxrErx#a^Vjlfh}%JPGylK~Qv@q>+KTlMeIDegU6ocI&A zr$^_gLH9k^qvvmwzHz8{#K>6O4)YrXi4|H~N*qdoO4TPVp?rPOuxjKj7K(I#e(7n8n1!XP<2q<{vVBP3rh~q}g<)&te~c zpREqO=ZAwZqPx^-%9Z295dSHmS1!}RL0<55d30&#>8xqW!lLv>>)ZRbxecipAlkxG z#an7$>Y&fnqJ4cDN$v~Ujn87=x-L3pZ}wxXpKaw@4ra{{ukdo#gpWR4W7{w?-ncD& zNEvz(db;Cvk@-kERvKMk3Q!X zjxJOi)>MmDqZpFOwlLu+ zCs$WWz6hc*@`O|OPIvMrz-8&K0@CrGEvLq+MY+T^^W>8ZiT9qlBV6|wGn3L%jD0(h}H~ zQRBmSYU4V-Zpu8*Von8Q!@TJalqQU@&ca=k*hc=X{WW6Gk3zyjXp+^zlX$RoBu+;% zRX#jH)GBe1O4V3ab-*k~(&CI@{bu6xNS3@8#Qr3go9Q;TXb0ToPuU+jZ-gEoA~e?@ zOqKu?o?D|Xb0v4#^3@59I#-d!rtd-Nk~#>(HQaNr0w%9zYRt_oI;8Ru3`K6~KzO7X zBI*VI))fItRh2FwufNgTbUZJ3%M!qg=>D4jwkxNx*1ABjrapOoOJJqzU>r;3ei$zx zZnOwoXh|epbAic)snz2>vMV(H2e1ohFhiux+-U6=YO1c5NMJ1b_PN)wQJHv@#Fw1KLU(AJ$ZSIu8qua6gW#Y`=kCcbF{78_N6fbpqNWlB@Ao2xP>PppEMb3l`q`Eq#k?aQjh|{nl)x@>b4}xh`SICAMV+wPmZp{X{dNL&+0+g)Rm9 zy;IuyGD22HnmJkXtsfW<=@d-wH5{5j*|Y>X5f z5URhB6Y^^x0k>rCiabdw#yZ(Sq)`EUjQx*d0k8QHqowli{PYiBhH1L?Z%*7z1J!j3g`A}%cCzsyO#&ru1 z5T)MO_j&HiwXV)4p8o~=!HE%ZC`-)(G^Q$l;K3UH-e|3>?V~d}r9QVvNpv=;621eN2o|^HJ0KoYZif(vqpaI2K)2-QuwM8asgZXU$5QXgqK)zAHRPmVXZTD7#m|=ZgZxFcmQV}8!#?yaY z?+~mi-o0ZQU)No@FMo#eJjJom?b*gw#(~`$v}I!n@aYEY;D|sy zau$65R&Y;31%yTd)Z@JTpIV~{e0aZ4QyrkWb`#xXnB;vZ)sx#$QQaJ7+*A{=g0s#z z@(y%;qCD~fOWf8Tv8ofvvC1Dm3PgqAkNMT5AbX6FLS5rKEJ_#M<|#EoZ1k&iev@>e z9Uviv?iN47X-nKBHIg46q;RkBZsZ#;k+w8z4ZFIdsfls|vuKps z>L_mS@_XK1;_DCjoeEU(909P}Patb8E4unx?~;1Y=+j0XH*~36tJp&l7S^f68w?=G%)GW@*Xoc{ID=>Y) z8}})@RJzOCh5Kc|ujCI4T@_!2hPA1>vRqz#05DD`C7)PWuxSllu2iXf3gNhgK)$@Y z`e%!O8mjbnVRhnOAL(2jYkrn#n4R$8^ZEcq)-DCAp7qe;N7Kro0UV)68kLv&%H`uE zx}0rZfPki$rz6D0IJU9;ZuudWvOj2+8w1(J_Cfu4t~7~3A-V}tT%<|Du&5BS%v}cN z#XjUW*_uz^TgteMb2%dGzcz`u=W2*B$K`cFP15o&{T{crvw1)*vZMe0XPmH)HC&Dd!KXiz`jI5hgtVV#Ht z%PT+qb)K@b`JXffzid#@)yi#h>?KM-csqh&M;we+AowIa*q`%H_)@^d9@r@3dy3y! z`IUErT{mtp7h$6e-zJMU<78=`wRgn>qfl1Xk+9F6yXhES(4}O&QgRFPFzT=_d}6Wt zB+KIp+vjTMgZ9X2O$u!N5>fPp!Z`@x?f&e{>*FQ4P?_SCDy#Rw(za?ucD)NttP9~U z2>H4{-&@^Z?OIbLs1n)e*|EyD7LK)Zd(#N@uuWR*2t^U`NkN}13u5v3Vs6)b-YiBT`tL6EJYX6<#@NRzjA zBkxL-5qlufqER^#2F6$K3&dQtzz(qGDAhP@5B;k+#`z3gug^Udb3kS>CTa}GxOx)0 zB;|zN_Cy_pwGye( zv-rSopLlP--Ro4Icy}vZ*0Q@Oe}^>D1T8Fv^!x{zs5C+GtOT(bb6Xq!o>WDS!TS*v zFS<@PnmP1WxM_Xp^x=@}@pQ*|tdTY2udGCHN+>87_Lto9Z{+e*eQ z!*}-Vg|AQ8EW>@KSDU(i-VdoQ3^jj%+-WB6Hn9l%NmHJrJC0>hoJR?DcIM>myo^>! z*XXCP#Zx0QFuC?hewwKr?Xf~f74^7hPT3LBare!R2RKfOW3l3Fn(|Y_NLDhJi}hq5 z065C`EW9bL9?~9Ys6r`Qj3>XH_iNDt(6`wE7Nz8xhEckN+0T2psQ)9U^J{+Rf8+iC zM3etSwPySWsP?-n6F-{tz|*nTqxpGG@Gb!j60YQs;77JMlNDScXH&6v`Ep~%@+|1a z=SwQS)6j7q^T?~8m>Z=UTLE)Ye8u_(<+jy4Y#yf2xr zc!q7ouAKv=5OC(l?yL$x=XM?w6zedgQ`m zd0o8EIh+$ut)Jbv>D+zz{_aMf_lEoR0AyHh`Ugn;V5*j*)8Y=eS%#~Zl7T9Rif_Rd z*fasG`g4xw&fme-7~jk?X-xcI9CfoKeUSqyUN?zEQ*T zZn6N({h$sUX3-SE83|u~iFy-a)UrTXaZxnOa_i9xbep(?ulaUA#%hJt{nYu_`bgpzKEt`8L-Wf4|T_ z+4%vw0P09#EHkAMw+$_Kr$9}f;XBdMzFK5OO=Km|Xp6tyDP5rB@!|W?!RTqZ;CL6; zb4)%UHqYQRFo;4#KV|nuIx+0vuthcdE)RM+B=Lr z*J`(%Jm%%am7aL7L(aG|A@jwYt&{5v|&19dnrqG5xNA zpKga3{Sn2MLV|v?%rrB_09HfSeh}qV>Z3-DGm!H*K*fPeSirM z)vEdR1HhW}dxIAuHI#3~!z|1MDo+1xjlT6z1f`$^aw*mX6z4@Zfl`=18{~+q4q#@1 zv=gsHTt5T2&=EfTtQW!`AD~0Ne#(I?qwC+w{Ul50@Zk6&kM_~ST}sWAjI_MF4RAQE zV@8D0ziD|qf>18jIvFc&NM2z;v`&lIprG~}#-{}5Nw&7wok(sx3Y-@t9=Bd^Q=yWex6TqH6?&OifzYCBro`HCLXFOZSh$J3 zRZ);O9xYy5&+y~a#Xa#6O}qH@orFPV?oak~2YSLv z+y)rncf{K*hY{MjCGm$k^R3aX<L?kd91Pv=Hf74bZPJUqikzVfseT?e|9c7|J3-= zGc353JK|1T(;gHSqL(JeKyq`Yz<;(ug!qKp*K^RFU!u^n*jmfyqCvGQjb*x2GJyjz zBOOD6@3uAb(M`PC0#=v_p`XJ#GU5_f+7q4aJTST74M!w}G@{K9kR#y5HOnu1bZR!g z$<@qKLs*!Yq9ydl>pm-Bg00uR{X$M++yg5o+5@e}oNd1#h_7>4Y^Q#6!6Md$n!X&^ zL-}?5EFsr;?>Z0VwpRY`X-(l@8LI!bEAodMgL{CzFU4jm_;|41XH3*o#~ly7>1MM^ zyey>7xp^6c)g z#>AChsgbdsvks9P@TRO9TbCBuid=MTy#*7%vSximK1hCoPc_y(4Olo%(Epr3DDO&{ zQCOz%H*e(YJq@e`l!M1Pkj83=4&0UcfUPV0APJ{z+4GJ=7OUOX*b;=G00>m^?xs&j za4?-<88tTj5eDGCA>Sm!aEbTG8<~GIzYf-UlO~e6NWo&%@3adr8i}EAOn1gU@K`+ldzdI{DgEjm`LK zj7lE+``t>b0smtQgh8aJfw7rt$Dvj}5PZjR$2)M2GCj@eEIl(piIX|(Q6GAf{1i#% z1<7h=T`1Xma>gifg$`p!TH3?aq-VFGY~EVn|5sUBQM)E2>=N$UZU=29CGxObFF zORlnZ_}upsDyHq=zRvAReIk|6SHBeP9@Mvd)R%e^9^}{3?&c`LP_t9wc{HXR(J*z! zM6t5BKZ;KQ?L?D(y~_OR6XAPQ)Y^7-T+ePqL05%}=m+y};uT&C$LU>2jGf`xlQ-64 zcY8jDx-$B?;}OV9Z;yI&;_-NX+D{omDy4(c(RK>(UQ`7883|? zxZL)*M5Yn_p>00y?0hRTjHZtHC`2)`frx$Gm~ydb-a^ZEcA!ezd`M~p+W7n)yC!#} z#Ar_RgSOiuf(Z_d8e2J$*Tl~Q-#|UKmAc-c78gRgtADffTDa;;KS4M^sM;Er|!`I0GVk(hQsRau7NDguiLdg z`v3Pg=IZkI66-SVO~kHaVFzGts9F45?c`_65PFy>;Yg{buGXAqPwh#^fDWDLAQsX^ zch3Ss@zZ4YIJ!@tVul;q?pE*~ruPY8PK_tG{F3fd;s9ua%2gGkJC+etVKoeB1HSR+ zvp%Vq^s07_sSZH1#RTqaIqlaW*_vEvDwZChoPB5~;e1=^&rK#cFYTK9neK{!(mPF( z*!Ag<1;U7iR+}@^fZGw(@efc*l*)Zb;f__>-=ylm7J(agrx130px&(*S~nIo{Mk&J zLT*);Uur>@pliMOc@L!zQQ!*#_KyvFuING!21O~Q60kmIo+?7qeka>*xda5%f4d_8 zr`WbH4!MTXobMU?RIoF9nFP>x;vmG3Byo*qjlZfSL$Hn9;N9;gWjo*A(<)+p{;${N zIgi49BCYT&>iMr6U(lDpG4@P39~x0YWg4wboR7mfzFU&2H>dZqFl8O@ZNyl`*LtRN zfz~T2O*Vpgx5v-c0CL1hw6f~5^y8C2CLohNtechi=2A&G#p=A*PVjOyH2Nc92qm9j zYMg<*-l@yI)Mpp7f$vM~Y>tRt9lt)`7ppS&PifP!VQ8ag$V2y{l$8?#_QzbO#VJbjKUbA2kzj|U$_C~4G zgIoGsy}=bJ6qi1?Hs&}y^?GFLdY|}VPJQ&g?)^=%r!!^vYgi{Wa@EsFTQU2r;G|i< zxCnP!WEec0Y0Rp(K=AE-DwDavXcUq3CU>d}7Y1JrxyWuK)E36e?UC{)$j1%*oN?Tg6)3^c>glF zM0Nir)apzk1Yj2Yz}J`h>l0(0@Ivqc4ru2eIt$obz*lIO3GjAlpd~;4tVW}O^fu^L z2B;ZQ{Q!;1c+LLfGyL;8{!d?(HCOr4al_!+$kZR=QC=;0hG)C^WusMWuJ>>%RU zNooxw#4-vX2Nkcr`IMADZ!bpc*T1@Y2Vm(PKL6a52sv2Jby51jgzB)ZDt`7miXVc^ ztN%y8fJ*HL>G&YE@s_pOpKY^4vHCNBhd&Q=5-7WZFM-YhAn9CS3cK&o1z(dp98ch$ z;+T^@|KKrDdl+J(>KR37g=;%l6Mlbe*s5!^Ce3=V3A(wtu@c_pxo6T?t6>(&04m+C zaZAr8R3}3Ww=QXjA9-K*>Fr=x<@aNP7Y}R-mmfc1h}!2+IVd@0Qd%Vp6O;Ty&mo^P zjFj(6T2vCyIy1k5>t{_SSF+W}eD*vIqd8yHeW_KGk>XC1%;dATp|Vf0Y&#QnHFsi8 zWR$}4;lYtwiapX4OJ0+sBtr_%^Z|QxP|i#Zp5N{UmHFUyYjMkAmGER zt8t%}$NI2~^S2cmISzAGQZKG3+CCtA$Fza4H9&GAPhl{bHGveV1N&U=i}H^15EJ1Z za#o2^wv_%JgMkiA4x#(=1hXkG4{JK)ap1&N@jQt`->zRTkCK#%yw6r5OvD> zDZqC=oW#>K7`${!UP4>9@nsV%1O>RfM z*o@w88;MR%(t_TYR=^##f6!5BS?DvVC}vfKNI>o>ZS?S}jZi`WBOhi(lVV7`(j>!R z+Q3I+8X}f@c2$wA{h7b-2grPmac|$v+&&GvdH$?R630bke$&RaxY)b@gQ;V|u+TL0 znP*e|A(?kChE0M zd^AH>%u>pEGmi zY@b6@81*f*6~lLU$mW^Sd_asw^|M9O>8x(>lq*u!|!WF3UU(7m`OoaX3x zn#L`YQ7xQdHMT}#Et*>q>e}Vys3c}=X;0Dns06DaGn8Ed;Q>Fhq`egqO&03B49cz3Tm&|A84Qd`yRaa}Zq>q}hKuMVGw!V#WDkgnmM9p)`E%})}DzOcA&7WcHzj~v&NYB1d%=+@xH(z0@wvn?y;VTv12~*^HTI^0kk(% ze%f|MV%)FyzC^4Dz8T^pAe~Eo!OIT|m$a{@y&NTWmfC{T#Ot*j9cHYFO*v=@BpzE{ zhwV()S4ZEkuA}=pbQG8LCNxMu<2K)NYc47r<3pqLsvOrMcUW@!daThyavY zal>e_A0Wn%*){k*PZ;t4FWne@86C|MS?<>7CdME#x|EBzD~_MsZi{3Aoz6`sDsISjUsPa3u zwh8`@hOT*JW*vdlUp&(|JGg%Jp}lq#lM?7!_Uu%jv^yh|f_0YWQ!dI7S=(AvNDOjp zZJJ+s=(ti^;AO)AfJUjU-GTiXu^RUTxN5ZHV-baf1nU0cMjI8;Q9u(adDA#}g&I1_ zaN^A6 z3~BFPuYGH9sT8;$y-G$-mNu(qobkH~O}@&q&;v_HVVa#Zl7QpZv@dj=oUi&ITs z68natyhXv~h23jDa*2NLpJt0lLPx$8wU-O6xyCQ4Qr)@|hBkUuWj;%D4hd z$*|V@RZEV=Nw?*fMeV1v#(@ix63sl1q!Hrl};`%+ou zJ-zJ1Gu@2R<%J1qM%d(2R@{olV90k-?JD%=LdNv!k*1a>VUs64b%xY8_qa9+(N$Ft zCM++=npB$&Q!qps6N%C#X3;dh*|yZ`?Ko07`!q_a)oDu{PSIIqqw$`GDzdZqynttq z>5JJ6zgu{kJkx^|xR*C+Lv}pp*`spBA%_dpQKj?5k!)?L10J_i{UnWg#&dJ?^Owm~iMZ~nsVv~y)oOW2@-MH*o`_1Ks?J+zldJ1ITnDmz(v)Tri0Z0o#0h;_Z3UJJid z+cXQC9K5bL%(*_1nTR`0p=F2ra>HN9xq5jQ2`_?3piY^h6tUIohwO;TztbPOw zqUf*#zo$wdh~5tpYMtFxBoLFWtoJ7A+zerv(mtu;Z6K%d(C>NK{W8PU@L#B4H@t<_8v$2)B1;;aK<#* z@{uvf1q?0GZe4FJqJc2$5eXKg2_X7Oujh@56F2QpN_NV9<$yv7qOP5Lhx3eHYEzmr z^eb6`>aPw+!#^C5(&3(iKqR32kHJp|UreTW_Qo!$RfN$w1|@cjkig+Y0c=LD03hm+ zeRXpQL?7=yKLhxL8AW%u*!Qd(A*!SG&tJ?RpHHYiF~X$3qGLuv$RQ?;g7-b*|9ZWe zV`CICuyu*?q8@AaYv>?0)M$&dr@bw9x1|m4Gc>4btEHgtAcyonQ}EJ&a#fg0@|_(} zGFHh2<^4&&Sn}toLbK5031}?#CK@-1YF7EXYnjU84@9!=5=+0!Vr zY{Q(NT}+RTDV>e+G*hRbgeH}Qz3p))X}V|qsR?@miQ(Be>&5{a!*VIPwn17o{#i5n zRJ+cao5pd$ySw(L5BUYr3em?}a+EnR(K^+<=iTX3L>y|!G#}2S%jX5HjpGX2lV`Hb z3ZBhtrqPD`B~#lD`shLof4 zT;B}r2R8rH7*_6Dn^;(9Rpr|FCS$EFz=mlxC|dyuDyA2;nK*1CT!cg%Czz_Ve>s5S zB+;Ov43p7f72ec*+y*qi#%>b$7x?QbY(yhW-7BkL|k90x=`~2lp87ipDell zzbJb6V4#t#iEMu&SfPO+7F-A6bb?UQFCq=Ta{Ksvv;wZAHrgmQmzTks@(V+W3iEb` z0w&_shb`4d<5o68y=(GyfRC^+CF-nWT@`-Ijz$#(Kl0@fYWv*9sH8qqK1;VXlH$g$ zJN|oWB;=FO+UBHt3suPg#)0J0Ug^kP%$}Fdw;$K@Ki3FX^GkKDB%E{|47)h;6#AcK zRvEwXIFDYmaDCd`eJ=fsDyIcnsSaJht~2#Cd$EmA)7;VGsXJAL|4Za@1!+on)G8ts zSyE5$AmY>YQvD&oZxA`}BTs?TnbT)0`|X$V*oBKuvGFY7uNPVAx_OCLN3mLKlj1U7 zsZZ%-oH{bXKdF)`!7*wre#}!6{2_KJ!8aZ|(Km`{c!x`AJL@^TQ|**CW95iMAv}A< z^wUail%)h!e+I&ZQ8h4Tx2vbEk<~bg%OJ^UOt2K}Iy*jW1TTLzNDs}iCeVCSR*Y3+ zhP*#0`RoEHxuvZZJXh6eh)y+&kVHApD`yHh73aF@Z zl#eZNU-`*ig;r-b53G!Qsb4&o#$|CWo?!uSa>-wL3#DybC5@o>g-Z)Mrn$H&t&9Um zLhv3Z+S-$h=~{^gu7<|RB>4KaY!qNh>{zeOMyVoKNN+X*8D&1&X#5DOn_L!lDZ|Y# zU!1~N&8A+@i@982g8;fiXMNK?*_xJS%&liT(3i-o3965!6XM;%k5-fFRT9NHo60&r z2MdI9@`*s24kp6bvn%-k*DpHz?;vfUK0TD4L(@=M8INcZhp91ZB_+@7xuhbq30|EBv*|P43lJsD1IMvzr~K=*7w^t%6Ek*? z#bAR5$#jNGeb^+F!(dQC(kQ;XvFKo@b&1oYfRd;RV>eo|CUUq9{nl@4e*GdNYfg^Q z+A^A_S8A84?{i#b_=ka!w<=v!CnKL7Gb~~ZF4Fm=hfWrjy%ySb(vNtK-$u@G_3P0->=04mU6)%*`zAIJoGh%CN zmqMB4LC~X?SlAGFVl{pz1`&*e)B(hSG~9Q8=#kL>JA3W-sF7QE=T%A?`48DEt#>Kh zm4qXSinGzAcaB4Ry!dh%!WnQnf^Dq@)R3v``<^>)Im#0mRjGh%@OfcL(dbSx)0i59 zqOYy&KhnN~DD8i+nQs=Kad62)O%Jl|FoVhaQuBFJ-{=U2I-{qXQ3|HrmZJQ0s zif4fRpu>Vcn9KU5l7?Yf(35F$Bxk#z2obRwYAEgftq!#cMAF5{@EZ5rS#@nOl$(}t zQn?m~++1bM&f?yp@1SgzHfLv)bhhv?(JqS8eGwtLVzSd;O4nkVa(a8r$-!CCm4@$Z zorPP$@__$Sfw)R}W8fjn^ZWp>qhB-!Gc;wu9FYimJw{-R0MRHgyNh0gxc%r(S_ZiDJnR0;`wkK>uuy;%HU>cK zNf?0CNbzgAr2_7DWV0CK<&gR5$`-#TVem+uGFw2!MhCCegXaAh*wp+;oW@;h9smn_ zlUj-anB7oQ0C#c%-t5Rzk>R(j7Ry&-fo0x@5s@Z}tz@tF7=oMm2T~D~j4isBwj4vZ zV2dQ<&O_r_qT&|k72fLzcn_5w2I^A3Az7-zeWM6z)|x2*e(40LKFG-bOo9@q1EdtL z?rjrX0Nl_fQ2O}?sJ-+jp)BZPxaXKYh)co4qZy;SSrxJx`FpEX&#eQNl|F{V!s;nW z+S;F2B)NZi^Pvlef?+IYkP%#`nhlL)RX|gLTRQWVx*CM2%c1}^8j_&m?j-lvI>{!+ z_;EX8UBS?v;t(1S={T^|&Jv2uoU0Y=NH%BaNL5VtQ_m&=buB494$kOwJpVLmHL(J8 zmqR4A%436|Uk50$NoTb`&cL~J$5jsgVywi~m6gCkS+Z(KA}4*$AZkm}G_8MZ_$We{ z(OL;j6egu5XEOy+sNKB0Xj*^9=;Xt32l57g)574}3gCWj4Z;pI zlyEua%n=8%(Wd!e`%@zk(yAy9K@Gj!{K-z@zATXDm^ZC4k8Hl`9Oh^6jJYQ@08|F$ z*Nu>a<56l;ZqhJroTL?pIU!{j{4FSS!P;VD3VK{Rn&kQS1d+Ao$G z&hx-SE+?HD)TMVBE5J}p(o0=try~za=@h;^Tq)vAV64#cG`Awx;;wReQzj5Z%z!CH zi|yl1$^X8PU&UmY6FJqGs$*fnlUC-LVN|-(QmRsO?&|9-$|_jmV_5h(V6b7Y$B-d3 z5_b*qA%Jn3Lnpr>wUCXQn3%A951TKg?LFqju57*31VA8jzE!I0&QtO~HqmR2aHHkv z#h9#WguSl1_5KyKIRve-ZLibxNhLLbc?BgFHB@mb)Lu3Z~J{pXV{a;0+7H~*p)&DRn+Uacq2UtSFQt_WY#-C@9klnF}nqKgv|CsnP;Nm zVm8gKP~9-ug7m_d;!eOTemVY|#D2;!1fCKPl@0fQxX>Ww90$ zqYSgv0}QD+30NYt)HZ+A28`vi}NCL=r;@1kDV&ODr#vp z?;eQ~TP?vGi6DXWU`|QsX-|6*qW~h3k(wA0T!4r%RYX=u98IW41)x$)l2I;4Bx#Gu zVZN5C40s|sd7vSXj$;$*CR^G~;+}I2^-a%H+2xiDYKO6_Zl*klFh7#c5r0c69z|&u zryN{Lw}FBPEW0~jD!mCD0un^$>aSzFjDU28vTvBkCX0m!Ei`(GrZvO4x=WnEvOtN? z)xg0;*GihO7uUT$}GzhFV##}@rc-ifIy{#u(3r1O3fkxjEg)$Ie7s+t@6`2~TTrtVp* zf{ld2`PIib?v#{f7a2(>O4Z^|uiwGLzY_db!AsLezITOaUxl#Nm1=3rajW%p{~b~ia0l)6h1=b z@9@gDr7EFCSkx)8UR)&V+N(-QK`RYh(;v5Oj#HK0dB<$%FImQ41+RSo1;2o_4N9-7 zo!qF7CeSr=l}Zh4m5=83a>072Z9RA-Z0o`A{vJ#TteJYRH*_39O~^oJVOT^@)Sb-9aJ0v z-lA@>R%LzCBMAn}gmZ#lur+qYeTw(?%6P~q0Mcd|&`vE$m{GRcZFP@v#BHASj!c%3-%SUq zxM{+Nd5$*vO6uet6oa zIRLpyYNfj1rbct2$9;r5JS{kZf_dEl-VU@apW%Se>hbB~0IJ%Dgil9khA8WpyMCZl z=Aih12u+w47Z8X&Fo)7dz{KW%Vk09O(%=o_!oH=5SAtx`zSf-md} zU{rI?p8Q%(&U4F+|2^~>Db<3u-hXAt!F?=KSt=8XNy{3APhKM^1v$+5lW|@toh3|q z-g!;aCK>SZ+;fTBhyS!So=Xc|G_ww*uHFpZosr$M692TNnw|2X=_gw~aeJx@+VGDA zqZcJ5CT52qJ9!D3l)Tg5H8Ejy#Y4DU^>S09X^L?Yk|>5(5lqr-rcOOZDLFoy!Ei$` znaJJ_?h(CN_`F5d=D}f#o}&e`zg%89To|A%UZdhMuhytvwFg6f`fcdWe^$phOVG2@4 zL*N@nxtdDnD5{d`<0(=!BQNxc^!RK1{h${n23e@&k@!NrBhkm?5UP@(*G-#hJmgLk zQmjhSM#1(Qf_ZW5krf@SZ{CXVNE{fFZ zlCpYLJg(vw_@HMc{#^)^MVWFSV~x2%&hdyhr6+6dN^bj@Ozoebp=hgDgj+3Layv7p zp6RhpYd!K6l2-rZ?!HqM!oH_kCIV-y4elBTVEwvk!q>z&E;H9NN60gCVtmk|X6Yzw z{PxPsTBLNN0OY7=<44@Ukz4_IQ@Im2c13yuTpll>%vfDxq+`U$fBkrY z!00A`DmQ<=8umm4N3G3+J%KsHO1>;mO5@h12iZUc=NmH7qaf98M@Nz|7SU^;+H$C#^j)BJV@sE_Qu5yP zA&3iZWvNE)37g6>pRHl!N5Gjix!{LE^#&z>I_*~_KYI^=u*pp&#R)QFpek2QM>(KA=K}O3 zNgzXBGyy<^+;dlpB{u9~xgGMAlY6qaSHFYI%#tPnq)7USN)0oPmN`|GU9Ng)j~D18 zp|whLF3^70SHN`$K)6Pk8)Ks6LG!7oH?11{COZB@pZ~x6n%y4<^XYK%HYon!&KZ(f zTe~K}2`nrh0}-MQIH$1i_XRqyEh*5ECbGNNPmV2;md}rD)fq85QLaeo(cC$X7R;m%$>b1 zCg8oS(i#1qFvqD+2B%Ol1~Zl+ya=)(`-N*5IFcd=mGDL1DhuOlifJ*CZ+u~*pKX| z-(GL>0xja5KX3ZE#SCUA;-Kijk2e&6*z4LfP5~T0nmz;8z8~DVAS>JzVd3{^C z%sXP8sA(?G_I26qS2v!{c?0{Is*OpfY6^2A#quSrP(cZ>=32RYU?bu9lq7X`>8AvP zmHp(j5McoYuPqxOrv*^Iep6rSir=Q0JiYm#V;r1s2%6l*m1aKT$* z@#xMBiYWC@%-9Tvo)#~(EK8^z6>IRS9>4}EQU@x2G%2VS_t}g#$k#F9O^XTPgYm5I zApC+_S{SSwbRY$qng{IGq?&wd5Vq+NdWWjnd3Rk7*q+^UFWd^f56jx}viseIiXJBv zF|atp`&MC&W585P`LL|+;38dBfv2$iVNCWv(E$$KHIl;;5qW1 z!ZfIc%0(R7)CU`Qg)m_OpX2KgqD`LbA((PgEP1d!SwBidPKfAmvp4~18fAgyOGTF; zC@&u9#NY9s|0!by&cK3Yp)g~^{75Ig5JOi)pM?i@#m%rOD7hADy<#JY$n3UzO)4^T zLoe-wQ_;DAsk1jnBRPE=TmX6*DbshICT+_x^xR9FPzvg*#;%4OS_&b-QDp>GBZwQT zMX=B1NLCI&ldIwsfa1Wd$klB+GvkA>#UcD0F-WTJe@J2JHspW3p=cDqSL62To_ z?4K4Y3vIrGO0t5fKeS0jFg35f9(;ektGzUpAzI1*gTBoN~0DqP= z@xuzipg?TB>^(Zj(wZugdZeEwTD&~FFTs?jUz+UWDU+u}JpcnTa3`Dx452qH??!KF z;&Hvs_;|o8GfyrMj?+1b#n*!kgU{(H_N|OINZ`-exV&(v?roNXXiuw$ZK9zwY#LB`fgQ!-o25 zUhDe7X`18Nq_f+>=e=OB61}WzfjQgl#Si^1Ts$|#*0;~u77twSETRjc#yCVg7pfqU z{YpCBs1XDxBhSIc0sNUCbt=W-Xv1Vm-YTN)nH=0^8k>-$AmrH`j}| za%9tZkm$vWv!=^w$Ll8m7>=P)E(=KlT`al7b;*Eft=L=beE}K|6 zc5^n0jz+P=TN<5i?`r3l{kGlK%eXMT;~W)21({vo^XfDyyP3>-sBWz_1RxGJ@d74^ z$rKd%(#vFsFQFvlK?Wd*7x=35G7Z=i{&jQaix=zL-sRA16d-!V6pwY)_nrB8d^TRr9C6 z_FYeY5!Ij`^Xgc@{M9*X!*|edbVb#VIU7+#Pjr=Z{9%QclRqnv4#Yt#5{RzlJZodB zR4-U{vV!r!4s*{>6uQ3LR(Li#*K1D6HO;Jt!T*g-f~yF$f&jxSXfHyPZ0yT>Y&cjr zEIF+ws1HDmn&I>Yb96{(2}S)i zE|G(csmk~W#V$t+2)Pa17QU)`!wtJ@3Xo}PJBwr*25?{Q5%mbWdyW8e}1Sal8oR3y0t{47U{)No;yNc~qJ!lOBi9 zA`_T=@R5AkS_Lzjy`u#FakS!ZM@QZ$ok0BVWFZh>xIY5)AVr8#Ols`?|QnRA)O)SiNW;vVswVfm09Yk7JsL(8w!XPCKb{L zgb&F?wl}9uKnQ32{`PVfya?RQ2hF%-)0)wrQPbJnKf*SD3Y0Gkz+W{rn@Mvyuw&g* zd(Cg{Y5h38syLT@j^O~a?CO2*^Dvnr0+Lz>eg)V`_+IJ8KzmT2FohiC8C>YXi&Q91 zmsZH4QY9X4rbIyFj(|Mrx1d!U7|NuyK>u@g&Y8A!cu$Q_rkT<*J=KSIeepuU7D^MV zQ@H^J>jo4tNL7WSL&t2iFfPaE3$1g5j*q)qkcT3qc|cIzG(##Hoby6NSniCal8BML z{7d1lTr*qinq<~na5`n>ySeJoI;C7!xDLrO(SKGG_TVZpiBc=L>P9^55 zibyZ_?7Fd}Pm-TJSSrzFkHC?qar%EsgG`*P1VlB9 zB5j=||D`c2yFX*5eAK6;z{|u6{J;v4H7O%tXK&c)}7VK`i9@*0N;*n0(B?y zQ;zG@FVo#wX3?q+VMhKq5}nUi;+vE&hNAvtx6V0igl~LL0hM6VBY6}Gxx(ReoM|Xb zW30_7H=E!tQ=vcKdla_(0^1*7;F|P{KS!bUUG&_KSpbBMtd1aM2p~no9Y5NH@0e4} zF!crXt`nSYEIyoqn&l<31Km{fb`z{u)C&{an-x>3?m-7H)|owjM$&mH1@B{H>h`(C z!!^*LB5=1{QS?#R2W9A6L)euJHetlgw`9Y%FA}rbiG3F27g^?M=7rnb3zKrT7mwi^ zffcs9@F|u^o7ZP2)QUI~<-{~9VyMwgI6i5i(Fzq}a=pI3I!E6ykic0E`8~Jz-w6Cy z1!G>Opg>+)qu3#J76CrD%GF0u3a_4z!nndHhK1f?h!CEtzMA1YxP}L8Mp%G!TF~&u zPSYvsXwxCURJ`oJAI{&tt@{oVndkowf&qr-f4c)Pjf%{3|9J=Sf7HT{Q~afc-}*q< z&@kT??^J0?B-qd$Uf-ahh~(CWOr{m9-AumQ-qyh?%>ZuCCA_u zoCZK)g$1HhaZR8=G#yQLvI4|1Z)0w0e;!~}^ZfjK#FGpK-xWc9;+**?0rx)k#l+Ip zM#8@0kZV7Q6$!Ho+20+kuo>Qs8)_3lnMzcdcBsNlk`gkdjp9=90F?Lhq*IpJI9e_z zBObx!M;$``g~(J-z06BUTp)>cN6R@NcS<(<72>kdORSkb*9ak%@b0|{FD}Dy;{Ym! z7IkPCx|f%}UDt&ETC;ApOnX$3Saa~K%%dmP1Olfdo)c*QWYVth$yJoOIGs_SY>eq2 zVy-E0077|KuqA>yxQxm+bF}w3aYB6_V=!XvVI`N(uLDdiovw)D z@OViCLj@UV-E6cPlpyO6hssHLn9pX~I0k_{2Fk=n_CD+jUqVI3QsX&-3!XpJm31d7 zt6Voh^<$_4LC+;5A;<`V3!0YRXPw=dS-0d(X)g?#;xwBt!FJV2b?_~%AP{U2w5wGf zk;VZ_2GZlcjb66w8;+D(7$0Svs~W*F4b?`xh7!IvZEEXUv2l>0(lCs73Ee(e_WZ>X z%N{OSWRaN^XV#NlEt$p~*|gd(*5YXb zB&kTXL3R>od@6Oa)lUj2YAfFy_SA(JOGpk)xFlxjY+a*7dx=rExNArpXS>#6M3#rQ zoMvqTWi3L~2EVCy(kO3rHxr8Wce?Pe73W}IJ)C+I%@7y2ND)dnzMCo|nGe zoieXy&f{#U=N#ttEaj5iraDbd{5E-4&-1n35CYJX5vz=kJvXp7%$O?13%LZ+y1WCT z2w4qWC#`CjlG*LHeAqRCuxe2Q$6af2vEE}FRbUyu_h*-h0Eh~p26$4dv@M9bp7NQV#Kv9iz!0iGe zehC!rzJViEqw}(Qv&D=`^f+vc(Cm*{BxV*bCTL-#Z3<>yVh&=2akZv)h#B&97V>sx z2vSKyvDQ|@=FmI(@KEk(?`o2)x+3D5zWW@?C;P$0C=vrjM9-t7Q^vS45e&CiDvfg+ zUeH!5*yc)~>g}NB0k0r|_5%CbAfys4hR@?KO!5B#miRw0$p7Xy6xpIHQjVe<_yr*1 z?bV#k|I7A|yNtMTELZQdqW|9fM4-=lHpDTBHL$m~>2U3sUT5B14e>pFX*ZGAn=;Kc zF=)gtLDB5SZd(AN38Zcs;XuY>&fh+oKM#{nf3{W?Eg39rBjLb*3})W}FjPPD6g6>y zaN?x($<31Dxfb~98{XX^Ep*PLQxLdI6?nMNShtp+M&B}A+MJ(j$p*}fNUfTE?e--C zsFnWqI|B?AH%v{phk!L5PN(`U!{J)RZdD9R!|I6C2nJm%^b7lP`_Mu&81o|QLe4v( z^#!ANvf_FD6}{%$L#K8NoLc=l)+aZxSl58mQXai0Ps(KZj;Fd|AkS{$14%+Z#Q>%O z7CzOcS#p^5Fb1&Q-9e8RC3*u=2R<>&DW}rU-Ug*!%hHJCU9-iWC?Mgee7(avTkc>jQZH#i!?@V)0aL2{qY)_oa*h(8x}Y)sXpw6Jav&-0jeLhTCw=zU&lQ z9pzP#5KKB!>2GMcB`q-mWb>;~gD)J%9F;cJCSPj4LXIOfFUT@N-2Nht57)z@@JVg*f_#t=e~KtkRW7VESEdKQ9XN274KIkY3)e&At(4=FDHd7s}mo&LcGeX0w+9QQ>tsJ8=KxB|gi6v(JDvX7`dLuH(bfJp6 zyfU%3-xfPap+jQ`tNcvYlT5~+gz|aS?CRD;_?|&;DI7kPUby!pvEtoZa-oi8tvW;- z>JXj6HQdlu9|2w2UcdEqh8Wwy60GsP(L0G4IBL zpJrb}DJirdg)s09T#w+VhiGMEv>mT$iXh&txD?O>sFm}?_qX3cTHr+h;YcW4zALY+%*!xX#1ftJphH z+&iv_X$Qx~MGLpcPH{?rCE7cne+^WY^uH*)NHAG<-WK0`OG2sLxJm+viGolFEMSj! zR|n+KhJGCbEGDOc_0+~Yz`rqV7l^2T3>XRsg3C{cHy21p-_Bhq%s+|EHuP~~8hmY% zC%zJjZduE;R6a(j5nKmZw+(NZackMRG*V3t5TG+$)?rcC#zN7x=<3Jx>Lgg zTna_sB;;I~Hb1&*1y=S_+)eX>NLv7cQyi$bM_V$2j1VY)MoI3~dK` zb>?hw)$=a9kUxC9p8w+G)$*&4SIPsv-_5()CxFZ`I(1n)wevyC zszj@6a|!{Lj{HP@rZC49?fsV*F>GxYFP}zsqlnJ=KYf8`z9HmOD@`eFXtpZuHiu)Z zAJ%*Zt0LtT%(h4>k!X%f%rgyLh;NGEJ!W)rAbAS{QkRaUb33x>nuAPdeVBsB&FNnW z%fmThQF^+MD}|Dl%W0C%(XnPUK3>Jcm>k!ZN}iO4vAvi(NjM6Ls$pb(k$W$vuD8VJ z>rd=^hJ!Vw(d|;@peb@e&r-&rS54|&lC&O@JZZZHEEp1W8k-7*K4!^M7Mn9uuxVe( z24KuF55x{G4Df=`H8=NcpAZ4$>6g!gZAt1Ko_!>puQ4G`h>$1!I#b@*ZpO4yb;Bt1 z+=xwbEjU-Si`)sHqixiRvYtD@*s4mBs;`9BF{z1*T|S$@m7Cl3Ep?=v?0RV+kxDH7 zFmjLVL-_&38P+LhK})_)&DyH^>Pj`jpp*Fzsji=UL!sdeM4^h&sX+Xba;{m^uXb;Y z6B`El_D;U2%_dcMEyrK0CQ?1dE3Pn$^Tjq(&LP($Hq0hgdNsL#eti>UDU8*f3u3a0 zQWhub8=14Bs}Da81{`YKyZYH%X69-$B4$g=KARbym_&=M^A``!Q}T2kVGUZH6-aNB3@suK+pCD+usyHst{Z zlK;KmI7!M6=PX>GpyW_|Fn~>iC+NLa*{1zpMNRxSP%B%@-$BaB`+@5Mp5H+fx8SqG zrtaMKz0LA56E_>Envky^%_pqd``Ze{Z+X(PNlcR}XwsZ7HGAfTSjs-jlok;2 zIzGmsn6J1hb7PgJS&?tmA(T`3iHd@E^DZmHQd>C9b3 zmrC0c+jm7u6R1xW6RC%!qnw^%Gsl^gwX>z=wGC`ls)6u$ZPXR)nwQXps`+P}Gc0_Q%j8q@+3U0IJZL4`$O-A>d zBKnJBQKrT?LchDR#1uFfFa&Qw)sq!zcWqJ zNXPMf0tR-NE$y_J7gqu)YtTjWP9Scxrat{;s2oVuaaHL&eaP#2nrz_rmmIYD#}JB^md?p_Vk8yiwj%~Cf~jS!QhCv zhoE=x4CT1JhV*#FJH8?$DmZKOb z@!l8eHC5DFrWt%8&<}j>Hv_Z0JOwZiLZ@5@;(ywI3Wl z64*WMm`O5(P+b8Ni)_3C*s~|4O+iSb-p=eJS3fJ3B9SLy5j`b8MlVTc^Pn9t`#nH~ z{+rnAZ~tC%)9{p|aolQk{84#Ssu+4Ai%t_=FGzk}+%__hU4;1A%sa4&w~~{(-^4UE zWad-rcTk;SsPF;GL$>M;`yCyd=&oxkRHC#TT>@r8XMywZ8rz&ajWh}`+&^U}<;FRK zg~iM9Jc4^>o3$m^S*VOo2N1|KefA*(Ku)kBdSIJih3nwt*|+!eLZ6`CVnKq*ZhWtl z2z|H>vCRo>-*_e2fi5_3!|@r1-!Tp48DRl9fwSLS=v6)zpkGGn0B;AS*3;jig7@y~ zw2}qtvI1cNahifx<`hn1#ovnipc7nMGTRHMVl%wB>zanGrU^)T(+VZ*!IrJd2LT#EOrM#sKVbbH$YU}y5{-7Cpg z2jCC2FxzH{5@Rw3CrDwkYd8<2=e<0jMqx2M&`xi(dObH^?`TArRpBhWCl9l;^PG@t zjP!)hdz@K-7;ld787VwYpfne4w8|gOade%;(_lRuZoZtoU`8b9r2gZYl(v3sl0)9k zQ)t;c877|Ds}evX$}Fbm6_e{jmolT!=X6`~C9p?xtz}{q-9#vWrXgoCpk^=jJK8hH zq}1&(H!gFDOnbqkV>Es)^wShrEr&qM}ZqKNgm}G#3l4zI5q|K$sW*_7EpLv z1nfHg*tIiKF_4ZxgQ}TY48+nW{LXPQ=~iL##=u;tmlsjWj>}kT@1o`wNDPN>bKAwC z7)%imdA{AN;eiqMocj5cnP?(BfOO-?jLan0LzyM`Xlj$$PAb#D2z=02^@L7xSDTZqH59lkFnD7zz5zXB@VDOV>+Oa8hic-wkNe3Y{D!l=&^;?0( zk0jM^$*TXU{|CmLWSLamXlia``k`wjsT;_l^ z*~WmI3ALb9TPMiW`@`LQ-5b7S8PMw(3@xfEwi0F6o*;)gK$k?C%8B?yt~k)OG5*}_ zHp*>+BRE706d5_?ytQ|!JW=Z=E!W(+`)#_0%pyrJrd?QFFXO%K*pXGlLOGb800y1AO-TxVOc`T1o z)D|_i&IK=KG0J`W)<`Vq95ou|ZsrVMeB*pS?)(I)_68LgT50%&Zb{htL1sEHu-u=l zb;P1H8%21cOxOp>00p_SYP0n&2@}!Ct$H+kmotK;v%HJwW$|!rq0UEDX|j zxaYmtZ?!$U7zySlZ2%1oQh*oSAaqn1tsMP?-c6kZYIS5cN}<0nFRy-QURnZRn{Tg;5AU4!h&86>7pO9o4JP@5+dg2M z3e!2TU#gJsfAdfNcE`27b#Opar{zi=A%^*8v;%uJG^a?aU1|JsxG40FzZ=LE#DipM zFd_==v>AT0(Yu+HPzhpTs%G8T_i~Viyb2Z*oNs7IU|?Aop+$PA)3-qa%GMv%T+NTk z4)5UAl7cJ=6-q7$%?s5Ng8b##HG^7gkEeyv?c5gxAG!`+gp$S;G_#6;(BSF*7=-h0 z_Dp8wtEEf=&k{RCeLBoz3VDs5A`Hb3r8lRbxC_V`5X$WWq00e`RHMvPr5I^Qqy*$q(!{r=w1ZohlUaJI zoSlA7S_Q^uTAvZK>Wx(vpY(xXf?$At)d^#nL#UI*lbT=P*lO8D<7xv;)43qB=834a znGOmQKWcZpzPqI^1rHFt&I?Z2JygY~*$sLie3&~@ixR;UJ?wVkY&2zl9EQE{883Q# z{e}?YG+JXe3DK)BdUi5N^Wa2zLr1$9|BlrFBK-*7nBX2neEq3oKD#%y$~hP>Ybt%< zhp_F^hE&{uJc#~BNW&|DP$Tnyf~=sG4Acc`zJq{bt>(y2Wdh|3T(w|Vj_{efv_1Nk zPhjYfRaa~%)m$P=Uwg(c-{9Bi<33XJ>^g?jpRSj`{R#%49!lUvbAU#scuoYci;p8A zH}VjAFSdSP0{l3|NX8aIf#5d1jU-83!L1>6M%FLTbz*S@DqKGE#r#lPy9~0sK>hS& zjppwB-n2@;3BY2|2_FD3>g8-`LVDX`VE7&UlzcG*25de20ngIc=|FOQ^gAdp1-1XD znJc#;$QCWx8rv5woW6MQDX3pP1-k6D$Vk!q3NG)2=S38=ea^R|T*nwO= z6>wb)s)3-M69E8+AXIA#ft3c>8;a|0zK}OggSUvll=}f-BEvBB9U znb|m=mAhva_C<@Ru1AE__S+qW3ZSOOhyM5XA`&2 zwv(hWW;NbDtzy@brkC2Cn$eI#n$708IC2g$rwX-od4$B!$=p869sSn2i3`laF5-^+ zkFN$jLnzktY?;5$R?my*%MiiUvd2eWX!2wQEN;1zyC>QeiQ8Ju!fzNlQY2)tfohWxa&Q){p;r z&Dw`XFQrIOn#x(&IeSNM%Q5Aju0MOSEqVk;-P$H2ynZh`utw;mwUu$hWuB&P0elfw zza?>#sS=thYVAxiDz+w0^&H2cuTUX@ z`0%ah0Q$?(01{Gw!8nys?+BrEZq+jUGH zWQ2;ai;ddh1{P#3iszUg>b4e^^m&i*fV>X^vll2vB1X2i3Y+~$aQSl*cJ2BK@ZY+pYf^bcH=p4*C+sa{DnQMyP*?3UB1fNp?Qqj9QHIX!prFVRqWYL zGjV*p$VywSU3gUTE*^iJ8YuD5iGb&JYl_)iP~whWB6~4|oZcLK^c~Pqm^8W%DK(>h zS--XKFe=!6S4D^Gx=gkk86!!(6iHL1HKidVoY7B% zM~wkrf+9VDC9-A!Zux22D zAm=*sJ#)lS;xDgpYVtbSg^L|*<5Uwn#pIOM~RVG|*g)bkJCs$j8bd8hY3LIeIR&bSC#Pg`~ zrYCj%(R0&PdW}uBxqDdRMjd zYnhX?TS|S5;T&!bM=(N1d1@c>oLstmS4u&CCMIfM%%i^ZebH$7u1x9Jr@kJr)?*@e zHQw*lo#g~Eu7`}7dtcA^-+Gp50jq~Ce?x$m2r+5&SJKd(8;LC!a6**xl?S;tmEXT} zQMi4uf1pXJAgYCyPbJxb24% ze#A@k;reIHK+00D90>pNG!4cEzu_^KG=EHQA(h;tulawY4FOoQCVfvp=wMH-Qp!|p z1P*DzPQl0cAZ%MXv44mVTI zp3kth^f0g*MiXH07UPb19f2^v{?x0a{Igz#{co-Y_5XcW19);~@(X^#Ty|@i{0<{v z{Fm^L-;h5%i{~NUrb%fP2bqHnEmy3qV^E7*vdvVIrwMuljrUb@oTo~3dzr$_dtqc}1L3K&%n}P{ zBUW)SUCaOw&4aDBQ8TU_wc?2`12Wc~+krrdZafKjnvKD7bYn76<=b1xhU$bmLW&olh z&vDpTCQ4nxW6hq^uF0x;cv(lvhFd!tvLK27n<^>tkL>;(-Ccg@+f4q= zsBts+#co=r=_#gn#DX#dVyp}#jc^30sTcyh(@nJhNj>a8sF#3B9;|xrWM6Zxm<6mp zRW?ph3nwN%89+unDMg`$ix2Gd%B@;JU6Sttsv*?<{4;9CLAn!kXt3L{Y;odW{EM{G z=yAO*GbhV*W0uu0#vh9Yz#2Qi-#G|j6orAdCHR8x3uVovUtyFP)kN z%_tUOMj<6S8u}e&{e>D#HD5jO=$@xbL|H0J(RXM^zLr1)8l^KaUfZMZVGo@zGDY-z zXE{<;S0m*=EY`S*hIAHxu zuzumtcjL~P6w0F+1$zfVc=39xZ*VV8tjyk>O8F%>20mr16CYVOqD9`E0mPhDEf5_YTk_Mi`z_e)b<3F{@L7 z5ky3^x`zb+mK`Ray^xfPv=u}^b5hVU6&FOwe9#_vLzqBnXU=r(4+1wwoepz;$9%y_ z<|CB_#va{G0TutuQ~hI}SLedZay2j7qeF=B_4)jYTGrj~k)YOzPe0D~4$H76bP?!B zRt5Tz4}sJcStfcD1NNQskA7rzAo1B&mvR5L5tGDYTYJoSa=UiIjxn&Wqx(2^mlou} z--sW0qllQNim!LIraNKnqC}DT29@P&rCxJyo-^s=)7IlqnOrDYOT98rgAP8Jv*W&6 zS1$t)i;e<|5TLPhJVF@pR{|C(Q0BP5UjVQ2flpn5q-gQqI9HOt9%`iP5pafj*AV}V zB?o^U9UG*L8n|U{?etm&B!QV{y_?9kD9NjHV`f3k!X}ZY+5rC;nbJX$fSsK3-(ayy zm4tCNVs~FE6XXU>Z@53Apci>0=_a&X9G_Su(B+()Q1vP{uVx6XGEo^uEF6Jsq-fr{ z`g2^qj-KSzr{WVrTATHG;kkyWw9{VxO}BMFu7VPIF>S*&Y1cG9vsZdnB|8dYedJF@ zm1fS1ZoiZk?Iu{d5cYq}wW>@?Y8@)^RDt=T#}d^lOhSVDE+x3IK!2sv@Jb46IDub> zf=}w37-=|Xr0@t4BxtG@pJTzBA)(e{>t$L6zc+|Lw`{mhY!Ao8$y*WO5I2r$sq=ei zY0k&I*4pyaJsdKYr07PPXoSg05^LCh7pZ9ljvZQ*sY9^}&nYFIY?T!-cHHrQ;%{AZ z(my)txV)#oNXfm8X{)M=+#5KWcJ~~qK^rFL!?V zaBjP+Onoe-ulVD9bp?}X7;Wy)w5TeFtaw?oQuVcyuc?f1&DWD%*Lb<{*f*Ie9bxGiW&-&pdcy(VbxD#B38R+kM^TkK9oAP9 zKHGy|8yMBYH-mt7C>Y$CacK*#Lcn~hNOqm}*#3EywYJmOdG2k~GylDBZazbj4R9Hy z8Vwa~fx2WNdsF-vX6g^5#_iKb|hw;QyHVy{KlWzEf= zNZ)0K2+{4d$8_XYpLBmKN!T*2{xXNA6p}W}(Woqa_ML|~a(~RMX>lt|sC-PQd}_;w zWo>^L%iTJ^z5yNf`2g|?>2iUfj?MAxc7cFZ%Q9xHEtirQy>F2xwFT7q+uCeAQ;!pj zUBu0Y$t$#va-HTLWz#rY}=3UfxRWVGYcS0loiHLbaR7nr4Xytor>VM+9$B12yHCe%Z#hV z&T%4zzZcw9W<|^zR+(26Ugosb$i0Gio4wEapC z8T7dyhea7;@BGSp_E9u}DZJA;scH%Mah;oYCKn48<{WQ2^cYVgORM-E5J&2dJ;08= zWtix|wSxn*q|Na#oXd7|HMsTs%gVDzR<@`%<$prEDcDadJ(u*9wuAs%mmo4SJvA z!(s)h=$HQaFJ>>xM%50(A7dZ9a_9^4O2FUDIGQfnu5Dh}M;Dehr>Y7?Z$YCD$~f*@ zeG;sfp7u}xmz7;v<|BfU!BgK5X_b;#C<|D;D}6${mzt=M@?Gf3`j*E+$+lK<_f*sDp z^P-a2E=p68cEPz4i5XW0TTHnxFfXXu8u}w9i71{WJwNQ_2AOQ9kVdxGs`CyoL^Yne zPJAxpei1jhu+Esx*c|f%A9Zl z*CNRaL@{v#pyZ|FTQAe}aPQ_7Y{WU49UM`Ypth0jmKva-G*SPvMEdLc^S@D8{#Tl- z;`|Q}%HSs2f5}5I+5w+EJ$?CSMb@hFpN!W2_vjtZxbp-UsE=+vT@fcs9f@*f8RIHO zx{cZ&k&N~&c@Vp1qCQRe=r+MfU&=8UUcz$rHot;&JFFZ)K1n6=`fHlLY2psKZHTG| z7AzJ}{9(cQc?PPpHHldDZ^@CG53?EPyK1VN;ZeL)im$mC?8u^E{TM7apwwDGzWg)r zJK2z$ea_wpS(S_PH$TY1>eKh?*%rbPVoJd@aDp0q8PFR7c9>dmaeLN95#qwMvaDbU zZVC=25N`P7-cvmHuXA&sBM-6&+m zEGh5^WXJ(@@Zv!r=T;*frswf$Q!)fH23VbDAp5n;vUH}eIEy-U!ifmJui79(VcvxdW8DT?MybX z*Ukdg4Ptc1)H1F;%C^WysYE^26~2AUOoDTrKUmmnXN%`y8Y!DF|M-wvFmS7bf`HsX zfl~EJ_Ofr_fwIm|s#obRRIktV!OF5Ok+O||V|FB-gvpaSS#y{Q3AeS^!YH(`2lHKO zzk%%7v=>XfG!z+&d$9orSpSaN_&>(+oN9Nr@2RdTVEIy5t1>b=sf}30jTKvUPl)&fpQ2V^PHV z%Wpt<;QDa5$Xl9MTH`21N?_)2^C*Db7{v?jJZ{9xIDD&gUcb|$!agqY6-E6OGVuhpap7l5GNazBKlcjs(c?yDP6>DA-!ji5A8JXv(2$_SlzCw>Zr7%(Jb`PB0E%MG4+ks;x1X&V4qn z8dk)Hg}-V5a*`%NWQQ?9Q*jop?xcLp8kwiz{X}(R+SVi%sl7ox!##m?{?%Qpb3754 zSalvWIN`&WYvFL?W%~|qqnZ9&)N~Z}C+^;`5}`k6d$q;%8&HYTA8LTM3vS>aK8|3} zkxcABpuq9u0~*27rr}r}_dO!6;U3MdFs@5EP}T#WPJmzQ@9v;&8+X7>R@VRHwyUKD z71e9Grd?F@yV{}+!!QxVz}e6=jEVtFM}#1dfr9|3=oWnME%f023CK-wXcbu-?KVhy zJA{pl*1(fvNeie8$b)pUiymSDyjbt5PB5b>WR#|SkY_uH1CNPrLvNyh%2&>>8=0sos`^#( z0ACC><8Dg`3cx~s+3+LcWo!y(X&9(&DUvLp<~2#-cvqJIDMe*eYdGVS*%@Co4uYQF!i|>9SHAeB8^v!_J55 zowP0W?Ii&<3*{MamVit#3)~5AjyOm$?ln^h)xA>?0yf(C$I+z5fz|B*3}3H_2*P&D z6OH#m^*x7TS+p)axdfbm^v2{QD^ZPNGiFZmApuEa{IBtS_g>7LMX7TQ&?uedj z4zs|)m?`ad;XTb71!{du4I6izvD}xD=NiqmgpMokw`*6}^F%ZvjY$oU{TnVe(me=> zSS`JLX7sHRdZv$rwu?pc9(Xs{>uybhvg7M2>w=`n-><8}6Psrq``@5E#y!ky)HSo# zw1clGt+C4>M~~IO>T;0oH9)M@oTB#j<=nG4A?4Pcp=f}gG@P_yI)XpZSde5^40si) z8sP88iYNzSIg|$EWrTOoR-k4(CJ#~#QA`FWuarI_6tX|LJ5dV<3qu^Z zsH(VEcS`;BU_2^D!lTzKvrypOyLpLa&6|kach39YQdi0BGF}7S@8hbaFAZDOSh#2% zb~@2Q#v-T9{u<#?M%rdBd|#M`C{Ekhd^24vbaaTRBw>Z2h(xy-_ZP;`I7#}h4-FQe z0Mw&E7H+)&$i($_l3lR=z>|mKHKKu-n_ibM5*v7 zmN+GWhPez*#Y0X%^t@Hqzwm4dyd=ITi&2w}KZpO!F62T>KrsbKci8utIFCic1|UQp z-TUa3p!YtiD8M8JoLR%EMg%8xj<3CbJW1XK4|peoD8UV3*!~DTM$~Dv%p0$2gb17XK)_J zWyGbw)lvQ1DDbxpKdSoru!$vdf7n-nD2+hIqAahd%>=*#J{7ti0^f_1{qh{7RkB;M z+B%gd`~JGb626F4fsR3Ri9du%JN(MlB%?C3rwmD++B|!dDFPd-C$eI zD2$~;RwV`fm&y3W%(V(%k$k;fwUl>b!wyw96?SLKbm^SBv!nEqI;!)uu%&eww&v`U zqTy6Yv@vsYA8hdn`UTo}z2>y@7O!RA$@3OTtwlX^j>>;Ck)Q3y#&m(sInQkzhPZ&X zViC?hvS6~EE`7=GvXvhvTa#cNn!<&(nBB{eTasHaf*`U{xT{VJpq#)B@_(8 zK1^8>oCqMSdt4PIXc2Q>C0w0Xq%l#m&ZpwAM7jkAo*Q5ZrW{ zc)1+yQyu?%3a z>xLFb%!?ckn{vtkD$8e$XTh^`SDz&`3V4iQXy8gg@(-b=4|9MO05u@jslgR3P#Qx+ zON9uOWdXWrnR?E%+=%DH(6CcxdR7F8PvLe02S5r2c>4eDf&Wi{qJIf2db~JrqTSEv zcBaD{{yv+Y;30S&aZB6`(EsV%0!tO7t-@GOQqy{}8^YQbG?9>b?a)s)O3&PFu>BCE z*Ne2RAnM8`N`32URIi*wPwVB*@L{=+mw!0R+vt0GhXh{&IvnSrx>0Ck@4i%1_Zo*3Ru6X-Bb?MwCZOWXrk>(qyx!C7PFveLPB}$PY&OS2vyPwwjo)Xp zQcG?Of~*a3YpOEk+P6;P>wh{KR;pQY!%%7#z1KIcLH;n zK#BemIcX7o(0!94JgJU5szYShN#CZeVYCEDsLYClzaJroBRVGiQ7EPGHWe}>5@N%u z>-GIhW{?3I%p|VNuYJ2e)n~9}c{Vdmro&Z_2{q%%L;IW?6AAEp!7|Ih>}7NDAVF|2{{}nP{+YqdOA3h+ZpEQSaPgCw`MQFlrigo9 z)1dCdku@|V6Q>*+kaIUM<`zfY5V`>73}=nNOubrg0mj`)IWvDfWf)%>M_^kfSmc?n zOZL5p{ror3>mM{~9GKi`>+AqLc#h9Cru6!~fz< z@`x_hyvpSRwdmtjSGsz9vPjE1M+K4sX)!w1!U*kx-esY9OG-Mb8to8qeDc*u0n1_( z328-l(gSIs_fEf(~W`f+TMA-edO*T|rU$vuGxTmL_}(tmH~gb_#dmrem~F1!iY zkf>LKFsW&LHsp8OLqM?8c=RIQX`_s9z1a5)4+oM@KLjbFMx3G%Lgn|c4PVB#WeyiN zWejQ7oiclerbWl5k&^%6Liedkh{9A^cg-aAh54I`@Qt{Id@oQ25OqdJh63z^(jSm$ zwGV0%S+0+kAVEObJ4mF*q8%v}N`HGZ88MFY>OcdJ>AQ&{+(Mpm6jTBTulL7) znmU4-28^OXt0qsz!ph0+!-3553_!`+u>_P3zc42M6?gK#dhLIoOR3ARzZdr~uG1R@ z-qeqRetCMs;c^NtQn(fe@&1cW8Z=)LPOFqVbH3y0sQO!WxLdVu(_Q_uClKJ|F2NV+ zgj4@}jX0H(_Yr^=^YRC`C2Le$^*s>XA*({c+XD-LN;Tc@WiqURL97>jc$|WCMTbem z2IZ<<59T`ZXHnr+zP2!C>~kJyJk$2QR|A=6F!saIN-0PcKx;*(134dE;C2)*)lCo& zC0P3Uv*!HBT#G{Bs-);3e1aB(CH`Uld=z(E@a1>U^;Wr-%Kg&9?zFGVZf9*E#KDXK zKLIV|jm9AA;8(FU1nOeZol~TjOis(hW0yog#C9@VVud%6i&Bb`3ojwO!$u&K%u)Cd z2V`Hwejwi79=3g-23bM8Eg-gx6L2mOEQ?Ux#RBAwXk0%;{|SK8+zOm<$PccY+seIF z)IsseEk4J~yKDR3Ks^Pp9yK4hO#)tNihb4mn7p`IuRJFN{A0X1ysFx&0H~Y+K#W^z z1L}>X?2nXGDvc0OiB0ZKg)#n%G3P(1PQ#V~iu@+kZzZN;!>B!ZO|T+x97(t0OSMa_ z-)aKRzG>W)y1z`2Ic$eBG7e8)+Be!-W3tUn7mtZSkP4%Yi5geI0>fx#oW#x^s-1Dj zalt{U)P>5AzGtEge%>RSJDndiHK&PtX0a)IV`Lb+_|14AmDqsP$>NjP)CQU@>!`YWsc~^$uBI z?=XlFa$7a%OI0;rEN6T+JJjxnK=d60Ghg2;h@F5sl^~b%s%M^7ZyuQ|WPZqDsJ|g9 z$%$EkCx6K!WdMofK0>ZSS%SSdfuPq%QV*QvV%R8HSlIu+Ao?`YbAilgPpb>L*!XWJCZdA zFxBeKdoCA?g_9b!W*~AOL6u1L!FRO)@vd3&a+voV#@O(>E9~hhKlI0BYY!E^&bS8?2SVWHi zGo$dJ{oSfsEe=e=7ou^MZ!UudzOjvDPwp8eFCUyxyW$y3vp*O{B7HIAq2b|2xuB3nwLm6Eybj!cucMsat6>sfw5RM*N=M<@DYA1IgpVrlgI{e|I zto_4BIe*kg&)M1}z_NFl=3Ugo#{L0MChXA>{x|8R_rhqFy{s(TD7@(zBe6ZGq4sZ= zoC2`FC2fQhf})*zKYI{kq<_wT~X1cR~T!)$!hMpa_sw_WwmY3k@6V8<#c}aGJdi9A@teV6}e9>;IYG|5rbG{)T8O zd()|Z#%kSmIdhw`_tz=FCH(3JQI`JlQX0BbX8bF}$)jzW<}TZhRw^?%0aRFlt8@nV7wqzL6#m=L?0*W|j4*Eq0pq&g=k~h&$H2f|d=9L- zIf1bE0wz<*M29tiZd~|%haXilo>A9ZmmmmBqQN6xx(&B^WHc`XHh(CUPWYUMw; zDm>uTW=dEKwgWfMs0whw0#iOv=5ZEA0-A=h{TNo3P>E1KWM{o&NhD7-hnuN29bLB; zHoqfUSfZpOB2ZqnQ65s?HozETiS^v5wbs?nTPmqL!$YQzr}A2z;vxipa=3n?t6b&PayC{X<&&)vwL`fO)P+HEsUksBf> zC}P8PNo8h{RGe7BvbY1+aq=ti+(nhtfOlY|9YmRFar&^l!DtZUZ2vX)dZgdKT57@m zvi$mwz)=YO&&7%QDT*Zgs@aG^h|2Qn^=*~Ss@B$no`G0J#xdHIXwl5RbWJT-x)w8# zld@gYdKd8#R+(r-j@WtM%k&)k0(N;{79%QcQ;h(>PwFr$>G?G7XPM}sAV4hE6ZR;7>05 zNaQrdL4z5^r1C(%h=2=4XpOc4-o!U}2fT5j3K))k9j4E}79krYc(BUry^qlPlh~^| zM;)qf7!L>V@+*cxTvoZ>Du$9)`M);E3+RHIte>s7ChEr>xI1dcSbeJR+%n(t0YB~r zoZHl_7WQU|YH5)#?|{^X`RhAD;Gz=27dipbr`4J0C=5aexA_n7K)tpdSX=@wR=#hb z0nFf4ATeStOo*cfp1V}IMe6tsRx9vRl=vK_9g?1W@DwePyfu%V%I$bDyi#|NS$xJ*1JDPXp#6f4nJ7j@-Gr+eD`uTR6lfVZLL{ zmCyBZI2q`*^jwL$=UY!x(4ExlnBP(fYV(ElgcX#0(=diuVm@DN36xw8fK~dk{R95= zsE3%$so*EOr@D~rRvpL3QO++PYF0D4)c?-pg`dz7!}|@yYB6c#8PVuB-?l6mxSS)q zFU>f-t}6`5#4^)_k;BM$m-#w%aaVXLAYFQ~wcuz`d9#+Idw?voJmMe>A8vv%ZPc}w z!0EK{I@aASL1{~#uuoyIMsOvOX_NwB%}WaJS%R&07Yyv{=MNkB3N5WRrPf$@ z((VG%CL0nOD;+J})f82*Uu%^zJb7VDK zdRTg4CM%m{M}cT*VS)j3(N{FHGqL!7%rs@f6>cgvKKk};K3-6^c8U8V+i|rcRBM0Y zkSD8#^)P-*Z|yALa#B1>vn=!DpNAr7E(H|a#wnt|QQ$N?(VzdM=$72_Z5H$M!FmWu%BK-DT<*Cd}?bEuj>j9~p1noe|)0{*o{xpPB zsez7$d?OF!ifx6bc8sOqX^%Y&E!0y5f}5kw^C_2X0f`>#x|*=7rK2}|S(+*hy*g#i zI^AE=iaQ=c;2}jZKlGcLt8ngp@l-4~T+9s4c%eqp^HjZsBvap*J}TX^ zC1wl<1;nsnr{||GAD)30XM+N1j&aQx5!;47S7e@)-fK~(=Sio~WyKs;HH3!{E%0>Q zs5o9;=GH=6fcseAan84H($cZVL@@g!4C0YxB5t3bNK9TzLN#Tn6#=aEpCpx6PBtjVRIV#g> zp<0>QVRUGJ_P;aGD4sq_PiC4@XA>cgZl{W%OnUY)Z4m@sy585CR`wO7gU&Rj`W8Jw zU5x}SO-8n{WJP#>%!VxcD$Y^5y_XP_E(?=cp|vTp<Wbt@wp!-ZAtmhklGapse#l&Pa(Lf{ExV~9*CPW(PbDI z?&z7gc+bC50ze9Vn(W6RWPir*naH*1tOCLd zcqtm;Sjj3t4U)D`;%%gtvl@AAFa$Rk3Bo<&SHz+Me0rgOMEyB;^ykoEbXn*F@WD@u zfc6m}EdZRJ;g7fdaeBZ3*MA%U2KG;9SN#V1>->M@4L%FT`Lz453&>*@_1b1Y2tjR* zzSb7TPr06mZE<#;6TjHHAlS2V=m?g4-m=k~jt;pjbr~}7jfd5$y8NBj3tI%X zvRr*F|4_y>LM`Y7-PtDN;&Jfv+;?3n7fs}7iyG+r_g zp=%j>dfVFQAzg*$sVoKiY|x}km7rUVcrSFzdR*5y&C7I>8>&fCo*xPmRrV8)Q&#e} z*ugOr_8E9Rwk+kRV|QpNsOnF9uYq9W+I}3i?fOB$%vN)GZ1LbZS#^s#48{B4oBOUs zE)#FAd|Yewfa5!N=`Z!w30n-NNm7-p2t*%Yu9FlIKJ2CVs2fel-l;TF!l24!oq3@* zje(v?a5jd!@V#*(x>HAHwqup8d5qoRQV zG4N0e0!e)0@j0EsceJd^|(}&L!;;7WR*dy_pp_JHXep2_rY?7DX5dmDSK<#wv=5uS!_4MZsq%>&x zr?~K1weKoJ@%A{xSo}3d+Rxx3ic{^jDZ(#GjxjWswC8j=HnGJ$of+imoIc4`?D%U| zAOLL(kjk~m4E2+(50->>oQZLo(#QwUWb zak(sw5*(%^n}vS%P*Y*ed^Em6^`~BhfZ9Q~4`}`$lc>jx%KGXOsriN)n0e zA27T?Z5ZggOZO}R8Ofs;h4w-l)1#-f1HeeTa9J?V{GC6T1fTfH>qxRBw!X8NzNK)? zb{Jt?Cb)+-wX?5@=WjqK$Y(R9p7jwg-%^T>R^f(q-pyOQ5C&9y8A)XAC>MidH^^2Q zm(u_e0OGGRhRCvJ>6&=blQN839cTBhW>WCX@m`;9tM+)?coF4{&7iFKuGf4Ohx3Q4)AaCr4fy$dTe*>lCkzGFk z<967X?t;WBoN=nlFieUj^|0 zky!6}V}q==B~7%H($Cat+apEk`$r}~&xtA!Ta11IPA$N@4a%YIV)TPSLq7?CI#<*I zc+Ag6lpH7)Am8%6jJn4Lx+PAF=HYN^07S@}{1~9G;;6s!v@ zm05F#3Hg!wy5M?@-#SNu2U;D%Arfh8zCJhJf-yeAh`4gs z3aHDq)N5`?GnV0aj6xTS zOsCpj(k0xVKhVO`LiIUWu9dFJCqY0pN7Y;Z2LHwHX0>~>B80XCmz0;(ML_#uUxy=5 z8VAmI$Nt|}NO04vT@p_FiDMQKuw^{z-SA&@IU(>8j%WX<)LMu=3})OT#QpTS5+yqV zq-3k?fa#^y|Jh#J+^-vNLdU65qWh3Nk`bikT;ay1_x@)C@L!|(AJ36q43GJJVh{Q@ z3TsZ^aO-E~7uN*>_tqu<&Ue5qRrx&4blANX&5ie-R4g(xzynAO)&GiQi24;nASkZ~ z*v{Rm?j%_9H>@uqo88Eo3!1U`d8M?$M=;VKqkiozal&P6)6I?Q8$*OS#oO|w%@ zErtUmxWXAUN1sJsZV*Z0$_h7q_vegof2g#FsRn3dx;}BnmOF^hA(-oO1#)baOW@wZ z@;(B8TUL00AA_BzjoWgJ4J*pLx)B-OzkO2{|Hh;Ut4fRF=P2rN%0=r72w&p5{fc3~?8ly;oi~kR!*FWXkAlDyy2=#>9dE}PD&l(FB#?5{(+ynwJG=6;N zk?}^2528bQddr$EhT(_sNtEd044~OtC-ABmU^pg6CLCMXwM=W^U;)S_avcX}pkJP6Sm^NaO(9ttS<;^F zQ-?v?J>erBvNV&VlsoaMpav|aLFvtiMdlv9(*O~{)U86N9wMjepFR!yKX=3wo=UCJHTxk&fmFJh|S6-RaGzPCTyCnn*uae1y^)|~k z-+4q^lp@#Du9?O%a;v@hRyN_meOzPm!nag2_uMK@U)Jm@Y@AVq(&WV^mXlj7Gn@a2 zCp)M~{r;Wn=%cN z7q(TDVP~$8&ai7B|@j@e{D-_+)HOJnvgmCF`WSu4a6d%tHyR6L6i# zFkkS?3Y4Bs$ESd6*A;5384B9(io=ad-EM!e+VjIa_zrFZE?j?BfIkB^?|it+xJL%Y zt+1b0_5W&TnIO>(p=W~kt{TEe-$KalIm*pD^!q5PCN#PpR*!C1Ey`HgoQ0Oiqt}OJ z_X+a7mNZ|~5e0U%iUY@IKivtE9WMd{qTCN2&fE!5zuX4EF~DTAUId_}Wae2gvK+Bm zg7^z&5o0po6GxSOAL*7^cPV=W@Z<}U29IcGJQrB8G-BowU8#l z_MMa?T2k0%(%L9-L}s8cX}8Wtug}@16hys)v^1LvQ0jX3eX{efy?@N?I$dO^$4>$7 zq2i;JLnbjOSReWwI4J6u=hfxOK{-WOq;e9uZj6o@GaTybF}CdA7#y!0%EFl2O-vj| z>%6=a5mv4evVi46IbcUh1Na$A{(VzbHIUYnJb)GHSXLMhTvLmA^8o(oaO}eyf79s4 zu~1c0kc;zL!~j!7vsAE$e!v~5aFBJs>1-aY>mzE}fhI4~!c}FrwDr`3pFA_?nN{Wd1rXanQd?EPsyp)j%31!v?5eMaxP5712TyQ z?aA}f87B(ryq|^cB4kIXX;+oOs0eo`$i;fzv)oSATNT5}fL8Dq^V=p*0p%Vd?>~y< z7F$(^8ol6R-W(n*I+TXNw}&1C>n+FK`Z%?|tdezgW2RL;tMWei=P2BOGy_w!=xK`h z=PXa0>u3>&n4Uh06!Hzq!chUvOa~K%Jcb zQ0fi%hFt*#axhcd_d}41J$ki>xt(eC**Kn3vcZ}IY~^!New_Ak#g343%|XB(`o^$|-vPpUUm$tFbS4Y)67 zXvjB>aa-Z_#9I_Y%%5cHjySzWVD;VSyHmUV#Sv{vR1+tjUJ4irqwIbc;Qza!y{idG z-EGMH2CA?vG=W52T}1(jWNos0B!$zT zdE`59Ngyo#6T04-^AG5{1+49Bjzqb}h-DS^@Is5|X0%%nvXIQSVSpuje@Us!psVzj z3S&Z)S?mkeyN|(!?F-Fcj;$7vXpQp1mcEmSb4tAROxa|`5AUOTF34HHy_Z8CrIUVHOIn^S2HT5~mEVg6Dk@}s zq%;e{#2wsi!)@X6_T|Vuug&SDkRX-AUqB>4D9oUgM0yz_aKOd8mBEpEIuvE@P)uoq?@ZMIt*yRd@NvdBgWlY&WN3jT$Rp8} zYk@B=0DOB1d?{jH>HNX5tj^!+7SlICQQL}Ir|YOuf9(3HQ-h0zT*`~Cs81!J3omq< z8`RSgM4&Vu@v~5HbN9k4YwmfK9+i71HcJ_@Jbq99M6!vwOG8zegCWsjh}9`{yIg)6spgtJCXm4}^O+3HkX z*HJk!I=));i=8=<4T805NQv&gR@YM|V_Vnl7T&P-YIe(Hl^%U#17q@4EKpgNi!L2` zEc_%RgaGL!zQ1T4uZeN0O6BgAVmFS`+(ND+=l5|V#V4)8y@+wcWHXxx=#hm*x_~v_ z(=%MAjg)0NV60S4Tk$}{l2UX~ASh)*xmrK&wJk9*Z%NH-o17qb z>#RY)5;Qcb^miq%VOPmef9{KWut zaZ|z8tx>RA|05r`jK3E8c26Qp#TQgaYY^~Dh47!_i+{OYO*MHexZ><+?`l)I_`Fz> zqcScUi8zGVc@o#|%+hxC{CQ2vZgtcPEdMWUe6$bNEUu-(6^LJNtD@d8m6HLMUi9@r zT%yHo3iwH~n-3umWbYWDINx=>ERn!wU(?^er2G^`$n(Ok``sb_t1RAi65<_AQ5`#P^Vb z?;+AnVPH(1bGy~Wg{URWk7w@2aDbQb&PfH{Y1EbESuP_zss&^X?7{jTSM-Vow0V1( zuOmXzR1!lg(!fA}L7wVzZvmSCmrTDZ#{nMZrAeGwNHMX=nkHB*wuq@UW8=2b;x0p?bT4TCIZqT5NaN71v9+Y zBFK?8atxMK>><$Gh5fLCm%?fG6b3)O1_e-zd~)%bg$2BBHz)=3HENiSMS z*Aj#+pkf^Cn@HjTsOy(QyVle2#M!5RZQd_>TU76i{GHb+ZX z%?y*4C7ciAu$RUkk{gR;W-+f3Gi2L}O3SA`rp|70n!tKE^kxtwsydc5WVl7|Zf$gC?@wApN1~B)1 z@%1p1Jj5HdlGHJu<(^~hLL#5(RtEdO?%3g8^`#XaNV&Z1E}T4EP11fS+Y!BfBr?nV z8o^`H(LdVjqU6(|jPFzR70xVA@Q$u?lV}d;B;AGFr1(AMC{LD4OSyebJ_a3O7-4!F430hpJ?U8qQIG$gpt!fOL zN#o20n(J|l&b$J}%@B#lvU#;xr#){<>W@x-A_%*R1~_GmGenKGoMKf8e~g(tjXf&T;` z0-3wtabJ%xye$I6wX?8DRds#QGMFD*xHsHif4Q_O5D~{w{^xAtf3p35dq(n|Spqg_=1g4TgyPJ7Q56>A1)r)y07OIFE>{%} zlhJ05o&GWnB0luGRp^cj;GJXuvBXalXc>Up`3A0b#k@HK-yI5lFB1CY`CdULhWg)+ z&+q)a@*xRTi??VXT-s$70sewxa$Fd>KD{O^%W~>>HJU~sRHFF!_J?`x*mh}CH`&?G zK9IH_eIRL?vS z7_%(G9!e;k;PGyN*;7FuQke1BGV`20i&Z%B;LOuT@><^xvg3t4QMfQ`RmhH@?Je*D zaAf7w6%;)^$6UJH?Sb?OBEzw0mZINQGh`j2M!G8oWYNG0eV+q8}`Y9 z(uwO@6OOi?wxmcCic$-aQ*IMU;@@sHd(pxnSkoHL)ZAHnDAS5Z^r?i32HmUza-pg7 z7atAYN8Opk+=4Inf)0u?LrY9z;wiL=vWI#>=qFC{d_#>>{Tf`_^BFfb5~K>(h=xaC zm}Ng?yOu`u+7hs3vk)6bSnjp)!tP9Dyjf32>85w+7VBbPmTqMb$Q(w}u>ZR7(AKc# zojAPVW9K7FiBm|dO2wh-z- z`8tGyL0`L=_d^XVpTA;^;lS0zOl@8W6u>F3XjC^gXuDX(n(Y#gNfVJGj}S-_llm6E zE;jd5UFu&s>&0&N$qinG^$HLemC0e}otjCQkyubbfSvtts4yY|e{=>-H9jq{tx1!W zvktXMpWAF;Wh)t3Q2oI63=w`~t3xlX*T>IROHafXG0kr14b|&SdJ#nU$HL?fR`Jk0 zfwE$AYuxhm*iObOTN~bYEKwg_guoYt7ky^+RZm62!;`Z1T)`w@yYC+YS?f?B{jHKTgsr3L<6ljN{@CJk?o49{9pncqF8>?8i=lM+e;++}5_zAvI-%BX(`S7E& z>mQ0UdbK zAXsVb2OS;vOTo_5|H0l{K-IN$*}}NHyC*mVcMG22E+M$POVHr%PLSa4?hqUT!9Br( zLvTO&H`hA3-|hZxcfanx-y5BgG4`olwfEta*IaYW)u&Zc6*XU1HpbZdaFbPhN#Z}R z0Bv^gq(lE{&Ii3MMwR)pK+wD0QUgix2dBIe*TwvTjKM}mGE+4@%D~MVb$n_w zZb-`beRX;^#mTLX&c;Nh&BiEhd_` z(U&ngd<<4N1K$l7RPJ+uJJps!Z7;=oLii($i4X&))HpS$B+5jc&IA95E6N7Bb}(a0 zTy>Z6!U5AQ+ooog#xxX!kUUTOsV89L+<==qBM01eY>u;8g@SR8rzuJ9^qa6sz;jqq z6o^_3nC~XtOZv7l)XkuLgOn4U4a$P2(I@9SAt-Coh)dwmTTEQOuL9|<49`_dT0d!J;Ec%OH`e&Y~MhiK$`U#0NnFS5lIpCJj zSYGnCp#I-`K0TJt;EWH@k2wKHu16QiY=C~J>=WTL@SB&U3g$B25+6Dw`jm_Gz$yD~ zPShe!8Wws2VThuyq@6gq8U{Qi88;r;ImNrs!W(0_(CI*`?USx-1kSTwbN4b?wle#? zqS3J~$dT8UQM2AGW(_hY=2fyjG#f7bb>q_!pv0y5BHpCpteZVxiM8a@{>B_!zdr6- z*iUVHV~aZon3afq2*8@n*NHhTHH_aZIlGFRC_KOu)A<|%yC9##?_kF*?>r-U`#cwt zxb=k#r18MOHmK6brWq=fz1p|hit8G7wve9jW}?0T^S^TiP^GMEq2m^zMyJY~?_mC* zyJCsL!t{hj+}VD2Fk0M<))e#@;g9lIS&NIdizJ`#o=<(0Igb9QGZNK|KbQ^I*;x16 zbLG%_d-!rH5pVgX9bPTU<$WQlYa|AX=R?`$U_-p!_4yShRH63}sA zJ^b;0ad{^brzP&^r71sjh9F1Q=Z8?148ER4<8_!9-F>DHmD=O?Zvj~)E&wzux1fQf zK1};nXX)`qStZ7v)?sDP1z|`T`CF;Ol_Zt6A<-zf8~V}$X$+}+9o57pIth_%RH|>f zk)F22cBa)r`Bw z!<_!`0?dZrZia6Oas)qg4yJ-pre4k97_t=!GIAc=biIIbF3{D6#~g9Tp{N)w zyQhcY;lG_+>?tNv%sqzdm$09rGK8G?HgL|q8SFq)RVPIjaaOK%j`k@A) zFf(F!U~dqTewcaR1D{I>0=LFeqX#D|nXgP;7c$9f@%F#+UW{9vAFA(UBMBXri{b-r z1iI?C?vEON(Lfpuz@M2*ANZH#K|-D-)Z z-@&*mPl&<-J_sWI_Gl-3W>wQyMeDgJO}Sqa6-5$oD~C^u>n?+s9X>;8AGk{Wyt&x;7?a z7SyZyc6KGCK8f0v<`k{?mGwDMCa;Gzry<{-V7kVKU%zlCjh@pY@)D9oT)Oh^1!@JOK*@ zUjJ7~hqdHR>YQx&1Jrw&3!&RzCPs;xgB5kf8O;z?O@%nOuG877`teXff=@MBR(CpG z-@%g9a^3IcMQ#9E{4wWgeMhCjB>9QRs?b4j2)sf&|d z9QZmM;k4U_Gy8e&BAeJ4yKlt;Q`;>`{@maD^%n-U%ejiU=MbAg!ACWl&R1hpg3Rrl zAjkTMA`Ez{xF>oIcbkiYH-=~6AKi8bb1YCr>)!)7pJa)yK%JI@`KiE%Mw)1Hy>vq| z+Tm>;*ptg5lM|f-wOZM9Ho8H@atKn+Wmv@a(=X`$nJ!V1+(X$Y!(m_L%AMbQ8IwC% zrOM>qf`3w1;(-)&LkwtF^w-XMy(TP&9naKdW(W_Jz7swjf%rmVe;VaJNZk(p9Srsx zp9Ot{e?J#4PJzbihZe0~dI?C3$y&5eNL0}7QOneNwAG+7PV_W`3!%_gj%|ux(Y|bc>4jnJ7DEaCr3ht6_x3hj9y8Hd7+9yK zI^aFH3y|oy0Ml+xx7wUyo!MH945!R!bu|=(Fx3OM^4w$*{zmf&NjkfD7)RnPyi)VS zCefEmz~`l82EUjf*8*%DAacg$0vKu~{UbMPzQW$1(+BG_Az`VR&qR6S&E+AJxBE#1 z??z_@a3GGY^qF`m3-~I)0_4nCCjtSr={^2Vy4fdn?I`>B_^RKjaiSG#Xe4=cEKsw|x->kA&-D~mf`@^v$&@-DQNaVJ zvvv*iFb;wOsK$MY4_T;JM?SwOPCN>?DxupJe+W6lb~B>lFWVq1;Emt2xG>sBhtGoE zl5MDcW|nU@kERf%;;)Hjp}d<(@=3=A8+or(-qnY4I7G&Mn}H>c8y_OvZ}!uxq}r0@ zWjBJ)3MOxOjNM+Qyo(2Gg7Tk+;JGCj%RD;L#6To$-mbEirD%*<8O*du88SWtq%dsm zK?%-{7gP7WxAy?O<9MfnP&v~}@Bv3V>lsuOiy=xe%{$_(V%CH|s~4sLw*(xwxST zGhze{$B8QQop7{#1vxuwd6P3bO`pfqg$GzQY$31=;*Bfs%PlV5PM}1E^~8#;GA0bO zT9=86#9qB*gQ5JqrTA*B{bMa)_C88vPjUDw67updp4@bFmJ=a;=;xWX2RKD63Wshs?H5J#(qP6zNB)v z*DtF ztvrWWJ(z?=IM8|?1E8icfLpElbyt&XcJkG}8Y1@cWf^74O-umwHTTU-@UAf7w3_av z>h`ZZasW>Hg-7l);RB4~P8UGQ*us}-%o(~lLZ06qpU?tUkBd|!v!DQ$V_OKVjk0`S z%PRwiYcBbKdML_=932LAEKyu=#Rmc4UBkMCi?TH2tV_Sf9=Ihk^e~)qbby^e?eXO; zCFK4(b(kNg9e0dTOIkNHL}q$jGH~fB^tlm!dc<|ko&^0Ci zc4DiQ1_ps7GL18DRsHfwEu33Cdph(XeJF=){1NOUGFc?GVPC!r{_*8PKa4*W-oNCX z>_30x-rsOH;s z9a8dp>l6X!&So$9*DaG5n1-;iHQ2!;VGiRQvtJioSZuOAf&}Y6

  • Kk77JDuprqD z9-G*b%xnpSu|90fJuc47(|}(3*~mL!3nv`9WUH$S(GtXdE8E!h~qMONnkG79P z)1S>d zY#W91al&gs`P?_v3b`0ba6VGH1234v#@}L_a#BB{|2YDqxtn`s+A-P!r*p0pvf+L6 zIEn?tw(6|)$NbA$;x3k>SdD;1Hs2;N({FCVs!&?U^KP8F}Do4xuDFs zFLeOiRXqwHTprz3^M&yjMAQ$*MH0?;yWe(Vren6pN{Ok?bF>@cfQ=22{Oyml^=cDhTxQ&~)FN^^V9>h5xE zk59J^r|51>1|fMTnFhA^_}0_Mx6S1nf1i76C_0JpP~2<;@|H;YSz(@jPSjo?|jOw zm$)pAG^*)`8l6x?ghPZOvMqR-d?>WEsMmVhF~MNtpAx$0;|@zHz&1zRF0ZxjiN7vS zstc!fCHXSl0mg>bWEE^0-RYwRUkOgW5R-Rmfa#fS5vUdxsA6HVNq*-XGKq|k8D5UBGvJRX;99W;8 z=z|f|n@5{c=SvXQFCq&6p-eDo;OwdGbGyb23MAGl(yy&=bojO;N{Iee5hBAIo8zYe zs2(@G`f|P!A9ayJP0a3tXCXcmtt3XK~ z7Fbx03Y{+)9+=C&g?s;w2tHovd9Pk-A3n#=b64YDcY2sU#xzQ#OrWInU#+tU%JH!` zF}M>lmGgOc~H+nX7nX3iuok%VON(SyKcWglQN^E$%W?soluC^&G|%ZP*`K z>dL)cN3DCvG0-`y3*BnAO*sE3+jv97`tHsg*g5Y20TI}M>8zp};Idf@ zT|WTgjjwD&@8wJ9uPqf?8oq&wE%_Caq*o5{6>ej{HuzA!nhOwo;ufu86y<{|?eUJp zQnAr?j@rftU6>@W1n8=wfVjtRi15DbkV@nxefLrX>W5g(+jO?iW@5!kws?u$8xJHl z^b+GB0RSM(ElRDy0##o_R2BGc#CC~%&wE}br-G4Bzl=ME(=2zQm zf{%%Y&v<0x!>#VOV*Q53hLuebEbW#9;pRUJ9#k}_?R#F81ia#fTk$7i^^c9sz+iRn z2fEH9Z~?A$)U$Xk#-uP<%^j=mj@abD3f_J1sAl#rQpmp_vj6|UV{m`QV^sdYTK-~5 z`-eO=GM*FFOQGMij~e!wPWx3`E$=vW>+oi|BCj>kU!t+yQ-8Jby14|)Vy5a)F``{+ zPRH*$eDI-r!;m!c6<;Pq@S7ehY*C*|eVcld3*0_kk*1!0uv{LID^aE-Ot~~obHs;` zYyBV-r6%Ir2`Ek~WO?QB`-{iLNmA=1$uEcAt5qq`i1c)rt$q9+%4nukD$epjiwBF9 zKLlTDkgUHMrdif2dA`PNf!vC_DX_EcmoP@ zio>CKg|horAS&L{(y_q&3R4_UGPPVGnar67+ZBZV4ie;>W($Il1m>kuabuqzwrrmX z)W;JmuoCnn0|j9Jr9g2SJ^hb&u#3Wq!T|c81Q;Y3!e1jSkLP<@`1O)i-9D2rqY=J$ z)&2eq+Y_j#u$~IgO^jZ028H>KI;JmVYV#10e<}ri~&SA;d|*FK{pzR?PCKM z7As@JxH9|kA`ZE)CxOFaMbxbWBT%LRu-B>4A|PRQ_#+Ms=-6jVm`Tl)$s{4Dpa8dX zSf0|$B)f&at)8Z#5f&a3fgu6uY&Zsn*YICkn_{G$c}toV167s!R8XzQ#yuZ^(0acN zmw)JEf2SY*jWXcKV|83E$Iu_78JM2!Y>)>x6^bL-iB^@+U-%|Dd1dNb(N`G_1dracB9Hu)anb z0Lh2`M?qb{_L`00+JOEVOxoB`Mj>4`a!`A0TwKa}AGIm~xKLJGiu ztylaO2NGDz|3Wk7mwQqkO0$9ur|?co&arWP;kiVuD2Oy+68#=gDo)w3V?{&k1*_d^ z(%20{^xGrRbKG|W^WId-2M0K-5{dI;cEHZb6q0)016BWi568@!aY2#4iJXEXiaD7Y zzyA%Ahw{NulK5wmZ#g|Jd^Y`VP?+OdU{<*#v{mExHvoTr$4;%?NX}=yWa>uf9e0vgbg z`8y`O|7;nE`jx=)Zy~RGYC^I`g;yZ;B0ypwXG1ecNMB%+`j_<6fA+)vl>c9Grc{3m zn%y*^{S>uwO$}=!wc`H~1qD@f(U(C{A%Ckb7GLQrP6Sy@OA{IG&cgYZv%{B+qY7o# zl=?<`VOjLI)ICw=ZqA6UTOW`$F5Njn7_*ySfvKP>QWl!QdsJeK3R$f-No&xuBP>%&&=B z=V}fW9U{m`fGzN%f!ITuK>Q1=`9? z{^XetCOF6S0D0tdTm-m;w)~W+S9v;<6Re;u5oVaAVxE8;GWM>-{i7To&8~rGr^JAhEZlB6x&!G$)cJZAs_Lr8k{J5uY zHQr%s1TPKp3_SN~vFK9~ja1tJH36io9BIWROJ3)#^9HrXDp`Asqd4wm7R3z5sEi5d z+h4W>;A6kX*%bfv)S_gXruDZL``}gR?-?gFklgMG(?@C>2QF zMz(K@*CCtiQ#S}tFZxUCQ;)h zN%kx*dfwC$ra@JiqPw_}9_bce!bZ`Kq?UTnI*%>?H8aK8+in|@eNUSOqQF%tp6x&| zXpU*c=gatsF3ITow5$uV_K-^{8XpEZ)ml(DR$%3Pzrw|NeUoh@p?@X@}s2U3Gk^_vVI2xd6jp5Bk#Np;|EZi zn@eDI>Q3#--MvA!ca!`b?CcQ0^Zby133jgw&^PNFK~MnE1Q7a1dlo60$ON{m zqKA3FYA;vP0YEMHciMoTtj`IS`%jN5!1AqkBKh_!Qg5$t17MT?doY zk6+WTZCwS`r}wwCVrajF)7WfC%(XiD2zUEtF1s7+>yhTRRJ;QPU2f8j#uen&W1nJGgG$4x3D}V9}CFb!4=(ijBpzdIhkF(G{O8mX08o;pr zA#L`<=l@LJ5U9)l_wO+GsUioMM~A=>1`=R*5zM^zW$pa=mQWP{EoH6zT;iu&|6Ahc zD*6xB$74hMQOzGarzmS?oHUibo<6t5vrgOE1RQ0#3@i)Eyi7qt=eobzseGA{rgO{H zS@V3{HUu7{ffiGwQd!aR1@mc23B_h3uti^&)crw%D)$)50!g$B%^h$7vgg>P8Ne|b z5WvRu2r&05S(GjjHK%_bM9Qhx>aCmvmNgm%wnI}vV*OmGR=Aj#;rYH*+;=eR7y3Rc z)dN{qL2&r547o2V8ebZDal%A?nyy4jM&`|YBemQ(JptYFSC;nw%kTX+z)MWQKhu3m z|5NbN-#FI)aavXrtdm@-lfMN$M)q!?7gDNz(^)%$<@dBc`D3`N@egn}ch8jJ&;D=V?FpNpvX@k{6qHe8hF>AHYg& z(Jp~^IashlZO~Vi2`S%=-Cbd#?SM9W(h#R+W+pvL6HF|PjmXU|FlTc6Ov`N0QuV-U z77&FInA6rR1TaOazFm|hwKz%8kcd7V`v7n^A}-hK%^>;iYz9a@e14S)DXo%8Mk}jM zqFLdhRlXsyc=6wIuKLfO%l^I3|ED~I0A@MGt*%OhKhTZXGAXalG&>)oU)OE?LahBDQF_q z&1C)=k>Aw%OvK-J+mb%xC*(1O)I956pf_y!S=@q3FNyn7QD} zdi2d5z?JF{x+9>;hW_z2kC|EjTIPT73;$n!?9Y`6dAJJDMzdO(?>4@JRp+9U#r|0CuRoZ_U z@4y)TY5x2vL6Z$k4nGtIhW`(#|9$k21?hjQ>DSfcf4jtgcb5=#Uw`Yf@%#4by)Uzy zwtQP-YkOO39QB(Zs2lhFk8jj}I4FXDUqCRnF>-WrFxIzz{A6ojfxyB>_KXbpK*rC{ zEMactWbD8!VWsb6EM{zIYh=tUV{BvUWJboy&L$}M+k;xQV|6d0RvS=jqP8|p#x_olWWQ9U60?fCoiVe5zNs;@ zlCh($vxA|rBT!1g!PZdO*ojP=SwT#Kj9JCl&54Xz+8QYK{I{#MSfg96vOBd$NxF1~*pF@g2RVrrP_BXitX$EE=hI zipfr?gf=qkNuveu@lVAct}Lm|wYcQ0gtf@YLZd&QZC(_6-I_vCbGng|lX;VvQW8Qe zNp_uD`|`)sDn5IwHyg3NZ?WtQb}Ha&#nQ39VVM|)C-nbOafXN5yM#CXf7#A@nSPK;lu*n0>Xmq?#xgwrG&5`*c3O)Kw2|2mYmr4D(oS6 zpQQBb<+##|&T_OG`OUf*BxzH`eZgyq3bO63fOowR?}d~x%Xk1YNI- zA^3tN*JNPFP(p$u#EBzh)B?@i0u6tLY;uN-wNxapSj0%hUrOD7unZ-=Fq3pX zGS0bY_=#senCL5-b1Bn_tZPzF4NNiU^zE}2if811iETG_XDf{IciwwS)NnOlUb_)y zp&F@D%H2RcW2s6%C+MkR1ujeZjWX(eK>Jh%IPKYP#1s_uRgtXOJ8H3#gy<=A^$R@$ za~Vv^DugW4V=^~G28byt#P87K8}4>@p5PT-?4NBB(>&8_GHljk((A^Qw2a)d+V)5q zicG66y52fit5p#}mC>v_wYN`}sDDTEIjB2^+HytU=3equyQlF8MWMSmP}A9o71ejI zS)Lk0o;Q{zr@L~$Kll8kN-3pw_5d!xN-hcg`PdBYJ*9_KqxkC})k8V+>){r$B+61` zjFp1(C;G8rB{S7^f{YFg2IAKU9m%EGBdszharJZstEyJnUAlA(0~UEilEKcRh>P2C z`y;Gb&c!n)F(}(iIZNu#3ZY;2KAc^vXO~caj=O+qX81<`CD7b|cbydN=*Gs4&ON|N z{9(5C_1O*6`Vn`a_G<>^*03}h-aNfoxD`;WsV`W8Z6u>Hd!1mbhi_X`Q{=V5 z(X>!fg5P{C9`bNX(_`V$IE=dr){tsgQ8lw?T|dr&|E1G4vjiI% z%P;e>An@VnTT#wCRv@HDiG7<0fh_bVDG{Dg z{dBJdL1aW?L;@Y?2^v4>NG3=#&vYv%Y_Sb(U`+c#n)+&_b;~~ zPPZUln&IV~=4~i(wgUdE@8cCY>#<9~mLe*fRA;sz7$iZ2UrZZ=A=_JHOsk+pV$D+( z4S^9PFHD%xh4dS%v8NqOc$CBj%}ybQK-X44q$GB|)l3FwXQ;~gq=JTwSZ2nKFT9~? zypdXSa!_-Ew18G>6+%mBkc`Y?LXU0_wE!#N)lX_y#kINV=7($8YFF=6o;{}qiE zmv?E)M$1#38B`r~IN6tJy}9mtm)e@i^22ZxMOiH^7G1Wvx|2ukZAr6-WfrULm+4o6 zrFZSg4;3b@Hnn|l8(%Vlc19U}?#?724A|e0M3UYpWy{yjeM%|z8FzUuIrP!U^+H{+ z#P4}o=5%VFHwI3I;oylSi*D%VLDa34LpaIQrt0V!5PUG7oeKQWiPT4KecMbkk3TvN zPxga$+|jKHZy|vPwd>yJ5z-3JF*-QS^QgB9j8R&JC#D@3CvOYQaLW4vYgG1~zRsek zj`wT2$9g>XvvD4CjIxPy8awkMy$PK3?6C{kqYHCy5l7s*e#QG_h@;`d|^= zcn#s5NK-SEXYxvZB&%Ze#D20H0WAw;dgjT~HV%%a6v1%X>T}lX9JW@?jNOru4~xjb z1^C~oKggTcL0i!rEg*foc&+w&u7Is|HbiMd;>G$swC~A%<^b8K5I@r<3*=;-TqX-~ z;xn*~jm$o>2t+g@;ZuBQqs z0|xp&=ro&JP4@5ZDPI!YJtp|Szk4lba-CAVN{uKz|88RfY7L$qPko@6fW&=xjsll9 zEsQ^z+RR1YiA$HS!VPCkapRrW!B_jfaOgDOR3fB`o`GZ*D`0vG8oVBaaJ*kWPJwb zwYO&H7;-n)nt;`G=GXnk#4>u{C~kquwQJ3-nf4WzE-kjVk=W$!Y6hmTE8K0FbKfqQ zhp(p)$|j>QFAn!NB)+vtL3^6SF2=eSxWC46e>?ptk)%loN}w`+dw~}^D%9dq$RonQ zi8kDYa+9Y4o&MaF!SacJI5(BRaXhVd;Y7;HCija2D1l>TT5akBf?5W7UvdT+4-;y` zdbxSL%vS~^Bd8{+IW4Fsja=W5x~O)VGe_rm6%DQSj9wtpFh`%if^qNo0BcW|%Ut`Z z@ssV?;3?%_EJ<8{u_Qgt`u|gxB-Y2H#6LeXu(PrLuq4$d=|nF+E=f1o9eKDi?>^k5 zwSq%DhX}&ZD^-0W)?H;zp87Or>ZtPb+$JKdzrd)P>Jl0$sgPiU?zW_;=z)BjWeVN` zRHhEB`O`3S!=)~>xh~YF9%HIgp!{K2)lP>`p^g|k6<#A>mDJAkH+GT`kP9(B`3eUH z#p_I_L{$j)mO`=1WDEC>K(Qy4KkqFTV<%I{Su=tlP^KkRPKqo}iliOtR~YV(F*YnR zHk7LQlvwl0cwxt4VJFV2N{Le=30Z9f=JUs(Cc1@hbl}LCG!x%yMzpAzFeuYEDw8-Wb1^CdP+(Zt-pAo9jz@&BVn!g& z+^AW9%6Uz9GUsIAt@Z)?#&Yr{E3!o)f~F2Nl_75lAEri zzoS`(X*Fzn;ZGx`e2dZNo+T4po8!pC zWL2-FwH9;1kn!p&C>gh+A{3Ke*b@%90mu98SQvM?9PJnkom>}0B z##?5!xx3Bo3t5KmjPwv!2m4J^D}^Du5kD{SA8x z8FyZ?)rT*Ps&c&&AJhoY&0TtTu-nBdRTQXYf?b;l3)yS(6p{VE@ufW@(HKTUxbO>l z+oDg{wy|QCAIk{DQp~)g$y)S#CJ%7^WvXn}sokl`{RPGDqo>*`%3)1YuLwcfKLU9K> zu1E$6`4arAVVRq)UV*>`5M3YA*WE-t>AD$hT7o9?25 z1k<5g4<~S3TyIeW!_aywo)e~(ZG3qWX|U#?LBQ2wg;G!uZmM{zVS%_lP949!YsGWb zPMiKwZ#g)0GkKH6ufFLE?%EO#R~gdx_ht5uG-FoviQn4wZF$^5Bk3M17~YU`z250M zg%k$r8!)lx+XV(+CP!2e+xP3YAGRj6-9*0_S7vW|2^>wtfb!m;mj^N0z~M7_i*3No zMx>IM#dU2lN>oO0lqFr-v1)m26kdMAYWPMd!VRgj0UJj$B}v6zN!Oc*uL`-lJ#TU@V{7%c>ZxU`enlZAG;d;2EhH>xFr|Mj{sJr>WahrXL#+~ zv<~L3{Y)`|)uPKCMEI$^i_C^F{bQAQ z$tD_>N}f0x<6$C|hOaV;RAK}(!{+~fG_#Hi=DrDT@k`#=M1(HUf)k&W^M)E93pLVPnXVxyL9f~%UXd1to?X{Wi@%eSG{CfPq}{qiwyhW zvYpldY41R4c$Ywv`;{Lfqpp;iPSa8xB6;1X!qZS~oV$C4sk-42h=9%dJZoA1DZ*Wx z3f*I7AsE6Sbxh8yE^4P$zabBjGS6dqtYGgdi1B!5Eh38!BOl2yy3gAIf}iclSL2KA zx2&(Vyh9jfW0wfR*X>5fzh_cQ$Eq8_zNaf6yuq{~RqIGG8~AaNgOgWz}g zXa>?s#A3+R)qO{?tVE%mG(3ByfpE~gIHL*edE5$C#gd%}t(S&oaFWLN6e%C3SCZL& zqr>psoNc=Cn%~>!wb}6A+jS*Vly)Oi4J)j=?XIIq?8|28w`a~VRwRN#4(K^Nn6!IS zy49`&cr=4;`zs?U;f$^UQS3HXEE>0^R2c&x!-+Q}nKW^S6&rpTqn-QB*=wEE1AKy_ z$r4AfClp3Yo}b=ag@-9L4CD_am?Jr>M7VBpwOwVHxT-{syG=~*m7LXT4?s4h;rYKA zM2*QQ>jJ_f*+zc1{$MMVhhyw$gvmXHt)?dNn{|Y?%Ka6Xz z{szSS+ryTX^Cw)RU2DlE1g)|~9(c$XuB2m!I+t8AwZ7JkN~xMW*>+DoX&B{P zF?x!2{50^|z_*+RoyI<}UeRdmj3AgQL3=W6n<3IVtxZWmiQPT@?PSA84*DFK{6)-d zm3Z5ORH%v@qJmLrNsL)8nSe!B{UXjpix?giok2-@Qf7p53nG9bF>kbv7lVmHqb%-O zv2TvX6X{w`o|kB7rBvF(5|&E7V)W7}`j$!|eRR?(*t@IEm> z3K~fq_|wTX|VPI2=x^gT4~DXf=H@yJdVW6nOQEnp?^fLtC^^H6>%dgMeT-oYK5u&Xvc9 zO7lvNdoY2Pu8TthTH5T1YKf-&38b*LP&I0iPwIW~L_Q6o?4`5PsZxh#*vQxYmhT;$ zxOrnk%PFIz)bDq`wv82td3iW8k>Z=4jmPJv2a6{^uzxpnm>&LK2%{l2uaYw2vtI5r zsdOW^JR9b(Dl13ckJ>6fVk6ML>Fj*R)VfgieMit5yOBjPplmJb=F_gn#f^FO62Dc} zZ0SM6o7c7xk^R_<^?tYyrdpQAD&iNKI*O%}iixHA#Tnmo!w!>7F5Im+-Yn_k zfM7Ye&95tCea@HWAK*_iQsBq?W=&r#>b+pL$!l*h`$Awa>K4m|^sLog$-D5D*Jz7D4v!j!>9l}bMW1b%$jCK7@=^7sAQYGo)G7#0P^3^Ulyqs@Cw3l{B%r-|lfsml_ic#+-w&GiNjRi*eTnRt!r)6*^nADaehR-c9d8XDUqwqgUQg zi_cH$*=_fvpafp~m-)zfeTS8@<-TCXC5`FF9kK1|>vPE_hi78x6i5a~ZGKVj8Dj02 zj_`6Y+*FCZ@c4>$N}|Dl_D*D2j`{Q5R>=x#5xFHtH;B(+{@Xc=G&SPOOzMi*J;_oG}2bU_&){zuTQOnSNJy=wfS;2jZfLm~L zc(S{+PlXlYgl?|uO zD4*th_rbgZU$xPl(s4+*wjjB6i5I6C<}9?ym8ZMbZY=TCI}un@XC(@z?qEvn5v~k~ zXHanHS!jGz5?7aW7W!_@Oks?^f%#JXbwQAO+pYRMl73SQGY@07 z_sz~?8#cBuo|P176GN6EPtQ+!#ivw6qWa=KMXiq8m_+p1iA8#Fi9L_FQ~3@HFLGC2 zODO;Rj$p`b3-%iw27=@b0S1ECy&e1^>W~u{Ej-Jj{{_D9j+|rMvawJ(&Pc`Q2HLs` zZ?S`h5&hvxlFY1&*lJbxc68GHq=WUQ#NjLb!L{!v4ww zRKVCgwsZA)L1B{&!3}#)BhbWH^S1B3HG)@?phMnvP_`_CzUo~7tkV<73doi?^0|@L zIB<2P&is}0>ZG-EVLbt{=)2>}cbLjobwW&V7?@DUs5UZ9O&i|KP*-(XxQXMgz9cZO zV0ZKfFB}Arn&LdntS`1k>vF_-_!(vhXkY2M~hCbji3ldHBBL}5bQq!1+a)Y1#XWG|mZ@1c*R zNiP-e1Pql4Lz`k>2(llM;OaE2@H679JbiP}utI%>{%tyCA!jC1s7_rY!*8_XRWf<9 z+Ys$byLT}MSMggF%6AFzD=w|CA53+_>n>v2J_VcRj#HXXgY6K+{hKut1^IZ z2rKGj4zvhiVM<#~ZN8FWRnNYLl6w|$g2ewtZL{i4W3IfAgFo^seX3VtM7}Jm`9xk? z>h1XA!wN**+Q-VF#Ib&op%0$hRI}Ua?ss(NjYuh~P=r!K5v^9=Ae&pLo7q7WAw7pg zbAdxfO0!nD#eNUmW_|6|pCl7k!@Y_l`per=dW;E3&DHq$Zc4P5>S^U)6sB-z^JhCD+!%az zR<<*|xG}OT*&;ycH$}G|E$Q~8EEr@sj$-fOuy?JPGTYK`NMNhU3gCjLDJeqBMV=eI zM+iQUT;M)e!3tN^w@pHS<%p~wQBr9@d54tSB0pL>s3pc(fZR={H=~WtQlChY@dPo{ zqE}U?K3MQQ4`N6?4s{-*l^vdfWbiXHdprf#U@}XW$ICNI`<;NgKxCBEeWIT1K61im z!K20~3%)!7n&G0qJR_yEjRwPrvg^x}$K)slJ4!yPMZ`;Pt?w^-!29^J5a59gOzWt{kQ&>m&{tx2%z=nVNN0r7B46v}vw zNwAHS_WYM;P8q$m*?syufFvk-h5-uvJhw}dwcja+0t^fbxqLQ6b zsN=d+Xts0CEQ-{Wgcj{+F*8jXrlw{l-9pwZ$(FjM&@BmSqOc|Pm=vpmn7=XAb&!ux(QjRKvm4(OUa=Wk8YUNRxSpX{1f z)1IM;+{Dvtxm8W^psnnH*BQk=sDQ?NSJ&aI!_S;ZwJ`BplNs1fUbj4L%Tyf*3km~-aY)?;F2vpiCGrN(y}e> zn|R!HSE~%Qmvl_#c3laskhcfCXlTjOc2CF}S#yisP(?le%aSi<;vU0hqfGdXPQ-Qo zl$!cO#%s1W`g)w@Pyf;MLBWnPzkO*bIw}6T<2)=Vp?CA73H-Hfrja?BSJOKxY_+U5 zU7LKe-{)YjroVgM57!yw81~o6hwJ7i9PxWOWz@XMtMa>^MO<3CJXx?e?os5{LwBj2 zR(Xp!zVQ!2E`3g3=5`Rcnb}+gzBl&%(V*@5t>=qGJ>74m>vsN{QRM(;+-Z`0-W27t z-llt8%g0EMqc$O3&S^I9lQQy`$5&-lY1v;nnb>bYqkr`b_mTJb#pjK3AK&({&=D0r zj@;X9utV(Y*BBN`tI`@B^ZA)rcl@%}hLu}WH?2>dh`dN~-kgA;+nYDlPk)?tI8fT| z^=g>#bY@NaktMm6aiMpt?+e$qTHT~`f_^t=i-N=dzy3iB#(qjH}@n9P3+y;&ThU3rFSM-SqIe^Y5Ln zhr~687ureX#{1s;y%?3Tpfr2wijCa$`maU=&z&hYK50IR-E3I=`4e}4P~{}k--YF4 zO!t}F*5&_L@ukq>bj^L|qK<{n%MS8gW>`H4*f|2aE7)m+1!YJ3*1f(lo|Pv}6C6wvuCAG2kP==F_mm*Y5B0)8}0>xVMSDa+~g(RB-RB zrYTvu)&eI{^gNC6)KRg2M2k5K4MrIJa!wM~;pXLEe)}0O`Alnu`vb3Ag|&7yfVhY` zPd_WCF*p?1uiI8p*V;9)Ll&|%=taQ3H@>BM4P8=4db5^gZ4S*2*t}C$!%i^p%mF6@ zjfF)|rY9zR^4Lu^3~rl~Ie5ve6AzxH&XTzPymmz%lZrxk2yN*53ON5@w#B^&tI5^|@nush&@o^3Q#F z-OO|xCi(dHqH_4avf3!em#0fd4y?Ceb7y(`J~nI2Fq&qykrKhrFx_RGb*iqpwd-ug zz`rZ!JDz6L9&r?(DWz*JD_-bZP;s?q)91X0U#g*==tUm&mS>BvZdp2E_lF7fCnUoR zUPrw6ft9j$&xo+f(Pn`msY#yi#C79uzG{#;W=KPJ?!q}xqMLP1yW;HEovKygP5E!}zN;U`%Du$+D?5C!1r(wRph} z+RKWfEVJDv9{F?G?zRsDE+);N8yr_Zi$Ce!@c7YAk3%jPn$3~TUcM_faKsO-CM5=N zmSdf(;ras8q#3Of%N!pKNpiYlaVYEO!dotDy4`lyOc~gno?El+$3@S$Gl9<+O{P(b z!pGTW>G{lmSG=Ppz$|*CcI?~e+54kQ&eXz;yagebr$>&t8zP=~@aS^;arcrun%~|i%Up$=pCq5iqZ(h_-;`7yn{v~5VbtM=Gi{@2dQJX2 zerQU)=;0zO`RF>TEayezhEFlvyQxo3M(*fn%CXXTlSn;kvHHo#SF|_3ylfXr)_!rH zqV?q6m)PphfA4QCthVVtvBy*QM^Am*OCDXfFAqGW-#oTzNPJ^M>NUC5V2Zrlt7)~* zmxOb|HS3-?`#!wZQ)LmyS!THNab88!VbPE^Qr7ZM{#~$(q~g+~&V;W#JOL`6MIbiq z7{30e=qEOQ---F}db*xYV{!|*6T|JRf!U?hcqmQ2-p{c{GDv8N0@`y{+1-e>Ec} zZoaES-LY`N#X|6W*2YGV9Vp zNzd(0n;iM*on2(5X5=G;D}CBpUt5azs@kUsn-hl_IC&Lo4}Q!!Rp)Op#>rp{y~W?P zX#G`t;rr5tzuL_i{r0z-fF_St%+;{rzZ~M&U3gx%S<~<3qpsr*Y3+$?Qz~Zp`sfVW zJ|$?<`$mu28*Zb1dP55sWf3#dZbIB8gI~us>?i}YQVi>lH`YDMcd4CfGqNKjICl1> z#Mv(^)yI?=jkCG3=Xv(CCDC(h zpvZvqWzxkrX63nOzbe&8=V``*I->?{8@Bj$?o^~u%a}%havRT8d_IAyH1qF3)e(&=4 za-k(pcI_Nn+BWe?UBWAeF!{-@rNauce;(7O<>PrlwP8s>W7s6V%zf z?{UfWO`R4!5!&@O6TA(IYruno(SJNSa=c%4@B#a=beGU_4{Za_ikpkyUP`3YaZ?XF zI?QM(|KR!i8Jo^02@71Z#Gh`CoK)ku<^I{C@WDPFZ|(%@-4|c~xcd51y`E5$2%qZt z$X^fG`_sD{dV9uq>OtA2$vNlpe#yKmFCQL1X5wyB79i7uL=?YGAX0 zo0-Tm&eVEfI(lPyMBaRF-LZ9ZX1`&-Jvu$C(ebE$-cw0a_5=CD32*ZSRdrFHW2-w$ za`)QrTi4>)CNPU&n~!cYjB$);XuNbpv+UN3gzkWSnZ2Rbc4PciDo2} zeSGeZ@_5$IVCT(7v#E6Rb$63N%YCu*O&YhR@(v7|(J2VmzcF{(mvK|xHLgGJK78@V z2aoNtd5Lp}oImRp7@9ZO`$JgOGn?PzS0(MYZ3?h8x|B3UHnU)<+bXL?)%C&+Yjv+g zR2F4s8V)g~Q*XTZsi{1vXcfQX;&6imx0PRU-&Y<~2k|RC|BLT&`|cI}XZI`&p zEtJWZV%Lz63uN+n0E@=(raGYan?SrTbQQ_PLSs6GP63cxQ0VO?lip|HL9~lSt~H^C zK#p&;uod_@4w)>>guJP}q!<*yp6f;;gWRzat^z>p8A>HdNO?4bk)-2idzh$92=1i` zBjTX~@}#^#A#w{2KrU;^MM2ADGyAwe*h&Irk`0KI8MHoWVG8)Klu2fQ6|Hiwb?Mmu zt)c+_mj5bOH1H;PGPTU%}i*Rdzppr84UnwhYp7pv8Cfk`n8Iu`<1gtoe z!yo}uSpUj}WOHmi0U&e&7dneza~1``h_!H)NFYT1kqM-tV7Wx9bS8|$0D}xBI>AVo zqlruikipQ+m4qTU?dUklAyt(Shd6V&UO`IO;MsSsNGg*97#f|a3weE?33yT*?Dlz` zz!n6VilBmUEZ~s3MFyaD#9J6Kor1bvCFrV#3(4uh^_qw2M9*YsG=l{XRcmz!W6*G z#nRc8q0S6`!ns@9xZ81UzG(-%DB;|38{&4rqCsf~rgEo- z*@1zt!z%^q4P56Si97(wwtzqqtzDmIi%Wbw!c8-1Qcyf_M8L==KQ6$U~S&;V`6CtQKMHej1$4A zI4>l%quBv7mI7RuUW!bCk1KV?SP)#wAOsOhX;dZ}vkr(C|BXBDMUr8eq*8(Hxskib zsx_WTL@t)j?L`9Qt}}9jSt=2Wu|kTxB3;G4Oj7BjlJJg`+GO~D$&AGsIA2odxoq%8tBTzgzU z1nmen*>~{5G$Eh^Ldg(#(Qze|SqfJTPc1kzq$Y9262VHqRVoyI4@-oAQc8nq=X$wFQ~D6jEjV)M?5v);$dbah)3#u zRg#Oc<>(a;ZY0>dh z3iJgSR4blLh<%tR6t5D>MFO6wl|<}EwFyFAO@cHFR1Z;*WspqN`@7NxXsG>H+TTG| z8L|ISWJkVO6cQ@@4i-uvEfD$1@NG4Kc^<&>AAn~j0M8ZxzA*&wT@Zjh1nvyr!3yA= z7E*V5-$&BxA3Cjf`^_YkeC+53Hyq9$b0C068-Sx4zyb9Yy3n`CVr&RxF*pJEInh_> z&>^KKS;~@w>A~g6d1A?OYA@t~-U@=eNJR#a^k%#xkPOj7+FpKKiIZqkTj z3V0A+(gL&;ubR zgJc&5h%hGe1tA2A@E5156PZPhV02Ym|>X$-kdK^lXQZ=BS0a3K4V0Wmn}*LkXInH+Q%r#c3+ zX=Iy1Ajl&72tpj9HV@{g`5dvbx~-Uq!eqXPd&&NQAS9!Z=Yg;qUJ$gP2~|}O#0cs# zGtp+8G!Ig@0R*f217xYwgVcQvfo!@u4>p>bRr!J(n)*DNy5E=(T9Q=P!Zfw`g!`NC?k1u>DtrnVMwy4n~E$&e%-Ot!kuSuk3A zRb^qp>iAsJh_x7Lbk?Q$Vs1FkiP`L>Xb9p&Kg*14l#K&h5!-@nF3HigP3d@ zhXo1vNIvGX*(^W)Y;!&b5(xeM=&--PKg$mm2v`DtA&27+@i{C%0UMs}O?8$?FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .integrity (NOLOAD): - { - . = ALIGN(4); - *(.integrity) /* .integrity internal integrity protection of NVFile */ - *(.integrity*) /* .integrity* internal integrity protection of NVFile */ - . = ALIGN(4); - } >INTEGRITY - - .nvfile (NOLOAD): - { - . = ALIGN(4); - *(.nvfile) /* .nvfile persisted NV storage for the TPM */ - *(.nvfile*) /* .nvfile* persisted NV storage for the TPM */ - . = ALIGN(4); - } >NVFILE - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - - /* Uninitialized data section */ - . = ALIGN(4); - .bss2 : - { - . = ALIGN(4); - *(.ram2) - *(.ram2*) - Middlewares\Platform\Cancel.o - Middlewares\Platform\Clock.o - Middlewares\Platform\Entropy.o -/* Middlewares\Platform\LocalityPlat.o*/ -/* Middlewares\Platform\NVMem.o*/ - Middlewares\Platform\PlatformData.o -/* Middlewares\Platform\PowerPlat.o*/ -/* Middlewares\Platform\PPPlat.o*/ -/* Middlewares\Platform\RunCommand.o*/ -/* Middlewares\Platform\Unique.o*/ - . = ALIGN(4); - } >RAM2 - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(4); - } >RAM - - - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/main.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/main.c deleted file mode 100644 index 77878e0f5..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/main.c +++ /dev/null @@ -1,409 +0,0 @@ - -/** - ****************************************************************************** - * @file : main.c - * @brief : Main program body - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -#include "stm32l4xx_hal.h" -#include "usb_device.h" - -/* USER CODE BEGIN Includes */ -#include -#include -#include -#include "TpmDevice.h" -#include "StmUtil.h" - -/* USER CODE END Includes */ - -/* Private variables ---------------------------------------------------------*/ -RNG_HandleTypeDef hrng; - -RTC_HandleTypeDef hrtc; - -UART_HandleTypeDef huart2; - -/* USER CODE BEGIN PV */ -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -void SystemClock_Config(void); -static void MX_GPIO_Init(void); -static void MX_RNG_Init(void); -static void MX_RTC_Init(void); -static void MX_USART2_UART_Init(void); - -/* USER CODE BEGIN PFP */ -/* Private function prototypes -----------------------------------------------*/ -#define CPU_CORE_FREQUENCY_HZ 800000000 /* CPU core frequency in Hz */ -void SWO_Init(uint32_t portBits, uint32_t cpuCoreFreqHz); -/* USER CODE END PFP */ - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/** - * @brief The application entry point. - * - * @retval None - */ -int main(void) -{ - /* USER CODE BEGIN 1 */ - - /* USER CODE END 1 */ - - /* MCU Configuration----------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - - /* USER CODE BEGIN Init */ - - /* USER CODE END Init */ - - /* Configure the system clock */ - SystemClock_Config(); - - /* USER CODE BEGIN SysInit */ - - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_RNG_Init(); - MX_RTC_Init(); - MX_USART2_UART_Init(); - MX_USB_DEVICE_Init(); - /* USER CODE BEGIN 2 */ - InitializeITM(); - fprintf(stderr, "\r\n\r\n=========================\r\n" - "= Nucleo-L476RG TPM 2.0 =\r\n" - "=========================\r\n"); - printf("Nucleo-L476RG TPM 2.0\r\n"); - - if(!TpmInitializeDevice()) - { - _Error_Handler(__FILE__, __LINE__); - } - - /* USER CODE END 2 */ - - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - - /* USER CODE END WHILE */ - - /* USER CODE BEGIN 3 */ - if(!TpmOperationsLoop()) - { - _Error_Handler(__FILE__, __LINE__); - } - - } - /* USER CODE END 3 */ - -} - -/** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) -{ - - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInit; - - /**Configure LSE Drive Capability - */ - HAL_PWR_EnableBkUpAccess(); - - __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSE - |RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = 16; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.MSICalibrationValue = 0; - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 1; // <-- This one gets dropped by V1.11.0 add me manually back in when CubeMX ran - RCC_OscInitStruct.PLL.PLLN = 10; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; - RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART2 - |RCC_PERIPHCLK_USB|RCC_PERIPHCLK_RNG; - PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; - PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; - PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_MSI; - PeriphClkInit.RngClockSelection = RCC_RNGCLKSOURCE_MSI; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - /**Configure the main internal regulator output voltage - */ - if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - /**Configure the Systick interrupt time - */ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - - /**Configure the Systick - */ - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - - /**Enable MSI Auto calibration - */ - HAL_RCCEx_EnableMSIPLLMode(); - - /* SysTick_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); -} - -/* RNG init function */ -static void MX_RNG_Init(void) -{ - - hrng.Instance = RNG; - if (HAL_RNG_Init(&hrng) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - -} - -/* RTC init function */ -static void MX_RTC_Init(void) -{ - - RTC_TimeTypeDef sTime; - RTC_DateTypeDef sDate; - - /**Initialize RTC Only - */ - hrtc.Instance = RTC; -if(HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_DR0) != 0x32F2){ - hrtc.Init.HourFormat = RTC_HOURFORMAT_24; - hrtc.Init.AsynchPrediv = 127; - hrtc.Init.SynchPrediv = 255; - hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; - hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; - hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - if (HAL_RTC_Init(&hrtc) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - /**Initialize RTC and set the Time and Date - */ - sTime.Hours = 0; - sTime.Minutes = 0; - sTime.Seconds = 0; - sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; - sTime.StoreOperation = RTC_STOREOPERATION_RESET; - if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BIN) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - sDate.WeekDay = RTC_WEEKDAY_MONDAY; - sDate.Month = RTC_MONTH_JANUARY; - sDate.Date = 1; - sDate.Year = 0; - - if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BIN) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - HAL_RTCEx_BKUPWrite(&hrtc,RTC_BKP_DR0,0x32F2); - } - -} - -/* USART2 init function */ -static void MX_USART2_UART_Init(void) -{ - - huart2.Instance = USART2; - huart2.Init.BaudRate = 115200; - huart2.Init.WordLength = UART_WORDLENGTH_8B; - huart2.Init.StopBits = UART_STOPBITS_1; - huart2.Init.Parity = UART_PARITY_NONE; - huart2.Init.Mode = UART_MODE_TX; - huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart2.Init.OverSampling = UART_OVERSAMPLING_16; - huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart2) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - -} - -/** Configure pins as - * Analog - * Input - * Output - * EVENT_OUT - * EXTI -*/ -static void MX_GPIO_Init(void) -{ - - GPIO_InitTypeDef GPIO_InitStruct; - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pin : B1_Pin */ - GPIO_InitStruct.Pin = B1_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pin : LD2_Pin */ - GPIO_InitStruct.Pin = LD2_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct); - -} - -/* USER CODE BEGIN 4 */ - -/* USER CODE END 4 */ - -/** - * @brief This function is executed in case of error occurrence. - * @param file: The file name as string. - * @param line: The line in file as a number. - * @retval None - */ -void _Error_Handler(char *file, int line) -{ - /* USER CODE BEGIN Error_Handler_Debug */ - dbgPrint("PANIC: EXECUTION HALTED %s@%d\r\n", file, line); - /* User can add his own implementation to report the HAL error return state */ - while(1) - { - } - /* USER CODE END Error_Handler_Debug */ -} - -#ifdef USE_FULL_ASSERT -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t* file, uint32_t line) -{ - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, - tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ -} -#endif /* USE_FULL_ASSERT */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/stm32l4xx_hal_msp.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/stm32l4xx_hal_msp.c deleted file mode 100644 index 3cdb95fb8..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/stm32l4xx_hal_msp.c +++ /dev/null @@ -1,225 +0,0 @@ -/** - ****************************************************************************** - * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization - * and de-Initialization codes. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -extern void _Error_Handler(char *, int); -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ -/** - * Initializes the Global MSP. - */ -void HAL_MspInit(void) -{ - /* USER CODE BEGIN MspInit 0 */ - - /* USER CODE END MspInit 0 */ - - __HAL_RCC_SYSCFG_CLK_ENABLE(); - __HAL_RCC_PWR_CLK_ENABLE(); - - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - - /* System interrupt init*/ - /* MemoryManagement_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0); - /* BusFault_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0); - /* UsageFault_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0); - /* SVCall_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0); - /* DebugMonitor_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0); - /* PendSV_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0); - /* SysTick_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); - - /* USER CODE BEGIN MspInit 1 */ - - /* USER CODE END MspInit 1 */ -} - -void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) -{ - - if(hrng->Instance==RNG) - { - /* USER CODE BEGIN RNG_MspInit 0 */ - - /* USER CODE END RNG_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_RNG_CLK_ENABLE(); - /* USER CODE BEGIN RNG_MspInit 1 */ - - /* USER CODE END RNG_MspInit 1 */ - } - -} - -void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng) -{ - - if(hrng->Instance==RNG) - { - /* USER CODE BEGIN RNG_MspDeInit 0 */ - - /* USER CODE END RNG_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_RNG_CLK_DISABLE(); - /* USER CODE BEGIN RNG_MspDeInit 1 */ - - /* USER CODE END RNG_MspDeInit 1 */ - } - -} - -void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) -{ - - if(hrtc->Instance==RTC) - { - /* USER CODE BEGIN RTC_MspInit 0 */ - - /* USER CODE END RTC_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_RTC_ENABLE(); - /* USER CODE BEGIN RTC_MspInit 1 */ - - /* USER CODE END RTC_MspInit 1 */ - } - -} - -void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) -{ - - if(hrtc->Instance==RTC) - { - /* USER CODE BEGIN RTC_MspDeInit 0 */ - - /* USER CODE END RTC_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_RTC_DISABLE(); - /* USER CODE BEGIN RTC_MspDeInit 1 */ - - /* USER CODE END RTC_MspDeInit 1 */ - } - -} - -void HAL_UART_MspInit(UART_HandleTypeDef* huart) -{ - - GPIO_InitTypeDef GPIO_InitStruct; - if(huart->Instance==USART2) - { - /* USER CODE BEGIN USART2_MspInit 0 */ - - /* USER CODE END USART2_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_USART2_CLK_ENABLE(); - - /**USART2 GPIO Configuration - PA2 ------> USART2_TX - PA3 ------> USART2_RX - */ - GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF7_USART2; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN USART2_MspInit 1 */ - - /* USER CODE END USART2_MspInit 1 */ - } - -} - -void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) -{ - - if(huart->Instance==USART2) - { - /* USER CODE BEGIN USART2_MspDeInit 0 */ - - /* USER CODE END USART2_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration - PA2 ------> USART2_TX - PA3 ------> USART2_RX - */ - HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin); - - /* USER CODE BEGIN USART2_MspDeInit 1 */ - - /* USER CODE END USART2_MspDeInit 1 */ - } - -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/stm32l4xx_it.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/stm32l4xx_it.c deleted file mode 100644 index a83db872c..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/stm32l4xx_it.c +++ /dev/null @@ -1,88 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_it.c - * @brief Interrupt Service Routines. - ****************************************************************************** - * - * COPYRIGHT(c) 2018 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" -#include "stm32l4xx.h" -#include "stm32l4xx_it.h" - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* External variables --------------------------------------------------------*/ -extern PCD_HandleTypeDef hpcd_USB_OTG_FS; - -/******************************************************************************/ -/* Cortex-M4 Processor Interruption and Exception Handlers */ -/******************************************************************************/ - -/** -* @brief This function handles System tick timer. -*/ -void SysTick_Handler(void) -{ - /* USER CODE BEGIN SysTick_IRQn 0 */ - - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - HAL_SYSTICK_IRQHandler(); - /* USER CODE BEGIN SysTick_IRQn 1 */ - - /* USER CODE END SysTick_IRQn 1 */ -} - -/******************************************************************************/ -/* STM32L4xx Peripheral Interrupt Handlers */ -/* Add here the Interrupt Handlers for the used peripherals. */ -/* For the available peripheral interrupt handler names, */ -/* please refer to the startup file (startup_stm32l4xx.s). */ -/******************************************************************************/ - -/** -* @brief This function handles USB OTG FS global interrupt. -*/ -void OTG_FS_IRQHandler(void) -{ - /* USER CODE BEGIN OTG_FS_IRQn 0 */ - - /* USER CODE END OTG_FS_IRQn 0 */ - HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); - /* USER CODE BEGIN OTG_FS_IRQn 1 */ - - /* USER CODE END OTG_FS_IRQn 1 */ -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/system_stm32l4xx.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/system_stm32l4xx.c deleted file mode 100644 index c76fe45ee..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/system_stm32l4xx.c +++ /dev/null @@ -1,353 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l4xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32l4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * After each device reset the MSI (4 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to - * configure the system clock before to branch to main program. - * - * This file configures the system clock as follows: - *============================================================================= - *----------------------------------------------------------------------------- - * System Clock source | MSI - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 4000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 4000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- - * PLL_M | 1 - *----------------------------------------------------------------------------- - * PLL_N | 8 - *----------------------------------------------------------------------------- - * PLL_P | 7 - *----------------------------------------------------------------------------- - * PLL_Q | 2 - *----------------------------------------------------------------------------- - * PLL_R | 2 - *----------------------------------------------------------------------------- - * PLLSAI1_P | NA - *----------------------------------------------------------------------------- - * PLLSAI1_Q | NA - *----------------------------------------------------------------------------- - * PLLSAI1_R | NA - *----------------------------------------------------------------------------- - * PLLSAI2_P | NA - *----------------------------------------------------------------------------- - * PLLSAI2_Q | NA - *----------------------------------------------------------------------------- - * PLLSAI2_R | NA - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Disabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** @addtogroup STM32L4xx_System_Private_Includes - * @{ - */ - -#include "stm32l4xx.h" - -#if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (MSI_VALUE) - #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ - uint32_t SystemCoreClock = 4000000U; - - const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; - const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; - const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \ - 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U}; -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000U; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= 0xEAF6FFFFU; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000U; - - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000U; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) - * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value - * 4 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U; - - /* Get MSI Range frequency--------------------------------------------------*/ - if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) - { /* MSISRANGE from RCC_CSR applies */ - msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; - } - else - { /* MSIRANGE from RCC_CR applies */ - msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; - } - /*MSI frequency range in HZ*/ - msirange = MSIRangeTable[msirange]; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR & RCC_CFGR_SWS) - { - case 0x00: /* MSI used as system clock source */ - SystemCoreClock = msirange; - break; - - case 0x04: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - - case 0x08: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - - case 0x0C: /* PLL used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; - - switch (pllsource) - { - case 0x02: /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm); - break; - - case 0x03: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm); - break; - - default: /* MSI used as PLL clock source */ - pllvco = (msirange / pllm); - break; - } - pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; - SystemCoreClock = pllvco/pllr; - break; - - default: - SystemCoreClock = msirange; - break; - } - /* Compute HCLK clock frequency --------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/usb_device.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/usb_device.c deleted file mode 100644 index 8301f6af7..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/usb_device.c +++ /dev/null @@ -1,173 +0,0 @@ -/** - ****************************************************************************** - * @file : usb_device.c - * @version : v2.0_Cube - * @brief : This file implements the USB Device - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#include "usb_device.h" -#include "usbd_core.h" -#include "usbd_desc.h" -#include "usbd_cdc.h" -#include "usbd_cdc_if.h" - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* USER CODE BEGIN PV */ -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE END PV */ - -/* USER CODE BEGIN PFP */ -/* Private function prototypes -----------------------------------------------*/ - -/* USER CODE END PFP */ - -/* Return USBD_OK if the Battery Charging Detection mode (BCD) is used, else USBD_FAIL. */ -extern USBD_StatusTypeDef USBD_LL_BatteryCharging(USBD_HandleTypeDef *pdev); - -/* USB Device Core handle declaration. */ -USBD_HandleTypeDef hUsbDeviceFS; - -/* - * -- Insert your variables declaration here -- - */ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* - * -- Insert your external function declaration here -- - */ -/* USER CODE BEGIN 1 */ -void MX_USB_DEVICE_DeInit(void) -{ - USBD_DeInit(&hUsbDeviceFS); -} - -/* USER CODE END 1 */ - -/** - * Init USB device Library, add supported class and start the library - * @retval None - */ -void MX_USB_DEVICE_Init(void) -{ - /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ - - /* USER CODE END USB_DEVICE_Init_PreTreatment */ - - /* Init Device Library, add supported class and start the library. */ - USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS); - USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC); - USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS); - /* Verify if the Battery Charging Detection mode (BCD) is used : */ - /* If yes, the USB device is started in the HAL_PCDEx_BCD_Callback */ - /* upon reception of PCD_BCD_DISCOVERY_COMPLETED message. */ - /* If no, the USB device is started now. */ - if (USBD_LL_BatteryCharging(&hUsbDeviceFS) != USBD_OK) { - USBD_Start(&hUsbDeviceFS); - } - /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ - - /* USER CODE END USB_DEVICE_Init_PostTreatment */ -} - -/** - * @brief Send BCD message to user layer - * @param hpcd: PCD handle - * @param msg: LPM message - * @retval None - */ -void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) -{ - USBD_HandleTypeDef usbdHandle = hUsbDeviceFS; - - /* USER CODE BEGIN 7 */ - if (hpcd->battery_charging_active == ENABLE) - { - switch(msg) - { - case PCD_BCD_CONTACT_DETECTION: - - break; - - case PCD_BCD_STD_DOWNSTREAM_PORT: - - break; - - case PCD_BCD_CHARGING_DOWNSTREAM_PORT: - - break; - - case PCD_BCD_DEDICATED_CHARGING_PORT: - - break; - - case PCD_BCD_DISCOVERY_COMPLETED: - USBD_Start(&usbdHandle); - break; - - case PCD_BCD_ERROR: - default: - break; - } - } - /* USER CODE END 7 */ -} - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/usbd_cdc_if.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/usbd_cdc_if.c deleted file mode 100644 index 46acaf9d4..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/usbd_cdc_if.c +++ /dev/null @@ -1,392 +0,0 @@ -/** - ****************************************************************************** - * @file : usbd_cdc_if.c - * @version : v2.0_Cube - * @brief : Usb device for Virtual Com Port. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_cdc_if.h" - -/* USER CODE BEGIN INCLUDE */ -#include -#include -#include "StmUtil.h" -#include "stm32l4xx_hal.h" - -/* USER CODE END INCLUDE */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ - -/* USER CODE BEGIN PV */ -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE END PV */ - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @brief Usb device library. - * @{ - */ - -/** @addtogroup USBD_CDC_IF - * @{ - */ - -/** @defgroup USBD_CDC_IF_Private_TypesDefinitions USBD_CDC_IF_Private_TypesDefinitions - * @brief Private types. - * @{ - */ - -/* USER CODE BEGIN PRIVATE_TYPES */ -#define CDC_RTS_MASK 0x0002 -#define CDC_DTR_MASK 0x0001 -void TpmConnectionReset(void); -int TpmSignalEvent(uint8_t* Buf, uint32_t *Len); - -/* USER CODE END PRIVATE_TYPES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Private_Defines USBD_CDC_IF_Private_Defines - * @brief Private defines. - * @{ - */ - -/* USER CODE BEGIN PRIVATE_DEFINES */ -/* Define size for the receive and transmit buffer over CDC */ -/* It's up to user to redefine and/or remove those define */ -#define APP_RX_DATA_SIZE 2048 -#define APP_TX_DATA_SIZE 2048 -typedef struct -{ - uint8_t bReqType; - uint8_t bRequest; - uint16_t wVal; - uint16_t wIndex; - uint16_t wLength; -} USBD_SETUP_PKT, *PUSBD_SETUP_PKT; -extern RTC_HandleTypeDef hrtc; -/* USER CODE END PRIVATE_DEFINES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Private_Macros USBD_CDC_IF_Private_Macros - * @brief Private macros. - * @{ - */ - -/* USER CODE BEGIN PRIVATE_MACRO */ - -/* USER CODE END PRIVATE_MACRO */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Private_Variables USBD_CDC_IF_Private_Variables - * @brief Private variables. - * @{ - */ -/* Create buffer for reception and transmission */ -/* It's up to user to redefine and/or remove those define */ -/** Received data over USB are stored in this buffer */ -uint8_t UserRxBufferFS[APP_RX_DATA_SIZE]; - -/** Data to send over USB CDC are stored in this buffer */ -uint8_t UserTxBufferFS[APP_TX_DATA_SIZE]; - -/* USER CODE BEGIN PRIVATE_VARIABLES */ - -/* USER CODE END PRIVATE_VARIABLES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables - * @brief Public variables. - * @{ - */ - -extern USBD_HandleTypeDef hUsbDeviceFS; - -/* USER CODE BEGIN EXPORTED_VARIABLES */ -USBD_CDC_LineCodingTypeDef LineCoding = -{ - 115200, /* baud rate*/ - 0x00, /* stop bits-1*/ - 0x00, /* parity - none*/ - 0x08 /* nb. of bits 8*/ -}; -volatile uint8_t CDC_RTS = 0; // RequestToSend -volatile uint8_t CDC_DTR = 0; // DataTerminalReady - -/* USER CODE END EXPORTED_VARIABLES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Private_FunctionPrototypes USBD_CDC_IF_Private_FunctionPrototypes - * @brief Private functions declaration. - * @{ - */ - -static int8_t CDC_Init_FS(void); -static int8_t CDC_DeInit_FS(void); -static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length); -static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len); - -/* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */ - -/* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */ - -/** - * @} - */ - -USBD_CDC_ItfTypeDef USBD_Interface_fops_FS = -{ - CDC_Init_FS, - CDC_DeInit_FS, - CDC_Control_FS, - CDC_Receive_FS -}; - -/* Private functions ---------------------------------------------------------*/ -/** - * @brief Initializes the CDC media low layer over the FS USB IP - * @retval USBD_OK if all operations are OK else USBD_FAIL - */ -static int8_t CDC_Init_FS(void) -{ - /* USER CODE BEGIN 3 */ - /* Set Application Buffers */ - USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); - USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); - return (USBD_OK); - /* USER CODE END 3 */ -} - -/** - * @brief DeInitializes the CDC media low layer - * @retval USBD_OK if all operations are OK else USBD_FAIL - */ -static int8_t CDC_DeInit_FS(void) -{ - /* USER CODE BEGIN 4 */ - return (USBD_OK); - /* USER CODE END 4 */ -} - -/** - * @brief Manage the CDC class requests - * @param cmd: Command code - * @param pbuf: Buffer containing command data (request parameters) - * @param length: Number of data to be sent (in bytes) - * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL - */ -static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) -{ - /* USER CODE BEGIN 5 */ - char parity[] = {'N', 'O', 'E', 'M', 'S'}; - uint8_t stop[] = {1, 15, 2}; - switch (cmd) - { - case CDC_SEND_ENCAPSULATED_COMMAND: - - break; - - case CDC_GET_ENCAPSULATED_RESPONSE: - - break; - - case CDC_SET_COMM_FEATURE: - - break; - - case CDC_GET_COMM_FEATURE: - - break; - - case CDC_CLEAR_COMM_FEATURE: - - break; - - /*******************************************************************************/ - /* Line Coding Structure */ - /*-----------------------------------------------------------------------------*/ - /* Offset | Field | Size | Value | Description */ - /* 0 | dwDTERate | 4 | Number |Data terminal rate, in bits per second*/ - /* 4 | bCharFormat | 1 | Number | Stop bits */ - /* 0 - 1 Stop bit */ - /* 1 - 1.5 Stop bits */ - /* 2 - 2 Stop bits */ - /* 5 | bParityType | 1 | Number | Parity */ - /* 0 - None */ - /* 1 - Odd */ - /* 2 - Even */ - /* 3 - Mark */ - /* 4 - Space */ - /* 6 | bDataBits | 1 | Number Data bits (5, 6, 7, 8 or 16). */ - /*******************************************************************************/ - case CDC_SET_LINE_CODING: - { - LineCoding.bitrate = pbuf[0] | (pbuf[1] << 8) | (pbuf[2] << 16) | (pbuf[3] << 24); - LineCoding.format = pbuf[4]; - LineCoding.paritytype = pbuf[5]; - LineCoding.datatype = pbuf[6]; - dbgPrint("CDC_SET_LINE_CODING: %lu-%d%c%d\r\n", LineCoding.bitrate, LineCoding.datatype, parity[LineCoding.paritytype], stop[LineCoding.format]); - break; - } - - case CDC_GET_LINE_CODING: - { - pbuf[0] = (uint8_t)(LineCoding.bitrate); - pbuf[1] = (uint8_t)(LineCoding.bitrate >> 8); - pbuf[2] = (uint8_t)(LineCoding.bitrate >> 16); - pbuf[3] = (uint8_t)(LineCoding.bitrate >> 24); - pbuf[4] = LineCoding.format; - pbuf[5] = LineCoding.paritytype; - pbuf[6] = LineCoding.datatype; - dbgPrint("CDC_GET_LINE_CODING: %lu-%d%c%d\r\n", LineCoding.bitrate, LineCoding.datatype, parity[LineCoding.paritytype], stop[LineCoding.format]); - break; - } - - case CDC_SET_CONTROL_LINE_STATE: - { - PUSBD_SETUP_PKT setupPkt = (PUSBD_SETUP_PKT)pbuf; - CDC_RTS = ((setupPkt->wVal & CDC_RTS_MASK) != 0); - CDC_DTR = ((setupPkt->wVal & CDC_DTR_MASK) != 0); - dbgPrint("CDC_SET_CONTROL_LINE_STATE: RTS=%d, DTR=%d\r\n", CDC_RTS, CDC_DTR); - // Reset any ongoing cmd transfers - TpmConnectionReset(); - break; - } - - case CDC_SEND_BREAK: - - break; - - default: - break; - } - - return (USBD_OK); - /* USER CODE END 5 */ -} - -/** - * @brief Data received over USB OUT endpoint are sent over CDC interface - * through this function. - * - * @note - * This function will block any OUT packet reception on USB endpoint - * untill exiting this function. If you exit this function before transfer - * is complete on CDC interface (ie. using DMA controller) it will result - * in receiving more data while previous ones are still not sent. - * - * @param Buf: Buffer of data to be received - * @param Len: Number of data received (in bytes) - * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL - */ -static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) -{ - /* USER CODE BEGIN 6 */ - if(!TpmSignalEvent(Buf, Len)) - { - return(USBD_FAIL); - } - - USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); - USBD_CDC_ReceivePacket(&hUsbDeviceFS); - return (USBD_OK); - /* USER CODE END 6 */ -} - -/** - * @brief CDC_Transmit_FS - * Data to send over USB IN endpoint are sent over CDC interface - * through this function. - * @note - * - * - * @param Buf: Buffer of data to be sent - * @param Len: Number of data to be sent (in bytes) - * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY - */ -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) -{ - uint8_t result = USBD_OK; - /* USER CODE BEGIN 7 */ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData; - if (hcdc->TxState != 0){ - return USBD_BUSY; - } - USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len); - result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); - /* USER CODE END 7 */ - return result; -} - -/* USER CODE BEGIN PRIVATE_FUNCTIONS_IMPLEMENTATION */ - -/* USER CODE END PRIVATE_FUNCTIONS_IMPLEMENTATION */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/usbd_conf.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/usbd_conf.c deleted file mode 100644 index 6bec5fa31..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/usbd_conf.c +++ /dev/null @@ -1,894 +0,0 @@ -/** - ****************************************************************************** - * @file : usbd_conf.c - * @version : v2.0_Cube - * @brief : This file implements the board support package for the USB device library - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx.h" -#include "stm32l4xx_hal.h" -#include "usbd_def.h" -#include "usbd_core.h" -#include "usbd_cdc.h" - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ - -/* USER CODE BEGIN PV */ -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE END PV */ - -PCD_HandleTypeDef hpcd_USB_OTG_FS; -void _Error_Handler(char * file, int line); - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* Exported function prototypes ----------------------------------------------*/ -extern USBD_StatusTypeDef USBD_LL_BatteryCharging(USBD_HandleTypeDef *pdev); - -/* USER CODE BEGIN PFP */ -/* Private function prototypes -----------------------------------------------*/ - -/* USER CODE END PFP */ - -/* Private functions ---------------------------------------------------------*/ - -/* USER CODE BEGIN 1 */ -static void SystemClockConfig_Resume(void); - -/* USER CODE END 1 */ - -void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state); -extern void SystemClock_Config(void); - -/******************************************************************************* - LL Driver Callbacks (PCD -> USB Device Library) -*******************************************************************************/ -/* MSP Init */ - -void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) -{ - GPIO_InitTypeDef GPIO_InitStruct; - if(pcdHandle->Instance==USB_OTG_FS) - { - /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ - - /* USER CODE END USB_OTG_FS_MspInit 0 */ - - /**USB_OTG_FS GPIO Configuration - PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP - */ - GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* Peripheral clock enable */ - __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - - /* Enable VDDUSB */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - HAL_PWREx_EnableVddUSB(); - __HAL_RCC_PWR_CLK_DISABLE(); - } - else - { - HAL_PWREx_EnableVddUSB(); - } - - /* Peripheral interrupt init */ - HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(OTG_FS_IRQn); - /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ - - /* USER CODE END USB_OTG_FS_MspInit 1 */ - } -} - -void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) -{ - if(pcdHandle->Instance==USB_OTG_FS) - { - /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */ - - /* USER CODE END USB_OTG_FS_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration - PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); - - /* Disable VDDUSB */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - HAL_PWREx_DisableVddUSB(); - __HAL_RCC_PWR_CLK_DISABLE(); - } - else - { - HAL_PWREx_DisableVddUSB(); - } - - /* Peripheral interrupt Deinit*/ - HAL_NVIC_DisableIRQ(OTG_FS_IRQn); - - /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */ - - /* USER CODE END USB_OTG_FS_MspDeInit 1 */ - } -} - -/** - * @brief Setup stage callback - * @param hpcd: PCD handle - * @retval None - */ -void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) -{ - USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); -} - -/** - * @brief Data Out stage callback. - * @param hpcd: PCD handle - * @param epnum: Endpoint number - * @retval None - */ -void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); -} - -/** - * @brief Data In stage callback. - * @param hpcd: PCD handle - * @param epnum: Endpoint number - * @retval None - */ -void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); -} - -/** - * @brief SOF callback. - * @param hpcd: PCD handle - * @retval None - */ -void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) -{ - USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); -} - -/** - * @brief Reset callback. - * @param hpcd: PCD handle - * @retval None - */ -void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) -{ - USBD_SpeedTypeDef speed = USBD_SPEED_FULL; - - /* Set USB current speed. */ - switch (hpcd->Init.speed) - { - case PCD_SPEED_FULL: - speed = USBD_SPEED_FULL; - break; - - default: - speed = USBD_SPEED_FULL; - break; - } - USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); - - /* Reset Device. */ - USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); -} - -/** - * @brief Suspend callback. - * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) - * @param hpcd: PCD handle - * @retval None - */ -void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) -{ - __HAL_PCD_GATE_PHYCLOCK(hpcd); - /* Inform USB library that core enters in suspend Mode. */ - USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); - /* Enter in STOP mode. */ - /* USER CODE BEGIN 2 */ - if (hpcd->Init.low_power_enable) - { - /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ - SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - } - /* USER CODE END 2 */ -} - -/** - * @brief Resume callback. - * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) - * @param hpcd: PCD handle - * @retval None - */ -void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) -{ - __HAL_PCD_UNGATE_PHYCLOCK(hpcd); - - /* USER CODE BEGIN 3 */ - if (hpcd->Init.low_power_enable) - { - /* Reset SLEEPDEEP bit of Cortex System Control Register. */ - SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - SystemClockConfig_Resume(); - } - /* USER CODE END 3 */ - USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); -} - -/** - * @brief ISOOUTIncomplete callback. - * @param hpcd: PCD handle - * @param epnum: Endpoint number - * @retval None - */ -void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); -} - -/** - * @brief ISOINIncomplete callback. - * @param hpcd: PCD handle - * @param epnum: Endpoint number - * @retval None - */ -void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); -} - -/** - * @brief Connect callback. - * @param hpcd: PCD handle - * @retval None - */ -void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) -{ - USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); -} - -/** - * @brief Disconnect callback. - * @param hpcd: PCD handle - * @retval None - */ -void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) -{ - USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); -} - -/******************************************************************************* - LL Driver Interface (USB Device Library --> PCD) -*******************************************************************************/ - -/** - * @brief Initializes the low level portion of the device driver. - * @param pdev: Device handle - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) -{ - /* Init USB Ip. */ - if (pdev->id == DEVICE_FS) { - /* Enable USB power on Pwrctrl CR2 register. */ - /* Link the driver to the stack. */ - hpcd_USB_OTG_FS.pData = pdev; - pdev->pData = &hpcd_USB_OTG_FS; - - hpcd_USB_OTG_FS.Instance = USB_OTG_FS; - hpcd_USB_OTG_FS.Init.dev_endpoints = 6; - hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; - hpcd_USB_OTG_FS.Init.ep0_mps = DEP0CTL_MPS_64; - hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; - hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; - hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; - hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; - hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE; - hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; - hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; - if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); - HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); - HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); - } - return USBD_OK; -} - -/** - * @brief De-Initializes the low level portion of the device driver. - * @param pdev: Device handle - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_DeInit(pdev->pData); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Starts the low level portion of the device driver. - * @param pdev: Device handle - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_Start(pdev->pData); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Stops the low level portion of the device driver. - * @param pdev: Device handle - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_Stop(pdev->pData); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Opens an endpoint of the low level driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @param ep_type: Endpoint type - * @param ep_mps: Endpoint max packet size - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Closes an endpoint of the low level driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Flushes an endpoint of the Low Level Driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Sets a Stall condition on an endpoint of the Low Level Driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Clears a Stall condition on an endpoint of the Low Level Driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Returns Stall condition. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval Stall (1: Yes, 0: No) - */ -uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; - - if((ep_addr & 0x80) == 0x80) - { - return hpcd->IN_ep[ep_addr & 0x7F].is_stall; - } - else - { - return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; - } -} - -/** - * @brief Assigns a USB address to the device. - * @param pdev: Device handle - * @param dev_addr: Device address - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Transmits data over an endpoint. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @param pbuf: Pointer to data to be sent - * @param size: Data size - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Prepares an endpoint for reception. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @param pbuf: Pointer to data to be received - * @param size: Data size - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Returns the last transfered packet size. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval Recived Data Size - */ -uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); -} - -#if (USBD_LPM_ENABLED == 1) -/** - * @brief Send LPM message to user layer - * @param hpcd: PCD handle - * @param msg: LPM message - * @retval None - */ -void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) -{ - switch (msg) - { - case PCD_LPM_L0_ACTIVE: - if (hpcd->Init.low_power_enable) - { - SystemClock_Config(); - - /* Reset SLEEPDEEP bit of Cortex System Control Register. */ - SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - } - __HAL_PCD_UNGATE_PHYCLOCK(hpcd); - USBD_LL_Resume(hpcd->pData); - break; - - case PCD_LPM_L1_ACTIVE: - __HAL_PCD_GATE_PHYCLOCK(hpcd); - USBD_LL_Suspend(hpcd->pData); - - /* Enter in STOP mode. */ - if (hpcd->Init.low_power_enable) - { - /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ - SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - } - break; - } -} -#endif /* (USBD_LPM_ENABLED == 1) */ - -/** - * @brief Delays routine for the USB Device Library. - * @param Delay: Delay in ms - * @retval None - */ -void USBD_LL_Delay(uint32_t Delay) -{ - HAL_Delay(Delay); -} - -/** - * @brief Static single allocation. - * @param size: Size of allocated memory - * @retval None - */ -void *USBD_static_malloc(uint32_t size) -{ - static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */ - return mem; -} - -/** - * @brief Dummy memory free - * @param p: Pointer to allocated memory address - * @retval None - */ -void USBD_static_free(void *p) -{ - -} - -/* USER CODE BEGIN 5 */ -/** - * @brief Configures system clock after wake-up from USB resume callBack: - * enable HSI, PLL and select PLL as system clock source. - * @retval None - */ -static void SystemClockConfig_Resume(void) -{ - SystemClock_Config(); -} -/* USER CODE END 5 */ - -/** - * @brief Software device connection - * @param hpcd: PCD handle - * @param state: Connection state (0: disconnected / 1: connected) - * @retval None - */ -void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) -{ - /* USER CODE BEGIN 6 */ - if (state == 1) - { - /* Configure Low connection state. */ - - } - else - { - /* Configure High connection state. */ - - } - /* USER CODE END 6 */ -} - -/** - * @brief Verify if the Battery Charging Detection mode (BCD) is used : - * return USBD_OK if true - * else return USBD_FAIL if false - * @param pdev: Device handle - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_BatteryCharging(USBD_HandleTypeDef *pdev) -{ - PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*)pdev->pData; - if (hpcd->Init.battery_charging_enable == ENABLE) - { - return USBD_OK; - } - else - { - return USBD_FAIL; - } -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/usbd_desc.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/usbd_desc.c deleted file mode 100644 index 1bd6b60af..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Src/usbd_desc.c +++ /dev/null @@ -1,405 +0,0 @@ -/** - ****************************************************************************** - * @file : usbd_desc.c - * @version : v2.0_Cube - * @brief : This file implements the USB device descriptors. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" -#include "usbd_desc.h" -#include "usbd_conf.h" - -/* USER CODE BEGIN INCLUDE */ - -/* USER CODE END INCLUDE */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ - -/* USER CODE BEGIN PV */ -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE END PV */ - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @addtogroup USBD_DESC - * @{ - */ - -/** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions - * @brief Private types. - * @{ - */ - -/* USER CODE BEGIN PRIVATE_TYPES */ - -/* USER CODE END PRIVATE_TYPES */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines - * @brief Private defines. - * @{ - */ - -#define USBD_VID 1155 -#define USBD_LANGID_STRING 1033 -#define USBD_MANUFACTURER_STRING "STMicroelectronics" -#define USBD_PID_FS 22336 -#define USBD_PRODUCT_STRING_FS "STM32 Virtual ComPort" -#define USBD_SERIALNUMBER_STRING_FS "00000000001A" -#define USBD_CONFIGURATION_STRING_FS "CDC Config" -#define USBD_INTERFACE_STRING_FS "CDC Interface" - -#define USB_SIZ_BOS_DESC 0x0C - -/* USER CODE BEGIN PRIVATE_DEFINES */ - -/* USER CODE END PRIVATE_DEFINES */ - -/** - * @} - */ - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros - * @brief Private macros. - * @{ - */ - -/* USER CODE BEGIN PRIVATE_MACRO */ - -/* USER CODE END PRIVATE_MACRO */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes - * @brief Private functions declaration. - * @{ - */ - -uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); - -#ifdef USB_SUPPORT_USER_STRING_DESC -uint8_t * USBD_FS_USRStringDesc(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); -#endif /* USB_SUPPORT_USER_STRING_DESC */ - -#if (USBD_LPM_ENABLED == 1) -uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -#endif /* (USBD_LPM_ENABLED == 1) */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables - * @brief Private variables. - * @{ - */ - -USBD_DescriptorsTypeDef FS_Desc = -{ - USBD_FS_DeviceDescriptor -, USBD_FS_LangIDStrDescriptor -, USBD_FS_ManufacturerStrDescriptor -, USBD_FS_ProductStrDescriptor -, USBD_FS_SerialStrDescriptor -, USBD_FS_ConfigStrDescriptor -, USBD_FS_InterfaceStrDescriptor -#if (USBD_LPM_ENABLED == 1) -, USBD_FS_USR_BOSDescriptor -#endif /* (USBD_LPM_ENABLED == 1) */ -}; - -#if defined ( __ICCARM__ ) /* IAR Compiler */ - #pragma data_alignment=4 -#endif /* defined ( __ICCARM__ ) */ -/** USB standard device descriptor. */ -__ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = -{ - 0x12, /*bLength */ - USB_DESC_TYPE_DEVICE, /*bDescriptorType*/ -#if (USBD_LPM_ENABLED == 1) - 0x01, /*bcdUSB */ /* changed to USB version 2.01 - in order to support LPM L1 suspend - resume test of USBCV3.0*/ -#else - 0x00, /*bcdUSB */ -#endif /* (USBD_LPM_ENABLED == 1) */ - 0x02, - 0x02, /*bDeviceClass*/ - 0x02, /*bDeviceSubClass*/ - 0x00, /*bDeviceProtocol*/ - USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ - LOBYTE(USBD_VID), /*idVendor*/ - HIBYTE(USBD_VID), /*idVendor*/ - LOBYTE(USBD_PID_FS), /*idProduct*/ - HIBYTE(USBD_PID_FS), /*idProduct*/ - 0x00, /*bcdDevice rel. 2.00*/ - 0x02, - USBD_IDX_MFC_STR, /*Index of manufacturer string*/ - USBD_IDX_PRODUCT_STR, /*Index of product string*/ - USBD_IDX_SERIAL_STR, /*Index of serial number string*/ - USBD_MAX_NUM_CONFIGURATION /*bNumConfigurations*/ -}; - -/* USB_DeviceDescriptor */ -/** BOS descriptor. */ -#if (USBD_LPM_ENABLED == 1) -#if defined ( __ICCARM__ ) /* IAR Compiler */ - #pragma data_alignment=4 -#endif /* defined ( __ICCARM__ ) */ -__ALIGN_BEGIN uint8_t USBD_FS_BOSDesc[USB_SIZ_BOS_DESC] __ALIGN_END = -{ - 0x5, - USB_DESC_TYPE_BOS, - 0xC, - 0x0, - 0x1, /* 1 device capability*/ - /* device capability*/ - 0x7, - USB_DEVICE_CAPABITY_TYPE, - 0x2, - 0x2, /* LPM capability bit set*/ - 0x0, - 0x0, - 0x0 -}; -#endif /* (USBD_LPM_ENABLED == 1) */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables - * @brief Private variables. - * @{ - */ - -#if defined ( __ICCARM__ ) /* IAR Compiler */ - #pragma data_alignment=4 -#endif /* defined ( __ICCARM__ ) */ - -/** USB lang indentifier descriptor. */ -__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = -{ - USB_LEN_LANGID_STR_DESC, - USB_DESC_TYPE_STRING, - LOBYTE(USBD_LANGID_STRING), - HIBYTE(USBD_LANGID_STRING) -}; - -#if defined ( __ICCARM__ ) /* IAR Compiler */ - #pragma data_alignment=4 -#endif /* defined ( __ICCARM__ ) */ -/* Internal string descriptor. */ -__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END; - -/** - * @} - */ - -/** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions - * @brief Private functions. - * @{ - */ - -/** - * @brief Return the device descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - *length = sizeof(USBD_FS_DeviceDesc); - return USBD_FS_DeviceDesc; -} - -/** - * @brief Return the LangID string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - *length = sizeof(USBD_LangIDDesc); - return USBD_LangIDDesc; -} - -/** - * @brief Return the product string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - if(speed == 0) - { - USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); - } - else - { - USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - -/** - * @brief Return the manufacturer string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); - return USBD_StrDesc; -} - -/** - * @brief Return the serial number string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - if(speed == USBD_SPEED_HIGH) - { - USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); - } - else - { - USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - -/** - * @brief Return the configuration string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - if(speed == USBD_SPEED_HIGH) - { - USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); - } - else - { - USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - -/** - * @brief Return the interface string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - if(speed == 0) - { - USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); - } - else - { - USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - -#if (USBD_LPM_ENABLED == 1) -/** - * @brief Return the BOS descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - *length = sizeof(USBD_FS_BOSDesc); - return (uint8_t*)USBD_FS_BOSDesc; -} -#endif /* (USBD_LPM_ENABLED == 1) */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/mx.scratch b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/mx.scratch deleted file mode 100644 index aafcf5af6..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/mx.scratch +++ /dev/null @@ -1,91 +0,0 @@ - - -D:\VS\brianTPM\Samples\Nucleo-TPM\L476RG\\Nucleo-L476RG -C -..\Drivers\CMSIS -C:\Users\Stefanth\STM32Cube\Repository\STM32Cube_FW_L4_V1.11.0\Drivers\CMSIS -TrueSTUDIO -0 - - - - - - - - - - - - - - - - - Nucleo-L476RG - STM32L476RGTx - 0x200 - 0xf000 - - NUCLEO-L476RG - - true - swd - - 1 - - - - - - - - - - - - __weak=__attribute__((weak)) - __packed=__attribute__((__packed__)) - - - - - - - USE_FULL_LL_DRIVER - MBEDTLS_CONFIG_FILE="mbedtls_config.h" - - - - - ..\Inc - ..\Drivers\STM32L4xx_HAL_Driver\Inc - ..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy - ..\Middlewares\ST\STM32_USB_Device_Library\Core\Inc - ..\Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Inc - ..\Drivers\CMSIS\Device\ST\STM32L4xx\Include - ..\Drivers\CMSIS\Include - - - - - - true - false - - - - Inc - - - Src - - - Drivers - - - Middlewares - - - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/startup/startup_stm32l476xx.s b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/startup/startup_stm32l476xx.s deleted file mode 100644 index f3537008f..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/startup/startup_stm32l476xx.s +++ /dev/null @@ -1,524 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32l476xx.s - * @author MCD Application Team - * @brief STM32L476xx devices vector table GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address, - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF1E0F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* Atollic update: set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - -LoopForever: - b LoopForever - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex-M4. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_PVM_IRQHandler - .word TAMP_STAMP_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word CAN1_TX_IRQHandler - .word CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM15_IRQHandler - .word TIM1_UP_TIM16_IRQHandler - .word TIM1_TRG_COM_TIM17_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word DFSDM1_FLT3_IRQHandler - .word TIM8_BRK_IRQHandler - .word TIM8_UP_IRQHandler - .word TIM8_TRG_COM_IRQHandler - .word TIM8_CC_IRQHandler - .word ADC3_IRQHandler - .word FMC_IRQHandler - .word SDMMC1_IRQHandler - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_DAC_IRQHandler - .word TIM7_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_IRQHandler - .word DMA2_Channel5_IRQHandler - .word DFSDM1_FLT0_IRQHandler - .word DFSDM1_FLT1_IRQHandler - .word DFSDM1_FLT2_IRQHandler - .word COMP_IRQHandler - .word LPTIM1_IRQHandler - .word LPTIM2_IRQHandler - .word OTG_FS_IRQHandler - .word DMA2_Channel6_IRQHandler - .word DMA2_Channel7_IRQHandler - .word LPUART1_IRQHandler - .word QUADSPI_IRQHandler - .word I2C3_EV_IRQHandler - .word I2C3_ER_IRQHandler - .word SAI1_IRQHandler - .word SAI2_IRQHandler - .word SWPMI1_IRQHandler - .word TSC_IRQHandler - .word LCD_IRQHandler - .word 0 - .word RNG_IRQHandler - .word FPU_IRQHandler - - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_PVM_IRQHandler - .thumb_set PVD_PVM_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM15_IRQHandler - .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM16_IRQHandler - .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM17_IRQHandler - .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak DFSDM1_FLT3_IRQHandler - .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler - - .weak TIM8_BRK_IRQHandler - .thumb_set TIM8_BRK_IRQHandler,Default_Handler - - .weak TIM8_UP_IRQHandler - .thumb_set TIM8_UP_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_IRQHandler - .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak ADC3_IRQHandler - .thumb_set ADC3_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak SDMMC1_IRQHandler - .thumb_set SDMMC1_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_IRQHandler - .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - - .weak DFSDM1_FLT0_IRQHandler - .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler - - .weak DFSDM1_FLT1_IRQHandler - .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler - - .weak DFSDM1_FLT2_IRQHandler - .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler - - .weak COMP_IRQHandler - .thumb_set COMP_IRQHandler,Default_Handler - - .weak LPTIM1_IRQHandler - .thumb_set LPTIM1_IRQHandler,Default_Handler - - .weak LPTIM2_IRQHandler - .thumb_set LPTIM2_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Channel6_IRQHandler - .thumb_set DMA2_Channel6_IRQHandler,Default_Handler - - .weak DMA2_Channel7_IRQHandler - .thumb_set DMA2_Channel7_IRQHandler,Default_Handler - - .weak LPUART1_IRQHandler - .thumb_set LPUART1_IRQHandler,Default_Handler - - .weak QUADSPI_IRQHandler - .thumb_set QUADSPI_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak SAI1_IRQHandler - .thumb_set SAI1_IRQHandler,Default_Handler - - .weak SAI2_IRQHandler - .thumb_set SAI2_IRQHandler,Default_Handler - - .weak SWPMI1_IRQHandler - .thumb_set SWPMI1_IRQHandler,Default_Handler - - .weak TSC_IRQHandler - .thumb_set TSC_IRQHandler,Default_Handler - - .weak LCD_IRQHandler - .thumb_set LCD_IRQHandler,Default_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.cproject b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.cproject deleted file mode 100644 index 74237474d..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.cproject +++ /dev/null @@ -1,325 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.mxproject b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.mxproject deleted file mode 100644 index 8142fc17b..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.mxproject +++ /dev/null @@ -1,14 +0,0 @@ -[PreviousGenFiles] -HeaderPath=D:/VS/brianTPM/Samples/Nucleo-TPM/L4A6RG/Inc -HeaderFiles=usb_device.h;usbd_conf.h;usbd_desc.h;usbd_cdc_if.h;stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h; -SourcePath=D:/VS/brianTPM/Samples/Nucleo-TPM/L4A6RG/Src -SourceFiles=usb_device.c;usbd_conf.c;usbd_desc.c;usbd_cdc_if.c;stm32l4xx_it.c;stm32l4xx_hal_msp.c;main.c; - -[PreviousLibFiles] -LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h;Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4a6xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h; - -[PreviousUsedTStudioFiles] -SourceFiles=..\Src\main.c;..\Src\usb_device.c;..\Src\usbd_conf.c;..\Src\usbd_desc.c;..\Src\usbd_cdc_if.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c;../\Src/system_stm32l4xx.c;../Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;null;../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c;../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c;../Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c;../Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c; -HeaderPath=..\Drivers\STM32L4xx_HAL_Driver\Inc;..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;..\Middlewares\ST\STM32_USB_Device_Library\Core\Inc;..\Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Inc;..\Drivers\CMSIS\Device\ST\STM32L4xx\Include;..\Drivers\CMSIS\Include;..\Inc; -CDefines=__weak:__attribute__((weak));__packed:__attribute__((__packed__)); - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.project b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.project deleted file mode 100644 index 7413f2942..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.project +++ /dev/null @@ -1,160 +0,0 @@ - - - Nucleo-L4A6RG - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?children? - ?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\|| - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc:/STM32100B-EVAL/Debug} - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - Inc/Platform - 2 - PARENT-1-PROJECT_LOC/Shared/Platform/include - - - Inc/TPMCmd - 2 - PARENT-3-PROJECT_LOC/TPMCmd/tpm/include - - - Inc/TPMDevice - 2 - PARENT-1-PROJECT_LOC/Shared/TPMDevice/include - - - Middlewares/Platform - 2 - PARENT-1-PROJECT_LOC/Shared/Platform/src - - - Middlewares/TPMCmd - 2 - PARENT-3-PROJECT_LOC/TPMCmd/tpm/src - - - Middlewares/TPMDevice - 2 - PARENT-1-PROJECT_LOC/Shared/TPMDevice/src - - - Middlewares/WolfCypt - 2 - virtual:/virtual - - - Src/syscalls.c - 1 - $%7BPARENT-1-PROJECT_LOC%7D/Shared/syscalls.c - - - Middlewares/WolfCypt/aes.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/aes.c - - - Middlewares/WolfCypt/ecc.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/ecc.c - - - Middlewares/WolfCypt/integer.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/integer.c - - - Middlewares/WolfCypt/memory.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/memory.c - - - Middlewares/WolfCypt/sha.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/sha.c - - - Middlewares/WolfCypt/sha256.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/sha256.c - - - Middlewares/WolfCypt/sha512.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/sha512.c - - - Middlewares/WolfCypt/tfm.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/tfm.c - - - Middlewares/WolfCypt/wolfmath.c - 1 - PARENT-3-PROJECT_LOC/external/wolfssl/wolfcrypt/src/wolfmath.c - - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.settings/com.atollic.truestudio.debug.hardware_device.prefs b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.settings/com.atollic.truestudio.debug.hardware_device.prefs deleted file mode 100644 index 2fed9c1af..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.settings/com.atollic.truestudio.debug.hardware_device.prefs +++ /dev/null @@ -1,11 +0,0 @@ -BOARD=None -CODE_LOCATION=FLASH -ENDIAN=Little-endian -MCU=STM32L4A6RG -MCU_VENDOR=STMicroelectronics -MODEL=Lite -PROBE=ST-LINK -PROJECT_FORMAT_VERSION=2 -TARGET=ARM\u00AE -VERSION=4.1.0 -eclipse.preferences.version=1 diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.settings/language.settings.xml b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.settings/language.settings.xml deleted file mode 100644 index 175a20393..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.settings/language.settings.xml +++ /dev/null @@ -1,20 +0,0 @@ - - - - - - - - - - - - - - - - - - - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.settings/org.eclipse.cdt.managedbuilder.core.prefs deleted file mode 100644 index 66eb6736f..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/.settings/org.eclipse.cdt.managedbuilder.core.prefs +++ /dev/null @@ -1,11 +0,0 @@ -eclipse.preferences.version=1 -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/CPATH/delimiter=; -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/CPATH/operation=remove -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/C_INCLUDE_PATH/delimiter=; -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/C_INCLUDE_PATH/operation=remove -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/append=true -environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.1518366166/appendContributed=true -environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/LIBRARY_PATH/delimiter=; -environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/LIBRARY_PATH/operation=remove -environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/append=true -environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.1518366166/appendContributed=true diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4a6xx.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4a6xx.h deleted file mode 100644 index df8de8ec8..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4a6xx.h +++ /dev/null @@ -1,20127 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4a6xx.h - * @author MCD Application Team - * @brief CMSIS STM32L4A6xx Device Peripheral Access Layer Header File. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS_Device - * @{ - */ - -/** @addtogroup stm32l4a6xx - * @{ - */ - -#ifndef __STM32L4A6xx_H -#define __STM32L4A6xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32L4XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum -{ -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */ - TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ - TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ - TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ - DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */ - DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */ - DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */ - COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ - LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ - DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ - LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ - QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */ - SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */ - SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */ - TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ - LCD_IRQn = 78, /*!< LCD global interrupt */ - AES_IRQn = 79, /*!< AES global interrupt */ - HASH_RNG_IRQn = 80, /*!< HASH and RNG global interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - CRS_IRQn = 82, /*!< CRS global interrupt */ - I2C4_EV_IRQn = 83, /*!< I2C4 Event interrupt */ - I2C4_ER_IRQn = 84, /*!< I2C4 Error interrupt */ - DCMI_IRQn = 85, /*!< DCMI global interrupt */ - CAN2_TX_IRQn = 86, /*!< CAN2 TX interrupt */ - CAN2_RX0_IRQn = 87, /*!< CAN2 RX0 interrupt */ - CAN2_RX1_IRQn = 88, /*!< CAN2 RX1 interrupt */ - CAN2_SCE_IRQn = 89, /*!< CAN2 SCE interrupt */ - DMA2D_IRQn = 90 /*!< DMA2D global interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_stm32l4xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ - __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ - __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ - __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ - uint32_t RESERVED1; /*!< Reserved, 0x1C */ - __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ - __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ - __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ - uint32_t RESERVED2; /*!< Reserved, 0x2C */ - __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ - __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ - uint32_t RESERVED3; /*!< Reserved, 0x44 */ - uint32_t RESERVED4; /*!< Reserved, 0x48 */ - __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ - uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ - __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ - __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ - __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ - __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ - uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ - __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ - __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ - __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ - __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ - uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ - __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ - __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ - uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ - uint32_t RESERVED9; /*!< Reserved, 0x0AC */ - __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ - -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ - uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ - __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */ -} ADC_Common_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ - __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ - __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ - __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ - __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ - __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ - __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ -} DAC_TypeDef; - -/** - * @brief DFSDM module registers - */ -typedef struct -{ - __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ - __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ - __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ - __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ - __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ - __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ - __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ - __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ - __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ - __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ - __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ - __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ - __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ - __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ - __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ -} DFSDM_Filter_TypeDef; - -/** - * @brief DFSDM channel configuration registers - */ -typedef struct -{ - __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ - __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ - __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and - short circuit detector register, Address offset: 0x08 */ - __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ - __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ -} DFSDM_Channel_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ - __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ -} DBGMCU_TypeDef; - - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register */ -} DMA_Request_TypeDef; - -/* Legacy define */ -#define DMA_request_TypeDef DMA_Request_TypeDef - - -/** - * @brief DMA2D Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ - __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ - __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ - __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ - __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ - __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ - __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ - __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ - __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ - __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ - __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ - __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ - __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ - __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ - __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ - __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ - __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ - __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ - __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ - __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ - uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ - __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ - __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ -} DMA2D_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ - __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ - __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ - __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ - __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ - __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ - __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ - __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ - __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ - __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ - __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ -} EXTI_TypeDef; - - -/** - * @brief Firewall - */ - -typedef struct -{ - __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ - __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ - __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ - __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ - __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ - __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ - uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ - __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ -} FIREWALL_TypeDef; - - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ - __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ - __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ - __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ - __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ - __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ - __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ - __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ - uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */ - __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ - __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ - __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ - __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ -} FLASH_TypeDef; - - -/** - * @brief Flexible Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FMC_Bank1_TypeDef; - -/** - * @brief Flexible Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FMC_Bank1E_TypeDef; - -/** - * @brief Flexible Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ - __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ - __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ - __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ -} FMC_Bank3_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - -} GPIO_TypeDef; - - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ - __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ - __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ - __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ - __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ - __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ - __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ - __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ - __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ -} IWDG_TypeDef; - -/** - * @brief LCD - */ - -typedef struct -{ - __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ - __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ - __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ - __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ -} LCD_TypeDef; - -/** - * @brief LPTIMER - */ -typedef struct -{ - __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ - __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ - __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ - __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ - __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ - __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ -} LPTIM_TypeDef; - -/** - * @brief Operational Amplifier (OPAMP) - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ - __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ - __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ -} OPAMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ -} OPAMP_Common_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ - __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ - __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ - __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ - __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ - __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ - __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ - __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ - __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ - __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ - __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ - __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ - __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ - __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ - __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ - __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ - __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ - __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ - __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ - __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ - __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ - __IO uint32_t PUCRI; /*!< Pull_up control register of portI, Address offset: 0x60 */ - __IO uint32_t PDCRI; /*!< Pull_Down control register of portI, Address offset: 0x64 */ -} PWR_TypeDef; - - -/** - * @brief QUAD Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ - __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ - __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ - __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ - __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ - __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ - __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ - __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ - __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ - __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ - __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ -} QUADSPI_TypeDef; - - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ - __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */ - __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */ - __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ - __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ - __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ - uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ - __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ - __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ - __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ - __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ - __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ - __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ - __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ - uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ - __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ - __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ - __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ - uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ - __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ - uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ - __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ - __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ - __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - uint32_t reserved; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ - __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ - __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ - __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ - __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ - __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ - __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ - __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ - __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ - __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ - __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ - __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ - __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ -} RTC_TypeDef; - - -/** - * @brief Serial Audio Interface - */ - -typedef struct -{ - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ -} SAI_TypeDef; - -typedef struct -{ - __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ - __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ - __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ - __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ - __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ - __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ -} SAI_Block_TypeDef; - - -/** - * @brief Secure digital input/output Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ -} SDMMC_TypeDef; - - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ - __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ - __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ - __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ - __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ -} SPI_TypeDef; - - -/** - * @brief Single Wire Protocol Master Interface SPWMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ - __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ - uint32_t RESERVED1; /*!< Reserved, 0x08 */ - __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ - __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ - __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ - __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ - __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ - __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ -} SWPMI_TypeDef; - - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ - __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ - __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ - __IO uint32_t SWPR2; /*!< SYSCFG SRAM2 write protection register 2, Address offset: 0x28 */ -} SYSCFG_TypeDef; - - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ - __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ - __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ - __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ - __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ - __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ -} TIM_TypeDef; - - -/** - * @brief Touch Sensing Controller (TSC) - */ - -typedef struct -{ - __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ - __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ - __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ - __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ - __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ - __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ - __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ -} TSC_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - uint16_t RESERVED2; /*!< Reserved, 0x12 */ - __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ - uint16_t RESERVED3; /*!< Reserved, 0x1A */ - __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ - __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - uint16_t RESERVED4; /*!< Reserved, 0x26 */ - __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - uint16_t RESERVED5; /*!< Reserved, 0x2A */ -} USART_TypeDef; - -/** - * @brief VREFBUF - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ - __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ -} VREFBUF_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief AES hardware accelerator - */ - -typedef struct -{ - __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ - __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ - __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ - __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ - __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ - __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ - __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ - __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ - __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ - __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ - __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ - __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ - __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ - __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ - __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ - __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ - __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ - __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ - __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ - __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ - __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ - __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ - __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */ -} AES_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ - __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ -} HASH_TypeDef; - -/** - * @brief HASH_DIGEST - */ - -typedef struct -{ - __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ -} HASH_DIGEST_TypeDef; - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @brief USB_OTG_Core_register - */ -typedef struct -{ - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/ - __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - uint32_t Reserved30[2]; /* Reserved 030h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ - __IO uint32_t GHWCFG1; /* User HW config1 044h*/ - __IO uint32_t GHWCFG2; /* User HW config2 048h*/ - __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/ - uint32_t Reserved6; /* Reserved 050h*/ - __IO uint32_t GLPMCFG; /* LPM Register 054h*/ - __IO uint32_t GPWRDN; /* Power Down Register 058h*/ - __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/ - __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/ - uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */ -} USB_OTG_GlobalTypeDef; - -/** - * @brief USB_OTG_device_Registers - */ -typedef struct -{ - __IO uint32_t DCFG; /* dev Configuration Register 800h*/ - __IO uint32_t DCTL; /* dev Control Register 804h*/ - __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ - uint32_t Reserved0C; /* Reserved 80Ch*/ - __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ - __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ - __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ - __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ - __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ - __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ - __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ - __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ - __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ - uint32_t Reserved40; /* dedicated EP mask 840h*/ - __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ - uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ -} USB_OTG_DeviceTypeDef; - -/** - * @brief USB_OTG_IN_Endpoint-Specific_Register - */ -typedef struct -{ - __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ - __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ - __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ - __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ - uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ -} USB_OTG_INEndpointTypeDef; - -/** - * @brief USB_OTG_OUT_Endpoint-Specific_Registers - */ -typedef struct -{ - __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ - __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ - __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ - uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ -} USB_OTG_OUTEndpointTypeDef; - -/** - * @brief USB_OTG_Host_Mode_Register_Structures - */ -typedef struct -{ - __IO uint32_t HCFG; /* Host Configuration Register 400h*/ - __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /* Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ -} USB_OTG_HostTypeDef; - -/** - * @brief USB_OTG_Host_Channel_Specific_Registers - */ -typedef struct -{ - __IO uint32_t HCCHAR; - __IO uint32_t HCSPLT; - __IO uint32_t HCINT; - __IO uint32_t HCINTMSK; - __IO uint32_t HCTSIZ; - __IO uint32_t HCDMA; - uint32_t Reserved[2]; -} USB_OTG_HostChannelTypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */ -#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 256 KB) base address */ -#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(64 KB) base address */ -#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ -#define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */ -#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */ - -#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */ -#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ - -/* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE - -#define SRAM1_SIZE_MAX ((uint32_t)0x00040000U) /*!< maximum SRAM1 size (up to 256 KBytes) */ -#define SRAM2_SIZE ((uint32_t)0x00010000U) /*!< SRAM2 size (64 KBytes) */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) - -#define FMC_BANK1 FMC_BASE -#define FMC_BANK1_1 FMC_BANK1 -#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U) -#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U) -#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U) -#define FMC_BANK3 (FMC_BASE + 0x20000000U) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) -#define LCD_BASE (APB1PERIPH_BASE + 0x2400U) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) -#define CRS_BASE (APB1PERIPH_BASE + 0x6000U) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) -#define I2C4_BASE (APB1PERIPH_BASE + 0x8400U) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) -#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) -#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) -#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) -#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) -#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) - - -/*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) -#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) -#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) -#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) -#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) -#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400U) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800U) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U) -#define SAI2_Block_A_BASE (SAI2_BASE + 0x004) -#define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U) -#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) -#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) -#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) -#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60) -#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80) -#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0) -#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0) -#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0) -#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100) -#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180) -#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200) -#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) - -/*!< AHB1 peripherals */ -#define DMA1_BASE (AHB1PERIPH_BASE) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) -#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) -#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) -#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) - - -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) -#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) - - -#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) -#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) -#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) -#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) - - -/*!< AHB2 peripherals */ -#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) -#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) -#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) -#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) -#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) -#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U) -#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U) -#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) -#define GPIOI_BASE (AHB2PERIPH_BASE + 0x2000U) - -#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U) - -#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) -#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U) -#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U) -#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) - -#define DCMI_BASE (AHB2PERIPH_BASE + 0x08050000U) - -#define AES_BASE (AHB2PERIPH_BASE + 0x08060000U) -#define HASH_BASE (AHB2PERIPH_BASE + 0x08060400U) -#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x08060710U) -#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) - - -/*!< FMC Banks registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) - -/* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t)0xE0042000U) - -/*!< USB registers base address */ -#define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U) - -#define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U) -#define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U) -#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U) -#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U) -#define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_HOST_BASE ((uint32_t)0x00000400U) -#define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U) -#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U) -#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U) -#define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U) -#define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U) -#define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U) - - -#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ -#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define LCD ((LCD_TypeDef *) LCD_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CRS ((CRS_TypeDef *) CRS_BASE) -#define CAN ((CAN_TypeDef *) CAN1_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define I2C4 ((I2C_TypeDef *) I2C4_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC1_BASE) -#define DAC1 ((DAC_TypeDef *) DAC1_BASE) -#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) -#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) -#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) -#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE) -#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) -#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) -#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) -#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) - -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) -#define COMP1 ((COMP_TypeDef *) COMP1_BASE) -#define COMP2 ((COMP_TypeDef *) COMP2_BASE) -#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) -#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define TIM15 ((TIM_TypeDef *) TIM15_BASE) -#define TIM16 ((TIM_TypeDef *) TIM16_BASE) -#define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define SAI1 ((SAI_TypeDef *) SAI1_BASE) -#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) -#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) -#define SAI2 ((SAI_TypeDef *) SAI2_BASE) -#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) -#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) -#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) -#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) -#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) -#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) -#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) -#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) -#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) -#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) -#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) -#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) -#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) -#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) -/* Aliases to keep compatibility after DFSDM renaming */ -#define DFSDM_Channel0 DFSDM1_Channel0 -#define DFSDM_Channel1 DFSDM1_Channel1 -#define DFSDM_Channel2 DFSDM1_Channel2 -#define DFSDM_Channel3 DFSDM1_Channel3 -#define DFSDM_Channel4 DFSDM1_Channel4 -#define DFSDM_Channel5 DFSDM1_Channel5 -#define DFSDM_Channel6 DFSDM1_Channel6 -#define DFSDM_Channel7 DFSDM1_Channel7 -#define DFSDM_Filter0 DFSDM1_Filter0 -#define DFSDM_Filter1 DFSDM1_Filter1 -#define DFSDM_Filter2 DFSDM1_Filter2 -#define DFSDM_Filter3 DFSDM1_Filter3 -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define TSC ((TSC_TypeDef *) TSC_BASE) - -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) -#define HASH ((HASH_TypeDef *) HASH_BASE) -#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) -#define AES ((AES_TypeDef *) AES_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) - - -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE) - - -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) -#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) -#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE) - - -#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) -#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) -#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) - -#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) - -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - -/** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ - -/* - * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) - */ -#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ - -/******************** Bit definition for ADC_ISR register *******************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ -#define ADC_ISR_EOSMP_Pos (1U) -#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ -#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ -#define ADC_ISR_EOC_Pos (2U) -#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ -#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ -#define ADC_ISR_EOS_Pos (3U) -#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ -#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ -#define ADC_ISR_OVR_Pos (4U) -#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ -#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ -#define ADC_ISR_JEOC_Pos (5U) -#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ -#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ -#define ADC_ISR_JEOS_Pos (6U) -#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ -#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ -#define ADC_ISR_AWD1_Pos (7U) -#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ -#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) -#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ -#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) -#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ -#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ -#define ADC_ISR_JQOVF_Pos (10U) -#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ -#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ - -/******************** Bit definition for ADC_IER register *******************/ -#define ADC_IER_ADRDYIE_Pos (0U) -#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ -#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ -#define ADC_IER_EOSMPIE_Pos (1U) -#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ -#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ -#define ADC_IER_EOCIE_Pos (2U) -#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ -#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ -#define ADC_IER_EOSIE_Pos (3U) -#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ -#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ -#define ADC_IER_OVRIE_Pos (4U) -#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ -#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ -#define ADC_IER_JEOCIE_Pos (5U) -#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ -#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ -#define ADC_IER_JEOSIE_Pos (6U) -#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ -#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ -#define ADC_IER_AWD1IE_Pos (7U) -#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ -#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ -#define ADC_IER_AWD2IE_Pos (8U) -#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ -#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ -#define ADC_IER_AWD3IE_Pos (9U) -#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ -#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ -#define ADC_IER_JQOVFIE_Pos (10U) -#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ -#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ - -/* Legacy defines */ -#define ADC_IER_ADRDY (ADC_IER_ADRDYIE) -#define ADC_IER_EOSMP (ADC_IER_EOSMPIE) -#define ADC_IER_EOC (ADC_IER_EOCIE) -#define ADC_IER_EOS (ADC_IER_EOSIE) -#define ADC_IER_OVR (ADC_IER_OVRIE) -#define ADC_IER_JEOC (ADC_IER_JEOCIE) -#define ADC_IER_JEOS (ADC_IER_JEOSIE) -#define ADC_IER_AWD1 (ADC_IER_AWD1IE) -#define ADC_IER_AWD2 (ADC_IER_AWD2IE) -#define ADC_IER_AWD3 (ADC_IER_AWD3IE) -#define ADC_IER_JQOVF (ADC_IER_JQOVFIE) - -/******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) -#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ -#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ -#define ADC_CR_ADDIS_Pos (1U) -#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ -#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ -#define ADC_CR_ADSTART_Pos (2U) -#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ -#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ -#define ADC_CR_JADSTART_Pos (3U) -#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ -#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ -#define ADC_CR_ADSTP_Pos (4U) -#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ -#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ -#define ADC_CR_JADSTP_Pos (5U) -#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ -#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ -#define ADC_CR_ADVREGEN_Pos (28U) -#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ -#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ -#define ADC_CR_DEEPPWD_Pos (29U) -#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ -#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ -#define ADC_CR_ADCALDIF_Pos (30U) -#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ -#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ -#define ADC_CR_ADCAL_Pos (31U) -#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ -#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ - -/******************** Bit definition for ADC_CFGR register ******************/ -#define ADC_CFGR_DMAEN_Pos (0U) -#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ -#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ -#define ADC_CFGR_DMACFG_Pos (1U) -#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ -#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ - -#define ADC_CFGR_DFSDMCFG_Pos (2U) -#define ADC_CFGR_DFSDMCFG_Msk (0x1U << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */ -#define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk /*!< ADC DFSDM mode configuration */ - -#define ADC_CFGR_RES_Pos (3U) -#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ -#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ -#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ -#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ - -#define ADC_CFGR_ALIGN_Pos (5U) -#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ - -#define ADC_CFGR_EXTSEL_Pos (6U) -#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ -#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ -#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ - -#define ADC_CFGR_EXTEN_Pos (10U) -#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ -#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ -#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ - -#define ADC_CFGR_OVRMOD_Pos (12U) -#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ -#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ -#define ADC_CFGR_CONT_Pos (13U) -#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ -#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ -#define ADC_CFGR_AUTDLY_Pos (14U) -#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ -#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ - -#define ADC_CFGR_DISCEN_Pos (16U) -#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ -#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ - -#define ADC_CFGR_DISCNUM_Pos (17U) -#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ -#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ -#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ - -#define ADC_CFGR_JDISCEN_Pos (20U) -#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ -#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ -#define ADC_CFGR_JQM_Pos (21U) -#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ -#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ -#define ADC_CFGR_AWD1SGL_Pos (22U) -#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ -#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ -#define ADC_CFGR_AWD1EN_Pos (23U) -#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ -#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ -#define ADC_CFGR_JAWD1EN_Pos (24U) -#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ -#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ -#define ADC_CFGR_JAUTO_Pos (25U) -#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ -#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ - -#define ADC_CFGR_AWD1CH_Pos (26U) -#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ -#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ -#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ - -#define ADC_CFGR_JQDIS_Pos (31U) -#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ -#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ - -/******************** Bit definition for ADC_CFGR2 register *****************/ -#define ADC_CFGR2_ROVSE_Pos (0U) -#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ -#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ -#define ADC_CFGR2_JOVSE_Pos (1U) -#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ -#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ - -#define ADC_CFGR2_OVSR_Pos (2U) -#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - -#define ADC_CFGR2_OVSS_Pos (5U) -#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ -#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ - -#define ADC_CFGR2_TROVS_Pos (9U) -#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ -#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ -#define ADC_CFGR2_ROVSM_Pos (10U) -#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ -#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ - -/******************** Bit definition for ADC_SMPR1 register *****************/ -#define ADC_SMPR1_SMP0_Pos (0U) -#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ -#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR1_SMP1_Pos (3U) -#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ -#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR1_SMP2_Pos (6U) -#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR1_SMP3_Pos (9U) -#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR1_SMP4_Pos (12U) -#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ -#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR1_SMP5_Pos (15U) -#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ -#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR1_SMP6_Pos (18U) -#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR1_SMP7_Pos (21U) -#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR1_SMP8_Pos (24U) -#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ -#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ - -#define ADC_SMPR1_SMP9_Pos (27U) -#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ -#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ - -#define ADC_SMPR1_SMPPLUS_Pos (31U) -#define ADC_SMPR1_SMPPLUS_Msk (0x1U << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ -#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ - -/******************** Bit definition for ADC_SMPR2 register *****************/ -#define ADC_SMPR2_SMP10_Pos (0U) -#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ -#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR2_SMP11_Pos (3U) -#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ -#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR2_SMP12_Pos (6U) -#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR2_SMP13_Pos (9U) -#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR2_SMP14_Pos (12U) -#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ -#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR2_SMP15_Pos (15U) -#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ -#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR2_SMP16_Pos (18U) -#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR2_SMP17_Pos (21U) -#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR2_SMP18_Pos (24U) -#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ -#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ - -/******************** Bit definition for ADC_TR1 register *******************/ -#define ADC_TR1_LT1_Pos (0U) -#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ -#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ -#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ -#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ -#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ -#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ -#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ -#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ -#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ -#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ -#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ -#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ -#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ - -#define ADC_TR1_HT1_Pos (16U) -#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ -#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ -#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ -#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ -#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ -#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ -#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ -#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ -#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ -#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ -#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ -#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ -#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ - -/******************** Bit definition for ADC_TR2 register *******************/ -#define ADC_TR2_LT2_Pos (0U) -#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ -#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ -#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ -#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ -#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ -#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ -#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ -#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ -#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ - -#define ADC_TR2_HT2_Pos (16U) -#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ -#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ -#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ -#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ -#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ -#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ -#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ -#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ -#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ - -/******************** Bit definition for ADC_TR3 register *******************/ -#define ADC_TR3_LT3_Pos (0U) -#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ -#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ -#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ -#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ -#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ -#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ -#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ -#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ -#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ - -#define ADC_TR3_HT3_Pos (16U) -#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ -#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ -#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ -#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ -#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ -#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ -#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ -#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ -#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ - -/******************** Bit definition for ADC_SQR1 register ******************/ -#define ADC_SQR1_L_Pos (0U) -#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ -#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ -#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ - -#define ADC_SQR1_SQ1_Pos (6U) -#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ -#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ -#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ - -#define ADC_SQR1_SQ2_Pos (12U) -#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ -#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ -#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ - -#define ADC_SQR1_SQ3_Pos (18U) -#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ -#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ -#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ - -#define ADC_SQR1_SQ4_Pos (24U) -#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ -#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ -#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR2 register ******************/ -#define ADC_SQR2_SQ5_Pos (0U) -#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ -#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ -#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ - -#define ADC_SQR2_SQ6_Pos (6U) -#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ -#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ -#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ - -#define ADC_SQR2_SQ7_Pos (12U) -#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ -#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ -#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ - -#define ADC_SQR2_SQ8_Pos (18U) -#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ -#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ -#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ - -#define ADC_SQR2_SQ9_Pos (24U) -#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ -#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ -#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR3 register ******************/ -#define ADC_SQR3_SQ10_Pos (0U) -#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ -#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ -#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ - -#define ADC_SQR3_SQ11_Pos (6U) -#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ -#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ -#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ - -#define ADC_SQR3_SQ12_Pos (12U) -#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ -#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ -#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ - -#define ADC_SQR3_SQ13_Pos (18U) -#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ -#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ -#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ - -#define ADC_SQR3_SQ14_Pos (24U) -#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ -#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ -#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR4 register ******************/ -#define ADC_SQR4_SQ15_Pos (0U) -#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ -#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ -#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ - -#define ADC_SQR4_SQ16_Pos (6U) -#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ -#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ -#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ -#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ -#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ -#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ -#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ -#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ -#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ -#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ -#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ -#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ -#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ -#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ -#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ -#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ -#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ -#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ -#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_JSQR register ******************/ -#define ADC_JSQR_JL_Pos (0U) -#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ -#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ -#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ - -#define ADC_JSQR_JEXTSEL_Pos (2U) -#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ -#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ -#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ - -#define ADC_JSQR_JEXTEN_Pos (6U) -#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ -#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ -#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ -#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ - -#define ADC_JSQR_JSQ1_Pos (8U) -#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ -#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ -#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ -#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ - -#define ADC_JSQR_JSQ2_Pos (14U) -#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ -#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ -#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ -#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ - -#define ADC_JSQR_JSQ3_Pos (20U) -#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ -#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ -#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ -#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ - -#define ADC_JSQR_JSQ4_Pos (26U) -#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ -#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ -#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ -#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for ADC_OFR1 register ******************/ -#define ADC_OFR1_OFFSET1_Pos (0U) -#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ -#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ -#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ - -#define ADC_OFR1_OFFSET1_CH_Pos (26U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ -#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ - -#define ADC_OFR1_OFFSET1_EN_Pos (31U) -#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ -#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ - -/******************** Bit definition for ADC_OFR2 register ******************/ -#define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ -#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ -#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ - -#define ADC_OFR2_OFFSET2_CH_Pos (26U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ -#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ - -#define ADC_OFR2_OFFSET2_EN_Pos (31U) -#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ -#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ - -/******************** Bit definition for ADC_OFR3 register ******************/ -#define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ -#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ -#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ - -#define ADC_OFR3_OFFSET3_CH_Pos (26U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ -#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ - -#define ADC_OFR3_OFFSET3_EN_Pos (31U) -#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ -#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ - -/******************** Bit definition for ADC_OFR4 register ******************/ -#define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ -#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ -#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ - -#define ADC_OFR4_OFFSET4_CH_Pos (26U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ -#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ - -#define ADC_OFR4_OFFSET4_EN_Pos (31U) -#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ -#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ - -/******************** Bit definition for ADC_JDR1 register ******************/ -#define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ -#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_JDR2 register ******************/ -#define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ -#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_JDR3 register ******************/ -#define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ -#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_JDR4 register ******************/ -#define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ -#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ -#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ - -/******************** Bit definition for ADC_AWD2CR register ****************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ -#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_AWD3CR register ****************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ -#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_DIFSEL register ****************/ -#define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ -#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ - -/******************** Bit definition for ADC_CALFACT register ***************/ -#define ADC_CALFACT_CALFACT_S_Pos (0U) -#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ -#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ - -#define ADC_CALFACT_CALFACT_D_Pos (16U) -#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ -#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ -#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ -#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ -#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ -#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ -#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ -#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ - -/************************* ADC Common registers *****************************/ -/******************** Bit definition for ADC_CSR register *******************/ -#define ADC_CSR_ADRDY_MST_Pos (0U) -#define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ -#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ -#define ADC_CSR_EOSMP_MST_Pos (1U) -#define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ -#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ -#define ADC_CSR_EOC_MST_Pos (2U) -#define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ -#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_MST_Pos (3U) -#define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ -#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_MST_Pos (4U) -#define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ -#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ -#define ADC_CSR_JEOC_MST_Pos (5U) -#define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ -#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_MST_Pos (6U) -#define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ -#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_MST_Pos (7U) -#define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ -#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ -#define ADC_CSR_AWD2_MST_Pos (8U) -#define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ -#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ -#define ADC_CSR_AWD3_MST_Pos (9U) -#define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ -#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_MST_Pos (10U) -#define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ -#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ - -#define ADC_CSR_ADRDY_SLV_Pos (16U) -#define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ -#define ADC_CSR_EOSMP_SLV_Pos (17U) -#define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ -#define ADC_CSR_EOC_SLV_Pos (18U) -#define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ -#define ADC_CSR_EOS_SLV_Pos (19U) -#define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ -#define ADC_CSR_OVR_SLV_Pos (20U) -#define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ -#define ADC_CSR_JEOC_SLV_Pos (21U) -#define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ -#define ADC_CSR_JEOS_SLV_Pos (22U) -#define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ -#define ADC_CSR_AWD1_SLV_Pos (23U) -#define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ -#define ADC_CSR_AWD2_SLV_Pos (24U) -#define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ -#define ADC_CSR_AWD3_SLV_Pos (25U) -#define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ -#define ADC_CSR_JQOVF_SLV_Pos (26U) -#define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ - -/******************** Bit definition for ADC_CCR register *******************/ -#define ADC_CCR_DUAL_Pos (0U) -#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ -#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ -#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ -#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ -#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ -#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ -#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ - -#define ADC_CCR_DELAY_Pos (8U) -#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ -#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ -#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ -#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ -#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ -#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ - -#define ADC_CCR_DMACFG_Pos (13U) -#define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ -#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ - -#define ADC_CCR_MDMA_Pos (14U) -#define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ -#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ -#define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ -#define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ - -#define ADC_CCR_CKMODE_Pos (16U) -#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ -#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ -#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ -#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ - -#define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ -#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ -#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ - -#define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ -#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ -#define ADC_CCR_TSEN_Pos (23U) -#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ -#define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ -#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ - -/******************** Bit definition for ADC_CDR register *******************/ -#define ADC_CDR_RDATA_MST_Pos (0U) -#define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ -#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ -#define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ -#define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ -#define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ -#define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ -#define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ -#define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ -#define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ -#define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ -#define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ -#define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ -#define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ -#define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ -#define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ -#define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ -#define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ -#define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ - -#define ADC_CDR_RDATA_SLV_Pos (16U) -#define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ -#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ -#define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ -#define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ -#define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ -#define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ -#define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ -#define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ -#define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ -#define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ -#define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ -#define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ -#define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ -#define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ -#define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ -#define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ -#define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ -#define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ - -/******************************************************************************/ -/* */ -/* Controller Area Network */ -/* */ -/******************************************************************************/ -/*!*/ -#define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ -#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ - -#define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ -#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ -#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ -#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
    © COPYRIGHT(c) 2017 STMicroelectronics
    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx - * @{ - */ - -#ifndef __STM32L4xx_H -#define __STM32L4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L4) -#define STM32L4 -#endif /* STM32L4 */ - -/* Uncomment the line below according to the target STM32L4 device used in your - application - */ - -#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ - !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ - !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ - !defined (STM32L496xx) && !defined (STM32L4A6xx) && \ - !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) - /* #define STM32L431xx */ /*!< STM32L431xx Devices */ - /* #define STM32L432xx */ /*!< STM32L432xx Devices */ - /* #define STM32L433xx */ /*!< STM32L433xx Devices */ - /* #define STM32L442xx */ /*!< STM32L442xx Devices */ - /* #define STM32L443xx */ /*!< STM32L443xx Devices */ - /* #define STM32L451xx */ /*!< STM32L451xx Devices */ - /* #define STM32L452xx */ /*!< STM32L452xx Devices */ - /* #define STM32L462xx */ /*!< STM32L462xx Devices */ - /* #define STM32L471xx */ /*!< STM32L471xx Devices */ - /* #define STM32L475xx */ /*!< STM32L475xx Devices */ - /* #define STM32L476xx */ /*!< STM32L476xx Devices */ - /* #define STM32L485xx */ /*!< STM32L485xx Devices */ - /* #define STM32L486xx */ /*!< STM32L486xx Devices */ - /* #define STM32L496xx */ /*!< STM32L496xx Devices */ - /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ - /* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */ - /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */ - /* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */ - /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */ - /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */ - /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_HAL_DRIVER */ -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number - */ -#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ -#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L4_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L431xx) - #include "stm32l431xx.h" -#elif defined(STM32L432xx) - #include "stm32l432xx.h" -#elif defined(STM32L433xx) - #include "stm32l433xx.h" -#elif defined(STM32L442xx) - #include "stm32l442xx.h" -#elif defined(STM32L443xx) - #include "stm32l443xx.h" -#elif defined(STM32L451xx) - #include "stm32l451xx.h" -#elif defined(STM32L452xx) - #include "stm32l452xx.h" -#elif defined(STM32L462xx) - #include "stm32l462xx.h" -#elif defined(STM32L471xx) - #include "stm32l471xx.h" -#elif defined(STM32L475xx) - #include "stm32l475xx.h" -#elif defined(STM32L476xx) - #include "stm32l476xx.h" -#elif defined(STM32L485xx) - #include "stm32l485xx.h" -#elif defined(STM32L486xx) - #include "stm32l486xx.h" -#elif defined(STM32L496xx) - #include "stm32l496xx.h" -#elif defined(STM32L4A6xx) - #include "stm32l4a6xx.h" -#elif defined(STM32L4R5xx) - #include "stm32l4r5xx.h" -#elif defined(STM32L4R7xx) - #include "stm32l4r7xx.h" -#elif defined(STM32L4R9xx) - #include "stm32l4r9xx.h" -#elif defined(STM32L4S5xx) - #include "stm32l4s5xx.h" -#elif defined(STM32L4S7xx) - #include "stm32l4s7xx.h" -#elif defined(STM32L4S9xx) - #include "stm32l4s9xx.h" -#else - #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l4xx_hal.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L4xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h deleted file mode 100644 index e6e4376fd..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l4xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L4XX_H -#define __SYSTEM_STM32L4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L4xx_System_Exported_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/arm_common_tables.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index 8742a5699..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,136 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. October 2015 -* $Revision: V.1.4.5 a -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -/* extern const q31_t realCoefAQ31[1024]; */ -/* extern const q31_t realCoefBQ31[1024]; */ -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/arm_const_structs.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/arm_const_structs.h deleted file mode 100644 index 726d06eb6..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/arm_const_structs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.h -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/arm_math.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/arm_math.h deleted file mode 100644 index d33f8a9b3..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7154 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2015 ARM Limited. All rights reserved. -* -* $Date: 20. October 2015 -* $Revision: V1.4.5 b -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) - * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - *
    - * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
    - * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
    - *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
    - * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
    - *     pData[i*numCols + j]
- *
    - * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
    - * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
    - * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
    - *     ARM_MATH_SIZE_MISMATCH
- *
    - * Otherwise the functions return - * 
    - *     ARM_MATH_SUCCESS
- *
    - * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
    - *     ARM_MATH_MATRIX_CHECK
- *
    - * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __GNUC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - -#elif defined __ICCARM__ - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - -#elif defined __CSMC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - -#elif defined __TASKING__ - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - -/* - #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) - #define __CLZ __clz - #endif - */ -/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) - static __INLINE uint32_t __CLZ( - q31_t data); - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - } -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - } - - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - } -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE int32_t __QADD( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE int32_t __QSUB( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE uint32_t __SXTB16( - uint32_t x) - { - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; - - - /** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - - /** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - - /** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - - /** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - - /** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f32; - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; - - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - - /** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
    -   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
    - * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
    -   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
    - * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - } - } - - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } - } - - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } - } - - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - float32_t arm_sin_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q31_t arm_sin_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q15_t arm_sin_q15( - q15_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - float32_t arm_cos_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q31_t arm_cos_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
    -   *      x1 = x0 - f(x0)/f'(x0)
-   *
    - * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
    -   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
    - */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in >= 0.0f) - { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - /** - * @brief floating-point Circular write function. - */ - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q15 Circular write function. - */ - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - - /** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - - /** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - - /** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
    -   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
    - * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
    -   *     XF = floor(x)
-   *     YF = floor(y)
-   *
    - * \par - * The interpolated output point is computed as: - * 
    -   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
    - * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - } - - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); - } - - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); - } - - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); - } - - /** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__CSMC__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__TASKING__) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/cmsis_armcc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/cmsis_armcc.h deleted file mode 100644 index 74c49c67d..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/cmsis_armcc.h +++ /dev/null @@ -1,734 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return(result); -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/cmsis_armcc_V6.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/cmsis_armcc_V6.h deleted file mode 100644 index cd13240ce..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/cmsis_armcc_V6.h +++ /dev/null @@ -1,1800 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc_V6.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_ARMCC_V6_H -#define __CMSIS_ARMCC_V6_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get IPSR Register (non-secure) - \details Returns the content of the non-secure IPSR Register when in secure state. - \return IPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get APSR Register (non-secure) - \details Returns the content of the non-secure APSR Register when in secure state. - \return APSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get xPSR Register (non-secure) - \details Returns the content of the non-secure xPSR Register when in secure state. - \return xPSR Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Base Priority with condition (non_secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) -{ - __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); -} -#endif - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Get Process Stack Pointer Limit - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Process Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - - return(result); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Get Main Stack Pointer Limit (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -} - - -#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ -/** - \brief Set Main Stack Pointer Limit (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -} -#endif - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - - -#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ - -/** - \brief Get FPSCR - \details eturns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#define __get_FPSCR __builtin_arm_get_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get FPSCR (non-secure) - \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. - \return Floating Point Status/Control register value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} -#endif - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#define __set_FPSCR __builtin_arm_set_fpscr -#if 0 -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#if (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set FPSCR (non-secure) - \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ - __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} -#endif - -#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __builtin_bswap32 - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} -#endif - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ - /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -/*#define __SSAT __builtin_arm_ssat*/ -#define __SSAT(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat -#if 0 -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) -#endif - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ - - -#if (__ARM_ARCH_8M__ == 1U) - -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH_8M__ == 1U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1U) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/cmsis_gcc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/cmsis_gcc.h deleted file mode 100644 index bb89fbba9..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/cmsis_gcc.h +++ /dev/null @@ -1,1373 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS Cortex-M Core Function/Instruction Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03U) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03U) */ - - -#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief Reverse byte order in signed short value - \details Reverses the byte order in a signed short value with sign extension to integer. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - int32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x04) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -#endif /* __CMSIS_GCC_H */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm0.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm0.h deleted file mode 100644 index 711dad551..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,798 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
    - Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    - Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
    - Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm0plus.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index b04aa3905..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,914 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
    - Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    - Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
    - Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm3.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm3.h deleted file mode 100644 index b4ac4c7b0..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1763 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
    - Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    - Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
    - Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm4.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm4.h deleted file mode 100644 index dc840ebf2..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1937 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
    - Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    - Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
    - Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm7.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm7.h deleted file mode 100644 index 3b7530ad5..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2512 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
    - Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    - Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
    - Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07U) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ -#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1U) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & 0x00000FF0UL) == 0x220UL) - { - return 2UL; /* Double + Single precision FPU */ - } - else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) - { - return 1UL; /* Single precision FPU */ - } - else - { - return 0UL; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1U) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cmFunc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 652a48af0..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cmInstr.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index f474b0e6f..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cmSimd.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cmSimd.h deleted file mode 100644 index 66bf5c2a7..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_cmSimd.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -/*------------------ RealView Compiler -----------------*/ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - -/*------------------ ARM Compiler V6 -------------------*/ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armcc_V6.h" - -/*------------------ GNU Compiler ----------------------*/ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - -/*------------------ ICC Compiler ----------------------*/ -#elif defined ( __ICCARM__ ) - #include - -/*------------------ TI CCS Compiler -------------------*/ -#elif defined ( __TMS470__ ) - #include - -/*------------------ TASKING Compiler ------------------*/ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -/*------------------ COSMIC Compiler -------------------*/ -#elif defined ( __CSMC__ ) - #include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_sc000.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_sc000.h deleted file mode 100644 index 514dbd81b..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,926 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
    - Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    - Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
    - Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_sc300.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_sc300.h deleted file mode 100644 index 8bd18aa31..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1745 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V4.30 - * @date 20. October 2015 - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
    - Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    - Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
    - Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ - #define __STATIC_INLINE static inline - -#else - #error Unknown compiler -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "core_cmInstr.h" /* Core Instruction Access */ -#include "core_cmFunc.h" /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Disable External Interrupt - \details Disables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Pending Interrupt - \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of an external interrupt. - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in NVIC and returns the active bit. - \param [in] IRQn Interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of an interrupt. - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) < 0) - { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of an interrupt. - The interrupt number can be positive to specify an external (device specific) interrupt, - or negative to specify an internal (core) interrupt. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) < 0) - { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h deleted file mode 100644 index 0ae9d0b24..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ /dev/null @@ -1,3309 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_hal_legacy.h - * @author MCD Application Team - * @brief This file contains aliases definition for the STM32Cube HAL constants - * macros and functions maintained for legacy purpose. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_HAL_LEGACY -#define __STM32_HAL_LEGACY - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose - * @{ - */ -#define AES_FLAG_RDERR CRYP_FLAG_RDERR -#define AES_FLAG_WRERR CRYP_FLAG_WRERR -#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF -#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR -#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - -/** - * @} - */ - -/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose - * @{ - */ -#define ADC_RESOLUTION12b ADC_RESOLUTION_12B -#define ADC_RESOLUTION10b ADC_RESOLUTION_10B -#define ADC_RESOLUTION8b ADC_RESOLUTION_8B -#define ADC_RESOLUTION6b ADC_RESOLUTION_6B -#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN -#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED -#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV -#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV -#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV -#define REGULAR_GROUP ADC_REGULAR_GROUP -#define INJECTED_GROUP ADC_INJECTED_GROUP -#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP -#define AWD_EVENT ADC_AWD_EVENT -#define AWD1_EVENT ADC_AWD1_EVENT -#define AWD2_EVENT ADC_AWD2_EVENT -#define AWD3_EVENT ADC_AWD3_EVENT -#define OVR_EVENT ADC_OVR_EVENT -#define JQOVF_EVENT ADC_JQOVF_EVENT -#define ALL_CHANNELS ADC_ALL_CHANNELS -#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS -#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS -#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR -#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 -#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 -#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 -#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO -#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 -#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 -#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE -#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING -#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING -#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING -#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 - -#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY -#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY -#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC -#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC -#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL -#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 -/** - * @} - */ - -/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose - * @{ - */ -#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE -#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE -#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 -#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 -#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 -#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 -#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 -#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 -#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ -#endif -#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR -#if defined(STM32F373xC) || defined(STM32F378xx) -#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 -#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR -#endif /* STM32F373xC || STM32F378xx */ - -#if defined(STM32L0) || defined(STM32L4) -#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON - -#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 -#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 -#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 -#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 -#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 -#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - -#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT -#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT -#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT -#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT -#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 -#if defined(STM32L0) -/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ -/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ -/* to the second dedicated IO (only for COMP2). */ -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 -#else -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 -#endif -#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 -#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 - -#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW -#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH - -/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ -/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ -#if defined(COMP_CSR_LOCK) -#define COMP_FLAG_LOCK COMP_CSR_LOCK -#elif defined(COMP_CSR_COMP1LOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK -#elif defined(COMP_CSR_COMPxLOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK -#endif - -#if defined(STM32L4) -#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 -#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 -#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 -#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 -#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE -#endif - -#if defined(STM32L0) -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER -#else -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED -#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER -#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER -#endif - -#endif -/** - * @} - */ - -/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose - * @{ - */ -#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig -/** - * @} - */ - -/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE -#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define DAC1_CHANNEL_1 DAC_CHANNEL_1 -#define DAC1_CHANNEL_2 DAC_CHANNEL_2 -#define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE 0x00000000U -#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 -#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 -#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE -#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE -#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE - -/** - * @} - */ - -/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP -#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE -#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - - - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD -#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD -#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS -#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES -#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES -#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE -#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE -#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE -#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE -#define OBEX_PCROP OPTIONBYTE_PCROP -#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG -#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE -#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE -#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE -#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD -#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD -#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE -#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD -#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD -#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE -#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD -#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -#define PAGESIZE FLASH_PAGE_SIZE -#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD -#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 -#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 -#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 -#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 -#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST -#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST -#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA -#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB -#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA -#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB -#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE -#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN -#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE -#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN -#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE -#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD -#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP -#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV -#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR -#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA -#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS -#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST -#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR -#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO -#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS -#define OB_WDG_SW OB_IWDG_SW -#define OB_WDG_HW OB_IWDG_HW -#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET -#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET -#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET -#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET -#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR -#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 -#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 -#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 - -/** - * @} - */ - -/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose - * @{ - */ - -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 -#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 -#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 -/** - * @} - */ - - -/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose - * @{ - */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) -#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE -#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE -#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 -#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 -#else -#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE -#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE -#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 -#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 -#endif -/** - * @} - */ - -/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef -#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef -/** - * @} - */ - -/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose - * @{ - */ -#define GET_GPIO_SOURCE GPIO_GET_INDEX -#define GET_GPIO_INDEX GPIO_GET_INDEX - -#if defined(STM32F4) -#define GPIO_AF12_SDMMC GPIO_AF12_SDIO -#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO -#endif - -#if defined(STM32F7) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32L4) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 -#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 -#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 - -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */ - -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L1 */ - -#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH -#endif /* STM32F0 || STM32F3 || STM32F1 */ - -#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose - * @{ - */ - -#if defined(STM32H7) - #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE - #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE - #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET - #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET - #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE - #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE - - #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 - #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 - - #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX - #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX - - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT - #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT - #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT - #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 - #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO - - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT - #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT - #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT - #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP - #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 - #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 - #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT - #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT - #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT - #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT - #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT - #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT - #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT - - #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT - #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING - #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING - #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - - -#endif /* STM32H7 */ - - -/** - * @} - */ - - -/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - -#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER -#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER -#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD -#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD -#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER -#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER -#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE -#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE -#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE -#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE -#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE -#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE -#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE -#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE -#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) -#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX -#endif -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose - * @{ - */ -#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE -#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define KR_KEY_RELOAD IWDG_KEY_RELOAD -#define KR_KEY_ENABLE IWDG_KEY_ENABLE -#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE -#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE -/** - * @} - */ - -/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose - * @{ - */ - -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION -#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS - -#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING -#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING -#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING - -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION -#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/* The following 3 definition have also been present in a temporary version of lptim.h */ -/* They need to be renamed also to the right name, just in case */ -#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/** - * @} - */ - -/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b -#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b -#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b -#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b - -#define NAND_AddressTypedef NAND_AddressTypeDef - -#define __ARRAY_ADDRESS ARRAY_ADDRESS -#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE -#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE -#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE -#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE -/** - * @} - */ - -/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose - * @{ - */ -#define NOR_StatusTypedef HAL_NOR_StatusTypeDef -#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS -#define NOR_ONGOING HAL_NOR_STATUS_ONGOING -#define NOR_ERROR HAL_NOR_STATUS_ERROR -#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT - -#define __NOR_WRITE NOR_WRITE -#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT -/** - * @} - */ - -/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose - * @{ - */ - -#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 -#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 -#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 -#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - -#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 -#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 -#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 - -#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS -#if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL -#endif -/** - * @} - */ - -/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose - * @{ - */ - -/* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD -#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA - -/* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD -#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD -#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD -#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD - -#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef -#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS -#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING -#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR -#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FORMAT_BIN RTC_FORMAT_BIN -#define FORMAT_BCD RTC_FORMAT_BCD - -#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE - -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT - -#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 - -#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE -#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 -#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 - -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 -#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 - -/** - * @} - */ - - -/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE -#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE - -#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE -#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE - -#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE -#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE - -#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE -#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE -/** - * @} - */ - - -/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE -#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE -#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE -#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE -#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE -#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE -#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE -#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE -#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE -#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE -#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose - * @{ - */ -#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE -#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE - -#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE -#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE - -#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE -#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose - * @{ - */ -#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK -#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - -#define TIM_DMABase_CR1 TIM_DMABASE_CR1 -#define TIM_DMABase_CR2 TIM_DMABASE_CR2 -#define TIM_DMABase_SMCR TIM_DMABASE_SMCR -#define TIM_DMABase_DIER TIM_DMABASE_DIER -#define TIM_DMABase_SR TIM_DMABASE_SR -#define TIM_DMABase_EGR TIM_DMABASE_EGR -#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 -#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 -#define TIM_DMABase_CCER TIM_DMABASE_CCER -#define TIM_DMABase_CNT TIM_DMABASE_CNT -#define TIM_DMABase_PSC TIM_DMABASE_PSC -#define TIM_DMABase_ARR TIM_DMABASE_ARR -#define TIM_DMABase_RCR TIM_DMABASE_RCR -#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 -#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 -#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 -#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 -#define TIM_DMABase_BDTR TIM_DMABASE_BDTR -#define TIM_DMABase_DCR TIM_DMABASE_DCR -#define TIM_DMABase_DMAR TIM_DMABASE_DMAR -#define TIM_DMABase_OR1 TIM_DMABASE_OR1 -#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 -#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 -#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 -#define TIM_DMABase_OR2 TIM_DMABASE_OR2 -#define TIM_DMABase_OR3 TIM_DMABASE_OR3 -#define TIM_DMABase_OR TIM_DMABASE_OR - -#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE -#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 -#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 -#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 -#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 -#define TIM_EventSource_COM TIM_EVENTSOURCE_COM -#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER -#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK -#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 - -#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER -#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS -#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS -#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS -#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS -#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS -#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS -#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS -#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS -#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS -#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS -#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS -#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS -#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS -#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS -#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS -#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS -#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS - -/** - * @} - */ - -/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose - * @{ - */ -#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING -#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose - * @{ - */ -#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE -#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE - -#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE -#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE - -#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 -#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 -#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 -#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 - -#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 -#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 -#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 -#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 - -#define __DIV_LPUART UART_DIV_LPUART - -#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE -#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose - * @{ - */ - -#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE -#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE - -#define USARTNACK_ENABLED USART_NACK_ENABLE -#define USARTNACK_DISABLED USART_NACK_DISABLE -/** - * @} - */ - -/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define CFR_BASE WWDG_CFR_BASE - -/** - * @} - */ - -/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose - * @{ - */ -#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 -#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME -#define INAK_TIMEOUT CAN_TIMEOUT_VALUE -#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE -#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) -#define CAN_TXSTATUS_OK ((uint8_t)0x01U) -#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) - -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define VLAN_TAG ETH_VLAN_TAG -#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD -#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD -#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD -#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK -#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK -#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK -#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK - -#define ETH_MMCCR 0x00000100U -#define ETH_MMCRIR 0x00000104U -#define ETH_MMCTIR 0x00000108U -#define ETH_MMCRIMR 0x0000010CU -#define ETH_MMCTIMR 0x00000110U -#define ETH_MMCTGFSCCR 0x0000014CU -#define ETH_MMCTGFMSCCR 0x00000150U -#define ETH_MMCTGFCR 0x00000168U -#define ETH_MMCRFCECR 0x00000194U -#define ETH_MMCRFAECR 0x00000198U -#define ETH_MMCRGUFCR 0x000001C4U - -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ -#if defined(STM32F1) -#else -#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ -#endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ - -/** - * @} - */ - -/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR -#define DCMI_IT_OVF DCMI_IT_OVR -#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI -#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI - -#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop -#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop -#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop - -/** - * @} - */ - -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose - * @{ - */ -#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 -#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 -#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 - -#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 -#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 -#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 -/** - * @} - */ -#endif /* STM32L4 || STM32F7*/ - -/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback -/** - * @} - */ - -/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef -#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef -#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish -#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish -#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish -#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish - -/*HASH Algorithm Selection*/ - -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 -#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 -#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 -#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 - -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH -#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC - -#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY -#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY -/** - * @} - */ - -/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode -#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode -#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode -#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode -#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode -#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) -#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect -#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) -#if defined(STM32L0) -#else -#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) -#endif -#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram -#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown -#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown -#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock -#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock -#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase -#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - - /** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter -#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter -#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter -#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter - -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) - /** - * @} - */ - -/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose - * @{ - */ -#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD -#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg -#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown -#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor -#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg -#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown -#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor -#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler -#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD -#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler -#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback -#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive -#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive -#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC -#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC -#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - -#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL -#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING -#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING -#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING -#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING -#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING -#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING - -#define CR_OFFSET_BB PWR_CR_OFFSET_BB -#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB -#define PMODE_BIT_NUMBER VOS_BIT_NUMBER -#define CR_PMODE_BB CR_VOS_BB - -#define DBP_BitNumber DBP_BIT_NUMBER -#define PVDE_BitNumber PVDE_BIT_NUMBER -#define PMODE_BitNumber PMODE_BIT_NUMBER -#define EWUP_BitNumber EWUP_BIT_NUMBER -#define FPDS_BitNumber FPDS_BIT_NUMBER -#define ODEN_BitNumber ODEN_BIT_NUMBER -#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER -#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER -#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER -#define BRE_BitNumber BRE_BIT_NUMBER - -#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - - /** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt -#define HAL_TIM_DMAError TIM_DMAError -#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt -#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback -#define HAL_LTDC_Relaod HAL_LTDC_Reload -#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig -#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig -/** - * @} - */ - - -/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported macros ------------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose - * @{ - */ -#define AES_IT_CC CRYP_IT_CC -#define AES_IT_ERR CRYP_IT_ERR -#define AES_FLAG_CCF CRYP_FLAG_CCF -/** - * @} - */ - -/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE -#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH -#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH -#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM -#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM -#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC -#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI -#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK -#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG -#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG -#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE -#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE -#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE - -#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY -#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 -#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS -#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER -#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER - -/** - * @} - */ - - -/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __ADC_ENABLE __HAL_ADC_ENABLE -#define __ADC_DISABLE __HAL_ADC_DISABLE -#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS -#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS -#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE -#define __ADC_IS_ENABLED ADC_IS_ENABLE -#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR -#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR -#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING -#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE - -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION -#define __HAL_ADC_JSQR_RK ADC_JSQR_RK -#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT -#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR -#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION -#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE -#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS -#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM -#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT -#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS -#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN -#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ -#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET -#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET -#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL -#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL -#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET -#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET -#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD - -#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION -#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER -#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI -#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER -#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER -#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE - -#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT -#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT -#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL -#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM -#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET -#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE -#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE -#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER - -#define __HAL_ADC_SQR1 ADC_SQR1 -#define __HAL_ADC_SMPR1 ADC_SMPR1 -#define __HAL_ADC_SMPR2 ADC_SMPR2 -#define __HAL_ADC_SQR3_RK ADC_SQR3_RK -#define __HAL_ADC_SQR2_RK ADC_SQR2_RK -#define __HAL_ADC_SQR1_RK ADC_SQR1_RK -#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS -#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS -#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV -#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection -#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_JSQR ADC_JSQR - -#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL -#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF -#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT -#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS -#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN -#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR -#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT -#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT -#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT -#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE - -/** - * @} - */ - -/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 -#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 -#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 -#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 -#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 -#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 -#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 -#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 -#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 -#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 -#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 -#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 -#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 -#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 -#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 -#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 - -#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 -#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 -#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 -#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 -#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 -#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 -#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 -#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 -#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 -#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 -#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 -#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 -#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 -#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 - - -#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 -#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 -#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 -#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 -#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 -#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 -#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC -#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC -#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG -#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG -#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG -#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG -#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT -#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT -#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT -#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT -#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT -#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT -#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 -#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 -#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 -#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 -#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 -#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32F3) -#define COMP_START __HAL_COMP_ENABLE -#define COMP_STOP __HAL_COMP_DISABLE -#define COMP_LOCK __HAL_COMP_LOCK - -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP7_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif -#else -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -#endif - -#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE - -#if defined(STM32L0) || defined(STM32L4) -/* Note: On these STM32 families, the only argument of this macro */ -/* is COMP_FLAG_LOCK. */ -/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ -/* argument. */ -#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) -#endif -/** - * @} - */ - -#if defined(STM32L0) || defined(STM32L4) -/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -/** - * @} - */ -#endif - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_WRPAREA IS_OB_WRPAREA -#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM -#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM -#define IS_TYPEERASE IS_FLASH_TYPEERASE -#define IS_NBSECTORS IS_FLASH_NBSECTORS -#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE - -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 -#define __HAL_I2C_GENERATE_START I2C_GENERATE_START -#if defined(STM32F1) -#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE -#else -#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE -#endif /* STM32F1 */ -#define __HAL_I2C_RISE_TIME I2C_RISE_TIME -#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD -#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST -#define __HAL_I2C_SPEED I2C_SPEED -#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE -#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ -#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS -#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE -#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ -#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB -#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB -#define __HAL_I2C_FREQRANGE I2C_FREQRANGE -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE -#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT - -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __IRDA_DISABLE __HAL_IRDA_DISABLE -#define __IRDA_ENABLE __HAL_IRDA_ENABLE - -#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION - -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE - - -/** - * @} - */ - - -/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS -#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS -/** - * @} - */ - - -/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT -#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT -#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE - -/** - * @} - */ - - -/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose - * @{ - */ -#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD -#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX -#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX -#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX -#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX -#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L -#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H -#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM -#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES -#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX -#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT -#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION -#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET - -/** - * @} - */ - - -/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE -#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE -#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine -#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) -#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention -#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 -#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 -#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB -#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB - -#if defined (STM32F4) -#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() -#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() -#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() -#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() -#else -#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG -#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT -#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT -#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG -#endif /* STM32F4 */ -/** - * @} - */ - - -/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose - * @{ - */ - -#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI -#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI - -#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) - -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE -#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET -#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET -#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE -#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE -#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET -#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET -#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE -#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE -#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE -#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET -#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE -#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE -#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET -#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET -#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET -#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET -#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET -#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET -#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET -#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET -#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET -#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET -#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET -#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET -#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET -#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET -#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE -#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE -#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET -#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET -#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE -#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE -#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE -#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE -#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET -#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET -#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE -#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE -#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE -#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE -#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET -#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET -#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE -#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE -#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET -#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET -#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE -#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE -#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE -#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE -#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET -#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET -#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE -#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE -#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET -#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET -#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE -#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE -#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE -#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE -#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET -#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET -#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE -#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE -#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET -#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET -#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE -#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE -#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE -#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE -#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET -#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET -#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE -#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE -#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE -#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE -#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET -#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET -#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE -#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE -#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE -#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE -#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET -#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET -#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE -#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE -#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET -#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET -#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE -#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE -#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE -#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE -#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE -#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE -#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE -#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE -#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE -#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE -#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET -#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET -#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE -#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE -#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET -#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET -#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE -#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE -#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE -#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE -#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE -#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE -#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET -#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET -#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE -#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE -#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE -#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE -#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE -#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE -#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET -#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET -#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE -#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE -#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE -#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE -#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET -#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET -#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE -#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE -#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE -#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE -#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET -#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET -#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE -#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE -#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE -#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE -#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET -#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET -#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE -#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE -#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE -#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE -#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET -#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET -#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE -#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE -#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE -#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE -#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET -#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET -#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE -#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE -#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE -#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE -#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET -#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET -#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE -#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE -#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE -#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE -#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET -#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET -#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE -#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE -#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE -#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE -#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET -#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET -#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE -#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE -#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE -#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE -#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET -#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET -#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE -#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE -#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE -#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE -#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET -#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET -#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE -#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE -#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE -#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE -#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET -#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET -#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE -#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE -#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE -#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE -#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET -#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET -#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE -#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE -#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE -#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE -#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET -#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET -#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE -#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE -#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE -#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE -#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET -#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET -#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE -#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE -#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE -#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE -#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET -#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET -#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE -#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE -#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE -#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE -#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET -#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET -#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE -#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE -#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE -#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE -#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET -#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET -#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE -#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE -#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE -#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE -#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET -#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET - -#if defined(STM32WB) -#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE -#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET -#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET -#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED -#define QSPI_IRQHandler QUADSPI_IRQHandler -#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ - -#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE -#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE -#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE -#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE -#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET -#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET -#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE -#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE -#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE -#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE -#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET -#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET -#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE -#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE -#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE -#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE -#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET -#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET -#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE -#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE -#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE -#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE -#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET -#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET -#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE -#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE -#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE -#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE -#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET -#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET -#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE -#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE -#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE -#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE -#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET -#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET -#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE -#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE -#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE -#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE -#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET -#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET -#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE -#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE -#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE -#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE -#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE -#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE -#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE -#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE -#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE -#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE -#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET -#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET -#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE -#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE -#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE -#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE -#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET -#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET -#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE -#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE -#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE -#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE -#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET -#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET -#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE -#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE -#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET -#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET -#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE -#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE -#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET -#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET -#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE -#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE -#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET -#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET -#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE -#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE -#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET -#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET -#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE -#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE -#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET -#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET -#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE -#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE -#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE -#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE -#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET -#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET -#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE -#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE -#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE -#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE -#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET -#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET -#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE -#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE -#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE -#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE -#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET -#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET -#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE -#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE -#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE -#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE -#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET -#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET -#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE -#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE -#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE -#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE -#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET -#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET -#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE -#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE -#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE -#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE -#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET -#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET -#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE -#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE -#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE -#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE -#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET -#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET -#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE -#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE -#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE -#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE -#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET -#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET -#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE -#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE -#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE -#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE -#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET -#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET -#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE -#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE -#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE -#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE -#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET -#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET -#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE -#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE -#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET -#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET -#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE -#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE -#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE -#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE -#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET -#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET -#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE -#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE -#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE -#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE -#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET -#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET -#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE -#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE -#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE -#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE -#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET -#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET -#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE -#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE -#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE -#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE -#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET -#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET -#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE -#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE -#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET -#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE -#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE -#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE -#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE -#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET -#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE -#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE -#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE -#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE -#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET -#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET -#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE -#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE -#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET -#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET -#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE -#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE -#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE -#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE -#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET -#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET -#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE -#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE -#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE -#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE -#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE -#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE -#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET -#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET -#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE -#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE - -#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET -#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE -#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE -#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE -#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE -#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE -#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE -#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE -#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE -#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE -#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET -#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET -#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE -#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE -#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE -#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE -#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET -#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET -#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE -#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE -#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE -#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET -#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET -#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE -#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE -#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE -#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET -#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE -#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE -#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE -#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE -#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE -#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE -#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE -#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE -#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE -#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE -#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE -#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE -#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET -#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET -#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE -#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE -#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE -#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET -#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET -#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE -#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE -#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE -#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET -#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET -#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE -#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE -#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE -#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET -#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET -#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE -#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE -#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE -#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET -#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE -#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE -#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE -#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE -#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET -#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET -#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE -#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE -#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE -#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED -#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE -#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE -#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE -#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE -#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET -#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET -#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE -#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE -#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE -#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET -#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET -#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE - -/* alias define maintained for legacy */ -#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET - -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE -#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE -#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE -#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE -#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE -#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE -#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE -#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE -#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE -#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE -#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE -#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE -#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE -#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE -#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE -#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE -#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE - -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET -#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET -#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET -#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET -#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET -#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET -#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET -#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET -#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET -#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET -#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET -#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET -#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET -#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET -#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET -#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET -#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET - -#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED -#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED -#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED -#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED -#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED -#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED -#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED -#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED -#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED -#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED -#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED -#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED -#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED -#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED -#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED -#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED -#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED -#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED -#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED -#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED -#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED -#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED -#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED -#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED -#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED -#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED -#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED -#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED -#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED -#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED -#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED -#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED -#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED -#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED -#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED -#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED -#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED -#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED -#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED -#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED -#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED -#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED -#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED -#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED -#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED -#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED -#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED -#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED -#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED -#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED -#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED -#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED -#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED -#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED -#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED -#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED -#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED -#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED -#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED -#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED -#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED -#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED -#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED -#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED -#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED -#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED -#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED -#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED -#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED -#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED -#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED -#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED -#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED -#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED -#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED -#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED -#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED -#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED -#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED -#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED -#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED -#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED -#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED -#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED -#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED -#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED -#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED -#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED -#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED -#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED -#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED -#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED -#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED -#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED -#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED -#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED -#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED -#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED -#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED -#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED -#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED -#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED -#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED -#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED -#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED -#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED -#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED -#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED -#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED -#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED -#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED -#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED -#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED -#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED - -#if defined(STM32F4) -#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED -#define Sdmmc1ClockSelection SdioClockSelection -#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO -#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 -#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK -#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG -#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET -#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE -#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE -#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED -#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED -#define SdioClockSelection Sdmmc1ClockSelection -#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 -#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE -#endif - -#if defined(STM32F7) -#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 -#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK -#endif - -#if defined(STM32H7) -#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() - -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() -#endif - -#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG -#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG - -#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE - -#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE -#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE -#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK -#define IS_RCC_HCLK_DIV IS_RCC_PCLK -#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK - -#define RCC_IT_HSI14 RCC_IT_HSI14RDY - -#define RCC_IT_CSSLSE RCC_IT_LSECSS -#define RCC_IT_CSSHSE RCC_IT_CSS - -#define RCC_PLLMUL_3 RCC_PLL_MUL3 -#define RCC_PLLMUL_4 RCC_PLL_MUL4 -#define RCC_PLLMUL_6 RCC_PLL_MUL6 -#define RCC_PLLMUL_8 RCC_PLL_MUL8 -#define RCC_PLLMUL_12 RCC_PLL_MUL12 -#define RCC_PLLMUL_16 RCC_PLL_MUL16 -#define RCC_PLLMUL_24 RCC_PLL_MUL24 -#define RCC_PLLMUL_32 RCC_PLL_MUL32 -#define RCC_PLLMUL_48 RCC_PLL_MUL48 - -#define RCC_PLLDIV_2 RCC_PLL_DIV2 -#define RCC_PLLDIV_3 RCC_PLL_DIV3 -#define RCC_PLLDIV_4 RCC_PLL_DIV4 - -#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE -#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG -#define RCC_MCO_NODIV RCC_MCODIV_1 -#define RCC_MCO_DIV1 RCC_MCODIV_1 -#define RCC_MCO_DIV2 RCC_MCODIV_2 -#define RCC_MCO_DIV4 RCC_MCODIV_4 -#define RCC_MCO_DIV8 RCC_MCODIV_8 -#define RCC_MCO_DIV16 RCC_MCODIV_16 -#define RCC_MCO_DIV32 RCC_MCODIV_32 -#define RCC_MCO_DIV64 RCC_MCODIV_64 -#define RCC_MCO_DIV128 RCC_MCODIV_128 -#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK -#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI -#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE -#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK -#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI -#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 -#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 -#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE -#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 - -#if defined(STM32L4) -#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) -#else -#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK -#endif - -#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 -#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL -#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI -#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 -#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 -#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 - -#define HSION_BitNumber RCC_HSION_BIT_NUMBER -#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER -#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER -#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER -#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER -#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER -#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER -#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER -#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER -#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER -#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER -#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER -#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER -#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER -#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER -#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER -#define LSION_BitNumber RCC_LSION_BIT_NUMBER -#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER -#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER -#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER -#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER -#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER -#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER -#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER -#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER -#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER -#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS -#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS -#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS -#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS -#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE -#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE - -#define CR_HSION_BB RCC_CR_HSION_BB -#define CR_CSSON_BB RCC_CR_CSSON_BB -#define CR_PLLON_BB RCC_CR_PLLON_BB -#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB -#define CR_MSION_BB RCC_CR_MSION_BB -#define CSR_LSION_BB RCC_CSR_LSION_BB -#define CSR_LSEON_BB RCC_CSR_LSEON_BB -#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB -#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB -#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB -#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB -#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB -#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB -#define CR_HSEON_BB RCC_CR_HSEON_BB -#define CSR_RMVF_BB RCC_CSR_RMVF_BB -#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB -#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB - -#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE -#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE -#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE -#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE -#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE - -#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT - -#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN -#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF - -#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 -#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ -#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP -#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ -#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE -#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 - -#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE -#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED -#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET -#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET -#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE -#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED -#define DfsdmClockSelection Dfsdm1ClockSelection -#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 -#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK -#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG -#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE -#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 -#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 -#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 - -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 -#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 - -/** - * @} - */ - -/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose - * @{ - */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) - -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32G0) -#else -#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG -#endif -#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT -#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT - -#if defined (STM32F1) -#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() - -#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() - -#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() - -#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() - -#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() -#else -#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) -#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) -#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) -#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) -#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) -#endif /* STM32F1 */ - -#define IS_ALARM IS_RTC_ALARM -#define IS_ALARM_MASK IS_RTC_ALARM_MASK -#define IS_TAMPER IS_RTC_TAMPER -#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER -#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT -#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE -#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION -#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE -#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ -#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION -#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER -#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK -#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER - -#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE -#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE - -/** - * @} - */ - -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE -#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS - -#if defined(STM32F4) || defined(STM32F2) -#define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT -#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND -/* alias CMSIS */ -#define SDMMC1_IRQn SDIO_IRQn -#define SDMMC1_IRQHandler SDIO_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED -#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION -#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND -#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT -#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED -#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE -#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE -#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE -#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE -#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT -#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT -#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG -#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG -#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT -#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND -/* alias CMSIS for compatibilities */ -#define SDIO_IRQn SDMMC1_IRQn -#define SDIO_IRQHandler SDMMC1_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) -#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef -#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef -#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef -#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef -#endif - -#if defined(STM32H7) -#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback -#endif -/** - * @} - */ - -/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT -#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT -#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE -#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE -#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE -#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE - -#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE - -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE - -/** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 -#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 -#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START -#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH -#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR -#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE -#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE -#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_SPI_1LINE_TX SPI_1LINE_TX -#define __HAL_SPI_1LINE_RX SPI_1LINE_RX -#define __HAL_SPI_RESET_CRC SPI_RESET_CRC - -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION -#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION - -#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD - -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT -#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT -#define __USART_ENABLE __HAL_USART_ENABLE -#define __USART_DISABLE __HAL_USART_DISABLE - -#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE -#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE - -/** - * @} - */ - -/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose - * @{ - */ -#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE - -#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE -#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE -#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE - -#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE -#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE -#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE - -#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE - -#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT - -#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT - -#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup -#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup - -#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo -#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE -#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE - -#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE -#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT - -#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE - -#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN -#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER -#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER -#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER -#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD -#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD -#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION -#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION -#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER -#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER -#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE -#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE - -#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT -#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT -#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG -#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER - -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE -#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE -#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_LTDC_LAYER LTDC_LAYER -#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG -/** - * @} - */ - -/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose - * @{ - */ -#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE -#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE -#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE -#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE -#define SAI_STREOMODE SAI_STEREOMODE -#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY -#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL -#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL -#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL -#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL -#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL -#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE -#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 -#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE -/** - * @} - */ - -/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32H7) -#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow -#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT -#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA -#endif -/** - * @} - */ - -/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32_HAL_LEGACY */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h deleted file mode 100644 index aafa7c351..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h +++ /dev/null @@ -1,669 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal.h - * @author MCD Application Team - * @brief This file contains all the functions prototypes for the HAL - * module driver. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_H -#define __STM32L4xx_HAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_conf.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup HAL - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants - * @{ - */ - -/** @defgroup SYSCFG_BootMode Boot Mode - * @{ - */ -#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) -#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1 -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2) -#define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0) -#else -#define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** - * @} - */ - -/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts - * @{ - */ -#define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ -#define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ -#define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ -#define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ -#define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ -#define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ - -/** - * @} - */ - -/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31) - * @{ - */ -#define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ -#define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ -#define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ -#define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ -#define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ -#define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ -#define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ -#define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ -#define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ -#define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ -#define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ -#define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ -#define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ -#define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ -#define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ -#define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ -#if defined(SYSCFG_SWPR_PAGE31) -#define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ -#define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ -#define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ -#define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ -#define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ -#define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ -#define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ -#define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ -#define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ -#define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ -#define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ -#define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ -#define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ -#define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ -#define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ -#define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ -#endif /* SYSCFG_SWPR_PAGE31 */ - -/** - * @} - */ - -#if defined(SYSCFG_SWPR2_PAGE63) -/** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63) - * @{ - */ -#define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */ -#define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */ -#define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */ -#define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */ -#define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */ -#define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */ -#define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */ -#define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */ -#define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */ -#define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */ -#define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */ -#define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */ -#define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */ -#define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */ -#define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */ -#define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */ -#define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */ -#define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */ -#define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */ -#define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */ -#define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */ -#define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */ -#define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */ -#define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */ -#define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */ -#define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */ -#define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */ -#define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */ -#define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */ -#define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */ -#define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */ -#define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */ - -/** - * @} - */ -#endif /* SYSCFG_SWPR2_PAGE63 */ - -#if defined(VREFBUF) -/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale - * @{ - */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ - -/** - * @} - */ - -/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance - * @{ - */ -#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ -#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ - -/** - * @} - */ -#endif /* VREFBUF */ - -/** @defgroup SYSCFG_flags_definition Flags - * @{ - */ - -#define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ -#define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ - -/** - * @} - */ - -/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO - * @{ - */ - -/** @brief Fast-mode Plus driving capability on a specific GPIO - */ -#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ -#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ -#if defined(SYSCFG_CFGR1_I2C_PB8_FMP) -#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ -#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ -#if defined(SYSCFG_CFGR1_I2C_PB9_FMP) -#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ -#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros - * @{ - */ - -/** @brief Freeze/Unfreeze Peripherals in Debug mode - */ -#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) -#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) -#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) -#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) -#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) -#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) -#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) -#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) -#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) -#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) -#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) -#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) -#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) -#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) -#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) -#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) -#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) -#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) -#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) -#endif - -#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) -#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) -#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP) -#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) -#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP) -#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) -#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) -#endif - -#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) -#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) -#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) -#endif - -#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) -#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) -#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) -#endif - -#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) -#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) -#endif - -#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) -#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) -#endif - -#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) -#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) -#endif - -#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) -#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) -#endif - -#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) -#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) -#endif - -/** - * @} - */ - -/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros - * @{ - */ - -/** @brief Main Flash memory mapped at 0x00000000. - */ -#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) - -/** @brief System Flash memory mapped at 0x00000000. - */ -#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) - -/** @brief Embedded SRAM mapped at 0x00000000. - */ -#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - -/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. - */ -#define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - -/** @brief OCTOSPI mapped at 0x00000000. - */ -#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2)) -#define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0)) - -#else - -/** @brief QUADSPI mapped at 0x00000000. - */ -#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** - * @brief Return the boot mode as configured by user. - * @retval The boot mode as configured by user. The returned value can be one - * of the following values: - * @arg @ref SYSCFG_BOOT_MAINFLASH - * @arg @ref SYSCFG_BOOT_SYSTEMFLASH - @if STM32L486xx - * @arg @ref SYSCFG_BOOT_FMC - @endif - * @arg @ref SYSCFG_BOOT_SRAM - * @arg @ref SYSCFG_BOOT_QUADSPI - */ -#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) - -/** @brief SRAM2 page 0 to 31 write protection enable macro - * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP - * @note Write protection can only be disabled by a system reset - */ -#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ - SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ - }while(0) - -#if defined(SYSCFG_SWPR2_PAGE63) -/** @brief SRAM2 page 32 to 63 write protection enable macro - * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63 - * @note Write protection can only be disabled by a system reset - */ -#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ - SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\ - }while(0) -#endif /* SYSCFG_SWPR2_PAGE63 */ - -/** @brief SRAM2 page write protection unlock prior to erase - * @note Writing a wrong key reactivates the write protection - */ -#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ - SYSCFG->SKR = 0x53;\ - }while(0) - -/** @brief SRAM2 erase - * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase - */ -#define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) - -/** @brief Floating Point Unit interrupt enable/disable macros - * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts - */ -#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ - SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ - }while(0) - -#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ - CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ - }while(0) - -/** @brief SYSCFG Break ECC lock. - * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. - * @note The selected configuration is locked and can be unlocked only by system reset. - */ -#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) - -/** @brief SYSCFG Break Cortex-M4 Lockup lock. - * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. - * @note The selected configuration is locked and can be unlocked only by system reset. - */ -#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) - -/** @brief SYSCFG Break PVD lock. - * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. - * @note The selected configuration is locked and can be unlocked only by system reset. - */ -#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) - -/** @brief SYSCFG Break SRAM2 parity lock. - * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. - * @note The selected configuration is locked and can be unlocked by system reset. - */ -#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) - -/** @brief Check SYSCFG flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag - * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0) - -/** @brief Set the SPF bit to clear the SRAM Parity Error Flag. - */ -#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) - -/** @brief Fast-mode Plus driving capability enable/disable macros - * @param __FASTMODEPLUS__ This parameter can be a value of : - * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 - * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 - * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 - * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 - */ -#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ - SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ - }while(0) - -#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ - CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ - }while(0) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros - * @{ - */ - -#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) - -#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ - ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ - ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ - ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) - -#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF)) - -#if defined(VREFBUF) -#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ - ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) - -#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ - ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) - -#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) -#endif /* VREFBUF */ - -#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) -#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) -#elif defined(SYSCFG_FASTMODEPLUS_PB8) -#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8)) -#elif defined(SYSCFG_FASTMODEPLUS_PB9) -#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) -#else -#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)) -#endif -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup HAL_Exported_Functions - * @{ - */ - -/** @addtogroup HAL_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_Init(void); -HAL_StatusTypeDef HAL_DeInit(void); -void HAL_MspInit(void); -void HAL_MspDeInit(void); -HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); - -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(uint32_t Delay); -uint32_t HAL_GetTick(void); -void HAL_SuspendTick(void); -void HAL_ResumeTick(void); -uint32_t HAL_GetHalVersion(void); -uint32_t HAL_GetREVID(void); -uint32_t HAL_GetDEVID(void); -uint32_t HAL_GetUIDw0(void); -uint32_t HAL_GetUIDw1(void); -uint32_t HAL_GetUIDw2(void); - -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group3 - * @{ - */ - -/* DBGMCU Peripheral Control functions *****************************************/ -void HAL_DBGMCU_EnableDBGSleepMode(void); -void HAL_DBGMCU_DisableDBGSleepMode(void); -void HAL_DBGMCU_EnableDBGStopMode(void); -void HAL_DBGMCU_DisableDBGStopMode(void); -void HAL_DBGMCU_EnableDBGStandbyMode(void); -void HAL_DBGMCU_DisableDBGStandbyMode(void); - -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group4 - * @{ - */ - -/* SYSCFG Control functions ****************************************************/ -void HAL_SYSCFG_SRAM2Erase(void); -void HAL_SYSCFG_EnableMemorySwappingBank(void); -void HAL_SYSCFG_DisableMemorySwappingBank(void); - -#if defined(VREFBUF) -void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); -void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); -void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); -HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); -void HAL_SYSCFG_DisableVREFBUF(void); -#endif /* VREFBUF */ - -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h deleted file mode 100644 index f3eea8a70..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h +++ /dev/null @@ -1,433 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX HAL module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_CORTEX_H -#define __STM32L4xx_HAL_CORTEX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup CORTEX CORTEX - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Types CORTEX Exported Types - * @{ - */ - -#if (__MPU_PRESENT == 1) -/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition - * @{ - */ -typedef struct -{ - uint8_t Enable; /*!< Specifies the status of the region. - This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ - uint8_t Number; /*!< Specifies the number of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Number */ - uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ - uint8_t Size; /*!< Specifies the size of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Size */ - uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint8_t TypeExtField; /*!< Specifies the TEX field level. - This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ - uint8_t AccessPermission; /*!< Specifies the region access permission type. - This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ - uint8_t DisableExec; /*!< Specifies the instruction access status. - This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ - uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ - uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. - This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ - uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ -}MPU_Region_InitTypeDef; -/** - * @} - */ -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group - * @{ - */ -#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, - 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, - 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, - 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, - 1 bit for subpriority */ -#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority, - 0 bit for subpriority */ -/** - * @} - */ - -/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source - * @{ - */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) -/** - * @} - */ - -#if (__MPU_PRESENT == 1) -/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control - * @{ - */ -#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) -#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) -#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) -#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable - * @{ - */ -#define MPU_REGION_ENABLE ((uint8_t)0x01) -#define MPU_REGION_DISABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access - * @{ - */ -#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) -#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable - * @{ - */ -#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable - * @{ - */ -#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable - * @{ - */ -#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels - * @{ - */ -#define MPU_TEX_LEVEL0 ((uint8_t)0x00) -#define MPU_TEX_LEVEL1 ((uint8_t)0x01) -#define MPU_TEX_LEVEL2 ((uint8_t)0x02) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size - * @{ - */ -#define MPU_REGION_SIZE_32B ((uint8_t)0x04) -#define MPU_REGION_SIZE_64B ((uint8_t)0x05) -#define MPU_REGION_SIZE_128B ((uint8_t)0x06) -#define MPU_REGION_SIZE_256B ((uint8_t)0x07) -#define MPU_REGION_SIZE_512B ((uint8_t)0x08) -#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) -#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) -#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) -#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) -#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) -#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) -#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) -#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) -#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) -#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) -#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) -#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) -#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) -#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) -#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) -#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) -#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) -#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) -#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) -#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) -#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) -#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) -#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes - * @{ - */ -#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) -#define MPU_REGION_PRIV_RW ((uint8_t)0x01) -#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) -#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) -#define MPU_REGION_PRIV_RO ((uint8_t)0x05) -#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number - * @{ - */ -#define MPU_REGION_NUMBER0 ((uint8_t)0x00) -#define MPU_REGION_NUMBER1 ((uint8_t)0x01) -#define MPU_REGION_NUMBER2 ((uint8_t)0x02) -#define MPU_REGION_NUMBER3 ((uint8_t)0x03) -#define MPU_REGION_NUMBER4 ((uint8_t)0x04) -#define MPU_REGION_NUMBER5 ((uint8_t)0x05) -#define MPU_REGION_NUMBER6 ((uint8_t)0x06) -#define MPU_REGION_NUMBER7 ((uint8_t)0x07) -/** - * @} - */ -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions - * @{ - */ - -/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * @{ - */ -/* Initialization and Configuration functions *****************************/ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); -void HAL_NVIC_SystemReset(void); -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); - -/** - * @} - */ - -/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions - * @{ - */ -/* Peripheral Control functions ***********************************************/ -uint32_t HAL_NVIC_GetPriorityGrouping(void); -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); -void HAL_SYSTICK_IRQHandler(void); -void HAL_SYSTICK_Callback(void); - -#if (__MPU_PRESENT == 1) -void HAL_MPU_Enable(uint32_t MPU_Control); -void HAL_MPU_Disable(void); -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); -#endif /* __MPU_PRESENT */ -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Macros CORTEX Private Macros - * @{ - */ -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ - ((GROUP) == NVIC_PRIORITYGROUP_1) || \ - ((GROUP) == NVIC_PRIORITYGROUP_2) || \ - ((GROUP) == NVIC_PRIORITYGROUP_3) || \ - ((GROUP) == NVIC_PRIORITYGROUP_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) - -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ - ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) - -#if (__MPU_PRESENT == 1) -#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ - ((STATE) == MPU_REGION_DISABLE)) - -#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ - ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) - -#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ - ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) - -#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ - ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) - -#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ - ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) - -#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ - ((TYPE) == MPU_TEX_LEVEL1) || \ - ((TYPE) == MPU_TEX_LEVEL2)) - -#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ - ((TYPE) == MPU_REGION_PRIV_RW) || \ - ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ - ((TYPE) == MPU_REGION_FULL_ACCESS) || \ - ((TYPE) == MPU_REGION_PRIV_RO) || \ - ((TYPE) == MPU_REGION_PRIV_RO_URO)) - -#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ - ((NUMBER) == MPU_REGION_NUMBER1) || \ - ((NUMBER) == MPU_REGION_NUMBER2) || \ - ((NUMBER) == MPU_REGION_NUMBER3) || \ - ((NUMBER) == MPU_REGION_NUMBER4) || \ - ((NUMBER) == MPU_REGION_NUMBER5) || \ - ((NUMBER) == MPU_REGION_NUMBER6) || \ - ((NUMBER) == MPU_REGION_NUMBER7)) - -#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ - ((SIZE) == MPU_REGION_SIZE_64B) || \ - ((SIZE) == MPU_REGION_SIZE_128B) || \ - ((SIZE) == MPU_REGION_SIZE_256B) || \ - ((SIZE) == MPU_REGION_SIZE_512B) || \ - ((SIZE) == MPU_REGION_SIZE_1KB) || \ - ((SIZE) == MPU_REGION_SIZE_2KB) || \ - ((SIZE) == MPU_REGION_SIZE_4KB) || \ - ((SIZE) == MPU_REGION_SIZE_8KB) || \ - ((SIZE) == MPU_REGION_SIZE_16KB) || \ - ((SIZE) == MPU_REGION_SIZE_32KB) || \ - ((SIZE) == MPU_REGION_SIZE_64KB) || \ - ((SIZE) == MPU_REGION_SIZE_128KB) || \ - ((SIZE) == MPU_REGION_SIZE_256KB) || \ - ((SIZE) == MPU_REGION_SIZE_512KB) || \ - ((SIZE) == MPU_REGION_SIZE_1MB) || \ - ((SIZE) == MPU_REGION_SIZE_2MB) || \ - ((SIZE) == MPU_REGION_SIZE_4MB) || \ - ((SIZE) == MPU_REGION_SIZE_8MB) || \ - ((SIZE) == MPU_REGION_SIZE_16MB) || \ - ((SIZE) == MPU_REGION_SIZE_32MB) || \ - ((SIZE) == MPU_REGION_SIZE_64MB) || \ - ((SIZE) == MPU_REGION_SIZE_128MB) || \ - ((SIZE) == MPU_REGION_SIZE_256MB) || \ - ((SIZE) == MPU_REGION_SIZE_512MB) || \ - ((SIZE) == MPU_REGION_SIZE_1GB) || \ - ((SIZE) == MPU_REGION_SIZE_2GB) || \ - ((SIZE) == MPU_REGION_SIZE_4GB)) - -#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_CORTEX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h deleted file mode 100644 index bb9816b41..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h +++ /dev/null @@ -1,213 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_def.h - * @author MCD Application Team - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DEF -#define __STM32L4xx_HAL_DEF - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx.h" -#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ -#include - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HAL Status structures definition - */ -typedef enum -{ - HAL_OK = 0x00, - HAL_ERROR = 0x01, - HAL_BUSY = 0x02, - HAL_TIMEOUT = 0x03 -} HAL_StatusTypeDef; - -/** - * @brief HAL Lock structures definition - */ -typedef enum -{ - HAL_UNLOCKED = 0x00, - HAL_LOCKED = 0x01 -} HAL_LockTypeDef; - -/* Exported macros -----------------------------------------------------------*/ - -#define HAL_MAX_DELAY 0xFFFFFFFFU - -#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) -#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) - -#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ - do{ \ - (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ - (__DMA_HANDLE__).Parent = (__HANDLE__); \ - } while(0) - -#define UNUSED(x) ((void)(x)) - -/** @brief Reset the Handle's State field. - * @param __HANDLE__: specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: - * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro - * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function - * HAL_PPP_Init() is called, the low level hardware initialization will be missed - * (i.e. HAL_PPP_MspInit() will not be executed). - * - When there is a need to reconfigure the low level hardware: instead of calling - * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). - * In this later function, when the Handle's "State" field is set to 0, it will execute the function - * HAL_PPP_MspInit() which will reconfigure the low level hardware. - * @retval None - */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) - -#if (USE_RTOS == 1) - /* Reserved for future use */ - #error " USE_RTOS should be 0 in the current HAL release " -#else - #define __HAL_LOCK(__HANDLE__) \ - do{ \ - if((__HANDLE__)->Lock == HAL_LOCKED) \ - { \ - return HAL_BUSY; \ - } \ - else \ - { \ - (__HANDLE__)->Lock = HAL_LOCKED; \ - } \ - }while (0) - - #define __HAL_UNLOCK(__HANDLE__) \ - do{ \ - (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0) -#endif /* USE_RTOS */ - -#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ -#endif /* __GNUC__ */ - - -/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ - #ifndef __ALIGN_END - #define __ALIGN_END __attribute__ ((aligned (4))) - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif /* __ALIGN_BEGIN */ -#else - #ifndef __ALIGN_END - #define __ALIGN_END - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #endif /* __CC_ARM */ - #endif /* __ALIGN_BEGIN */ -#endif /* __GNUC__ */ - -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC HAL_StatusTypeDef - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc HAL_StatusTypeDef - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) - -#endif - -/** - * @brief __NOINLINE definition - */ -#if defined ( __CC_ARM ) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- -*/ -#define __NOINLINE __attribute__ ( (noinline) ) - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- -*/ -#define __NOINLINE _Pragma("optimize = no_inline") - -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32L4xx_HAL_DEF */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h deleted file mode 100644 index c11a47cca..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h +++ /dev/null @@ -1,766 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_dma.h - * @author MCD Application Team - * @brief Header file of DMA HAL module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DMA_H -#define __STM32L4xx_HAL_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup DMA_Exported_Types DMA Exported Types - * @{ - */ - -/** - * @brief DMA Configuration Structure definition - */ -typedef struct -{ - uint32_t Request; /*!< Specifies the request selected for the specified channel. - This parameter can be a value of @ref DMA_request */ - - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_Data_transfer_direction */ - - uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ - - uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_Memory_incremented_mode */ - - uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_Peripheral_data_size */ - - uint32_t MemDataAlignment; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_Memory_data_size */ - - uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_Priority_level */ -} DMA_InitTypeDef; - -/** - * @brief HAL DMA State structures definition - */ -typedef enum -{ - HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ -}HAL_DMA_StateTypeDef; - -/** - * @brief HAL DMA Error Code structure definition - */ -typedef enum -{ - HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */ -}HAL_DMA_LevelCompleteTypeDef; - - -/** - * @brief HAL DMA Callback ID structure definition - */ -typedef enum -{ - HAL_DMA_XFER_CPLT_CB_ID = 0x00, /*!< Full transfer */ - HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01, /*!< Half transfer */ - HAL_DMA_XFER_ERROR_CB_ID = 0x02, /*!< Error */ - HAL_DMA_XFER_ABORT_CB_ID = 0x03, /*!< Abort */ - HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */ - -}HAL_DMA_CallbackIDTypeDef; - -/** - * @brief DMA handle Structure definition - */ -typedef struct __DMA_HandleTypeDef -{ - DMA_Channel_TypeDef *Instance; /*!< Register base address */ - - DMA_InitTypeDef Init; /*!< DMA communication parameters */ - - HAL_LockTypeDef Lock; /*!< DMA locking object */ - - __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - - void *Parent; /*!< Parent object state */ - - void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ - - void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ - - void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - - void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ - - __IO uint32_t ErrorCode; /*!< DMA Error code */ - - DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ - - uint32_t ChannelIndex; /*!< DMA Channel Index */ - -#if defined(DMAMUX1) - DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ - - DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ - - uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ - - DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ - - DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ - - uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ - -#endif /* DMAMUX1 */ - -}DMA_HandleTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants DMA Exported Constants - * @{ - */ - -/** @defgroup DMA_Error_Code DMA Error Code - * @{ - */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */ -#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004U) /*!< Abort requested with no Xfer ongoing */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */ -#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */ -#define HAL_DMA_ERROR_SYNC ((uint32_t)0x00000200U) /*!< DMAMUX sync overrun error */ -#define HAL_DMA_ERROR_REQGEN ((uint32_t)0x00000400U) /*!< DMAMUX request generator overrun error */ - -/** - * @} - */ - -/** @defgroup DMA_request DMA request - * @{ - */ -#if !defined (DMAMUX1) - -#define DMA_REQUEST_0 ((uint32_t)0x00000000) -#define DMA_REQUEST_1 ((uint32_t)0x00000001) -#define DMA_REQUEST_2 ((uint32_t)0x00000002) -#define DMA_REQUEST_3 ((uint32_t)0x00000003) -#define DMA_REQUEST_4 ((uint32_t)0x00000004) -#define DMA_REQUEST_5 ((uint32_t)0x00000005) -#define DMA_REQUEST_6 ((uint32_t)0x00000006) -#define DMA_REQUEST_7 ((uint32_t)0x00000007) - -#endif - -#if defined(DMAMUX1) - -#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ - -#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ -#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ -#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ -#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ - -#define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */ - -#define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */ -#define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */ - -#define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */ -#define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */ - -#define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */ -#define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */ -#define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */ -#define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */ -#define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */ -#define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */ - -#define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */ -#define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */ -#define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */ -#define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */ -#define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */ -#define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */ -#define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */ -#define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */ - -#define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */ -#define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */ -#define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */ -#define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */ -#define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */ -#define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */ - -#define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */ -#define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */ -#define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */ -#define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */ - -#define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */ -#define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */ - -#define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */ -#define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */ -#define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */ -#define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */ - -#define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */ -#define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */ - -#define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */ -#define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */ -#define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */ -#define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */ -#define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */ -#define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */ -#define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */ - -#define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */ -#define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */ -#define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */ -#define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */ -#define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */ -#define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */ -#define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */ - -#define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */ -#define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */ -#define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */ -#define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */ -#define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */ - -#define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */ -#define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */ -#define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */ -#define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */ -#define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */ -#define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */ - -#define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */ -#define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */ -#define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */ -#define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */ -#define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */ - -#define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */ -#define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */ -#define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */ -#define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */ -#define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */ -#define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */ - -#define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */ -#define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */ -#define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */ -#define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */ - -#define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */ -#define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */ -#define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */ -#define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */ - -#define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */ -#define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */ -#define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */ -#define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */ - -#define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */ - -#define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */ -#define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */ - -#define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */ - -#endif /* DMAMUX1 */ - -/** - * @} - */ - -/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction - * @{ - */ -#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode - * @{ - */ -#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ -#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode - * @{ - */ -#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ -#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size - * @{ - */ -#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ -#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ -#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_Memory_data_size DMA Memory data size - * @{ - */ -#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ -#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ -#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_mode DMA mode - * @{ - */ -#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ -#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ -/** - * @} - */ - -/** @defgroup DMA_Priority_level DMA Priority level - * @{ - */ -#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ -#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ -#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ -#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ -/** - * @} - */ - - -/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions - * @{ - */ -#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) -#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) -#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) -/** - * @} - */ - -/** @defgroup DMA_flag_definitions DMA flag definitions - * @{ - */ -#define DMA_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA_FLAG_TE7 ((uint32_t)0x08000000) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup DMA_Exported_Macros DMA Exported Macros - * @{ - */ - -/** @brief Reset DMA handle state. - * @param __HANDLE__: DMA handle - * @retval None - */ -#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) - -/** - * @brief Enable the specified DMA Channel. - * @param __HANDLE__: DMA handle - * @retval None - */ -#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) - -/** - * @brief Disable the specified DMA Channel. - * @param __HANDLE__: DMA handle - * @retval None - */ -#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) - - -/* Interrupt & Flag management */ - -/** - * @brief Return the current DMA Channel transfer complete flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer complete flag index. - */ - -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ - DMA_FLAG_TC7) - -/** - * @brief Return the current DMA Channel half transfer complete flag. - * @param __HANDLE__: DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ - DMA_FLAG_HT7) - -/** - * @brief Return the current DMA Channel transfer error flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ - DMA_FLAG_TE7) - -/** - * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__: DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ - DMA_ISR_GIF7) - -/** - * @brief Get the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * @arg DMA_FLAG_GLx: Global interrupt flag - * Where x can be from 1 to 7 to select the DMA Channel x flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ - (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) - -/** - * @brief Clear the DMA Channel pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * @arg DMA_FLAG_GLx: Global interrupt flag - * Where x can be from 1 to 7 to select the DMA Channel x flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ - (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) - -/** - * @brief Enable the specified DMA Channel interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) - -/** - * @brief Disable the specified DMA Channel interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified DMA Channel interrupt is enabled or not. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval The state of DMA_IT (SET or RESET). - */ -#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) - -/** - * @brief Return the number of remaining data units in the current DMA Channel transfer. - * @param __HANDLE__: DMA handle - * @retval The number of remaining data units in the current DMA Channel transfer. - */ -#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) - -/** - * @} - */ - -#if defined(DMAMUX1) -/* Include DMA HAL Extension module */ -#include "stm32l4xx_hal_dma_ex.h" -#endif /* DMAMUX1 */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup DMA_Exported_Functions - * @{ - */ - -/** @addtogroup DMA_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); - -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DMA_Private_Macros DMA Private Macros - * @{ - */ - -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ - ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) - -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ - ((STATE) == DMA_PINC_DISABLE)) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ - ((STATE) == DMA_MINC_DISABLE)) - -#if !defined (DMAMUX1) - -#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ - ((REQUEST) == DMA_REQUEST_1) || \ - ((REQUEST) == DMA_REQUEST_2) || \ - ((REQUEST) == DMA_REQUEST_3) || \ - ((REQUEST) == DMA_REQUEST_4) || \ - ((REQUEST) == DMA_REQUEST_5) || \ - ((REQUEST) == DMA_REQUEST_6) || \ - ((REQUEST) == DMA_REQUEST_7)) -#endif - -#if defined(DMAMUX1) - -#define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN) - -#endif /* DMAMUX1 */ - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ - ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_PDATAALIGN_WORD)) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ - ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_MDATAALIGN_WORD )) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR)) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ - ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ - ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h deleted file mode 100644 index 0ce4b2ae2..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h +++ /dev/null @@ -1,298 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_dma_ex.h - * @author MCD Application Team - * @brief Header file of DMA HAL extension module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_DMA_EX_H -#define __STM32L4xx_HAL_DMA_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(DMAMUX1) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMAEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Types DMAEx Exported Types - * @{ - */ - -/** - * @brief HAL DMA Synchro definition - */ - - -/** - * @brief HAL DMAMUX Synchronization configuration structure definition - */ -typedef struct -{ - uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. - This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */ - - uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. - This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */ - - FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled - This parameter can take the value ENABLE or DISABLE*/ - - - FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. - This parameter can take the value ENABLE or DISABLE */ - - uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event - This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ - - -}HAL_DMA_MuxSyncConfigTypeDef; - - -/** - * @brief HAL DMAMUX request generator parameters structure definition - */ -typedef struct -{ - uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator - This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */ - - uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. - This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */ - - uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event - This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ - -}HAL_DMA_MuxRequestGeneratorConfigTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants - * @{ - */ - -/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection - * @{ - */ -#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */ -#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */ -#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */ -#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */ -#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */ -#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */ -#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */ -#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */ -#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */ -#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */ -#define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */ -#define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */ -#define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */ -#define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */ -#define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */ -#define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */ -#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */ -#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */ -#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */ -#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */ -#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */ -#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 21U /*!< Synchronization Signal is LPTIM2 OUT */ -#define HAL_DMAMUX1_SYNC_DSI_TE 22U /*!< Synchronization Signal is DSI Tearing Effect */ -#define HAL_DMAMUX1_SYNC_DSI_EOT 23U /*!< Synchronization Signal is DSI End of refresh */ -#define HAL_DMAMUX1_SYNC_DMA2D_EOT 24U /*!< Synchronization Signal is DMA2D End of Transfer */ -#define HAL_DMAMUX1_SYNC_LDTC_IT 25U /*!< Synchronization Signal is LDTC IT */ - -/** - * @} - */ - -/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection - * @{ - */ -#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */ -#define HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0) /*!< synchronize with rising edge events */ -#define HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1) /*!< synchronize with falling edge events */ -#define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL) /*!< synchronize with rising and falling edge events */ - -/** - * @} - */ - -/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection - * @{ - */ - -#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */ -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */ -#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */ -#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */ -#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */ -#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */ - -/** - * @} - */ - -/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection - * @{ - */ -#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT 0U /*!< block request generator events */ -#define HAL_DMAMUX_REQUEST_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ -#define HAL_DMAMUX_REQUEST_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ -#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMAEx_Exported_Functions - * @{ - */ - -/* IO operation functions *****************************************************/ -/** @addtogroup DMAEx_Exported_Functions_Group1 - * @{ - */ - -/* ------------------------- REQUEST -----------------------------------------*/ -HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, - HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); -HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma); -/* -------------------------------------------------------------------------- */ - -/* ------------------------- SYNCHRO -----------------------------------------*/ -HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); -/* -------------------------------------------------------------------------- */ - -void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); - -/** - * @} - */ - -/** - * @} - */ - - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DMAEx_Private_Macros DMAEx Private Macros - * @brief DMAEx private macros - * @{ - */ - -#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LDTC_IT) - -#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) - -#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ - ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ - ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ - ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) - -#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) - -#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ - ((EVENT) == ENABLE)) - -#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQUEST_GEN_LTDC_IT) - -#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32)) - -#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQUEST_GEN_NO_EVENT) || \ - ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING) || \ - ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_FALLING) || \ - ((POLARITY) == HAL_DMAMUX_REQUEST_GEN_RISING_FALLING)) - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DMAMUX1 */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h deleted file mode 100644 index e05c897ba..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h +++ /dev/null @@ -1,1022 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_flash.h - * @author MCD Application Team - * @brief Header file of FLASH HAL module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_FLASH_H -#define __STM32L4xx_HAL_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Types FLASH Exported Types - * @{ - */ - -/** - * @brief FLASH Erase structure definition - */ -typedef struct -{ - uint32_t TypeErase; /*!< Mass erase or page erase. - This parameter can be a value of @ref FLASH_Type_Erase */ - uint32_t Banks; /*!< Select bank to erase. - This parameter must be a value of @ref FLASH_Banks - (FLASH_BANK_BOTH should be used only for mass erase) */ - uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled - This parameter must be a value between 0 and (max number of pages in the bank - 1) - (eg : 255 for 1MB dual bank) */ - uint32_t NbPages; /*!< Number of pages to be erased. - This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/ -} FLASH_EraseInitTypeDef; - -/** - * @brief FLASH Option Bytes Program structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< Option byte to be configured. - This parameter can be a combination of the values of @ref FLASH_OB_Type */ - uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). - Only one WRP area could be programmed at the same time. - This parameter can be value of @ref FLASH_OB_WRP_Area */ - uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). - This parameter must be a value between 0 and (max number of pages in the bank - 1) - (eg : 25 for 1MB dual bank) */ - uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). - This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */ - uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP). - This parameter can be a value of @ref FLASH_OB_Read_Protection */ - uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). - This parameter can be a combination of @ref FLASH_OB_USER_Type */ - uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). - This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, - @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, - @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, - @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, - @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, - @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, - @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */ - uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). - This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) - and @ref FLASH_OB_PCROP_RDP */ - uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). - This parameter must be a value between begin and end of bank - => Be careful of the bank swapping for the address */ - uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). - This parameter must be a value between PCROP Start address and end of bank */ -} FLASH_OBProgramInitTypeDef; - -/** - * @brief FLASH Procedure structure definition - */ -typedef enum -{ - FLASH_PROC_NONE = 0, - FLASH_PROC_PAGE_ERASE, - FLASH_PROC_MASS_ERASE, - FLASH_PROC_PROGRAM, - FLASH_PROC_PROGRAM_LAST -} FLASH_ProcedureTypeDef; - -/** - * @brief FLASH Cache structure definition - */ -typedef enum -{ - FLASH_CACHE_DISABLED = 0, - FLASH_CACHE_ICACHE_ENABLED, - FLASH_CACHE_DCACHE_ENABLED, - FLASH_CACHE_ICACHE_DCACHE_ENABLED -} FLASH_CacheTypeDef; - -/** - * @brief FLASH handle Structure definition - */ -typedef struct -{ - HAL_LockTypeDef Lock; /* FLASH locking object */ - __IO uint32_t ErrorCode; /* FLASH error code */ - __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ - __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */ - __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */ - __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ - __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ - __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */ -}FLASH_ProcessTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Constants FLASH Exported Constants - * @{ - */ - -/** @defgroup FLASH_Error FLASH Error - * @{ - */ -#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000) -#define HAL_FLASH_ERROR_OP ((uint32_t)0x00000001) -#define HAL_FLASH_ERROR_PROG ((uint32_t)0x00000002) -#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000004) -#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008) -#define HAL_FLASH_ERROR_SIZ ((uint32_t)0x00000010) -#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000020) -#define HAL_FLASH_ERROR_MIS ((uint32_t)0x00000040) -#define HAL_FLASH_ERROR_FAST ((uint32_t)0x00000080) -#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000100) -#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x00000200) -#define HAL_FLASH_ERROR_ECCD ((uint32_t)0x00000400) -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define HAL_FLASH_ERROR_PEMPTY ((uint32_t)0x00000800) -#endif -/** - * @} - */ - -/** @defgroup FLASH_Type_Erase FLASH Erase Type - * @{ - */ -#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!> 24) /*!< ECC Correction Interrupt source */ -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Macros FLASH Exported Macros - * @brief macros to control FLASH features - * @{ - */ - -/** - * @brief Set the FLASH Latency. - * @param __LATENCY__: FLASH Latency - * This parameter can be one of the following values : - * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state - * @arg FLASH_LATENCY_2: FLASH Two wait states - * @arg FLASH_LATENCY_3: FLASH Three wait states - * @arg FLASH_LATENCY_4: FLASH Four wait states - * @retval None - */ -#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))) - -/** - * @brief Get the FLASH Latency. - * @retval FLASH Latency - * This parameter can be one of the following values : - * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state - * @arg FLASH_LATENCY_2: FLASH Two wait states - * @arg FLASH_LATENCY_3: FLASH Three wait states - * @arg FLASH_LATENCY_4: FLASH Four wait states - */ -#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) - -/** - * @brief Enable the FLASH prefetch buffer. - * @retval None - */ -#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) - -/** - * @brief Disable the FLASH prefetch buffer. - * @retval None - */ -#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) - -/** - * @brief Enable the FLASH instruction cache. - * @retval none - */ -#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) - -/** - * @brief Disable the FLASH instruction cache. - * @retval none - */ -#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) - -/** - * @brief Enable the FLASH data cache. - * @retval none - */ -#define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN) - -/** - * @brief Disable the FLASH data cache. - * @retval none - */ -#define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN) - -/** - * @brief Reset the FLASH instruction Cache. - * @note This function must be used only when the Instruction Cache is disabled. - * @retval None - */ -#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ - } while (0) - -/** - * @brief Reset the FLASH data Cache. - * @note This function must be used only when the data Cache is disabled. - * @retval None - */ -#define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \ - } while (0) - -/** - * @brief Enable the FLASH power down during Low-power run mode. - * @note Writing this bit to 0 this bit, automatically the keys are - * loss and a new unlock sequence is necessary to re-write it to 1. - */ -#define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ - WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ - SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ - } while (0) - -/** - * @brief Disable the FLASH power down during Low-power run mode. - * @note Writing this bit to 0 this bit, automatically the keys are - * loss and a new unlock sequence is necessary to re-write it to 1. - */ -#define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \ - WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ - } while (0) - -/** - * @brief Enable the FLASH power down during Low-Power sleep mode - * @retval none - */ -#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) - -/** - * @brief Disable the FLASH power down during Low-Power sleep mode - * @retval none - */ -#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) - -/** - * @} - */ - -/** @defgroup FLASH_Interrupt FLASH Interrupts Macros - * @brief macros to handle FLASH interrupts - * @{ - */ - -/** - * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__: FLASH interrupt - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_OPERR: Error Interrupt - * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt - * @arg FLASH_IT_ECCC: ECC Correction Interrupt - * @retval none - */ -#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ - if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ - } while(0) - -/** - * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__: FLASH interrupt - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_OPERR: Error Interrupt - * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt - * @arg FLASH_IT_ECCC: ECC Correction Interrupt - * @retval none - */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ - if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ - } while(0) - -/** - * @brief Check whether the specified FLASH flag is set or not. - * @param __FLAG__: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH Operation error flag - * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH Size error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag - * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag - * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag - * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag - * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag - * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag - * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices) - * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected - * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) ? \ - (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ - (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) - -/** - * @brief Clear the FLASH's pending flags. - * @param __FLAG__: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH Operation error flag - * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH Size error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag - * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag - * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag - * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag - * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag - * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected - * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected - * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags - * @retval None - */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ - if((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ - } while(0) -/** - * @} - */ - -/* Include FLASH HAL Extended module */ -#include "stm32l4xx_hal_flash_ex.h" -#include "stm32l4xx_hal_flash_ramfunc.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASH_Exported_Functions - * @{ - */ - -/* Program operation functions ***********************************************/ -/** @addtogroup FLASH_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -/* FLASH IRQ handler method */ -void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ -void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); -void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); -/** - * @} - */ - -/* Peripheral Control functions **********************************************/ -/** @addtogroup FLASH_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_Lock(void); -/* Option bytes control */ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); -/** - * @} - */ - -/* Peripheral State functions ************************************************/ -/** @addtogroup FLASH_Exported_Functions_Group3 - * @{ - */ -uint32_t HAL_FLASH_GetError(void); -/** - * @} - */ - -/** - * @} - */ - -/* Private constants --------------------------------------------------------*/ -/** @defgroup FLASH_Private_Constants FLASH Private Constants - * @{ - */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x800 << 10) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) -#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x200 << 10) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) -#else -#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10)) -#endif - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) -#else -#define FLASH_BANK_SIZE (FLASH_SIZE) -#endif - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define FLASH_PAGE_SIZE ((uint32_t)0x1000) -#define FLASH_PAGE_SIZE_128_BITS ((uint32_t)0x2000) -#else -#define FLASH_PAGE_SIZE ((uint32_t)0x800) -#endif - -#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ - -#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ - ((VALUE) == FLASH_TYPEERASE_MASSERASE)) - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ - ((BANK) == FLASH_BANK_2) || \ - ((BANK) == FLASH_BANK_BOTH)) - -#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ - ((BANK) == FLASH_BANK_2)) -#else -#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) - -#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) -#endif - -#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \ - ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST)) - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_BASE+0x1FFFFF)) -#else -#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \ - ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \ - ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \ - ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? \ - ((ADDRESS) <= FLASH_BASE+0x1FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF)))))) -#endif - -#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF)) - -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS)) - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_FLASH_PAGE(PAGE) ((PAGE) < 256) -#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) -#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \ - ((PAGE) < 256))))) -#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 256) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \ - ((PAGE) < 256)))) -#else -#define IS_FLASH_PAGE(PAGE) (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 128) : \ - ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x80) ? ((PAGE) < 64) : \ - ((PAGE) < 128)))) -#endif - -#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP))) - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ - ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) -#else -#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) -#endif - -#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ - ((LEVEL) == OB_RDP_LEVEL_1)/* ||\ - ((LEVEL) == OB_RDP_LEVEL_2)*/) - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0xFFFF) && ((TYPE) != 0)) -#elif defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0)) -#else -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x7E7F) && ((TYPE) != 0) && (((TYPE)&0x0180) == 0)) -#endif - -#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ - ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ - ((LEVEL) == OB_BOR_LEVEL_4)) - -#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) - -#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) - -#define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) - -#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) - -#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) - -#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) - -#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE)) - -#define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) -#endif - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) -#endif - -#define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) - -#define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) - -#define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) - -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ - defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) - -#define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_BOOT0_RESET) || ((VALUE) == OB_BOOT0_SET)) -#endif - -#define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE)) - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ - ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ - ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ - ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ - ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ - ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ - ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ - ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) -#else -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ - ((LATENCY) == FLASH_LATENCY_1) || \ - ((LATENCY) == FLASH_LATENCY_2) || \ - ((LATENCY) == FLASH_LATENCY_3) || \ - ((LATENCY) == FLASH_LATENCY_4)) -#endif -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_FLASH_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h deleted file mode 100644 index 63d5c9fcd..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_flash_ex.h - * @author MCD Application Team - * @brief Header file of FLASH HAL Extended module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_FLASH_EX_H -#define __STM32L4xx_HAL_FLASH_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASHEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -#if defined (FLASH_CFGR_LVEN) -/** @addtogroup FLASHEx_Exported_Constants - * @{ - */ -/** @defgroup FLASHEx_LVE_PIN_CFG FLASHEx LVE pin configuration - * @{ - */ -#define FLASH_LVE_PIN_CTRL 0x00000000U /*!< LVE FLASH pin controlled by power controller */ -#define FLASH_LVE_PIN_FORCED FLASH_CFGR_LVEN /*!< LVE FLASH pin enforced to low (external SMPS used) */ -/** - * @} - */ - -/** - * @} - */ -#endif /* FLASH_CFGR_LVEN */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASHEx_Exported_Functions - * @{ - */ - -/* Extended Program operation functions *************************************/ -/** @addtogroup FLASHEx_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); -/** - * @} - */ - -#if defined (FLASH_CFGR_LVEN) -/** @addtogroup FLASHEx_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE); -/** - * @} - */ -#endif /* FLASH_CFGR_LVEN */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** - @cond 0 - */ -#if defined (FLASH_CFGR_LVEN) -#define IS_FLASH_LVE_PIN(CFG) (((CFG) == FLASH_LVE_PIN_CTRL) || ((CFG) == FLASH_LVE_PIN_FORCED)) -#endif /* FLASH_CFGR_LVEN */ -/** - @endcond - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_FLASH_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h deleted file mode 100644 index b0988b027..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_flash_ramfunc.h - * @author MCD Application Team - * @brief Header file of FLASH RAMFUNC driver. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_FLASH_RAMFUNC_H -#define __STM32L4xx_FLASH_RAMFUNC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH_RAMFUNC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC HAL_StatusTypeDef - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc HAL_StatusTypeDef - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) - -#endif - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASH_RAMFUNC_Exported_Functions - * @{ - */ - -/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 - * @{ - */ -/* Peripheral Control functions ************************************************/ -__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void); -__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void); -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -__RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig); -#endif -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_FLASH_RAMFUNC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h deleted file mode 100644 index 9f4bbac54..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h +++ /dev/null @@ -1,316 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_gpio.h - * @author MCD Application Team - * @brief Header file of GPIO HAL module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_GPIO_H -#define __STM32L4xx_HAL_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Types GPIO Exported Types - * @{ - */ -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_mode */ - - uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. - This parameter can be a value of @ref GPIO_pull */ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_speed */ - - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins - This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ -}GPIO_InitTypeDef; - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - GPIO_PIN_RESET = 0, - GPIO_PIN_SET -}GPIO_PinState; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Constants GPIO Exported Constants - * @{ - */ -/** @defgroup GPIO_pins GPIO pins - * @{ - */ -#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ - -#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ -/** - * @} - */ - -/** @defgroup GPIO_mode GPIO mode - * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, Alternate or Analog) - * @{ - */ -#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ -#define GPIO_MODE_ANALOG_ADC_CONTROL ((uint32_t)0x0000000B) /*!< Analog Mode for ADC conversion */ -#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ -/** - * @} - */ - -/** @defgroup GPIO_speed GPIO speed - * @brief GPIO Output Maximum frequency - * @{ - */ -#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< range up to 5 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< range 5 MHz to 25 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< range 50 MHz to 80 MHz, please refer to the product datasheet */ -/** - * @} - */ - - /** @defgroup GPIO_pull GPIO pull - * @brief GPIO Pull-Up or Pull-Down Activation - * @{ - */ -#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ -#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** - * @brief Check whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__: specifies the EXTI line flag to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) - -/** - * @brief Clear the EXTI's line pending flags. - * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) - -/** - * @brief Check whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__: specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) - -/** - * @brief Clear the EXTI's line pending bits. - * @param __EXTI_LINE__: specifies the EXTI lines to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ -#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) - -#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\ - (((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00)) - -#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ - ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ - ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ - ((__MODE__) == GPIO_MODE_AF_PP) ||\ - ((__MODE__) == GPIO_MODE_AF_OD) ||\ - ((__MODE__) == GPIO_MODE_IT_RISING) ||\ - ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ - ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ - ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ - ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ - ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ - ((__MODE__) == GPIO_MODE_ANALOG) ||\ - ((__MODE__) == GPIO_MODE_ANALOG_ADC_CONTROL)) - -#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ - ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ - ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ - ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) - -#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ - ((__PULL__) == GPIO_PULLUP) || \ - ((__PULL__) == GPIO_PULLDOWN)) -/** - * @} - */ - -/* Include GPIO HAL Extended module */ -#include "stm32l4xx_hal_gpio_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * @{ - */ - -/* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); - -/** - * @} - */ - -/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_GPIO_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h deleted file mode 100644 index 63c69cb9e..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h +++ /dev/null @@ -1,822 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_gpio_ex.h - * @author MCD Application Team - * @brief Header file of GPIO HAL Extended module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_GPIO_EX_H -#define __STM32L4xx_HAL_GPIO_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIOEx GPIOEx - * @brief GPIO Extended HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants - * @{ - */ - -/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection - * @{ - */ - -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) -/*--------------STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx---*/ -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#if defined(STM32L433xx) || defined(STM32L443xx) -#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */ -#endif /* STM32L433xx || STM32L443xx */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART1 Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ -#define GPIO_AF6_COMP1 ((uint8_t)0x06) /* COMP1 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) -#define GPIO_AF10_USB_FS ((uint8_t)0x0A) /* USB_FS Alternate Function mapping */ -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ -#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */ - -#if defined(STM32L433xx) || defined(STM32L443xx) -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */ -#endif /* STM32L433xx || STM32L443xx */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_SWPMI1 ((uint8_t)0x0C) /* SWPMI1 Alternate Function mapping */ -#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ -#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ -#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ -#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) - -#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ - -#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) -/*--------------STM32L451xx/STM32L452xx/STM32L462xx---------------------------*/ -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_I2C4 ((uint8_t)0x02) /* I2C4 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ -#define GPIO_AF3_CAN1 ((uint8_t)0x03) /* CAN1 Alternate Function mapping */ -#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF6_COMP1 ((uint8_t)0x06) /* COMP1 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ - - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#if defined(STM32L452xx) || defined(STM32L462xx) -#define GPIO_AF10_USB_FS ((uint8_t)0x0A) /* USB_FS Alternate Function mapping */ -#endif /* STM32L452xx || STM32L462xx */ -#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */ -#define GPIO_AF10_CAN1 ((uint8_t)0x0A) /* CAN1 Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ -#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ -#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ -#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ -#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) - -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) -/*--------------STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx/STM32L486xx---*/ -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#if defined(STM32L476xx) || defined(STM32L486xx) -#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */ -#endif /* STM32L476xx || STM32L486xx */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ -#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ - - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ -#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */ - -#if defined(STM32L476xx) || defined(STM32L486xx) -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */ -#endif /* STM32L476xx || STM32L486xx */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#define GPIO_AF12_SWPMI1 ((uint8_t)0x0C) /* SWPMI1 Alternate Function mapping */ -#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ -#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ -#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */ -#define GPIO_AF13_TIM8_COMP2 ((uint8_t)0x0D) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ -#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ -#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ -#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM8_COMP1 ((uint8_t)0x0E) /* TIM8/COMP1 Break in Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - -#if defined(STM32L496xx) || defined(STM32L4A6xx) -/*--------------------------------STM32L496xx/STM32L4A6xx---------------------*/ -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ -#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -#define GPIO_AF2_I2C4 ((uint8_t)0x02) /* I2C4 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF3_CAN2 ((uint8_t)0x03) /* CAN2 Alternate Function mapping */ -#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ -#define GPIO_AF3_QUADSPI ((uint8_t)0x03) /* QUADSPI Alternate Function mapping */ -#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */ -#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ -#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */ -#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */ -#define GPIO_AF5_QUADSPI ((uint8_t)0x05) /* QUADSPI Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF8_CAN2 ((uint8_t)0x08) /* CAN2 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */ -#define GPIO_AF10_CAN2 ((uint8_t)0x0A) /* CAN2 Alternate Function mapping */ -#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_LCD ((uint8_t)0x0B) /* LCD Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#define GPIO_AF12_SWPMI1 ((uint8_t)0x0C) /* SWPMI1 Alternate Function mapping */ -#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ -#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ -#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */ -#define GPIO_AF13_TIM8_COMP2 ((uint8_t)0x0D) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ -#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ -#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ -#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM8_COMP1 ((uint8_t)0x0E) /* TIM8/COMP1 Break in Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) - -#endif /* STM32L496xx || STM32L4A6xx */ - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -/*---STM32L4R5xx/STM32L4R7xx/STM32L4R9xx/STM32L4S5xx/STM32L4S7xx/STM32L4S9xx--*/ -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ -#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ -#define GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OctoSPI Manager Port 1 Alternate Function mapping */ -#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */ -#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ -#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */ -#define GPIO_AF5_DFSDM1 ((uint8_t)0x05) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */ -#define GPIO_AF5_OCTOSPIM_P1 ((uint8_t)0x05) /* OctoSPI Manager Port 1 Alternate Function mapping */ -#define GPIO_AF5_OCTOSPIM_P2 ((uint8_t)0x05) /* OctoSPI Manager Port 2 Alternate Function mapping */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */ -#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */ -#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OctoSPI Manager Port 1 Alternate Function mapping */ -#define GPIO_AF10_OCTOSPIM_P2 ((uint8_t)0x0A) /* OctoSPI Manager Port 2 Alternate Function mapping */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_DSI ((uint8_t)0x0B) /* DSI Alternate Function mapping */ -#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ -#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#define GPIO_AF12_DSI ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ -#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */ -#define GPIO_AF13_TIM8_COMP1 ((uint8_t)0x0D) /* TIM8/COMP1 Break in Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ -#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ -#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ -#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM8_COMP2 ((uint8_t)0x0E) /* TIM8/COMP2 Break in Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros - * @{ - */ - -/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index -* @{ - */ -#if defined(STM32L431xx) || defined(STM32L433xx) || defined(STM32L443xx) - -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U : 7U) - -#endif /* STM32L431xx || STM32L433xx || STM32L443xx */ - -#if defined(STM32L432xx) || defined(STM32L442xx) - -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U : 7U) - -#endif /* STM32L432xx || STM32L442xx */ - -#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) - -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U : 7U) - -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) - -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U : 7U) - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - -#if defined(STM32L496xx) || defined(STM32L4A6xx) - -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) - -#endif /* STM32L496xx || STM32L4A6xx */ - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_GPIO_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h deleted file mode 100644 index 7a8f85f29..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h +++ /dev/null @@ -1,708 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_i2c.h - * @author MCD Application Team - * @brief Header file of I2C HAL module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_I2C_H -#define __STM32L4xx_HAL_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup I2C_Exported_Types I2C Exported Types - * @{ - */ - -/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition - * @brief I2C Configuration Structure definition - * @{ - */ -typedef struct -{ - uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization - section in Reference manual */ - - uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_ADDRESSING_MODE */ - - uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ - - uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ - - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ - - uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ - - uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ - -} I2C_InitTypeDef; - -/** - * @} - */ - -/** @defgroup HAL_state_structure_definition HAL state structure definition - * @brief HAL State structure definition - * @note HAL I2C State value coding follow below described bitmap :\n - * b7-b6 Error information\n - * 00 : No Error\n - * 01 : Abort (Abort user request on going)\n - * 10 : Timeout\n - * 11 : Error\n - * b5 IP initilisation status\n - * 0 : Reset (IP not initialized)\n - * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n - * b4 (not used)\n - * x : Should be set to 0\n - * b3\n - * 0 : Ready or Busy (No Listen mode ongoing)\n - * 1 : Listen (IP in Address Listen Mode)\n - * b2 Intrinsic process state\n - * 0 : Ready\n - * 1 : Busy (IP busy with some configuration or internal operations)\n - * b1 Rx state\n - * 0 : Ready (no Rx operation ongoing)\n - * 1 : Busy (Rx operation ongoing)\n - * b0 Tx state\n - * 0 : Ready (no Tx operation ongoing)\n - * 1 : Busy (Tx operation ongoing) - * @{ - */ -typedef enum -{ - HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ - HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ - HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ - HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ - HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission - process is ongoing */ - HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception - process is ongoing */ - HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ - -} HAL_I2C_StateTypeDef; - -/** - * @} - */ - -/** @defgroup HAL_mode_structure_definition HAL mode structure definition - * @brief HAL Mode structure definition - * @note HAL I2C Mode value coding follow below described bitmap :\n - * b7 (not used)\n - * x : Should be set to 0\n - * b6\n - * 0 : None\n - * 1 : Memory (HAL I2C communication is in Memory Mode)\n - * b5\n - * 0 : None\n - * 1 : Slave (HAL I2C communication is in Slave Mode)\n - * b4\n - * 0 : None\n - * 1 : Master (HAL I2C communication is in Master Mode)\n - * b3-b2-b1-b0 (not used)\n - * xxxx : Should be set to 0000 - * @{ - */ -typedef enum -{ - HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ - HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ - HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ - HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ - -} HAL_I2C_ModeTypeDef; - -/** - * @} - */ - -/** @defgroup I2C_Error_Code_definition I2C Error Code definition - * @brief I2C Error Code definition - * @{ - */ -#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ -#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ -#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ -#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ -#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ -/** - * @} - */ - -/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition - * @brief I2C handle Structure definition - * @{ - */ -typedef struct __I2C_HandleTypeDef -{ - I2C_TypeDef *Instance; /*!< I2C registers base address */ - - I2C_InitTypeDef Init; /*!< I2C communication parameters */ - - uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ - - uint16_t XferSize; /*!< I2C transfer size */ - - __IO uint16_t XferCount; /*!< I2C transfer counter */ - - __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can - be a value of @ref I2C_XFEROPTIONS */ - - __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - - HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ - - DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ - - HAL_LockTypeDef Lock; /*!< I2C locking object */ - - __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ - - __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ - - __IO uint32_t ErrorCode; /*!< I2C Error code */ - - __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ -} I2C_HandleTypeDef; -/** - * @} - */ - -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Constants I2C Exported Constants - * @{ - */ - -/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options - * @{ - */ -#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) -#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -/** - * @} - */ - -/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode - * @{ - */ -#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) -#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) -/** - * @} - */ - -/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode - * @{ - */ -#define I2C_DUALADDRESS_DISABLE (0x00000000U) -#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN -/** - * @} - */ - -/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks - * @{ - */ -#define I2C_OA2_NOMASK ((uint8_t)0x00U) -#define I2C_OA2_MASK01 ((uint8_t)0x01U) -#define I2C_OA2_MASK02 ((uint8_t)0x02U) -#define I2C_OA2_MASK03 ((uint8_t)0x03U) -#define I2C_OA2_MASK04 ((uint8_t)0x04U) -#define I2C_OA2_MASK05 ((uint8_t)0x05U) -#define I2C_OA2_MASK06 ((uint8_t)0x06U) -#define I2C_OA2_MASK07 ((uint8_t)0x07U) -/** - * @} - */ - -/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode - * @{ - */ -#define I2C_GENERALCALL_DISABLE (0x00000000U) -#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN -/** - * @} - */ - -/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode - * @{ - */ -#define I2C_NOSTRETCH_DISABLE (0x00000000U) -#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH -/** - * @} - */ - -/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size - * @{ - */ -#define I2C_MEMADD_SIZE_8BIT (0x00000001U) -#define I2C_MEMADD_SIZE_16BIT (0x00000002U) -/** - * @} - */ - -/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View - * @{ - */ -#define I2C_DIRECTION_TRANSMIT (0x00000000U) -#define I2C_DIRECTION_RECEIVE (0x00000001U) -/** - * @} - */ - -/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode - * @{ - */ -#define I2C_RELOAD_MODE I2C_CR2_RELOAD -#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND -#define I2C_SOFTEND_MODE (0x00000000U) -/** - * @} - */ - -/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode - * @{ - */ -#define I2C_NO_STARTSTOP (0x00000000U) -#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) -#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) -/** - * @} - */ - -/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition - * @brief I2C Interrupt definition - * Elements values convention: 0xXXXXXXXX - * - XXXXXXXX : Interrupt control mask - * @{ - */ -#define I2C_IT_ERRI I2C_CR1_ERRIE -#define I2C_IT_TCI I2C_CR1_TCIE -#define I2C_IT_STOPI I2C_CR1_STOPIE -#define I2C_IT_NACKI I2C_CR1_NACKIE -#define I2C_IT_ADDRI I2C_CR1_ADDRIE -#define I2C_IT_RXI I2C_CR1_RXIE -#define I2C_IT_TXI I2C_CR1_TXIE -/** - * @} - */ - -/** @defgroup I2C_Flag_definition I2C Flag definition - * @{ - */ -#define I2C_FLAG_TXE I2C_ISR_TXE -#define I2C_FLAG_TXIS I2C_ISR_TXIS -#define I2C_FLAG_RXNE I2C_ISR_RXNE -#define I2C_FLAG_ADDR I2C_ISR_ADDR -#define I2C_FLAG_AF I2C_ISR_NACKF -#define I2C_FLAG_STOPF I2C_ISR_STOPF -#define I2C_FLAG_TC I2C_ISR_TC -#define I2C_FLAG_TCR I2C_ISR_TCR -#define I2C_FLAG_BERR I2C_ISR_BERR -#define I2C_FLAG_ARLO I2C_ISR_ARLO -#define I2C_FLAG_OVR I2C_ISR_OVR -#define I2C_FLAG_PECERR I2C_ISR_PECERR -#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT -#define I2C_FLAG_ALERT I2C_ISR_ALERT -#define I2C_FLAG_BUSY I2C_ISR_BUSY -#define I2C_FLAG_DIR I2C_ISR_DIR -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Macros I2C Exported Macros - * @{ - */ - -/** @brief Reset I2C handle state. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) - -/** @brief Enable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) - -/** @brief Disable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - -/** @brief Check whether the specified I2C interrupt source is enabled or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the I2C interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Check whether the specified I2C flag is set or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref I2C_FLAG_TXE Transmit data register empty - * @arg @ref I2C_FLAG_TXIS Transmit interrupt status - * @arg @ref I2C_FLAG_RXNE Receive data register not empty - * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure received flag - * @arg @ref I2C_FLAG_STOPF STOP detection flag - * @arg @ref I2C_FLAG_TC Transfer complete (master mode) - * @arg @ref I2C_FLAG_TCR Transfer complete reload - * @arg @ref I2C_FLAG_BERR Bus error - * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun - * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref I2C_FLAG_ALERT SMBus alert - * @arg @ref I2C_FLAG_BUSY Bus busy - * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) - * - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) - -/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg @ref I2C_FLAG_TXE Transmit data register empty - * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure received flag - * @arg @ref I2C_FLAG_STOPF STOP detection flag - * @arg @ref I2C_FLAG_BERR Bus error - * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun - * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref I2C_FLAG_ALERT SMBus alert - * - * @retval None - */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ - : ((__HANDLE__)->Instance->ICR = (__FLAG__))) - -/** @brief Enable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Disable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) -/** - * @} - */ - -/* Include I2C HAL Extended module */ -#include "stm32l4xx_hal_i2c_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2C_Exported_Functions - * @{ - */ - -/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -/* Initialization and de-initialization functions******************************/ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ -/* IO operation functions ****************************************************/ -/******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); - -/******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); - -/******* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -/** - * @} - */ - -/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ -/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); -void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @{ - */ -/* Peripheral State, Mode and Error functions *********************************/ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); - -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Constants I2C Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2C_Private_Macro I2C Private Macros - * @{ - */ - -#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == I2C_ADDRESSINGMODE_10BIT)) - -#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) - -#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ - ((MASK) == I2C_OA2_MASK01) || \ - ((MASK) == I2C_OA2_MASK02) || \ - ((MASK) == I2C_OA2_MASK03) || \ - ((MASK) == I2C_OA2_MASK04) || \ - ((MASK) == I2C_OA2_MASK05) || \ - ((MASK) == I2C_OA2_MASK06) || \ - ((MASK) == I2C_OA2_MASK07)) - -#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ - ((CALL) == I2C_GENERALCALL_ENABLE)) - -#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLE)) - -#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) - -#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ - ((MODE) == I2C_AUTOEND_MODE) || \ - ((MODE) == I2C_SOFTEND_MODE)) - -#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ - ((REQUEST) == I2C_GENERATE_START_READ) || \ - ((REQUEST) == I2C_GENERATE_START_WRITE) || \ - ((REQUEST) == I2C_NO_STARTSTOP)) - -#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ - ((REQUEST) == I2C_NEXT_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME)) - -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) - -#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U) -#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) -#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) -#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1) -#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2) - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) - -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) - -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -/* Private functions are defined in stm32l4xx_hal_i2c.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L4xx_HAL_I2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h deleted file mode 100644 index 726a83fba..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h +++ /dev/null @@ -1,186 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_i2c_ex.h - * @author MCD Application Team - * @brief Header file of I2C HAL Extended module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_I2C_EX_H -#define __STM32L4xx_HAL_I2C_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2CEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants - * @{ - */ - -/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter - * @{ - */ -#define I2C_ANALOGFILTER_ENABLE 0x00000000U -#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF -/** - * @} - */ - -/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus - * @{ - */ -#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ -#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ -#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ -#if defined(SYSCFG_CFGR1_I2C_PB8_FMP) -#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ -#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ -#else -#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */ -#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */ -#endif -#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ -#if defined(SYSCFG_CFGR1_I2C2_FMP) -#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ -#else -#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ -#endif -#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ -#if defined(SYSCFG_CFGR1_I2C4_FMP) -#define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ -#else -#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */ -#endif -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions - * @{ - */ - -/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); -void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); -void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros - * @{ - */ -#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLE)) - -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) - -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ - ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \ - (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4))) -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions - * @{ - */ -/* Private functions are defined in stm32l4xx_hal_i2c_ex.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_I2C_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h deleted file mode 100644 index 51e0e5740..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h +++ /dev/null @@ -1,874 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pcd.h - * @author MCD Application Team - * @brief Header file of PCD HAL module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_PCD_H -#define __STM32L4xx_HAL_PCD_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_ll_usb.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup PCD - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup PCD_Exported_Types PCD Exported Types - * @{ - */ - - /** - * @brief PCD State structure definition - */ -typedef enum -{ - HAL_PCD_STATE_RESET = 0x00, - HAL_PCD_STATE_READY = 0x01, - HAL_PCD_STATE_ERROR = 0x02, - HAL_PCD_STATE_BUSY = 0x03, - HAL_PCD_STATE_TIMEOUT = 0x04 -} PCD_StateTypeDef; - -/* Device LPM suspend state */ -typedef enum -{ - LPM_L0 = 0x00, /* on */ - LPM_L1 = 0x01, /* LPM L1 sleep */ - LPM_L2 = 0x02, /* suspend */ - LPM_L3 = 0x03, /* off */ -}PCD_LPM_StateTypeDef; - -#if defined (USB) -/** - * @brief PCD double buffered endpoint direction - */ -typedef enum -{ - PCD_EP_DBUF_OUT, - PCD_EP_DBUF_IN, - PCD_EP_DBUF_ERR, -}PCD_EP_DBUF_DIR; - -/** - * @brief PCD endpoint buffer number - */ -typedef enum -{ - PCD_EP_NOBUF, - PCD_EP_BUF0, - PCD_EP_BUF1 -}PCD_EP_BUF_NUM; -#endif /* USB */ - -#if defined (USB_OTG_FS) -typedef USB_OTG_GlobalTypeDef PCD_TypeDef; -typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; -typedef USB_OTG_EPTypeDef PCD_EPTypeDef; -#endif /* USB_OTG_FS */ - -#if defined (USB) -typedef USB_TypeDef PCD_TypeDef; -typedef USB_CfgTypeDef PCD_InitTypeDef; -typedef USB_EPTypeDef PCD_EPTypeDef; -#endif /* USB */ - -/** - * @brief PCD Handle Structure definition - */ -typedef struct -{ - PCD_TypeDef *Instance; /*!< Register base address */ - PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address: not used by USB OTG FS */ - PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */ - HAL_LockTypeDef Lock; /*!< PCD peripheral status */ - __IO PCD_StateTypeDef State; /*!< PCD communication state */ - uint32_t Setup[12]; /*!< Setup packet buffer */ - PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ - uint32_t BESL; - - - uint32_t lpm_active; /*!< Enable or disable the Link Power Management . - This parameter can be set to ENABLE or DISABLE */ - - uint32_t battery_charging_active; /*!< Enable or disable Battery charging. - This parameter can be set to ENABLE or DISABLE */ - void *pData; /*!< Pointer to upper stack Handler */ - -} PCD_HandleTypeDef; - -/** - * @} - */ - -/* Include PCD HAL Extended module */ -#include "stm32l4xx_hal_pcd_ex.h" - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PCD_Exported_Constants PCD Exported Constants - * @{ - */ - -/** @defgroup PCD_Speed PCD Speed - * @{ - */ -#define PCD_SPEED_FULL 1 -/** - * @} - */ - -/** @defgroup PCD_PHY_Module PCD PHY Module - * @{ - */ -#define PCD_PHY_EMBEDDED 1 -/** - * @} - */ - -/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value - * @{ - */ -#ifndef USBD_FS_TRDT_VALUE - #define USBD_FS_TRDT_VALUE 5 -#endif /* USBD_FS_TRDT_VALUE */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup PCD_Exported_Macros PCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ -#if defined (USB_OTG_FS) -#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) - -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) -#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) - - -#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \ - ~(USB_OTG_PCGCCTL_STOPCLK) - -#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK - -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR1 & (USB_OTG_FS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR1 = USB_OTG_FS_WAKEUP_EXTI_LINE - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do {\ - EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\ - EXTI->FTSR1 |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - } while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\ - EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - EXTI->FTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= USB_OTG_FS_WAKEUP_EXTI_LINE) - -#endif /* USB_OTG_FS */ - -#if defined (USB) -#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) - -#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE -#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE) -#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR1 & (USB_WAKEUP_EXTI_LINE) -#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR1 = USB_WAKEUP_EXTI_LINE - -#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() do {\ - EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\ - EXTI->FTSR1 |= (USB_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - } while(0) - -#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\ - EXTI->RTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE);\ - EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE;\ - EXTI->FTSR1 |= USB_WAKEUP_EXTI_LINE;\ - } while(0) - -#define __HAL_USB_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= USB_WAKEUP_EXTI_LINE) - -#endif /* USB */ - -/** - * @} - */ - -/** @addtogroup PCD_Exported_Functions PCD Exported Functions - * @{ - */ - -/* Initialization/de-initialization functions ********************************/ -/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd); -void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); -void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); -/** - * @} - */ - -/* I/O operation functions ***************************************************/ -/* Non-Blocking mode: Interrupt */ -/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ - /* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); - -void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); -/** - * @} - */ - -/* Peripheral Control functions **********************************************/ -/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); -HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -/** - * @} - */ - -/* Peripheral State functions ************************************************/ -/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions - * @{ - */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup PCD_Private_Constants PCD Private Constants - * @{ - */ -/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt - * @{ - */ -#if defined (USB_OTG_FS) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08) -#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10) - -#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the USB EXTI Line */ -#endif /* USB_OTG_FS */ - -#if defined (USB) -#define USB_WAKEUP_EXTI_LINE ((uint32_t)0x00020000) /*!< External interrupt line 17Connected to the USB EXTI Line */ -#endif /* USB */ - -/** - * @} - */ - -#if defined (USB) -/** @defgroup PCD_EP0_MPS PCD EP0 MPS - * @{ - */ -#define PCD_EP0MPS_64 DEP0CTL_MPS_64 -#define PCD_EP0MPS_32 DEP0CTL_MPS_32 -#define PCD_EP0MPS_16 DEP0CTL_MPS_16 -#define PCD_EP0MPS_08 DEP0CTL_MPS_8 -/** - * @} - */ - -/** @defgroup PCD_ENDP PCD ENDP - * @{ - */ -#define PCD_ENDP0 ((uint8_t)0) -#define PCD_ENDP1 ((uint8_t)1) -#define PCD_ENDP2 ((uint8_t)2) -#define PCD_ENDP3 ((uint8_t)3) -#define PCD_ENDP4 ((uint8_t)4) -#define PCD_ENDP5 ((uint8_t)5) -#define PCD_ENDP6 ((uint8_t)6) -#define PCD_ENDP7 ((uint8_t)7) -/** - * @} - */ - -/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind - * @{ - */ -#define PCD_SNG_BUF 0 -#define PCD_DBL_BUF 1 -/** - * @} - */ -#endif /* USB */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup PCD_Private_Macros PCD Private Macros - * @{ - */ -#if defined (USB) -/* SetENDPOINT */ -#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue)) - -/* GetENDPOINT */ -#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2)) - -/* ENDPOINT transfer */ -#define USB_EP0StartXfer USB_EPStartXfer - -/** - * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wType: Endpoint Type. - * @retval None - */ -#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) ))) - -/** - * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval Endpoint Type - */ -#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) - -/** - * @brief free buffer used from the application realizing it to the line - toggles bit SW_BUF in the double buffered endpoint register - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bDir: Direction - * @retval None - */ -#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\ -{\ - if ((bDir) == PCD_EP_DBUF_OUT)\ - { /* OUT double buffered endpoint */\ - PCD_TX_DTOG((USBx), (bEpNum));\ - }\ - else if ((bDir) == PCD_EP_DBUF_IN)\ - { /* IN double buffered endpoint */\ - PCD_RX_DTOG((USBx), (bEpNum));\ - }\ -} - -/** - * @brief gets direction of the double buffered endpoint - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval EP_DBUF_OUT, EP_DBUF_IN, - * EP_DBUF_ERR if the endpoint counter not yet programmed. - */ -#define PCD_GET_DB_DIR(USBx, bEpNum)\ -{\ - if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\ - return(PCD_EP_DBUF_OUT);\ - else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\ - return(PCD_EP_DBUF_IN);\ - else\ - return(PCD_EP_DBUF_ERR);\ -} - -/** - * @brief sets the status for tx transfer (bits STAT_TX[1:0]). - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wState: new state - * @retval None - */ -#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\ - \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\ - /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wState))!= 0)\ - { \ - _wRegVal ^= USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));\ - } /* PCD_SET_EP_TX_STATUS */ - -/** - * @brief sets the status for rx transfer (bits STAT_TX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wState: new state - * @retval None - */ -#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\ - register uint16_t _wRegVal; \ - \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\ - /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wState))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \ - } /* PCD_SET_EP_RX_STATUS */ - -/** - * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wStaterx: new state. - * @param wStatetx: new state. - * @retval None - */ -#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\ - register uint32_t _wRegVal; \ - \ - _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ - /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \ - { \ - _wRegVal ^= USB_EPRX_DTOG2; \ - } \ - /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \ - { \ - _wRegVal ^= USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \ - } /* PCD_SET_EP_TXRX_STATUS */ - -/** - * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] - * /STAT_RX[1:0]) - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval status - */ -#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) -#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT) - -/** - * @brief sets directly the VALID tx/rx-status into the endpoint register - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) -#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) - -/** - * @brief checks stall condition in an endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval TRUE = endpoint in stall condition. - */ -#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \ - == USB_EP_TX_STALL) -#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \ - == USB_EP_RX_STALL) - -/** - * @brief set & clear EP_KIND bit. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK)))) -#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK)))) - -/** - * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) -#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) - -/** - * @brief Sets/clears directly EP_KIND bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) -#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) - -/** - * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK)) -#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK)) - -/** - * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) -#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK))) - -/** - * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\ - { \ - PCD_RX_DTOG((USBx), (bEpNum)); \ - } -#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\ - { \ - PCD_TX_DTOG((USBx), (bEpNum)); \ - } - -/** - * @brief Sets address in an endpoint register. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bAddr: Address. - * @retval None - */ -#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\ - USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr)) - -#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) - -#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)(((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400))) - -#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ - uint16_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ - } - -/** - * @brief sets address of the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wAddr: address to be set (must be word aligned). - * @retval None - */ -#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) -#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) - -/** - * @brief Gets address of the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval address of the buffer. - */ -#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) -#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) - -/** - * @brief Sets counter of rx buffer with no. of blocks. - * @param dwReg: Register - * @param wCount: Counter. - * @param wNBlocks: no. of Blocks. - * @retval None - */ -#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 5;\ - if(((wCount) & 0x1f) == 0)\ - { \ - (wNBlocks)--;\ - } \ - *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \ - }/* PCD_CALC_BLK32 */ - -#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 1;\ - if(((wCount) & 0x1) != 0)\ - { \ - (wNBlocks)++;\ - } \ - *pdwReg = (uint16_t)((wNBlocks) << 10);\ - }/* PCD_CALC_BLK2 */ - -#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\ - uint16_t wNBlocks;\ - if((wCount) > 62) \ - { \ - PCD_CALC_BLK32((dwReg),(wCount),wNBlocks); \ - } \ - else \ - { \ - PCD_CALC_BLK2((dwReg),(wCount),wNBlocks); \ - } \ - }/* PCD_SET_EP_CNT_RX_REG */ - -#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\ - uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \ - PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\ - } - -/** - * @brief sets counter for the tx/rx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wCount: Counter value. - * @retval None - */ -#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount)) - - -/** - * @brief gets counter of the tx buffer. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval Counter value - */ -#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff) -#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff) - -/** - * @brief Sets buffer 0/1 address in a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wBuf0Addr: buffer 0 address. - * @retval Counter value - */ -#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));} -#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));} - -/** - * @brief Sets addresses in a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param wBuf0Addr: buffer 0 address. - * @param wBuf1Addr = buffer 1 address. - * @retval None - */ -#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \ - PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\ - PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\ - } /* PCD_SET_EP_DBUF_ADDR */ - -/** - * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) -#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) - -/** - * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @param bDir: endpoint dir EP_DBUF_OUT = OUT - * EP_DBUF_IN = IN - * @param wCount: Counter value - * @retval None - */ -#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \ - if((bDir) == PCD_EP_DBUF_OUT)\ - /* OUT endpoint */ \ - {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \ - else if((bDir) == PCD_EP_DBUF_IN)\ - /* IN endpoint */ \ - *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ - } /* SetEPDblBuf0Count*/ - -#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \ - if((bDir) == PCD_EP_DBUF_OUT)\ - {/* OUT endpoint */ \ - PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)); \ - } \ - else if((bDir) == PCD_EP_DBUF_IN)\ - {/* IN endpoint */ \ - *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \ - } \ - } /* SetEPDblBuf1Count */ - -#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\ - PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ - PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ - } /* PCD_SET_EP_DBUF_CNT */ - -/** - * @brief Gets buffer 0/1 rx/tx counter for double buffering. - * @param USBx: USB peripheral instance register address. - * @param bEpNum: Endpoint Number. - * @retval None - */ -#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) -#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) - -#endif /* USB */ - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) - -/** @defgroup PCD_Instance_definition PCD Instance definition - * @{ - */ -#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE -/** - * @} - */ -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L4xx_HAL_PCD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h deleted file mode 100644 index f27c8b6a4..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h +++ /dev/null @@ -1,136 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pcd_ex.h - * @author MCD Application Team - * @brief Header file of PCD HAL module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_PCD_EX_H -#define __STM32L4xx_HAL_PCD_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup PCDEx - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -typedef enum -{ - PCD_LPM_L0_ACTIVE = 0x00, /* on */ - PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ -}PCD_LPM_MsgTypeDef; - -typedef enum -{ - PCD_BCD_ERROR = 0xFF, - PCD_BCD_CONTACT_DETECTION = 0xFE, - PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, - PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, - PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, - PCD_BCD_DISCOVERY_COMPLETED = 0x00, - -}PCD_BCD_MsgTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/* Exported macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions - * @{ - */ -/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @{ - */ - -#if defined(USB_OTG_FS) -HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); -HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); -#endif /* USB_OTG_FS */ - -#if defined (USB) -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, - uint16_t ep_addr, - uint16_t ep_kind, - uint32_t pmaadress); -#endif /* USB */ -HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); -void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); -void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); -void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L4xx_HAL_PCD_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h deleted file mode 100644 index f33df34e8..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h +++ /dev/null @@ -1,427 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pwr.h - * @author MCD Application Team - * @brief Header file of PWR HAL module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_PWR_H -#define __STM32L4xx_HAL_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Types PWR Exported Types - * @{ - */ - -/** - * @brief PWR PVD configuration structure definition - */ -typedef struct -{ - uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. - This parameter can be a value of @ref PWR_PVD_detection_level. */ - - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWR_PVD_Mode. */ -}PWR_PVDTypeDef; - - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants PWR Exported Constants - * @{ - */ - - -/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels - * @{ - */ -#define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */ -#define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */ -#define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */ -#define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */ -#define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */ -#define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */ -#define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */ -#define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */ -/** - * @} - */ - -/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode - * @{ - */ -#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */ -#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ -/** - * @} - */ - - - - -/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode - * @{ - */ -#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */ -#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */ -/** - * @} - */ - -/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry - * @{ - */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */ -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */ -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry - * @{ - */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */ -#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */ -/** - * @} - */ - - -/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line - * @{ - */ -#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ -/** - * @} - */ - -/** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line - * @{ - */ -#define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup PWR_Exported_Macros PWR Exported Macros - * @{ - */ - -/** @brief Check whether or not a specific PWR flag is set. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event - * was received from the WKUP pin 1. - * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event - * was received from the WKUP pin 2. - * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event - * was received from the WKUP pin 3. - * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event - * was received from the WKUP pin 4. - * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event - * was received from the WKUP pin 5. - * @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system - * entered StandBy mode. - * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on - * the internal wakeup line. - * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the - * low-power regulator is ready. - * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the - * regulator is ready in main mode or is in low-power mode. - * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready - * in the selected voltage range or is still changing to the required voltage level. - * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is - * below or above the selected PVD threshold. - * @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is - * is below or above PVM1 threshold (applicable when USB feature is supported). - @if STM32L486xx - * @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is - * is below or above PVM2 threshold (applicable when VDDIO2 is present on device). - @endif - * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is - * is below or above PVM3 threshold. - * @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is - * is below or above PVM4 threshold. - * - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\ - (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\ - (PWR->SR2 & (1U << ((__FLAG__) & 31U))) ) - -/** @brief Clear a specific PWR flag. - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event - * was received from the WKUP pin 1. - * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event - * was received from the WKUP pin 2. - * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event - * was received from the WKUP pin 3. - * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event - * was received from the WKUP pin 4. - * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event - * was received from the WKUP pin 5. - * @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags. - * @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system - * entered Standby mode. - * @retval None - */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\ - (PWR->SCR = (__FLAG__)) :\ - (PWR->SCR = (1U << ((__FLAG__) & 31U))) ) -/** - * @brief Enable the PVD Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Enable the PVD Event Line. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) - -/** - * @brief Disable the PVD Event Line. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) - -/** - * @brief Enable the PVD Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Enable the PVD Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) - - -/** - * @brief Disable the PVD Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) - - -/** - * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) - -/** - * @brief Check whether or not the PVD EXTI interrupt flag is set. - * @retval EXTI PVD Line Status. - */ -#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD) - -/** - * @brief Clear the PVD EXTI interrupt flag. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD) - -/** - * @} - */ - - -/* Private macros --------------------------------------------------------*/ -/** @addtogroup PWR_Private_Macros PWR Private Macros - * @{ - */ - -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ - ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ - ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ - ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) - -#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\ - ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ - ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ - ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ - ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ - ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ - ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) - -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) - -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) - -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) - -/** - * @} - */ - -/* Include PWR HAL Extended module */ -#include "stm32l4xx_hal_pwr_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions *******************************/ -void HAL_PWR_DeInit(void); -void HAL_PWR_EnableBkUpAccess(void); -void HAL_PWR_DisableBkUpAccess(void); - -/** - * @} - */ - -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); -void HAL_PWR_EnablePVD(void); -void HAL_PWR_DisablePVD(void); - - -/* WakeUp pins configuration functions ****************************************/ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); - -/* Low Power modes configuration functions ************************************/ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -void HAL_PWR_EnterSTANDBYMode(void); - -void HAL_PWR_EnableSleepOnExit(void); -void HAL_PWR_DisableSleepOnExit(void); -void HAL_PWR_EnableSEVOnPend(void); -void HAL_PWR_DisableSEVOnPend(void); - -void HAL_PWR_PVDCallback(void); - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L4xx_HAL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h deleted file mode 100644 index 283047816..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h +++ /dev/null @@ -1,906 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pwr_ex.h - * @author MCD Application Team - * @brief Header file of PWR HAL Extended module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_PWR_EX_H -#define __STM32L4xx_HAL_PWR_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWREx - * @{ - */ - - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Types PWR Extended Exported Types - * @{ - */ - - -/** - * @brief PWR PVM configuration structure definition - */ -typedef struct -{ - uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. - This parameter can be a value of @ref PWREx_PVM_Type. - @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). -@if STM32L486xx - @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). -@endif - @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. - @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */ - - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWREx_PVM_Mode. */ -}PWR_PVMTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants - * @{ - */ - -/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants - * @{ - */ -#define PWR_WUP_POLARITY_SHIFT 0x05 /*!< Internal constant used to retrieve wakeup pin polariry */ -/** - * @} - */ - - -/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins - * @{ - */ -#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ -#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ -#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ -#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ -#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ -#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ -#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ -#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ -#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ -#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ -#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR4_WP1<IMR2, PWR_EXTI_LINE_PVM1) - -/** - * @brief Disable the PVM1 Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1) - -/** - * @brief Enable the PVM1 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) - -/** - * @brief Disable the PVM1 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1) - -/** - * @brief Enable the PVM1 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) - -/** - * @brief Disable the PVM1 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1) - -/** - * @brief Enable the PVM1 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) - - -/** - * @brief Disable the PVM1 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1) - - -/** - * @brief PVM1 EXTI line configuration: set rising & falling edge trigger. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1) - -/** - * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not. - * @retval EXTI PVM1 Line Status. - */ -#define __HAL_PWR_PVM1_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM1) - -/** - * @brief Clear the PVM1 EXTI flag. - * @retval None - */ -#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1) - -#endif /* PWR_CR2_PVME1 */ - - -#if defined(PWR_CR2_PVME2) -/** - * @brief Enable the PVM2 Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) - -/** - * @brief Disable the PVM2 Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2) - -/** - * @brief Enable the PVM2 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) - -/** - * @brief Disable the PVM2 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2) - -/** - * @brief Enable the PVM2 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) - -/** - * @brief Disable the PVM2 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2) - -/** - * @brief Enable the PVM2 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) - - -/** - * @brief Disable the PVM2 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2) - - -/** - * @brief PVM2 EXTI line configuration: set rising & falling edge trigger. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2) - -/** - * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not. - * @retval EXTI PVM2 Line Status. - */ -#define __HAL_PWR_PVM2_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM2) - -/** - * @brief Clear the PVM2 EXTI flag. - * @retval None - */ -#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2) - -#endif /* PWR_CR2_PVME2 */ - - -/** - * @brief Enable the PVM3 Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) - -/** - * @brief Disable the PVM3 Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3) - -/** - * @brief Enable the PVM3 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) - -/** - * @brief Disable the PVM3 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3) - -/** - * @brief Enable the PVM3 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) - -/** - * @brief Disable the PVM3 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3) - -/** - * @brief Enable the PVM3 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) - - -/** - * @brief Disable the PVM3 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3) - - -/** - * @brief PVM3 EXTI line configuration: set rising & falling edge trigger. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3) - -/** - * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not. - * @retval EXTI PVM3 Line Status. - */ -#define __HAL_PWR_PVM3_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM3) - -/** - * @brief Clear the PVM3 EXTI flag. - * @retval None - */ -#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3) - - - - -/** - * @brief Enable the PVM4 Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) - -/** - * @brief Disable the PVM4 Extended Interrupt Line. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4) - -/** - * @brief Enable the PVM4 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) - -/** - * @brief Disable the PVM4 Event Line. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4) - -/** - * @brief Enable the PVM4 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) - -/** - * @brief Disable the PVM4 Extended Interrupt Rising Trigger. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4) - -/** - * @brief Enable the PVM4 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) - - -/** - * @brief Disable the PVM4 Extended Interrupt Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4) - - -/** - * @brief PVM4 EXTI line configuration: set rising & falling edge trigger. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4) - -/** - * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set. - * @retval EXTI PVM4 Line Status. - */ -#define __HAL_PWR_PVM4_EXTI_GET_FLAG() (EXTI->PR2 & PWR_EXTI_LINE_PVM4) - -/** - * @brief Clear the PVM4 EXTI flag. - * @retval None - */ -#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4) - - -/** - * @brief Configure the main internal regulator output voltage. - * @param __REGULATOR__: specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption. - * This parameter can be one of the following values: - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, - * typical output voltage at 1.2 V, - * system frequency up to 80 MHz. - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, - * typical output voltage at 1.0 V, - * system frequency up to 26 MHz. - * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check - * whether or not VOSF flag is cleared when moving from range 2 to range 1. User - * may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting. - * @retval None - */ -#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ - __IO uint32_t tmpreg; \ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ - UNUSED(tmpreg); \ - } while(0) - -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros - * @{ - */ - -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2) || \ - ((PIN) == PWR_WAKEUP_PIN3) || \ - ((PIN) == PWR_WAKEUP_PIN4) || \ - ((PIN) == PWR_WAKEUP_PIN5) || \ - ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ - ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ - ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ - ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ - ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ - ((PIN) == PWR_WAKEUP_PIN5_LOW)) - -#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ - ((TYPE) == PWR_PVM_2) ||\ - ((TYPE) == PWR_PVM_3) ||\ - ((TYPE) == PWR_PVM_4)) -#elif defined (STM32L471xx) -#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\ - ((TYPE) == PWR_PVM_3) ||\ - ((TYPE) == PWR_PVM_4)) -#endif - -#if defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ - ((TYPE) == PWR_PVM_3) ||\ - ((TYPE) == PWR_PVM_4)) -#elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L442xx) || defined (STM32L451xx) -#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\ - ((TYPE) == PWR_PVM_4)) -#endif - -#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ - ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ - ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ - ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ - ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ - ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ - ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) - -#if defined(PWR_CR5_R1MODE) -#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) || \ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) -#else -#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) -#endif - - -#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ - ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) - -#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\ - ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) - -#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) - - -#if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ - ((GPIO) == PWR_GPIO_B) ||\ - ((GPIO) == PWR_GPIO_C) ||\ - ((GPIO) == PWR_GPIO_D) ||\ - ((GPIO) == PWR_GPIO_E) ||\ - ((GPIO) == PWR_GPIO_H)) -#elif defined (STM32L432xx) || defined (STM32L442xx) -#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ - ((GPIO) == PWR_GPIO_B) ||\ - ((GPIO) == PWR_GPIO_C) ||\ - ((GPIO) == PWR_GPIO_H)) -#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) -#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ - ((GPIO) == PWR_GPIO_B) ||\ - ((GPIO) == PWR_GPIO_C) ||\ - ((GPIO) == PWR_GPIO_D) ||\ - ((GPIO) == PWR_GPIO_E) ||\ - ((GPIO) == PWR_GPIO_F) ||\ - ((GPIO) == PWR_GPIO_G) ||\ - ((GPIO) == PWR_GPIO_H)) -#elif defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ - ((GPIO) == PWR_GPIO_B) ||\ - ((GPIO) == PWR_GPIO_C) ||\ - ((GPIO) == PWR_GPIO_D) ||\ - ((GPIO) == PWR_GPIO_E) ||\ - ((GPIO) == PWR_GPIO_F) ||\ - ((GPIO) == PWR_GPIO_G) ||\ - ((GPIO) == PWR_GPIO_H) ||\ - ((GPIO) == PWR_GPIO_I)) -#endif - - -/** - * @} - */ - - -/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions - * @{ - */ - -/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions - * @{ - */ - - -/* Peripheral Control functions **********************************************/ -uint32_t HAL_PWREx_GetVoltageRange(void); -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); -void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); -void HAL_PWREx_DisableBatteryCharging(void); -#if defined(PWR_CR2_USV) -void HAL_PWREx_EnableVddUSB(void); -void HAL_PWREx_DisableVddUSB(void); -#endif /* PWR_CR2_USV */ -#if defined(PWR_CR2_IOSV) -void HAL_PWREx_EnableVddIO2(void); -void HAL_PWREx_DisableVddIO2(void); -#endif /* PWR_CR2_IOSV */ -void HAL_PWREx_EnableInternalWakeUpLine(void); -void HAL_PWREx_DisableInternalWakeUpLine(void); -HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); -HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); -HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); -HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); -void HAL_PWREx_EnablePullUpPullDownConfig(void); -void HAL_PWREx_DisablePullUpPullDownConfig(void); -void HAL_PWREx_EnableSRAM2ContentRetention(void); -void HAL_PWREx_DisableSRAM2ContentRetention(void); -#if defined(PWR_CR1_RRSTP) -void HAL_PWREx_EnableSRAM3ContentRetention(void); -void HAL_PWREx_DisableSRAM3ContentRetention(void); -#endif /* PWR_CR1_RRSTP */ -#if defined(PWR_CR3_DSIPDEN) -void HAL_PWREx_EnableDSIPinsPDActivation(void); -void HAL_PWREx_DisableDSIPinsPDActivation(void); -#endif /* PWR_CR3_DSIPDEN */ -#if defined(PWR_CR2_PVME1) -void HAL_PWREx_EnablePVM1(void); -void HAL_PWREx_DisablePVM1(void); -#endif /* PWR_CR2_PVME1 */ -#if defined(PWR_CR2_PVME2) -void HAL_PWREx_EnablePVM2(void); -void HAL_PWREx_DisablePVM2(void); -#endif /* PWR_CR2_PVME2 */ -void HAL_PWREx_EnablePVM3(void); -void HAL_PWREx_DisablePVM3(void); -void HAL_PWREx_EnablePVM4(void); -void HAL_PWREx_DisablePVM4(void); -HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); - - -/* Low Power modes configuration functions ************************************/ -void HAL_PWREx_EnableLowPowerRunMode(void); -HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); -void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry); -void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); -void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); -void HAL_PWREx_EnterSHUTDOWNMode(void); - -void HAL_PWREx_PVD_PVM_IRQHandler(void); -#if defined(PWR_CR2_PVME1) -void HAL_PWREx_PVM1Callback(void); -#endif /* PWR_CR2_PVME1 */ -#if defined(PWR_CR2_PVME2) -void HAL_PWREx_PVM2Callback(void); -#endif /* PWR_CR2_PVME2 */ -void HAL_PWREx_PVM3Callback(void); -void HAL_PWREx_PVM4Callback(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L4xx_HAL_PWR_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h deleted file mode 100644 index 9c8014cde..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h +++ /dev/null @@ -1,4594 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rcc.h - * @author MCD Application Team - * @brief Header file of RCC HAL module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_RCC_H -#define __STM32L4xx_HAL_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RCC_Exported_Types RCC Exported Types - * @{ - */ - -/** - * @brief RCC PLL configuration structure definition - */ -typedef struct -{ - uint32_t PLLState; /*!< The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ - - uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. - This parameter must be a number between Min_Data = 1 and Max_Data = 8 on the other devices */ - - uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. - This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ - - uint32_t PLLP; /*!< PLLP: Division factor for SAI clock. - This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ - - uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks. - This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ - - uint32_t PLLR; /*!< PLLR: Division for the main system clock. - User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ. - This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ - -}RCC_PLLInitTypeDef; - -/** - * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition - */ -typedef struct -{ - uint32_t OscillatorType; /*!< The oscillators to be configured. - This parameter can be a value of @ref RCC_Oscillator_Type */ - - uint32_t HSEState; /*!< The new state of the HSE. - This parameter can be a value of @ref RCC_HSE_Config */ - - uint32_t LSEState; /*!< The new state of the LSE. - This parameter can be a value of @ref RCC_LSE_Config */ - - uint32_t HSIState; /*!< The new state of the HSI. - This parameter can be a value of @ref RCC_HSI_Config */ - - uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */ - - uint32_t LSIState; /*!< The new state of the LSI. - This parameter can be a value of @ref RCC_LSI_Config */ - - uint32_t MSIState; /*!< The new state of the MSI. - This parameter can be a value of @ref RCC_MSI_Config */ - - uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - - uint32_t MSIClockRange; /*!< The MSI frequency range. - This parameter can be a value of @ref RCC_MSI_Clock_Range */ - - uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices). - This parameter can be a value of @ref RCC_HSI48_Config */ - - RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ - -}RCC_OscInitTypeDef; - -/** - * @brief RCC System, AHB and APB busses clock configuration structure definition - */ -typedef struct -{ - uint32_t ClockType; /*!< The clock to be configured. - This parameter can be a value of @ref RCC_System_Clock_Type */ - - uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). - This parameter can be a value of @ref RCC_System_Clock_Source */ - - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_AHB_Clock_Source */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - - uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - -}RCC_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_Timeout_Value Timeout Values - * @{ - */ -#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT -/** - * @} - */ - -/** @defgroup RCC_Oscillator_Type Oscillator Type - * @{ - */ -#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ -#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ -#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ -#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ -#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ -#define RCC_OSCILLATORTYPE_MSI 0x00000010U /*!< MSI to configure */ -#if defined(RCC_HSI48_SUPPORT) -#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_HSE_Config HSE Config - * @{ - */ -#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ -#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ -#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ -/** - * @} - */ - -/** @defgroup RCC_LSE_Config LSE Config - * @{ - */ -#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ -#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ -#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ -/** - * @} - */ - -/** @defgroup RCC_HSI_Config HSI Config - * @{ - */ -#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ -#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ - -#if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) -#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ -#else -#define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */ -#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ -/** - * @} - */ - -/** @defgroup RCC_LSI_Config LSI Config - * @{ - */ -#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ -#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ -/** - * @} - */ - -/** @defgroup RCC_MSI_Config MSI Config - * @{ - */ -#define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ -#define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ - -#define RCC_MSICALIBRATION_DEFAULT 0U /*!< Default MSI calibration trimming value */ -/** - * @} - */ - -#if defined(RCC_HSI48_SUPPORT) -/** @defgroup RCC_HSI48_Config HSI48 Config - * @{ - */ -#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ -#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ -/** - * @} - */ -#else -/** @defgroup RCC_HSI48_Config HSI48 Config - * @{ - */ -#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ -/** - * @} - */ -#endif /* RCC_HSI48_SUPPORT */ - -/** @defgroup RCC_PLL_Config PLL Config - * @{ - */ -#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ -#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ -#define RCC_PLL_ON 0x00000002U /*!< PLL activation */ -/** - * @} - */ - -/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider - * @{ - */ -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) -#define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */ -#define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */ -#define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */ -#define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */ -#define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */ -#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ -#define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */ -#define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */ -#define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */ -#define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */ -#define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */ -#define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */ -#define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */ -#define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */ -#define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */ -#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ -#define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */ -#define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */ -#define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */ -#define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */ -#define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */ -#define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */ -#define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */ -#define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */ -#define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */ -#define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */ -#define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */ -#define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */ -#define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */ -#define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */ -#else -#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */ -#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */ -#endif /* RCC_PLLP_DIV_2_31_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider - * @{ - */ -#define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */ -#define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */ -#define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */ -#define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */ -/** - * @} - */ - -/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider - * @{ - */ -#define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */ -#define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */ -#define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */ -#define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */ -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source PLL Clock Source - * @{ - */ -#define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ -#define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ -#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ -#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Output PLL Clock Output - * @{ - */ -#if defined(RCC_PLLSAI2_SUPPORT) -#define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */ -#else -#define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */ -#endif /* RCC_PLLSAI2_SUPPORT */ -#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ -#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ -/** - * @} - */ - -/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output - * @{ - */ -#define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */ -#define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */ -#define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */ -/** - * @} - */ - -#if defined(RCC_PLLSAI2_SUPPORT) - -/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output - * @{ - */ -#define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */ -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) -#define RCC_PLLSAI2_DSICLK RCC_PLLSAI2CFGR_PLLSAI2QEN /*!< PLLDSICLK selection from PLLSAI2 */ -#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) -#define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */ -#else -#define RCC_PLLSAI2_LTDCCLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLLTDCCLK selection from PLLSAI2 */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ -/** - * @} - */ - -#endif /* RCC_PLLSAI2_SUPPORT */ - -/** @defgroup RCC_MSI_Clock_Range MSI Clock Range - * @{ - */ -#define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ -#define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ -#define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ -#define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ -#define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ -#define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ -#define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ -#define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ -#define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ -#define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ -#define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ -#define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Type System Clock Type - * @{ - */ -#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ -#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ -#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ -#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source System Clock Source - * @{ - */ -#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ -#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ -#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ -#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status - * @{ - */ -#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source AHB Clock Source - * @{ - */ -#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ -#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ -#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ -#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ -#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ -#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ -#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ -#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ -#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source - * @{ - */ -#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ -#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ -#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ -#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ -#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source RTC Clock Source - * @{ - */ -#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ -/** - * @} - */ - -/** @defgroup RCC_MCO_Index MCO Index - * @{ - */ -#define RCC_MCO1 0x00000000U -#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source - * @{ - */ -#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ -#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ -#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ -#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ -#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ -#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ -#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ -#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ -#if defined(RCC_HSI48_SUPPORT) -#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */ -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler - * @{ - */ -#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ -#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ -#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ -#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ -#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_Interrupt Interrupts - * @{ - */ -#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ -#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ -#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ -#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ -#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ -#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ -#define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ -#if defined(RCC_PLLSAI2_SUPPORT) -#define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ -#endif /* RCC_PLLSAI2_SUPPORT */ -#define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ -#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ -#if defined(RCC_HSI48_SUPPORT) -#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_Flag Flags - * Elements values convention: XXXYYYYYb - * - YYYYY : Flag position in the register - * - XXX : Register index - * - 001: CR register - * - 010: BDCR register - * - 011: CSR register - * - 100: CRRCR register - * @{ - */ -/* Flags in the CR register */ -#define RCC_FLAG_MSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos) /*!< MSI Ready flag */ -#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ -#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ -#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ -#define RCC_FLAG_PLLSAI1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos) /*!< PLLSAI1 Ready flag */ -#if defined(RCC_PLLSAI2_SUPPORT) -#define RCC_FLAG_PLLSAI2RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos) /*!< PLLSAI2 Ready flag */ -#endif /* RCC_PLLSAI2_SUPPORT */ - -/* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ -#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ - -/* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ -#define RCC_FLAG_RMVF ((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos) /*!< Remove reset flag */ -#define RCC_FLAG_FWRST ((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos) /*!< Firewall reset flag */ -#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ -#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ -#define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ -#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ -#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ -#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ -#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ - -#if defined(RCC_HSI48_SUPPORT) -/* Flags in the CRRCR register */ -#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ -#endif /* RCC_HSI48_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_LSEDrive_Config LSE Drive Config - * @{ - */ -#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ -#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ -#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ -#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ -/** - * @} - */ - -/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock - * @{ - */ -#define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ -#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TSC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GFXMMU */ - - -#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) - -#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) - -#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) - -#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) -#endif /* GFXMMU */ - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GPIOI */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* HASH */ - -#define __HAL_RCC_RNG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ - - -#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) - -#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) - -#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) -#endif /* GPIOI */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) -#endif /* HASH */ - -#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OSPIMEN) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN) -#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ - -/** - * @} - */ - -/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* FMC_BANK1 */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OCTOSPI2 */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) -#endif /* FMC_BANK1 */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN) -#endif /* OCTOSPI2 */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable - * @brief Enable or disable the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(LCD) -#define __HAL_RCC_LCD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* LCD */ - -#if defined(RCC_APB1ENR1_RTCAPBEN) -#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* RCC_APB1ENR1_RTCAPBEN */ - -#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(SPI2) -#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(USART3) -#define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* USB */ - -#define __HAL_RCC_PWR_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ - UNUSED(tmpreg); \ - } while(0) - - -#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) - -#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) - -#if defined(LCD) -#define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); -#endif /* LCD */ - -#if defined(RCC_APB1ENR1_RTCAPBEN) -#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); -#endif /* RCC_APB1ENR1_RTCAPBEN */ - -#if defined(SPI2) -#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) - -#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) - -#if defined(USART3) -#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); -#endif /* CRS */ - -#define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); -#endif /* USB */ - -#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) - -#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) - -#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) - -#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) - -#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable - * @brief Enable or disable the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ - -#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ - UNUSED(tmpreg); \ - } while(0) - - -#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* DSI */ - - -#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) - -#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) -#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ - -#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) - -#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) - -#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) - -#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the AHB1 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET) - -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != RESET) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET) - -#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET) - -#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != RESET) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != RESET) -#endif /* GFXMMU */ - - -#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET) - -#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == RESET) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET) - -#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET) - -#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == RESET) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == RESET) -#endif /* GFXMMU */ - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the AHB2 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET) - -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != RESET) - -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != RESET) -#endif /* GPIOI */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != RESET) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != RESET) -#endif /* HASH */ - -#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET) - - -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET) - -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET) - -#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == RESET) -#endif /* GPIOI */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == RESET) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == RESET) -#endif /* HASH */ - -#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET) - -/** - * @} - */ - -/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the AHB3 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET) -#endif /* FMC_BANK1 */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET) -#endif /* QUADSPI */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET) -#endif /* FMC_BANK1 */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET) -#endif /* QUADSPI */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the APB1 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET) - -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET) - -#if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET) -#endif /* LCD */ - -#if defined(RCC_APB1ENR1_RTCAPBEN) -#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET) -#endif /* RCC_APB1ENR1_RTCAPBEN */ - -#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET) - -#if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET) - -#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET) - -#if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != RESET) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != RESET) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET) -#endif /* USB */ - -#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET) - -#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET) - -#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET) - -#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET) - -#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET) - - -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET) - -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET) - -#if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET) -#endif /* LCD */ - -#if defined(RCC_APB1ENR1_RTCAPBEN) -#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET) -#endif /* RCC_APB1ENR1_RTCAPBEN */ - -#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET) - -#if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET) - -#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET) - -#if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == RESET) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == RESET) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET) -#endif /* USB */ - -#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET) - -#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET) - -#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET) - -#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET) - -#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the APB2 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET) - -#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET) - -#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET) -#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ - -#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET) - -#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET) - -#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET) - -#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != RESET) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) != RESET) -#endif /* DSI */ - - -#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET) - -#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET) -#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ - -#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET) - -#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET) - -#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET) - -#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == RESET) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN) == RESET) -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset - * @brief Force or release AHB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) - -#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) - -#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) - -#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) - -#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) -#endif /* GFXMMU */ - - -#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) - -#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) - -#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) - -#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) - -#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) -#endif /* GFXMMU */ - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset - * @brief Force or release AHB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU) - -#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) - -#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) - -#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) -#endif /* GPIOI */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) -#endif /* HASH */ - -#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) -#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) -#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ - - -#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) - -#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) - -#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) - -#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST) -#endif /* GPIOI */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) -#endif /* HASH */ - -#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OSPIMRST) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2RSTR_SDMMC1RST) -#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST) -#endif /* SDMMC1 && RCC_AHB2RSTR_SDMMC1RST */ - -/** - * @} - */ - -/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset - * @brief Force or release AHB3 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU) - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) -#endif /* FMC_BANK1 */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) -#endif /* OCTOSPI2 */ - -#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) -#endif /* FMC_BANK1 */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI2RST) -#endif /* OCTOSPI2 */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU) - -#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) - -#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) - -#if defined(LCD) -#define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) -#endif /* LCD */ - -#if defined(SPI2) -#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) - -#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) - -#if defined(USART3) -#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) -#endif /* USB */ - -#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) - -#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) - -#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) - -#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) - -#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) - - -#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U) - -#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) - -#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) - -#if defined(LCD) -#define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) -#endif /* LCD */ - -#if defined(SPI2) -#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) - -#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) - -#if defined(USART3) -#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) -#endif /* USB */ - -#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) - -#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) - -#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) - -#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) - -#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) - -#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) - -#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) -#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) -#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ - -#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) - -#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) - -#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) - -#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) -#endif /* DSI */ - - -#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) - -#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) - -#if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) -#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) -#endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ - -#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) - -#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) - -#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) - -#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIRST) -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) - -#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) - -#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) - -#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) - -#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) -#endif /* GFXMMU */ - - -#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) - -#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) - -#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) - -#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) - -#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) -#endif /* GFXMMU */ - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) - -#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) - -#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) -#endif /* GPIOI */ - -#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) - -#if defined(SRAM3) -#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) -#endif /* SRAM3 */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) -#endif /* HASH */ - -#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) -#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ - - -#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) - -#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) - -#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) -#endif /* GPIOI */ - -#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) - -#if defined(SRAM3) -#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) -#endif /* SRAM3 */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) -#endif /* HASH */ - -#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) -#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ - -/** - * @} - */ - -/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) -#endif /* OCTOSPI2 */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) -#endif /* FMC_BANK1 */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) -#endif /* OCTOSPI2 */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) -#endif /* FMC_BANK1 */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) - -#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) - -#if defined(LCD) -#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) -#endif /* LCD */ - -#if defined(RCC_APB1SMENR1_RTCAPBSMEN) -#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) -#endif /* RCC_APB1SMENR1_RTCAPBSMEN */ - -#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) - -#if defined(SPI2) -#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) - -#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) - -#if defined(USART3) -#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) -#endif /* USB */ - -#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) - -#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) - -#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) - -#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) - -#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) - - -#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) - -#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) - -#if defined(LCD) -#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) -#endif /* LCD */ - -#if defined(RCC_APB1SMENR1_RTCAPBSMEN) -#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) -#endif /* RCC_APB1SMENR1_RTCAPBSMEN */ - -#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) - -#if defined(SPI2) -#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) - -#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) - -#if defined(USART3) -#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) -#endif /* USB */ - -#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) - -#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) - -#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) - -#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) - -#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) - -#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) -#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ - -#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) - -#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) - -#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) - -#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) -#endif /* DSI */ - - -#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) - -#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) -#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ - -#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) - -#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) - -#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) - -#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status - * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET) - -#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != RESET) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET) - -#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET) - -#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET) - -#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != RESET) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) != RESET) -#endif /* GFXMMU */ - - -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET) - -#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET) - -#if defined(DMAMUX1) -#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == RESET) -#endif /* DMAMUX1 */ - -#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET) - -#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET) - -#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET) - -#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == RESET) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) == RESET) -#endif /* GFXMMU */ - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status - * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET) - -#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET) - -#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != RESET) -#endif /* GPIOI */ - -#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET) - -#if defined(SRAM3) -#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) != RESET) -#endif /* SRAM3 */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != RESET) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != RESET) -#endif /* HASH */ - -#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) != RESET) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) != RESET) -#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ - - -#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET) - -#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET) - -#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET) - -#if defined(GPIOD) -#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET) -#endif /* GPIOD */ - -#if defined(GPIOE) -#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET) -#endif /* GPIOE */ - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET) -#endif /* GPIOF */ - -#if defined(GPIOG) -#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET) -#endif /* GPIOG */ - -#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == RESET) -#endif /* GPIOI */ - -#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET) - -#if defined(SRAM3) -#define __HAL_RCC_SRAM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM3SMEN) == RESET) -#endif /* SRAM3 */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET) -#endif /* USB_OTG_FS */ - -#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET) - -#if defined(DCMI) -#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == RESET) -#endif /* DCMI */ - -#if defined(AES) -#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == RESET) -#endif /* HASH */ - -#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET) - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OSPIMSMEN) == RESET) -#endif /* OCTOSPIM */ - -#if defined(SDMMC1) && defined(RCC_AHB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SDMMC1SMEN) == RESET) -#endif /* SDMMC1 && RCC_AHB2SMENR_SDMMC1SMEN */ - -/** - * @} - */ - -/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status - * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) != RESET) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) != RESET) -#endif /* OCTOSPI2 */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET) -#endif /* FMC_BANK1 */ - - -#if defined(QUADSPI) -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET) -#endif /* QUADSPI */ - -#if defined(OCTOSPI1) -#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI1SMEN) == RESET) -#endif /* OCTOSPI1 */ - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_OSPI2SMEN) == RESET) -#endif /* OCTOSPI2 */ - -#if defined(FMC_BANK1) -#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET) -#endif /* FMC_BANK1 */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status - * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET) - -#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET) - -#if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET) -#endif /* LCD */ - -#if defined(RCC_APB1SMENR1_RTCAPBSMEN) -#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET) -#endif /* RCC_APB1SMENR1_RTCAPBSMEN */ - -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET) - -#if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET) - -#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET) - -#if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != RESET) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != RESET) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET) -#endif /* USB */ - -#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET) - -#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET) - -#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET) - -#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET) - -#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET) - - -#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET) - -#if defined(TIM3) -#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET) -#endif /* TIM3 */ - -#if defined(TIM4) -#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET) -#endif /* TIM4 */ - -#if defined(TIM5) -#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET) -#endif /* TIM5 */ - -#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET) - -#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET) - -#if defined(LCD) -#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET) -#endif /* LCD */ - -#if defined(RCC_APB1SMENR1_RTCAPBSMEN) -#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET) -#endif /* RCC_APB1SMENR1_RTCAPBSMEN */ - -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET) - -#if defined(SPI2) -#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET) -#endif /* SPI2 */ - -#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET) - -#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET) - -#if defined(USART3) -#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET) -#endif /* USART3 */ - -#if defined(UART4) -#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET) -#endif /* UART4 */ - -#if defined(UART5) -#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET) -#endif /* UART5 */ - -#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET) - -#if defined(I2C2) -#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET) -#endif /* I2C2 */ - -#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET) - -#if defined(I2C4) -#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == RESET) -#endif /* I2C4 */ - -#if defined(CRS) -#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET) -#endif /* CRS */ - -#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET) - -#if defined(CAN2) -#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == RESET) -#endif /* CAN2 */ - -#if defined(USB) -#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET) -#endif /* USB */ - -#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET) - -#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET) - -#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET) - -#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET) - -#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET) - -#if defined(SWPMI1) -#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET) -#endif /* SWPMI1 */ - -#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status - * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET) - -#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET) -#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ - -#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET) - -#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET) - -#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET) - -#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) != RESET) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) != RESET) -#endif /* DSI */ - - -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET) - -#if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET) -#endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ - -#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET) - -#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET) - -#if defined(TIM8) -#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET) -#endif /* TIM8 */ - -#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET) - -#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET) - -#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET) - -#if defined(TIM17) -#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET) -#endif /* TIM17 */ - -#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET) -#endif /* SAI2 */ - -#if defined(DFSDM1_Filter0) -#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET) -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) == RESET) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSISMEN) == RESET) -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset - * @{ - */ - -/** @brief Macros to force or release the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - * @retval None - */ -#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) - -#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) - -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration - * @{ - */ - -/** @brief Macros to enable or disable the RTC clock. - * @note As the RTC is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * HAL_PWR_EnableBkUpAccess() function before to configure the RTC - * (to be done once after reset). - * @note These macros must be used after the RTC clock source was selected. - * @retval None - */ -#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) - -#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) - -/** - * @} - */ - -/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - * @retval None - */ -#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) - -#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) - -/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value - * (default is RCC_HSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices). - * @retval None - */ -#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ - MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) - -/** - * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) - * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. - * @note The enable of this function has not effect on the HSION bit. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS) - -#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS) - -/** - * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) - * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. - * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication - * speed because of the HSI startup time. - * @note The enable of this function has not effect on the HSION bit. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) - -#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) - -/** - * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). - * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after - * startup from Reset, wakeup from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * @note MSI can not be stopped if it is used as system clock source. - * In this case, you have to select another source of the system - * clock then stop the MSI. - * @note After enabling the MSI, the application software should wait on - * MSIRDY flag to be set indicating that MSI clock is stable and can - * be used as system clock source. - * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator - * clock cycles. - * @retval None - */ -#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) - -#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) - -/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal MSI RC. - * Refer to the Application Note AN3300 for more details on how to - * calibrate the MSI. - * @param __MSICALIBRATIONVALUE__ specifies the calibration trimming value - * (default is RCC_MSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 255. - * @retval None - */ -#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ - MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (__MSICALIBRATIONVALUE__) << RCC_ICSCR_MSITRIM_Pos) - -/** - * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode - * @note After restart from Reset , the MSI clock is around 4 MHz. - * After stop the startup clock can be MSI (at any of its possible - * frequencies, the one that was used before entering stop mode) or HSI. - * After Standby its frequency can be selected between 4 possible values - * (1, 2, 4 or 8 MHz). - * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready - * (MSIRDY=1). - * @note The MSI clock range after reset can be modified on the fly. - * @param __MSIRANGEVALUE__ specifies the MSI clock range. - * This parameter must be one of the following values: - * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz - * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz - * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz - * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz - * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz - * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) - * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz - * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz - * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz - * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz - * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz - * @retval None - */ -#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ - do { \ - SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ - MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ - } while(0) - -/** - * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode - * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). - * @param __MSIRANGEVALUE__ specifies the MSI clock range. - * This parameter must be one of the following values: - * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz - * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) - * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz - * @retval None - */ -#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \ - MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) - -/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode - * @retval MSI clock range. - * This parameter must be one of the following values: - * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz - * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz - * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz - * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz - * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz - * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset) - * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz - * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz - * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz - * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz - * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz - */ -#define __HAL_RCC_GET_MSI_RANGE() \ - ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \ - READ_BIT(RCC->CR, RCC_CR_MSIRANGE) : \ - READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4U) - -/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - * @retval None - */ -#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) - -#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) - -/** - * @brief Macro to configure the External High Speed oscillator (HSE). - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param __STATE__ specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. - * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. - * @retval None - */ -#define __HAL_RCC_HSE_CONFIG(__STATE__) \ - do { \ - if((__STATE__) == RCC_HSE_ON) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else if((__STATE__) == RCC_HSE_BYPASS) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - } while(0) - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this macro. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param __STATE__ specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. - * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. - * @retval None - */ -#define __HAL_RCC_LSE_CONFIG(__STATE__) \ - do { \ - if((__STATE__) == RCC_LSE_ON) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else if((__STATE__) == RCC_LSE_BYPASS) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - } while(0) - -#if defined(RCC_HSI48_SUPPORT) - -/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). - * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. - * @note After enabling the HSI48, the application software should wait on HSI48RDY - * flag to be set indicating that HSI48 clock is stable. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) - -#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) - -#endif /* RCC_HSI48_SUPPORT */ - -/** @brief Macros to configure the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it cannot be changed unless the - * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by - * a Power On Reset (POR). - * - * @param __RTC_CLKSOURCE__ specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected - * - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - * @retval None - */ -#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ - MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) - - -/** @brief Macro to get the RTC clock source. - * @retval The returned value can be one of the following: - * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected - */ -#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) - -/** @brief Macros to enable or disable the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - * @retval None - */ -#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) - -#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) - -/** @brief Macro to configure the PLL clock source. - * @note This function must be used only when the main PLL is disabled. - * @param __PLLSOURCE__ specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry - * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). - * @retval None - * - */ -#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) - -/** @brief Macro to configure the PLL source division factor M. - * @note This function must be used only when the main PLL is disabled. - * @param __PLLM__ specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. - * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency - * of 16 MHz to limit PLL jitter. - * @retval None - * - */ -#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U) - -/** - * @brief Macro to configure the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param __PLLSOURCE__ specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry - * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). - * - * @param __PLLM__ specifies the division factor for PLL VCO input clock. - * This parameter must be a number between Min_Data = 1 and Max_Data = 16 on STM32L4Rx/STM32L4Sx devices. - * This parameter must be a number between Min_Data = 1 and Max_Data = 8 on other devices. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency - * of 16 MHz to limit PLL jitter. - * - * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. - * This parameter must be a number between 8 and 86. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 64 and 344 MHz. - * - * @param __PLLP__ specifies the division factor for SAI clock. - * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x - * else (2 to 31). - * - * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks. - * This parameter must be in the range (2, 4, 6 or 8). - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - * @param __PLLR__ specifies the division factor for the main system clock. - * @note You have to set the PLLR parameter correctly to not exceed 80MHZ. - * This parameter must be in the range (2, 4, 6 or 8). - * @retval None - */ -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - -#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ - (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ - (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ - ((uint32_t)(__PLLP__) << 27U)) -#else - -#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ - (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ - (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ - (__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) - -#endif /* RCC_PLLP_DIV_2_31_SUPPORT */ - -/** @brief Macro to get the oscillator used as PLL clock source. - * @retval The oscillator used as PLL clock source. The returned value can be one - * of the following: - * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. - */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)) - -/** - * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) - * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime - * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot - * be stopped if used as System Clock. - * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. - * This parameter can be one or a combination of the following values: - * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), - * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). - * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) - * @retval None - */ -#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) - -#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) - -/** - * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) - * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. - * This parameter can be one of the following values: - * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), - * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). - * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) - * @retval SET / RESET - */ -#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) - -/** - * @brief Macro to configure the system clock source. - * @param __SYSCLKSOURCE__ specifies the system clock source. - * This parameter can be one of the following values: - * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. - * @retval None - */ -#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) - -/** @brief Macro to get the clock source used as system clock. - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)) - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. - * This parameter can be one of the following values: - * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. - * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. - * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. - * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. - * @retval None - */ -#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__)) - -/** - * @brief Macro to configure the wake up from stop clock. - * @param __STOPWUCLK__ specifies the clock source used after wake up from stop. - * This parameter can be one of the following values: - * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source - * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source - * @retval None - */ -#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) - - -/** @brief Macro to configure the MCO clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled - * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee - * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source - @if STM32L443xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 - @endif - @if STM32L4A6xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 - @endif - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 - * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 - * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 - * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 - * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 - */ -#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) - -/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management - * @brief macros to manage the specified RCC Flags and interrupts. - * @{ - */ - -/** @brief Enable RCC interrupt(s). - * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_MSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt - * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 - * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt - @if STM32L443xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - @if STM32L4A6xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - * @retval None - */ -#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) - -/** @brief Disable RCC interrupt(s). - * @param __INTERRUPT__ specifies the RCC interrupt source(s) to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_MSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt - * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 - * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt - @if STM32L443xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - @if STM32L4A6xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - * @retval None - */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) - -/** @brief Clear the RCC's interrupt pending bits. - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_MSIRDY MSI ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt - * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 - * @arg @ref RCC_IT_CSS HSE Clock security system interrupt - * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt - @if STM32L443xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - @if STM32L4A6xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - * @retval None - */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) - -/** @brief Check whether the RCC interrupt has occurred or not. - * @param __INTERRUPT__ specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_MSIRDY MSI ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt - * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 - * @arg @ref RCC_IT_CSS HSE Clock security system interrupt - * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt - @if STM32L443xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - @if STM32L4A6xx - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 - @endif - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__)) - -/** @brief Set RMVF bit to clear the reset flags. - * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, - * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. - * @retval None - */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF) - -/** @brief Check whether the selected RCC flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready - * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready - * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready - * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready - * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready - * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2 - @if STM32L443xx - * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 - @endif - @if STM32L4A6xx - * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 - @endif - * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready - * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection - * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready - * @arg @ref RCC_FLAG_BORRST BOR reset - * @arg @ref RCC_FLAG_OBLRST OBLRST reset - * @arg @ref RCC_FLAG_PINRST Pin reset - * @arg @ref RCC_FLAG_FWRST FIREWALL reset - * @arg @ref RCC_FLAG_RMVF Remove reset Flag - * @arg @ref RCC_FLAG_SFTRST Software reset - * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset - * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset - * @arg @ref RCC_FLAG_LPWRRST Low Power reset - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#if defined(RCC_HSI48_SUPPORT) -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ - ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ - ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ - ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ - (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) -#else -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ - ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ - ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ - (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) -#endif /* RCC_HSI48_SUPPORT */ - -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Constants RCC Private Constants - * @{ - */ -/* Defines used for Flags */ -#define CR_REG_INDEX 1U -#define BDCR_REG_INDEX 2U -#define CSR_REG_INDEX 3U -#if defined(RCC_HSI48_SUPPORT) -#define CRRCR_REG_INDEX 4U -#endif /* RCC_HSI48_SUPPORT */ - -#define RCC_FLAG_MASK 0x1FU -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCC_Private_Macros - * @{ - */ - -#if defined(RCC_HSI48_SUPPORT) -#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) -#else -#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) -#endif /* RCC_HSI48_SUPPORT */ - -#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ - ((__HSE__) == RCC_HSE_BYPASS)) - -#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ - ((__LSE__) == RCC_LSE_BYPASS)) - -#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) - -#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) - -#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) - -#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) - -#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) - -#if defined(RCC_HSI48_SUPPORT) -#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) -#endif /* RCC_HSI48_SUPPORT */ - -#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ - ((__PLL__) == RCC_PLL_ON)) - -#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ - ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ - ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ - ((__SOURCE__) == RCC_PLLSOURCE_HSE)) - -#if defined(RCC_PLLM_DIV_1_16_SUPPORT) -#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) -#else -#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) -#endif /*RCC_PLLM_DIV_1_16_SUPPORT */ - -#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) - -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) -#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) -#else -#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) -#endif /*RCC_PLLP_DIV_2_31_SUPPORT */ - -#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ - ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) - -#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ - ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) - -#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ - (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \ - (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \ - (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) - -#if defined(RCC_PLLSAI2_SUPPORT) -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) -#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ - (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \ - (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) -#elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ - (((__VALUE__) & RCC_PLLSAI2_DSICLK) == RCC_PLLSAI2_DSICLK) || \ - (((__VALUE__) & RCC_PLLSAI2_LTDCCLK) == RCC_PLLSAI2_LTDCCLK)) && \ - (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_DSICLK|RCC_PLLSAI2_LTDCCLK)) == 0U)) -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ -#endif /* RCC_PLLSAI2_SUPPORT */ - -#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ - ((__RANGE__) == RCC_MSIRANGE_1) || \ - ((__RANGE__) == RCC_MSIRANGE_2) || \ - ((__RANGE__) == RCC_MSIRANGE_3) || \ - ((__RANGE__) == RCC_MSIRANGE_4) || \ - ((__RANGE__) == RCC_MSIRANGE_5) || \ - ((__RANGE__) == RCC_MSIRANGE_6) || \ - ((__RANGE__) == RCC_MSIRANGE_7) || \ - ((__RANGE__) == RCC_MSIRANGE_8) || \ - ((__RANGE__) == RCC_MSIRANGE_9) || \ - ((__RANGE__) == RCC_MSIRANGE_10) || \ - ((__RANGE__) == RCC_MSIRANGE_11)) - -#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ - ((__RANGE__) == RCC_MSIRANGE_5) || \ - ((__RANGE__) == RCC_MSIRANGE_6) || \ - ((__RANGE__) == RCC_MSIRANGE_7)) - -#define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U)) - -#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) - -#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ - ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ - ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ - ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ - ((__HCLK__) == RCC_SYSCLK_DIV512)) - -#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ - ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ - ((__PCLK__) == RCC_HCLK_DIV16)) - -#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) - -#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) - -#if defined(RCC_HSI48_SUPPORT) -#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) -#else -#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) -#endif /* RCC_HSI48_SUPPORT */ - -#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ - ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ - ((__DIV__) == RCC_MCODIV_16)) - -#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ - ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ - ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ - ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) - -#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ - ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) -/** - * @} - */ - -/* Include RCC HAL Extended module */ -#include "stm32l4xx_hal_rcc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCC_Exported_Functions - * @{ - */ - - -/** @addtogroup RCC_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); - -/** - * @} - */ - -/** @addtogroup RCC_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); -void HAL_RCC_EnableCSS(void); -uint32_t HAL_RCC_GetSysClockFreq(void); -uint32_t HAL_RCC_GetHCLKFreq(void); -uint32_t HAL_RCC_GetPCLK1Freq(void); -uint32_t HAL_RCC_GetPCLK2Freq(void); -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); -/* CSS NMI IRQ handler */ -void HAL_RCC_NMI_IRQHandler(void); -/* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CSSCallback(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_RCC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h deleted file mode 100644 index b0000a7ab..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h +++ /dev/null @@ -1,3018 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rcc_ex.h - * @author MCD Application Team - * @brief Header file of RCC HAL Extended module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_RCC_EX_H -#define __STM32L4xx_HAL_RCC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Types RCCEx Exported Types - * @{ - */ - -/** - * @brief PLLSAI1 Clock structure definition - */ -typedef struct -{ - - uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ -#else - uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ -#endif - - uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. - This parameter must be a number between 8 and 86 or 127 depending on devices. */ - - uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock. - This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ - - uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock. - This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ - - uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock. - This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ - - uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. - This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ -}RCC_PLLSAI1InitTypeDef; - -#if defined(RCC_PLLSAI2_SUPPORT) - -/** - * @brief PLLSAI2 Clock structure definition - */ -typedef struct -{ - - uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ -#else - uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ -#endif - - uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock. - This parameter must be a number between 8 and 86 or 127 depending on devices. */ - - uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock. - This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ - -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) - uint32_t PLLSAI2Q; /*!< PLLSAI2Q: specifies the division factor for DSI clock. - This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ -#endif - - uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock. - This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ - - uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled. - This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */ -}RCC_PLLSAI2InitTypeDef; - -#endif /* RCC_PLLSAI2_SUPPORT */ - -/** - * @brief RCC extended clocks structure definition - */ -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. - This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */ - -#if defined(RCC_PLLSAI2_SUPPORT) - - RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters. - This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */ - -#endif /* RCC_PLLSAI2_SUPPORT */ - - uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. - This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ - - uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. - This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ - -#if defined(USART3) - - uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. - This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ - -#endif /* USART3 */ - -#if defined(UART4) - - uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. - This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ - -#endif /* UART4 */ - -#if defined(UART5) - - uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. - This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ - -#endif /* UART5 */ - - uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. - This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. - This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ - -#if defined(I2C2) - - uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. - This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ - -#endif /* I2C2 */ - - uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. - This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ - -#if defined(I2C4) - - uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. - This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ - -#endif /* I2C4 */ - - uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. - This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ - - uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. - This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ - - uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. - This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ - -#if defined(SAI2) - - uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. - This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ - -#endif /* SAI2 */ - -#if defined(USB_OTG_FS) || defined(USB) - - uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG). - This parameter can be a value of @ref RCCEx_USB_Clock_Source */ - -#endif /* USB_OTG_FS || USB */ - -#if defined(SDMMC1) - - uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG). - This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ - -#endif /* SDMMC1 */ - - uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1). - This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ - - uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. - This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ - -#if defined(SWPMI1) - - uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source. - This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */ - -#endif /* SWPMI1 */ - -#if defined(DFSDM1_Filter0) - - uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source. - This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */ - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source. - This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */ - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) - - uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source. - This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ - -#endif /* LTDC */ - -#if defined(DSI) - - uint32_t DsiClockSelection; /*!< Specifies DSI clock source. - This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ - -#endif /* DSI */ - -#if defined(OCTOSPI1) || defined(OCTOSPI2) - - uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. - This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ - -#endif - - uint32_t RTCClockSelection; /*!< Specifies RTC clock source. - This parameter can be a value of @ref RCC_RTC_Clock_Source */ -}RCC_PeriphCLKInitTypeDef; - -#if defined(CRS) - -/** - * @brief RCC_CRS Init structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. - This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ - - uint32_t Source; /*!< Specifies the SYNC signal source. - This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ - - uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. - This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ - - uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. - It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) - This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ - - uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. - This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ - - uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. - This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ - -}RCC_CRSInitTypeDef; - -/** - * @brief RCC_CRS Synchronization structure definition - */ -typedef struct -{ - uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. - This parameter must be a number between 0 and 0xFFFF */ - - uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. - This parameter must be a number between 0 and 0x3F */ - - uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter - value latched in the time of the last SYNC event. - This parameter must be a number between 0 and 0xFFFF */ - - uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the - frequency error counter latched in the time of the last SYNC event. - It shows whether the actual frequency is below or above the target. - This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ - -}RCC_CRSSynchroInfoTypeDef; - -#endif /* CRS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants - * @{ - */ - -/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source - * @{ - */ -#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ -#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ -/** - * @} - */ - -/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection - * @{ - */ -#define RCC_PERIPHCLK_USART1 0x00000001U -#define RCC_PERIPHCLK_USART2 0x00000002U -#if defined(USART3) -#define RCC_PERIPHCLK_USART3 0x00000004U -#endif -#if defined(UART4) -#define RCC_PERIPHCLK_UART4 0x00000008U -#endif -#if defined(UART5) -#define RCC_PERIPHCLK_UART5 0x00000010U -#endif -#define RCC_PERIPHCLK_LPUART1 0x00000020U -#define RCC_PERIPHCLK_I2C1 0x00000040U -#if defined(I2C2) -#define RCC_PERIPHCLK_I2C2 0x00000080U -#endif -#define RCC_PERIPHCLK_I2C3 0x00000100U -#define RCC_PERIPHCLK_LPTIM1 0x00000200U -#define RCC_PERIPHCLK_LPTIM2 0x00000400U -#define RCC_PERIPHCLK_SAI1 0x00000800U -#if defined(SAI2) -#define RCC_PERIPHCLK_SAI2 0x00001000U -#endif -#if defined(USB_OTG_FS) || defined(USB) -#define RCC_PERIPHCLK_USB 0x00002000U -#endif -#define RCC_PERIPHCLK_ADC 0x00004000U -#if defined(SWPMI1) -#define RCC_PERIPHCLK_SWPMI1 0x00008000U -#endif -#if defined(DFSDM1_Filter0) -#define RCC_PERIPHCLK_DFSDM1 0x00010000U -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#endif -#define RCC_PERIPHCLK_RTC 0x00020000U -#define RCC_PERIPHCLK_RNG 0x00040000U -#if defined(SDMMC1) -#define RCC_PERIPHCLK_SDMMC1 0x00080000U -#endif -#if defined(I2C4) -#define RCC_PERIPHCLK_I2C4 0x00100000U -#endif -#if defined(LTDC) -#define RCC_PERIPHCLK_LTDC 0x00400000U -#endif -#if defined(DSI) -#define RCC_PERIPHCLK_DSI 0x00800000U -#endif -#if defined(OCTOSPI1) || defined(OCTOSPI2) -#define RCC_PERIPHCLK_OSPI 0x01000000U -#endif -/** - * @} - */ - - -/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source - * @{ - */ -#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U -#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 -#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 -#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) -/** - * @} - */ - -/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source - * @{ - */ -#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U -#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 -#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 -#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) -/** - * @} - */ - -#if defined(USART3) -/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source - * @{ - */ -#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U -#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 -#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 -#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) -/** - * @} - */ -#endif /* USART3 */ - -#if defined(UART4) -/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source - * @{ - */ -#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U -#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 -#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 -#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) -/** - * @} - */ -#endif /* UART4 */ - -#if defined(UART5) -/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source - * @{ - */ -#define RCC_UART5CLKSOURCE_PCLK1 0x00000000U -#define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 -#define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 -#define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) -/** - * @} - */ -#endif /* UART5 */ - -/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source - * @{ - */ -#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U -#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 -#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 -#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) -/** - * @} - */ - -/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source - * @{ - */ -#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U -#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 -#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 -/** - * @} - */ - -#if defined(I2C2) -/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source - * @{ - */ -#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U -#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 -#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 -/** - * @} - */ -#endif /* I2C2 */ - -/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source - * @{ - */ -#define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U -#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 -#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 -/** - * @} - */ - -#if defined(I2C4) -/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source - * @{ - */ -#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U -#define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0 -#define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1 -/** - * @} - */ -#endif /* I2C4 */ - -/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source - * @{ - */ -#define RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U -#if defined(RCC_PLLSAI2_SUPPORT) -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0 -#else -#define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0 -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#endif /* RCC_PLLSAI2_SUPPORT */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR2_SAI1SEL_1 -#define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) -#define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 -#else -#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1 -#define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -/** - * @} - */ - -#if defined(SAI2) -/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source - * @{ - */ -#define RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0 -#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1 -#define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) -#define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 -#else -#define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0 -#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1 -#define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -/** - * @} - */ -#endif /* SAI2 */ - -/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source - * @{ - */ -#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U -#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 -#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 -#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL -/** - * @} - */ - -/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source - * @{ - */ -#define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U -#define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 -#define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 -#define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL -/** - * @} - */ - -#if defined(SDMMC1) -/** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source - * @{ - */ -#if defined(RCC_HSI48_SUPPORT) -#define RCC_SDMMC1CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock selected as SDMMC1 clock */ -#else -#define RCC_SDMMC1CLKSOURCE_NONE 0x00000000U /*!< No clock selected as SDMMC1 clock */ -#endif /* RCC_HSI48_SUPPORT */ -#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 "Q" clock selected as SDMMC1 clock */ -#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL "Q" clock selected as SDMMC1 clock */ -#define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /*!< MSI clock selected as SDMMC1 clock */ -#if defined(RCC_CCIPR2_SDMMCSEL) -#define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLL "P" clock selected as SDMMC1 kernel clock */ -#endif /* RCC_CCIPR2_SDMMCSEL */ -/** - * @} - */ -#endif /* SDMMC1 */ - -/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source - * @{ - */ -#if defined(RCC_HSI48_SUPPORT) -#define RCC_RNGCLKSOURCE_HSI48 0x00000000U -#else -#define RCC_RNGCLKSOURCE_NONE 0x00000000U -#endif /* RCC_HSI48_SUPPORT */ -#define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 -#define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 -#define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL -/** - * @} - */ - -#if defined(USB_OTG_FS) || defined(USB) -/** @defgroup RCCEx_USB_Clock_Source USB Clock Source - * @{ - */ -#if defined(RCC_HSI48_SUPPORT) -#define RCC_USBCLKSOURCE_HSI48 0x00000000U -#else -#define RCC_USBCLKSOURCE_NONE 0x00000000U -#endif /* RCC_HSI48_SUPPORT */ -#define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 -#define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 -#define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL -/** - * @} - */ -#endif /* USB_OTG_FS || USB */ - -/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source - * @{ - */ -#define RCC_ADCCLKSOURCE_NONE 0x00000000U -#define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) -#define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ -#define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL -/** - * @} - */ - -#if defined(SWPMI1) -/** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source - * @{ - */ -#define RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U -#define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL -/** - * @} - */ -#endif /* SWPMI1 */ - -#if defined(DFSDM1_Filter0) -/** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source - * @{ - */ -#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL -#else -#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -/** - * @} - */ - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source - * @{ - */ -#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0x00000000U -#define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 -#define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 -/** - * @} - */ -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) -/** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source - * @{ - */ -#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 0x00000000U -#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 -#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 -#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR -/** - * @} - */ -#endif /* LTDC */ - -#if defined(DSI) -/** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source - * @{ - */ -#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U -#define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL -/** - * @} - */ -#endif /* DSI */ - -#if defined(OCTOSPI1) || defined(OCTOSPI2) -/** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source - * @{ - */ -#define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U -#define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 -#define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 -/** - * @} - */ -#endif /* OCTOSPI1 || OCTOSPI2 */ - -/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line - * @{ - */ -#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ -/** - * @} - */ - -#if defined(CRS) - -/** @defgroup RCCEx_CRS_Status RCCEx CRS Status - * @{ - */ -#define RCC_CRS_NONE 0x00000000U -#define RCC_CRS_TIMEOUT 0x00000001U -#define RCC_CRS_SYNCOK 0x00000002U -#define RCC_CRS_SYNCWARN 0x00000004U -#define RCC_CRS_SYNCERR 0x00000008U -#define RCC_CRS_SYNCMISS 0x00000010U -#define RCC_CRS_TRIMOVF 0x00000020U -/** - * @} - */ - -/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource - * @{ - */ -#define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ -#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ -#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider - * @{ - */ -#define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ -#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ -#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ -#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ -#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ -#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ -#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ -#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity - * @{ - */ -#define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ -#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault - * @{ - */ -#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds - to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault - * @{ - */ -#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault - * @{ - */ -#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval. - The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value - corresponds to a higher output frequency */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection - * @{ - */ -#define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ -#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ -/** - * @} - */ - -/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources - * @{ - */ -#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ -#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ -#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ -#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ -#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ -#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ -#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ - -/** - * @} - */ - -/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags - * @{ - */ -#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ -#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ -#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ -#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ -#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ -#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ -#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros - * @{ - */ - - -/** - * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. - * - * @note This function must be used only when the PLLSAI1 is disabled. - * @note PLLSAI1 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - @if STM32L4S9xx - * @param __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock. - * This parameter must be a number between Min_Data = 1 and Max_Data = 16. - * - @endif - * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. - * This parameter must be a number between 8 and 86. - * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO - * output frequency is between 64 and 344 MHz. - * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N - * - * @param __PLLSAI1P__ specifies the division factor for SAI clock. - * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx - * else (2 to 31). - * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P - * - * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. - * This parameter must be in the range (2, 4, 6 or 8). - * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q - * - * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock. - * This parameter must be in the range (2, 4, 6 or 8). - * ADC clock frequency = f(PLLSAI1) / PLLSAI1R - * - * @retval None - */ -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - -#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ - ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | \ - (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) - -#else - -#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ - (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ - (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)) - -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ - -#else - -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - -#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ - ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) - -#else - -#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ - (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)) - -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ - -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - -/** - * @brief Macro to configure the PLLSAI1 clock multiplication factor N. - * - * @note This function must be used only when the PLLSAI1 is disabled. - * @note PLLSAI1 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock. - * This parameter must be a number between 8 and 86. - * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO - * output frequency is between 64 and 344 MHz. - * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N - * - * @retval None - */ -#define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) - -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - -/** @brief Macro to configure the PLLSAI1 input clock division factor M. - * - * @note This function must be used only when the PLLSAI1 is disabled. - * @note PLLSAI1 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI1M__ specifies the division factor for PLLSAI1 clock. - * This parameter must be a number between Min_Data = 1 and Max_Data = 16. - * - * @retval None - */ - -#define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) - -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - -/** @brief Macro to configure the PLLSAI1 clock division factor P. - * - * @note This function must be used only when the PLLSAI1 is disabled. - * @note PLLSAI1 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI1P__ specifies the division factor for SAI clock. - * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx - * else (2 to 31). - * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P - * - * @retval None - */ -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - -#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) - -#else - -#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) - -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ - -/** @brief Macro to configure the PLLSAI1 clock division factor Q. - * - * @note This function must be used only when the PLLSAI1 is disabled. - * @note PLLSAI1 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock. - * This parameter must be in the range (2, 4, 6 or 8). - * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q - * - * @retval None - */ -#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) - -/** @brief Macro to configure the PLLSAI1 clock division factor R. - * - * @note This function must be used only when the PLLSAI1 is disabled. - * @note PLLSAI1 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI1R__ specifies the division factor for ADC clock. - * This parameter must be in the range (2, 4, 6 or 8) - * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R - * - * @retval None - */ -#define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) - -/** - * @brief Macros to enable or disable the PLLSAI1. - * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. - * @retval None - */ - -#define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON) - -#define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON) - -/** - * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). - * @note Enabling and disabling those clocks can be done without the need to stop the PLL. - * This is mainly used to save Power. - * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. - * This parameter can be one or a combination of the following values: - * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), - * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). - * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. - * @retval None - */ - -#define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) - -#define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) - -/** - * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). - * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output. - * This parameter can be one of the following values: - * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz), - * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). - * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral. - * @retval SET / RESET - */ -#define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) - -#if defined(RCC_PLLSAI2_SUPPORT) - -/** - * @brief Macro to configure the PLLSAI2 clock multiplication and division factors. - * - * @note This function must be used only when the PLLSAI2 is disabled. - * @note PLLSAI2 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - @if STM32L4S9xx - * @param __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock. - * This parameter must be a number between Min_Data = 1 and Max_Data = 16. - * - @endif - * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. - * This parameter must be a number between 8 and 86. - * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO - * output frequency is between 64 and 344 MHz. - * - * @param __PLLSAI2P__ specifies the division factor for SAI clock. - * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx - * else (2 to 31). - * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P - * - @if STM32L4S9xx - * @param __PLLSAI2Q__ specifies the division factor for DSI clock. - * This parameter must be in the range (2, 4, 6 or 8). - * DSI clock frequency = f(PLLSAI2) / PLLSAI2Q - * - @endif - * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock. - * This parameter must be in the range (2, 4, 6 or 8). - * - * @retval None - */ - -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - -# if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) - -#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ - (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) - -# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) - -#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | \ - (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) - -# else - -#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)) - -# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ - -#else - -# if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) - -#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - ((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) - -# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) - -#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \ - ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) - -# else - -#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ - WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \ - ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)) - -# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ - -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - - -/** - * @brief Macro to configure the PLLSAI2 clock multiplication factor N. - * - * @note This function must be used only when the PLLSAI2 is disabled. - * @note PLLSAI2 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock. - * This parameter must be a number between 8 and 86. - * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO - * output frequency is between 64 and 344 MHz. - * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N - * - * @retval None - */ -#define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) - -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - -/** @brief Macro to configure the PLLSAI2 input clock division factor M. - * - * @note This function must be used only when the PLLSAI2 is disabled. - * @note PLLSAI2 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI2M__ specifies the division factor for PLLSAI2 clock. - * This parameter must be a number between Min_Data = 1 and Max_Data = 16. - * - * @retval None - */ - -#define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) - -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - -/** @brief Macro to configure the PLLSAI2 clock division factor P. - * - * @note This function must be used only when the PLLSAI2 is disabled. - * @note PLLSAI2 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI2P__ specifies the division factor. - * This parameter must be a number in the range (7 or 17). - * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__ - * - * @retval None - */ -#define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) - -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) - -/** @brief Macro to configure the PLLSAI2 clock division factor Q. - * - * @note This function must be used only when the PLLSAI2 is disabled. - * @note PLLSAI2 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI2Q__ specifies the division factor for USB/RNG/SDMMC1 clock. - * This parameter must be in the range (2, 4, 6 or 8). - * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI2) / PLLSAI2Q - * - * @retval None - */ -#define __HAL_RCC_PLLSAI2_DIVQ_CONFIG(__PLLSAI2Q__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) - -#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ - -/** @brief Macro to configure the PLLSAI2 clock division factor R. - * - * @note This function must be used only when the PLLSAI2 is disabled. - * @note PLLSAI2 clock source is common with the main PLL (configured through - * __HAL_RCC_PLL_CONFIG() macro) - * - * @param __PLLSAI2R__ specifies the division factor. - * This parameter must be in the range (2, 4, 6 or 8). - * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__ - * - * @retval None - */ -#define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) - -/** - * @brief Macros to enable or disable the PLLSAI2. - * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes. - * @retval None - */ - -#define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON) - -#define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON) - -/** - * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). - * @note Enabling and disabling those clocks can be done without the need to stop the PLL. - * This is mainly used to save Power. - * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. - * This parameter can be one or a combination of the following values: - @if STM32L486xx - * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. - @endif - @if STM32L4A6xx - * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. - @endif - @if STM32L4S9xx - * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. - @endif - * @retval None - */ - -#define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) - -#define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) - -/** - * @brief Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK). - * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output. - * This parameter can be one of the following values: - @if STM32L486xx - * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. - @endif - @if STM32L4A6xx - * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral. - @endif - @if STM32L4S9xx - * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface in case. - * @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral. - @endif - * @retval SET / RESET - */ -#define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) - -#endif /* RCC_PLLSAI2_SUPPORT */ - -/** - * @brief Macro to configure the SAI1 clock source. - * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived - * from the PLLSAI1, system PLL or external clock (through a dedicated pin). - * This parameter can be one of the following values: - * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) - @if STM32L486xx - * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 - @endif - * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) - * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) - @if STM32L4S9xx - * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 - @endif - * - @if STM32L443xx - * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2. - @endif - * - * @retval None - */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__)) -#else -#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** @brief Macro to get the SAI1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) - @if STM32L486xx - * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2 - @endif - * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK) - * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) - * - * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 - * clock source when PLLs are disabled for devices without PLLSAI2. - * - */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL)) -#else -#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#if defined(SAI2) - -/** - * @brief Macro to configure the SAI2 clock source. - * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived - * from the PLLSAI2, system PLL or external clock (through a dedicated pin). - * This parameter can be one of the following values: - * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) - @if STM32L4S9xx - * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 - @endif - * - * @retval None - */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__)) -#else -#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** @brief Macro to get the SAI2 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) - */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL)) -#else -#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* SAI2 */ - -/** @brief Macro to configure the I2C1 clock (I2C1CLK). - * - * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock - * @retval None - */ -#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__)) - -/** @brief Macro to get the I2C1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock - */ -#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)) - -#if defined(I2C2) - -/** @brief Macro to configure the I2C2 clock (I2C2CLK). - * - * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock - * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock - * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock - * @retval None - */ -#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__)) - -/** @brief Macro to get the I2C2 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock - * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock - * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock - */ -#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)) - -#endif /* I2C2 */ - -/** @brief Macro to configure the I2C3 clock (I2C3CLK). - * - * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock - * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock - * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock - * @retval None - */ -#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__)) - -/** @brief Macro to get the I2C3 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock - * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock - * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock - */ -#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)) - -#if defined(I2C4) - -/** @brief Macro to configure the I2C4 clock (I2C4CLK). - * - * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock - * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock - * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock - * @retval None - */ -#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__)) - -/** @brief Macro to get the I2C4 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock - * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock - * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock - */ -#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)) - -#endif /* I2C4 */ - - -/** @brief Macro to configure the USART1 clock (USART1CLK). - * - * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock - * @retval None - */ -#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__)) - -/** @brief Macro to get the USART1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock - */ -#define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)) - -/** @brief Macro to configure the USART2 clock (USART2CLK). - * - * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock - * @retval None - */ -#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__)) - -/** @brief Macro to get the USART2 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock - */ -#define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)) - -#if defined(USART3) - -/** @brief Macro to configure the USART3 clock (USART3CLK). - * - * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock - * @retval None - */ -#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__)) - -/** @brief Macro to get the USART3 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock - */ -#define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)) - -#endif /* USART3 */ - -#if defined(UART4) - -/** @brief Macro to configure the UART4 clock (UART4CLK). - * - * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock - * @retval None - */ -#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__)) - -/** @brief Macro to get the UART4 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock - */ -#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)) - -#endif /* UART4 */ - -#if defined(UART5) - -/** @brief Macro to configure the UART5 clock (UART5CLK). - * - * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock - * @retval None - */ -#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__)) - -/** @brief Macro to get the UART5 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock - */ -#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)) - -#endif /* UART5 */ - -/** @brief Macro to configure the LPUART1 clock (LPUART1CLK). - * - * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock - * @retval None - */ -#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__)) - -/** @brief Macro to get the LPUART1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock - */ -#define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)) - -/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). - * - * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock - * @retval None - */ -#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) - -/** @brief Macro to get the LPTIM1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock - */ -#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)) - -/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). - * - * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock - * @retval None - */ -#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__)) - -/** @brief Macro to get the LPTIM2 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock - */ -#define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)) - -#if defined(SDMMC1) - -/** @brief Macro to configure the SDMMC1 clock. - * - @if STM32L486xx - * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. - @endif - * - @if STM32L443xx - * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. - @endif - * - * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. - * This parameter can be one of the following values: - @if STM32L486xx - * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock - @endif - @if STM32L443xx - * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock - @endif - @if STM32L4S9xx - * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock - @endif - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock - * @retval None - */ -#if defined(RCC_CCIPR2_SDMMCSEL) -#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ - do \ - { \ - if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \ - { \ - SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \ - } \ - } while(0) -#else -#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)) -#endif /* RCC_CCIPR2_SDMMCSEL */ - -/** @brief Macro to get the SDMMC1 clock. - * @retval The clock source can be one of the following values: - @if STM32L486xx - * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock - @endif - @if STM32L443xx - * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock - @endif - @if STM32L4S9xx - * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48 - * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock - * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock - @endif - * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock - */ -#if defined(RCC_CCIPR2_SDMMCSEL) -#define __HAL_RCC_GET_SDMMC1_SOURCE() \ - ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) -#else -#define __HAL_RCC_GET_SDMMC1_SOURCE() \ - (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) -#endif /* RCC_CCIPR2_SDMMCSEL */ - -#endif /* SDMMC1 */ - -/** @brief Macro to configure the RNG clock. - * - * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. - * - * @param __RNG_CLKSOURCE__ specifies the RNG clock source. - * This parameter can be one of the following values: - @if STM32L486xx - * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 - @endif - @if STM32L443xx - * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 - @endif - * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock - * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock - * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock - * @retval None - */ -#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__)) - -/** @brief Macro to get the RNG clock. - * @retval The clock source can be one of the following values: - @if STM32L486xx - * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48 - @endif - @if STM32L443xx - * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48 - @endif - * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock - * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock - * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock - */ -#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) - -#if defined(USB_OTG_FS) || defined(USB) - -/** @brief Macro to configure the USB clock (USBCLK). - * - * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. - * - * @param __USB_CLKSOURCE__ specifies the USB clock source. - * This parameter can be one of the following values: - @if STM32L486xx - * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 - @endif - @if STM32L443xx - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 - @endif - * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock - * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock - * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock - * @retval None - */ -#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__)) - -/** @brief Macro to get the USB clock source. - * @retval The clock source can be one of the following values: - @if STM32L486xx - * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48 - @endif - @if STM32L443xx - * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48 - @endif - * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock - * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock - * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock - */ -#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)) - -#endif /* USB_OTG_FS || USB */ - -/** @brief Macro to configure the ADC interface clock. - * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock - @if STM32L486xx - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices - @endif - * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock - * @retval None - */ -#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__)) - -/** @brief Macro to get the ADC clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock - @if STM32L486xx - * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices - @endif - * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock - */ -#define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)) - -#if defined(SWPMI1) - -/** @brief Macro to configure the SWPMI1 clock. - * @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock - * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock - * @retval None - */ -#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__)) - -/** @brief Macro to get the SWPMI1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock - * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock - */ -#define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)) - -#endif /* SWPMI1 */ - -#if defined(DFSDM1_Filter0) -/** @brief Macro to configure the DFSDM1 clock. - * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock - * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock - * @retval None - */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) -#else -#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** @brief Macro to get the DFSDM1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock - * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock - */ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL)) -#else -#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -/** @brief Macro to configure the DFSDM1 audio clock. - * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock - * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock - * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock - * @retval None - */ -#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__)) - -/** @brief Macro to get the DFSDM1 audio clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock - * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock - * @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock - */ -#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL)) - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) - -/** @brief Macro to configure the LTDC clock. - * @param __LTDC_CLKSOURCE__ specifies the DSI clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock - * @retval None - */ -#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__)) - -/** @brief Macro to get the LTDC clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock - * @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock - */ -#define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR)) - -#endif /* LTDC */ - -#if defined(DSI) - -/** @brief Macro to configure the DSI clock. - * @param __DSI_CLKSOURCE__ specifies the DSI clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock - * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock - * @retval None - */ -#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__)) - -/** @brief Macro to get the DSI clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock - * @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock - */ -#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL)) - -#endif /* DSI */ - -#if defined(OCTOSPI1) || defined(OCTOSPI2) - -/** @brief Macro to configure the OctoSPI clock. - * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock - * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock - * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock - * @retval None - */ -#define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__)) - -/** @brief Macro to get the OctoSPI clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock - * @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock - * @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock - */ -#define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL)) - -#endif /* OCTOSPI1 || OCTOSPI2 */ - -/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management - * @brief macros to manage the specified RCC Flags and interrupts. - * @{ - */ - -/** @brief Enable PLLSAI1RDY interrupt. - * @retval None - */ -#define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) - -/** @brief Disable PLLSAI1RDY interrupt. - * @retval None - */ -#define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) - -/** @brief Clear the PLLSAI1RDY interrupt pending bit. - * @retval None - */ -#define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC) - -/** @brief Check whether PLLSAI1RDY interrupt has occurred or not. - * @retval TRUE or FALSE. - */ -#define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) - -/** @brief Check whether the PLLSAI1RDY flag is set or not. - * @retval TRUE or FALSE. - */ -#define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) - -#if defined(RCC_PLLSAI2_SUPPORT) - -/** @brief Enable PLLSAI2RDY interrupt. - * @retval None - */ -#define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) - -/** @brief Disable PLLSAI2RDY interrupt. - * @retval None - */ -#define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) - -/** @brief Clear the PLLSAI2RDY interrupt pending bit. - * @retval None - */ -#define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC) - -/** @brief Check whether the PLLSAI2RDY interrupt has occurred or not. - * @retval TRUE or FALSE. - */ -#define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) - -/** @brief Check whether the PLLSAI2RDY flag is set or not. - * @retval TRUE or FALSE. - */ -#define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)) - -#endif /* RCC_PLLSAI2_SUPPORT */ - - -/** - * @brief Enable the RCC LSE CSS Extended Interrupt Line. - * @retval None - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Disable the RCC LSE CSS Extended Interrupt Line. - * @retval None - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Enable the RCC LSE CSS Event Line. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Disable the RCC LSE CSS Event Line. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) - - -/** - * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) - - -/** - * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) - - -/** - * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. - * @retval EXTI RCC LSE CSS Line Status. - */ -#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) - -/** - * @brief Clear the RCC LSE CSS EXTI flag. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) - - -#if defined(CRS) - -/** - * @brief Enable the specified CRS interrupts. - * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval None - */ -#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) - -/** - * @brief Disable the specified CRS interrupts. - * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval None - */ -#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) - -/** @brief Check whether the CRS interrupt has occurred or not. - * @param __INTERRUPT__ specifies the CRS interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** @brief Clear the CRS interrupt pending bits - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt - * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt - * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt - */ -/* CRS IT Error Mask */ -#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) - -#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ - if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \ - { \ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ - } \ - else \ - { \ - WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ - } \ - } while(0) - -/** - * @brief Check whether the specified CRS flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK - * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning - * @arg @ref RCC_CRS_FLAG_ERR Error - * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC - * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow - * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error - * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed - * @retval The new state of _FLAG_ (TRUE or FALSE). - */ -#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the CRS specified FLAG. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK - * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning - * @arg @ref RCC_CRS_FLAG_ERR Error - * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC - * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow - * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error - * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed - * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR - * @retval None - */ - -/* CRS Flag Error Mask */ -#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) - -#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ - if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \ - { \ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ - } \ - else \ - { \ - WRITE_REG(CRS->ICR, (__FLAG__)); \ - } \ - } while(0) - -#endif /* CRS */ - -/** - * @} - */ - -#if defined(CRS) - -/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features - * @{ - */ -/** - * @brief Enable the oscillator clock for frequency error counter. - * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. - * @retval None - */ -#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) - -/** - * @brief Disable the oscillator clock for frequency error counter. - * @retval None - */ -#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) - -/** - * @brief Enable the automatic hardware adjustement of TRIM bits. - * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. - * @retval None - */ -#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) - -/** - * @brief Enable or disable the automatic hardware adjustement of TRIM bits. - * @retval None - */ -#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) - -/** - * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies - * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency - * of the synchronization source after prescaling. It is then decreased by one in order to - * reach the expected synchronization on the zero value. The formula is the following: - * RELOAD = (fTARGET / fSYNC) -1 - * @param __FTARGET__ Target frequency (value in Hz) - * @param __FSYNC__ Synchronization signal frequency (value in Hz) - * @retval None - */ -#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCCEx_Exported_Functions - * @{ - */ - -/** @addtogroup RCCEx_Exported_Functions_Group1 - * @{ - */ - -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); - -/** - * @} - */ - -/** @addtogroup RCCEx_Exported_Functions_Group2 - * @{ - */ - -HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); -HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); - -#if defined(RCC_PLLSAI2_SUPPORT) - -HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init); -HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void); - -#endif /* RCC_PLLSAI2_SUPPORT */ - -void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); -void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); -void HAL_RCCEx_EnableLSECSS(void); -void HAL_RCCEx_DisableLSECSS(void); -void HAL_RCCEx_EnableLSECSS_IT(void); -void HAL_RCCEx_LSECSS_IRQHandler(void); -void HAL_RCCEx_LSECSS_Callback(void); -void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); -void HAL_RCCEx_DisableLSCO(void); -void HAL_RCCEx_EnableMSIPLLMode(void); -void HAL_RCCEx_DisableMSIPLLMode(void); - -/** - * @} - */ - -#if defined(CRS) - -/** @addtogroup RCCEx_Exported_Functions_Group3 - * @{ - */ - -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); -void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); -void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); -uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); -void HAL_RCCEx_CRS_IRQHandler(void); -void HAL_RCCEx_CRS_SyncOkCallback(void); -void HAL_RCCEx_CRS_SyncWarnCallback(void); -void HAL_RCCEx_CRS_ExpectedSyncCallback(void); -void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCCEx_Private_Macros - * @{ - */ - -#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) - -#if defined(STM32L431xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) - -#elif defined(STM32L432xx) || defined(STM32L442xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)) - -#elif defined(STM32L433xx) || defined(STM32L443xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) - -#elif defined(STM32L451xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) - -#elif defined(STM32L452xx) || defined(STM32L462xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) - -#elif defined(STM32L471xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) - -#elif defined(STM32L496xx) || defined(STM32L4A6xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) - -#elif defined(STM32L4R5xx) || defined(STM32L4S5xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)) - -#elif defined(STM32L4R7xx) || defined(STM32L4S7xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) - -#elif defined(STM32L4R9xx) || defined(STM32L4S9xx) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)) - -#else - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) - -#endif /* STM32L431xx */ - -#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) - -#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) - -#if defined(USART3) - -#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) - -#endif /* USART3 */ - -#if defined(UART4) - -#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) - -#endif /* UART4 */ - -#if defined(UART5) - -#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) - -#endif /* UART5 */ - -#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) - -#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) - -#if defined(I2C2) - -#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) - -#endif /* I2C2 */ - -#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) - -#if defined(I2C4) - -#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) - -#endif /* I2C4 */ - -#if defined(RCC_PLLSAI2_SUPPORT) - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define IS_RCC_SAI1CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) -#else -#define IS_RCC_SAI1CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#else - -#define IS_RCC_SAI1CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) - -#endif /* RCC_PLLSAI2_SUPPORT */ - -#if defined(RCC_PLLSAI2_SUPPORT) - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define IS_RCC_SAI2CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) -#else -#define IS_RCC_SAI2CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* RCC_PLLSAI2_SUPPORT */ - -#define IS_RCC_LPTIM1CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) - -#define IS_RCC_LPTIM2CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) - -#if defined(SDMMC1) -#if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL) - -#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) - -#elif defined(RCC_HSI48_SUPPORT) - -#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) -#else - -#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) - -#endif /* RCC_HSI48_SUPPORT */ -#endif /* SDMMC1 */ - -#if defined(RCC_HSI48_SUPPORT) - -#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) - -#else - -#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) - -#endif /* RCC_HSI48_SUPPORT */ - -#if defined(USB_OTG_FS) || defined(USB) -#if defined(RCC_HSI48_SUPPORT) - -#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) - -#else - -#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) - -#endif /* RCC_HSI48_SUPPORT */ -#endif /* USB_OTG_FS || USB */ - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) - -#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) - -#else - -#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ - -#if defined(SWPMI1) - -#define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI)) - -#endif /* SWPMI1 */ - -#if defined(DFSDM1_Filter0) - -#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ - ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ - ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI)) - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) - -#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV2) || \ - ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV4) || \ - ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV8) || \ - ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV16)) - -#endif /* LTDC */ - -#if defined(DSI) - -#define IS_RCC_DSICLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY) || \ - ((__SOURCE__) == RCC_DSICLKSOURCE_PLLSAI2)) - -#endif /* DSI */ - -#if defined(OCTOSPI1) || defined(OCTOSPI2) - -#define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \ - ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)) - -#endif /* OCTOSPI1 || OCTOSPI2 */ - -#define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) - -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) -#define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) -#else -#define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - -#define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) - -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) -#define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) -#else -#define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ - -#define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ - ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) - -#define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ - ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) - -#if defined(RCC_PLLSAI2_SUPPORT) - -#define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) - -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) -#define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) -#else -#define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - -#define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) - -#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) -#define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) -#else -#define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) -#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ - -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) -#define IS_RCC_PLLSAI2Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ - ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) -#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ - -#define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ - ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) - -#endif /* RCC_PLLSAI2_SUPPORT */ - -#if defined(CRS) - -#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ - ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ - ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) - -#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ - ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ - ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ - ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) - -#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ - ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) - -#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) - -#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) - -#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) - -#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ - ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) - -#endif /* CRS */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_RCC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h deleted file mode 100644 index 4eedd1bb2..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h +++ /dev/null @@ -1,325 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rng.h - * @author MCD Application Team - * @brief Header file of RNG HAL module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_RNG_H -#define __STM32L4xx_HAL_RNG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup RNG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Exported_Types RNG Exported Types - * @{ - */ - -#if defined(RNG_CR_CED) -/** - * @brief RNG Configuration Structure definition - */ -typedef struct -{ - uint32_t ClockErrorDetection; /*!< Clock error detection */ -}RNG_InitTypeDef; -#endif /* defined(RNG_CR_CED) */ - -/** - * @brief RNG HAL State Structure definition - */ -typedef enum -{ - HAL_RNG_STATE_RESET = 0x00, /*!< RNG not yet initialized or disabled */ - HAL_RNG_STATE_READY = 0x01, /*!< RNG initialized and ready for use */ - HAL_RNG_STATE_BUSY = 0x02, /*!< RNG internal process is ongoing */ - HAL_RNG_STATE_TIMEOUT = 0x03, /*!< RNG timeout state */ - HAL_RNG_STATE_ERROR = 0x04 /*!< RNG error state */ - -}HAL_RNG_StateTypeDef; - -/** - * @brief RNG Handle Structure definition - */ -typedef struct -{ - RNG_TypeDef *Instance; /*!< Register base address */ - -#if defined(RNG_CR_CED) - RNG_InitTypeDef Init; /*!< RNG configuration parameters */ -#endif /* defined(RNG_CR_CED) */ - - HAL_LockTypeDef Lock; /*!< RNG locking object */ - - __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ - - uint32_t RandomNumber; /*!< Last Generated RNG Data */ - -}RNG_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Exported_Constants RNG Exported Constants - * @{ - */ - -/** @defgroup RNG_Interrupt_definition RNG Interrupts Definition - * @{ - */ -#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */ -#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */ -#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */ -/** - * @} - */ - -/** @defgroup RNG_Flag_definition RNG Flags Definition - * @{ - */ -#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */ -#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */ -#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */ -/** - * @} - */ - -#if defined(RNG_CR_CED) -/** @defgroup RNG_Clock_Error_Detection RNG Clock Error Detection - * @{ - */ -#define RNG_CED_ENABLE ((uint32_t)0x00000000) /*!< Clock error detection enabled */ -#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */ -/** - * @} - */ -#endif /* defined(RNG_CR_CED) */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup RNG_Exported_Macros RNG Exported Macros - * @{ - */ - -/** @brief Reset RNG handle state. - * @param __HANDLE__: RNG Handle - * @retval None - */ -#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) - -/** - * @brief Enable the RNG peripheral. - * @param __HANDLE__: RNG Handle - * @retval None - */ -#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN) - -/** - * @brief Disable the RNG peripheral. - * @param __HANDLE__: RNG Handle - * @retval None - */ -#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN) - -/** - * @brief Check whether the specified RNG flag is set or not. - * @param __HANDLE__: RNG Handle - * @param __FLAG__: RNG flag - * This parameter can be one of the following values: - * @arg RNG_FLAG_DRDY: Data ready - * @arg RNG_FLAG_CECS: Clock error current status - * @arg RNG_FLAG_SECS: Seed error current status - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - - -/** - * @brief Clear the selected RNG flag status. - * @param __HANDLE__: RNG handle - * @param __FLAG__: RNG flag to clear - * @note WARNING: This is a dummy macro for HAL code alignment, - * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only. - * @retval None - */ -#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */ - - - -/** - * @brief Enable the RNG interrupt. - * @param __HANDLE__: RNG Handle - * @retval None - */ -#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE) - -/** - * @brief Disable the RNG interrupt. - * @param __HANDLE__: RNG Handle - * @retval None - */ -#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE) - -/** - * @brief Check whether the specified RNG interrupt has occurred or not. - * @param __HANDLE__: RNG Handle - * @param __INTERRUPT__: specifies the RNG interrupt status flag to check. - * This parameter can be one of the following values: - * @arg RNG_IT_DRDY: Data ready interrupt - * @arg RNG_IT_CEI: Clock error interrupt - * @arg RNG_IT_SEI: Seed error interrupt - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** - * @brief Clear the RNG interrupt status flags. - * @param __HANDLE__: RNG Handle - * @param __INTERRUPT__: specifies the RNG interrupt status flag to clear. - * This parameter can be one of the following values: - * @arg RNG_IT_CEI: Clock error interrupt - * @arg RNG_IT_SEI: Seed error interrupt - * @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY. - * @retval None - */ -#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__)) - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Exported_Functions RNG Exported Functions - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng); -HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng); -void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng); -void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng); -/** - * @} - */ - -/* Peripheral Control functions ************************************************/ -/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions - * @{ - */ -uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */ -uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */ - -HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); -HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng); - -void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); -void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); -void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit); -/** - * @} - */ - -/* Peripheral State functions **************************************************/ -/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions - * @{ - */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RNG_Private_Macros RNG Private Macros - * @{ - */ - -#if defined(RNG_CR_CED) -/** - * @brief Verify the RNG Clock Error Detection mode. - * @param __MODE__: RNG Clock Error Detection mode - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_RNG_CED(__MODE__) (((__MODE__) == RNG_CED_ENABLE) || \ - ((__MODE__) == RNG_CED_DISABLE)) -#endif /* defined(RNG_CR_CED) */ - -/** - * @} - */ -/* Private functions prototypes ----------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_RNG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h deleted file mode 100644 index ed269a98c..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h +++ /dev/null @@ -1,861 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rtc.h - * @author MCD Application Team - * @brief Header file of RTC HAL module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_RTC_H -#define __STM32L4xx_HAL_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RTC_Exported_Types RTC Exported Types - * @{ - */ -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */ - HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */ - HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ - HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ - HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ - -}HAL_RTCStateTypeDef; - -/** - * @brief RTC Configuration Structure definition - */ -typedef struct -{ - uint32_t HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ - - uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ - - uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. - This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ - - uint32_t OutPutRemap; /*!< Specifies the remap for RTC output. - This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */ - - uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. - This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ - - uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. - This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ -}RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t Hours; /*!< Specifies the RTC Time Hour. - This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. - This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ - - uint8_t Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - - uint8_t Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - - uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ - - uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. - This parameter corresponds to a time unit range between [0-1] Second - with [1 Sec / SecondFraction +1] granularity */ - - uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content - corresponding to Synchronous pre-scaler factor value (PREDIV_S) - This parameter corresponds to a time unit range between [0-1] Second - with [1 Sec / SecondFraction +1] granularity. - This field will be used only by HAL_RTC_GetTime function */ - - uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. - This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ - - uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit - in CR register to store the operation. - This parameter can be a value of @ref RTC_StoreOperation_Definitions */ -}RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t Date; /*!< Specifies the RTC Date. - This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ - - uint8_t Year; /*!< Specifies the RTC Date Year. - This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ - -}RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ - - uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - - uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. - This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ - - uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. - If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint32_t Alarm; /*!< Specifies the alarm . - This parameter can be a value of @ref RTC_Alarms_Definitions */ -}RTC_AlarmTypeDef; - -/** - * @brief Time Handle Structure definition - */ -typedef struct -{ - RTC_TypeDef *Instance; /*!< Register base address */ - - RTC_InitTypeDef Init; /*!< RTC required parameters */ - - HAL_LockTypeDef Lock; /*!< RTC locking object */ - - __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ - -}RTC_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RTC_Exported_Constants RTC Exported Constants - * @{ - */ - -/** @defgroup RTC_Hour_Formats RTC Hour Formats - * @{ - */ -#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000) -#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040) -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions - * @{ - */ -#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000) -#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000) -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT - * @{ - */ -#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000) -#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE) -/** - * @} - */ - -/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap - * @{ - */ -#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000) -#define RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP) -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions - * @{ - */ -#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) -/** - * @} - */ - -/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions - * @{ - */ -#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000) -#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000) -#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions - * @{ - */ -#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000) -#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000) -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions - * @{ - */ -#define RTC_FORMAT_BIN ((uint32_t)0x00000000) -#define RTC_FORMAT_BCD ((uint32_t)0x00000001) -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions - * @{ - */ - -/* Coded in BCD format */ -#define RTC_MONTH_JANUARY ((uint8_t)0x01) -#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) -#define RTC_MONTH_MARCH ((uint8_t)0x03) -#define RTC_MONTH_APRIL ((uint8_t)0x04) -#define RTC_MONTH_MAY ((uint8_t)0x05) -#define RTC_MONTH_JUNE ((uint8_t)0x06) -#define RTC_MONTH_JULY ((uint8_t)0x07) -#define RTC_MONTH_AUGUST ((uint8_t)0x08) -#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) -#define RTC_MONTH_OCTOBER ((uint8_t)0x10) -#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) -#define RTC_MONTH_DECEMBER ((uint8_t)0x12) -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions - * @{ - */ -#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) -#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) -#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) -#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) -#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) -#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) -#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) -/** - * @} - */ - -/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions - * @{ - */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000) -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000) -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions - * @{ - */ -#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) -#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 -#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 -#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 -#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions - * @{ - */ -#define RTC_ALARM_A RTC_CR_ALRAE -#define RTC_ALARM_B RTC_CR_ALRBE -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions - * @{ - */ -#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm - comparison. Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm - comparison. Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match - to activate alarm. */ -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) /*!< Enable Timestamp Interrupt */ -#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) /*!< Enable Wakeup timer Interrupt */ -#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) /*!< Enable Alarm A Interrupt */ -#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) /*!< Enable Alarm B Interrupt */ -#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /*!< Enable all Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt */ -#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt */ -#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE) /*!< Enable Tamper 3 Interrupt */ -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions RTC Flags Definitions - * @{ - */ -#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF) -#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F) -#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F) -#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F) -#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF) -#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF) -#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF) -#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF) -#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF) -#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF) -#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF) -#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF) -#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS) -#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF) -#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF) -#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF) -#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup RTC_Exported_Macros RTC Exported Macros - * @{ - */ - -/** @brief Reset RTC handle state. - * @param __HANDLE__: RTC handle. - * @retval None - */ -#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) - -/** - * @brief Disable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->WPR = 0xCA; \ - (__HANDLE__)->Instance->WPR = 0x53; \ - } while(0) - -/** - * @brief Enable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->WPR = 0xFF; \ - } while(0) - - -/** - * @brief Enable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) - -/** - * @brief Disable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) - -/** - * @brief Enable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) - -/** - * @brief Disable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) - -/** - * @brief Enable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Alarm interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) - -/** - * @brief Get the selected RTC Alarm's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to check. - * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF - * @arg RTC_FLAG_ALRAWF - * @arg RTC_FLAG_ALRBWF - * @retval None - */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Clear the RTC Alarm's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. - * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF - * @retval None - */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Check whether the specified RTC Alarm interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** - * @brief Enable interrupt on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable interrupt on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) - -/** - * @brief Enable event on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable event on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) - -/** - * @brief Enable falling edge trigger on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable falling edge trigger on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) - -/** - * @brief Enable rising edge trigger on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable rising edge trigger on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) - -/** - * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not. - * @retval Line Status. - */ -#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Clear the RTC Alarm associated Exti line flag. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Generate a Software interrupt on RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @} - */ - -/* Include RTC HAL Extended module */ -#include "stm32l4xx_hal_rtc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTC_Exported_Functions - * @{ - */ - -/** @addtogroup RTC_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group2 - * @{ - */ -/* RTC Time and Date functions ************************************************/ -HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group3 - * @{ - */ -/* RTC Alarm functions ********************************************************/ -HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group4 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group5 - * @{ - */ -/* Peripheral State functions *************************************************/ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); - -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RTC_Private_Constants RTC Private Constants - * @{ - */ -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK 0x007F7F7FU -#define RTC_DR_RESERVED_MASK 0x00FFFF3FU -#define RTC_INIT_MASK 0xFFFFFFFFU -#define RTC_RSF_MASK 0xFFFFFF5FU - -#define RTC_TIMEOUT_VALUE 1000 - -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the RTC Alarm event */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup RTC_Private_Macros RTC Private Macros - * @{ - */ - -/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters - * @{ - */ - -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ - ((FORMAT) == RTC_HOURFORMAT_24)) - -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ - ((POL) == RTC_OUTPUT_POLARITY_LOW)) - -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ - ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) - -#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \ - ((REMAP) == RTC_OUTPUT_REMAP_POS1)) - -#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM)) - -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ - ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ - ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) - -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ - ((OPERATION) == RTC_STOREOPERATION_SET)) - -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) - -#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99) - -#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12)) - -#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31)) - -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) - -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31)) - -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ - ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) - -#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) - -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) - -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF) - -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) - -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F) - -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF) - -#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12)) - -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23) - -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59) - -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59) - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup RTC_Private_Functions - * @{ - */ - -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); -uint8_t RTC_ByteToBcd2(uint8_t Value); -uint8_t RTC_Bcd2ToByte(uint8_t Value); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_RTC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h deleted file mode 100644 index 102703f1e..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h +++ /dev/null @@ -1,1100 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rtc_ex.h - * @author MCD Application Team - * @brief Header file of RTC HAL Extended module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_RTC_EX_H -#define __STM32L4xx_HAL_RTC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup RTCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Types RTCEx Exported Types - * @{ - */ -/** - * @brief RTC Tamper structure definition - */ -typedef struct -{ - uint32_t Tamper; /*!< Specifies the Tamper Pin. - This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ - - uint32_t Interrupt; /*!< Specifies the Tamper Interrupt. - This parameter can be a value of @ref RTCEx_Tamper_Interrupt_Definitions */ - - uint32_t Trigger; /*!< Specifies the Tamper Trigger. - This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ - - uint32_t NoErase; /*!< Specifies the Tamper no erase mode. - This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */ - - uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. - This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */ - - uint32_t Filter; /*!< Specifies the RTC Filter Tamper. - This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ - - uint32_t SamplingFrequency; /*!< Specifies the sampling frequency. - This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */ - - uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration . - This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ - - uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp . - This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */ - - uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. - This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ -}RTC_TamperTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants - * @{ - */ - -/** @defgroup RTCEx_Output_selection_Definitions RTC Output Selection Definitions - * @{ - */ -#define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000) -#define RTC_OUTPUT_ALARMA ((uint32_t)0x00200000) -#define RTC_OUTPUT_ALARMB ((uint32_t)0x00400000) -#define RTC_OUTPUT_WAKEUP ((uint32_t)0x00600000) -/** - * @} - */ - -/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions - * @{ - */ -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#define RTC_BKP_DR20 ((uint32_t)0x00000014) -#define RTC_BKP_DR21 ((uint32_t)0x00000015) -#define RTC_BKP_DR22 ((uint32_t)0x00000016) -#define RTC_BKP_DR23 ((uint32_t)0x00000017) -#define RTC_BKP_DR24 ((uint32_t)0x00000018) -#define RTC_BKP_DR25 ((uint32_t)0x00000019) -#define RTC_BKP_DR26 ((uint32_t)0x0000001A) -#define RTC_BKP_DR27 ((uint32_t)0x0000001B) -#define RTC_BKP_DR28 ((uint32_t)0x0000001C) -#define RTC_BKP_DR29 ((uint32_t)0x0000001D) -#define RTC_BKP_DR30 ((uint32_t)0x0000001E) -#define RTC_BKP_DR31 ((uint32_t)0x0000001F) -/** - * @} - */ - -/** @defgroup RTCEx_TimeStamp_Edges_definitions RTC TimeStamp Edges Definitions - * @{ - */ -#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000) -#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection - * @{ - */ -#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions - * @{ - */ -#if defined(RTC_TAMPER1_SUPPORT) -#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E -#endif /* RTC_TAMPER1_SUPPORT */ -#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E -#if defined(RTC_TAMPER3_SUPPORT) -#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E -#endif /* RTC_TAMPER3_SUPPORT */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions - * @{ - */ -#if defined(RTC_TAMPER1_SUPPORT) -#define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE -#endif /* RTC_TAMPER1_SUPPORT */ -#define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE -#if defined(RTC_TAMPER3_SUPPORT) -#define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE -#endif /* RTC_TAMPER3_SUPPORT */ -#define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions - * @{ - */ -#define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) -#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002) -#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE -#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Tamper EraseBackUp Definitions -* @{ -*/ -#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000) -#define RTC_TAMPER_ERASE_BACKUP_DISABLE ((uint32_t)0x00020000) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Tamper Mask Flag Definitions -* @{ -*/ -#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000) -#define RTC_TAMPERMASK_FLAG_ENABLE ((uint32_t)0x00040000) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions - * @{ - */ -#define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ - -#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8 - consecutive samples at the active level. */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions - * @{ - */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions - * @{ - */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions - * @{ - */ -#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions - * @{ - */ -#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ -/** - * @} - */ - -/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wakeup Timer Definitions - * @{ - */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003) -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004) -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions - * @{ - */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 8s, else 2exp18 RTCCLK seconds */ -/** - * @} - */ - -/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions - * @{ - */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0] - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0] */ -/** - * @} - */ - -/** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions - * @{ - */ -#define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) -#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000) -/** - * @} - */ - -/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions - * @{ - */ -#define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000) -#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros - * @{ - */ - -/** - * @brief Enable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) - -/** - * @brief Disable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) - -/** - * @brief Enable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be disabled. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) - -/** - * @brief Check whether the specified RTC Wake Up timer interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** - * @brief Get the selected RTC WakeUpTimer's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_WUTF - * @arg RTC_FLAG_WUTWF - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Clear the RTC Wake Up timer's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear. - * This parameter can be: - * @arg RTC_FLAG_WUTF - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -#if defined(RTC_TAMPER1_SUPPORT) -/** - * @brief Enable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E)) - -/** - * @brief Disable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E)) -#endif /* RTC_TAMPER1_SUPPORT */ - -/** - * @brief Enable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E)) - -/** - * @brief Disable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E)) - -#if defined(RTC_TAMPER3_SUPPORT) -/** - * @brief Enable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E)) - -/** - * @brief Disable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E)) -#endif /* RTC_TAMPER3_SUPPORT */ - -/** - * @brief Enable the RTC Tamper interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC Tamper interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. - * This parameter can be: - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT) -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3)) != RESET) ? SET : RESET) : \ - ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) : \ - (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7)) != RESET) ? SET : RESET)) -#else -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5)) != RESET) ? SET : RESET) -#endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */ - -/** - * @brief Check whether the specified RTC Tamper interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TAMP: All tampers interrupts - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** - * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper1 flag - * @arg RTC_FLAG_TAMP2F: Tamper2 flag - * @arg RTC_FLAG_TAMP3F: Tamper3 flag - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to clear. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper1 flag - * @arg RTC_FLAG_TAMP2F: Tamper2 flag - * @arg RTC_FLAG_TAMP3F: Tamper3 flag - * @retval None - */ -#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Enable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) - -/** - * @brief Disable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) - -/** - * @brief Enable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be enabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to be disabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET) - -/** - * @brief Check whether the specified RTC Time Stamp interrupt is enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** - * @brief Get the selected RTC TimeStamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC TimeStamp Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_TSF - * @arg RTC_FLAG_TSOVF - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Clear the RTC Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. - * This parameter can be: - * @arg RTC_FLAG_TSF - * @arg RTC_FLAG_TSOVF - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Enable the RTC internal TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE)) - -/** - * @brief Disable the RTC internal TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE)) - -/** - * @brief Get the selected RTC Internal Time Stamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_ITSF - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Clear the RTC Internal Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear. - * This parameter can be: - * @arg RTC_FLAG_ITSF - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Enable the RTC calibration output. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) - -/** - * @brief Disable the calibration output. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) - -/** - * @brief Enable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) - -/** - * @brief Disable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) - -/** - * @brief Get the selected RTC shift operation's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC shift operation Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_SHPF - * @retval None - */ -#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET) - -/** - * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable event on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable event on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. - * This parameter can be: - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not. - * @retval Line Status. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Clear the RTC WakeUp Timer associated Exti line flag. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) - -/** - * @brief Enable event on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable event on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) - -/** - * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) - -/** - * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) - -/** - * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. - * This parameter can be: - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not. - * @retval Line Status. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Clear the RTC Tamper and Timestamp associated Exti line flag. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTCEx_Exported_Functions - * @{ - */ - -/* RTC TimeStamp and Tamper functions *****************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); -HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); - -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); - -#if defined(RTC_TAMPER1_SUPPORT) -void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); -#endif /* RTC_TAMPER1_SUPPORT */ -void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); -#if defined(RTC_TAMPER3_SUPPORT) -void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); -#endif /* RTC_TAMPER3_SUPPORT */ -void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#if defined(RTC_TAMPER1_SUPPORT) -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#endif /* RTC_TAMPER1_SUPPORT */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#if defined(RTC_TAMPER3_SUPPORT) -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#endif /* RTC_TAMPER3_SUPPORT */ -/** - * @} - */ - -/* RTC Wake-up functions ******************************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -/** - * @} - */ - -/* Extended Control functions ************************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group3 - * @{ - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); - -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/* Extended RTC features functions *******************************************/ -/** @addtogroup RTCEx_Exported_Functions_Group4 - * @{ - */ -void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RTCEx_Private_Constants RTCEx Private Constants - * @{ - */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup RTCEx_Private_Macros RTCEx Private Macros - * @{ - */ - -/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters - * @{ - */ - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ - ((OUTPUT) == RTC_OUTPUT_WAKEUP)) - -#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER) - -#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ - ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) - -#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) - -#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & (uint32_t)0xFFB6FFFB) == 0x00) && ((INTERRUPT) != (uint32_t)RESET)) - -#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT)) - -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) - -#define IS_RTC_TAMPER_ERASE_MODE(MODE) (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \ - ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE)) - -#define IS_RTC_TAMPER_MASKFLAG_STATE(STATE) (((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \ - ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE)) - -#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ - ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) - -#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) - -#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) - -#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ - ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) - -#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ - ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) - -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) - -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) - -#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) - -#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ - ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) - -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) - -#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ - ((SEL) == RTC_SHIFTADD1S_SET)) - -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) - -#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ - ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_RTC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h deleted file mode 100644 index bfc0194b0..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h +++ /dev/null @@ -1,2043 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_tim.h - * @author MCD Application Team - * @brief Header file of TIM HAL module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_TIM_H -#define __STM32L4xx_HAL_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIM_Exported_Types TIM Exported Types - * @{ - */ - -/** - * @brief TIM Time base Configuration Structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_ClockDivision */ - - uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. - This parameter can be a value of @ref TIM_AutoReloadPreload */ -} TIM_Base_InitTypeDef; - -/** - * @brief TIM Output Compare Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCFastMode; /*!< Specifies the Fast mode state. - This parameter can be a value of @ref TIM_Output_Fast_State - @note This parameter is valid only in PWM1 and PWM2 mode. */ - - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OC_InitTypeDef; - -/** - * @brief TIM One Pulse Mode Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_OnePulse_InitTypeDef; - - -/** - * @brief TIM Input Capture Configuration Structure definition - */ -typedef struct -{ - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_IC_InitTypeDef; - -/** - * @brief TIM Encoder Configuration Structure definition - */ -typedef struct -{ - uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Mode */ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC1Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC2Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC2Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_Encoder_InitTypeDef; - - -/** - * @brief Clock Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClockSource; /*!< TIM clock sources - This parameter can be a value of @ref TIM_Clock_Source */ - uint32_t ClockPolarity; /*!< TIM clock polarity - This parameter can be a value of @ref TIM_Clock_Polarity */ - uint32_t ClockPrescaler; /*!< TIM clock prescaler - This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClockConfigTypeDef; - -/** - * @brief Clear Input Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClearInputState; /*!< TIM clear Input state - This parameter can be ENABLE or DISABLE */ - uint32_t ClearInputSource; /*!< TIM clear Input sources - This parameter can be a value of @ref TIM_ClearInput_Source */ - uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity - This parameter can be a value of @ref TIM_ClearInput_Polarity */ - uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter can be a value of @ref TIM_ClearInput_Prescaler */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -}TIM_ClearInputConfigTypeDef; - -/** - * @brief TIM Master configuration Structure definition - * @note Advanced timers provide TRGO2 internal line which is redirected - * to the ADC - */ -typedef struct { - uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ - uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ - uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode */ -}TIM_MasterConfigTypeDef; - -/** - * @brief TIM Slave configuration Structure definition - */ -typedef struct { - uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ - uint32_t InputTrigger; /*!< Input Trigger source - This parameter can be a value of @ref TIM_Trigger_Selection */ - uint32_t TriggerPolarity; /*!< Input Trigger polarity - This parameter can be a value of @ref TIM_Trigger_Polarity */ - uint32_t TriggerPrescaler; /*!< Input trigger prescaler - This parameter can be a value of @ref TIM_Trigger_Prescaler */ - uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - -}TIM_SlaveConfigTypeDef; - -/** - * @brief TIM Break input(s) and Dead time configuration Structure definition - * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable - * filter and polarity. - */ -typedef struct -{ - uint32_t OffStateRunMode; /*!< TIM off state in run mode - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity - This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t BreakFilter; /*!< Specifies the break input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Break2State; /*!< TIM Break2 State - This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ - uint32_t Break2Polarity; /*!< TIM Break2 input polarity - This parameter can be a value of @ref TIM_Break2_Polarity */ - uint32_t Break2Filter; /*!< TIM break2 input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BreakDeadTimeConfigTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ -}HAL_TIM_StateTypeDef; - -/** - * @brief HAL Active channel structures definition - */ -typedef enum -{ - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_5 = 0x10, /*!< The active channel is 5 */ - HAL_TIM_ACTIVE_CHANNEL_6 = 0x20, /*!< The active channel is 6 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ -}HAL_TIM_ActiveChannel; - -/** - * @brief TIM Time Base Handle Structure definition - */ -typedef struct -{ - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ -}TIM_HandleTypeDef; - -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_Exported_Constants TIM Exported Constants - * @{ - */ - -/** @defgroup TIM_ClearInput_Source TIM Clear Input Source - * @{ - */ -#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) -#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) -#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address TIM DMA Base Address - * @{ - */ -#define TIM_DMABASE_CR1 (0x00000000) -#define TIM_DMABASE_CR2 (0x00000001) -#define TIM_DMABASE_SMCR (0x00000002) -#define TIM_DMABASE_DIER (0x00000003) -#define TIM_DMABASE_SR (0x00000004) -#define TIM_DMABASE_EGR (0x00000005) -#define TIM_DMABASE_CCMR1 (0x00000006) -#define TIM_DMABASE_CCMR2 (0x00000007) -#define TIM_DMABASE_CCER (0x00000008) -#define TIM_DMABASE_CNT (0x00000009) -#define TIM_DMABASE_PSC (0x0000000A) -#define TIM_DMABASE_ARR (0x0000000B) -#define TIM_DMABASE_RCR (0x0000000C) -#define TIM_DMABASE_CCR1 (0x0000000D) -#define TIM_DMABASE_CCR2 (0x0000000E) -#define TIM_DMABASE_CCR3 (0x0000000F) -#define TIM_DMABASE_CCR4 (0x00000010) -#define TIM_DMABASE_BDTR (0x00000011) -#define TIM_DMABASE_DCR (0x00000012) -#define TIM_DMABASE_DMAR (0x00000013) -#define TIM_DMABASE_OR1 (0x00000014) -#define TIM_DMABASE_CCMR3 (0x00000015) -#define TIM_DMABASE_CCR5 (0x00000016) -#define TIM_DMABASE_CCR6 (0x00000017) -#define TIM_DMABASE_OR2 (0x00000018) -#define TIM_DMABASE_OR3 (0x00000019) -/** - * @} - */ - -/** @defgroup TIM_Event_Source TIM Extended Event Source - * @{ - */ -#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ -#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ -#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ -#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ -#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ -#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ -#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ -#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ -#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ -/** - * @} - */ - -/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity - * @{ - */ -#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Polarity TIM ETR Polarity - * @{ - */ -#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler - * @{ - */ -#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ -#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ -#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ -#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode TIM Counter Mode - * @{ - */ -#define TIM_COUNTERMODE_UP ((uint32_t)0x0000) -#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR -#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 -#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 -#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS -/** - * @} - */ - -/** @defgroup TIM_ClockDivision TIM Clock Division - * @{ - */ -#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) -#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) -#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) -/** - * @} - */ - -/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload - * @{ - */ -#define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000) /*!< TIMx_ARR register is not buffered */ -#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State TIM Output Compare State - * @{ - */ -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State - * @{ - */ -#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) -#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) -/** - * @} - */ - -/** @defgroup TIM_Output_Fast_State TIM Output Fast State - * @{ - */ -#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) -#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity - * @{ - */ -#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) -#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity - * @{ - */ -#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) -#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State - * @{ - */ -#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) -#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State - * @{ - */ -#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) -#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity - * @{ - */ -#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING -#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING -#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection - * @{ - */ -#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ -#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler - * @{ - */ -#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ -#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ -#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ -#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode - * @{ - */ -#define TIM_OPMODE_SINGLE (TIM_CR1_OPM) -#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode TIM Encoder Mode - * @{ - */ -#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) -#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) -#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) -/** - * @} - */ - -/** @defgroup TIM_Interrupt_definition TIM interrupt Definition - * @{ - */ -#define TIM_IT_UPDATE (TIM_DIER_UIE) -#define TIM_IT_CC1 (TIM_DIER_CC1IE) -#define TIM_IT_CC2 (TIM_DIER_CC2IE) -#define TIM_IT_CC3 (TIM_DIER_CC3IE) -#define TIM_IT_CC4 (TIM_DIER_CC4IE) -#define TIM_IT_COM (TIM_DIER_COMIE) -#define TIM_IT_TRIGGER (TIM_DIER_TIE) -#define TIM_IT_BREAK (TIM_DIER_BIE) -/** - * @} - */ - -/** @defgroup TIM_Commutation_Source TIM Commutation Source - * @{ - */ -#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) -#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources TIM DMA Sources - * @{ - */ -#define TIM_DMA_UPDATE (TIM_DIER_UDE) -#define TIM_DMA_CC1 (TIM_DIER_CC1DE) -#define TIM_DMA_CC2 (TIM_DIER_CC2DE) -#define TIM_DMA_CC3 (TIM_DIER_CC3DE) -#define TIM_DMA_CC4 (TIM_DIER_CC4DE) -#define TIM_DMA_COM (TIM_DIER_COMDE) -#define TIM_DMA_TRIGGER (TIM_DIER_TDE) -/** - * @} - */ - -/** @defgroup TIM_Flag_definition TIM Flag Definition - * @{ - */ -#define TIM_FLAG_UPDATE (TIM_SR_UIF) -#define TIM_FLAG_CC1 (TIM_SR_CC1IF) -#define TIM_FLAG_CC2 (TIM_SR_CC2IF) -#define TIM_FLAG_CC3 (TIM_SR_CC3IF) -#define TIM_FLAG_CC4 (TIM_SR_CC4IF) -#define TIM_FLAG_CC5 (TIM_SR_CC5IF) -#define TIM_FLAG_CC6 (TIM_SR_CC6IF) -#define TIM_FLAG_COM (TIM_SR_COMIF) -#define TIM_FLAG_TRIGGER (TIM_SR_TIF) -#define TIM_FLAG_BREAK (TIM_SR_BIF) -#define TIM_FLAG_BREAK2 (TIM_SR_B2IF) -#define TIM_FLAG_SYSTEM_BREAK (TIM_SR_SBIF) -#define TIM_FLAG_CC1OF (TIM_SR_CC1OF) -#define TIM_FLAG_CC2OF (TIM_SR_CC2OF) -#define TIM_FLAG_CC3OF (TIM_SR_CC3OF) -#define TIM_FLAG_CC4OF (TIM_SR_CC4OF) -/** - * @} - */ - -/** @defgroup TIM_Channel TIM Channel - * @{ - */ -#define TIM_CHANNEL_1 ((uint32_t)0x0000) -#define TIM_CHANNEL_2 ((uint32_t)0x0004) -#define TIM_CHANNEL_3 ((uint32_t)0x0008) -#define TIM_CHANNEL_4 ((uint32_t)0x000C) -#define TIM_CHANNEL_5 ((uint32_t)0x0010) -#define TIM_CHANNEL_6 ((uint32_t)0x0014) -#define TIM_CHANNEL_ALL ((uint32_t)0x003C) -/** - * @} - */ - -/** @defgroup TIM_Clock_Source TIM Clock Source - * @{ - */ -#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) -#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) -#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) -#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) -/** - * @} - */ - -/** @defgroup TIM_Clock_Polarity TIM Clock Polarity - * @{ - */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler - * @{ - */ -#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ -#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ -#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity - * @{ - */ -#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler - * @{ - */ -#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state - * @{ - */ -#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) -#define TIM_OSSR_DISABLE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state - * @{ - */ -#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) -#define TIM_OSSI_DISABLE ((uint32_t)0x0000) -/** - * @} - */ -/** @defgroup TIM_Lock_level TIM Lock level - * @{ - */ -#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) -#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) -#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) -#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable - * @{ - */ -#define TIM_BREAK_ENABLE (TIM_BDTR_BKE) -#define TIM_BREAK_DISABLE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity TIM Break Input Polarity - * @{ - */ -#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) -#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) -/** - * @} - */ - -/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable - * @{ - */ -#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000) -#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) -/** - * @} - */ - -/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity - * @{ - */ -#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000) -#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable - * @{ - */ -#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) -#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 - * @{ - */ -#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ -#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ -#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ -#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection - * @{ - */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) -#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) -#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) -#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) -#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) -#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) - * @{ - */ -#define TIM_TRGO2_RESET ((uint32_t)0x00000000) -#define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) -#define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2)) -#define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3)) -#define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)) -#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) -#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)) -#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode - * @{ - */ -#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) -#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode TIM Slave mode - * @{ - */ -#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) -#define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2)) -#define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)) -#define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)) -#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)) -#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes - * @{ - */ -#define TIM_OCMODE_TIMING ((uint32_t)0x0000) -#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) -#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2) - -#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3) -#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) -#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) -#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Selection TIM Trigger Selection - * @{ - */ -#define TIM_TS_ITR0 ((uint32_t)0x0000) -#define TIM_TS_ITR1 ((uint32_t)0x0010) -#define TIM_TS_ITR2 ((uint32_t)0x0020) -#define TIM_TS_ITR3 ((uint32_t)0x0030) -#define TIM_TS_TI1F_ED ((uint32_t)0x0040) -#define TIM_TS_TI1FP1 ((uint32_t)0x0050) -#define TIM_TS_TI2FP2 ((uint32_t)0x0060) -#define TIM_TS_ETRF ((uint32_t)0x0070) -#define TIM_TS_NONE ((uint32_t)0xFFFF) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity - * @{ - */ -#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler - * @{ - */ -#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ -#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ -#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection - * @{ - */ -#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) -#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length - * @{ - */ -#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) -#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) -#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) -#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) -#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) -#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) -#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) -#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) -#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) -#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) -#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) -#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) -#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) -#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) -#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) -#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) -#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) -#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) -/** - * @} - */ - -/** @defgroup DMA_Handle_index TIM DMA Handle Index - * @{ - */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ -/** - * @} - */ - -/** @defgroup Channel_CC_State TIM Capture/Compare Channel State - * @{ - */ -#define TIM_CCx_ENABLE ((uint32_t)0x0001) -#define TIM_CCx_DISABLE ((uint32_t)0x0000) -#define TIM_CCxN_ENABLE ((uint32_t)0x0004) -#define TIM_CCxN_DISABLE ((uint32_t)0x0000) -/** - * @} - */ - -/** @defgroup TIM_Break_System TIM Break System - * @{ - */ -#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ -#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ -#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/8/15/16/17 */ -#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */ -/** - * @} - */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup TIM_Exported_Macros TIM Exported Macros - * @{ - */ - -/** @brief Reset TIM handle state. - * @param __HANDLE__ TIM handle. - * @retval None - */ -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) - -/** - * @brief Enable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) - -/** - * @brief Enable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) - -/** - * @brief Disable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ - { \ - (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ - } \ - } \ - } while(0) - -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled - */ -#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ - { \ - (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ - } \ - } \ - } while(0) - -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled unconditionally - */ -#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) - -/** @brief Enable the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to enable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) - - -/** @brief Disable the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to disable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) - -/** @brief Enable the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to enable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) - -/** @brief Disable the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to disable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) - -/** @brief Check whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 6 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag - * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) - -/** @brief Clear the specified TIM interrupt flag. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to clear. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 6 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag - * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** - * @brief Check whether the specified TIM interrupt source is enabled or not. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval The state of TIM_IT (SET or RESET). - */ -#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Clear the TIM interrupt pending bits. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) - -/** - * @brief Indicates whether or not the TIM Counter is used as downcounter. - * @param __HANDLE__ TIM handle. - * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder -mode. - */ -#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) - - -/** - * @brief Set the TIM Prescaler on runtime. - * @param __HANDLE__ TIM handle. - * @param __PRESC__ specifies the Prescaler new value. - * @retval None - */ -#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) - -/** - * @brief Set the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @param __COUNTER__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) - -/** - * @brief Get the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) - */ -#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ - ((__HANDLE__)->Instance->CNT) - -/** - * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __AUTORELOAD__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) - -/** - * @brief Get the TIM Autoreload Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) - */ -#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ - ((__HANDLE__)->Instance->ARR) - -/** - * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __CKD__ specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - * @retval None - */ -#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) - -/** - * @brief Get the TIM Clock Division value on runtime. - * @param __HANDLE__ TIM handle. - * @retval The clock division can be one of the following values: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - */ -#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) - -/** - * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__ specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ - do{ \ - TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) - -/** - * @brief Get the TIM Input Capture prescaler on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get input capture 1 prescaler value - * @arg TIM_CHANNEL_2: get input capture 2 prescaler value - * @arg TIM_CHANNEL_3: get input capture 3 prescaler value - * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval The input capture prescaler can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - */ -#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) - -/** - * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param __COMPARE__ specifies the Capture Compare register new value. - * @retval None - */ -#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) - -/** - * @brief Get the TIM Capture Compare Register value on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channel associated with the capture compare register - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get capture/compare 1 register value - * @arg TIM_CHANNEL_2: get capture/compare 2 register value - * @arg TIM_CHANNEL_3: get capture/compare 3 register value - * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @arg TIM_CHANNEL_5: get capture/compare 5 register value - * @arg TIM_CHANNEL_6: get capture/compare 6 register value - * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) - */ -#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ - ((__HANDLE__)->Instance->CCR6)) - -/** - * @brief Set the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval None - */ -#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) - -/** - * @brief Reset the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval None - */ -#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) - -/** - * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__ TIM handle. - * @note When the USR bit of the TIMx_CR1 register is set, only counter - * overflow/underflow generates an update interrupt or DMA request (if - * enabled) - * @retval None - */ -#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) - -/** - * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__ TIM handle. - * @note When the USR bit of the TIMx_CR1 register is reset, any of the - * following events generate an update interrupt or DMA request (if - * enabled): - * _ Counter overflow underflow - * _ Setting the UG bit - * _ Update generation through the slave mode controller - * @retval None - */ -#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) - -/** - * @brief Set the TIM Capture x input polarity on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__ Polarity for TIx source - * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge - * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge - * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge - * @retval None - */ -#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - do{ \ - TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ - }while(0) - -/** - * @} - */ -/* End of exported macros ----------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup TIM_Private_Constants TIM Private Constants - * @{ - */ -/* The counter of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) -#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) -/** - * @} - */ -/* End of private constants --------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup TIM_Private_Macros TIM Private Macros - * @{ - */ - -#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) - -#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ - ((__BASE__) == TIM_DMABASE_CR2) || \ - ((__BASE__) == TIM_DMABASE_SMCR) || \ - ((__BASE__) == TIM_DMABASE_DIER) || \ - ((__BASE__) == TIM_DMABASE_SR) || \ - ((__BASE__) == TIM_DMABASE_EGR) || \ - ((__BASE__) == TIM_DMABASE_CCMR1) || \ - ((__BASE__) == TIM_DMABASE_CCMR2) || \ - ((__BASE__) == TIM_DMABASE_CCER) || \ - ((__BASE__) == TIM_DMABASE_CNT) || \ - ((__BASE__) == TIM_DMABASE_PSC) || \ - ((__BASE__) == TIM_DMABASE_ARR) || \ - ((__BASE__) == TIM_DMABASE_RCR) || \ - ((__BASE__) == TIM_DMABASE_CCR1) || \ - ((__BASE__) == TIM_DMABASE_CCR2) || \ - ((__BASE__) == TIM_DMABASE_CCR3) || \ - ((__BASE__) == TIM_DMABASE_CCR4) || \ - ((__BASE__) == TIM_DMABASE_BDTR) || \ - ((__BASE__) == TIM_DMABASE_CCMR3) || \ - ((__BASE__) == TIM_DMABASE_CCR5) || \ - ((__BASE__) == TIM_DMABASE_CCR6) || \ - ((__BASE__) == TIM_DMABASE_OR1) || \ - ((__BASE__) == TIM_DMABASE_OR2) || \ - ((__BASE__) == TIM_DMABASE_OR3)) - - -#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - - -#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ - ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) - -#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ - ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ - ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) - -#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ - ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) - -#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ - ((__STATE__) == TIM_OCFAST_ENABLE)) - -#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ - ((__POLARITY__) == TIM_OCPOLARITY_LOW)) - -#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ - ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) - -#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ - ((__STATE__) == TIM_OCIDLESTATE_RESET)) - -#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ - ((__STATE__) == TIM_OCNIDLESTATE_RESET)) - -#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ - ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) - -#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ - ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ - ((__SELECTION__) == TIM_ICSELECTION_TRC)) - -#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV8)) - -#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ - ((__MODE__) == TIM_OPMODE_REPETITIVE)) - -#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ - ((__MODE__) == TIM_ENCODERMODE_TI2) || \ - ((__MODE__) == TIM_ENCODERMODE_TI12)) - -#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - -#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2) || \ - ((__CHANNEL__) == TIM_CHANNEL_3) || \ - ((__CHANNEL__) == TIM_CHANNEL_4) || \ - ((__CHANNEL__) == TIM_CHANNEL_5) || \ - ((__CHANNEL__) == TIM_CHANNEL_6) || \ - ((__CHANNEL__) == TIM_CHANNEL_ALL)) - -#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2)) - -#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2) || \ - ((__CHANNEL__) == TIM_CHANNEL_3)) - -#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) - -#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) - -#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) - -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) - -#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) - -#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) - -#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) - - -#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ - ((__STATE__) == TIM_OSSR_DISABLE)) - -#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ - ((__STATE__) == TIM_OSSI_DISABLE)) - -#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_3)) - -#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xF) - - -#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ - ((__STATE__) == TIM_BREAK_DISABLE)) - -#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) - -#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ - ((__STATE__) == TIM_BREAK2_DISABLE)) - -#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) - -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ - ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) - -#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFF) == 0x00000000)) - -#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ - ((__SOURCE__) == TIM_TRGO_ENABLE) || \ - ((__SOURCE__) == TIM_TRGO_UPDATE) || \ - ((__SOURCE__) == TIM_TRGO_OC1) || \ - ((__SOURCE__) == TIM_TRGO_OC1REF) || \ - ((__SOURCE__) == TIM_TRGO_OC2REF) || \ - ((__SOURCE__) == TIM_TRGO_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO_OC4REF)) - -#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ - ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ - ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ - ((__SOURCE__) == TIM_TRGO2_OC1) || \ - ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ - ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ - ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ - ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) - -#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ - ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) - -#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ - ((__MODE__) == TIM_SLAVEMODE_RESET) || \ - ((__MODE__) == TIM_SLAVEMODE_GATED) || \ - ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ - ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ - ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) - -#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ - ((__MODE__) == TIM_OCMODE_PWM2) || \ - ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ - ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) - -#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ - ((__MODE__) == TIM_OCMODE_ACTIVE) || \ - ((__MODE__) == TIM_OCMODE_INACTIVE) || \ - ((__MODE__) == TIM_OCMODE_TOGGLE) || \ - ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ - ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ - ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ - ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) - -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ETRF)) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_NONE)) - - -#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) - -#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) - -#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) - -#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ - ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) - -#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) - -#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) - -#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF) - -#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) - -#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) - -#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) - -#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12)))) - -#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) - -/** - * @} - */ -/* End of private macros -----------------------------------------------------*/ - -/* Include TIM HAL Extended module */ -#include "stm32l4xx_hal_tim_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions - * @{ - */ -/* Time Base functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions - * @{ - */ -/* Timer Output Compare functions *********************************************/ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions - * @{ - */ -/* Timer PWM functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions - * @{ - */ -/* Timer Input Capture functions **********************************************/ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions - * @{ - */ -/* Timer One Pulse functions **************************************************/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions - * @{ - */ -/* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); - /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * @{ - */ -/* Interrupt Handler functions ***********************************************/ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * @{ - */ -/* Callback in non blocking modes (Interrupt and DMA) *************************/ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions - * @{ - */ -/* Peripheral State functions ************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @defgroup TIM_Private_Functions TIM Private Functions -* @{ -*/ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); - -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); -void TIM_DMAError(DMA_HandleTypeDef *hdma); -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); -/** -* @} -*/ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_TIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h deleted file mode 100644 index eae1c9a32..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h +++ /dev/null @@ -1,484 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_tim_ex.h - * @author MCD Application Team - * @brief Header file of TIM HAL Extended module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_TIM_EX_H -#define __STM32L4xx_HAL_TIM_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIMEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types - * @{ - */ - -/** - * @brief TIM Hall sensor Configuration Structure definition - */ - -typedef struct -{ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ -} TIM_HallSensor_InitTypeDef; - -/** - * @brief TIM Break/Break2 input configuration - */ -typedef struct { - uint32_t Source; /*!< Specifies the source of the timer break input. - This parameter can be a value of @ref TIMEx_Break_Input_Source */ - uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. - This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ - uint32_t Polarity; /*!< Specifies the break input source polarity. - This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity - Not relevant when analog watchdog output of the DFSDM1 used as break input source */ -} TIMEx_BreakInputConfigTypeDef; - -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants - * @{ - */ - -/** @defgroup TIMEx_Remap TIM Extended Remapping - * @{ - */ -#define TIM_TIM1_ETR_ADC1_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD2 */ -#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) -#define TIM_TIM1_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD1 */ -#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1) /* !< TIM1_ETR is connected to ADC3 AWD2 */ -#define TIM_TIM1_ETR_ADC3_AWD3 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0) /* !< TIM1_ETR is connected to ADC3 AWD3 */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ -#define TIM_TIM1_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM1 TI1 is connected to GPIO */ -#define TIM_TIM1_TI1_COMP1 (TIM1_OR1_TI1_RMP) /* !< TIM1 TI1 is connected to COMP1 */ -#define TIM_TIM1_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM1_ETR is connected to GPIO */ -#define TIM_TIM1_ETR_COMP1 (TIM1_OR2_ETRSEL_0) /* !< TIM1_ETR is connected to COMP1 output */ -#define TIM_TIM1_ETR_COMP2 (TIM1_OR2_ETRSEL_1) /* !< TIM1_ETR is connected to COMP2 output */ - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM2_ITR1_TIM8_TRGO ((uint32_t)(0x00000000)) /* !< TIM2_ITR1 is connected to TIM8_TRGO */ -#define TIM_TIM2_ITR1_OTG_FS_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to OTG_FS SOF */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define TIM_TIM2_ITR1_NONE ((uint32_t)(0x00000000)) /* !< No internal trigger on TIM2_ITR1 */ -#define TIM_TIM2_ITR1_USB_SOF (TIM2_OR1_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */ -#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ - /* STM32L451xx || STM32L452xx || STM32L462xx */ -#define TIM_TIM2_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM2_ETR is connected to GPIO */ -#define TIM_TIM2_ETR_LSE (TIM2_OR1_ETR1_RMP) /* !< TIM2_ETR is connected to LSE */ -#define TIM_TIM2_ETR_COMP1 (TIM2_OR2_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 output */ -#define TIM_TIM2_ETR_COMP2 (TIM2_OR2_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 output */ -#define TIM_TIM2_TI4_GPIO ((uint32_t)(0x00000000)) /* !< TIM2 TI4 is connected to GPIO */ -#define TIM_TIM2_TI4_COMP1 (TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to COMP1 output */ -#define TIM_TIM2_TI4_COMP2 (TIM2_OR1_TI4_RMP_1) /* !< TIM2 TI4 is connected to COMP2 output */ -#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0) /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */ - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM3_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM3 TI1 is connected to GPIO */ -#define TIM_TIM3_TI1_COMP1 (TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to COMP1 output */ -#define TIM_TIM3_TI1_COMP2 (TIM3_OR1_TI1_RMP_1) /* !< TIM3 TI1 is connected to COMP2 output */ -#define TIM_TIM3_TI1_COMP1_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0) /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */ -#define TIM_TIM3_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM3_ETR is connected to GPIO */ -#define TIM_TIM3_ETR_COMP1 (TIM3_OR2_ETRSEL_0) /* !< TIM3_ETR is connected to COMP1 output */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) -#define TIM_TIM8_ETR_ADC2_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */ -#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1) /* !< TIM8_ETR is connected to ADC2 AWD2 */ -#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */ -#define TIM_TIM8_ETR_ADC3_NONE ((uint32_t)(0x00000000)) /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/ -#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD1 */ -#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1) /* !< TIM8_ETR is connected to ADC3 AWD2 */ -#define TIM_TIM8_ETR_ADC3_AWD3 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0) /* !< TIM8_ETR is connected to ADC3 AWD3 */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM8_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM8 TI1 is connected to GPIO */ -#define TIM_TIM8_TI1_COMP2 (TIM8_OR1_TI1_RMP) /* !< TIM8 TI1 is connected to COMP1 */ -#define TIM_TIM8_ETR_GPIO ((uint32_t)(0x00000000)) /* !< TIM8_ETR is connected to GPIO */ -#define TIM_TIM8_ETR_COMP1 (TIM8_OR2_ETRSEL_0) /* !< TIM8_ETR is connected to COMP1 output */ -#define TIM_TIM8_ETR_COMP2 (TIM8_OR2_ETRSEL_1) /* !< TIM8_ETR is connected to COMP2 output */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#define TIM_TIM15_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM15 TI1 is connected to GPIO */ -#define TIM_TIM15_TI1_LSE (TIM15_OR1_TI1_RMP) /* !< TIM15 TI1 is connected to LSE */ -#define TIM_TIM15_ENCODERMODE_NONE ((uint32_t)(0x00000000)) /* !< No redirection */ -#define TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0) /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1) /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#define TIM_TIM16_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM16 TI1 is connected to GPIO */ -#define TIM_TIM16_TI1_LSI (TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to LSI */ -#define TIM_TIM16_TI1_LSE (TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to LSE */ -#define TIM_TIM16_TI1_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to RTC wakeup interrupt */ -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) -#define TIM_TIM16_TI1_MSI (TIM16_OR1_TI1_RMP_2) /* !< TIM16 TI1 is connected to MSI */ -#define TIM_TIM16_TI1_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0) /* !< TIM16 TI1 is connected to HSE div 32 */ -#define TIM_TIM16_TI1_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1) /* !< TIM16 TI1 is connected to MCO */ -#endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ - /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L496xx || STM32L4A6xx */ - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_TIM17_TI1_GPIO ((uint32_t)(0x00000000)) /* !< TIM17 TI1 is connected to GPIO */ -#define TIM_TIM17_TI1_MSI (TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MSI */ -#define TIM_TIM17_TI1_HSE_32 (TIM17_OR1_TI1_RMP_1) /* !< TIM17 TI1 is connected to HSE div 32 */ -#define TIM_TIM17_TI1_MCO (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0) /* !< TIM17 TI1 is connected to MCO */ -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input TIM Extended Break input - * @{ - */ -#define TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */ -#define TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source - * @{ - */ -#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */ -#define TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */ -#define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling - * @{ - */ -#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */ -#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity - * @{ - */ -#define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */ -#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */ -/** - * @} - */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros - * @{ - */ - -/** - * @} - */ -/* End of exported macro -----------------------------------------------------*/ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros - * @{ - */ -#define IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F)) - -#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ - ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1)) -#else -#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ - ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) - -#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) -/** - * @} - */ -/* End of private macro ------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions - * @{ - */ - -/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * @{ - */ -/* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); - -void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); - - /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * @{ - */ -/* Timer Complementary Output Compare functions *****************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * @{ - */ -/* Timer Complementary PWM functions ****************************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * @{ - */ -/* Timer Complementary One Pulse functions **********************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Extended Control functions ************************************************/ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); -HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); - -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions - * @brief Extended Callbacks functions - * @{ - */ -/* Extended Callback **********************************************************/ -void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions - * @brief Extended Peripheral State functions - * @{ - */ -/* Extended Peripheral State functions ***************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions -* @{ -*/ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); -/** -* @} -*/ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L4xx_HAL_TIM_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h deleted file mode 100644 index 34e100955..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h +++ /dev/null @@ -1,1638 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_uart.h - * @author MCD Application Team - * @brief Header file of UART HAL module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_UART_H -#define __STM32L4xx_HAL_UART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UART_Exported_Types UART Exported Types - * @{ - */ - -/** - * @brief UART Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate register is computed using the following formula: - UART: - ===== - - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1 - LPUART: - ======= - Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - - where (uart/lpuart)_ker_ck_pres is the UART input clock divided by a prescaler */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UARTEx_Word_Length. */ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits. */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode. */ - - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). - This parameter can be a value of @ref UART_Over_Sampling. */ - - uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ - -#if defined(USART_PRESC_PRESCALER) - uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. - This parameter can be a value of @ref UART_ClockPrescaler. */ -#endif - -}UART_InitTypeDef; - -/** - * @brief UART Advanced Features initalization structure definition - */ -typedef struct -{ - uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several - Advanced Features may be initialized at the same time . - This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */ - - uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. - This parameter can be a value of @ref UART_Tx_Inv. */ - - uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. - This parameter can be a value of @ref UART_Rx_Inv. */ - - uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic - vs negative/inverted logic). - This parameter can be a value of @ref UART_Data_Inv. */ - - uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. - This parameter can be a value of @ref UART_Rx_Tx_Swap. */ - - uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. - This parameter can be a value of @ref UART_Overrun_Disable. */ - - uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. - This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ - - uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. - This parameter can be a value of @ref UART_AutoBaudRate_Enable */ - - uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate - detection is carried out. - This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ - - uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. - This parameter can be a value of @ref UART_MSB_First. */ -} UART_AdvFeatureInitTypeDef; - - - -/** - * @brief HAL UART State structures definition - * @note HAL UART State value is a combination of 2 different substates: gState and RxState. - * - gState contains UART state information related to global Handle management - * and also information related to Tx operations. - * gState value coding follow below described bitmap : - * b7-b6 Error information - * 00 : No Error - * 01 : (Not Used) - * 10 : Timeout - * 11 : Error - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized. HAL UART Init function already called) - * b4-b3 (not used) - * xx : Should be set to 00 - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) - * b1 (not used) - * x : Should be set to 0 - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) - * 1 : Busy (Tx operation ongoing) - * - RxState contains information related to Rx operations. - * RxState value coding follow below described bitmap : - * b7-b6 (not used) - * xx : Should be set to 00 - * b5 IP initilisation status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP not initialized) - * b4-b2 (not used) - * xxx : Should be set to 000 - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 (not used) - * x : Should be set to 0. - */ -typedef enum -{ - HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ - HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ - HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing - Value is allowed for gState only */ - HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing - Value is allowed for gState only */ - HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing - Value is allowed for RxState only */ - HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ - HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state - Value is allowed for gState only */ - HAL_UART_STATE_ERROR = 0xE0U /*!< Error - Value is allowed for gState only */ -}HAL_UART_StateTypeDef; - -/** - * @brief HAL UART Error Code structure definition - */ -typedef enum -{ - HAL_UART_ERROR_NONE = 0x00U, /*!< No error */ - HAL_UART_ERROR_PE = 0x01U, /*!< Parity error */ - HAL_UART_ERROR_NE = 0x02U, /*!< Noise error */ - HAL_UART_ERROR_FE = 0x04U, /*!< frame error */ - HAL_UART_ERROR_ORE = 0x08U, /*!< Overrun error */ - HAL_UART_ERROR_DMA = 0x10U /*!< DMA transfer error */ -}HAL_UART_ErrorTypeDef; - -/** - * @brief UART clock sources definition - */ -typedef enum -{ - UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ - UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ - UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ - UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ - UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ - UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ -}UART_ClockSourceTypeDef; - -/** - * @brief UART handle Structure definition - */ -typedef struct __UART_HandleTypeDef -{ - USART_TypeDef *Instance; /*!< UART registers base address */ - - UART_InitTypeDef Init; /*!< UART communication parameters */ - - UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ - - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< UART Tx Transfer size */ - - __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< UART Rx Transfer size */ - - __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ - - uint16_t Mask; /*!< UART Rx RDR register mask */ - -#if defined(USART_CR1_FIFOEN) - uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ - - uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - - uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. - This parameter can be a value of @ref UARTEx_FIFO_mode. */ -#endif - -#if defined(USART_CR2_SLVEN) - uint32_t SlaveMode; /*!< Specifies if the UART SPI Slave mode is being used. - This parameter can be a value of @ref UARTEx_Slave_Mode. */ -#endif - - void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - - void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ - - DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ - - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ - - __IO uint32_t ErrorCode; /*!< UART Error code */ - -}UART_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UART_Exported_Constants UART Exported Constants - * @{ - */ - -/** @defgroup UART_Stop_Bits UART Number of Stop Bits - * @{ - */ -#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ -#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ -#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ -#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ -/** - * @} - */ - -/** @defgroup UART_Parity UART Parity - * @{ - */ -#define UART_PARITY_NONE 0x00000000U /*!< No parity */ -#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ -#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ -/** - * @} - */ - -/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control - * @{ - */ -#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ -#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ -#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ -#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ -/** - * @} - */ - -/** @defgroup UART_Mode UART Transfer Mode - * @{ - */ -#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ -#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ -#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ -/** - * @} - */ - -/** @defgroup UART_State UART State - * @{ - */ -#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ -#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ -/** - * @} - */ - -/** @defgroup UART_Over_Sampling UART Over Sampling - * @{ - */ -#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - -/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method - * @{ - */ -#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ -#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ -/** - * @} - */ - -#if defined(USART_PRESC_PRESCALER) -/** @defgroup UART_ClockPrescaler UART Clock Prescaler - * @{ - */ -#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ -#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ -#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ -#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ -#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ -#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ -#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ -#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ -#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ -#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ -#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ -#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ -/** - * @} - */ -#endif - -/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode - * @{ - */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */ -/** - * @} - */ - -/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut - * @{ - */ -#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */ -#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */ -/** - * @} - */ - -/** @defgroup UART_LIN UART Local Interconnection Network mode - * @{ - */ -#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ -#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ -/** - * @} - */ - -/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection - * @{ - */ -#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ -#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ -/** - * @} - */ - -/** @defgroup UART_DMA_Tx UART DMA Tx - * @{ - */ -#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ -#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ -/** - * @} - */ - -/** @defgroup UART_DMA_Rx UART DMA Rx - * @{ - */ -#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ -#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ -/** - * @} - */ - -/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection - * @{ - */ -#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ -#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ -/** - * @} - */ - -/** @defgroup UART_WakeUp_Methods UART WakeUp Methods - * @{ - */ -#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ -#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ -/** - * @} - */ - -/** @defgroup UART_Request_Parameters UART Request Parameters - * @{ - */ -#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ -#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ -#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ -#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ -#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ -/** - * @} - */ - -/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type - * @{ - */ -#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ -#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ -#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ -#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ -#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ -#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ -#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ -#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ -#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ -/** - * @} - */ - -/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion - * @{ - */ -#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ -#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion - * @{ - */ -#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ -#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion - * @{ - */ -#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ -#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap - * @{ - */ -#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ -#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ -/** - * @} - */ - -/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable - * @{ - */ -#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ -#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ -/** - * @} - */ - -/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable - * @{ - */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ -/** - * @} - */ - -/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error - * @{ - */ -#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ -#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ -/** - * @} - */ - -/** @defgroup UART_MSB_First UART Advanced Feature MSB First - * @{ - */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ -#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ -/** - * @} - */ - -/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable - * @{ - */ -#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ -#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ -/** - * @} - */ - -/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable - * @{ - */ -#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ -#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ -/** - * @} - */ - -/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register - * @{ - */ -#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ -/** - * @} - */ - -/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection - * @{ - */ -#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ -#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ -#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */ -/** - * @} - */ - -/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity - * @{ - */ -#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ -#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ -/** - * @} - */ - -/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register - * @{ - */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */ -/** - * @} - */ - -/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register - * @{ - */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ -/** - * @} - */ - -/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask - * @{ - */ -#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ -/** - * @} - */ - -/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value - * @{ - */ -#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ -/** - * @} - */ - -/** @defgroup UART_Flags UART Status Flags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the ISR register - * @{ - */ -#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ -#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ -#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ -#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ -#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ -#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ -#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ -#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ -#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ -#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ -#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ -#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ -#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ -#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ -#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ -#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ -#if defined(USART_CR1_FIFOEN) -#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */ -#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ -#else -#define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */ -#endif -#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ -#if defined(USART_CR1_FIFOEN) -#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ -#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ -#else -#define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */ -#endif -#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ -#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ -#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ -#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ -#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ -/** - * @} - */ - -/** @defgroup UART_Interrupt_definition UART Interrupts Definition - * Elements values convention: 000ZZZZZ0XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * - ZZZZZ : Flag position in the ISR register(5bits) - * @{ - */ -#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ -#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ -#if defined(USART_CR1_FIFOEN) -#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ -#endif -#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ -#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ -#if defined(USART_CR1_FIFOEN) -#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ -#endif -#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ -#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ -#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ -#define UART_IT_CM 0x112EU /*!< UART character match interruption */ -#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ -#if defined(USART_CR1_FIFOEN) -#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ -#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ -#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ -#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ -#endif - -/* Elements values convention: 000000000XXYYYYYb - - YYYYY : Interrupt source position in the XX register (5bits) - - XX : Interrupt source register (2bits) - - 01: CR1 register - - 10: CR2 register - - 11: CR3 register */ -#define UART_IT_ERR 0x0060U /*!< UART error interruption */ - -/* Elements values convention: 0000ZZZZ00000000b - - ZZZZ : Flag position in the ISR register(4bits) */ -#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ -#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ -#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ -/** - * @} - */ - -/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags - * @{ - */ -#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ -#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ -#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ -#if defined(USART_CR1_FIFOEN) -#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ -#endif -#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ -#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ -#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ -#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup UART_Exported_Macros UART Exported Macros - * @{ - */ - -/** @brief Reset UART handle states. - * @param __HANDLE__ UART handle. - * @retval None - */ -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - } while(0) -/** @brief Flush the UART Data registers. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ - } while(0) - -/** @brief Clear the specified UART pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag - * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag - * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_CMF Character Match Clear Flag - * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag - * @retval None - */ -#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - -/** @brief Clear the UART PE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) - -/** @brief Clear the UART FE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) - -/** @brief Clear the UART NE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) - -/** @brief Clear the UART ORE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) - -/** @brief Clear the UART IDLE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) - -#if defined(USART_CR1_FIFOEN) -/** @brief Clear the UART TX FIFO empty clear flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) -#endif - -/** @brief Check whether the specified UART flag is set or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag - * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag - * @arg @ref UART_FLAG_RXFF RXFIFO Full flag - * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag - * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag - * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag - * @arg @ref UART_FLAG_WUF Wake up from stop mode flag - * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) - * @arg @ref UART_FLAG_SBKF Send Break flag - * @arg @ref UART_FLAG_CMF Character match flag - * @arg @ref UART_FLAG_BUSY Busy flag - * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag - * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag - * @arg @ref UART_FLAG_CTS CTS Change flag - * @arg @ref UART_FLAG_LBDF LIN Break detection flag - * @arg @ref UART_FLAG_TXE Transmit data register empty flag - * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag - * @arg @ref UART_FLAG_TC Transmission Complete flag - * @arg @ref UART_FLAG_RXNE Receive data register not empty flag - * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag - * @arg @ref UART_FLAG_IDLE Idle Line detection flag - * @arg @ref UART_FLAG_ORE Overrun Error flag - * @arg @ref UART_FLAG_NE Noise Error flag - * @arg @ref UART_FLAG_FE Framing Error flag - * @arg @ref UART_FLAG_PE Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) - -/** @brief Enable the specified UART interrupt. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref UART_IT_RXFF RXFIFO Full interrupt - * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt - * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt - * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) - - -/** @brief Disable the specified UART interrupt. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref UART_IT_RXFF RXFIFO Full interrupt - * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt - * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt - * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) - -/** @brief Check whether the specified UART interrupt has occurred or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt to check. - * This parameter can be one of the following values: - * @arg @ref UART_IT_RXFF RXFIFO Full interrupt - * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt - * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt - * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) - -/** @brief Check whether the specified UART interrupt source is enabled or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref UART_IT_RXFF RXFIFO Full interrupt - * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt - * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt - * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) - -/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set - * to clear the corresponding interrupt - * This parameter can be one of the following values: - * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag - * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag - * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_CMF Character Match Clear Flag - * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag - * @retval None - */ -#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) - -/** @brief Set a specific UART request flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __REQ__ specifies the request flag to set - * This parameter can be one of the following values: - * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request - * @arg @ref UART_SENDBREAK_REQUEST Send Break Request - * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request - * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request - * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request - * @retval None - */ -#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__)) - -/** @brief Enable the UART one bit sample method. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) - -/** @brief Disable the UART one bit sample method. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) - -/** @brief Enable UART. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) - -/** @brief Disable UART. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) - -/** @brief Enable CTS flow control. - * @note This macro allows to enable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ - } while(0) - -/** @brief Disable CTS flow control. - * @note This macro allows to disable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ - } while(0) - -/** @brief Enable RTS flow control. - * @note This macro allows to enable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ - } while(0) - -/** @brief Disable RTS flow control. - * @note This macro allows to disable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ - } while(0) -/** - * @} - */ - -/* Private variables -----------------------------------------------------*/ -#if defined(USART_PRESC_PRESCALER) -/** @defgroup UART_Private_Variables UART Private Variables - * @{ - */ -static const uint16_t UARTPrescTable[12] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256}; -/** - * @} - */ -#endif - -/* Private macros --------------------------------------------------------*/ -/** @defgroup UART_Private_Macros UART Private Macros - * @{ - */ -#if defined(USART_PRESC_PRESCALER) - -/** @brief BRR division operation to set BRR register with LPUART. - * @param __PCLK__ LPUART clock. - * @param __BAUD__ Baud rate set by the user. - * @param __CLOCKPRESCALER__ UART prescaler value. - * @retval Division result - */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((((uint64_t)(__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*256)) + ((__BAUD__)/2)) / (__BAUD__)) - -/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. - * @param __PCLK__ UART clock. - * @param __BAUD__ Baud rate set by the user. - * @param __CLOCKPRESCALER__ UART prescaler value. - * @retval Division result - */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2) + ((__BAUD__)/2)) / (__BAUD__)) - -/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. - * @param __PCLK__ UART clock. - * @param __BAUD__ Baud rate set by the user. - * @param __CLOCKPRESCALER__ UART prescaler value. - * @retval Division result - */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2)) / (__BAUD__)) - -#else - -/** @brief BRR division operation to set BRR register with LPUART. - * @param __PCLK__ LPUART clock. - * @param __BAUD__ Baud rate set by the user. - * @retval Division result - */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__) (((((uint64_t)(__PCLK__)*256)) + ((__BAUD__)/2)) / (__BAUD__)) - -/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. - * @param __PCLK__ UART clock. - * @param __BAUD__ Baud rate set by the user. - * @retval Division result - */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__)) - -/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. - * @param __PCLK__ UART clock. - * @param __BAUD__ Baud rate set by the user. - * @retval Division result - */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__)) - -#endif /* USART_PRESC_PRESCALER */ - -/** @brief Check whether or not UART instance is Low Power UART. - * @param __HANDLE__ specifies the UART Handle. - * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) - */ -#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE(__HANDLE__->Instance)) - -/** @brief Check UART Baud rate. - * @param __BAUDRATE__ Baudrate specified by the user. - * The maximum Baud Rate is derived from the maximum clock on G0 (i.e. 52 MHz) - * divided by the smallest oversampling used on the USART (i.e. 8) - * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) - */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6500001U) - -/** @brief Check UART assertion time. - * @param __TIME__ 5-bit value assertion time. - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) - -/** @brief Check UART deassertion time. - * @param __TIME__ 5-bit value deassertion time. - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) - -/** - * @brief Ensure that UART frame number of stop bits is valid. - * @param __STOPBITS__ UART frame number of stop bits. - * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ -#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ - ((__STOPBITS__) == UART_STOPBITS_1) || \ - ((__STOPBITS__) == UART_STOPBITS_1_5) || \ - ((__STOPBITS__) == UART_STOPBITS_2)) - -/** - * @brief Ensure that LPUART frame number of stop bits is valid. - * @param __STOPBITS__ LPUART frame number of stop bits. - * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ -#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ - ((__STOPBITS__) == UART_STOPBITS_2)) - -/** - * @brief Ensure that UART frame parity is valid. - * @param __PARITY__ UART frame parity. - * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ -#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ - ((__PARITY__) == UART_PARITY_EVEN) || \ - ((__PARITY__) == UART_PARITY_ODD)) - -/** - * @brief Ensure that UART hardware flow control is valid. - * @param __CONTROL__ UART hardware flow control. - * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) - */ -#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ - (((__CONTROL__) == UART_HWCONTROL_NONE) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS) || \ - ((__CONTROL__) == UART_HWCONTROL_CTS) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) - -/** - * @brief Ensure that UART communication mode is valid. - * @param __MODE__ UART communication mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) - -/** - * @brief Ensure that UART state is valid. - * @param __STATE__ UART state. - * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) - */ -#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ - ((__STATE__) == UART_STATE_ENABLE)) - -/** - * @brief Ensure that UART oversampling is valid. - * @param __SAMPLING__ UART oversampling. - * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ -#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ - ((__SAMPLING__) == UART_OVERSAMPLING_8)) - -/** - * @brief Ensure that UART frame sampling is valid. - * @param __ONEBIT__ UART frame sampling. - * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) - */ -#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ - ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) - -/** - * @brief Ensure that UART auto Baud rate detection mode is valid. - * @param __MODE__ UART auto Baud rate detection mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) - -/** - * @brief Ensure that UART receiver timeout setting is valid. - * @param __TIMEOUT__ UART receiver timeout setting. - * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) - */ -#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ - ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) - -/** - * @brief Ensure that UART LIN state is valid. - * @param __LIN__ UART LIN state. - * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) - */ -#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ - ((__LIN__) == UART_LIN_ENABLE)) - -/** - * @brief Ensure that UART LIN break detection length is valid. - * @param __LENGTH__ UART LIN break detection length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ - ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) - -/** - * @brief Ensure that UART DMA TX state is valid. - * @param __DMATX__ UART DMA TX state. - * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) - */ -#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ - ((__DMATX__) == UART_DMA_TX_ENABLE)) - -/** - * @brief Ensure that UART DMA RX state is valid. - * @param __DMARX__ UART DMA RX state. - * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) - */ -#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ - ((__DMARX__) == UART_DMA_RX_ENABLE)) - -/** - * @brief Ensure that UART half-duplex state is valid. - * @param __HDSEL__ UART half-duplex state. - * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) - */ -#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ - ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) - -/** - * @brief Ensure that UART wake-up method is valid. - * @param __WAKEUP__ UART wake-up method . - * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) - */ -#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ - ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) - -/** - * @brief Ensure that UART request parameter is valid. - * @param __PARAM__ UART request parameter. - * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) - */ -#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ - ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ - ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ - ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ - ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) - -/** - * @brief Ensure that UART advanced features initialization is valid. - * @param __INIT__ UART advanced features initialization. - * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) - */ -#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ - UART_ADVFEATURE_TXINVERT_INIT | \ - UART_ADVFEATURE_RXINVERT_INIT | \ - UART_ADVFEATURE_DATAINVERT_INIT | \ - UART_ADVFEATURE_SWAP_INIT | \ - UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ - UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ - UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ - UART_ADVFEATURE_MSBFIRST_INIT)) - -/** - * @brief Ensure that UART frame TX inversion setting is valid. - * @param __TXINV__ UART frame TX inversion setting. - * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ - ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) - -/** - * @brief Ensure that UART frame RX inversion setting is valid. - * @param __RXINV__ UART frame RX inversion setting. - * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ - ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) - -/** - * @brief Ensure that UART frame data inversion setting is valid. - * @param __DATAINV__ UART frame data inversion setting. - * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ - ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) - -/** - * @brief Ensure that UART frame RX/TX pins swap setting is valid. - * @param __SWAP__ UART frame RX/TX pins swap setting. - * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) - */ -#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ - ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) - -/** - * @brief Ensure that UART frame overrun setting is valid. - * @param __OVERRUN__ UART frame overrun setting. - * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) - */ -#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ - ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) - -/** - * @brief Ensure that UART auto Baud rate state is valid. - * @param __AUTOBAUDRATE__ UART auto Baud rate state. - * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) - */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ - ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) - -/** - * @brief Ensure that UART DMA enabling or disabling on error setting is valid. - * @param __DMA__ UART DMA enabling or disabling on error setting. - * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) - */ -#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ - ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) - -/** - * @brief Ensure that UART frame MSB first setting is valid. - * @param __MSBFIRST__ UART frame MSB first setting. - * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) - */ -#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ - ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) - -/** - * @brief Ensure that UART stop mode state is valid. - * @param __STOPMODE__ UART stop mode state. - * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) - */ -#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ - ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) - -/** - * @brief Ensure that UART mute mode state is valid. - * @param __MUTE__ UART mute mode state. - * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) - */ -#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ - ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) - -/** - * @brief Ensure that UART wake-up selection is valid. - * @param __WAKE__ UART wake-up selection. - * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) - */ -#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ - ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ - ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) - -/** - * @brief Ensure that UART driver enable polarity is valid. - * @param __POLARITY__ UART driver enable polarity. - * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) - */ -#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ - ((__POLARITY__) == UART_DE_POLARITY_LOW)) - -#if defined(USART_PRESC_PRESCALER) -/** - * @brief Ensure that UART Prescaler is valid. - * @param __CLOCKPRESCALER__ UART Prescaler value. - * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) - */ -#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) -#endif - -#if defined(USART_CR1_FIFOEN) -/** - * @brief Ensure that UART TXFIFO threshold level is valid. - * @param __THRESHOLD__ UART TXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) - -/** - * @brief Ensure that UART RXFIFO threshold level is valid. - * @param __THRESHOLD__ UART RXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) -#endif - -/** - * @} - */ - -/* Include UART HAL Extended module */ -#include "stm32l4xx_hal_uart_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); -HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart); -void HAL_UART_MspInit(UART_HandleTypeDef *huart); -void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); -/* Transfer Abort functions */ -HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); - -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); -void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart); -void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart); -void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); -void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @{ - */ - -/* Peripheral State and Errors functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions -----------------------------------------------------------*/ -/** @addtogroup UART_Private_Functions UART Private Functions - * @{ - */ - -HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_UART_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h deleted file mode 100644 index 926662f36..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h +++ /dev/null @@ -1,771 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_uart_ex.h - * @author MCD Application Team - * @brief Header file of UART HAL Extended module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_UART_EX_H -#define __STM32L4xx_HAL_UART_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup UARTEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UARTEx_Exported_Types UARTEx Exported Types - * @{ - */ - -/** - * @brief UART wake up from stop mode parameters - */ -typedef struct -{ - uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF). - This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. - If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must - be filled up. */ - - uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. - This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ - - uint8_t Address; /*!< UART/USART node address (7-bit long max). */ -} UART_WakeUpTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants - * @{ - */ - -/** @defgroup UARTEx_Word_Length UARTEx Word Length - * @{ - */ -#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ -/** - * @} - */ - -/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length - * @{ - */ -#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ -/** - * @} - */ - -#if defined(USART_CR2_SLVEN) -/** @defgroup UARTEx_Slave_Select_management UARTEx Slave Select Management - * @{ - */ -#define UART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ -#define UART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ -/** - * @} - */ -#endif - -#if defined(USART_CR1_FIFOEN) -/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level - * @brief UART TXFIFO level - * @{ - */ -#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ -#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ -/** - * @} - */ - -/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level - * @brief UART RXFIFO level - * @{ - */ -#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ -#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ -/** - * @} - */ -#endif - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UARTEx_Exported_Functions - * @{ - */ - -/** @addtogroup UARTEx_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); - -/** - * @} - */ - -/** @addtogroup UARTEx_Exported_Functions_Group2 - * @{ - */ - -/* IO operation functions *****************************************************/ -void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); - -#if defined(USART_CR1_FIFOEN) -void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); -void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); -#endif - -/** - * @} - */ - -/** @addtogroup UARTEx_Exported_Functions_Group3 - * @{ - */ - -/* Peripheral Control functions **********************************************/ -HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); -HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); - -#if defined(USART_CR2_SLVEN) -HAL_StatusTypeDef HAL_UARTEx_EnableSlaveMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_DisableSlaveMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSConfig); -#endif - -#if defined(USART_CR1_FIFOEN) -HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); -HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); -#endif - - -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup UARTEx_Private_Constants UARTEx Private Constants - * @{ - */ -#if defined(USART_CR2_SLVEN) -/** @defgroup UARTEx_Slave_Mode UARTEx Synchronous Slave mode - * @{ - */ -#define UART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ -#define UART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ -/** - * @} - */ -#endif - -#if defined(USART_CR1_FIFOEN) -/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode - * @{ - */ -#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ -/** - * @} - */ -#endif -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup UARTEx_Private_Macros UARTEx Private Macros - * @{ - */ - -/** @brief Report the UART clock source. - * @param __HANDLE__ specifies the UART Handle. - * @param __CLOCKSOURCE__ output variable. - * @retval UART clocking source, written in __CLOCKSOURCE__. - */ -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == UART4) \ - { \ - switch(__HAL_RCC_GET_UART4_SOURCE()) \ - { \ - case RCC_UART4CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART4CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART4CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART4CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == UART5) \ - { \ - switch(__HAL_RCC_GET_UART5_SOURCE()) \ - { \ - case RCC_UART5CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART5CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART5CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART5CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ - case RCC_LPUART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_LPUART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_LPUART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_LPUART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - } while(0) -#elif defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ - case RCC_LPUART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_LPUART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_LPUART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_LPUART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - } while(0) -#elif defined (STM32L432xx) || defined (STM32L442xx) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ - case RCC_LPUART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_LPUART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_LPUART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_LPUART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - } while(0) -#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == UART4) \ - { \ - switch(__HAL_RCC_GET_UART4_SOURCE()) \ - { \ - case RCC_UART4CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART4CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART4CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART4CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ - case RCC_LPUART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_LPUART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_LPUART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_LPUART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - } while(0) -#endif - -/** @brief Report the UART mask to apply to retrieve the received data - * according to the word length and to the parity bits activation. - * @note If PCE = 1, the parity bit is not included in the data extracted - * by the reception API(). - * This masking operation is not carried out in the case of - * DMA transfers. - * @param __HANDLE__: specifies the UART Handle. - * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. - */ -#define UART_MASK_COMPUTATION(__HANDLE__) \ - do { \ - if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x01FF ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x00FF ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x00FF ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x007F ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x007F ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x003F ; \ - } \ - } \ -} while(0) - - -/** - * @brief Ensure that UART frame length is valid. - * @param __LENGTH__ UART frame length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ - ((__LENGTH__) == UART_WORDLENGTH_8B) || \ - ((__LENGTH__) == UART_WORDLENGTH_9B)) - -/** - * @brief Ensure that UART wake-up address length is valid. - * @param __ADDRESS__ UART wake-up address length. - * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) - */ -#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ - ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) - -#if defined(USART_CR2_SLVEN) -/** - * @brief Ensure that UART Negative Slave Select (NSS) pin management is valid. - * @param __NSS__ UART Negative Slave Select pin management. - * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) - */ -#define IS_UART_NSS(__NSS__) (((__NSS__) == UART_NSS_HARD) || \ - ((__NSS__) == UART_NSS_SOFT)) -#endif - -#if defined(USART_CR1_FIFOEN) -/** - * @brief Ensure that UART TXFIFO threshold level is valid. - * @param __THRESHOLD__ UART TXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) - -/** - * @brief Ensure that USART RXFIFO threshold level is valid. - * @param __THRESHOLD__ USART RXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) -#endif - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_UART_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h deleted file mode 100644 index d10baf2e6..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h +++ /dev/null @@ -1,617 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_ll_usb.h - * @author MCD Application Team - * @brief Header file of USB Core HAL module. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_LL_USB_H -#define __STM32L4xx_LL_USB_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal_def.h" - -/** @addtogroup STM32L4xx_HAL - * @{ - */ - -/** @addtogroup USB_Core - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief USB Mode definition - */ -typedef enum -{ - USB_DEVICE_MODE = 0, - USB_HOST_MODE = 1, - USB_DRD_MODE = 2 - -}USB_ModeTypeDef; - -#if defined (USB_OTG_FS) -/** - * @brief URB States definition - */ -typedef enum { - URB_IDLE = 0, - URB_DONE, - URB_NOTREADY, - URB_NYET, - URB_ERROR, - URB_STALL - -}USB_OTG_URBStateTypeDef; - -/** - * @brief Host channel States definition - */ -typedef enum { - HC_IDLE = 0, - HC_XFRC, - HC_HALTED, - HC_NAK, - HC_NYET, - HC_STALL, - HC_XACTERR, - HC_BBLERR, - HC_DATATGLERR - -}USB_OTG_HCStateTypeDef; - -/** - * @brief PCD Initialization Structure definition - */ -typedef struct -{ - uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t Host_channels; /*!< Host Channels number. - This parameter Depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed_ */ - - uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */ - - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. - This parameter can be any value of @ref USB_EP0_MPS_ */ - - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY_ */ - - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - - uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ - - uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ - - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ - - uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ - - uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ - - uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ - -}USB_OTG_CfgTypeDef; - -typedef struct -{ - uint8_t num; /*!< Endpoint number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t is_stall; /*!< Endpoint stall condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type_ */ - - uint8_t data_pid_start; /*!< Initial data PID - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t even_odd_frame; /*!< IFrame parity - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint16_t tx_fifo_num; /*!< Transmission FIFO number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t maxpacket; /*!< Endpoint Max packet size - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ - - uint32_t xfer_len; /*!< Current transfer length */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ - -}USB_OTG_EPTypeDef; - -typedef struct -{ - uint8_t dev_addr ; /*!< USB device address. - This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ - - uint8_t ch_num; /*!< Host channel number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t ep_num; /*!< Endpoint number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t ep_is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t speed; /*!< USB Host speed. - This parameter can be any value of @ref USB_Core_Speed_ */ - - uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ - - uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ - - uint8_t ep_type; /*!< Endpoint Type. - This parameter can be any value of @ref USB_EP_Type_ */ - - uint16_t max_packet; /*!< Endpoint Max packet size. - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t data_pid; /*!< Initial data PID. - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - - uint32_t xfer_len; /*!< Current transfer length. */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ - - uint8_t toggle_in; /*!< IN transfer current toggle flag. - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t toggle_out; /*!< OUT transfer current toggle flag - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ - - uint32_t ErrCnt; /*!< Host channel error count.*/ - - USB_OTG_URBStateTypeDef urb_state; /*!< URB state. - This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ - - USB_OTG_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ - -}USB_OTG_HCTypeDef; -#endif /* USB_OTG_FS */ - -#if defined (USB) -/** - * @brief USB Initialization Structure definition - */ -typedef struct -{ - uint32_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed */ - - uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */ - - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. - This parameter can be any value of @ref USB_EP0_MPS */ - - uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY */ - - uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - - uint32_t low_power_enable; /*!< Enable or disable Low Power mode */ - - uint32_t lpm_enable; /*!< Enable or disable Battery charging. */ - - uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ -} USB_CfgTypeDef; - -typedef struct -{ - uint8_t num; /*!< Endpoint number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t is_stall; /*!< Endpoint stall condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type */ - - uint16_t pmaadress; /*!< PMA Address - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint16_t pmaaddr0; /*!< PMA Address0 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint16_t pmaaddr1; /*!< PMA Address1 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint8_t doublebuffer; /*!< Double buffer enable - This parameter can be 0 or 1 */ - - uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral - This parameter is added to ensure compatibility across USB peripherals */ - - uint32_t maxpacket; /*!< Endpoint Max packet size - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - - uint32_t xfer_len; /*!< Current transfer length */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ - -} USB_EPTypeDef; -#endif /* USB */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PCD_Exported_Constants PCD Exported Constants - * @{ - */ -#if defined (USB_OTG_FS) -/** @defgroup USB_Core_Mode_ USB Core Mode - * @{ - */ -#define USB_OTG_MODE_DEVICE 0 -#define USB_OTG_MODE_HOST 1 -#define USB_OTG_MODE_DRD 2 -/** - * @} - */ - -/** @defgroup USB_Core_Speed_ USB Core Speed - * @{ - */ -#define USB_OTG_SPEED_HIGH 0 -#define USB_OTG_SPEED_HIGH_IN_FULL 1 -#define USB_OTG_SPEED_LOW 2 -#define USB_OTG_SPEED_FULL 3 -/** - * @} - */ - -/** @defgroup USB_Core_PHY_ USB Core PHY - * @{ - */ -#define USB_OTG_EMBEDDED_PHY 1 -/** - * @} - */ - -/** @defgroup USB_Core_MPS_ USB Core MPS - * @{ - */ -#define USB_OTG_FS_MAX_PACKET_SIZE 64 -#define USB_OTG_MAX_EP0_SIZE 64 -/** - * @} - */ - -/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency - * @{ - */ -#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1) -#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1) -#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1) -#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1) -/** - * @} - */ - -/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval - * @{ - */ -#define DCFG_FRAME_INTERVAL_80 0 -#define DCFG_FRAME_INTERVAL_85 1 -#define DCFG_FRAME_INTERVAL_90 2 -#define DCFG_FRAME_INTERVAL_95 3 -/** - * @} - */ - -/** @defgroup USB_EP0_MPS_ USB EP0 MPS - * @{ - */ -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 -/** - * @} - */ - -/** @defgroup USB_EP_Speed_ USB EP Speed - * @{ - */ -#define EP_SPEED_LOW 0 -#define EP_SPEED_FULL 1 -#define EP_SPEED_HIGH 2 -/** - * @} - */ - -/** @defgroup USB_EP_Type_ USB EP Type - * @{ - */ -#define EP_TYPE_CTRL 0 -#define EP_TYPE_ISOC 1 -#define EP_TYPE_BULK 2 -#define EP_TYPE_INTR 3 -#define EP_TYPE_MSK 3 -/** - * @} - */ - -/** @defgroup USB_STS_Defines_ USB STS Defines - * @{ - */ -#define STS_GOUT_NAK 1 -#define STS_DATA_UPDT 2 -#define STS_XFER_COMP 3 -#define STS_SETUP_COMP 4 -#define STS_SETUP_UPDT 6 -/** - * @} - */ - -/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines - * @{ - */ -#define HCFG_30_60_MHZ 0 -#define HCFG_48_MHZ 1 -#define HCFG_6_MHZ 2 -/** - * @} - */ - -/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines - * @{ - */ -#define HPRT0_PRTSPD_HIGH_SPEED 0 -#define HPRT0_PRTSPD_FULL_SPEED 1 -#define HPRT0_PRTSPD_LOW_SPEED 2 -/** - * @} - */ - -#define HCCHAR_CTRL 0 -#define HCCHAR_ISOC 1 -#define HCCHAR_BULK 2 -#define HCCHAR_INTR 3 - -#define HC_PID_DATA0 0 -#define HC_PID_DATA2 1 -#define HC_PID_DATA1 2 -#define HC_PID_SETUP 3 - -#define GRXSTS_PKTSTS_IN 2 -#define GRXSTS_PKTSTS_IN_XFER_COMP 3 -#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 -#define GRXSTS_PKTSTS_CH_HALTED 7 - -#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE) -#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE) - -#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) -#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) -#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE)) -#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE) - -#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE)) -#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE)) - -#endif /* USB_OTG_FS */ - -#if defined (USB) -/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS - * @{ - */ -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 -/** - * @} - */ - -/** @defgroup USB_LL_EP_Type USB Low Layer EP Type - * @{ - */ -#define EP_TYPE_CTRL 0 -#define EP_TYPE_ISOC 1 -#define EP_TYPE_BULK 2 -#define EP_TYPE_INTR 3 -#define EP_TYPE_MSK 3 -/** - * @} - */ - -#define BTABLE_ADDRESS (0x000) -#endif /* USB */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -#if defined (USB_OTG_FS) -#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) -#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) - -#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) -#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) -#endif /* USB_OTG_FS */ - -/* Exported functions --------------------------------------------------------*/ -#if defined (USB_OTG_FS) -HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); -HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init); -HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed); -HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ); -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); -void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup); -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum); -void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); - -HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq); -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state); -uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); -uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num); -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num); -HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); -#endif /* USB_OTG_FS */ - -#if defined (USB) -HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef Init); -HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef Init); -HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx , uint8_t speed); -HAL_StatusTypeDef USB_FlushRxFifo (USB_TypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ); -HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep ,uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len); -void * USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx , USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx); -HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t dma, uint8_t *psetup); -uint32_t USB_ReadInterrupts (USB_TypeDef *USBx); -uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum); -void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt); - -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx); -void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -#endif /* USB */ -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L4xx_LL_USB_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c deleted file mode 100644 index 5e6dae988..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c +++ /dev/null @@ -1,693 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal.c - * @author MCD Application Team - * @brief HAL module driver. - * This is the common part of the HAL initialization - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. - [..] - The HAL contains two APIs' categories: - (+) Common HAL APIs - (+) Services HAL APIs - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL HAL - * @brief HAL module driver - * @{ - */ - -#ifdef HAL_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** - * @brief STM32L4xx HAL Driver version number - */ -#define __STM32L4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L4xx_HAL_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */ -#define __STM32L4xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ -#define __STM32L4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L4xx_HAL_VERSION ((__STM32L4xx_HAL_VERSION_MAIN << 24)\ - |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\ - |(__STM32L4xx_HAL_VERSION_SUB2 << 8 )\ - |(__STM32L4xx_HAL_VERSION_RC)) - -#if defined(VREFBUF) -#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms (to be confirmed) */ -#endif /* VREFBUF */ - -/* ------------ SYSCFG registers bit address in the alias region ------------ */ -#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) -/* --- MEMRMP Register ---*/ -/* Alias word address of FB_MODE bit */ -#define MEMRMP_OFFSET SYSCFG_OFFSET -#define FB_MODE_BitNumber ((uint8_t)0x8) -#define FB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4)) - -/* --- SCSR Register ---*/ -/* Alias word address of SRAM2ER bit */ -#define SCSR_OFFSET (SYSCFG_OFFSET + 0x18) -#define BRER_BitNumber ((uint8_t)0x0) -#define SCSR_SRAM2ER_BB (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (BRER_BitNumber * 4)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -__IO uint32_t uwTick; - -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Functions HAL Exported Functions - * @{ - */ - -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the Flash interface the NVIC allocation and initial time base - clock configuration. - (+) De-initialize common part of the HAL. - (+) Configure the time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) SysTick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and - handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __weak - to make override possible in case of other implementations in user file. -@endverbatim - * @{ - */ - -/** - * @brief Configure the Flash prefetch, the Instruction and Data caches, - * the time base source, NVIC and any required global low level hardware - * by calling the HAL_MspInit() callback function to be optionally defined in user file - * stm32l4xx_hal_msp.c. - * - * @note HAL_Init() function is called at the beginning of program after reset and before - * the clock configuration. - * - * @note In the default implementation the System Timer (Systick) is used as source of time base. - * The Systick configuration is based on MSI clock, as MSI is the clock - * used after a system Reset and the NVIC configuration is set to Priority group 4. - * Once done, time base tick starts incrementing: the tick variable counter is incremented - * each 1ms in the SysTick_Handler() interrupt handler. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_Init(void) -{ - /* Configure Flash prefetch, Instruction cache, Data cache */ - /* Default configuration at reset is: */ - /* - Prefetch disabled */ - /* - Instruction cache enabled */ - /* - Data cache enabled */ -#if (INSTRUCTION_CACHE_ENABLE == 0) - __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); -#endif /* INSTRUCTION_CACHE_ENABLE */ - -#if (DATA_CACHE_ENABLE == 0) - __HAL_FLASH_DATA_CACHE_DISABLE(); -#endif /* DATA_CACHE_ENABLE */ - -#if (PREFETCH_ENABLE != 0) - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); -#endif /* PREFETCH_ENABLE */ - - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - - /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ - HAL_InitTick(TICK_INT_PRIORITY); - - /* Init the low level hardware */ - HAL_MspInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief De-initialize common part of the HAL and stop the source of time base. - * @note This function is optional. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DeInit(void) -{ - /* Reset of all peripherals */ - __HAL_RCC_APB1_FORCE_RESET(); - __HAL_RCC_APB1_RELEASE_RESET(); - - __HAL_RCC_APB2_FORCE_RESET(); - __HAL_RCC_APB2_RELEASE_RESET(); - - __HAL_RCC_AHB1_FORCE_RESET(); - __HAL_RCC_AHB1_RELEASE_RESET(); - - __HAL_RCC_AHB2_FORCE_RESET(); - __HAL_RCC_AHB2_RELEASE_RESET(); - - __HAL_RCC_AHB3_FORCE_RESET(); - __HAL_RCC_AHB3_RELEASE_RESET(); - - /* De-Init the low level hardware */ - HAL_MspDeInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initialize the MSP. - * @retval None - */ -__weak void HAL_MspInit(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the MSP. - * @retval None - */ -__weak void HAL_MspDeInit(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief This function configures the source of the time base: - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The SysTick interrupt must have higher priority (numerically lower) - * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - * The function is declared as __weak to be overwritten in case of other - * implementation in user file. - * @param TickPriority Tick interrupt priority. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(SystemCoreClock/1000); - - /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions - * -@verbatim - =============================================================================== - ##### HAL Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Provide a tick value in millisecond - (+) Provide a blocking delay in millisecond - (+) Suspend the time base source interrupt - (+) Resume the time base source interrupt - (+) Get the HAL API driver version - (+) Get the device identifier - (+) Get the device revision identifier - -@endverbatim - * @{ - */ - -/** - * @brief This function is called to increment a global variable "uwTick" - * used as application time base. - * @note In the default implementation, this variable is incremented each 1ms - * in SysTick ISR. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_IncTick(void) -{ - uwTick++; -} - -/** - * @brief Provide a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t HAL_GetTick(void) -{ - return uwTick; -} - -/** - * @brief This function provides minimum delay (in milliseconds) based - * on variable incremented. - * @note In the default implementation , SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals where uwTick - * is incremented. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void HAL_Delay(uint32_t Delay) -{ - uint32_t tickstart = HAL_GetTick(); - uint32_t wait = Delay; - - /* Add a period to guaranty minimum wait */ - if (wait < HAL_MAX_DELAY) - { - wait++; - } - - while((HAL_GetTick() - tickstart) < wait) - { - } -} - -/** - * @brief Suspend Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the SysTick interrupt will be disabled and so Tick increment - * is suspended. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_SuspendTick(void) -{ - /* Disable SysTick Interrupt */ - SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief Resume Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the SysTick interrupt will be enabled and so Tick increment - * is resumed. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_ResumeTick(void) -{ - /* Enable SysTick Interrupt */ - SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief Return the HAL revision. - * @retval version : 0xXYZR (8bits for each decimal, R for RC) - */ -uint32_t HAL_GetHalVersion(void) -{ - return __STM32L4xx_HAL_VERSION; -} - -/** - * @brief Return the device revision identifier. - * @retval Device revision identifier - */ -uint32_t HAL_GetREVID(void) -{ - return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16); -} - -/** - * @brief Return the device identifier. - * @retval Device identifier - */ -uint32_t HAL_GetDEVID(void) -{ - return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); -} - -/** - * @brief Return the first word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw0(void) -{ - return(READ_REG(*((uint32_t *)UID_BASE))); -} - -/** - * @brief Return the second word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw1(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); -} - -/** - * @brief Return the third word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw2(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions - * @brief HAL Debug functions - * -@verbatim - =============================================================================== - ##### HAL Debug functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Enable/Disable Debug module during SLEEP mode - (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes - (+) Enable/Disable Debug module during STANDBY mode - -@endverbatim - * @{ - */ - -/** - * @brief Enable the Debug Module during SLEEP mode. - * @retval None - */ -void HAL_DBGMCU_EnableDBGSleepMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Disable the Debug Module during SLEEP mode. - * @retval None - */ -void HAL_DBGMCU_DisableDBGSleepMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes. - * @retval None - */ -void HAL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes. - * @retval None - */ -void HAL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode. - * @retval None - */ -void HAL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode. - * @retval None - */ -void HAL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions - * @brief HAL SYSCFG configuration functions - * -@verbatim - =============================================================================== - ##### HAL SYSCFG configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start a hardware SRAM2 erase operation - (+) Enable/Disable the Internal FLASH Bank Swapping - (+) Configure the Voltage reference buffer - (+) Enable/Disable the Voltage reference buffer - (+) Enable/Disable the I/O analog switch voltage booster - -@endverbatim - * @{ - */ - -/** - * @brief Start a hardware SRAM2 erase operation. - * @note As long as SRAM2 is not erased the SRAM2ER bit will be set. - * This bit is automatically reset at the end of the SRAM2 erase operation. - * @retval None - */ -void HAL_SYSCFG_SRAM2Erase(void) -{ - /* unlock the write protection of the SRAM2ER bit */ - SYSCFG->SKR = 0xCA; - SYSCFG->SKR = 0x53; - /* Starts a hardware SRAM2 erase operation*/ - *(__IO uint32_t *) SCSR_SRAM2ER_BB = (uint8_t)0x00000001; -} - -/** - * @brief Enable the Internal FLASH Bank Swapping. - * - * @note This function can be used only for STM32L4xx devices. - * - * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) - * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) - * - * @retval None - */ -void HAL_SYSCFG_EnableMemorySwappingBank(void) -{ - *(__IO uint32_t *)FB_MODE_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disable the Internal FLASH Bank Swapping. - * - * @note This function can be used only for STM32L4xx devices. - * - * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) - * and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) - * - * @retval None - */ -void HAL_SYSCFG_DisableMemorySwappingBank(void) -{ - - *(__IO uint32_t *)FB_MODE_BB = (uint32_t)DISABLE; -} - -#if defined(VREFBUF) -/** - * @brief Configure the internal voltage reference buffer voltage scale. - * @param VoltageScaling specifies the output voltage to achieve - * This parameter can be one of the following values: - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. - * This requires VDDA equal to or higher than 2.4 V. - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V. - * This requires VDDA equal to or higher than 2.8 V. - * @retval None - */ -void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); - - MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); -} - -/** - * @brief Configure the internal voltage reference buffer high impedance mode. - * @param Mode specifies the high impedance mode - * This parameter can be one of the following values: - * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. - * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. - * @retval None - */ -void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); - - MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); -} - -/** - * @brief Tune the Internal Voltage Reference buffer (VREFBUF). - * @retval None - */ -void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); - - MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); -} - -/** - * @brief Enable the Internal Voltage Reference buffer (VREFBUF). - * @retval HAL_OK/HAL_TIMEOUT - */ -HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) -{ - uint32_t tickstart = 0; - - SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait for VRR bit */ - while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == RESET) - { - if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Disable the Internal Voltage Reference buffer (VREFBUF). - * - * @retval None - */ -void HAL_SYSCFG_DisableVREFBUF(void) -{ - CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); -} -#endif /* VREFBUF */ - -/** - * @brief Enable the I/O analog switch voltage booster - * - * @retval None - */ -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) -{ - SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); -} - -/** - * @brief Disable the I/O analog switch voltage booster - * - * @retval None - */ -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) -{ - CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c deleted file mode 100644 index 99afff61e..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c +++ /dev/null @@ -1,539 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_cortex.c - * @author MCD Application Team - * @brief CORTEX HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the CORTEX: - * + Initialization and Configuration functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - - [..] - *** How to configure Interrupts using CORTEX HAL driver *** - =========================================================== - [..] - This section provides functions allowing to configure the NVIC interrupts (IRQ). - The Cortex-M4 exceptions are managed by CMSIS functions. - - (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function. - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). - - -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. - The pending IRQ priority will be managed only by the sub priority. - - -@- IRQ priority order (sorted by highest to lowest priority): - (+@) Lowest pre-emption priority - (+@) Lowest sub priority - (+@) Lowest hardware priority (IRQ number) - - [..] - *** How to configure SysTick using CORTEX HAL driver *** - ======================================================== - [..] - Setup SysTick Timer for time base. - - (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which - is a CMSIS function that: - (++) Configures the SysTick Reload register with value passed as function parameter. - (++) Configures the SysTick IRQ priority to the lowest value (0x0F). - (++) Resets the SysTick Counter register. - (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). - (++) Enables the SysTick Interrupt. - (++) Starts the SysTick Counter. - - (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro - __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the - HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined - inside the stm32l4xx_hal_cortex.h file. - - (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function - call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. - - (+) To adjust the SysTick time base, use the following formula: - - Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) - (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function - (++) Reload Value should not exceed 0xFFFFFF - - @endverbatim - ****************************************************************************** - - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. - - ========================================================================================================================== - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ========================================================================================================================== - NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority - | | | 4 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority - | | | 3 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bit for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bit for subpriority - ========================================================================================================================== - - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @addtogroup CORTEX - * @{ - */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup CORTEX_Exported_Functions - * @{ - */ - - -/** @addtogroup CORTEX_Exported_Functions_Group1 - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and Configuration functions ##### - ============================================================================== - [..] - This section provides the CORTEX HAL driver functions allowing to configure Interrupts - SysTick functionalities - -@endverbatim - * @{ - */ - - -/** - * @brief Set the priority grouping field (pre-emption priority and subpriority) - * using the required unlock sequence. - * @param PriorityGroup: The priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, - * 1 bit for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, - * 0 bit for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ - NVIC_SetPriorityGrouping(PriorityGroup); -} - -/** - * @brief Set the priority of an interrupt. - * @param IRQn: External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @param PreemptPriority: The pre-emption priority for the IRQn channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority - * @param SubPriority: the subpriority level for the IRQ channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority. - * @retval None - */ -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t prioritygroup = 0x00; - - /* Check the parameters */ - assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - - prioritygroup = NVIC_GetPriorityGrouping(); - - NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); -} - -/** - * @brief Enable a device specific interrupt in the NVIC interrupt controller. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @retval None - */ -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Enable interrupt */ - NVIC_EnableIRQ(IRQn); -} - -/** - * @brief Disable a device specific interrupt in the NVIC interrupt controller. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @retval None - */ -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Disable interrupt */ - NVIC_DisableIRQ(IRQn); -} - -/** - * @brief Initiate a system reset request to reset the MCU. - * @retval None - */ -void HAL_NVIC_SystemReset(void) -{ - /* System Reset */ - NVIC_SystemReset(); -} - -/** - * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): - * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. - * @retval status: - 0 Function succeeded. - * - 1 Function failed. - */ -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) -{ - return SysTick_Config(TicksNumb); -} -/** - * @} - */ - -/** @addtogroup CORTEX_Exported_Functions_Group2 - * @brief Cortex control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK, MPU) functionalities. - - -@endverbatim - * @{ - */ - -/** - * @brief Get the priority grouping field from the NVIC Interrupt Controller. - * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) - */ -uint32_t HAL_NVIC_GetPriorityGrouping(void) -{ - /* Get the PRIGROUP[10:8] field value */ - return NVIC_GetPriorityGrouping(); -} - -/** - * @brief Get the priority of an interrupt. - * @param IRQn: External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @param PriorityGroup: the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, - * 1 bit for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, - * 0 bit for subpriority - * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority: Pointer on the Subpriority value (starting from 0). - * @retval None - */ -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - /* Get priority for Cortex-M system or device specific interrupts */ - NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); -} - -/** - * @brief Set Pending bit of an external interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @retval None - */ -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Set interrupt pending */ - NVIC_SetPendingIRQ(IRQn); -} - -/** - * @brief Get Pending Interrupt (read the pending register in the NVIC - * and return the pending bit for the specified interrupt). - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Return 1 if pending else 0 */ - return NVIC_GetPendingIRQ(IRQn); -} - -/** - * @brief Clear the pending bit of an external interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @retval None - */ -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Clear pending interrupt */ - NVIC_ClearPendingIRQ(IRQn); -} - -/** - * @brief Get active interrupt (read the active register in NVIC and return the active bit). - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) -{ - /* Return 1 if active else 0 */ - return NVIC_GetActive(IRQn); -} - -/** - * @brief Configure the SysTick clock source. - * @param CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); - if (CLKSource == SYSTICK_CLKSOURCE_HCLK) - { - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - } - else - { - SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; - } -} - -/** - * @brief Handle SYSTICK interrupt request. - * @retval None - */ -void HAL_SYSTICK_IRQHandler(void) -{ - HAL_SYSTICK_Callback(); -} - -/** - * @brief SYSTICK callback. - * @retval None - */ -__weak void HAL_SYSTICK_Callback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SYSTICK_Callback could be implemented in the user file - */ -} - -#if (__MPU_PRESENT == 1) -/** - * @brief Disable the MPU. - * @retval None - */ -void HAL_MPU_Disable(void) -{ - /* Make sure outstanding transfers are done */ - __DMB(); - - /* Disable fault exceptions */ - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - - /* Disable the MPU and clear the control register*/ - MPU->CTRL = 0U; -} - -/** - * @brief Enable the MPU. - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged accessto the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -void HAL_MPU_Enable(uint32_t MPU_Control) -{ - /* Enable the MPU */ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - - /* Enable fault exceptions */ - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; - - /* Ensure MPU settings take effects */ - __DSB(); - __ISB(); -} - -/** - * @brief Initialize and configure the Region and the memory to be protected. - * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains - * the initialization and configuration information. - * @retval None - */ -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) -{ - /* Check the parameters */ - assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); - assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); - - /* Set the Region number */ - MPU->RNR = MPU_Init->Number; - - if ((MPU_Init->Enable) != RESET) - { - /* Check the parameters */ - assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); - assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); - assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); - assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); - assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); - assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); - assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); - - MPU->RBAR = MPU_Init->BaseAddress; - MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | - ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | - ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | - ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | - ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | - ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | - ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | - ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | - ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); - } - else - { - MPU->RBAR = 0x00; - MPU->RASR = 0x00; - } -} -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CORTEX_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c deleted file mode 100644 index 9963ae866..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c +++ /dev/null @@ -1,1179 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_dma.c - * @author MCD Application Team - * @brief DMA HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access (DMA) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and errors functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable and configure the peripheral to be connected to the DMA Channel - (except for internal SRAM / FLASH memories: no initialization is - necessary). Please refer to the Reference manual for connection between peripherals - and DMA requests. - - (#) For a given Channel, program the required configuration through the following parameters: - Channel request, Transfer Direction, Source and Destination data formats, - Circular or Normal mode, Channel Priority level, Source and Destination Increment mode - using HAL_DMA_Init() function. - - Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX - thanks to: - (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ; - (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); - - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error - detection. - - (#) Use HAL_DMA_Abort() function to abort the current transfer - - -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. - - *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source - address and destination address and the Length of data to be transferred - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this - case a fixed Timeout can be configured by User depending from his application. - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. - In this case the DMA interrupt is configured - (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function to register callbacks with HAL_DMA_RegisterCallback(). - - *** DMA HAL driver macros list *** - ============================================= - [..] - Below the list of macros in DMA HAL driver. - - (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. - (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. - (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. - (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. - (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. - (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not. - - [..] - (@) You can refer to the DMA HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup DMA DMA - * @brief DMA HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup DMA_Private_Functions DMA Private Functions - * @{ - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -#if defined(DMAMUX1) -static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); -static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); -#endif /* DMAMUX1 */ - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize the DMA Channel source - and destination addresses, incrementation and data sizes, transfer direction, - circular/normal mode selection, memory-to-memory mode selection and Channel priority value. - [..] - The HAL_DMA_Init() function follows the DMA configuration procedures as described in - reference manual. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DMA according to the specified - * parameters in the DMA_InitTypeDef and initialize the associated handle. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ - uint32_t tmp = 0; - - /* Check the DMA handle allocation */ - if(hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); - assert_param(IS_DMA_MODE(hdma->Init.Mode)); - assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - - assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); - - /* Compute the channel index */ - if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) - { - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; - hdma->DmaBaseAddress = DMA1; - } - else - { - /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; - hdma->DmaBaseAddress = DMA2; - } - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Get the CR register value */ - tmp = hdma->Instance->CCR; - - /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ - tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | - DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | - DMA_CCR_DIR | DMA_CCR_MEM2MEM)); - - /* Prepare the DMA Channel configuration */ - tmp |= hdma->Init.Direction | - hdma->Init.PeriphInc | hdma->Init.MemInc | - hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - hdma->Init.Mode | hdma->Init.Priority; - - /* Write to DMA Channel CR register */ - hdma->Instance->CCR = tmp; - - -#if defined(DMAMUX1) - /* Initialize parameters for DMAMUX channel : - DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask - */ - DMA_CalcDMAMUXChannelBaseAndMask(hdma); - - if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) - { - /* if memory to memory force the request to 0*/ - hdma->Init.Request = DMA_REQUEST_MEM2MEM; - } - - /* Set peripheral request to DMAMUX channel */ - hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); - - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) - { - /* Initialize parameters for DMAMUX request generator : - DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask - */ - DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); - - /* Reset the DMAMUX request generator register*/ - hdma->DMAmuxRequestGen->RGCR = 0U; - - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - } - else - { - hdma->DMAmuxRequestGen = 0U; - hdma->DMAmuxRequestGenStatus = 0U; - hdma->DMAmuxRequestGenStatusMask = 0U; - } -#endif /* DMAMUX1 */ - -#if !defined (DMAMUX1) - - /* Set request selection */ - if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) - { - /* Write to DMA channel selection register */ - if (DMA1 == hdma->DmaBaseAddress) - { - /* Reset request selection for DMA1 Channelx */ - DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex); - - /* Configure request selection for DMA1 Channelx */ - DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); - } - else /* DMA2 */ - { - /* Reset request selection for DMA2 Channelx */ - DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << hdma->ChannelIndex); - - /* Configure request selection for DMA2 Channelx */ - DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex)); - } - } - -#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ - - /* Clean callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - - /* Initialise the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - - /* Allocate lock resource and initialize it */ - hdma->Lock = HAL_UNLOCKED; - - return HAL_OK; -} - -/** - * @brief DeInitialize the DMA peripheral. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) -{ - - /* Check the DMA handle allocation */ - if (NULL == hdma ) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - /* Disable the selected DMA Channelx */ - __HAL_DMA_DISABLE(hdma); - - /* Compute the channel index */ - if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) - { - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; - hdma->DmaBaseAddress = DMA1; - } - else - { - /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; - hdma->DmaBaseAddress = DMA2; - } - - /* Reset DMA Channel control register */ - hdma->Instance->CCR = 0; - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); - -#if !defined (DMAMUX1) - - /* Reset DMA channel selection register */ - if (DMA1 == hdma->DmaBaseAddress) - { - /* DMA1 */ - DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); - } - else - { - /* DMA2 */ - DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex)); - } -#endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ - /* STM32L496xx || STM32L4A6xx */ - -#if defined(DMAMUX1) - - /* Initialize parameters for DMAMUX channel : - DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ - - DMA_CalcDMAMUXChannelBaseAndMask(hdma); - - /* Reset the DMAMUX channel that corresponds to the DMA channel */ - hdma->DMAmuxChannel->CCR = 0; - - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - /* Reset Request generator parameters if any */ - if(((hdma->Init.Request > 0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) - { - /* Initialize parameters for DMAMUX request generator : - DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask - */ - DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); - - /* Reset the DMAMUX request generator register*/ - hdma->DMAmuxRequestGen->RGCR = 0U; - - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - } - - hdma->DMAmuxRequestGen = 0U; - hdma->DMAmuxRequestGenStatus = 0U; - hdma->DMAmuxRequestGenStatusMask = 0U; - -#endif /* DMAMUX1 */ - - /* Initialise the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state */ - hdma->State = HAL_DMA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions - * @brief Input and Output operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the source, destination address and data length and Start DMA transfer - (+) Configure the source, destination address and data length and - Start DMA transfer with interrupt - (+) Abort DMA transfer - (+) Poll for transfer complete - (+) Handle DMA interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Start the DMA Transfer. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Configure the source, destination address and the data length & clear flags*/ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - status = HAL_BUSY; - } - return status; -} - -/** - * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Configure the source, destination address and the data length & clear flags*/ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the transfer complete interrupt */ - /* Enable the transfer Error interrupt */ - if(NULL != hdma->XferHalfCpltCallback ) - { - /* Enable the Half transfer complete interrupt as well */ - __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - } - else - { - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); - } - -#ifdef DMAMUX1 - - /* Check if DMAMUX Synchronization is enabled*/ - if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) - { - /* Enable DMAMUX sync overrun IT*/ - hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; - } - - if(hdma->DMAmuxRequestGen != 0U) - { - /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ - /* enable the request gen overrun IT*/ - hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; - } - -#endif /* DMAMUX1 */ - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Remain BUSY */ - status = HAL_BUSY; - } - return status; -} - -/** - * @brief Abort the DMA Transfer. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the DMA peripheral handle */ - if(NULL == hdma) - { - return HAL_ERROR; - } - - /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - -#if defined(DMAMUX1) - /* disable the DMAMUX sync overrun IT*/ - hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; -#endif /* DMAMUX1 */ - - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - -#if defined(DMAMUX1) - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - if(hdma->DMAmuxRequestGen != 0U) - { - /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ - /* disable the request gen overrun IT*/ - hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; - - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - } - -#endif /* DMAMUX1 */ - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @brief Aborts the DMA Transfer in Interrupt mode. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(HAL_DMA_STATE_BUSY != hdma->State) - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - status = HAL_ERROR; - } - else - { - /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - -#if defined(DMAMUX1) - /* disable the DMAMUX sync overrun IT*/ - hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - if(hdma->DMAmuxRequestGen != 0U) - { - /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ - /* disable the request gen overrun IT*/ - hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; - - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - } - -#else - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); -#endif /* DMAMUX1 */ - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Call User Abort callback */ - if(hdma->XferAbortCallback != NULL) - { - hdma->XferAbortCallback(hdma); - } - } - return status; -} - -/** - * @brief Polling for transfer complete. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CompleteLevel: Specifies the DMA level complete. - * @param Timeout: Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) -{ - uint32_t temp; - uint32_t tickstart = 0; - - if(HAL_DMA_STATE_BUSY != hdma->State) - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - __HAL_UNLOCK(hdma); - return HAL_ERROR; - } - - /* Polling mode not supported in circular mode */ - if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - return HAL_ERROR; - } - - /* Get the level transfer complete flag */ - if (HAL_DMA_FULL_TRANSFER == CompleteLevel) - { - /* Transfer Complete flag */ - temp = DMA_FLAG_TC1 << hdma->ChannelIndex; - } - else - { - /* Half Transfer Complete flag */ - temp = DMA_FLAG_HT1 << hdma->ChannelIndex; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(RESET == (hdma->DmaBaseAddress->ISR & temp)) - { - if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))) - { - /* When a DMA transfer error occurs */ - /* A hardware clear of its EN bits is performed */ - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TE; - - /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - } - } - -#if defined(DMAMUX1) - /*Check for DMAMUX Request generator (if used) overrun status */ - if(hdma->DMAmuxRequestGen != 0U) - { - /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ - if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) - { - /* Disable the request gen overrun interrupt */ - hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; - - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; - } - } - - /* Check for DMAMUX Synchronization overrun */ - if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) - { - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; - } -#endif /* DMAMUX1 */ - - if(HAL_DMA_FULL_TRANSFER == CompleteLevel) - { - /* Clear the transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex); - - /* The selected Channelx EN bit is cleared (DMA is disabled and - all transfers are complete) */ - hdma->State = HAL_DMA_STATE_READY; - } - else - { - /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex); - } - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @brief Handle DMA interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval None - */ -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) -{ - uint32_t flag_it = hdma->DmaBaseAddress->ISR; - uint32_t source_it = hdma->Instance->CCR; - - /* Half Transfer Complete Interrupt management ******************************/ - if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT))) - { - /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - /* Disable the half transfer interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - } - /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << hdma->ChannelIndex); - - /* DMA peripheral state is not updated in Half Transfer */ - /* but in Transfer Complete case */ - - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } - } - - /* Transfer Complete Interrupt management ***********************************/ - else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC))) - { - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - /* Disable the transfer complete and error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - } - /* Clear the transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << hdma->ChannelIndex); - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete callback */ - hdma->XferCpltCallback(hdma); - } - } - - /* Transfer Error Interrupt management **************************************/ - else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) - { - /* When a DMA transfer error occurs */ - /* A hardware clear of its EN bits is performed */ - /* Disable ALL DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TE; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if (hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } - return; -} - -/** - * @brief Register callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CallbackID: User Callback identifer - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback: pointer to private callbacsk function which has pointer to - * a DMA_HandleTypeDef structure as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = pCallback; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = pCallback; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @brief UnRegister callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CallbackID: User Callback identifer - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = NULL; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = NULL; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = NULL; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = NULL; - break; - - case HAL_DMA_XFER_ALL_CB_ID: - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @} - */ - - - -/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DMA state - (+) Get error code - -@endverbatim - * @{ - */ - -/** - * @brief Return the DMA hande state. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL state - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) -{ - /* Return DMA handle state */ - return hdma->State; -} - -/** - * @brief Return the DMA error code. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval DMA Error Code - */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) -{ - return hdma->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Sets the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ -#if defined(DMAMUX1) - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - if(hdma->DMAmuxRequestGen != 0U) - { - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - } -#endif - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - - /* Configure DMA Channel data length */ - hdma->Instance->CNDTR = DataLength; - - /* Peripheral to Memory */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Channel destination address */ - hdma->Instance->CPAR = DstAddress; - - /* Configure DMA Channel source address */ - hdma->Instance->CMAR = SrcAddress; - } - /* Memory to Peripheral */ - else - { - /* Configure DMA Channel source address */ - hdma->Instance->CPAR = SrcAddress; - - /* Configure DMA Channel destination address */ - hdma->Instance->CMAR = DstAddress; - } -} - -#if defined(DMAMUX1) - -/** - * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ -static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) -{ - uint32_t channel_number = 0; - DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase; - - /* check if instance is not outside the DMA channel range */ - if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) - { - /* DMA1 */ - DMAMUX1_ChannelBase = DMAMUX1_Channel0; - } - else - { - /* DMA2 */ - DMAMUX1_ChannelBase = DMAMUX1_Channel7; - } - channel_number = (((uint32_t)hdma->Instance & 0xFF) - 8) / 20; - hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_ChannelBase + (hdma->ChannelIndex >> 2) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)); - hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; - hdma->DMAmuxChannelStatusMask = 1U << channel_number; -} - -/** - * @brief Updates the DMA handle with the DMAMUX request generator params - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ - -static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) -{ - uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; - - /* DMA Channels are connected to DMAMUX1 request generator blocks*/ - hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); - - hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; - - hdma->DMAmuxRequestGenStatusMask = 1U << (request - 1U); -} - -#endif /* DMAMUX1 */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_DMA_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c deleted file mode 100644 index 50b09d590..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c +++ /dev/null @@ -1,319 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_dma_ex.c - * @author MCD Application Team - * @brief DMA Extension HAL module driver - * This file provides firmware functions to manage the following - * functionalities of the DMA Extension peripheral: - * + Extended features functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The DMA Extension HAL driver can be used as follows: - - (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. - (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. - Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used - to respectively enable/disable the request generator. - - (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from - the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler. - As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be - called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project - (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -#if defined(DMAMUX1) - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup DMAEx DMAEx - * @brief DMA Extended HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private Constants ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions - * @{ - */ - -/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - - (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. - (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. - Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used - to respectively enable/disable the request generator. - -@endverbatim - * @{ - */ - - -/** - * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance). - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. - * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); - - assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity)); - assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); - assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); - assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); - - /*Check if the DMA state is ready */ - if(hdma->State == HAL_DMA_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hdma); - - /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ - MODIFY_REG( hdma->DMAmuxChannel->CCR, \ - (~DMAMUX_CxCR_DMAREQ_ID) , \ - ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ - pSyncConfig->SyncPolarity | (pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ - (pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); - - /* Process UnLocked */ - __HAL_UNLOCK(hdma); - - return HAL_OK; - } - else - { - /*DMA State not Ready*/ - return HAL_ERROR; - } -} - -/** - * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. - * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : - * contains the request generator parameters. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); - - assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); - assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); - - /* check if the DMA state is ready - and DMA is using a DMAMUX request generator block - */ - if((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U)) - { - /* Process Locked */ - __HAL_LOCK(hdma); - - /* Set the request generator new parameters*/ - hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ - ((pRequestGeneratorConfig->RequestNumber - 1U) << POSITION_VAL(DMAMUX_RGxCR_GNBREQ))| \ - pRequestGeneratorConfig->Polarity; - /* Process UnLocked */ - __HAL_UNLOCK(hdma); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance). - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - /* check if the DMA state is ready - and DMA is using a DMAMUX request generator block - */ - if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) - { - - /* Enable the request generator*/ - hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance). - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - /* check if the DMA state is ready - and DMA is using a DMAMUX request generator block - */ - if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) - { - - /* Disable the request generator*/ - hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Handles DMAMUX interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA channel. - * @retval None - */ -void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) -{ - /* Check for DMAMUX Synchronization overrun */ - if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) - { - /* Disable the synchro overrun interrupt */ - hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; - - /* Clear the DMAMUX synchro overrun flag */ - hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } - - if(hdma->DMAmuxRequestGen != 0) - { - /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ - if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) - { - /* Disable the request gen overrun interrupt */ - hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; - - /* Clear the DMAMUX request generator overrun flag */ - hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } - } -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DMAMUX1 */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c deleted file mode 100644 index ec118ec83..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c +++ /dev/null @@ -1,835 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_flash.c - * @author MCD Application Team - * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the internal FLASH memory: - * + Program operations functions - * + Memory Control functions - * + Peripheral Errors functions - * - @verbatim - ============================================================================== - ##### FLASH peripheral features ##### - ============================================================================== - - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses - to the Flash memory. It implements the erase and program Flash memory operations - and the read and write protection mechanisms. - - [..] The Flash memory interface accelerates code execution with a system of instruction - prefetch and cache lines. - - [..] The FLASH main features are: - (+) Flash memory read operations - (+) Flash memory program/erase operations - (+) Read / write protections - (+) Option bytes programming - (+) Prefetch on I-Code - (+) 32 cache lines of 4*64 bits on I-Code - (+) 8 cache lines of 4*64 bits on D-Code - (+) Error code correction (ECC) : Data in flash are 72-bits word - (8 bits added per double word) - - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH - memory of all STM32L4xx devices. - - (#) Flash Memory IO Programming functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and - HAL_FLASH_Lock() functions - (++) Program functions: double word and fast program (full row programming) - (++) There Two modes of programming : - (+++) Polling mode using HAL_FLASH_Program() function - (+++) Interrupt mode using HAL_FLASH_Program_IT() function - - (#) Interrupts and flags management functions : - (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() - (++) Callback functions are called when the flash operations are finished : - HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise - HAL_FLASH_OperationErrorCallback() - (++) Get error flag status by calling HAL_GetError() - - (#) Option bytes management functions : - (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and - HAL_FLASH_OB_Lock() functions - (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function. - In this case, a reset is generated - - [..] - In addition to these functions, this driver includes a set of macros allowing - to handle the following operations: - (+) Set the latency - (+) Enable/Disable the prefetch buffer - (+) Enable/Disable the Instruction cache and the Data cache - (+) Reset the Instruction cache and the Data cache - (+) Enable/Disable the Flash power-down during low-power run and sleep modes - (+) Enable/Disable the Flash interrupts - (+) Monitor the Flash flags status - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASH FLASH - * @brief FLASH HAL module driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define FLASH_NB_DOUBLE_WORDS_IN_ROW 64 -#else -#define FLASH_NB_DOUBLE_WORDS_IN_ROW 32 -#endif -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Variables FLASH Private Variables - * @{ - */ -/** - * @brief Variable used for Program/Erase sectors under interruption - */ -FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASH_Private_Functions FLASH Private Functions - * @{ - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -extern void FLASH_PageErase(uint32_t Page, uint32_t Banks); -extern void FLASH_FlushCaches(void); -static void FLASH_SetErrorCode(void); -static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); -static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Functions FLASH Exported Functions - * @{ - */ - -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions - * -@verbatim - =============================================================================== - ##### Programming operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the FLASH - program operations. - -@endverbatim - * @{ - */ - -/** - * @brief Program double word or fast program of a row at a specified address. - * @param TypeProgram: Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed - * This parameter is the data for the double word program and the address where - * are stored the data for the row fast program - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t prog_bit = 0; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Deactivate the data cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; - } - else - { - pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; - } - - if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) - { - /* Program double-word (64-bit) at a specified address */ - FLASH_Program_DoubleWord(Address, Data); - prog_bit = FLASH_CR_PG; - } - else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)) - { - /* Fast program a 32 row double-word (64-bit) at a specified address */ - FLASH_Program_Fast(Address, (uint32_t)Data); - - /* If it is the last row, the bit will be cleared at the end of the operation */ - if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST) - { - prog_bit = FLASH_CR_FSTPG; - } - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the program operation is completed, disable the PG or FSTPG Bit */ - if (prog_bit != 0) - { - CLEAR_BIT(FLASH->CR, prog_bit); - } - - /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches(); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Program double word or fast program of a row at a specified address with interrupt enabled. - * @param TypeProgram: Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed - * This parameter is the data for the double word program and the address where - * are stored the data for the row fast program - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Deactivate the data cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; - } - else - { - pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; - } - - /* Set internal variables used by the IRQ handler */ - if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST) - { - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST; - } - else - { - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; - } - pFlash.Address = Address; - - /* Enable End of Operation and Error interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); - - if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) - { - /* Program double-word (64-bit) at a specified address */ - FLASH_Program_DoubleWord(Address, Data); - } - else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)) - { - /* Fast program a 32 row double-word (64-bit) at a specified address */ - FLASH_Program_Fast(Address, (uint32_t)Data); - } - - return status; -} - -/** - * @brief Handle FLASH interrupt request. - * @retval None - */ -void HAL_FLASH_IRQHandler(void) -{ - uint32_t tmp_page; - - /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB)); -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - CLEAR_BIT(FLASH->CR, FLASH_CR_MER2); -#endif - - /* Disable the FSTPG Bit only if it is the last row programmed */ - if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST) - { - CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG); - } - - /* Check FLASH operation error flags */ - if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) || -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))) -#else - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))) -#endif - { - /*Save the error code*/ - FLASH_SetErrorCode(); - - /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches() ; - - /* FLASH error interrupt user callback */ - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE) - { - HAL_FLASH_OperationErrorCallback(pFlash.Page); - } - else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE) - { - HAL_FLASH_OperationErrorCallback(pFlash.Bank); - } - else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) || - (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)) - { - HAL_FLASH_OperationErrorCallback(pFlash.Address); - } - - /*Stop the procedure ongoing*/ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - - /* Check FLASH End of Operation flag */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE) - { - /* Nb of pages to erased can be decreased */ - pFlash.NbPagesToErase--; - - /* Check if there are still pages to erase*/ - if(pFlash.NbPagesToErase != 0) - { - /* Indicate user which page has been erased*/ - HAL_FLASH_EndOfOperationCallback(pFlash.Page); - - /* Increment page number */ - pFlash.Page++; - tmp_page = pFlash.Page; - FLASH_PageErase(tmp_page, pFlash.Bank); - } - else - { - /* No more pages to Erase */ - /* Reset Address and stop Erase pages procedure */ - pFlash.Page = 0xFFFFFFFF; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - - /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches() ; - - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(pFlash.Page); - } - } - else - { - /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches() ; - - if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE) - { - /* MassErase ended. Return the selected bank */ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(pFlash.Bank); - } - else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) || - (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)) - { - /* Program ended. Return the selected address */ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(pFlash.Address); - } - - /*Clear the procedure ongoing*/ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - } - - if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) - { - /* Disable End of Operation and Error interrupts */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - } -} - -/** - * @brief FLASH end of operation interrupt callback. - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * Mass Erase: Bank number which has been requested to erase - * Page Erase: Page which has been erased - * (if 0xFFFFFFFF, it means that all the selected pages have been erased) - * Program: Address which was selected for data program - * @retval None - */ -__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ -} - -/** - * @brief FLASH operation error interrupt callback. - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * Mass Erase: Bank number which has been requested to erase - * Page Erase: Page number which returned an error - * Program: Address which was selected for data program - * @retval None - */ -__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief Management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the FLASH - memory operations. - -@endverbatim - * @{ - */ - -/** - * @brief Unlock the FLASH control register access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) - { - /* Authorize the FLASH Registers access */ - WRITE_REG(FLASH->KEYR, FLASH_KEY1); - WRITE_REG(FLASH->KEYR, FLASH_KEY2); - - /* Verify Flash is unlocked */ - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) - { - status = HAL_ERROR; - } - } - - return status; -} - -/** - * @brief Lock the FLASH control register access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - SET_BIT(FLASH->CR, FLASH_CR_LOCK); - - return HAL_OK; -} - -/** - * @brief Unlock the FLASH Option Bytes Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) -{ - if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != RESET) - { - /* Authorizes the Option Byte register programming */ - WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); - WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Lock the FLASH Option Bytes Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ - SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK); - - return HAL_OK; -} - -/** - * @brief Launch the option byte loading. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) -{ - /* Set the bit to force the option byte reloading */ - SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); - - /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time Errors of the FLASH peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Get the specific FLASH error flag. - * @retval FLASH_ErrorCode: The returned value can be: - * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) - * @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag - * @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag - * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag - * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag - * @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag - * @arg HAL_FLASH_ERROR_NONE: No error set - * @arg HAL_FLASH_ERROR_OP: FLASH Operation error - * @arg HAL_FLASH_ERROR_PROG: FLASH Programming error - * @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error - * @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error - * @arg HAL_FLASH_ERROR_SIZ: FLASH Size error - * @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error - * @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error - * @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error - * @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error - * @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error - * @arg FLASH_FLAG_PEMPTY : FLASH Boot from not programmed flash (apply only for STM32L43x/STM32L44x devices) - * @arg HAL_FLASH_ERROR_ECCD: FLASH two ECC errors have been detected - */ -uint32_t HAL_FLASH_GetError(void) -{ - return pFlash.ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** @addtogroup FLASH_Private_Functions - * @{ - */ - -/** - * @brief Wait for a FLASH operation to complete. - * @param Timeout: maximum flash operation timeout - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) -{ - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) - { - if(Timeout != HAL_MAX_DELAY) - { - if((HAL_GetTick() - tickstart) >= Timeout) - { - return HAL_TIMEOUT; - } - } - } - - if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) || -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY))) -#else - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))) -#endif - { - /*Save the error code*/ - FLASH_SetErrorCode(); - - return HAL_ERROR; - } - - /* Check FLASH End of Operation flag */ - if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - - /* If there is an error flag set */ - return HAL_OK; -} - -/** - * @brief Set the specific FLASH error flag. - * @retval None - */ -static void FLASH_SetErrorCode(void) -{ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OP; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZ; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_MIS; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_FAST; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_ECCD; - } - -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ - defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PEMPTY)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PEMPTY; - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PEMPTY); - } -#endif - - /* Clear error programming flags */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); -} - -/** - * @brief Program double-word (64-bit) at a specified address. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval None - */ -static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) -{ - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Set PG bit */ - SET_BIT(FLASH->CR, FLASH_CR_PG); - - /* Program the double word */ - *(__IO uint32_t*)Address = (uint32_t)Data; - *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); -} - -/** - * @brief Fast program a row double-word (64-bit) at a specified address. - * @param Address: specifies the address to be programmed. - * @param DataAddress: specifies the address where the data are stored. - * @retval None - */ -static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) -{ - uint8_t row_index = (2*FLASH_NB_DOUBLE_WORDS_IN_ROW); - __IO uint32_t *dest_addr = (__IO uint32_t*)Address; - __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress; - - /* Check the parameters */ - assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address)); - - /* Set FSTPG bit */ - SET_BIT(FLASH->CR, FLASH_CR_FSTPG); - - /* Disable interrupts to avoid any interruption during the loop */ - __disable_irq(); - - /* Program the double word of the row */ - do - { - *dest_addr++ = *src_addr++; - } while (--row_index != 0); - - /* Re-enable the interrupts */ - __enable_irq(); -} - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c deleted file mode 100644 index 1ba98a0c1..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c +++ /dev/null @@ -1,1305 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_flash_ex.c - * @author MCD Application Team - * @brief Extended FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the FLASH extended peripheral: - * + Extended programming operations functions - * - @verbatim - ============================================================================== - ##### Flash Extended features ##### - ============================================================================== - - [..] Comparing to other previous devices, the FLASH interface for STM32L4xx - devices contains the following additional features - - (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write - capability (RWW) - (+) Dual bank memory organization - (+) PCROP protection for all banks - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory - of all STM32L4xx devices. It includes - (#) Flash Memory Erase functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and - HAL_FLASH_Lock() functions - (++) Erase function: Erase page, erase all sectors - (++) There are two modes of erase : - (+++) Polling Mode using HAL_FLASHEx_Erase() - (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() - - (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to : - (++) Set/Reset the write protection - (++) Set the Read protection Level - (++) Program the user Option Bytes - (++) Configure the PCROP protection - - (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to : - (++) Get the value of a write protection area - (++) Know if the read protection is activated - (++) Get the value of the user Option Bytes - (++) Get the value of a PCROP area - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASHEx FLASHEx - * @brief FLASH Extended HAL module driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Variables FLASHEx Private Variables - * @{ - */ -extern FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions - * @{ - */ -extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -void FLASH_PageErase(uint32_t Page, uint32_t Banks); -static void FLASH_MassErase(uint32_t Banks); -void FLASH_FlushCaches(void); -static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); -static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel); -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig); -static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr); -static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset); -static uint32_t FLASH_OB_GetRDP(void); -static uint32_t FLASH_OB_GetUser(void); -static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr); -/** - * @} - */ - -/* Exported functions -------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions - * @{ - */ - -/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions - * @brief Extended IO operation functions - * -@verbatim - =============================================================================== - ##### Extended programming operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the Extended FLASH - programming operations Operations. - -@endverbatim - * @{ - */ -/** - * @brief Perform a mass erase or erase the specified FLASH memory pages. - * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @param[out] PageError : pointer to variable that contains the configuration - * information on faulty page in case of error (0xFFFFFFFF means that all - * the pages have been correctly erased) - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t page_index = 0; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Deactivate the cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) - { - /* Disable instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED; - } - else - { - pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED; - } - } - else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; - } - else - { - pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; - } - - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /* Mass erase to be done */ - FLASH_MassErase(pEraseInit->Banks); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* If the erase operation is completed, disable the MER1 and MER2 Bits */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); -#else - /* If the erase operation is completed, disable the MER1 Bit */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1)); -#endif - } - else - { - /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFF; - - for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++) - { - FLASH_PageErase(page_index, pEraseInit->Banks); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the PER Bit */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB)); - - if (status != HAL_OK) - { - /* In case of error, stop erase procedure and return the faulty address */ - *PageError = page_index; - break; - } - } - } - - /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches(); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. - * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Deactivate the cache if they are activated to avoid data misbehavior */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) - { - /* Disable instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED; - } - else - { - pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED; - } - } - else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED; - } - else - { - pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; - } - - /* Enable End of Operation and Error interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); - - pFlash.Bank = pEraseInit->Banks; - - if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /* Mass erase to be done */ - pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE; - FLASH_MassErase(pEraseInit->Banks); - } - else - { - /* Erase by page to be done */ - pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE; - pFlash.NbPagesToErase = pEraseInit->NbPages; - pFlash.Page = pEraseInit->Page; - - /*Erase 1st page and wait for IT */ - FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks); - } - - return status; -} - -/** - * @brief Program Option bytes. - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); - - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Write protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_WRP) != RESET) - { - /* Configure of Write protection on the selected area */ - if(FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK) - { - status = HAL_ERROR; - } - - } - - /* Read protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET) - { - /* Configure the Read protection level */ - if(FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK) - { - status = HAL_ERROR; - } - } - - /* User Configuration */ - if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET) - { - /* Configure the user option bytes */ - if(FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK) - { - status = HAL_ERROR; - } - } - - /* PCROP Configuration */ - if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET) - { - if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr) - { - /* Configure the Proprietary code readout protection */ - if(FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr) != HAL_OK) - { - status = HAL_ERROR; - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Get the Option bytes configuration. - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that contains the - * configuration information. - * @note The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate - * which area is requested for the WRP and PCROP, else no information will be returned - * - * @retval None - */ -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) -{ - pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER); - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) || - (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB)) -#else - if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB)) -#endif - { - pOBInit->OptionType |= OPTIONBYTE_WRP; - /* Get write protection on the selected area */ - FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset)); - } - - /* Get Read protection level */ - pOBInit->RDPLevel = FLASH_OB_GetRDP(); - - /* Get the user option bytes */ - pOBInit->USERConfig = FLASH_OB_GetUser(); - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2)) -#else - if(pOBInit->PCROPConfig == FLASH_BANK_1) -#endif - { - pOBInit->OptionType |= OPTIONBYTE_PCROP; - /* Get the Proprietary code readout protection */ - FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr)); - } -} - -/** - * @} - */ - -#if defined (FLASH_CFGR_LVEN) -/** @defgroup FLASHEx_Exported_Functions_Group2 Extended specific configuration functions - * @brief Extended specific configuration functions - * -@verbatim - =============================================================================== - ##### Extended specific configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the Extended FLASH - specific configurations. - -@endverbatim - * @{ - */ - -/** - * @brief Configuration of the LVE pin of the Flash (managed by power controller - * or forced to low in order to use an external SMPS) - * @param ConfigLVE: Configuration of the LVE pin, - * This parameter can be one of the following values: - * @arg FLASH_LVE_PIN_CTRL: LVE FLASH pin controlled by power controller - * @arg FLASH_LVE_PIN_FORCED: LVE FLASH pin enforced to low (external SMPS used) - * - * @note Before enforcing the LVE pin to low, the SOC should be in low voltage - * range 2 and the voltage VDD12 should be higher than 1.08V and SMPS is ON. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_LVE_PIN(ConfigLVE)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - /* Check that the voltage scaling is range 2 */ - if (HAL_PWREx_GetVoltageRange() == PWR_REGULATOR_VOLTAGE_SCALE2) - { - /* Configure the LVEN bit */ - MODIFY_REG(FLASH->CFGR, FLASH_CFGR_LVEN, ConfigLVE); - - /* Check that the bit has been correctly configured */ - if (READ_BIT(FLASH->CFGR, FLASH_CFGR_LVEN) != ConfigLVE) - { - status = HAL_ERROR; - } - } - else - { - /* Not allow to force Flash LVE pin if not in voltage range 2 */ - status = HAL_ERROR; - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @} - */ -#endif /* FLASH_CFGR_LVEN */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** @addtogroup FLASHEx_Private_Functions - * @{ - */ -/** - * @brief Mass erase of FLASH memory. - * @param Banks: Banks to be erased - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: Bank1 to be erased - * @arg FLASH_BANK_2: Bank2 to be erased - * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased - * @retval None - */ -static void FLASH_MassErase(uint32_t Banks) -{ -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != RESET) -#endif - { - /* Check the parameters */ - assert_param(IS_FLASH_BANK(Banks)); - - /* Set the Mass Erase Bit for the bank 1 if requested */ - if((Banks & FLASH_BANK_1) != RESET) - { - SET_BIT(FLASH->CR, FLASH_CR_MER1); - } - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* Set the Mass Erase Bit for the bank 2 if requested */ - if((Banks & FLASH_BANK_2) != RESET) - { - SET_BIT(FLASH->CR, FLASH_CR_MER2); - } -#endif - } -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - else - { - SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); - } -#endif - - /* Proceed to erase all sectors */ - SET_BIT(FLASH->CR, FLASH_CR_STRT); -} - -/** - * @brief Erase the specified FLASH memory page. - * @param Page: FLASH page to erase - * This parameter must be a value between 0 and (max number of pages in the bank - 1) - * @param Banks: Bank(s) where the page will be erased - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: Page in bank 1 to be erased - * @arg FLASH_BANK_2: Page in bank 2 to be erased - * @retval None - */ -void FLASH_PageErase(uint32_t Page, uint32_t Banks) -{ - /* Check the parameters */ - assert_param(IS_FLASH_PAGE(Page)); - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if(READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) - { - CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); - } - else -#endif - { - assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); - - if((Banks & FLASH_BANK_1) != RESET) - { - CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); - } - else - { - SET_BIT(FLASH->CR, FLASH_CR_BKER); - } - } -#endif - - /* Proceed to erase the page */ - MODIFY_REG(FLASH->CR, FLASH_CR_PNB, (Page << POSITION_VAL(FLASH_CR_PNB))); - SET_BIT(FLASH->CR, FLASH_CR_PER); - SET_BIT(FLASH->CR, FLASH_CR_STRT); -} - -/** - * @brief Flush the instruction and data caches. - * @retval None - */ -void FLASH_FlushCaches(void) -{ - /* Flush instruction cache */ - if((pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_ENABLED) || - (pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) - { - /* Reset instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_RESET(); - /* Enable instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); - } - - /* Flush data cache */ - if((pFlash.CacheToReactivate == FLASH_CACHE_DCACHE_ENABLED) || - (pFlash.CacheToReactivate == FLASH_CACHE_ICACHE_DCACHE_ENABLED)) - { - /* Reset data cache */ - __HAL_FLASH_DATA_CACHE_RESET(); - /* Enable data cache */ - __HAL_FLASH_DATA_CACHE_ENABLE(); - } - - /* Reset internal variable */ - pFlash.CacheToReactivate = FLASH_CACHE_DISABLED; -} - -/** - * @brief Configure the write protection of the desired pages. - * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase Flash memory if the CPU debug - * features are connected (JTAG or single wire) or boot code is being - * executed from RAM or System flash, even if WRP is not activated. - * @note To configure the WRP options, the option lock bit OPTLOCK must be - * cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the WRP options, the option bytes must be reloaded - * through the call of the HAL_FLASH_OB_Launch() function. - * - * @param WRPArea: specifies the area to be configured. - * This parameter can be one of the following values: - * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A - * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B - * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply for STM32L43x/STM32L44x devices) - * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply for STM32L43x/STM32L44x devices) - * - * @param WRPStartOffset: specifies the start page of the write protected area - * This parameter can be page number between 0 and (max number of pages in the bank - 1) - * - * @param WRDPEndOffset: specifies the end page of the write protected area - * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1) - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WRPAREA(WRPArea)); - assert_param(IS_FLASH_PAGE(WRPStartOffset)); - assert_param(IS_FLASH_PAGE(WRDPEndOffset)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Configure the write protected area */ - if(WRPArea == OB_WRPAREA_BANK1_AREAA) - { - MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), - (WRPStartOffset | (WRDPEndOffset << 16))); - } - else if(WRPArea == OB_WRPAREA_BANK1_AREAB) - { - MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), - (WRPStartOffset | (WRDPEndOffset << 16))); - } -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - else if(WRPArea == OB_WRPAREA_BANK2_AREAA) - { - MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), - (WRPStartOffset | (WRDPEndOffset << 16))); - } - else if(WRPArea == OB_WRPAREA_BANK2_AREAB) - { - MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), - (WRPStartOffset | (WRDPEndOffset << 16))); - } -#endif - - /* Set OPTSTRT Bit */ - SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the option byte program operation is completed, disable the OPTSTRT Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - } - - return status; -} - -/** - * @brief Set the read protection level. - * - * @note To configure the RDP level, the option lock bit OPTLOCK must be - * cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the RDP level, the option bytes must be reloaded - * through the call of the HAL_FLASH_OB_Launch() function. - * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible - * to go back to level 1 or 0 !!! - * - * @param RDPLevel: specifies the read protection level. - * This parameter can be one of the following values: - * @arg OB_RDP_LEVEL_0: No protection - * @arg OB_RDP_LEVEL_1: Read protection of the memory - * @arg OB_RDP_LEVEL_2: Full chip protection - * - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_RDP_LEVEL(RDPLevel)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Configure the RDP level in the option bytes register */ - MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel); - - /* Set OPTSTRT Bit */ - SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the option byte program operation is completed, disable the OPTSTRT Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - } - - return status; -} - -/** - * @brief Program the FLASH User Option Byte. - * - * @note To configure the user option bytes, the option lock bit OPTLOCK must - * be cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the user option bytes, the option bytes must be reloaded - * through the call of the HAL_FLASH_OB_Launch() function. - * - * @param UserType: The FLASH User Option Bytes to be modified - * @param UserConfig: The FLASH User Option Bytes values: - * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16), - * IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20), - * DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). - * - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) -{ - uint32_t optr_reg_val = 0; - uint32_t optr_reg_mask = 0; - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_USER_TYPE(UserType)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - if((UserType & OB_USER_BOR_LEV) != RESET) - { - /* BOR level option byte should be modified */ - assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV)); - - /* Set value and mask for BOR level option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV); - optr_reg_mask |= FLASH_OPTR_BOR_LEV; - } - - if((UserType & OB_USER_nRST_STOP) != RESET) - { - /* nRST_STOP option byte should be modified */ - assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP)); - - /* Set value and mask for nRST_STOP option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP); - optr_reg_mask |= FLASH_OPTR_nRST_STOP; - } - - if((UserType & OB_USER_nRST_STDBY) != RESET) - { - /* nRST_STDBY option byte should be modified */ - assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY)); - - /* Set value and mask for nRST_STDBY option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY); - optr_reg_mask |= FLASH_OPTR_nRST_STDBY; - } - - if((UserType & OB_USER_nRST_SHDW) != RESET) - { - /* nRST_SHDW option byte should be modified */ - assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW)); - - /* Set value and mask for nRST_SHDW option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW); - optr_reg_mask |= FLASH_OPTR_nRST_SHDW; - } - - if((UserType & OB_USER_IWDG_SW) != RESET) - { - /* IWDG_SW option byte should be modified */ - assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW)); - - /* Set value and mask for IWDG_SW option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW); - optr_reg_mask |= FLASH_OPTR_IWDG_SW; - } - - if((UserType & OB_USER_IWDG_STOP) != RESET) - { - /* IWDG_STOP option byte should be modified */ - assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP)); - - /* Set value and mask for IWDG_STOP option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP); - optr_reg_mask |= FLASH_OPTR_IWDG_STOP; - } - - if((UserType & OB_USER_IWDG_STDBY) != RESET) - { - /* IWDG_STDBY option byte should be modified */ - assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY)); - - /* Set value and mask for IWDG_STDBY option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY); - optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; - } - - if((UserType & OB_USER_WWDG_SW) != RESET) - { - /* WWDG_SW option byte should be modified */ - assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW)); - - /* Set value and mask for WWDG_SW option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW); - optr_reg_mask |= FLASH_OPTR_WWDG_SW; - } - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if((UserType & OB_USER_BFB2) != RESET) - { - /* BFB2 option byte should be modified */ - assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2)); - - /* Set value and mask for BFB2 option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2); - optr_reg_mask |= FLASH_OPTR_BFB2; - } - - if((UserType & OB_USER_DUALBANK) != RESET) - { -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* DUALBANK option byte should be modified */ - assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DB1M)); - - /* Set value and mask for DUALBANK option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_DB1M); - optr_reg_mask |= FLASH_OPTR_DB1M; -#else - /* DUALBANK option byte should be modified */ - assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK)); - - /* Set value and mask for DUALBANK option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK); - optr_reg_mask |= FLASH_OPTR_DUALBANK; -#endif - } -#endif - - if((UserType & OB_USER_nBOOT1) != RESET) - { - /* nBOOT1 option byte should be modified */ - assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1)); - - /* Set value and mask for nBOOT1 option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1); - optr_reg_mask |= FLASH_OPTR_nBOOT1; - } - - if((UserType & OB_USER_SRAM2_PE) != RESET) - { - /* SRAM2_PE option byte should be modified */ - assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE)); - - /* Set value and mask for SRAM2_PE option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE); - optr_reg_mask |= FLASH_OPTR_SRAM2_PE; - } - - if((UserType & OB_USER_SRAM2_RST) != RESET) - { - /* SRAM2_RST option byte should be modified */ - assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST)); - - /* Set value and mask for SRAM2_RST option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST); - optr_reg_mask |= FLASH_OPTR_SRAM2_RST; - } - -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || \ - defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if((UserType & OB_USER_nSWBOOT0) != RESET) - { - /* nSWBOOT0 option byte should be modified */ - assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0)); - - /* Set value and mask for nSWBOOT0 option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0); - optr_reg_mask |= FLASH_OPTR_nSWBOOT0; - } - - if((UserType & OB_USER_nBOOT0) != RESET) - { - /* nBOOT0 option byte should be modified */ - assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0)); - - /* Set value and mask for nBOOT0 option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0); - optr_reg_mask |= FLASH_OPTR_nBOOT0; - } -#endif - - /* Configure the option bytes register */ - MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val); - - /* Set OPTSTRT Bit */ - SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the option byte program operation is completed, disable the OPTSTRT Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - } - - return status; -} - -/** - * @brief Configure the Proprietary code readout protection of the desired addresses. - * - * @note To configure the PCROP options, the option lock bit OPTLOCK must be - * cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the PCROP options, the option bytes must be reloaded - * through the call of the HAL_FLASH_OB_Launch() function. - * - * @param PCROPConfig: specifies the configuration (Bank to be configured and PCROP_RDP option). - * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 - * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE - * - * @param PCROPStartAddr: specifies the start address of the Proprietary code readout protection - * This parameter can be an address between begin and end of the bank - * - * @param PCROPEndAddr: specifies the end address of the Proprietary code readout protection - * This parameter can be an address between PCROPStartAddr and end of the bank - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t reg_value = 0; - uint32_t bank1_addr; -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - uint32_t bank2_addr; -#endif - - /* Check the parameters */ - assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH)); - assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP)); - assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr)); - assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* Get the information about the bank swapping */ - if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) - { - bank1_addr = FLASH_BASE; - bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; - } - else - { - bank1_addr = FLASH_BASE + FLASH_BANK_SIZE; - bank2_addr = FLASH_BASE; - } -#else - bank1_addr = FLASH_BASE; -#endif - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) - { - /* Configure the Proprietary code readout protection */ - if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) - { - reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); - MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); - - reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); - MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); - } - else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) - { - reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4); - MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); - - reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4); - MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); - } - } - else -#endif - { - /* Configure the Proprietary code readout protection */ - if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) - { - reg_value = ((PCROPStartAddr - bank1_addr) >> 3); - MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); - - reg_value = ((PCROPEndAddr - bank1_addr) >> 3); - MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); - } -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) - { - reg_value = ((PCROPStartAddr - bank2_addr) >> 3); - MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); - - reg_value = ((PCROPEndAddr - bank2_addr) >> 3); - MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); - } -#endif - } - - MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP)); - - /* Set OPTSTRT Bit */ - SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the option byte program operation is completed, disable the OPTSTRT Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - } - - return status; -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * - * @param[in] WRPArea: specifies the area to be returned. - * This parameter can be one of the following values: - * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A - * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B - * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices) - * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices) - * - * @param[out] WRPStartOffset: specifies the address where to copied the start page - * of the write protected area - * - * @param[out] WRDPEndOffset: specifies the address where to copied the end page of - * the write protected area - * - * @retval None - */ -static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset) -{ - /* Get the configuration of the write protected area */ - if(WRPArea == OB_WRPAREA_BANK1_AREAA) - { - *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT); - *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16); - } - else if(WRPArea == OB_WRPAREA_BANK1_AREAB) - { - *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT); - *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16); - } -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - else if(WRPArea == OB_WRPAREA_BANK2_AREAA) - { - *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT); - *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16); - } - else if(WRPArea == OB_WRPAREA_BANK2_AREAB) - { - *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT); - *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16); - } -#endif -} - -/** - * @brief Return the FLASH Read Protection level. - * @retval FLASH ReadOut Protection Status: - * This return value can be one of the following values: - * @arg OB_RDP_LEVEL_0: No protection - * @arg OB_RDP_LEVEL_1: Read protection of the memory - * @arg OB_RDP_LEVEL_2: Full chip protection - */ -static uint32_t FLASH_OB_GetRDP(void) -{ - if ((READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_0) && - (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_2)) - { - return (OB_RDP_LEVEL_1); - } - else - { - return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP)); - } -} - -/** - * @brief Return the FLASH User Option Byte value. - * @retval The FLASH User Option Bytes values: - * For STM32L47x/STM32L48x devices : - * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), - * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), - * BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). - * For STM32L43x/STM32L44x devices : - * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), - * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), - * nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27). - */ -static uint32_t FLASH_OB_GetUser(void) -{ - uint32_t user_config = READ_REG(FLASH->OPTR); - CLEAR_BIT(user_config, FLASH_OPTR_RDP); - - return user_config; -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * - * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option). - * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 - * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE - * - * @param PCROPStartAddr [out]: specifies the address where to copied the start address - * of the Proprietary code readout protection - * - * @param PCROPEndAddr [out]: specifies the address where to copied the end address of - * the Proprietary code readout protection - * - * @retval None - */ -static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr) -{ - uint32_t reg_value = 0; - uint32_t bank1_addr; -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - uint32_t bank2_addr; -#endif - -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - /* Get the information about the bank swapping */ - if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) - { - bank1_addr = FLASH_BASE; - bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; - } - else - { - bank1_addr = FLASH_BASE + FLASH_BANK_SIZE; - bank2_addr = FLASH_BASE; - } -#else - bank1_addr = FLASH_BASE; -#endif - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == RESET) - { - if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) - { - reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); - *PCROPStartAddr = (reg_value << 4) + FLASH_BASE; - - reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); - *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; - } - else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) - { - reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); - *PCROPStartAddr = (reg_value << 4) + FLASH_BASE; - - reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); - *PCROPEndAddr = (reg_value << 4) + FLASH_BASE; - } - } - else -#endif - { - if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) - { - reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); - *PCROPStartAddr = (reg_value << 3) + bank1_addr; - - reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); - *PCROPEndAddr = (reg_value << 3) + bank1_addr; - } -#if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) - { - reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); - *PCROPStartAddr = (reg_value << 3) + bank2_addr; - - reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); - *PCROPEndAddr = (reg_value << 3) + bank2_addr; - } -#endif - } - - *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP); -} -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c deleted file mode 100644 index fbd9462a1..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c +++ /dev/null @@ -1,271 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_flash_ramfunc.c - * @author MCD Application Team - * @brief FLASH RAMFUNC driver. - * This file provides a Flash firmware functions which should be - * executed from internal SRAM - * + FLASH HalfPage Programming - * + FLASH Power Down in Run mode - * - * @verbatim - ============================================================================== - ##### Flash RAM functions ##### - ============================================================================== - - *** ARM Compiler *** - -------------------- - [..] RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate - source module. Using the 'Options for File' dialog you can simply change - the 'Code / Const' area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the - Options for Target' dialog. - - *** ICCARM Compiler *** - ----------------------- - [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". - - *** GNU Compiler *** - -------------------- - [..] RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC - * @brief FLASH functions executed from RAM - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -extern FLASH_ProcessTypeDef pFlash; - -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions -------------------------------------------------------*/ - -/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH in RAM function Exported Functions - * @{ - */ - -/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### ramfunc functions ##### - =============================================================================== - [..] - This subsection provides a set of functions that should be executed from RAM. - -@endverbatim - * @{ - */ - -/** - * @brief Enable the Power down in Run Mode - * @note This function should be called and executed from SRAM memory - * @retval None - */ -__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void) -{ - /* Enable the Power Down in Run mode*/ - __HAL_FLASH_POWER_DOWN_ENABLE(); - - return HAL_OK; - -} - -/** - * @brief Disable the Power down in Run Mode - * @note This function should be called and executed from SRAM memory - * @retval None - */ -__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void) -{ - /* Disable the Power Down in Run mode*/ - __HAL_FLASH_POWER_DOWN_DISABLE(); - - return HAL_OK; -} - -#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -/** - * @brief Program the FLASH DBANK User Option Byte. - * - * @note To configure the user option bytes, the option lock bit OPTLOCK must - * be cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To modify the DBANK option byte, no PCROP region should be defined. - * To deactivate PCROP, user should perform RDP changing - * - * @param DBankConfig: The FLASH DBANK User Option Byte value. - * This parameter can be one of the following values: - * @arg OB_DBANK_128_BITS: Single-bank with 128-bits data - * @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data - * - * @retval HAL status - */ -__RAM_FUNC HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) -{ - register uint32_t count, reg; - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check if the PCROP is disabled */ - reg = FLASH->PCROP1SR; - if (reg > FLASH->PCROP1ER) - { - reg = FLASH->PCROP2SR; - if (reg > FLASH->PCROP2ER) - { - /* Disable Flash prefetch */ - __HAL_FLASH_PREFETCH_BUFFER_DISABLE(); - - if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) - { - /* Disable Flash instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); - - /* Flush Flash instruction cache */ - __HAL_FLASH_INSTRUCTION_CACHE_RESET(); - } - - if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) - { - /* Disable Flash data cache */ - __HAL_FLASH_DATA_CACHE_DISABLE(); - - /* Flush Flash data cache */ - __HAL_FLASH_DATA_CACHE_RESET(); - } - - /* Disable WRP zone 1 of 1st bank if needed */ - reg = FLASH->WRP1AR; - if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> POSITION_VAL(FLASH_WRP1AR_WRP1A_STRT)) <= - ((reg & FLASH_WRP1AR_WRP1A_END) >> POSITION_VAL(FLASH_WRP1AR_WRP1A_END))) - { - MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT); - } - - /* Disable WRP zone 2 of 1st bank if needed */ - reg = FLASH->WRP1BR; - if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> POSITION_VAL(FLASH_WRP1BR_WRP1B_STRT)) <= - ((reg & FLASH_WRP1BR_WRP1B_END) >> POSITION_VAL(FLASH_WRP1BR_WRP1B_END))) - { - MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT); - } - - /* Disable WRP zone 1 of 2nd bank if needed */ - reg = FLASH->WRP2AR; - if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> POSITION_VAL(FLASH_WRP2AR_WRP2A_STRT)) <= - ((reg & FLASH_WRP2AR_WRP2A_END) >> POSITION_VAL(FLASH_WRP2AR_WRP2A_END))) - { - MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT); - } - - /* Disable WRP zone 2 of 2nd bank if needed */ - reg = FLASH->WRP2BR; - if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> POSITION_VAL(FLASH_WRP2BR_WRP2B_STRT)) <= - ((reg & FLASH_WRP2BR_WRP2B_END) >> POSITION_VAL(FLASH_WRP2BR_WRP2B_END))) - { - MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT); - } - - /* Modify the DBANK user option byte */ - MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig); - - /* Set OPTSTRT Bit */ - SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - - /* Wait for last operation to be completed */ - /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */ - count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8 / 1000); - do - { - if (count-- == 0) - { - break; - } - } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET); - - /* If the option byte program operation is completed, disable the OPTSTRT Bit */ - CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); - - /* Set the bit to force the option byte reloading */ - SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} -#endif - -/** - * @} - */ - -/** - * @} - */ -#endif /* HAL_FLASH_MODULE_ENABLED */ - - - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c deleted file mode 100644 index 280eb31cf..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c +++ /dev/null @@ -1,568 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_gpio.c - * @author MCD Application Team - * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the General Purpose Input/Output (GPIO) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * - @verbatim - ============================================================================== - ##### GPIO Peripheral features ##### - ============================================================================== - [..] - (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually - configured by software in several modes: - (++) Input mode - (++) Analog mode - (++) Output mode - (++) Alternate function mode - (++) External interrupt/event lines - - (+) During and just after reset, the alternate functions and external interrupt - lines are not active and the I/O ports are configured in input floating mode. - - (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be - activated or not. - - (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull - type and the IO speed can be selected depending on the VDD value. - - (+) The microcontroller IO pins are connected to onboard peripherals/modules through a - multiplexer that allows only one peripheral alternate function (AF) connected - to an IO pin at a time. In this way, there can be no conflict between peripherals - sharing the same IO pin. - - (+) All ports have external interrupt/event capability. To use external interrupt - lines, the port must be configured in input mode. All available GPIO pins are - connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - - (+) The external interrupt/event controller consists of up to 39 edge detectors - (16 lines are connected to GPIO) for generating event/interrupt requests (each - input line can be independently configured to select the type (interrupt or event) - and the corresponding trigger event (rising or falling or both). Each line can - also be masked independently. - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). - - (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). - (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure - (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef - structure. - (++) In case of Output or alternate function mode selection: the speed is - configured through "Speed" member from GPIO_InitTypeDef structure. - (++) In alternate mode is selection, the alternate function connected to the IO - is configured through "Alternate" member from GPIO_InitTypeDef structure. - (++) Analog mode is required when a pin is to be used as ADC channel - or DAC output. - (++) In case of external interrupt/event selection the "Mode" member from - GPIO_InitTypeDef structure select the type (interrupt or event) and - the corresponding trigger event (rising or falling or both). - - (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority - mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using - HAL_NVIC_EnableIRQ(). - - (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). - - (#) To set/reset the level of a pin configured in output mode use - HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - - (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - - (#) During and just after reset, the alternate functions are not - active and the GPIO pins are configured in input floating mode (except JTAG - pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has - priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PH0 and PH1, respectively, when the HSE oscillator is off. - The HSE has priority over the GPIO function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIO GPIO - * @brief GPIO HAL module driver - * @{ - */ - -#ifdef HAL_GPIO_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup GPIO_Private_Defines GPIO Private Defines - * @{ - */ -#define GPIO_MODE ((uint32_t)0x00000003) -#define ANALOG_MODE ((uint32_t)0x00000008) -#define EXTI_MODE ((uint32_t)0x10000000) -#define GPIO_MODE_IT ((uint32_t)0x00010000) -#define GPIO_MODE_EVT ((uint32_t)0x00020000) -#define RISING_EDGE ((uint32_t)0x00100000) -#define FALLING_EDGE ((uint32_t)0x00200000) -#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) - -#define GPIO_NUMBER ((uint32_t)16) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ -/** - * @} - */ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) -{ - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t temp = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); - assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); - - /* Configure the port pins */ - while (((GPIO_Init->Pin) >> position) != RESET) - { - /* Get current io position */ - iocurrent = (GPIO_Init->Pin) & (1U << position); - - if(iocurrent) - { - /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameters */ - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3]; - temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); - GPIOx->AFR[position >> 3] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODE0 << (position * 2)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); - GPIOx->MODER = temp; - - /* In case of Output or Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Speed parameter */ - assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); - /* Configure the IO Speed */ - temp = GPIOx->OSPEEDR; - temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2)); - temp |= (GPIO_Init->Speed << (position * 2)); - GPIOx->OSPEEDR = temp; - - /* Configure the IO Output Type */ - temp = GPIOx->OTYPER; - temp &= ~(GPIO_OTYPER_OT0 << position) ; - temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); - GPIOx->OTYPER = temp; - } - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) - - /* In case of Analog mode, check if ADC control mode is selected */ - if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG) - { - /* Configure the IO Output Type */ - temp = GPIOx->ASCR; - temp &= ~(GPIO_ASCR_ASC0 << position) ; - temp |= (((GPIO_Init->Mode & ANALOG_MODE) >> 3) << position); - GPIOx->ASCR = temp; - } - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - - /* Activate the Pull-up or Pull down resistor for the current IO */ - temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2)); - temp |= ((GPIO_Init->Pull) << (position * 2)); - GPIOx->PUPDR = temp; - - /*--------------------- EXTI Mode Configuration ------------------------*/ - /* Configure the External Interrupt or event for the current IO */ - if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) - { - /* Enable SYSCFG Clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - temp = SYSCFG->EXTICR[position >> 2]; - temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); - temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))); - SYSCFG->EXTICR[position >> 2] = temp; - - /* Clear EXTI line configuration */ - temp = EXTI->IMR1; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - { - temp |= iocurrent; - } - EXTI->IMR1 = temp; - - temp = EXTI->EMR1; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - { - temp |= iocurrent; - } - EXTI->EMR1 = temp; - - /* Clear Rising Falling edge configuration */ - temp = EXTI->RTSR1; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) - { - temp |= iocurrent; - } - EXTI->RTSR1 = temp; - - temp = EXTI->FTSR1; - temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) - { - temp |= iocurrent; - } - EXTI->FTSR1 = temp; - } - } - - position++; - } -} - -/** - * @brief De-initialize the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Configure the port pins */ - while ((GPIO_Pin >> position) != RESET) - { - /* Get current io position */ - iocurrent = (GPIO_Pin) & (1U << position); - - if (iocurrent) - { - /*------------------------- GPIO Mode Configuration --------------------*/ - /* Configure IO in Analog Mode */ - GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2)); - - /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - - /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2)); - - /* Configure the default value IO Output Type */ - GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; - - /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2)); - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) - - /* Deactivate the Control bit of Analog mode for the current IO */ - GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position); - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ - - /*------------------------- EXTI Mode Configuration --------------------*/ - /* Clear the External Interrupt or Event for the current IO */ - - tmp = SYSCFG->EXTICR[position >> 2]; - tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); - if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) - { - tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); - SYSCFG->EXTICR[position >> 2] &= ~tmp; - - /* Clear EXTI line configuration */ - EXTI->IMR1 &= ~((uint32_t)iocurrent); - EXTI->EMR1 &= ~((uint32_t)iocurrent); - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR1 &= ~((uint32_t)iocurrent); - EXTI->FTSR1 &= ~((uint32_t)iocurrent); - } - } - - position++; - } -} - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions - * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Read the specified input port pin. - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_PIN_x where x can be (0..15). - * @retval The input port pin value. - */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - GPIO_PinState bitstatus; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) - { - bitstatus = GPIO_PIN_SET; - } - else - { - bitstatus = GPIO_PIN_RESET; - } - return bitstatus; -} - -/** - * @brief Set or clear the selected data port bit. - * - * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState: specifies the value to be written to the selected bit. - * This parameter can be one of the GPIO_PinState enum values: - * @arg GPIO_PIN_RESET: to clear the port pin - * @arg GPIO_PIN_SET: to set the port pin - * @retval None - */ -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_PIN_ACTION(PinState)); - - if(PinState != GPIO_PIN_RESET) - { - GPIOx->BSRR = (uint32_t)GPIO_Pin; - } - else - { - GPIOx->BRR = (uint32_t)GPIO_Pin; - } -} - -/** - * @brief Toggle the specified GPIO pin. - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the pin to be toggled. - * @retval None - */ -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->ODR ^= GPIO_Pin; -} - -/** -* @brief Lock GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family - * @param GPIO_Pin: specifies the port bits to be locked. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = GPIO_LCKR_LCKK; - - /* Check the parameters */ - assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Apply lock key write sequence */ - tmp |= GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - - if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) - { - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Handle EXTI interrupt request. - * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. - * @retval None - */ -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) -{ - /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) - { - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); - HAL_GPIO_EXTI_Callback(GPIO_Pin); - } -} - -/** - * @brief EXTI line detection callback. - * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. - * @retval None - */ -__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(GPIO_Pin); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_GPIO_EXTI_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - - -/** - * @} - */ - -#endif /* HAL_GPIO_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c deleted file mode 100644 index 63d38c339..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c +++ /dev/null @@ -1,4868 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_i2c.c - * @author MCD Application Team - * @brief I2C HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Inter Integrated Circuit (I2C) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The I2C HAL driver can be used as follows: - - (#) Declare a I2C_HandleTypeDef handle structure, for example: - I2C_HandleTypeDef hi2c; - - (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: - (##) Enable the I2Cx interface clock - (##) I2C pins configuration - (+++) Enable the clock for the I2C GPIOs - (+++) Configure I2C pins as alternate function open-drain - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the I2Cx interrupt priority - (+++) Enable the NVIC I2C IRQ Channel - (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel - (+++) Enable the DMAx interface clock using - (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx channel - (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on - the DMA Tx or Rx channel - - (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, - Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - - (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. - - (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() - - (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() - - *** Polling mode IO MEM operation *** - ===================================== - [..] - (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() - - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - - *** Interrupt mode IO sequential operation *** - ============================================== - [..] - (@) These interfaces allow to manage a sequential transfer with a repeated start condition - when a direction change during transfer - [..] - (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode - (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition - (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT()) - (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer - if no direction change and without a final stop condition in both cases - (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer - if no direction change and with a final stop condition in both cases - - (+) Differents sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() - (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() - (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - *** Interrupt mode IO MEM operation *** - ======================================= - [..] - (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - *** DMA mode IO MEM operation *** - ================================= - [..] - (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() - - - *** I2C HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in I2C HAL driver. - - (+) __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode - (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt - - [..] - (@) You can refer to the I2C HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup I2C I2C - * @brief I2C HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup I2C_Private_Define I2C Private Define - * @{ - */ -#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ -#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ -#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ - -#define MAX_NBYTE_SIZE 255U -#define SlaveAddr_SHIFT 7U -#define SlaveAddr_MSK 0x06U - -/* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ -#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ - - -/* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (0x00000001U) -#define I2C_XFER_RX_IT (0x00000002U) -#define I2C_XFER_LISTEN_IT (0x00000004U) - -#define I2C_XFER_ERROR_IT (0x00000011U) -#define I2C_XFER_CPLT_IT (0x00000012U) -#define I2C_XFER_RELOAD_IT (0x00000012U) - -/* Private define Sequential Transfer Options default/reset value */ -#define I2C_NO_OPTION_FRAME (0xFFFF0000U) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ - ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmatx->Instance)->CNDTR)) : \ - ((uint32_t)(((DMA_Channel_TypeDef *)(__HANDLE__)->hdmarx->Instance)->CNDTR))) - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -/* Private functions to handle DMA transfer */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAError(DMA_HandleTypeDef *hdma); -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); - -/* Private functions to handle IT transfer */ -static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); - -/* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); - -/* Private functions for I2C transfer IRQ handler */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); - -/* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); - -/* Private functions to centralize the enable/disable of Interrupts */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); - -/* Private functions to flush TXDR register */ -static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); - -/* Private functions to handle start, restart or stop a transfer */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Functions I2C Exported Functions - * @{ - */ - -/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - deinitialize the I2Cx peripheral: - - (+) User must Implement HAL_I2C_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_I2C_Init() to configure the selected device with - the selected configuration: - (++) Clock Timing - (++) Own Address 1 - (++) Addressing mode (Master, Slave) - (++) Dual Addressing mode - (++) Own Address 2 - (++) Own Address 2 Mask - (++) General call mode - (++) Nostretch mode - - (+) Call the function HAL_I2C_DeInit() to restore the default configuration - of the selected I2Cx peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the I2C according to the specified parameters - * in the I2C_InitTypeDef and initialize the associated handle. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if (hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); - assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); - assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); - assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); - assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); - assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); - assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); - - if (hi2c->State == HAL_I2C_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hi2c->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_I2C_MspInit(hi2c); - } - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ - /* Configure I2Cx: Frequency range */ - hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; - - /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ - /* Disable Own Address1 before set the Own Address1 configuration */ - hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - - /* Configure I2Cx: Own Address1 and ack own address1 mode */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); - } - else /* I2C_ADDRESSINGMODE_10BIT */ - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); - } - - /*---------------------------- I2Cx CR2 Configuration ----------------------*/ - /* Configure I2Cx: Addressing Master mode */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - hi2c->Instance->CR2 = (I2C_CR2_ADD10); - } - /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ - hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); - - /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ - /* Disable Own Address2 before set the Own Address2 configuration */ - hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; - - /* Configure I2Cx: Dual mode and Own Address2 */ - hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); - - /*---------------------------- I2Cx CR1 Configuration ----------------------*/ - /* Configure I2Cx: Generalcall and NoStretch mode */ - hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); - - /* Enable the selected I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - return HAL_OK; -} - -/** - * @brief DeInitialize the I2C peripheral. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if (hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the I2C Peripheral Clock */ - __HAL_I2C_DISABLE(hi2c); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_I2C_MspDeInit(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_RESET; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Release Lock */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Initialize the I2C MSP. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the I2C MSP. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the I2C data - transfers. - - (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_I2C_Master_Transmit() - (++) HAL_I2C_Master_Receive() - (++) HAL_I2C_Slave_Transmit() - (++) HAL_I2C_Slave_Receive() - (++) HAL_I2C_Mem_Write() - (++) HAL_I2C_Mem_Read() - (++) HAL_I2C_IsDeviceReady() - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_I2C_Master_Transmit_IT() - (++) HAL_I2C_Master_Receive_IT() - (++) HAL_I2C_Slave_Transmit_IT() - (++) HAL_I2C_Slave_Receive_IT() - (++) HAL_I2C_Mem_Write_IT() - (++) HAL_I2C_Mem_Read_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_I2C_Master_Transmit_DMA() - (++) HAL_I2C_Master_Receive_DMA() - (++) HAL_I2C_Slave_Transmit_DMA() - (++) HAL_I2C_Slave_Receive_DMA() - (++) HAL_I2C_Mem_Write_DMA() - (++) HAL_I2C_Mem_Read_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2C_MemTxCpltCallback() - (++) HAL_I2C_MemRxCpltCallback() - (++) HAL_I2C_MasterTxCpltCallback() - (++) HAL_I2C_MasterRxCpltCallback() - (++) HAL_I2C_SlaveTxCpltCallback() - (++) HAL_I2C_SlaveRxCpltCallback() - (++) HAL_I2C_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmits in master mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - } - - while (hi2c->XferCount > 0U) - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives in master mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } - - while (hi2c->XferCount > 0U) - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* If 10bit addressing mode is selected */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Wait until DIR flag is set Transmitter mode */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - while (hi2c->XferCount > 0U) - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - } - - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in blocking mode - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Wait until DIR flag is reset Receiver mode */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - while (hi2c->XferCount > 0U) - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Store Last receive data if any */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferCount--; - } - - if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) - { - return HAL_TIMEOUT; - } - else - { - return HAL_ERROR; - } - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferCount--; - } - - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_TIMEOUT; - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - if (hi2c->XferSize > 0U) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) -{ - uint32_t xfermode = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - if (hi2c->XferSize > 0U) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in blocking mode to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - do - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - - } - while (hi2c->XferCount > 0U); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in blocking mode from a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); - } - - do - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - while (hi2c->XferCount > 0U); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be read - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = 0U; - uint32_t xfermode = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Checks if target device is ready for communication. - * @note This function is used with Memory devices - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param Trials Number of trials - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - __IO uint32_t I2C_Trials = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - do - { - /* Generate Start */ - hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set or a NACK flag is set*/ - tickstart = HAL_GetTick(); - while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) - { - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - - /* Check if the NACKF flag has not been set */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) - { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - - /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials++ == Trials) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - } - while (I2C_Trials < Trials); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode = 0U; - uint32_t xferrequest = I2C_GENERATE_START_WRITE; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; - - /* If size > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - /* If transfer direction not change, do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) - { - xferrequest = I2C_NO_STARTSTOP; - } - - /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode = 0U; - uint32_t xferrequest = I2C_GENERATE_START_READ; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; - - /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - /* If transfer direction not change, do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) - { - xferrequest = I2C_NO_STARTSTOP; - } - - /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave RX state to TX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; - - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave TX state to RX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; - - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Enable the Address listen mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Enable the Address Match interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Disable the Address listen mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp; - - /* Disable Address listen mode only if a transfer is not ongoing */ - if (hi2c->State == HAL_I2C_STATE_LISTEN) - { - tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; - hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - /* Disable the Address Match interrupt */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) -{ - if (hi2c->Mode == HAL_I2C_MODE_MASTER) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Set State at HAL_I2C_STATE_ABORT */ - hi2c->State = HAL_I2C_STATE_ABORT; - - /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ - /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ - I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - return HAL_OK; - } - else - { - /* Wrong usage of abort function */ - /* This function should be used only in case of abort monitored by master device */ - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ - -/** - * @brief This function handles I2C event interrupt request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - /* Get current IT Flags and IT sources value */ - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - - /* I2C events treatment -------------------------------------*/ - if (hi2c->XferISR != NULL) - { - hi2c->XferISR(hi2c, itflags, itsources); - } -} - -/** - * @brief This function handles I2C error interrupt request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - - /* I2C Bus error interrupt occurred ------------------------------------*/ - if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); - } - - /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); - } - - /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); - } - - /* Call the Error Callback in case of Error detected */ - if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) - { - I2C_ITError(hi2c, hi2c->ErrorCode); - } -} - -/** - * @brief Master Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Master Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterRxCpltCallback could be implemented in the user file - */ -} - -/** @brief Slave Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Slave Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Slave Address Match callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION - * @param AddrMatchCode Address Match Code - * @retval None - */ -__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - UNUSED(TransferDirection); - UNUSED(AddrMatchCode); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AddrCallback() could be implemented in the user file - */ -} - -/** - * @brief Listen Complete callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ListenCpltCallback() could be implemented in the user file - */ -} - -/** - * @brief Memory Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Memory Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief I2C error callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief I2C abort callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AbortCpltCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @brief Peripheral State, Mode and Error functions - * -@verbatim - =============================================================================== - ##### Peripheral State, Mode and Error functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the I2C handle state. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL state - */ -HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) -{ - /* Return I2C handle state */ - return hi2c->State; -} - -/** - * @brief Returns the I2C Master, Slave, Memory or no mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL mode - */ -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) -{ - return hi2c->Mode; -} - -/** -* @brief Return the I2C error code. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. -* @retval I2C Error Code -*/ -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) -{ - return hi2c->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup I2C_Private_Functions - * @{ - */ - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - uint16_t devaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - /* No need to generate STOP, it is automatically done */ - /* Error callback will be send during stop flag treatment */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferSize--; - hi2c->XferCount--; - } - else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) - { - devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - else - { - /* Call TxCpltCallback() if no stop mode is set */ - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSequentialCplt(hi2c); - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - } - else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - if (hi2c->XferCount == 0U) - { - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Generate a stop condition in case of no transfer option */ - if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } - else - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSequentialCplt(hi2c); - } - } - } - else - { - /* Wrong size Status regarding TC flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - - if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - /* Process locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0*/ - /* So clear Flag NACKF only */ - if (hi2c->XferCount == 0U) - { - if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ - (hi2c->State == HAL_I2C_STATE_LISTEN)) - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); - } - else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - else - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) - { - if (hi2c->XferCount > 0U) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - hi2c->XferSize--; - hi2c->XferCount--; - } - - if ((hi2c->XferCount == 0U) && \ - (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) - { - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - } - else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) - { - I2C_ITAddrCplt(hi2c, ITFlags); - } - else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) - { - /* Write data to TXDR only if XferCount not reach "0" */ - /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Datas have already been sent */ - /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if (hi2c->XferCount > 0U) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; - hi2c->XferSize--; - } - else - { - if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) - { - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSequentialCplt(hi2c); - } - } - } - - /* Check if STOPF is set */ - if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - uint16_t devaddress = 0U; - uint32_t xfermode = 0U; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* No need to generate STOP, it is automatically done */ - /* But enable STOP interrupt, to treat it */ - /* Error callback will be send during stop flag treatment */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) - { - /* Disable TC interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); - - if (hi2c->XferCount != 0U) - { - /* Recover Slave address */ - devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Prepare the new XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Set the new XferSize in Nbytes register */ - I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Enable DMA Request */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) -{ - /* Process locked */ - __HAL_LOCK(hi2c); - - if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0 */ - /* So clear Flag NACKF only */ - if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for write request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -{ - I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for read request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shift at right before call interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) -{ - I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - return HAL_ERROR; - } - else - { - return HAL_TIMEOUT; - } - } - - /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TC flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - return HAL_OK; -} - -/** - * @brief I2C Address complete process callback. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - uint8_t transferdirection = 0U; - uint16_t slaveaddrcode = 0U; - uint16_t ownadd1code = 0U; - uint16_t ownadd2code = 0U; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(ITFlags); - - /* In case of Listen state, need to inform upper layer of address match code event */ - if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) - { - transferdirection = I2C_GET_DIR(hi2c); - slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); - ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); - ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); - - /* If 10bits addressing mode is selected */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) - { - slaveaddrcode = ownadd1code; - hi2c->AddrEventCount++; - if (hi2c->AddrEventCount == 2U) - { - /* Reset Address Event counter */ - hi2c->AddrEventCount = 0U; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - else - { - slaveaddrcode = ownadd2code; - - /* Disable ADDR Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - /* else 7 bits addressing mode is selected */ - else - { - /* Disable ADDR Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); - } - } - /* Else clear address flag only */ - else - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - } -} - -/** - * @brief I2C Master sequential complete process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) -{ - /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* No Generate Stop, to permit restart mode */ - /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; - hi2c->XferISR = NULL; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterTxCpltCallback(hi2c); - } - /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; - hi2c->XferISR = NULL; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterRxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Slave sequential complete process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) -{ - /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - - if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Tx complete callback to inform upper layer of the end of transmit process */ - HAL_I2C_SlaveTxCpltCallback(hi2c); - } - - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Rx complete callback to inform upper layer of the end of receive process */ - HAL_I2C_SlaveRxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Master complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Reset handle parameters */ - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = NULL; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - - if ((ITFlags & I2C_FLAG_AF) != RESET) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set acknowledge error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MemTxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_MasterTxCpltCallback(hi2c); - } - } - /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MemRxCpltCallback(hi2c); - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - HAL_I2C_MasterRxCpltCallback(hi2c); - } - } -} - -/** - * @brief I2C Slave complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* If a DMA is ongoing, Update handle size context */ - if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || - ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) - { - hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); - } - - /* All data are not transferred, so set error code accordingly */ - if (hi2c->XferCount != 0U) - { - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Store Last receive data if any */ - if (((ITFlags & I2C_FLAG_RXNE) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - - if ((hi2c->XferSize > 0U)) - { - hi2c->XferSize--; - hi2c->XferCount--; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - if (hi2c->State == HAL_I2C_STATE_LISTEN) - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); - } - } - else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - HAL_I2C_ListenCpltCallback(hi2c); - } - /* Call the corresponding callback to inform upper layer of End of Transfer */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Slave Rx Complete callback */ - HAL_I2C_SlaveRxCpltCallback(hi2c); - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Slave Tx Complete callback */ - HAL_I2C_SlaveTxCpltCallback(hi2c); - } -} - -/** - * @brief I2C Listen complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Reset handle parameters */ - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - /* Store Last receive data if any */ - if (((ITFlags & I2C_FLAG_RXNE) != RESET)) - { - /* Read data from RXDR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; - - if ((hi2c->XferSize > 0U)) - { - hi2c->XferSize--; - hi2c->XferCount--; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - - /* Disable all Interrupts*/ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - HAL_I2C_ListenCpltCallback(hi2c); -} - -/** - * @brief I2C interrupts error process. - * @param hi2c I2C handle. - * @param ErrorCode Error code to handle. - * @retval None - */ -static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) -{ - /* Reset handle parameters */ - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferCount = 0U; - - /* Set new error code */ - hi2c->ErrorCode |= ErrorCode; - - /* Disable Interrupts */ - if ((hi2c->State == HAL_I2C_STATE_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) - { - /* Disable all interrupts, except interrupts related to LISTEN state */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* keep HAL_I2C_STATE_LISTEN if set */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = I2C_Slave_ISR_IT; - } - else - { - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* If state is an abort treatment on goind, don't change state */ - /* This change will be do later */ - if (hi2c->State != HAL_I2C_STATE_ABORT) - { - /* Set HAL_I2C_STATE_READY */ - hi2c->State = HAL_I2C_STATE_READY; - } - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->XferISR = NULL; - } - - /* Abort DMA TX transfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); - } - } - /* Abort DMA RX transfer if any */ - else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); - } - } - else if (hi2c->State == HAL_I2C_STATE_ABORT) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_AbortCpltCallback(hi2c); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_ErrorCallback(hi2c); - } -} - -/** - * @brief I2C Tx data register flush process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) -{ - /* If a pending TXIS flag is set */ - /* Write a dummy data in TXDR to clear it */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) - { - hi2c->Instance->TXDR = 0x00U; - } - - /* Flush TX register if not empty */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); - } -} - -/** - * @brief DMA I2C master transmit process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* If last transfer, enable STOP interrupt */ - if (hi2c->XferCount == 0U) - { - /* Enable STOP interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - } - /* else prepare a new DMA transfer and enable TCReload interrupt */ - else - { - /* Update Buffer pointer */ - hi2c->pBuffPtr += hi2c->XferSize; - - /* Set the XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); - } -} - -/** - * @brief DMA I2C slave transmit process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ -} - -/** - * @brief DMA I2C master receive process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* If last transfer, enable STOP interrupt */ - if (hi2c->XferCount == 0U) - { - /* Enable STOP interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - } - /* else prepare a new DMA transfer and enable TCReload interrupt */ - else - { - /* Update Buffer pointer */ - hi2c->pBuffPtr += hi2c->XferSize; - - /* Set the XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); - } -} - -/** - * @brief DMA I2C slave receive process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ -} - -/** - * @brief DMA I2C communication error callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAError(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); -} - -/** - * @brief DMA I2C communication abort callback - * (To be called at end of DMA Abort procedure). - * @param hdma DMA handle. - * @retval None - */ -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Reset AbortCpltCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if (hi2c->State == HAL_I2C_STATE_ABORT) - { - hi2c->State = HAL_I2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_AbortCpltCallback(hi2c); - } - else - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - HAL_I2C_ErrorCallback(hi2c); - } -} - -/** - * @brief This function handles I2C Communication Timeout. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Flag Specifies the I2C flag to check. - * @param Status The new Flag status (SET or RESET). - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) - { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) - { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - /* Check if an RXNE is pending */ - /* Store Last receive data if any */ - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) - { - /* Return HAL_OK */ - /* The Reading of data from RXDR will be done in caller function */ - return HAL_OK; - } - else - { - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - - /* Check for the Timeout */ - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief This function handles Acknowledge failed detection during an I2C Communication. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - /* Wait until STOP Flag is reset */ - /* AutoEnd should be initiate after AF */ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - } - - /* Clear NACKF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - return HAL_OK; -} - -/** - * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). - * @param hi2c I2C handle. - * @param DevAddress Specifies the slave address to be programmed. - * @param Size Specifies the number of bytes to be programmed. - * This parameter must be a value between 0 and 255. - * @param Mode New state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg @ref I2C_RELOAD_MODE Enable Reload mode . - * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. - * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. - * @param Request New state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. - * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). - * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. - * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. - * @retval None - */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_TRANSFER_MODE(Mode)); - assert_param(IS_TRANSFER_REQUEST(Request)); - - /* update CR2 register */ - MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); -} - -/** - * @brief Manage the enabling of Interrupts. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0U; - - if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ - (hi2c->XferISR == I2C_Slave_ISR_DMA)) - { - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - } - else - { - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK, and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; - } - - if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; - } - - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - } - - /* Enable interrupts only at the end */ - /* to avoid the risk of I2C interrupt handle execution before */ - /* all interrupts requested done */ - __HAL_I2C_ENABLE_IT(hi2c, tmpisr); - - return HAL_OK; -} - -/** - * @brief Manage the disabling of Interrupts. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0U; - - if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Disable TC and TXI interrupts */ - tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) - { - /* Disable NACK and STOP interrupts */ - tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - } - - if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Disable TC and RXI interrupts */ - tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - - if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) - { - /* Disable NACK and STOP interrupts */ - tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - } - - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Disable ADDR, NACK and STOP interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - - /* Disable interrupts only at the end */ - /* to avoid a breaking situation like at "t" time */ - /* all disable interrupts request are not done */ - __HAL_I2C_DISABLE_IT(hi2c, tmpisr); - - return HAL_OK; -} - -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c deleted file mode 100644 index bd4e329dd..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c +++ /dev/null @@ -1,355 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_i2c_ex.c - * @author MCD Application Team - * @brief I2C Extended HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of I2C Extended peripheral: - * + Extended features functions - * - @verbatim - ============================================================================== - ##### I2C peripheral Extended features ##### - ============================================================================== - - [..] Comparing to other previous devices, the I2C interface for STM32L4xx - devices contains the following additional features - - (+) Possibility to disable or enable Analog Noise Filter - (+) Use of a configured Digital Noise Filter - (+) Disable or enable wakeup from Stop mode(s) - (+) Disable or enable Fast Mode Plus - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure Noise Filter and Wake Up Feature - (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() - (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() - (#) Configure the enable or disable of I2C Wake Up Mode using the functions : - (++) HAL_I2CEx_EnableWakeUp() - (++) HAL_I2CEx_DisableWakeUp() - (#) Configure the enable or disable of fast mode plus driving capability using the functions : - (++) HAL_I2CEx_EnableFastModePlus() - (++) HAL_I2CEx_DisableFastModePlus() - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup I2CEx I2CEx - * @brief I2C Extended HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions - * @{ - */ - -/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure Noise Filters - (+) Configure Wake Up Feature - (+) Configure Fast Mode Plus - -@endverbatim - * @{ - */ - -/** - * @brief Configure I2C Analog noise filter. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param AnalogFilter New state of the Analog filter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Reset I2Cx ANOFF bit */ - hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); - - /* Set analog filter bit*/ - hi2c->Instance->CR1 |= AnalogFilter; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configure I2C Digital noise filter. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) -{ - uint32_t tmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Get the old register value */ - tmpreg = hi2c->Instance->CR1; - - /* Reset I2Cx DNF bits [11:8] */ - tmpreg &= ~(I2C_CR1_DNF); - - /* Set I2Cx DNF coefficient */ - tmpreg |= DigitalFilter << 8U; - - /* Store the new register value */ - hi2c->Instance->CR1 = tmpreg; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Enable I2C wakeup from Stop mode(s). - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) -{ - /* Check the parameters */ - assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Enable wakeup from stop mode */ - hi2c->Instance->CR1 |= I2C_CR1_WUPEN; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Disable I2C wakeup from Stop mode(s). - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) -{ - /* Check the parameters */ - assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Enable wakeup from stop mode */ - hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Enable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus Selects the pin. - * This parameter can be one of the @ref I2CEx_FastModePlus values - * @note For I2C1, fast mode plus driving capability can be enabled on all selected - * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently - * on each one of the following pins PB6, PB7, PB8 and PB9. - * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. - * @note For all I2C2 pins fast mode plus driving capability can be enabled - * only by using I2C_FASTMODEPLUS_I2C2 parameter. - * @note For all I2C3 pins fast mode plus driving capability can be enabled - * only by using I2C_FASTMODEPLUS_I2C3 parameter. - * @note For all I2C4 pins fast mode plus driving capability can be enabled - * only by using I2C_FASTMODEPLUS_I2C4 parameter. - * @retval None - */ -void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) -{ - /* Check the parameter */ - assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - - /* Enable SYSCFG clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Enable fast mode plus driving capability for selected pin */ - SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); -} - -/** - * @brief Disable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus Selects the pin. - * This parameter can be one of the @ref I2CEx_FastModePlus values - * @note For I2C1, fast mode plus driving capability can be disabled on all selected - * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently - * on each one of the following pins PB6, PB7, PB8 and PB9. - * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. - * @note For all I2C2 pins fast mode plus driving capability can be disabled - * only by using I2C_FASTMODEPLUS_I2C2 parameter. - * @note For all I2C3 pins fast mode plus driving capability can be disabled - * only by using I2C_FASTMODEPLUS_I2C3 parameter. - * @note For all I2C4 pins fast mode plus driving capability can be disabled - * only by using I2C_FASTMODEPLUS_I2C4 parameter. - * @retval None - */ -void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) -{ - /* Check the parameter */ - assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - - /* Enable SYSCFG clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Disable fast mode plus driving capability for selected pin */ - CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c deleted file mode 100644 index 6aed000b8..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c +++ /dev/null @@ -1,1675 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pcd.c - * @author MCD Application Team - * @brief PCD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The PCD HAL driver can be used as follows: - - (#) Declare a PCD_HandleTypeDef handle structure, for example: - PCD_HandleTypeDef hpcd; - - (#) Fill parameters of Init structure in HCD handle - - (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) - - (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: - (##) Enable the PCD/USB Low Level interface clock using - (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - (##) Initialize the related GPIO clocks - (##) Configure PCD pin-out - (##) Configure PCD NVIC interrupt - - (#)Associate the Upper USB device stack to the HAL PCD Driver: - (##) hpcd.pData = pdev; - - (#)Enable PCD transmission and reception: - (##) HAL_PCD_Start(); - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup PCD PCD - * @brief PCD HAL module driver - * @{ - */ - -#ifdef HAL_PCD_MODULE_ENABLED - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** - * USB_OTG_CORE VERSION ID - */ -#define USB_OTG_CORE_ID_310A 0x4F54310A -#define USB_OTG_CORE_ID_320A 0x4F54320A - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup PCD_Private_Macros PCD Private Macros - * @{ - */ -#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) -#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) -/** - * @} - */ - -/* Private functions prototypes ----------------------------------------------*/ -/** @defgroup PCD_Private_Functions PCD Private Functions - * @{ - */ -#if defined (USB_OTG_FS) -static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); -#endif /* USB_OTG_FS */ -#if defined (USB) -static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); -#endif /* USB */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup PCD_Exported_Functions PCD Exported Functions - * @{ - */ - -/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the PCD according to the specified - * parameters in the PCD_InitTypeDef and initialize the associated handle. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) -{ - uint32_t index = 0U; - - /* Check the PCD handle allocation */ - if(hpcd == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); - - if(hpcd->State == HAL_PCD_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hpcd->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_PCD_MspInit(hpcd); - } - - hpcd->State = HAL_PCD_STATE_BUSY; - - /* Disable the Interrupts */ - __HAL_PCD_DISABLE(hpcd); - - /*Init the Core (common init.) */ - USB_CoreInit(hpcd->Instance, hpcd->Init); - - /* Force Device Mode*/ - USB_SetCurrentMode(hpcd->Instance , USB_DEVICE_MODE); - - /* Init endpoints structures */ - for (index = 0; index < hpcd->Init.dev_endpoints ; index++) - { - /* Init ep structure */ - hpcd->IN_ep[index].is_in = 1; - hpcd->IN_ep[index].num = index; - hpcd->IN_ep[index].tx_fifo_num = index; - /* Control until ep is activated */ - hpcd->IN_ep[index].type = EP_TYPE_CTRL; - hpcd->IN_ep[index].maxpacket = 0; - hpcd->IN_ep[index].xfer_buff = 0; - hpcd->IN_ep[index].xfer_len = 0; - } - - for (index = 0; index < 15 ; index++) - { - hpcd->OUT_ep[index].is_in = 0; - hpcd->OUT_ep[index].num = index; - hpcd->IN_ep[index].tx_fifo_num = index; - /* Control until ep is activated */ - hpcd->OUT_ep[index].type = EP_TYPE_CTRL; - hpcd->OUT_ep[index].maxpacket = 0; - hpcd->OUT_ep[index].xfer_buff = 0; - hpcd->OUT_ep[index].xfer_len = 0; - } - - /* Init Device */ - USB_DevInit(hpcd->Instance, hpcd->Init); - - hpcd->USB_Address = 0; - - hpcd->State= HAL_PCD_STATE_READY; - - /* Activate LPM */ - if (hpcd->Init.lpm_enable ==1) - { - HAL_PCDEx_ActivateLPM(hpcd); - } - /* Activate Battery charging */ - if (hpcd->Init.battery_charging_enable ==1) - { - HAL_PCDEx_ActivateBCD(hpcd); - } - USB_DevDisconnect (hpcd->Instance); - return HAL_OK; -} - -/** - * @brief DeInitializes the PCD peripheral. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) -{ - /* Check the PCD handle allocation */ - if(hpcd == NULL) - { - return HAL_ERROR; - } - - hpcd->State = HAL_PCD_STATE_BUSY; - - /* Stop Device */ - HAL_PCD_Stop(hpcd); - - /* DeInit the low level hardware */ - HAL_PCD_MspDeInit(hpcd); - - hpcd->State = HAL_PCD_STATE_RESET; - - return HAL_OK; -} - -/** - * @brief Initializes the PCD MSP. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes PCD MSP. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the PCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Start The USB OTG Device. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - USB_DevConnect (hpcd->Instance); - __HAL_PCD_ENABLE(hpcd); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Stop The USB OTG Device. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - __HAL_PCD_DISABLE(hpcd); - USB_StopDevice(hpcd->Instance); - USB_DevDisconnect (hpcd->Instance); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} -#if defined (USB_OTG_FS) -/** - * @brief Handles PCD interrupt request. - * @param hpcd: PCD handle - * @retval HAL status - */ -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t index = 0U, ep_intr = 0U, epint = 0U, epnum = 0U; - uint32_t fifoemptymsk = 0U, temp = 0U; - USB_OTG_EPTypeDef *ep = NULL; - uint32_t hclk = 80000000; - - /* ensure that we are in device mode */ - if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) - { - /* avoid spurious interrupt */ - if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) - { - return; - } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) - { - /* incorrect mode, acknowledge the interrupt */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); - } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) - { - epnum = 0; - - /* Read in the device interrupt bits */ - ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); - - while (ep_intr) - { - if (ep_intr & 0x1) - { - epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum); - - if (( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); - - /* setup/out transaction management for Core ID 310A */ - if (USBx->GSNPSID == USB_OTG_CORE_ID_310A) - { - if (!(USBx_OUTEP(0)->DOEPINT & (0x1 << 15))) - { - if (hpcd->Init.dma_enable == 1) - { - hpcd->OUT_ep[epnum].xfer_count = - hpcd->OUT_ep[epnum].maxpacket - - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - - hpcd->OUT_ep[epnum].xfer_buff += - hpcd->OUT_ep[epnum].maxpacket; - } - - HAL_PCD_DataOutStageCallback(hpcd, epnum); - - if (hpcd->Init.dma_enable == 1) - { - if (!epnum && !hpcd->OUT_ep[epnum].xfer_len) - { - /* this is ZLP, so prepare EP0 for next setup */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); - } - } - } - - /* Clear the SetPktRcvd flag*/ - USBx_OUTEP(0)->DOEPINT |= (0x1 << 15) | (0x1 << 5); - } - else - { - if (hpcd->Init.dma_enable == 1) - { - hpcd->OUT_ep[epnum].xfer_count = - hpcd->OUT_ep[epnum].maxpacket - - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; - } - - HAL_PCD_DataOutStageCallback(hpcd, epnum); - - if (hpcd->Init.dma_enable == 1) - { - if (!epnum && !hpcd->OUT_ep[epnum].xfer_len) - { - /* this is ZLP, so prepare EP0 for next setup */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); - } - } - } - } - - if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) - { - /* Inform the upper layer that a setup packet is available */ - HAL_PCD_SetupStageCallback(hpcd); - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); - } - - if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); - } - -#ifdef USB_OTG_DOEPINT_OTEPSPR - /* Clear Status Phase Received interrupt */ - if(( epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); - } -#endif /* USB_OTG_DOEPINT_OTEPSPR */ - } - epnum++; - ep_intr >>= 1; - } - } - - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) - { - /* Read in the device interrupt bits */ - ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); - - epnum = 0; - - while ( ep_intr ) - { - if (ep_intr & 0x1) /* In ITR */ - { - epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum); - - if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) - { - fifoemptymsk = 0x1 << epnum; - USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); - - if (hpcd->Init.dma_enable == 1) - { - hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; - } - - HAL_PCD_DataInStageCallback(hpcd, epnum); - - if (hpcd->Init.dma_enable == 1) - { - /* this is ZLP, so prepare EP0 for next setup */ - if((epnum == 0) && (hpcd->IN_ep[epnum].xfer_len == 0)) - { - /* prepare to rx more setup packets */ - USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup); - } - } - } - if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); - } - if(( epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); - } - if(( epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); - } - if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); - } - if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) - { - PCD_WriteEmptyTxFifo(hpcd , epnum); - } - } - epnum++; - ep_intr >>= 1; - } - } - - /* Handle Resume Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) - { - /* Clear the Remote Wake-up Signaling */ - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - - if(hpcd->LPM_State == LPM_L1) - { - hpcd->LPM_State = LPM_L0; - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); - } - else - { - HAL_PCD_ResumeCallback(hpcd); - } - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); - } - - /* Handle Suspend Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) - { - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) - { - - HAL_PCD_SuspendCallback(hpcd); - } - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); - } - - /* Handle LPM Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); - if( hpcd->LPM_State == LPM_L0) - { - hpcd->LPM_State = LPM_L1; - hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >>2 ; - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); - } - else - { - HAL_PCD_SuspendCallback(hpcd); - } - } - - /* Handle Reset Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) - { - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - USB_FlushTxFifo(hpcd->Instance , 0x10); - - for (index = 0; index < hpcd->Init.dev_endpoints ; index++) - { - USBx_INEP(index)->DIEPINT = 0xFF; - USBx_OUTEP(index)->DOEPINT = 0xFF; - } - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK |= 0x10001; - - if(hpcd->Init.use_dedicated_ep1) - { - USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); - USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); - } - else - { -#ifdef USB_OTG_DOEPINT_OTEPSPR - USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM); -#else - USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); -#endif /* USB_OTG_DOEPINT_OTEPSPR */ - USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); - } - - /* Set Default Address to 0 */ - USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; - - /* setup EP0 to receive SETUP packets */ - USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); - } - - /* Handle Enumeration done Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) - { - USB_ActivateSetup(hpcd->Instance); - hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; - - hpcd->Init.speed = USB_OTG_SPEED_FULL; - hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; - - /* The USBTRD is configured according to the tables below, depending on AHB frequency - used by application. In the low AHB frequency range it is used to stretch enough the USB response - time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access - latency to the Data FIFO */ - - /* Get hclk frequency value */ - hclk = HAL_RCC_GetHCLKFreq(); - - if((hclk >= 14200000)&&(hclk < 15000000)) - { - /* hclk Clock Range between 14.2-15 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 15000000)&&(hclk < 16000000)) - { - /* hclk Clock Range between 15-16 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 16000000)&&(hclk < 17200000)) - { - /* hclk Clock Range between 16-17.2 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 17200000)&&(hclk < 18500000)) - { - /* hclk Clock Range between 17.2-18.5 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 18500000)&&(hclk < 20000000)) - { - /* hclk Clock Range between 18.5-20 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 20000000)&&(hclk < 21800000)) - { - /* hclk Clock Range between 20-21.8 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 21800000)&&(hclk < 24000000)) - { - /* hclk Clock Range between 21.8-24 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 24000000)&&(hclk < 27700000)) - { - /* hclk Clock Range between 24-27.7 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else if((hclk >= 27700000)&&(hclk < 32000000)) - { - /* hclk Clock Range between 27.7-32 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - else /* if(hclk >= 32000000) */ - { - /* hclk Clock Range between 32-80 MHz */ - hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT); - } - - HAL_PCD_ResetCallback(hpcd); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); - } - - /* Handle RxQLevel Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) - { - USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - temp = USBx->GRXSTSP; - - ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; - - if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) - { - if((temp & USB_OTG_GRXSTSP_BCNT) != 0) - { - USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4); - ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - } - } - else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) - { - USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8); - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - } - USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } - - /* Handle SOF Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) - { - HAL_PCD_SOFCallback(hpcd); - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); - } - - /* Handle Incomplete ISO IN Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) - { - HAL_PCD_ISOINIncompleteCallback(hpcd, epnum); - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); - } - - /* Handle Incomplete ISO OUT Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) - { - HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum); - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); - } - - /* Handle Connection event Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) - { - HAL_PCD_ConnectCallback(hpcd); - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); - } - - /* Handle Disconnection event Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) - { - temp = hpcd->Instance->GOTGINT; - - if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) - { - HAL_PCD_DisconnectCallback(hpcd); - } - hpcd->Instance->GOTGINT |= temp; - } - } -} - -#endif /* USB_OTG_FS */ - -#if defined (USB) -/** - * @brief This function handles PCD interrupt request. - * @param hpcd: PCD handle - * @retval HAL status - */ -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) -{ - uint32_t wInterrupt_Mask = 0; - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) - { - /* servicing of the endpoint correct transfer interrupt */ - /* clear of the CTR flag into the sub */ - PCD_EP_ISR_Handler(hpcd); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); - HAL_PCD_ResetCallback(hpcd); - HAL_PCD_SetAddress(hpcd, 0); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) - { - - hpcd->Instance->CNTR &= ~(USB_CNTR_LPMODE); - - /*set wInterrupt_Mask global variable*/ - wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM; - - /*Set interrupt mask*/ - hpcd->Instance->CNTR = wInterrupt_Mask; - - /* enable L1REQ interrupt */ - if (hpcd->Init.lpm_enable ==1) - { - wInterrupt_Mask |= USB_CNTR_L1REQM; - - /* Enable LPM support and enable ACK answer to LPM request*/ - USB_TypeDef *USBx = hpcd->Instance; - hpcd->lpm_active = ENABLE; - hpcd->LPM_State = LPM_L0; - - USBx->LPMCSR |= (USB_LPMCSR_LMPEN); - USBx->LPMCSR |= (USB_LPMCSR_LPMACK); - } - - if(hpcd->LPM_State == LPM_L1) - { - hpcd->LPM_State = LPM_L0; - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); - } - - HAL_PCD_ResumeCallback(hpcd); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) - { - /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - - /* Force low-power mode in the macrocell */ - hpcd->Instance->CNTR |= USB_CNTR_FSUSP; - hpcd->Instance->CNTR |= USB_CNTR_LPMODE; - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) - { - HAL_PCD_SuspendCallback(hpcd); - } - } - - /* Handle LPM Interrupt */ - if(__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ); - if( hpcd->LPM_State == LPM_L0) - { - /* Force suspend and low-power mode before going to L1 state*/ - hpcd->Instance->CNTR |= USB_CNTR_LPMODE; - hpcd->Instance->CNTR |= USB_CNTR_FSUSP; - - hpcd->LPM_State = LPM_L1; - hpcd->BESL = (hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >>2 ; - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); - } - else - { - HAL_PCD_SuspendCallback(hpcd); - } - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); - HAL_PCD_SOFCallback(hpcd); - } - - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF)) - { - /* clear ESOF flag in ISTR */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); - } -} -#endif /* USB */ - -/** - * @brief Data OUT stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ -__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_DataOutStageCallback could be implemented in the user file - */ -} - -/** - * @brief Data IN stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ -__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_DataInStageCallback could be implemented in the user file - */ -} -/** - * @brief Setup stage callback. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_SetupStageCallback could be implemented in the user file - */ -} - -/** - * @brief USB Start Of Frame callback. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_SOFCallback could be implemented in the user file - */ -} - -/** - * @brief USB Reset callback. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ResetCallback could be implemented in the user file - */ -} - -/** - * @brief Suspend event callback. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_SuspendCallback could be implemented in the user file - */ -} - -/** - * @brief Resume event callback. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ResumeCallback could be implemented in the user file - */ -} - -/** - * @brief Incomplete ISO OUT callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ -__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file - */ -} - -/** - * @brief Incomplete ISO IN callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval None - */ -__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file - */ -} - -/** - * @brief Connection event callback. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ConnectCallback could be implemented in the user file - */ -} - -/** - * @brief Disconnection event callback. - * @param hpcd: PCD handle - * @retval None - */ -__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_DisconnectCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the PCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Connect the USB device. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - USB_DevConnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Disconnect the USB device. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - USB_DevDisconnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - -/** - * @brief Set the USB Device address. - * @param hpcd: PCD handle - * @param address: new device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) -{ - __HAL_LOCK(hpcd); - hpcd->USB_Address = address; - USB_SetDevAddress(hpcd->Instance, address); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} -/** - * @brief Open and configure an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param ep_mps: endpoint max packet size - * @param ep_type: endpoint type - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) -{ - HAL_StatusTypeDef ret = HAL_OK; - PCD_EPTypeDef *ep = NULL; - - if ((ep_addr & 0x80) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; - ep->maxpacket = ep_mps; - ep->type = ep_type; - - __HAL_LOCK(hpcd); - USB_ActivateEndpoint(hpcd->Instance , ep); - __HAL_UNLOCK(hpcd); - return ret; - -} - - -/** - * @brief Deactivate an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep = NULL; - - if ((ep_addr & 0x80) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; - - __HAL_LOCK(hpcd); - USB_DeactivateEndpoint(hpcd->Instance , ep); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - - -/** - * @brief Receive an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the reception buffer - * @param len: amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) -{ - PCD_EPTypeDef *ep = NULL; - - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; - - /*setup and start the Xfer */ - ep->xfer_buff = pBuf; - ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; - - if ((ep_addr & 0x7F) == 0 ) - { - USB_EP0StartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); - } - else - { - USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); - } - - return HAL_OK; -} - -/** - * @brief Get Received Data Size. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval Data Size - */ -uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count; -} -/** - * @brief Send an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the transmission buffer - * @param len: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) -{ - PCD_EPTypeDef *ep = NULL; - - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - - /*setup and start the Xfer */ - ep->xfer_buff = pBuf; - ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 1; - ep->num = ep_addr & 0x7F; - - if ((ep_addr & 0x7F) == 0 ) - { - USB_EP0StartXfer(hpcd->Instance,ep, hpcd->Init.dma_enable); - } - else - { - USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable); - } - - return HAL_OK; -} - -/** - * @brief Set a STALL condition over an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep = NULL; - - if ((0x80 & ep_addr) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - ep->is_stall = 1; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - - __HAL_LOCK(hpcd); - USB_EPSetStall(hpcd->Instance , ep); - if((ep_addr & 0x7F) == 0) - { - USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); - } - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Clear a STALL condition over in an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep = NULL; - - if ((0x80 & ep_addr) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - ep->is_stall = 0; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); - - __HAL_LOCK(hpcd); - USB_EPClearStall(hpcd->Instance , ep); - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Flush an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - __HAL_LOCK(hpcd); - - if ((ep_addr & 0x80) == 0x80) - { - USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F); - } - else - { - USB_FlushRxFifo(hpcd->Instance); - } - - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Activate remote wakeup signalling. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - return(USB_ActivateRemoteWakeup(hpcd->Instance)); -} - -/** - * @brief De-activate remote wakeup signalling. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - return(USB_DeActivateRemoteWakeup(hpcd->Instance)); -} -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the PCD handle state. - * @param hpcd: PCD handle - * @retval HAL state - */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) -{ - return hpcd->State; -} -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup PCD_Private_Functions - * @{ - */ -#if defined (USB_OTG_FS) -/** - * @brief Check FIFO for the next packet to be loaded. - * @param hpcd: PCD handle - * @param epnum: endpoint number - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - USB_OTG_EPTypeDef *ep = NULL; - int32_t len = 0U; - uint32_t len32b = 0; - uint32_t fifoemptymsk = 0; - - ep = &hpcd->IN_ep[epnum]; - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - - - len32b = (len + 3) / 4; - - while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b && - ep->xfer_count < ep->xfer_len && - ep->xfer_len != 0) - { - /* Write the FIFO */ - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - len32b = (len + 3) / 4; - - USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable); - - ep->xfer_buff += len; - ep->xfer_count += len; - } - - if(len <= 0) - { - fifoemptymsk = 0x1 << epnum; - USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - - } - - return HAL_OK; -} -#endif /* USB_OTG_FS */ - -#if defined (USB) -/** - * @brief This function handles PCD Endpoint interrupt request. - * @param hpcd: PCD handle - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) -{ - PCD_EPTypeDef *ep = NULL; - uint16_t count = 0; - uint8_t epindex = 0; - __IO uint16_t wIstr = 0; - __IO uint16_t wEPVal = 0; - - /* stay in loop while pending interrupts */ - while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0) - { - /* extract highest priority endpoint number */ - epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); - - if (epindex == 0) - { - /* Decode and service control endpoint interrupt */ - - /* DIR bit = origin of the interrupt */ - if ((wIstr & USB_ISTR_DIR) == 0) - { - /* DIR = 0 */ - - /* DIR = 0 => IN int */ - /* DIR = 0 implies that (EP_CTR_TX = 1) always */ - PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); - ep = &hpcd->IN_ep[0]; - - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff += ep->xfer_count; - - /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, 0); - - - if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) - { - hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); - hpcd->USB_Address = 0; - } - - } - else - { - /* DIR = 1 */ - - /* DIR = 1 & CTR_RX => SETUP or OUT int */ - /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ - ep = &hpcd->OUT_ep[0]; - wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if ((wEPVal & USB_EP_SETUP) != 0) - { - /* Get SETUP Packet*/ - ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - USB_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count); - /* SETUP bit kept frozen while CTR_RX = 1*/ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - - /* Process SETUP Packet*/ - HAL_PCD_SetupStageCallback(hpcd); - } - - else if ((wEPVal & USB_EP_CTR_RX) != 0) - { - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - /* Get Control Data OUT Packet*/ - ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - - if (ep->xfer_count != 0) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - ep->xfer_buff+=ep->xfer_count; - } - - /* Process Control Data OUT Packet*/ - HAL_PCD_DataOutStageCallback(hpcd, 0); - - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); - } - } - } - else - { - /* Decode and service non control endpoints interrupt */ - - /* process related endpoint register */ - wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); - if ((wEPVal & USB_EP_CTR_RX) != 0) - { - /* clear int flag */ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); - ep = &hpcd->OUT_ep[epindex]; - - /* OUT double Buffering*/ - if (ep->doublebuffer == 0) - { - count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); - } - } - else - { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) - { - /*read from endpoint BUF0Addr buffer*/ - count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); - } - } - else - { - /*read from endpoint BUF1Addr buffer*/ - count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (count != 0) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); - } - } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT); - } - /*multi-packet on the NON control OUT endpoint*/ - ep->xfer_count+=count; - ep->xfer_buff+=count; - - if ((ep->xfer_len == 0) || (count < ep->maxpacket)) - { - /* RX COMPLETE */ - HAL_PCD_DataOutStageCallback(hpcd, ep->num); - } - else - { - HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); - } - - } /* if((wEPVal & EP_CTR_RX) */ - - if ((wEPVal & USB_EP_CTR_TX) != 0) - { - ep = &hpcd->IN_ep[epindex]; - - /* clear int flag */ - PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - - /* IN double Buffering*/ - if (ep->doublebuffer == 0) - { - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); - } - } - else - { - if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX) - { - /*read from endpoint BUF0Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); - } - } - else - { - /*read from endpoint BUF1Addr buffer*/ - ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) - { - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); - } - } - PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN); - } - /*multi-packet on the NON control IN endpoint*/ - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff+=ep->xfer_count; - - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, ep->num); - } - else - { - HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len); - } - } - } - } - return HAL_OK; -} -#endif /* USB */ - -/** - * @} - */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* HAL_PCD_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c deleted file mode 100644 index 8a3cc9a34..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c +++ /dev/null @@ -1,523 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pcd_ex.c - * @author MCD Application Team - * @brief PCD Extended HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Extended features functions - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup PCDEx PCDEx - * @brief PCD Extended HAL module driver - * @{ - */ - -#ifdef HAL_PCD_MODULE_ENABLED - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions - * @{ - */ - -/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @brief PCDEx control functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Update FIFO configuration - -@endverbatim - * @{ - */ -#if defined (USB_OTG_FS) -/** - * @brief Set Tx FIFO - * @param hpcd: PCD handle - * @param fifo: The number of Tx fifo - * @param size: Fifo size - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) -{ - uint8_t index = 0; - uint32_t Tx_Offset = 0; - - /* TXn min size = 16 words. (n : Transmit FIFO index) - When a TxFIFO is not used, the Configuration should be as follows: - case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) - --> Txm can use the space allocated for Txn. - case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) - --> Txn should be configured with the minimum space of 16 words - The FIFO is used optimally when used TxFIFOs are allocated in the top - of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. - When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ - - Tx_Offset = hpcd->Instance->GRXFSIZ; - - if(fifo == 0) - { - hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset; - } - else - { - Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; - for (index = 0; index < (fifo - 1); index++) - { - Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16); - } - - /* Multiply Tx_Size by 2 to get higher performance */ - hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset; - } - - return HAL_OK; -} - -/** - * @brief Set Rx FIFO - * @param hpcd: PCD handle - * @param size: Size of Rx fifo - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) -{ - hpcd->Instance->GRXFSIZ = size; - - return HAL_OK; -} - -/** - * @brief Activate LPM feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = ENABLE; - hpcd->LPM_State = LPM_L0; - USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; - USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; -} - -/** - * @brief Deactivate LPM feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = DISABLE; - USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; - USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; -} - -/** - * @brief Handle BatteryCharging Process. - * @param hpcd: PCD handle - * @retval HAL status - */ -void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t tickstart = HAL_GetTick(); - - /* Start BCD When device is connected */ - if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS) - { - /* Enable DCD : Data Contact Detect */ - USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; - - /* Wait Detect flag or a timeout is happen*/ - while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > 1000) - { - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); - return; - } - } - - /* Right response got */ - HAL_Delay(100); - - /* Check Detect flag*/ - if (USBx->GCCFG & USB_OTG_GCCFG_DCDET) - { - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); - } - - /*Primary detection: checks if connected to Standard Downstream Port - (without charging capability) */ - USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN; - USBx->GCCFG |= USB_OTG_GCCFG_PDEN; - HAL_Delay(100); - - if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET)) - { - /* Case of Standard Downstream Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); - } - else - { - /* start secondary detection to check connection to Charging Downstream - Port or Dedicated Charging Port */ - USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN; - USBx->GCCFG |= USB_OTG_GCCFG_SDEN; - HAL_Delay(100); - - if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET) - { - /* case Dedicated Charging Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); - } - else - { - /* case Charging Downstream Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); - } - } - /* Battery Charging capability discovery finished */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); - } -} - -/** - * @brief Activate BatteryCharging feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->battery_charging_active = ENABLE; - USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN); - - return HAL_OK; -} - -/** - * @brief Deactivate BatteryCharging feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = DISABLE; - USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); - return HAL_OK; -} -#endif /* USB_OTG_FS */ - -#if defined (USB) -/** - * @brief Configure PMA for EP - * @param hpcd : Device instance - * @param ep_addr: endpoint address - * @param ep_kind: endpoint Kind - * USB_SNG_BUF: Single Buffer used - * USB_DBL_BUF: Double Buffer used - * @param pmaadress: EP address in The PMA: In case of single buffer endpoint - * this parameter is 16-bit value providing the address - * in PMA allocated to endpoint. - * In case of double buffer endpoint this parameter - * is a 32-bit value providing the endpoint buffer 0 address - * in the LSB part of 32-bit value and endpoint buffer 1 address - * in the MSB part of 32-bit value. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, - uint16_t ep_addr, - uint16_t ep_kind, - uint32_t pmaadress) - -{ - PCD_EPTypeDef *ep = NULL; - - /* initialize ep structure*/ - if ((0x80 & ep_addr) == 0x80) - { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - /* Here we check if the endpoint is single or double Buffer*/ - if (ep_kind == PCD_SNG_BUF) - { - /*Single Buffer*/ - ep->doublebuffer = 0; - /*Configure te PMA*/ - ep->pmaadress = (uint16_t)pmaadress; - } - else /*USB_DBL_BUF*/ - { - /*Double Buffer Endpoint*/ - ep->doublebuffer = 1; - /*Configure the PMA*/ - ep->pmaaddr0 = pmaadress & 0xFFFF; - ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16; - } - - return HAL_OK; -} - -/** - * @brief Activate BatteryCharging feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_TypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = ENABLE; - - USBx->BCDR |= (USB_BCDR_BCDEN); - /* Enable DCD : Data Contact Detect */ - USBx->BCDR |= (USB_BCDR_DCDEN); - - return HAL_OK; -} - -/** - * @brief Deactivate BatteryCharging feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_TypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = DISABLE; - - USBx->BCDR &= ~(USB_BCDR_BCDEN); - return HAL_OK; -} - -/** - * @brief Handle BatteryCharging Process. - * @param hpcd: PCD handle - * @retval HAL status - */ -void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) -{ - USB_TypeDef *USBx = hpcd->Instance; - uint32_t tickstart = HAL_GetTick(); - - /* Wait Detect flag or a timeout is happen*/ - while ((USBx->BCDR & USB_BCDR_DCDET) == 0) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > 1000) - { - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); - return; - } - } - - HAL_Delay(300); - - /* Data Pin Contact ? Check Detect flag */ - if (USBx->BCDR & USB_BCDR_DCDET) - { - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); - } - /* Primary detection: checks if connected to Standard Downstream Port - (without charging capability) */ - USBx->BCDR &= ~(USB_BCDR_DCDEN); - USBx->BCDR |= (USB_BCDR_PDEN); - HAL_Delay(300); - - /* If Charger detect ? */ - if (USBx->BCDR & USB_BCDR_PDET) - { - /* Start secondary detection to check connection to Charging Downstream - Port or Dedicated Charging Port */ - USBx->BCDR &= ~(USB_BCDR_PDEN); - USBx->BCDR |= (USB_BCDR_SDEN); - HAL_Delay(300); - - /* If CDP ? */ - if (USBx->BCDR & USB_BCDR_SDET) - { - /* Dedicated Downstream Port DCP */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); - } - else - { - /* Charging Downstream Port CDP */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); - - /* Battery Charging capability discovery finished - Start Enumeration*/ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); - } - } - else /* NO */ - { - /* Standard Downstream Port */ - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); - } -} - -/** - * @brief Activate LPM feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) -{ - - USB_TypeDef *USBx = hpcd->Instance; - hpcd->lpm_active = ENABLE; - hpcd->LPM_State = LPM_L0; - - USBx->LPMCSR |= (USB_LPMCSR_LMPEN); - USBx->LPMCSR |= (USB_LPMCSR_LPMACK); - - - return HAL_OK; -} - -/** - * @brief Deactivate LPM feature. - * @param hpcd: PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) -{ - USB_TypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = DISABLE; - - USBx->LPMCSR &= ~ (USB_LPMCSR_LMPEN); - USBx->LPMCSR &= ~ (USB_LPMCSR_LPMACK); - - return HAL_OK; -} - -#endif /* USB */ - -/** - * @brief Send LPM message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message - * @retval HAL status - */ -__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(msg); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCDEx_LPM_Callback could be implemented in the user file - */ -} - -/** - * @brief Send BatteryCharging message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message - * @retval HAL status - */ -__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(msg); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCDEx_BCD_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* HAL_PCD_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c deleted file mode 100644 index 3f5877b4d..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c +++ /dev/null @@ -1,674 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pwr.c - * @author MCD Application Team - * @brief PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Initialization/de-initialization functions - * + Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup PWR PWR - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup PWR_Private_Defines PWR Private Defines - * @{ - */ - -/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask - * @{ - */ -#define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */ -#define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */ -#define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */ -#define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */ -/** - * @} - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the HAL PWR peripheral registers to their default reset values. - * @retval None - */ -void HAL_PWR_DeInit(void) -{ - __HAL_RCC_PWR_FORCE_RESET(); - __HAL_RCC_PWR_RELEASE_RESET(); -} - -/** - * @brief Enable access to the backup domain - * (RTC registers, RTC backup data registers). - * @note After reset, the backup domain is protected against - * possible unwanted write accesses. - * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain. - * In order to set or modify the RTC clock, the backup domain access must be - * disabled. - * @note LSEON bit that switches on and off the LSE crystal belongs as well to the - * back-up domain. - * @retval None - */ -void HAL_PWR_EnableBkUpAccess(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_DBP); -} - -/** - * @brief Disable access to the backup domain - * (RTC registers, RTC backup data registers). - * @retval None - */ -void HAL_PWR_DisableBkUpAccess(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); -} - - - - -/** - * @} - */ - - - -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @brief Low Power modes configuration functions - * -@verbatim - - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - - [..] - *** PVD configuration *** - ========================= - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a - threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register). - - (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower - than the PVD threshold. This event is internally connected to the EXTI - line16 and can generate an interrupt if enabled. This is done through - __HAL_PVD_EXTI_ENABLE_IT() macro. - (+) The PVD is stopped in Standby mode. - - - *** WakeUp pin configuration *** - ================================ - [..] - (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. - The polarity of these pins can be set to configure event detection on high - level (rising edge) or low level (falling edge). - - - - *** Low Power modes configuration *** - ===================================== - [..] - The devices feature 8 low-power modes: - (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on. - (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on. - (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on. - (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on. - (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on. - (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode. - (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on. - (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off. - (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off. - - - *** Low-power run mode *** - ========================== - [..] - (+) Entry: (from main run mode) - (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. - - (+) Exit: - (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only - then can the system clock frequency be increased above 2 MHz. - - - *** Sleep mode / Low-power sleep mode *** - ========================================= - [..] - (+) Entry: - The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API - in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. - (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). - (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode). - In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand. - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - - (+) WFI Exit: - (++) Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) or any wake-up event. - - (+) WFE Exit: - (++) Any wake-up event such as an EXTI line configured in event mode. - - [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, - the MCU is in Low-power Run mode. - - *** Stop 0, Stop 1 and Stop 2 modes *** - =============================== - [..] - (+) Entry: - The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's: - (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode(). - (++) HAL_PWREx_EnterSTOP2Mode() for mode 2. - (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only): - (++) PWR_MAINREGULATOR_ON - (++) PWR_LOWPOWERREGULATOR_ON - (+) Exit (interrupt or event-triggered, specified when entering STOP mode): - (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction - (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction - - (+) WFI Exit: - (++) Any EXTI Line (Internal or External) configured in Interrupt mode. - (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts - when programmed in wakeup mode. - (+) WFE Exit: - (++) Any EXTI Line (Internal or External) configured in Event mode. - - [..] - When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode - depending on the LPR bit setting. - When exiting Stop 2 mode, the MCU is in Run mode. - - *** Standby mode *** - ==================== - [..] - The Standby mode offers two options: - (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode). - SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers - and Standby circuitry. - (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled). - SRAM and register contents are lost except for the RTC registers, RTC backup registers - and Standby circuitry. - - (++) Entry: - (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. - SRAM1 and register contents are lost except for registers in the Backup domain and - Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. - To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API - to set RRS bit. - - (++) Exit: - (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, - external reset in NRST pin, IWDG reset. - - [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset. - - - *** Shutdown mode *** - ====================== - [..] - In Shutdown mode, - voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared. - SRAM and registers contents are lost except for backup domain registers. - - (+) Entry: - The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API. - - (+) Exit: - (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, - external reset in NRST pin. - - [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset. - - - *** Auto-wakeup (AWU) from low-power mode *** - ============================================= - [..] - The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event or a time-stamp event, without depending on - an external interrupt (Auto-wakeup mode). - - (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes - - - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to - configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. - - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to configure the RTC to detect the tamper or time stamp event using the - HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. - - (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to - configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function. - -@endverbatim - * @{ - */ - - - -/** - * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD). - * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD - * configuration information. - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage thresholds corresponding to each - * detection level. - * @retval None - */ -HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) -{ - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); - assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); - - /* Set PLS bits according to PVDLevel value */ - MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel); - - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) - { - __HAL_PWR_PVD_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) - { - __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - } - - return HAL_OK; -} - - -/** - * @brief Enable the Power Voltage Detector (PVD). - * @retval None - */ -void HAL_PWR_EnablePVD(void) -{ - SET_BIT(PWR->CR2, PWR_CR2_PVDE); -} - -/** - * @brief Disable the Power Voltage Detector (PVD). - * @retval None - */ -void HAL_PWR_DisablePVD(void) -{ - CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); -} - - - - -/** - * @brief Enable the WakeUp PINx functionality. - * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable. - * This parameter can be one of the following legacy values which set the default polarity - * i.e. detection on high level (rising edge): - * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 - * - * or one of the following value where the user can explicitly specify the enabled pin and - * the chosen polarity: - * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW - * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW - * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW - * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW - * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW - * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. - * @retval None - */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) -{ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); - - /* Specifies the Wake-Up pin polarity for the event detection - (rising or falling edge) */ - MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); - - /* Enable wake-up pin */ - SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); - - -} - -/** - * @brief Disable the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. - * This parameter can be one of the following values: - * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 - * @retval None - */ -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) -{ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - - CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); -} - - -/** - * @brief Enter Sleep or Low-power Sleep mode. - * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode. - * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode. - * This parameter can be one of the following values: - * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode) - * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) - * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet - * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set - * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the - * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register. - * Additionally, the clock frequency must be reduced below 2 MHz. - * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must - * be done before calling HAL_PWR_EnterSLEEPMode() API. - * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in - * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API. - * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction - * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction - * @note When WFI entry is used, tick interrupt have to be disabled if not desired as - * the interrupt wake up source. - * @retval None - */ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); - - /* Set Regulator parameter */ - if (Regulator == PWR_MAINREGULATOR_ON) - { - /* If in low-power run mode at this point, exit it */ - if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) - { - HAL_PWREx_DisableLowPowerRunMode(); - } - /* Regulator now in main mode. */ - } - else - { - /* If in run mode, first move to low-power run mode. - The system clock frequency must be below 2 MHz at this point. */ - if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET) - { - HAL_PWREx_EnableLowPowerRunMode(); - } - } - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select SLEEP mode entry -------------------------------------------------*/ - if(SLEEPEntry == PWR_SLEEPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - -} - - -/** - * @brief Enter Stop mode - * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running - * on devices where only "Stop mode" is mentioned with main or low power regulator ON. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated - * only to the peripheral requesting it. - * SRAM1, SRAM2 and register contents are preserved. - * The BOR is available. - * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1). - * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. - * @note When the voltage regulator operates in low power mode (Stop 1), an additional - * startup delay is incurred when waking up. - * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption - * is higher although the startup time is reduced. - * @param Regulator: Specifies the regulator state in Stop mode. - * This parameter can be one of the following values: - * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON) - * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON) - * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction. - * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction. - * @retval None - */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - - if(Regulator == PWR_LOWPOWERREGULATOR_ON) - { - HAL_PWREx_EnterSTOP1Mode(STOPEntry); - } - else - { - HAL_PWREx_EnterSTOP0Mode(STOPEntry); - } -} - -/** - * @brief Enter Standby mode. - * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched - * off. The voltage regulator is disabled, except when SRAM2 content is preserved - * in which case the regulator is in low-power mode. - * SRAM1 and register contents are lost except for registers in the Backup domain and - * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. - * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API - * to set RRS bit. - * The BOR is available. - * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. - * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and - * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the - * same. - * These states are effective in Standby mode only if APC bit is set through - * HAL_PWREx_EnablePullUpPullDownConfig() API. - * @retval None - */ -void HAL_PWR_EnterSTANDBYMode(void) -{ - /* Set Stand-by mode */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - - - -/** - * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. - * @retval None - */ -void HAL_PWR_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - - -/** - * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * @retval None - */ -void HAL_PWR_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - - - -/** - * @brief Enable CORTEX M4 SEVONPEND bit. - * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_EnableSEVOnPend(void) -{ - /* Set SEVONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - - -/** - * @brief Disable CORTEX M4 SEVONPEND bit. - * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_DisableSEVOnPend(void) -{ - /* Clear SEVONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - - - - - -/** - * @brief PWR PVD interrupt callback - * @retval None - */ -__weak void HAL_PWR_PVDCallback(void) -{ - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_PWR_PVDCallback can be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c deleted file mode 100644 index 1c08c0fef..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c +++ /dev/null @@ -1,1399 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_pwr_ex.c - * @author MCD Application Team - * @brief Extended PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Extended Initialization and de-initialization functions - * + Extended Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup PWREx PWREx - * @brief PWR Extended HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) -#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */ -#elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) -#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */ -#elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) -#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x00000003) /* PH0/PH1 */ -#elif defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000FFFF) /* PH0..PH15 */ -#endif - -#if defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) -#define PWR_PORTI_AVAILABLE_PINS ((uint32_t)0x00000FFF) /* PI0..PI11 */ -#endif - -/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines - * @{ - */ - -/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask - * @{ - */ -#define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */ -#define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */ -#define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */ -#define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */ -/** - * @} - */ - -/** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value - * @{ - */ -#define PWR_FLAG_SETTING_DELAY_US 50 /*!< Time out value for REGLPF and VOSF flags setting */ -/** - * @} - */ - - - -/** - * @} - */ - - - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions - * @{ - */ - -/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Initialization and de-initialization functions ##### - =============================================================================== - [..] - -@endverbatim - * @{ - */ - - -/** - * @brief Return Voltage Scaling Range. - * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2 - * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable) - */ -uint32_t HAL_PWREx_GetVoltageRange(void) -{ -#if defined(PWR_CR5_R1MODE) - if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) - { - return PWR_REGULATOR_VOLTAGE_SCALE2; - } - else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE) - { - /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */ - return PWR_REGULATOR_VOLTAGE_SCALE1; - } - else - { - return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST; - } -#else - return (PWR->CR1 & PWR_CR1_VOS); -#endif -} - - - -/** - * @brief Configure the main internal regulator output voltage. - * @param VoltageScaling: specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption. - * This parameter can be one of the following values: - @if STM32L4S9xx - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode, - * typical output voltage at 1.2 V, - * system frequency up to 120 MHz. - @endif - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, - * typical output voltage at 1.2 V, - * system frequency up to 80 MHz. - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, - * typical output voltage at 1.0 V, - * system frequency up to 26 MHz. - * @note When moving from Range 1 to Range 2, the system frequency must be decreased to - * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. - * When moving from Range 2 to Range 1, the system frequency can be increased to - * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. For - * some devices, the system frequency can be increased up to 120 MHz. - * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be - * cleared before returning the status. If the flag is not cleared within - * 50 microseconds, HAL_TIMEOUT status is reported. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) -{ - uint32_t wait_loop_index = 0; - - assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); - -#if defined(PWR_CR5_R1MODE) - if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) - { - /* If current range is range 2 */ - if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) - { - /* Make sure Range 1 Boost is enabled */ - CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); - - /* Set Range 1 */ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Wait until VOSF is cleared */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) - { - wait_loop_index--; - } - if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) - { - return HAL_TIMEOUT; - } - } - /* If current range is range 1 normal or boost mode */ - else - { - /* Enable Range 1 Boost (no issue if bit already reset) */ - CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); - } - } - else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) - { - /* If current range is range 2 */ - if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) - { - /* Make sure Range 1 Boost is disabled */ - SET_BIT(PWR->CR5, PWR_CR5_R1MODE); - - /* Set Range 1 */ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Wait until VOSF is cleared */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) - { - wait_loop_index--; - } - if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) - { - return HAL_TIMEOUT; - } - } - /* If current range is range 1 normal or boost mode */ - else - { - /* Disable Range 1 Boost (no issue if bit already set) */ - SET_BIT(PWR->CR5, PWR_CR5_R1MODE); - } - } - else - { - /* Set Range 2 */ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); - /* No need to wait for VOSF to be cleared for this transition */ - /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ - } - -#else - - /* If Set Range 1 */ - if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) - { - if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1) - { - /* Set Range 1 */ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); - - /* Wait until VOSF is cleared */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) - { - wait_loop_index--; - } - if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) - { - return HAL_TIMEOUT; - } - } - } - else - { - if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2) - { - /* Set Range 2 */ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); - /* No need to wait for VOSF to be cleared for this transition */ - } - } -#endif - - return HAL_OK; -} - - -/** - * @brief Enable battery charging. - * When VDD is present, charge the external battery on VBAT thru an internal resistor. - * @param ResistorSelection: specifies the resistor impedance. - * This parameter can be one of the following values: - * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor - * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor - * @retval None - */ -void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) -{ - assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); - - /* Specify resistor selection */ - MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); - - /* Enable battery charging */ - SET_BIT(PWR->CR4, PWR_CR4_VBE); -} - - -/** - * @brief Disable battery charging. - * @retval None - */ -void HAL_PWREx_DisableBatteryCharging(void) -{ - CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); -} - - -#if defined(PWR_CR2_USV) -/** - * @brief Enable VDDUSB supply. - * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. - * @retval None - */ -void HAL_PWREx_EnableVddUSB(void) -{ - SET_BIT(PWR->CR2, PWR_CR2_USV); -} - - -/** - * @brief Disable VDDUSB supply. - * @retval None - */ -void HAL_PWREx_DisableVddUSB(void) -{ - CLEAR_BIT(PWR->CR2, PWR_CR2_USV); -} -#endif /* PWR_CR2_USV */ - -#if defined(PWR_CR2_IOSV) -/** - * @brief Enable VDDIO2 supply. - * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. - * @retval None - */ -void HAL_PWREx_EnableVddIO2(void) -{ - SET_BIT(PWR->CR2, PWR_CR2_IOSV); -} - - -/** - * @brief Disable VDDIO2 supply. - * @retval None - */ -void HAL_PWREx_DisableVddIO2(void) -{ - CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); -} -#endif /* PWR_CR2_IOSV */ - - -/** - * @brief Enable Internal Wake-up Line. - * @retval None - */ -void HAL_PWREx_EnableInternalWakeUpLine(void) -{ - SET_BIT(PWR->CR3, PWR_CR3_EIWF); -} - - -/** - * @brief Disable Internal Wake-up Line. - * @retval None - */ -void HAL_PWREx_DisableInternalWakeUpLine(void) -{ - CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); -} - - - -/** - * @brief Enable GPIO pull-up state in Standby and Shutdown modes. - * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in - * pull-up state in Standby and Shutdown modes. - * @note This state is effective in Standby and Shutdown modes only if APC bit - * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. - * @note The configuration is lost when exiting the Shutdown mode due to the - * power-on reset, maintained when exiting the Standby mode. - * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding - * PDy bit of PWR_PDCRx register is cleared unless it is reserved. - * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input - * parameter at the same time are set. - * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H - * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. - * @param GPIONumber: Specify the I/O pins numbers. - * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to set - * several bits for a given port in a single API call. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) -{ - assert_param(IS_PWR_GPIO(GPIO)); - assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - - switch (GPIO) - { - case PWR_GPIO_A: - SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); - CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); - break; - case PWR_GPIO_B: - SET_BIT(PWR->PUCRB, GPIONumber); - CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); - break; - case PWR_GPIO_C: - SET_BIT(PWR->PUCRC, GPIONumber); - CLEAR_BIT(PWR->PDCRC, GPIONumber); - break; -#if defined(GPIOD) - case PWR_GPIO_D: - SET_BIT(PWR->PUCRD, GPIONumber); - CLEAR_BIT(PWR->PDCRD, GPIONumber); - break; -#endif -#if defined(GPIOE) - case PWR_GPIO_E: - SET_BIT(PWR->PUCRE, GPIONumber); - CLEAR_BIT(PWR->PDCRE, GPIONumber); - break; -#endif -#if defined(GPIOF) - case PWR_GPIO_F: - SET_BIT(PWR->PUCRF, GPIONumber); - CLEAR_BIT(PWR->PDCRF, GPIONumber); - break; -#endif -#if defined(GPIOG) - case PWR_GPIO_G: - SET_BIT(PWR->PUCRG, GPIONumber); - CLEAR_BIT(PWR->PDCRG, GPIONumber); - break; -#endif - case PWR_GPIO_H: - SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); -#if defined (STM32L496xx) || defined (STM32L4A6xx) - CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); -#else - CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); -#endif - break; -#if defined(GPIOI) - case PWR_GPIO_I: - SET_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); - CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); - break; -#endif - default: - return HAL_ERROR; - } - - return HAL_OK; -} - - -/** - * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. - * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O - * in pull-up state in Standby and Shutdown modes. - * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input - * parameter at the same time are reset. - * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H - * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. - * @param GPIONumber: Specify the I/O pins numbers. - * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to reset - * several bits for a given port in a single API call. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) -{ - assert_param(IS_PWR_GPIO(GPIO)); - assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - - switch (GPIO) - { - case PWR_GPIO_A: - CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); - break; - case PWR_GPIO_B: - CLEAR_BIT(PWR->PUCRB, GPIONumber); - break; - case PWR_GPIO_C: - CLEAR_BIT(PWR->PUCRC, GPIONumber); - break; -#if defined(GPIOD) - case PWR_GPIO_D: - CLEAR_BIT(PWR->PUCRD, GPIONumber); - break; -#endif -#if defined(GPIOE) - case PWR_GPIO_E: - CLEAR_BIT(PWR->PUCRE, GPIONumber); - break; -#endif -#if defined(GPIOF) - case PWR_GPIO_F: - CLEAR_BIT(PWR->PUCRF, GPIONumber); - break; -#endif -#if defined(GPIOG) - case PWR_GPIO_G: - CLEAR_BIT(PWR->PUCRG, GPIONumber); - break; -#endif - case PWR_GPIO_H: - CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); - break; -#if defined(GPIOI) - case PWR_GPIO_I: - CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); - break; -#endif - default: - return HAL_ERROR; - } - - return HAL_OK; -} - - - -/** - * @brief Enable GPIO pull-down state in Standby and Shutdown modes. - * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in - * pull-down state in Standby and Shutdown modes. - * @note This state is effective in Standby and Shutdown modes only if APC bit - * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. - * @note The configuration is lost when exiting the Shutdown mode due to the - * power-on reset, maintained when exiting the Standby mode. - * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding - * PUy bit of PWR_PUCRx register is cleared unless it is reserved. - * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input - * parameter at the same time are set. - * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H - * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. - * @param GPIONumber: Specify the I/O pins numbers. - * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to set - * several bits for a given port in a single API call. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) -{ - assert_param(IS_PWR_GPIO(GPIO)); - assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - - switch (GPIO) - { - case PWR_GPIO_A: - SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); - CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); - break; - case PWR_GPIO_B: - SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); - CLEAR_BIT(PWR->PUCRB, GPIONumber); - break; - case PWR_GPIO_C: - SET_BIT(PWR->PDCRC, GPIONumber); - CLEAR_BIT(PWR->PUCRC, GPIONumber); - break; -#if defined(GPIOD) - case PWR_GPIO_D: - SET_BIT(PWR->PDCRD, GPIONumber); - CLEAR_BIT(PWR->PUCRD, GPIONumber); - break; -#endif -#if defined(GPIOE) - case PWR_GPIO_E: - SET_BIT(PWR->PDCRE, GPIONumber); - CLEAR_BIT(PWR->PUCRE, GPIONumber); - break; -#endif -#if defined(GPIOF) - case PWR_GPIO_F: - SET_BIT(PWR->PDCRF, GPIONumber); - CLEAR_BIT(PWR->PUCRF, GPIONumber); - break; -#endif -#if defined(GPIOG) - case PWR_GPIO_G: - SET_BIT(PWR->PDCRG, GPIONumber); - CLEAR_BIT(PWR->PUCRG, GPIONumber); - break; -#endif - case PWR_GPIO_H: -#if defined (STM32L496xx) || defined (STM32L4A6xx) - SET_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); -#else - SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); -#endif - CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); - break; -#if defined(GPIOI) - case PWR_GPIO_I: - SET_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); - CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); - break; -#endif - default: - return HAL_ERROR; - } - - return HAL_OK; -} - - -/** - * @brief Disable GPIO pull-down state in Standby and Shutdown modes. - * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O - * in pull-down state in Standby and Shutdown modes. - * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input - * parameter at the same time are reset. - * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H - * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. - * @param GPIONumber: Specify the I/O pins numbers. - * This parameter can be one of the following values: - * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less - * I/O pins are available) or the logical OR of several of them to reset - * several bits for a given port in a single API call. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) -{ - assert_param(IS_PWR_GPIO(GPIO)); - assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); - - switch (GPIO) - { - case PWR_GPIO_A: - CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); - break; - case PWR_GPIO_B: - CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); - break; - case PWR_GPIO_C: - CLEAR_BIT(PWR->PDCRC, GPIONumber); - break; -#if defined(GPIOD) - case PWR_GPIO_D: - CLEAR_BIT(PWR->PDCRD, GPIONumber); - break; -#endif -#if defined(GPIOE) - case PWR_GPIO_E: - CLEAR_BIT(PWR->PDCRE, GPIONumber); - break; -#endif -#if defined(GPIOF) - case PWR_GPIO_F: - CLEAR_BIT(PWR->PDCRF, GPIONumber); - break; -#endif -#if defined(GPIOG) - case PWR_GPIO_G: - CLEAR_BIT(PWR->PDCRG, GPIONumber); - break; -#endif - case PWR_GPIO_H: -#if defined (STM32L496xx) || defined (STM32L4A6xx) - CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); -#else - CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); -#endif - break; -#if defined(GPIOI) - case PWR_GPIO_I: - CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); - break; -#endif - default: - return HAL_ERROR; - } - - return HAL_OK; -} - - - -/** - * @brief Enable pull-up and pull-down configuration. - * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in - * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. - * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding - * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). - * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there - * is no conflict when setting PUy or PDy bit. - * @retval None - */ -void HAL_PWREx_EnablePullUpPullDownConfig(void) -{ - SET_BIT(PWR->CR3, PWR_CR3_APC); -} - - -/** - * @brief Disable pull-up and pull-down configuration. - * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in - * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. - * @retval None - */ -void HAL_PWREx_DisablePullUpPullDownConfig(void) -{ - CLEAR_BIT(PWR->CR3, PWR_CR3_APC); -} - - - -/** - * @brief Enable SRAM2 content retention in Standby mode. - * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in - * Standby mode and its content is kept. - * @retval None - */ -void HAL_PWREx_EnableSRAM2ContentRetention(void) -{ - SET_BIT(PWR->CR3, PWR_CR3_RRS); -} - - -/** - * @brief Disable SRAM2 content retention in Standby mode. - * @note When RRS bit is reset, SRAM2 is powered off in Standby mode - * and its content is lost. - * @retval None - */ -void HAL_PWREx_DisableSRAM2ContentRetention(void) -{ - CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); -} - - -#if defined(PWR_CR1_RRSTP) -/** - * @brief Enable SRAM3 content retention in Stop 2 mode. - * @note When RRSTP bit is set, SRAM3 is powered by the low-power regulator in - * Stop 2 mode and its content is kept. - * @retval None - */ -void HAL_PWREx_EnableSRAM3ContentRetention(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_RRSTP); -} - - -/** - * @brief Disable SRAM3 content retention in Stop 2 mode. - * @note When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode - * and its content is lost. - * @retval None - */ -void HAL_PWREx_DisableSRAM3ContentRetention(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP); -} -#endif /* PWR_CR1_RRSTP */ - -#if defined(PWR_CR3_DSIPDEN) -/** - * @brief Enable pull-down activation on DSI pins. - * @retval None - */ -void HAL_PWREx_EnableDSIPinsPDActivation(void) -{ - SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); -} - - -/** - * @brief Disable pull-down activation on DSI pins. - * @retval None - */ -void HAL_PWREx_DisableDSIPinsPDActivation(void) -{ - CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); -} -#endif /* PWR_CR3_DSIPDEN */ - -#if defined(PWR_CR2_PVME1) -/** - * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. - * @retval None - */ -void HAL_PWREx_EnablePVM1(void) -{ - SET_BIT(PWR->CR2, PWR_PVM_1); -} - -/** - * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. - * @retval None - */ -void HAL_PWREx_DisablePVM1(void) -{ - CLEAR_BIT(PWR->CR2, PWR_PVM_1); -} -#endif /* PWR_CR2_PVME1 */ - - -#if defined(PWR_CR2_PVME2) -/** - * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V. - * @retval None - */ -void HAL_PWREx_EnablePVM2(void) -{ - SET_BIT(PWR->CR2, PWR_PVM_2); -} - -/** - * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V. - * @retval None - */ -void HAL_PWREx_DisablePVM2(void) -{ - CLEAR_BIT(PWR->CR2, PWR_PVM_2); -} -#endif /* PWR_CR2_PVME2 */ - - -/** - * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V. - * @retval None - */ -void HAL_PWREx_EnablePVM3(void) -{ - SET_BIT(PWR->CR2, PWR_PVM_3); -} - -/** - * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V. - * @retval None - */ -void HAL_PWREx_DisablePVM3(void) -{ - CLEAR_BIT(PWR->CR2, PWR_PVM_3); -} - - -/** - * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V. - * @retval None - */ -void HAL_PWREx_EnablePVM4(void) -{ - SET_BIT(PWR->CR2, PWR_PVM_4); -} - -/** - * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V. - * @retval None - */ -void HAL_PWREx_DisablePVM4(void) -{ - CLEAR_BIT(PWR->CR2, PWR_PVM_4); -} - - - - -/** - * @brief Configure the Peripheral Voltage Monitoring (PVM). - * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the - * PVM configuration information. - * @note The API configures a single PVM according to the information contained - * in the input structure. To configure several PVMs, the API must be singly - * called for each PVM used. - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage thresholds corresponding to each - * detection level and to each monitored supply. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) -{ - /* Check the parameters */ - assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); - assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); - - - /* Configure EXTI 35 to 38 interrupts if so required: - scan thru PVMType to detect which PVMx is set and - configure the corresponding EXTI line accordingly. */ - switch (sConfigPVM->PVMType) - { -#if defined(PWR_CR2_PVME1) - case PWR_PVM_1: - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVM1_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVM1_EXTI_DISABLE_IT(); - __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); - __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) - { - __HAL_PWR_PVM1_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) - { - __HAL_PWR_PVM1_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) - { - __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) - { - __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); - } - break; -#endif /* PWR_CR2_PVME1 */ - -#if defined(PWR_CR2_PVME2) - case PWR_PVM_2: - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVM2_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVM2_EXTI_DISABLE_IT(); - __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); - __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) - { - __HAL_PWR_PVM2_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) - { - __HAL_PWR_PVM2_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) - { - __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) - { - __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); - } - break; -#endif /* PWR_CR2_PVME2 */ - - case PWR_PVM_3: - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVM3_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVM3_EXTI_DISABLE_IT(); - __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); - __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) - { - __HAL_PWR_PVM3_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) - { - __HAL_PWR_PVM3_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) - { - __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) - { - __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); - } - break; - - case PWR_PVM_4: - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVM4_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVM4_EXTI_DISABLE_IT(); - __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); - __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) - { - __HAL_PWR_PVM4_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) - { - __HAL_PWR_PVM4_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) - { - __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) - { - __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); - } - break; - - default: - return HAL_ERROR; - - } - - - return HAL_OK; -} - - - -/** - * @brief Enter Low-power Run mode - * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. - * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the - * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register. - * Additionally, the clock frequency must be reduced below 2 MHz. - * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must - * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. - * @retval None - */ -void HAL_PWREx_EnableLowPowerRunMode(void) -{ - /* Set Regulator parameter */ - SET_BIT(PWR->CR1, PWR_CR1_LPR); -} - - -/** - * @brief Exit Low-power Run mode. - * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that - * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode - * returns HAL_TIMEOUT status). The system clock frequency can then be - * increased above 2 MHz. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) -{ - uint32_t wait_loop_index = 0; - - /* Clear LPR bit */ - CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); - - /* Wait until REGLPF is reset */ - wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); - while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))) - { - wait_loop_index--; - } - if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) - { - return HAL_TIMEOUT; - } - - return HAL_OK; -} - - -/** - * @brief Enter Stop 0 mode. - * @note In Stop 0 mode, main and low voltage regulators are ON. - * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated - * only to the peripheral requesting it. - * SRAM1, SRAM2 and register contents are preserved. - * The BOR is available. - * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. - * @note By keeping the internal regulator ON during Stop 0 mode, the consumption - * is higher although the startup time is reduced. - * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction - * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction - * @retval None - */ -void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Stop 0 mode with Main Regulator */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - - -/** - * @brief Enter Stop 1 mode. - * @note In Stop 1 mode, only low power voltage regulator is ON. - * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability - * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI - * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated - * only to the peripheral requesting it. - * SRAM1, SRAM2 and register contents are preserved. - * The BOR is available. - * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. - * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode. - * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction - * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction - * @retval None - */ -void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Stop 1 mode with Low-Power Regulator */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - - -/** - * @brief Enter Stop 2 mode. - * @note In Stop 2 mode, only low power voltage regulator is ON. - * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode. - * @note All clocks in the VCORE domain are stopped, the PLL, the MSI, - * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability - * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after - * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only - * to the peripheral requesting it. - * SRAM1, SRAM2 and register contents are preserved. - * The BOR is available. - * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode. - * Otherwise, Stop 1 mode is entered. - * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register - * is set; the MSI oscillator is selected if STOPWUCK is cleared. - * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction - * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction - * @retval None - */ -void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) -{ - /* Check the parameter */ - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Set Stop mode 2 */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - - - - - -/** - * @brief Enter Shutdown mode. - * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched - * off. The voltage regulator is disabled and Vcore domain is powered off. - * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain. - * The BOR is not available. - * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. - * @retval None - */ -void HAL_PWREx_EnterSHUTDOWNMode(void) -{ - - /* Set Shutdown mode */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - - - - -/** - * @brief This function handles the PWR PVD/PVMx interrupt request. - * @note This API should be called under the PVD_PVM_IRQHandler(). - * @retval None - */ -void HAL_PWREx_PVD_PVM_IRQHandler(void) -{ - /* Check PWR exti flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) - { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - - /* Clear PVD exti pending bit */ - __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); - } - /* Next, successively check PVMx exti flags */ -#if defined(PWR_CR2_PVME1) - if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET) - { - /* PWR PVM1 interrupt user callback */ - HAL_PWREx_PVM1Callback(); - - /* Clear PVM1 exti pending bit */ - __HAL_PWR_PVM1_EXTI_CLEAR_FLAG(); - } -#endif /* PWR_CR2_PVME1 */ -#if defined(PWR_CR2_PVME2) - if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET) - { - /* PWR PVM2 interrupt user callback */ - HAL_PWREx_PVM2Callback(); - - /* Clear PVM2 exti pending bit */ - __HAL_PWR_PVM2_EXTI_CLEAR_FLAG(); - } -#endif /* PWR_CR2_PVME2 */ - if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET) - { - /* PWR PVM3 interrupt user callback */ - HAL_PWREx_PVM3Callback(); - - /* Clear PVM3 exti pending bit */ - __HAL_PWR_PVM3_EXTI_CLEAR_FLAG(); - } - if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET) - { - /* PWR PVM4 interrupt user callback */ - HAL_PWREx_PVM4Callback(); - - /* Clear PVM4 exti pending bit */ - __HAL_PWR_PVM4_EXTI_CLEAR_FLAG(); - } -} - - -#if defined(PWR_CR2_PVME1) -/** - * @brief PWR PVM1 interrupt callback - * @retval None - */ -__weak void HAL_PWREx_PVM1Callback(void) -{ - /* NOTE : This function should not be modified; when the callback is needed, - HAL_PWREx_PVM1Callback() API can be implemented in the user file - */ -} -#endif /* PWR_CR2_PVME1 */ - -#if defined(PWR_CR2_PVME2) -/** - * @brief PWR PVM2 interrupt callback - * @retval None - */ -__weak void HAL_PWREx_PVM2Callback(void) -{ - /* NOTE : This function should not be modified; when the callback is needed, - HAL_PWREx_PVM2Callback() API can be implemented in the user file - */ -} -#endif /* PWR_CR2_PVME2 */ - -/** - * @brief PWR PVM3 interrupt callback - * @retval None - */ -__weak void HAL_PWREx_PVM3Callback(void) -{ - /* NOTE : This function should not be modified; when the callback is needed, - HAL_PWREx_PVM3Callback() API can be implemented in the user file - */ -} - -/** - * @brief PWR PVM4 interrupt callback - * @retval None - */ -__weak void HAL_PWREx_PVM4Callback(void) -{ - /* NOTE : This function should not be modified; when the callback is needed, - HAL_PWREx_PVM4Callback() API can be implemented in the user file - */ -} - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c deleted file mode 100644 index 06a9b2665..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c +++ /dev/null @@ -1,1730 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rcc.c - * @author MCD Application Team - * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Reset and Clock Control (RCC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### RCC specific features ##### - ============================================================================== - [..] - After reset the device is running from Multiple Speed Internal oscillator - (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache - and I-Cache are disabled, and all peripherals are off except internal - SRAM, Flash and JTAG. - - (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses: - all peripherals mapped on these busses are running at MSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in analog mode, except the JTAG pins which - are assigned to be used for debug purpose. - - [..] - Once the device started from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB busses prescalers - (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals which clocks are not - derived from the System clock (SAIx, RTC, ADC, USB OTG FS/SDMMC1/RNG) - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup RCC RCC - * @brief RCC HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup RCC_Private_Constants RCC Private Constants - * @{ - */ -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define MSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define HSI48_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCC_Private_Macros RCC Private Macros - * @{ - */ -#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 - -#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ - (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__))) -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup RCC_Private_Functions RCC Private Functions - * @{ - */ -static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -static uint32_t RCC_GetSysClockFreqFromPLLSource(void); -#endif -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the internal and external oscillators - (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 - and APB2). - - [..] Internal/external clock and PLL configuration - (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ. - It can be used to generate the clock for the USB OTG FS (48 MHz). - The number of flash wait states is automatically adjusted when MSI range is updated with - HAL_RCC_OscConfig() and the MSI is used as System clock source. - - (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC - clock source. - - (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also optionally as RTC clock source. - - (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source. - - (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks: - (++) The first output is used to generate the high speed system clock (up to 80MHz). - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). - (++) The third output is used to generate an accurate clock to achieve - high-quality audio performance on SAI interface. - - (+) PLLSAI1 (clocked by HSI, HSE or MSI) providing up to three independent output clocks: - (++) The first output is used to generate SAR ADC1 clock. - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). - (++) The Third output is used to generate an accurate clock to achieve - high-quality audio performance on SAI interface. - - (+) PLLSAI2 (clocked by HSI , HSE or MSI) providing up to two independent output clocks: - (++) The first output is used to generate SAR ADC2 clock. - (++) The second output is used to generate an accurate clock to achieve - high-quality audio performance on SAI interface. - - (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs - (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to HSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) - exception vector. - - (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or - main PLL clock (through a configurable prescaler) on PA8 pin. - - [..] System, AHB and APB busses clocks configuration - (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, - HSE and main PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. - - -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: - - (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLSAI1) or (PLLSAI2) or - from an external clock mapped on the SAI_CKIN pin. - You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. - (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 31. - You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function - to configure this clock. - (+@) USB OTG FS, SDMMC1 and RNG: USB OTG FS requires a frequency equal to 48 MHz - to work correctly, while the SDMMC1 and RNG peripherals require a frequency - equal or lower than to 48 MHz. This clock is derived of the main PLL or PLLSAI1 - through PLLQ divider. You have to enable the peripheral clock and use - HAL_RCCEx_PeriphCLKConfig() function to configure this clock. - (+@) IWDG clock which is always the LSI clock. - - - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz. - The clock source frequency should be adapted depending on the device voltage range - as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter. - - @endverbatim - - Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices - +--------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |--------------------------------------| - | | voltage range 1 | voltage range 2 | - | | 1.2 V | 1.0 V | - |-----------------|-------------------|------------------| - |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 | - |-----------------|-------------------|------------------| - |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 8 < HCLK <= 16 | - |-----------------|-------------------|------------------| - |2WS(3 CPU cycles)| 40 < HCLK <= 60 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |3WS(4 CPU cycles)| 60 < HCLK <= 80 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |4WS(5 CPU cycles)| 80 < HCLK <= 100 | 16 < HCLK <= 26 | - |-----------------|-------------------|------------------| - |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26 | - +--------------------------------------------------------+ - - Table 2. HCLK clock frequency for other STM32L4 devices - +-------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |-------------------------------------| - | | voltage range 1 | voltage range 2 | - | | 1.2 V | 1.0 V | - |-----------------|------------------|------------------| - |0WS(1 CPU cycles)| 0 < HCLK <= 16 | 0 < HCLK <= 6 | - |-----------------|------------------|------------------| - |1WS(2 CPU cycles)| 16 < HCLK <= 32 | 6 < HCLK <= 12 | - |-----------------|------------------|------------------| - |2WS(3 CPU cycles)| 32 < HCLK <= 48 | 12 < HCLK <= 18 | - |-----------------|------------------|------------------| - |3WS(4 CPU cycles)| 48 < HCLK <= 64 | 18 < HCLK <= 26 | - |-----------------|------------------|------------------| - |4WS(5 CPU cycles)| 64 < HCLK <= 80 | 18 < HCLK <= 26 | - +-------------------------------------------------------+ - * @{ - */ - -/** - * @brief Reset the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - MSI ON and used as system clock source - * - HSE, HSI, PLL, PLLSAI1 and PLLISAI2 OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 OFF - * - All interrupts disabled - * - All interrupt and reset flags cleared - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_DeInit(void) -{ - uint32_t tickstart = 0; - - /* Set MSION bit */ - SET_BIT(RCC->CR, RCC_CR_MSION); - - /* Insure MSIRDY bit is set before writing default MSIRANGE value */ - /* Get start tick */ - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set MSIRANGE default value */ - MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, RCC_MSIRANGE_6); - - /* Reset CFGR register (MSI is selected as system clock source) */ - CLEAR_REG(RCC->CFGR); - - /* Update the SystemCoreClock global variable for MSI as system clock source */ - SystemCoreClock = MSI_VALUE; - - /* Configure the source of time base considering new system clock settings */ - if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) - { - return HAL_ERROR; - } - - /* Insure MSI selected as system clock source */ - /* Get start tick */ - tickstart = HAL_GetTick(); - - /* Wait till system clock source is ready */ - while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */ -#if defined(RCC_PLLSAI2_SUPPORT) - - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON); - -#else - - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON| RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON); - -#endif /* RCC_PLLSAI2_SUPPORT */ - - /* Insure PLLRDY, PLLSAI1RDY and PLLSAI2RDY (if present) are reset */ - /* Get start tick */ - tickstart = HAL_GetTick(); - -#if defined(RCC_PLLSAI2_SUPPORT) - - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) - -#else - - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) - -#endif - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Reset PLLCFGR register */ - CLEAR_REG(RCC->PLLCFGR); - SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4 ); - - /* Reset PLLSAI1CFGR register */ - CLEAR_REG(RCC->PLLSAI1CFGR); - SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N_4 ); - -#if defined(RCC_PLLSAI2_SUPPORT) - - /* Reset PLLSAI2CFGR register */ - CLEAR_REG(RCC->PLLSAI2CFGR); - SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N_4 ); - -#endif /* RCC_PLLSAI2_SUPPORT */ - - /* Reset HSEBYP bit */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - - /* Disable all interrupts */ - CLEAR_REG(RCC->CIER); - - /* Clear all interrupt flags */ - WRITE_REG(RCC->CICR, 0xFFFFFFFFU); - - /* Clear all reset flags */ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); - - return HAL_OK; -} - -/** - * @brief Initialize the RCC Oscillators according to the specified parameters in the - * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC Oscillators. - * @note The PLL is not disabled when used as system clock. - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this macro. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(RCC_OscInitStruct != NULL); - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - - /*----------------------------- MSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) - { - /* Check the parameters */ - assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); - assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); - assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); - - /* When the MSI is used as system clock it will not be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) ) - { - if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) - { - return HAL_ERROR; - } - - /* Otherwise, just the calibration and MSI range change are allowed */ - else - { - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ - if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) - { - /* First increase number of wait states update if necessary */ - if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) - { - return HAL_ERROR; - } - - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - } - else - { - /* Else, keep current flash latency while decreasing applies */ - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - - /* Decrease number of wait states update if necessary */ - if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) - { - return HAL_ERROR; - } - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; - - /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick (TICK_INT_PRIORITY); - } - } - else - { - /* Check the MSI State */ - if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) - { - /* Enable the Internal High Speed oscillator (MSI). */ - __HAL_RCC_MSI_ENABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - - } - else - { - /* Disable the Internal High Speed oscillator (MSI). */ - __HAL_RCC_MSI_DISABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - - /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) - { - if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - { - return HAL_ERROR; - } - } - else - { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - - /* Check the HSE State */ - if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) - { - if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) - { - /* When HSI is used as system clock it will not be disabled */ - if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - } - else - { - /* Check the HSI State */ - if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is disabled */ - while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - { - FlagStatus pwrclkchanged = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Update LSE configuration in Backup Domain control register */ - /* Requires to enable write access to Backup Domain of necessary */ - if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR1, PWR_CR1_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - - /* Check the LSE State */ - if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is disabled */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != RESET) - { - if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Restore clock configuration if changed */ - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } -#if defined(RCC_HSI48_SUPPORT) - /*------------------------------ HSI48 Configuration -----------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); - - /* Check the LSI State */ - if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) - { - /* Enable the Internal Low Speed oscillator (HSI48). */ - __HAL_RCC_HSI48_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI48 is ready */ - while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (HSI48). */ - __HAL_RCC_HSI48_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI48 is disabled */ - while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } -#endif /* RCC_HSI48_SUPPORT */ - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - - if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) - { - /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { - if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); - assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); - assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); - assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the main PLL clock source, multiplication and division factors. */ - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - RCC_OscInitStruct->PLL.PLLM, - RCC_OscInitStruct->PLL.PLLN, - RCC_OscInitStruct->PLL.PLLP, - RCC_OscInitStruct->PLL.PLLQ, - RCC_OscInitStruct->PLL.PLLR); - - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - - /* Enable PLL System Clock output. */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Disable all PLL outputs to save power if no PLLs on */ - if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) -#if defined(RCC_PLLSAI2_SUPPORT) - && - (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) -#endif /* RCC_PLLSAI2_SUPPORT */ - ) - { - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); - } - -#if defined(RCC_PLLSAI2_SUPPORT) - __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK); -#else - __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK); -#endif /* RCC_PLLSAI2_SUPPORT */ - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is disabled */ - while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - else - { - return HAL_ERROR; - } - } - return HAL_OK; -} - -/** - * @brief Initialize the CPU, AHB and APB busses clocks according to the specified - * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC peripheral. - * @param FLatency FLASH Latency - * This parameter can be one of the following values: - * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle - * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle - * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles - * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles - * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles - @if STM32L4S9xx - * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles - * @arg FLASH_LATENCY_6 FLASH 6 Latency cycles - * @arg FLASH_LATENCY_7 FLASH 7 Latency cycles - * @arg FLASH_LATENCY_8 FLASH 8 Latency cycles - * @arg FLASH_LATENCY_9 FLASH 9 Latency cycles - * @arg FLASH_LATENCY_10 FLASH 10 Latency cycles - * @arg FLASH_LATENCY_11 FLASH 11 Latency cycles - * @arg FLASH_LATENCY_12 FLASH 12 Latency cycles - * @arg FLASH_LATENCY_13 FLASH 13 Latency cycles - * @arg FLASH_LATENCY_14 FLASH 14 Latency cycles - * @arg FLASH_LATENCY_15 FLASH 15 Latency cycles - @endif - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated by HAL_RCC_GetHCLKFreq() function called within this function - * - * @note The MSI is used by default as system clock source after - * startup from Reset, wake-up from STANDBY mode. After restart from Reset, - * the MSI frequency is set to its default value 4 MHz. - * - * @note The HSI can be selected as system clock source after - * from STOP modes or in case of failure of the HSE used directly or indirectly - * as system clock (if the Clock Security System CSS is enabled). - * - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source is ready. - * - * @note You can use HAL_RCC_GetClockConfig() function to know which clock is - * currently used as system clock source. - * - * @note Depending on the device voltage range, the software has to set correctly - * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above "Initialization/de-initialization functions") - * @retval None - */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) -{ - uint32_t tickstart = 0; -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - uint32_t pllfreq = 0; - uint32_t hpre = RCC_SYSCLK_DIV1; -#endif - - /* Check the parameters */ - assert_param(RCC_ClkInitStruct != NULL); - assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); - assert_param(IS_FLASH_LATENCY(FLatency)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ - - /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != FLatency) - { - return HAL_ERROR; - } - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* PLL is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) - { - return HAL_ERROR; - } -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */ - /* Compute target PLL output frequency */ - pllfreq = RCC_GetSysClockFreqFromPLLSource(); - - /* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */ - if((pllfreq > 80000000U) && - (((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) && (RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1)) - || - ((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)))) - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); - hpre = RCC_SYSCLK_DIV2; - } -#endif - } - else - { - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* MSI is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) - { - /* Check the MSI ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) - { - return HAL_ERROR; - } - } - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */ - pllfreq = HAL_RCC_GetSysClockFreq(); - - /* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */ - if(pllfreq > 80000000U) - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2); - hpre = RCC_SYSCLK_DIV2; - } -#endif - - } - - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) - { - if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - else - { - /* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */ - if(hpre == RCC_SYSCLK_DIV2) - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1); - } - } -#endif - - /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; - - /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick (TICK_INT_PRIORITY); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to: - - (+) Ouput clock to MCO pin. - (+) Retrieve current clock frequencies. - (+) Enable the Clock Security System. - -@endverbatim - * @{ - */ - -/** - * @brief Select the clock source to output on MCO pin(PA8). - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCOx specifies the output direction for the clock source. - * For STM32L4xx family this parameter can have only one value: - * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). - * @param RCC_MCOSource specifies the clock source to output. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO - * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee - * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source - @if STM32L443xx - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 - @endif - * @param RCC_MCODiv specifies the MCO prescaler. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 no division applied to MCO clock - * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock - * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock - * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock - * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock - * @retval None - */ -void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) -{ - GPIO_InitTypeDef GPIO_InitStruct; - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCOx)); - assert_param(IS_RCC_MCODIV(RCC_MCODiv)); - assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - - /* MCO Clock Enable */ - __MCO1_CLK_ENABLE(); - - /* Configue the MCO1 pin in alternate function mode */ - GPIO_InitStruct.Pin = MCO1_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Alternate = GPIO_AF0_MCO; - HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); - - /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv )); -} - -/** - * @brief Return the SYSCLK frequency. - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is MSI, function returns values based on MSI - * Value as defined by the MSI range. - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), - * HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32l4xx_hal_conf.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * - * @note Each time SYSCLK changes, this function must be called to update the - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * - * @retval SYSCLK frequency - */ -uint32_t HAL_RCC_GetSysClockFreq(void) -{ - uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U; - uint32_t sysclockfreq = 0U; - - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) || - ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI))) - { - /* MSI or PLL with MSI source used as system clock source */ - - /* Get SYSCLK source */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) - { /* MSISRANGE from RCC_CSR applies */ - msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; - } - else - { /* MSIRANGE from RCC_CR applies */ - msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; - } - /*MSI frequency range in HZ*/ - msirange = MSIRangeTable[msirange]; - - if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) - { - /* MSI used as system clock source */ - sysclockfreq = msirange; - } - } - else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) - { - /* HSI used as system clock source */ - sysclockfreq = HSI_VALUE; - } - else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) - { - /* HSE used as system clock source */ - sysclockfreq = HSE_VALUE; - } - - if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) - { - /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); - pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; - - switch (pllsource) - { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - break; - - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - break; - - case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ - default: - pllvco = (msirange / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - break; - } - pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; - sysclockfreq = pllvco/pllr; - } - - return sysclockfreq; -} - -/** - * @brief Return the HCLK frequency. - * @note Each time HCLK changes, this function must be called to update the - * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. - * @retval HCLK frequency in Hz - */ -uint32_t HAL_RCC_GetHCLKFreq(void) -{ - return SystemCoreClock; -} - -/** - * @brief Return the PCLK1 frequency. - * @note Each time PCLK1 changes, this function must be called to update the - * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK1 frequency in Hz - */ -uint32_t HAL_RCC_GetPCLK1Freq(void) -{ - /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); -} - -/** - * @brief Return the PCLK2 frequency. - * @note Each time PCLK2 changes, this function must be called to update the - * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK2 frequency in Hz - */ -uint32_t HAL_RCC_GetPCLK2Freq(void) -{ - /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); -} - -/** - * @brief Configure the RCC_OscInitStruct according to the internal - * RCC configuration registers. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - /* Check the parameters */ - assert_param(RCC_OscInitStruct != NULL); - - /* Set all possible values for the Oscillator type parameter ---------------*/ -#if defined(RCC_HSI48_SUPPORT) - RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ - RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; -#else - RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ - RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; -#endif /* RCC_HSI48_SUPPORT */ - - /* Get the HSE configuration -----------------------------------------------*/ - if(READ_BIT(RCC->CR, RCC_CR_HSEBYP) == RCC_CR_HSEBYP) - { - RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; - } - else if(READ_BIT(RCC->CR, RCC_CR_HSEON) == RCC_CR_HSEON) - { - RCC_OscInitStruct->HSEState = RCC_HSE_ON; - } - else - { - RCC_OscInitStruct->HSEState = RCC_HSE_OFF; - } - - /* Get the MSI configuration -----------------------------------------------*/ - if(READ_BIT(RCC->CR, RCC_CR_MSION) == RCC_CR_MSION) - { - RCC_OscInitStruct->MSIState = RCC_MSI_ON; - } - else - { - RCC_OscInitStruct->MSIState = RCC_MSI_OFF; - } - - RCC_OscInitStruct->MSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos; - RCC_OscInitStruct->MSIClockRange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE); - - /* Get the HSI configuration -----------------------------------------------*/ - if(READ_BIT(RCC->CR, RCC_CR_HSION) == RCC_CR_HSION) - { - RCC_OscInitStruct->HSIState = RCC_HSI_ON; - } - else - { - RCC_OscInitStruct->HSIState = RCC_HSI_OFF; - } - - RCC_OscInitStruct->HSICalibrationValue = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos; - - /* Get the LSE configuration -----------------------------------------------*/ - if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) - { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; - } - else if(READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == RCC_BDCR_LSEON) - { - RCC_OscInitStruct->LSEState = RCC_LSE_ON; - } - else - { - RCC_OscInitStruct->LSEState = RCC_LSE_OFF; - } - - /* Get the LSI configuration -----------------------------------------------*/ - if(READ_BIT(RCC->CSR, RCC_CSR_LSION) == RCC_CSR_LSION) - { - RCC_OscInitStruct->LSIState = RCC_LSI_ON; - } - else - { - RCC_OscInitStruct->LSIState = RCC_LSI_OFF; - } - -#if defined(RCC_HSI48_SUPPORT) - /* Get the HSI48 configuration ---------------------------------------------*/ - if(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) - { - RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; - } - else - { - RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; - } -#else - RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; -#endif /* RCC_HSI48_SUPPORT */ - - /* Get the PLL configuration -----------------------------------------------*/ - if(READ_BIT(RCC->CR, RCC_CR_PLLON) == RCC_CR_PLLON) - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; - } - else - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; - } - RCC_OscInitStruct->PLL.PLLSource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLM = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; - RCC_OscInitStruct->PLL.PLLN = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - RCC_OscInitStruct->PLL.PLLQ = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); - RCC_OscInitStruct->PLL.PLLR = (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U); -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - RCC_OscInitStruct->PLL.PLLP = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#else - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) - { - RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV17; - } - else - { - RCC_OscInitStruct->PLL.PLLP = RCC_PLLP_DIV7; - } -#endif /* RCC_PLLP_DIV_2_31_SUPPORT */ -} - -/** - * @brief Configure the RCC_ClkInitStruct according to the internal - * RCC configuration registers. - * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that - * will be configured. - * @param pFLatency Pointer on the Flash Latency. - * @retval None - */ -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) -{ - /* Check the parameters */ - assert_param(RCC_ClkInitStruct != NULL); - assert_param(pFLatency != NULL); - - /* Set all possible values for the Clock type parameter --------------------*/ - RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - /* Get the SYSCLK configuration --------------------------------------------*/ - RCC_ClkInitStruct->SYSCLKSource = READ_BIT(RCC->CFGR, RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1); - - /* Get the APB2 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB2CLKDivider = (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> 3U); - - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY); -} - -/** - * @brief Enable the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. - * @note The Clock Security System can only be cleared by reset. - * @retval None - */ -void HAL_RCC_EnableCSS(void) -{ - SET_BIT(RCC->CR, RCC_CR_CSSON) ; -} - -/** - * @brief Handle the RCC Clock Security System interrupt request. - * @note This API should be called under the NMI_Handler(). - * @retval None - */ -void HAL_RCC_NMI_IRQHandler(void) -{ - /* Check RCC CSSF interrupt flag */ - if(__HAL_RCC_GET_IT(RCC_IT_CSS)) - { - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CSSCallback(); - - /* Clear RCC CSS pending bit */ - __HAL_RCC_CLEAR_IT(RCC_IT_CSS); - } -} - -/** - * @brief RCC Clock Security System interrupt callback. - * @retval none - */ -__weak void HAL_RCC_CSSCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RCC_CSSCallback should be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup RCC_Private_Functions - * @{ - */ -/** - * @brief Update number of Flash wait states in line with MSI range and current - voltage range. - * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11 - * @retval HAL status - */ -static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) -{ - uint32_t vos = 0; - uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ - - if(__HAL_RCC_PWR_IS_CLK_ENABLED()) - { - vos = HAL_PWREx_GetVoltageRange(); - } - else - { - __HAL_RCC_PWR_CLK_ENABLE(); - vos = HAL_PWREx_GetVoltageRange(); - __HAL_RCC_PWR_CLK_DISABLE(); - } - - if(vos == PWR_REGULATOR_VOLTAGE_SCALE1) - { - if(msirange > RCC_MSIRANGE_8) - { - /* MSI > 16Mhz */ - if(msirange > RCC_MSIRANGE_10) - { - /* MSI 48Mhz */ - latency = FLASH_LATENCY_2; /* 2WS */ - } - else - { - /* MSI 24Mhz or 32Mhz */ - latency = FLASH_LATENCY_1; /* 1WS */ - } - } - /* else MSI <= 16Mhz default FLASH_LATENCY_0 0WS */ - } - else - { -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - if(msirange >= RCC_MSIRANGE_8) - { - /* MSI >= 16Mhz */ - latency = FLASH_LATENCY_2; /* 2WS */ - } - else - { - if(msirange == RCC_MSIRANGE_7) - { - /* MSI 8Mhz */ - latency = FLASH_LATENCY_1; /* 1WS */ - } - /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ - } -#else - if(msirange > RCC_MSIRANGE_8) - { - /* MSI > 16Mhz */ - latency = FLASH_LATENCY_3; /* 3WS */ - } - else - { - if(msirange == RCC_MSIRANGE_8) - { - /* MSI 16Mhz */ - latency = FLASH_LATENCY_2; /* 2WS */ - } - else if(msirange == RCC_MSIRANGE_7) - { - /* MSI 8Mhz */ - latency = FLASH_LATENCY_1; /* 1WS */ - } - /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ - } -#endif - } - - __HAL_FLASH_SET_LATENCY(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) != latency) - { - return HAL_ERROR; - } - - return HAL_OK; -} - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -/** - * @brief Compute SYSCLK frequency based on PLL SYSCLK source. - * @retval SYSCLK frequency - */ -static uint32_t RCC_GetSysClockFreqFromPLLSource(void) -{ - uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U; - uint32_t sysclockfreq = 0U; - - if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) - { - /* Get MSI range source */ - if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) - { /* MSISRANGE from RCC_CSR applies */ - msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos; - } - else - { /* MSIRANGE from RCC_CR applies */ - msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; - } - /*MSI frequency range in HZ*/ - msirange = MSIRangeTable[msirange]; - } - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); - pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; - - switch (pllsource) - { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - break; - - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - break; - - case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ - default: - pllvco = (msirange / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - break; - } - - pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U; - sysclockfreq = pllvco/pllr; - - return sysclockfreq; -} -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c deleted file mode 100644 index 7c31e73fb..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c +++ /dev/null @@ -1,3358 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rcc_ex.c - * @author MCD Application Team - * @brief Extended RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities RCC extended peripheral: - * + Extended Peripheral Control functions - * + Extended Clock management functions - * + Extended Clock Recovery System Control functions - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup RCCEx RCCEx - * @brief RCC Extended HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Constants RCCEx Private Constants - * @{ - */ -#define PLLSAI1_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define PLLSAI2_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ - -#define DIVIDER_P_UPDATE 0U -#define DIVIDER_Q_UPDATE 1U -#define DIVIDER_R_UPDATE 2U - -#define __LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define LSCO_GPIO_PORT GPIOA -#define LSCO_PIN GPIO_PIN_2 -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup RCCEx_Private_Functions RCCEx Private Functions - * @{ - */ -static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider); - -#if defined(RCC_PLLSAI2_SUPPORT) - -static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider); - -#endif /* RCC_PLLSAI2_SUPPORT */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions - * @{ - */ - -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - [..] - (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including - the backup registers) are set to their reset values. - -@endverbatim - * @{ - */ -/** - * @brief Initialize the RCC extended peripherals clocks according to the specified - * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains a field PeriphClockSelection which can be a combination of the following values: - * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock - * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock - @if STM32L462xx - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1) - @endif - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM1) - @endif - * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock - @if STM32L462xx - * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) - @endif - @if STM32L4S9xx - * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) - @endif - * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock - * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) - @endif - @if STM32L4S9xx - * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) - @endif - * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock - @if STM32L443xx - * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) - @endif - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) - @endif - * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART2 USART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART3 USART1 peripheral clock - @if STM32L462xx - * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) - @endif - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) - * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) - * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) - @endif - @if STM32L4S9xx - * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) - * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral kernel clock (only for devices with DFSDM1) - * @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO DFSDM1 peripheral audio clock (only for devices with DFSDM1) - * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (only for devices with LTDC) - * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock (only for devices with DSI) - * @arg @ref RCC_PERIPHCLK_OSPI OctoSPI peripheral clock (only for devices with OctoSPI) - @endif - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source: in this case the access to Backup domain is enabled. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tmpregister = 0; - uint32_t tickstart = 0U; - HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ - HAL_StatusTypeDef status = HAL_OK; /* Final status */ - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*-------------------------- SAI1 clock source configuration ---------------------*/ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection)); - - switch(PeriphClkInit->Sai1ClockSelection) - { - case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ - /* Enable SAI Clock output generated form System PLL . */ -#if defined(RCC_PLLSAI2_SUPPORT) - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); -#else - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK); -#endif /* RCC_PLLSAI2_SUPPORT */ - /* SAI1 clock source config set later after clock selection check */ - break; - - case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/ - /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE); - /* SAI1 clock source config set later after clock selection check */ - break; - -#if defined(RCC_PLLSAI2_SUPPORT) - - case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/ - /* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */ - ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE); - /* SAI1 clock source config set later after clock selection check */ - break; - -#endif /* RCC_PLLSAI2_SUPPORT */ - - case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/ -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - /* SAI1 clock source config set later after clock selection check */ - break; - - default: - ret = HAL_ERROR; - break; - } - - if(ret == HAL_OK) - { - /* Set the source of SAI1 clock*/ - __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - -#if defined(SAI2) - - /*-------------------------- SAI2 clock source configuration ---------------------*/ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection)); - - switch(PeriphClkInit->Sai2ClockSelection) - { - case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ - /* Enable SAI Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); - /* SAI2 clock source config set later after clock selection check */ - break; - - case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/ - /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE); - /* SAI2 clock source config set later after clock selection check */ - break; - - case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/ - /* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */ - ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE); - /* SAI2 clock source config set later after clock selection check */ - break; - - case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/ -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/ -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - /* SAI2 clock source config set later after clock selection check */ - break; - - default: - ret = HAL_ERROR; - break; - } - - if(ret == HAL_OK) - { - /* Set the source of SAI2 clock*/ - __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } -#endif /* SAI2 */ - - /*-------------------------- RTC clock source configuration ----------------------*/ - if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) - { - FlagStatus pwrclkchanged = RESET; - - /* Check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - /* Enable Power Clock */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR1, PWR_CR1_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == RESET) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - ret = HAL_TIMEOUT; - break; - } - } - - if(ret == HAL_OK) - { - /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ - tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); - - if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - /* Restore the Content of BDCR register */ - RCC->BDCR = tmpregister; - } - - /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ - if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - ret = HAL_TIMEOUT; - break; - } - } - } - - if(ret == HAL_OK) - { - /* Apply new RTC clock source selection */ - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - else - { - /* set overall return value */ - status = ret; - } - - /* Restore clock configuration if changed */ - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - - /*-------------------------- USART1 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - { - /* Check the parameters */ - assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); - - /* Configure the USART1 clock source */ - __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - } - - /*-------------------------- USART2 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - { - /* Check the parameters */ - assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); - - /* Configure the USART2 clock source */ - __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); - } - -#if defined(USART3) - - /*-------------------------- USART3 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) - { - /* Check the parameters */ - assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); - - /* Configure the USART3 clock source */ - __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); - } - -#endif /* USART3 */ - -#if defined(UART4) - - /*-------------------------- UART4 clock source configuration --------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) - { - /* Check the parameters */ - assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); - - /* Configure the UART4 clock source */ - __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); - } - -#endif /* UART4 */ - -#if defined(UART5) - - /*-------------------------- UART5 clock source configuration --------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) - { - /* Check the parameters */ - assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); - - /* Configure the UART5 clock source */ - __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); - } - -#endif /* UART5 */ - - /*-------------------------- LPUART1 clock source configuration ------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) - { - /* Check the parameters */ - assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); - - /* Configure the LPUAR1 clock source */ - __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); - } - - /*-------------------------- LPTIM1 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) - { - assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); - __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); - } - - /*-------------------------- LPTIM2 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) - { - assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection)); - __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); - } - - /*-------------------------- I2C1 clock source configuration ---------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); - - /* Configure the I2C1 clock source */ - __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - } - -#if defined(I2C2) - - /*-------------------------- I2C2 clock source configuration ---------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); - - /* Configure the I2C2 clock source */ - __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); - } - -#endif /* I2C2 */ - - /*-------------------------- I2C3 clock source configuration ---------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); - - /* Configure the I2C3 clock source */ - __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); - } - -#if defined(I2C4) - - /*-------------------------- I2C4 clock source configuration ---------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); - - /* Configure the I2C4 clock source */ - __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); - } - -#endif /* I2C4 */ - -#if defined(USB_OTG_FS) || defined(USB) - - /*-------------------------- USB clock source configuration ----------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) - { - assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); - __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); - - if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) - { - /* Enable PLL48M1CLK output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - } - else - { - if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) - { - /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - - if(ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } - } - } - } - -#endif /* USB_OTG_FS || USB */ - -#if defined(SDMMC1) - - /*-------------------------- SDMMC1 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1)) - { - assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); - __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); - - if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */ - { - /* Enable PLL48M1CLK output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - } -#if defined(RCC_CCIPR2_SDMMCSEL) - else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLP) /* PLL "P" ? */ - { - /* Enable PLLSAI3CLK output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); - } -#endif - else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1) - { - /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - - if(ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } - } - } - -#endif /* SDMMC1 */ - - /*-------------------------- RNG clock source configuration ----------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) - { - assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); - __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); - - if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) - { - /* Enable PLL48M1CLK output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - } - else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1) - { - /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); - - if(ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } - } - } - - /*-------------------------- ADC clock source configuration ----------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) - { - /* Check the parameters */ - assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); - - /* Configure the ADC interface clock source */ - __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); - - if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) - { - /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */ - ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE); - - if(ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } - } - -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) - - else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2) - { - /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ - ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); - - if(ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } - } - -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ - - } - -#if defined(SWPMI1) - - /*-------------------------- SWPMI1 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) - { - /* Check the parameters */ - assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); - - /* Configure the SWPMI1 clock source */ - __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); - } - -#endif /* SWPMI1 */ - -#if defined(DFSDM1_Filter0) - - /*-------------------------- DFSDM1 clock source configuration -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) - { - /* Check the parameters */ - assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); - - /* Configure the DFSDM1 interface clock source */ - __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); - } - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /*-------------------------- DFSDM1 audio clock source configuration -------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) - { - /* Check the parameters */ - assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); - - /* Configure the DFSDM1 interface audio clock source */ - __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); - } - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) - - /*-------------------------- LTDC clock source configuration --------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) - { - /* Check the parameters */ - assert_param(IS_RCC_LTDCCLKSOURCE(PeriphClkInit->LtdcClockSelection)); - - /* Disable the PLLSAI2 */ - __HAL_RCC_PLLSAI2_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) - { - ret = HAL_TIMEOUT; - break; - } - } - - if(ret == HAL_OK) - { - /* Configure the LTDC clock source */ - __HAL_RCC_LTDC_CONFIG(PeriphClkInit->LtdcClockSelection); - - /* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */ - ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE); - } - - if(ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } - } - -#endif /* LTDC */ - -#if defined(DSI) - - /*-------------------------- DSI clock source configuration ---------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) - { - /* Check the parameters */ - assert_param(IS_RCC_DSICLKSOURCE(PeriphClkInit->DsiClockSelection)); - - /* Configure the DSI clock source */ - __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection); - - if(PeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLLSAI2) - { - /* PLLSAI2 input clock, parameters M, N & Q configuration and clock output (PLLSAI2ClockOut) */ - ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_Q_UPDATE); - - if(ret != HAL_OK) - { - /* set overall return value */ - status = ret; - } - } - } - -#endif /* DSI */ - -#if defined(OCTOSPI1) || defined(OCTOSPI2) - - /*-------------------------- OctoSPIx clock source configuration ----------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) - { - /* Check the parameters */ - assert_param(IS_RCC_OSPICLKSOURCE(PeriphClkInit->OspiClockSelection)); - - /* Configure the OctoSPI clock source */ - __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); - - if(PeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL) - { - /* Enable PLL48M1CLK output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); - } - } - -#endif /* OCTOSPI1 || OCTOSPI2 */ - - return status; -} - -/** - * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * returns the configuration information for the Extended Peripherals - * clocks(SAI1, SAI2, LPTIM1, LPTIM2, I2C1, I2C2, I2C3, I2C4, LPUART, - * USART1, USART2, USART3, UART4, UART5, RTC, ADCx, DFSDMx, SWPMI1, USB, SDMMC1 and RNG). - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - /* Set all possible values for the extended clock type parameter------------*/ - -#if defined(STM32L431xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L432xx) || defined(STM32L442xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L433xx) || defined(STM32L443xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L451xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L452xx) || defined(STM32L462xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L471xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L496xx) || defined(STM32L4A6xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_RTC ; - -#elif defined(STM32L4R5xx) || defined(STM32L4S5xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI; - -#elif defined(STM32L4R7xx) || defined(STM32L4S7xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC; - -#elif defined(STM32L4R9xx) || defined(STM32L4S9xx) - - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_USB | \ - RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_DFSDM1 | \ - RCC_PERIPHCLK_DFSDM1AUDIO | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_DSI; - -#endif /* STM32L431xx */ - - /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ - - PeriphClkInit->PLLSAI1.PLLSAI1Source = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos; -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U; -#else - PeriphClkInit->PLLSAI1.PLLSAI1M = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U; -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - PeriphClkInit->PLLSAI1.PLLSAI1N = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; - PeriphClkInit->PLLSAI1.PLLSAI1P = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos) << 4U) + 7U; - PeriphClkInit->PLLSAI1.PLLSAI1Q = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) * 2U; - PeriphClkInit->PLLSAI1.PLLSAI1R = ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) * 2U; - -#if defined(RCC_PLLSAI2_SUPPORT) - - /* Get the PLLSAI2 Clock configuration -----------------------------------------------*/ - - PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source; -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - PeriphClkInit->PLLSAI2.PLLSAI2M = (READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U; -#else - PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M; -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - PeriphClkInit->PLLSAI2.PLLSAI2N = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; - PeriphClkInit->PLLSAI2.PLLSAI2P = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) >> RCC_PLLSAI2CFGR_PLLSAI2P_Pos) << 4U) + 7U; -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) - PeriphClkInit->PLLSAI2.PLLSAI2Q = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) * 2U; -#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ - PeriphClkInit->PLLSAI2.PLLSAI2R = ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R)>> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) * 2U; - -#endif /* RCC_PLLSAI2_SUPPORT */ - - /* Get the USART1 clock source ---------------------------------------------*/ - PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); - /* Get the USART2 clock source ---------------------------------------------*/ - PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); - -#if defined(USART3) - /* Get the USART3 clock source ---------------------------------------------*/ - PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); -#endif /* USART3 */ - -#if defined(UART4) - /* Get the UART4 clock source ----------------------------------------------*/ - PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); -#endif /* UART4 */ - -#if defined(UART5) - /* Get the UART5 clock source ----------------------------------------------*/ - PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); -#endif /* UART5 */ - - /* Get the LPUART1 clock source --------------------------------------------*/ - PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); - - /* Get the I2C1 clock source -----------------------------------------------*/ - PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); - -#if defined(I2C2) - /* Get the I2C2 clock source ----------------------------------------------*/ - PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); -#endif /* I2C2 */ - - /* Get the I2C3 clock source -----------------------------------------------*/ - PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); - -#if defined(I2C4) - /* Get the I2C4 clock source -----------------------------------------------*/ - PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); -#endif /* I2C4 */ - - /* Get the LPTIM1 clock source ---------------------------------------------*/ - PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); - - /* Get the LPTIM2 clock source ---------------------------------------------*/ - PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); - - /* Get the SAI1 clock source -----------------------------------------------*/ - PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); - -#if defined(SAI2) - /* Get the SAI2 clock source -----------------------------------------------*/ - PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); -#endif /* SAI2 */ - - /* Get the RTC clock source ------------------------------------------------*/ - PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); - -#if defined(USB_OTG_FS) || defined(USB) - /* Get the USB clock source ------------------------------------------------*/ - PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); -#endif /* USB_OTG_FS || USB */ - -#if defined(SDMMC1) - /* Get the SDMMC1 clock source ---------------------------------------------*/ - PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); -#endif /* SDMMC1 */ - - /* Get the RNG clock source ------------------------------------------------*/ - PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); - - /* Get the ADC clock source ------------------------------------------------*/ - PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); - -#if defined(SWPMI1) - /* Get the SWPMI1 clock source ---------------------------------------------*/ - PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE(); -#endif /* SWPMI1 */ - -#if defined(DFSDM1_Filter0) - /* Get the DFSDM1 clock source ---------------------------------------------*/ - PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - /* Get the DFSDM1 audio clock source ---------------------------------------*/ - PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ -#endif /* DFSDM1_Filter0 */ - -#if defined(LTDC) - /* Get the LTDC clock source -----------------------------------------------*/ - PeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); -#endif /* LTDC */ - -#if defined(DSI) - /* Get the DSI clock source ------------------------------------------------*/ - PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); -#endif /* DSI */ - -#if defined(OCTOSPI1) || defined(OCTOSPI2) - /* Get the OctoSPIclock source --------------------------------------------*/ - PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); -#endif /* OCTOSPI1 || OCTOSPI2 */ -} - -/** - * @brief Return the peripheral clock frequency for peripherals with clock source from PLLSAIs - * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk Peripheral clock identifier - * This parameter can be one of the following values: - * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock - * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock - @if STM32L462xx - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM) - @endif - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral clock (only for devices with DFSDM) - @endif - * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock - @if STM32L462xx - * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) - @endif - @if STM32L4S9xx - * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock (only for devices with I2C4) - @endif - * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock - * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) - @endif - @if STM32L4S9xx - * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock (only for devices with SAI2) - @endif - * @arg @ref RCC_PERIPHCLK_SDMMC1 SDMMC1 peripheral clock - @if STM32L443xx - * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) - @endif - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_SWPMI1 SWPMI1 peripheral clock (only for devices with SWPMI1) - @endif - * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART2 USART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART3 USART1 peripheral clock - @if STM32L462xx - * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) - @endif - @if STM32L486xx - * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) - * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) - @endif - @if STM32L4A6xx - * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock (only for devices with UART4) - * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock (only for devices with UART5) - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) - @endif - @if STM32L4S9xx - * @arg @ref RCC_PERIPHCLK_UART4 USART1 peripheral clock (only for devices with UART4) - * @arg @ref RCC_PERIPHCLK_UART5 USART1 peripheral clock (only for devices with UART5) - * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (only for devices with USB) - * @arg @ref RCC_PERIPHCLK_DFSDM1 DFSDM1 peripheral kernel clock (only for devices with DFSDM1) - * @arg @ref RCC_PERIPHCLK_DFSDM1AUDIO DFSDM1 peripheral audio clock (only for devices with DFSDM1) - * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (only for devices with LTDC) - * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock (only for devices with DSI) - * @arg @ref RCC_PERIPHCLK_OSPI OctoSPI peripheral clock (only for devices with OctoSPI) - @endif - * @retval Frequency in Hz - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ - uint32_t frequency = 0U; - uint32_t srcclk = 0U; - uint32_t pllvco = 0U, plln = 0U, pllp = 0U; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); - - if(PeriphClk == RCC_PERIPHCLK_RTC) - { - /* Get the current RTC source */ - srcclk = __HAL_RCC_GET_RTC_SOURCE(); - - /* Check if LSE is ready and if RTC clock selection is LSE */ - if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Check if LSI is ready and if RTC clock selection is LSI */ - else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - { - frequency = LSI_VALUE; - } - /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ - else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) - { - frequency = HSE_VALUE / 32U; - } - /* Clock not enabled for RTC*/ - else - { - frequency = 0U; - } - } - else - { - /* Other external peripheral clock source than RTC */ - - /* Compute PLL clock input */ - if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI) /* MSI ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) - { - /*MSI frequency range in HZ*/ - pllvco = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else - { - pllvco = 0U; - } - } - else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - pllvco = HSI_VALUE; - } - else - { - pllvco = 0U; - } - } - else if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) - { - pllvco = HSE_VALUE; - } - else - { - pllvco = 0U; - } - } - else /* No source */ - { - pllvco = 0U; - } - -#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - - switch(PeriphClk) - { -#if defined(SAI2) - - case RCC_PERIPHCLK_SAI1: - case RCC_PERIPHCLK_SAI2: - - if(PeriphClk == RCC_PERIPHCLK_SAI1) - { - srcclk = __HAL_RCC_GET_SAI1_SOURCE(); - - if(srcclk == RCC_SAI1CLKSOURCE_PIN) - { - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - } - /* Else, PLL clock output to check below */ - } - else /* RCC_PERIPHCLK_SAI2 */ - { - srcclk = __HAL_RCC_GET_SAI2_SOURCE(); - - if(srcclk == RCC_SAI2CLKSOURCE_PIN) - { - frequency = EXTERNAL_SAI2_CLOCK_VALUE; - } - /* Else, PLL clock output to check below */ - } - -#else - - case RCC_PERIPHCLK_SAI1: - - if(PeriphClk == RCC_PERIPHCLK_SAI1) - { - srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL); - - if(srcclk == RCC_SAI1CLKSOURCE_PIN) - { - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - } - /* Else, PLL clock output to check below */ - } - -#endif /* SAI2 */ - - if(frequency == 0U) - { -#if defined(SAI2) - if((srcclk == RCC_SAI1CLKSOURCE_PLL) || (srcclk == RCC_SAI2CLKSOURCE_PLL)) - { - if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET) - { - /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - frequency = (pllvco * plln) / pllp; - } - } - else if(srcclk == 0U) /* RCC_SAI1CLKSOURCE_PLLSAI1 || RCC_SAI2CLKSOURCE_PLLSAI1 */ - { - if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#endif - /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - frequency = (pllvco * plln) / pllp; - } - } -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - else if((srcclk == RCC_SAI1CLKSOURCE_HSI) || (srcclk == RCC_SAI2CLKSOURCE_HSI)) - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - } -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#else - if(srcclk == RCC_SAI1CLKSOURCE_PLL) - { - if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != RESET) - { - /* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - - frequency = (pllvco * plln) / pllp; - } - else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - /* HSI automatically selected as clock source if PLLs not enabled */ - frequency = HSI_VALUE; - } - else - { - /* No clock source */ - frequency = 0U; - } - } - else if(srcclk == RCC_SAI1CLKSOURCE_PLLSAI1) - { - if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#endif - /* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - - frequency = (pllvco * plln) / pllp; - } - else if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - /* HSI automatically selected as clock source if PLLs not enabled */ - frequency = HSI_VALUE; - } - else - { - /* No clock source */ - frequency = 0U; - } - } -#endif /* SAI2 */ - -#if defined(RCC_PLLSAI2_SUPPORT) - - else if((srcclk == RCC_SAI1CLKSOURCE_PLLSAI2) || (srcclk == RCC_SAI2CLKSOURCE_PLLSAI2)) - { - if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET) - { -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLLSAI2 Source) / PLLSAI2M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); -#endif - /* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */ - plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; -#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - frequency = (pllvco * plln) / pllp; - } - } - -#endif /* RCC_PLLSAI2_SUPPORT */ - - else - { - /* No clock source */ - frequency = 0U; - } - } - break; - -#if defined(USB_OTG_FS) || defined(USB) - - case RCC_PERIPHCLK_USB: - -#endif /* USB_OTG_FS || USB */ - - case RCC_PERIPHCLK_RNG: - -#if defined(SDMMC1) && !defined(RCC_CCIPR2_SDMMCSEL) - - case RCC_PERIPHCLK_SDMMC1: - -#endif /* SDMMC1 && !RCC_CCIPR2_SDMMCSEL */ - - srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); - - if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) - { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else - { - frequency = 0U; - } - } - else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; - } - } - else if(srcclk == RCC_CCIPR_CLK48SEL_0) /* PLLSAI1 ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#endif - /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; - } - } -#if defined(RCC_HSI48_SUPPORT) - else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */ - { - frequency = HSI48_VALUE; - } - else /* No clock source */ - { - frequency = 0U; - } -#else - else /* No clock source */ - { - frequency = 0U; - } -#endif /* RCC_HSI48_SUPPORT */ - break; - -#if defined(SDMMC1) && defined(RCC_CCIPR2_SDMMCSEL) - - case RCC_PERIPHCLK_SDMMC1: - - if(HAL_IS_BIT_SET(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL)) /* PLL "P" ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - /* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; -#if defined(RCC_PLLP_DIV_2_31_SUPPORT) - pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos; -#endif - if(pllp == 0U) - { - if(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) != RESET) - { - pllp = 17U; - } - else - { - pllp = 7U; - } - } - frequency = (pllvco * plln) / pllp; - } - else - { - frequency = 0U; - } - } - else /* 48MHz from PLL "Q" or MSI or PLLSAI1Q or HSI48 */ - { - srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL); - - if(srcclk == RCC_CCIPR_CLK48SEL) /* MSI ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY)) - { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else - { - frequency = 0U; - } - } - else if(srcclk == RCC_CCIPR_CLK48SEL_1) /* PLL "Q" ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) || defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); -#endif - /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; - } - } - else if(srcclk == RCC_CCIPR_CLK48SEL_0) /* PLLSAI1 ? */ - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN)) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#endif - /* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; - } - } - else if((srcclk == 0U) && (HAL_IS_BIT_SET(RCC->CRRCR, RCC_CRRCR_HSI48RDY))) /* HSI48 ? */ - { - frequency = HSI48_VALUE; - } - else /* No clock source */ - { - frequency = 0U; - } - } - break; - -#endif /* SDMMC1 && RCC_CCIPR2_SDMMCSEL */ - - case RCC_PERIPHCLK_USART1: - /* Get the current USART1 source */ - srcclk = __HAL_RCC_GET_USART1_SOURCE(); - - if(srcclk == RCC_USART1CLKSOURCE_PCLK2) - { - frequency = HAL_RCC_GetPCLK2Freq(); - } - else if(srcclk == RCC_USART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART1 */ - else - { - frequency = 0U; - } - break; - - case RCC_PERIPHCLK_USART2: - /* Get the current USART2 source */ - srcclk = __HAL_RCC_GET_USART2_SOURCE(); - - if(srcclk == RCC_USART2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_USART2CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART2 */ - else - { - frequency = 0U; - } - break; - -#if defined(USART3) - - case RCC_PERIPHCLK_USART3: - /* Get the current USART3 source */ - srcclk = __HAL_RCC_GET_USART3_SOURCE(); - - if(srcclk == RCC_USART3CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_USART3CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART3 */ - else - { - frequency = 0U; - } - break; - -#endif /* USART3 */ - -#if defined(UART4) - - case RCC_PERIPHCLK_UART4: - /* Get the current UART4 source */ - srcclk = __HAL_RCC_GET_UART4_SOURCE(); - - if(srcclk == RCC_UART4CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_UART4CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for UART4 */ - else - { - frequency = 0U; - } - break; - -#endif /* UART4 */ - -#if defined(UART5) - - case RCC_PERIPHCLK_UART5: - /* Get the current UART5 source */ - srcclk = __HAL_RCC_GET_UART5_SOURCE(); - - if(srcclk == RCC_UART5CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_UART5CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for UART5 */ - else - { - frequency = 0U; - } - break; - -#endif /* UART5 */ - - case RCC_PERIPHCLK_LPUART1: - /* Get the current LPUART1 source */ - srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); - - if(srcclk == RCC_LPUART1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_LPUART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if((srcclk == RCC_LPUART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPUART1 */ - else - { - frequency = 0U; - } - break; - - case RCC_PERIPHCLK_ADC: - - srcclk = __HAL_RCC_GET_ADC_SOURCE(); - - if(srcclk == RCC_ADCCLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI1) - { - if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* f(PLLSAI1 Source) / PLLSAI1M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)); -#endif - /* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */ - plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U); - } - } -#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx) - else if(srcclk == RCC_ADCCLKSOURCE_PLLSAI2) - { - if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET) - { -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* f(PLLSAI2 Source) / PLLSAI2M */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)); -#endif - /* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */ - plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U); - } - } -#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */ - /* Clock not enabled for ADC */ - else - { - frequency = 0U; - } - break; - -#if defined(DFSDM1_Filter0) - - case RCC_PERIPHCLK_DFSDM1: - /* Get the current DFSDM1 source */ - srcclk = __HAL_RCC_GET_DFSDM1_SOURCE(); - - if(srcclk == RCC_DFSDM1CLKSOURCE_PCLK2) - { - frequency = HAL_RCC_GetPCLK2Freq(); - } - else - { - frequency = HAL_RCC_GetSysClockFreq(); - } - break; - -#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - - case RCC_PERIPHCLK_DFSDM1AUDIO: - /* Get the current DFSDM1 audio source */ - srcclk = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); - - if(srcclk == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) - { - frequency = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); - } - else if((srcclk == RCC_DFSDM1AUDIOCLKSOURCE_MSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))) - { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else if((srcclk == RCC_DFSDM1AUDIOCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for DFSDM1 audio source */ - else - { - frequency = 0U; - } - break; - -#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* DFSDM1_Filter0 */ - - case RCC_PERIPHCLK_I2C1: - /* Get the current I2C1 source */ - srcclk = __HAL_RCC_GET_I2C1_SOURCE(); - - if(srcclk == RCC_I2C1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_I2C1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C1 */ - else - { - frequency = 0U; - } - break; - -#if defined(I2C2) - - case RCC_PERIPHCLK_I2C2: - /* Get the current I2C2 source */ - srcclk = __HAL_RCC_GET_I2C2_SOURCE(); - - if(srcclk == RCC_I2C2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_I2C2CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C2 */ - else - { - frequency = 0U; - } - break; - -#endif /* I2C2 */ - - case RCC_PERIPHCLK_I2C3: - /* Get the current I2C3 source */ - srcclk = __HAL_RCC_GET_I2C3_SOURCE(); - - if(srcclk == RCC_I2C3CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_I2C3CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C3 */ - else - { - frequency = 0U; - } - break; - -#if defined(I2C4) - - case RCC_PERIPHCLK_I2C4: - /* Get the current I2C4 source */ - srcclk = __HAL_RCC_GET_I2C4_SOURCE(); - - if(srcclk == RCC_I2C4CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if(srcclk == RCC_I2C4CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_I2C4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for I2C4 */ - else - { - frequency = 0U; - } - break; - -#endif /* I2C4 */ - - case RCC_PERIPHCLK_LPTIM1: - /* Get the current LPTIM1 source */ - srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); - - if(srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if((srcclk == RCC_LPTIM1CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - { - frequency = LSI_VALUE; - } - else if((srcclk == RCC_LPTIM1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if ((srcclk == RCC_LPTIM1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM1 */ - else - { - frequency = 0U; - } - break; - - case RCC_PERIPHCLK_LPTIM2: - /* Get the current LPTIM2 source */ - srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); - - if(srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if((srcclk == RCC_LPTIM2CLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) - { - frequency = LSI_VALUE; - } - else if((srcclk == RCC_LPTIM2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - else if ((srcclk == RCC_LPTIM2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM2 */ - else - { - frequency = 0U; - } - break; - -#if defined(SWPMI1) - - case RCC_PERIPHCLK_SWPMI1: - /* Get the current SWPMI1 source */ - srcclk = __HAL_RCC_GET_SWPMI1_SOURCE(); - - if(srcclk == RCC_SWPMI1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if((srcclk == RCC_SWPMI1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for SWPMI1 */ - else - { - frequency = 0U; - } - break; - -#endif /* SWPMI1 */ - -#if defined(OCTOSPI1) || defined(OCTOSPI2) - - case RCC_PERIPHCLK_OSPI: - /* Get the current OctoSPI clock source */ - srcclk = __HAL_RCC_GET_OSPI_SOURCE(); - - if(srcclk == RCC_OSPICLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if((srcclk == RCC_OSPICLKSOURCE_MSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIRDY))) - { - /*MSI frequency range in HZ*/ - frequency = MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> 4U)]; - } - else if(srcclk == RCC_OSPICLKSOURCE_PLL) - { - if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)) - { - /* f(PLL Source) / PLLM */ - pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); - /* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */ - plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; - frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U); - } - else - { - frequency = 0U; - } - } - /* Clock not enabled for OctoSPI */ - else - { - frequency = 0U; - } - break; - -#endif /* OCTOSPI1 || OCTOSPI2 */ - - default: - break; - } - } - - return(frequency); -} - -/** - * @} - */ - -/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions - * @brief Extended Clock management functions - * -@verbatim - =============================================================================== - ##### Extended clock management functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the - activation or deactivation of MSI PLL-mode, PLLSAI1, PLLSAI2, LSE CSS, - Low speed clock output and clock after wake-up from STOP mode. -@endverbatim - * @{ - */ - -/** - * @brief Enable PLLSAI1. - * @param PLLSAI1Init pointer to an RCC_PLLSAI1InitTypeDef structure that - * contains the configuration information for the PLLSAI1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) -{ - uint32_t tickstart = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */ - assert_param(IS_RCC_PLLSAI1SOURCE(PLLSAI1Init->PLLSAI1Source)); - assert_param(IS_RCC_PLLSAI1M_VALUE(PLLSAI1Init->PLLSAI1M)); - assert_param(IS_RCC_PLLSAI1N_VALUE(PLLSAI1Init->PLLSAI1N)); - assert_param(IS_RCC_PLLSAI1P_VALUE(PLLSAI1Init->PLLSAI1P)); - assert_param(IS_RCC_PLLSAI1Q_VALUE(PLLSAI1Init->PLLSAI1Q)); - assert_param(IS_RCC_PLLSAI1R_VALUE(PLLSAI1Init->PLLSAI1R)); - assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PLLSAI1Init->PLLSAI1ClockOut)); - - /* Disable the PLLSAI1 */ - __HAL_RCC_PLLSAI1_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI1 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* Configure the PLLSAI1 Multiplication factor N */ - /* Configure the PLLSAI1 Division factors M, P, Q and R */ - __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1M, PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R); -#else - /* Configure the PLLSAI1 Multiplication factor N */ - /* Configure the PLLSAI1 Division factors P, Q and R */ - __HAL_RCC_PLLSAI1_CONFIG(PLLSAI1Init->PLLSAI1N, PLLSAI1Init->PLLSAI1P, PLLSAI1Init->PLLSAI1Q, PLLSAI1Init->PLLSAI1R); -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - /* Configure the PLLSAI1 Clock output(s) */ - __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PLLSAI1Init->PLLSAI1ClockOut); - - /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ - __HAL_RCC_PLLSAI1_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI1 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - } - - return status; -} - -/** - * @brief Disable PLLSAI1. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) -{ - uint32_t tickstart = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* Disable the PLLSAI1 */ - __HAL_RCC_PLLSAI1_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI1 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - /* Disable the PLLSAI1 Clock outputs */ - __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1CFGR_PLLSAI1PEN|RCC_PLLSAI1CFGR_PLLSAI1QEN|RCC_PLLSAI1CFGR_PLLSAI1REN); - - /* Reset PLL source to save power if no PLLs on */ - if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) -#if defined(RCC_PLLSAI2_SUPPORT) - && - (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) -#endif /* RCC_PLLSAI2_SUPPORT */ - ) - { - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); - } - - return status; -} - -#if defined(RCC_PLLSAI2_SUPPORT) - -/** - * @brief Enable PLLSAI2. - * @param PLLSAI2Init pointer to an RCC_PLLSAI2InitTypeDef structure that - * contains the configuration information for the PLLSAI2 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) -{ - uint32_t tickstart = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */ - assert_param(IS_RCC_PLLSAI2SOURCE(PLLSAI2Init->PLLSAI2Source)); - assert_param(IS_RCC_PLLSAI2M_VALUE(PLLSAI2Init->PLLSAI2M)); - assert_param(IS_RCC_PLLSAI2N_VALUE(PLLSAI2Init->PLLSAI2N)); - assert_param(IS_RCC_PLLSAI2P_VALUE(PLLSAI2Init->PLLSAI2P)); -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) - assert_param(IS_RCC_PLLSAI2Q_VALUE(PLLSAI2Init->PLLSAI2Q)); -#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ - assert_param(IS_RCC_PLLSAI2R_VALUE(PLLSAI2Init->PLLSAI2R)); - assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PLLSAI2Init->PLLSAI2ClockOut)); - - /* Disable the PLLSAI2 */ - __HAL_RCC_PLLSAI2_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI2 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT) - /* Configure the PLLSAI2 Multiplication factor N */ - /* Configure the PLLSAI2 Division factors M, P, Q and R */ - __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R); -#elif defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* Configure the PLLSAI2 Multiplication factor N */ - /* Configure the PLLSAI2 Division factors M, P and R */ - __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2M, PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R); -#elif defined(RCC_PLLSAI2Q_DIV_SUPPORT) - /* Configure the PLLSAI2 Multiplication factor N */ - /* Configure the PLLSAI2 Division factors P, Q and R */ - __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2Q, PLLSAI2Init->PLLSAI2R); -#else - /* Configure the PLLSAI2 Multiplication factor N */ - /* Configure the PLLSAI2 Division factors P and R */ - __HAL_RCC_PLLSAI2_CONFIG(PLLSAI2Init->PLLSAI2N, PLLSAI2Init->PLLSAI2P, PLLSAI2Init->PLLSAI2R); -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ - /* Configure the PLLSAI2 Clock output(s) */ - __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PLLSAI2Init->PLLSAI2ClockOut); - - /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/ - __HAL_RCC_PLLSAI2_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - } - - return status; -} - -/** - * @brief Disable PLLISAI2. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) -{ - uint32_t tickstart = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* Disable the PLLSAI2 */ - __HAL_RCC_PLLSAI2_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - /* Disable the PLLSAI2 Clock outputs */ -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) - __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2QEN|RCC_PLLSAI2CFGR_PLLSAI2REN); -#else - __HAL_RCC_PLLSAI2CLKOUT_DISABLE(RCC_PLLSAI2CFGR_PLLSAI2PEN|RCC_PLLSAI2CFGR_PLLSAI2REN); -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */ - - /* Reset PLL source to save power if no PLLs on */ - if((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) - && - (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) - ) - { - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); - } - - return status; -} - -#endif /* RCC_PLLSAI2_SUPPORT */ - -/** - * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock. - * @param WakeUpClk Wakeup clock - * This parameter can be one of the following values: - * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection - * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection - * @note This function shall not be called after the Clock Security System on HSE has been - * enabled. - * @retval None - */ -void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) -{ - assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); - - __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); -} - -/** - * @brief Configure the MSI range after standby mode. - * @note After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). - * @param MSIRange MSI range - * This parameter can be one of the following values: - * @arg @ref RCC_MSIRANGE_4 Range 4 around 1 MHz - * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz - * @arg @ref RCC_MSIRANGE_6 Range 6 around 4 MHz (reset value) - * @arg @ref RCC_MSIRANGE_7 Range 7 around 8 MHz - * @retval None - */ -void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange) -{ - assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange)); - - __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange); -} - -/** - * @brief Enable the LSE Clock Security System. - * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled - * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC - * clock with HAL_RCCEx_PeriphCLKConfig(). - * @retval None - */ -void HAL_RCCEx_EnableLSECSS(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; -} - -/** - * @brief Disable the LSE Clock Security System. - * @note LSE Clock Security System can only be disabled after a LSE failure detection. - * @retval None - */ -void HAL_RCCEx_DisableLSECSS(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; - - /* Disable LSE CSS IT if any */ - __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); -} - -/** - * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. - * @note LSE Clock Security System Interrupt is mapped on RTC EXTI line 19 - * @retval None - */ -void HAL_RCCEx_EnableLSECSS_IT(void) -{ - /* Enable LSE CSS */ - SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; - - /* Enable LSE CSS IT */ - __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); - - /* Enable IT on EXTI Line 19 */ - __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); - __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); -} - -/** - * @brief Handle the RCC LSE Clock Security System interrupt request. - * @retval None - */ -void HAL_RCCEx_LSECSS_IRQHandler(void) -{ - /* Check RCC LSE CSSF flag */ - if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) - { - /* RCC LSE Clock Security System interrupt user callback */ - HAL_RCCEx_LSECSS_Callback(); - - /* Clear RCC LSE CSS pending bit */ - __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); - } -} - -/** - * @brief RCCEx LSE Clock Security System interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_LSECSS_Callback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file - */ -} - -/** - * @brief Select the Low Speed clock source to output on LSCO pin (PA2). - * @param LSCOSource specifies the Low Speed clock source to output. - * This parameter can be one of the following values: - * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source - * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source - * @retval None - */ -void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) -{ - GPIO_InitTypeDef GPIO_InitStruct; - FlagStatus pwrclkchanged = RESET; - FlagStatus backupchanged = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); - - /* LSCO Pin Clock Enable */ - __LSCO_CLK_ENABLE(); - - /* Configue the LSCO pin in analog mode */ - GPIO_InitStruct.Pin = LSCO_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct); - - /* Update LSCOSEL clock source in Backup Domain control register */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - { - HAL_PWR_EnableBkUpAccess(); - backupchanged = SET; - } - - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); - - if(backupchanged == SET) - { - HAL_PWR_DisableBkUpAccess(); - } - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } -} - -/** - * @brief Disable the Low Speed clock output. - * @retval None - */ -void HAL_RCCEx_DisableLSCO(void) -{ - FlagStatus pwrclkchanged = RESET; - FlagStatus backupchanged = RESET; - - /* Update LSCOEN bit in Backup Domain control register */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - { - /* Enable access to the backup domain */ - HAL_PWR_EnableBkUpAccess(); - backupchanged = SET; - } - - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); - - /* Restore previous configuration */ - if(backupchanged == SET) - { - /* Disable access to the backup domain */ - HAL_PWR_DisableBkUpAccess(); - } - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } -} - -/** - * @brief Enable the PLL-mode of the MSI. - * @note Prior to enable the PLL-mode of the MSI for automatic hardware - * calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig(). - * @retval None - */ -void HAL_RCCEx_EnableMSIPLLMode(void) -{ - SET_BIT(RCC->CR, RCC_CR_MSIPLLEN) ; -} - -/** - * @brief Disable the PLL-mode of the MSI. - * @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled. - * @retval None - */ -void HAL_RCCEx_DisableMSIPLLMode(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN) ; -} - -/** - * @} - */ - -#if defined(CRS) - -/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions - * @brief Extended Clock Recovery System Control functions - * -@verbatim - =============================================================================== - ##### Extended Clock Recovery System Control functions ##### - =============================================================================== - [..] - For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows: - - (#) In System clock config, HSI48 needs to be enabled - - (#) Enable CRS clock in IP MSP init which will use CRS functions - - (#) Call CRS functions as follows: - (##) Prepare synchronization configuration necessary for HSI48 calibration - (+++) Default values can be set for frequency Error Measurement (reload and error limit) - and also HSI48 oscillator smooth trimming. - (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate - directly reload value with target and sychronization frequencies values - (##) Call function HAL_RCCEx_CRSConfig which - (+++) Resets CRS registers to their default values. - (+++) Configures CRS registers with synchronization configuration - (+++) Enables automatic calibration and frequency error counter feature - Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the - periodic USB SOF will not be generated by the host. No SYNC signal will therefore be - provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock - precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs - should be used as SYNC signal. - - (##) A polling function is provided to wait for complete synchronization - (+++) Call function HAL_RCCEx_CRSWaitSynchronization() - (+++) According to CRS status, user can decide to adjust again the calibration or continue - application if synchronization is OK - - (#) User can retrieve information related to synchronization in calling function - HAL_RCCEx_CRSGetSynchronizationInfo() - - (#) Regarding synchronization status and synchronization information, user can try a new calibration - in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. - Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), - it means that the actual frequency is lower than the target (and so, that the TRIM value should be - incremented), while when it is detected during the upcounting phase it means that the actual frequency - is higher (and that the TRIM value should be decremented). - - (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go - through CRS Handler (CRS_IRQn/CRS_IRQHandler) - (++) Call function HAL_RCCEx_CRSConfig() - (++) Enable CRS_IRQn (thanks to NVIC functions) - (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) - (++) Implement CRS status management in the following user callbacks called from - HAL_RCCEx_CRS_IRQHandler(): - (+++) HAL_RCCEx_CRS_SyncOkCallback() - (+++) HAL_RCCEx_CRS_SyncWarnCallback() - (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() - (+++) HAL_RCCEx_CRS_ErrorCallback() - - (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). - This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) - -@endverbatim - * @{ - */ - -/** - * @brief Start automatic synchronization for polling mode - * @param pInit Pointer on RCC_CRSInitTypeDef structure - * @retval None - */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) -{ - uint32_t value = 0; - - /* Check the parameters */ - assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); - assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); - assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); - assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); - assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); - assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); - - /* CONFIGURATION */ - - /* Before configuration, reset CRS registers to their default values*/ - __HAL_RCC_CRS_FORCE_RESET(); - __HAL_RCC_CRS_RELEASE_RESET(); - - /* Set the SYNCDIV[2:0] bits according to Prescaler value */ - /* Set the SYNCSRC[1:0] bits according to Source value */ - /* Set the SYNCSPOL bit according to Polarity value */ - value = (pInit->Prescaler | pInit->Source | pInit->Polarity); - /* Set the RELOAD[15:0] bits according to ReloadValue value */ - value |= pInit->ReloadValue; - /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ - value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); - WRITE_REG(CRS->CFGR, value); - - /* Adjust HSI48 oscillator smooth trimming */ - /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ - MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); - - /* START AUTOMATIC SYNCHRONIZATION*/ - - /* Enable Automatic trimming & Frequency error counter */ - SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); -} - -/** - * @brief Generate the software synchronization event - * @retval None - */ -void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) -{ - SET_BIT(CRS->CR, CRS_CR_SWSYNC); -} - -/** - * @brief Return synchronization info - * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure - * @retval None - */ -void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) -{ - /* Check the parameter */ - assert_param(pSynchroInfo != NULL); - - /* Get the reload value */ - pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); - - /* Get HSI48 oscillator smooth trimming */ - pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); - - /* Get Frequency error capture */ - pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); - - /* Get Frequency error direction */ - pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); -} - -/** -* @brief Wait for CRS Synchronization status. -* @param Timeout Duration of the timeout -* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization -* frequency. -* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. -* @retval Combination of Synchronization status -* This parameter can be a combination of the following values: -* @arg @ref RCC_CRS_TIMEOUT -* @arg @ref RCC_CRS_SYNCOK -* @arg @ref RCC_CRS_SYNCWARN -* @arg @ref RCC_CRS_SYNCERR -* @arg @ref RCC_CRS_SYNCMISS -* @arg @ref RCC_CRS_TRIMOVF -*/ -uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) -{ - uint32_t crsstatus = RCC_CRS_NONE; - uint32_t tickstart = 0U; - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait for CRS flag or timeout detection */ - do - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - crsstatus = RCC_CRS_TIMEOUT; - } - } - /* Check CRS SYNCOK flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) - { - /* CRS SYNC event OK */ - crsstatus |= RCC_CRS_SYNCOK; - - /* Clear CRS SYNC event OK bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); - } - - /* Check CRS SYNCWARN flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) - { - /* CRS SYNC warning */ - crsstatus |= RCC_CRS_SYNCWARN; - - /* Clear CRS SYNCWARN bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); - } - - /* Check CRS TRIM overflow flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) - { - /* CRS SYNC Error */ - crsstatus |= RCC_CRS_TRIMOVF; - - /* Clear CRS Error bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); - } - - /* Check CRS Error flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) - { - /* CRS SYNC Error */ - crsstatus |= RCC_CRS_SYNCERR; - - /* Clear CRS Error bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); - } - - /* Check CRS SYNC Missed flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) - { - /* CRS SYNC Missed */ - crsstatus |= RCC_CRS_SYNCMISS; - - /* Clear CRS SYNC Missed bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); - } - - /* Check CRS Expected SYNC flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) - { - /* frequency error counter reached a zero value */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); - } - } while(RCC_CRS_NONE == crsstatus); - - return crsstatus; -} - -/** - * @brief Handle the Clock Recovery System interrupt request. - * @retval None - */ -void HAL_RCCEx_CRS_IRQHandler(void) -{ - uint32_t crserror = RCC_CRS_NONE; - /* Get current IT flags and IT sources values */ - uint32_t itflags = READ_REG(CRS->ISR); - uint32_t itsources = READ_REG(CRS->CR); - - /* Check CRS SYNCOK flag */ - if(((itflags & RCC_CRS_FLAG_SYNCOK) != RESET) && ((itsources & RCC_CRS_IT_SYNCOK) != RESET)) - { - /* Clear CRS SYNC event OK flag */ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); - - /* user callback */ - HAL_RCCEx_CRS_SyncOkCallback(); - } - /* Check CRS SYNCWARN flag */ - else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != RESET) && ((itsources & RCC_CRS_IT_SYNCWARN) != RESET)) - { - /* Clear CRS SYNCWARN flag */ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); - - /* user callback */ - HAL_RCCEx_CRS_SyncWarnCallback(); - } - /* Check CRS Expected SYNC flag */ - else if(((itflags & RCC_CRS_FLAG_ESYNC) != RESET) && ((itsources & RCC_CRS_IT_ESYNC) != RESET)) - { - /* frequency error counter reached a zero value */ - WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); - - /* user callback */ - HAL_RCCEx_CRS_ExpectedSyncCallback(); - } - /* Check CRS Error flags */ - else - { - if(((itflags & RCC_CRS_FLAG_ERR) != RESET) && ((itsources & RCC_CRS_IT_ERR) != RESET)) - { - if((itflags & RCC_CRS_FLAG_SYNCERR) != RESET) - { - crserror |= RCC_CRS_SYNCERR; - } - if((itflags & RCC_CRS_FLAG_SYNCMISS) != RESET) - { - crserror |= RCC_CRS_SYNCMISS; - } - if((itflags & RCC_CRS_FLAG_TRIMOVF) != RESET) - { - crserror |= RCC_CRS_TRIMOVF; - } - - /* Clear CRS Error flags */ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC); - - /* user error callback */ - HAL_RCCEx_CRS_ErrorCallback(crserror); - } - } -} - -/** - * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_SyncOkCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System Error interrupt callback. - * @param Error Combination of Error status. - * This parameter can be a combination of the following values: - * @arg @ref RCC_CRS_SYNCERR - * @arg @ref RCC_CRS_SYNCMISS - * @arg @ref RCC_CRS_TRIMOVF - * @retval none - */ -__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(Error); - - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file - */ -} - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/** @addtogroup RCCEx_Private_Functions - * @{ - */ - -/** - * @brief Configure the parameters N & P & optionally M of PLLSAI1 and enable PLLSAI1 output clock(s). - * @param PllSai1 pointer to an RCC_PLLSAI1InitTypeDef structure that - * contains the configuration parameters N & P & optionally M as well as PLLSAI1 output clock(s) - * @param Divider divider parameter to be updated - * - * @note PLLSAI1 is temporary disable to apply new parameters - * - * @retval HAL status - */ -static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider) -{ - uint32_t tickstart = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* check for PLLSAI1 Parameters used to output PLLSAI1CLK */ - /* P, Q and R dividers are verified in each specific divider case below */ - assert_param(IS_RCC_PLLSAI1SOURCE(PllSai1->PLLSAI1Source)); - assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M)); - assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N)); - assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut)); - - /* Check that PLLSAI1 clock source and divider M can be applied */ - if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) - { - /* PLL clock source and divider M already set, check that no request for change */ - if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source) - || - (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE) -#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - || - (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M) -#endif - ) - { - status = HAL_ERROR; - } - } - else - { - /* Check PLLSAI1 clock source availability */ - switch(PllSai1->PLLSAI1Source) - { - case RCC_PLLSOURCE_MSI: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY)) - { - status = HAL_ERROR; - } - break; - case RCC_PLLSOURCE_HSI: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY)) - { - status = HAL_ERROR; - } - break; - case RCC_PLLSOURCE_HSE: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) - { - status = HAL_ERROR; - } - break; - default: - status = HAL_ERROR; - break; - } - - if(status == HAL_OK) - { -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* Set PLLSAI1 clock source */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source); -#else - /* Set PLLSAI1 clock source and divider M */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos); -#endif - } - } - - if(status == HAL_OK) - { - /* Disable the PLLSAI1 */ - __HAL_RCC_PLLSAI1_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI1 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { - if(Divider == DIVIDER_P_UPDATE) - { - assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P)); -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - - /* Configure the PLLSAI1 Division factor M, P and Multiplication factor N*/ -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV | RCC_PLLSAI1CFGR_PLLSAI1M, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) | - ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); -#else - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1M, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | - ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ - -#else - /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/ -#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)); -#else - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)); -#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ - -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - } - else if(Divider == DIVIDER_Q_UPDATE) - { - assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q)); -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* Configure the PLLSAI1 Division factor M, Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1M, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | - ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); -#else - /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)); -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - } - else - { - assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R)); -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) - /* Configure the PLLSAI1 Division factor M, R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R | RCC_PLLSAI1CFGR_PLLSAI1M, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | - ((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)); -#else - /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI1CFGR, - RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, - (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | - (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)); -#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */ - } - - /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ - __HAL_RCC_PLLSAI1_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI1 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { - /* Configure the PLLSAI1 Clock output(s) */ - __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut); - } - } - } - - return status; -} - -#if defined(RCC_PLLSAI2_SUPPORT) - -/** - * @brief Configure the parameters N & P & optionally M of PLLSAI2 and enable PLLSAI2 output clock(s). - * @param PllSai2 pointer to an RCC_PLLSAI2InitTypeDef structure that - * contains the configuration parameters N & P & optionally M as well as PLLSAI2 output clock(s) - * @param Divider divider parameter to be updated - * - * @note PLLSAI2 is temporary disable to apply new parameters - * - * @retval HAL status - */ -static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider) -{ - uint32_t tickstart = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* check for PLLSAI2 Parameters used to output PLLSAI2CLK */ - /* P, Q and R dividers are verified in each specific divider case below */ - assert_param(IS_RCC_PLLSAI2SOURCE(PllSai2->PLLSAI2Source)); - assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M)); - assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N)); - assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut)); - - /* Check that PLLSAI2 clock source and divider M can be applied */ - if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) - { - /* PLL clock source and divider M already set, check that no request for change */ - if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source) - || - (PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE) -#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - || - (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M) -#endif - ) - { - status = HAL_ERROR; - } - } - else - { - /* Check PLLSAI2 clock source availability */ - switch(PllSai2->PLLSAI2Source) - { - case RCC_PLLSOURCE_MSI: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY)) - { - status = HAL_ERROR; - } - break; - case RCC_PLLSOURCE_HSI: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY)) - { - status = HAL_ERROR; - } - break; - case RCC_PLLSOURCE_HSE: - if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) - { - status = HAL_ERROR; - } - break; - default: - status = HAL_ERROR; - break; - } - - if(status == HAL_OK) - { -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* Set PLLSAI2 clock source */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source); -#else - /* Set PLLSAI2 clock source and divider M */ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos); -#endif - } - } - - if(status == HAL_OK) - { - /* Disable the PLLSAI2 */ - __HAL_RCC_PLLSAI2_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI2 is ready to be updated */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { - if(Divider == DIVIDER_P_UPDATE) - { - assert_param(IS_RCC_PLLSAI2P_VALUE(PllSai2->PLLSAI2P)); -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - - /* Configure the PLLSAI2 Division factor M, P and Multiplication factor N*/ -#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV | RCC_PLLSAI2CFGR_PLLSAI2M, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) | - ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); -#else - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2M, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | - ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); -#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ - -#else - /* Configure the PLLSAI2 Division factor P and Multiplication factor N*/ -#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - (PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)); -#else - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)); -#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */ - -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - } -#if defined(RCC_PLLSAI2Q_DIV_SUPPORT) - else if(Divider == DIVIDER_Q_UPDATE) - { - assert_param(IS_RCC_PLLSAI2Q_VALUE(PllSai2->PLLSAI2Q)); -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* Configure the PLLSAI2 Division factor M, Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q | RCC_PLLSAI2CFGR_PLLSAI2M, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) | - ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); -#else - /* Configure the PLLSAI2 Division factor Q and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - (((PllSai2->PLLSAI2Q >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)); -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - } -#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */ - else - { - assert_param(IS_RCC_PLLSAI2R_VALUE(PllSai2->PLLSAI2R)); -#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) - /* Configure the PLLSAI2 Division factor M, R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R | RCC_PLLSAI2CFGR_PLLSAI2M, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | - ((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)); -#else - /* Configure the PLLSAI2 Division factor R and Multiplication factor N*/ - MODIFY_REG(RCC->PLLSAI2CFGR, - RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, - (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | - (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)); -#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */ - } - - /* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/ - __HAL_RCC_PLLSAI2_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI2 is ready */ - while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { - /* Configure the PLLSAI2 Clock output(s) */ - __HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut); - } - } - } - - return status; -} - -#endif /* RCC_PLLSAI2_SUPPORT */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c deleted file mode 100644 index 469c6af21..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c +++ /dev/null @@ -1,527 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rng.c - * @author MCD Application Team - * @brief RNG HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Random Number Generator (RNG) peripheral: - * + Initialization/de-initialization functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The RNG HAL driver can be used as follows: - - (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro - in HAL_RNG_MspInit(). - (#) Activate the RNG peripheral using HAL_RNG_Init() function. - (#) Wait until the 32-bit Random Number Generator contains a valid - random data using (polling/interrupt) mode. - (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup RNG RNG - * @brief RNG HAL module driver. - * @{ - */ - -#ifdef HAL_RNG_MODULE_ENABLED - - - -/* Private types -------------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup RNG_Private_Constants RNG_Private_Constants - * @{ - */ -#define RNG_TIMEOUT_VALUE 2 -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup RNG_Exported_Functions - * @{ - */ - -/** @addtogroup RNG_Exported_Functions_Group1 - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the RNG according to the specified parameters - in the RNG_InitTypeDef and create the associated handle - (+) DeInitialize the RNG peripheral - (+) Initialize the RNG MSP (MCU Specific Package) - (+) DeInitialize the RNG MSP - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the RNG peripheral and initialize the associated handle. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) -{ - /* Check the RNG handle allocation */ - if(hrng == NULL) - { - return HAL_ERROR; - } - - assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); -#if defined(RNG_CR_CED) - assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection)); -#endif /* defined(RNG_CR_CED) */ - - if(hrng->State == HAL_RNG_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrng->Lock = HAL_UNLOCKED; - - /* Init the low level hardware */ - HAL_RNG_MspInit(hrng); - } - - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - -#if defined(RNG_CR_CED) - /* Clock Error Detection configuration */ - MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); -#endif /* defined(RNG_CR_CED) */ - - /* Enable the RNG Peripheral */ - __HAL_RNG_ENABLE(hrng); - - /* Initialize the RNG state */ - hrng->State = HAL_RNG_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitialize the RNG peripheral. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) -{ - /* Check the RNG handle allocation */ - if(hrng == NULL) - { - return HAL_ERROR; - } - -#if defined(RNG_CR_CED) - /* Clear Clock Error Detection bit */ - CLEAR_BIT(hrng->Instance->CR, RNG_CR_CED); -#endif /* defined(RNG_CR_CED) */ - - /* Disable the RNG Peripheral */ - CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN); - - /* Clear RNG interrupt status flags */ - CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS); - - /* DeInit the low level hardware */ - HAL_RNG_MspDeInit(hrng); - - /* Update the RNG state */ - hrng->State = HAL_RNG_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hrng); - - /* Return the function status */ - return HAL_OK; -} - -/** - * @brief Initialize the RNG MSP. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval None - */ -__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_MspInit must be implemented in the user file. - */ -} - -/** - * @brief DeInitialize the RNG MSP. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval None - */ -__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_MspDeInit must be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @addtogroup RNG_Exported_Functions_Group2 - * @brief Management functions. - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Get the 32 bit Random number - (+) Get the 32 bit Random number with interrupt enabled - (+) Handle RNG interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Generate a 32-bit random number. - * @note Each time the random number data is read the RNG_FLAG_DRDY flag - * is automatically cleared. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @param random32bit: pointer to generated random number variable if successful. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit) -{ - uint32_t tickstart = 0; - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(hrng); - - /* Check RNS peripheral state */ - if(hrng->State == HAL_RNG_STATE_READY) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if data register contains valid random data */ - while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE) - { - hrng->State = HAL_RNG_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - - return HAL_TIMEOUT; - } - } - - /* Get a 32bit Random number */ - hrng->RandomNumber = hrng->Instance->DR; - *random32bit = hrng->RandomNumber; - - hrng->State = HAL_RNG_STATE_READY; - } - else - { - status = HAL_ERROR; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - - return status; -} - -/** - * @brief Generate a 32-bit random number in interrupt mode. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(hrng); - - /* Check RNG peripheral state */ - if(hrng->State == HAL_RNG_STATE_READY) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - - /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ - __HAL_RNG_ENABLE_IT(hrng); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Handle RNG interrupt request. - * @note In the case of a clock error, the RNG is no more able to generate - * random numbers because the PLL48CLK clock is not correct. User has - * to check that the clock controller is correctly configured to provide - * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). - * The clock error has no impact on the previously generated - * random numbers, and the RNG_DR register contents can be used. - * @note In the case of a seed error, the generation of random numbers is - * interrupted as long as the SECS bit is '1'. If a number is - * available in the RNG_DR register, it must not be used because it may - * not have enough entropy. In this case, it is recommended to clear the - * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable - * the RNG peripheral to reinitialize and restart the RNG. - * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS - * or CEIS are set. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval None - - */ -void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) -{ - /* RNG clock error interrupt occurred */ - if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_ERROR; - - HAL_RNG_ErrorCallback(hrng); - - /* Clear the clock error flag */ - __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI); - - } - - /* Check RNG data ready interrupt occurred */ - if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET) - { - /* Generate random number once, so disable the IT */ - __HAL_RNG_DISABLE_IT(hrng); - - /* Get the 32bit Random number (DRDY flag automatically cleared) */ - hrng->RandomNumber = hrng->Instance->DR; - - if(hrng->State != HAL_RNG_STATE_ERROR) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_READY; - - /* Data Ready callback */ - HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber); - } - } -} - -/** - * @brief Return generated random number in polling mode (Obsolete). - * @note Use HAL_RNG_GenerateRandomNumber() API instead. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval random value - */ -uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng) -{ - if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK) - { - return hrng->RandomNumber; - } - else - { - return 0; - } -} - - -/** - * @brief Return a 32-bit random number with interrupt enabled (Obsolete). - * @note Use HAL_RNG_GenerateRandomNumber_IT() API instead. - * @param hrng: RNG handle - * @retval 32-bit random number - */ -uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) -{ - uint32_t random32bit = 0; - - /* Process locked */ - __HAL_LOCK(hrng); - - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - /* Get a 32bit Random number */ - random32bit = hrng->Instance->DR; - - /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ - __HAL_RNG_ENABLE_IT(hrng); - - /* Return the 32 bit random number */ - return random32bit; -} - - - -/** - * @brief Read latest generated random number. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval random value - */ -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) -{ - return(hrng->RandomNumber); -} - -/** - * @brief Data Ready callback in non-blocking mode. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @param random32bit: generated random value - * @retval None - */ -__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - UNUSED(random32bit); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_ReadyDataCallback must be implemented in the user file. - */ -} - -/** - * @brief RNG error callback. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval None - */ -__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_ErrorCallback must be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @addtogroup RNG_Exported_Functions_Group3 - * @brief Peripheral State functions. - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Return the RNG handle state. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval HAL state - */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) -{ - /* Return RNG handle state */ - return hrng->State; -} - -/** - * @} - */ - -/** - * @} - */ - - -#endif /* HAL_RNG_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c deleted file mode 100644 index 73ffaf2f1..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c +++ /dev/null @@ -1,1539 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rtc.c - * @author MCD Application Team - * @brief RTC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) peripheral: - * + Initialization - * + Calendar (Time and Date) configuration - * + Alarms (Alarm A and Alarm B) configuration - * + WakeUp Timer configuration - * + TimeStamp configuration - * + Tampers configuration - * + Backup Data Registers configuration - * + RTC Tamper and TimeStamp Pins Selection - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### RTC Operating Condition ##### - =============================================================================== - [..] The real-time clock (RTC) and the RTC backup registers can be powered - from the VBAT voltage when the main VDD supply is powered off. - To retain the content of the RTC backup registers and supply the RTC - when VDD is turned off, VBAT pin can be connected to an optional - standby voltage supplied by a battery or by another source. - - ##### Backup Domain Reset ##### - =============================================================================== - [..] The backup domain reset sets all RTC registers and the RCC_BDCR register - to their reset values. - A backup domain reset is generated when one of the following events occurs: - (#) Software reset, triggered by setting the BDRST bit in the - RCC Backup domain control register (RCC_BDCR). - (#) VDD or VBAT power on, if both supplies have previously been powered off. - (#) Tamper detection event resets all data backup registers. - - ##### Backup Domain Access ##### - =================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted write - accesses. - - [..] To enable access to the RTC Domain and RTC registers, proceed as follows: - (#) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for - PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32) - (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro. - - ##### How to use RTC Driver ##### - =================================================================== - [..] - (#) Enable the RTC domain access (see description in the section above). - (#) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. - - *** Time and Date configuration *** - =================================== - [..] - (#) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() - and HAL_RTC_SetDate() functions. - (#) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. - - *** Alarm configuration *** - =========================== - [..] - (#) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. - You can also configure the RTC Alarm with interrupt mode using the - HAL_RTC_SetAlarm_IT() function. - (#) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. - - ##### RTC and low power modes ##### - =================================================================== - [..] The MCU can be woken up from a low power mode by an RTC alternate - function. - [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - These RTC alternate functions can wake up the system from the Stop and - Standby low power modes. - [..] The system can also wake up from low power modes without depending - on an external interrupt (Auto-wakeup mode), by using the RTC alarm - or the RTC wakeup events. - [..] The RTC provides a programmable time base for waking up from the - Stop or Standby mode at regular intervals. - Wakeup from STOP and Standby modes is possible only when the RTC clock source - is LSE or LSI. - - @endverbatim - - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup RTC RTC - * @brief RTC HAL module driver - * @{ - */ - -#ifdef HAL_RTC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Functions RTC Exported Functions - * @{ - */ - -/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provide functions allowing to initialize and configure the - RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable - RTC registers Write protection, enter and exit the RTC initialization mode, - RTC registers synchronization check and reference clock detection enable. - (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. - It is split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler. - (++) When both prescalers are used, it is recommended to configure the - asynchronous prescaler to a high value to minimize power consumption. - (#) All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - (#) To configure the RTC Calendar, user application should enter - initialization mode. In this mode, the calendar counter is stopped - and its value can be updated. When the initialization sequence is - complete, the calendar restarts counting after 4 RTCCLK cycles. - (#) To read the calendar through the shadow registers after Calendar - initialization, calendar update or after wakeup from low power modes - the software must first clear the RSF flag. The software must then - wait until it is set again before reading the calendar, which means - that the calendar registers have been correctly copied into the - RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function - implements the above software sequence (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the RTC according to the specified parameters - * in the RTC_InitTypeDef structure and initialize the associated handle. - * @param hrtc: RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) -{ - /* Check the RTC peripheral state */ - if(hrtc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); - assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); - assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap)); - assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); - assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); - - if(hrtc->State == HAL_RTC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrtc->Lock = HAL_UNLOCKED; - - /* Initialize RTC MSP */ - HAL_RTC_MspInit(hrtc); - } - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - else - { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); - /* Set RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); - - /* Configure the RTC PRER */ - hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - } - - hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP); - hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; - } -} - -/** - * @brief DeInitialize the RTC peripheral. - * @param hrtc: RTC handle - * @note This function doesn't reset the RTC Backup Data registers. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - hrtc->Instance->TR = (uint32_t)0x00000000; - hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); - /* Reset All CR bits except CR[2:0] */ - hrtc->Instance->CR &= RTC_CR_WUCKSEL; - - tickstart = HAL_GetTick(); - - /* Wait till WUTWF flag is set and if Time out is reached exit */ - while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - - /* Reset all RTC CR register bits */ - hrtc->Instance->CR &= (uint32_t)0x00000000; - hrtc->Instance->WUTR = RTC_WUTR_WUT; - hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF)); - hrtc->Instance->ALRMAR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBR = (uint32_t)0x00000000; - hrtc->Instance->SHIFTR = (uint32_t)0x00000000; - hrtc->Instance->CALR = (uint32_t)0x00000000; - hrtc->Instance->ALRMASSR = (uint32_t)0x00000000; - hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000; - - /* Reset ISR register and exit initialization mode */ - hrtc->Instance->ISR = (uint32_t)0x00000000; - - /* Reset Tamper configuration register */ - hrtc->Instance->TAMPCR = 0x00000000; - - /* Reset Option register */ - hrtc->Instance->OR = 0x00000000; - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* De-Initialize RTC MSP */ - HAL_RTC_MspDeInit(hrtc); - - hrtc->State = HAL_RTC_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Initialize the RTC MSP. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the RTC MSP. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTC_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions - * @brief RTC Time and Date functions - * -@verbatim - =============================================================================== - ##### RTC Time and Date functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Time and Date features - -@endverbatim - * @{ - */ - -/** - * @brief Set RTC current time. - * @param hrtc: RTC handle - * @param sTime: Pointer to Time structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if(Format == RTC_FORMAT_BIN) - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(sTime->Hours)); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(sTime->Hours)); - } - assert_param(IS_RTC_MINUTES(sTime->Minutes)); - assert_param(IS_RTC_SECONDS(sTime->Seconds)); - - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ - (((uint32_t)sTime->TimeFormat) << 16)); - } - else - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(sTime->Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - tmpreg = (((uint32_t)(sTime->Hours) << 16) | \ - ((uint32_t)(sTime->Minutes) << 8) | \ - ((uint32_t)sTime->Seconds) | \ - ((uint32_t)(sTime->TimeFormat) << 16)); - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Set the RTC_TR register */ - hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Clear the bits to be configured */ - hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK); - - /* Configure the RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - __HAL_UNLOCK(hrtc); - - return HAL_OK; - } -} - -/** - * @brief Get RTC current time. - * @param hrtc: RTC handle - * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned - * with input format (BIN or BCD), also SubSeconds field returning the - * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler - * factor to be used for second fraction ratio computation. - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds - * value in second fraction ratio with time unit following generic formula: - * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit - * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers to ensure consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers until Current date is read - * to ensure consistency between the time and date values. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get subseconds structure field from the corresponding register*/ - sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); - - /* Get SecondFraction structure field from the corresponding register field*/ - sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); - - /* Get the TR register */ - tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); - - /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) - { - /* Convert the time structure parameters to Binary format */ - sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); - sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); - sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); - } - - return HAL_OK; -} - -/** - * @brief Set RTC current date. - * @param hrtc: RTC handle - * @param sDate: Pointer to date structure - * @param Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) -{ - uint32_t datetmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) - { - sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); - } - - assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); - - if(Format == RTC_FORMAT_BIN) - { - assert_param(IS_RTC_YEAR(sDate->Year)); - assert_param(IS_RTC_MONTH(sDate->Month)); - assert_param(IS_RTC_DATE(sDate->Date)); - - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ - ((uint32_t)sDate->WeekDay << 13)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); - datetmpreg = RTC_Bcd2ToByte(sDate->Month); - assert_param(IS_RTC_MONTH(datetmpreg)); - datetmpreg = RTC_Bcd2ToByte(sDate->Date); - assert_param(IS_RTC_DATE(datetmpreg)); - - datetmpreg = ((((uint32_t)sDate->Year) << 16) | \ - (((uint32_t)sDate->Month) << 8) | \ - ((uint32_t)sDate->Date) | \ - (((uint32_t)sDate->WeekDay) << 13)); - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Set the RTC_DR register */ - hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY ; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; - } -} - -/** - * @brief Get RTC current date. - * @param hrtc: RTC handle - * @param sDate: Pointer to Date structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers to ensure consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers until Current date is read. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) -{ - uint32_t datetmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get the DR register */ - datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); - sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) - { - /* Convert the date structure parameters to Binary format */ - sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); - sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); - sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); - } - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions - * @brief RTC Alarm functions - * -@verbatim - =============================================================================== - ##### RTC Alarm functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Alarm feature - -@endverbatim - * @{ - */ -/** - * @brief Set the specified RTC Alarm. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) -{ - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(sAlarm->Alarm)); - assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if(Format == RTC_FORMAT_BIN) - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); - } - assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); - assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); - } - - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - else - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - - /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Alarm register */ - if(sAlarm->Alarm == RTC_ALARM_A) - { - /* Disable the Alarm A interrupt */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Sub Second register */ - hrtc->Instance->ALRMASSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(hrtc); - } - else - { - /* Disable the Alarm B interrupt */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm B Sub Second register */ - hrtc->Instance->ALRMBSSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMB_ENABLE(hrtc); - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set the specified RTC Alarm with Interrupt. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Alarm structure - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the HAL_RTC_DeactivateAlarm()). - * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) -{ - uint32_t tickstart = 0; - uint32_t tmpreg = 0, subsecondtmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(sAlarm->Alarm)); - assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if(Format == RTC_FORMAT_BIN) - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); - } - assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); - assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); - } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - else - { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Alarm register */ - if(sAlarm->Alarm == RTC_ALARM_A) - { - /* Disable the Alarm A interrupt */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* Clear flag alarm A */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Sub Second register */ - hrtc->Instance->ALRMASSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(hrtc); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA); - } - else - { - /* Disable the Alarm B interrupt */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* Clear flag alarm B */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm B Sub Second register */ - hrtc->Instance->ALRMBSSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMB_ENABLE(hrtc); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB); - } - - /* RTC Alarm Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate the specified RTC Alarm. - * @param hrtc: RTC handle - * @param Alarm: Specifies the Alarm. - * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALARM(Alarm)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - if(Alarm == RTC_ALARM_A) - { - /* AlarmA */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) - { - if( (HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - else - { - /* AlarmB */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB); - - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Get the RTC Alarm value and masks. - * @param hrtc: RTC handle - * @param sAlarm: Pointer to Date structure - * @param Alarm: Specifies the Alarm. - * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB - * @param Format: Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) -{ - uint32_t tmpreg = 0, subsecondtmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(Alarm)); - - if(Alarm == RTC_ALARM_A) - { - /* AlarmA */ - sAlarm->Alarm = RTC_ALARM_A; - - tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); - } - else - { - sAlarm->Alarm = RTC_ALARM_B; - - tmpreg = (uint32_t)(hrtc->Instance->ALRMBR); - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); - } - - /* Fill the structure with the read parameters */ - /* ALRMAR/ALRMBR registers have same mapping) */ - sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16); - sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8); - sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; - sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); - - if(Format == RTC_FORMAT_BIN) - { - sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); - sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); - sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - } - - return HAL_OK; -} - -/** - * @brief Handle Alarm interrupt request. - * @param hrtc: RTC handle - * @retval None - */ -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) -{ - /* Clear the EXTI's line Flag for RTC Alarm */ - __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); - - /* As alarms are sharing the same EXTI line, exit when no more pending Alarm event */ - while(((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)) || - ((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET))) - { - /* Get the AlarmA interrupt source enable status and pending flag status*/ - if((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)) - { - /* Clear the AlarmA interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* AlarmA callback */ - HAL_RTC_AlarmAEventCallback(hrtc); - } - - /* Get the AlarmB interrupt source enable status and pending flag status*/ - if((__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET) && (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)) - { - /* Clear the AlarmB interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - /* AlarmB callback */ - HAL_RTCEx_AlarmBEventCallback(hrtc); - } - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Alarm A callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTC_AlarmAEventCallback could be implemented in the user file - */ -} - -/** - * @brief Handle AlarmA Polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Alarm interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Wait for RTC Time and Date Synchronization - -@endverbatim - * @{ - */ - -/** - * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc: RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) -{ - uint32_t tickstart = 0; - - /* Clear RSF flag */ - hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; - - tickstart = HAL_GetTick(); - - /* Wait the registers to be synchronised */ - while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Get RTC state - -@endverbatim - * @{ - */ -/** - * @brief Return the RTC handle state. - * @param hrtc: RTC handle - * @retval HAL state - */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) -{ - /* Return RTC handle state */ - return hrtc->State; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Functions RTC Private functions - * @{ - */ -/** - * @brief Enter the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc: RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) -{ - uint32_t tickstart = 0; - - /* Check if the Initialization mode is set */ - if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; - - tickstart = HAL_GetTick(); - /* Wait till RTC is in INIT state and if Time out is reached exit */ - while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - - -/** - * @brief Convert a 2 digit decimal to BCD format. - * @param Value: Byte to be converted - * @retval Converted byte - */ -uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint32_t bcdhigh = 0; - - while(Value >= 10) - { - bcdhigh++; - Value -= 10; - } - - return ((uint8_t)(bcdhigh << 4) | Value); -} - -/** - * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted - * @retval Converted word - */ -uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint32_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); -} - -/** - * @} - */ - -#endif /* HAL_RTC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c deleted file mode 100644 index 31a6fe7de..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c +++ /dev/null @@ -1,1875 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_rtc_ex.c - * @author MCD Application Team - * @brief Extended RTC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) Extended peripheral: - * + RTC Time Stamp functions - * + RTC Tamper functions - * + RTC Wake-up functions - * + Extended Control functions - * + Extended RTC features functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (+) Enable the RTC domain access. - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. - - *** RTC Wakeup configuration *** - ================================ - [..] - (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() - function. You can also configure the RTC Wakeup timer with interrupt mode - using the HAL_RTCEx_SetWakeUpTimer_IT() function. - (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() - function. - - *** Outputs configuration *** - ============================= - [..] The RTC has 2 different outputs: - (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B - and WaKeUp signals. - To output the selected RTC signal, use the HAL_RTC_Init() function. - (+) RTC_CALIB: this output is 512Hz signal or 1Hz. - To enable the RTC_CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function. - (+) Two pins can be used as RTC_ALARM or RTC_CALIB (PC13, PB2) managed on - the RTC_OR register. - (+) When the RTC_CALIB or RTC_ALARM output is selected, the RTC_OUT pin is - automatically configured in output alternate function. - - *** Smooth digital Calibration configuration *** - ================================================ - [..] - (+) Configure the RTC Original Digital Calibration Value and the corresponding - calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib() - function. - - *** TimeStamp configuration *** - =============================== - [..] - (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function. - You can also configure the RTC TimeStamp with interrupt mode using the - HAL_RTCEx_SetTimeStamp_IT() function. - (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() - function. - - *** Internal TimeStamp configuration *** - =============================== - [..] - (+) Enable the RTC internal TimeStamp using the HAL_RTCEx_SetInternalTimeStamp() function. - User has to check internal timestamp occurrence using __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG. - (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() - function. - - *** Tamper configuration *** - ============================ - [..] - (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge - or Level according to the Tamper filter (if equal to 0 Edge else Level) - value, sampling frequency, NoErase, MaskFlag, precharge or discharge and - Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper - with interrupt mode using HAL_RTCEx_SetTamper_IT() function. - (+) The default configuration of the Tamper erases the backup registers. To avoid - erase, enable the NoErase field on the RTC_TAMPCR register. - - *** Backup Data Registers configuration *** - =========================================== - [..] - (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() - function. - (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() - function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup RTCEx RTCEx - * @brief RTC Extended HAL module driver - * @{ - */ - -#ifdef HAL_RTC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT) -#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS |\ - (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ - (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE |\ - (uint32_t)RTC_TAMPCR_TAMP1IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\ - (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF |\ - (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF) -#elif defined(RTC_TAMPER1_SUPPORT) -#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS |\ - (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ - (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE |\ - (uint32_t)RTC_TAMPCR_TAMP1IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\ - (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF) -#elif defined(RTC_TAMPER3_SUPPORT) -#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS |\ - (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ - (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE |\ - (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF |\ - (uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF) -#else -#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS |\ - (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ - (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE |\ - (uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF) -#endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions - * @{ - */ - - -/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions - * @brief RTC TimeStamp and Tamper functions - * -@verbatim - =============================================================================== - ##### RTC TimeStamp and Tamper functions ##### - =============================================================================== - - [..] This section provide functions allowing to configure TimeStamp feature - -@endverbatim - * @{ - */ - -/** - * @brief Set TimeStamp. - * @note This API must be called before enabling the TimeStamp feature. - * @param hrtc: RTC handle - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the - * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the - * falling edge of the related pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. - * The RTC TimeStamp Pin is per default PC13, but for reasons of - * compatibility, this parameter is required. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); - assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - tmpreg|= TimeStampEdge; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set TimeStamp with Interrupt. - * @param hrtc: RTC handle - * @note This API must be called before enabling the TimeStamp feature. - * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the - * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the - * falling edge of the related pin. - * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. - * The RTC TimeStamp Pin is per default PC13, but for reasons of - * compatibility, this parameter is required. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); - assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - tmpreg |= TimeStampEdge; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - - /* Enable IT timestamp */ - __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); - - /* RTC timestamp Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate TimeStamp. - * @param hrtc: RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) -{ - uint32_t tmpreg = 0; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set Internal TimeStamp. - * @note This API must be called before enabling the internal TimeStamp feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the internal Time Stamp Enable bits */ - __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate Internal TimeStamp. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the internal Time Stamp Enable bits */ - __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Get the RTC TimeStamp value. - * @param hrtc: RTC handle - * @param sTimeStamp: Pointer to Time structure - * @param sTimeStampDate: Pointer to Date structure - * @param Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) -{ - uint32_t tmptime = 0, tmpdate = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); - sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; - - /* Fill the Date structure fields with the read parameters */ - sTimeStampDate->Year = 0; - sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) - { - /* Convert the TimeStamp structure parameters to Binary format */ - sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); - sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); - sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); - - /* Convert the DateTimeStamp structure parameters to Binary format */ - sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); - sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); - sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); - } - - /* Clear the TIMESTAMP Flags */ - __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_ITSF); - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - - return HAL_OK; -} - -/** - * @brief Set Tamper. - * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc: RTC handle - * @param sTamper: Pointer to Tamper Structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); - assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); - assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Configure the tamper trigger */ - if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) - { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); - } - - if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) - { - sTamper->NoErase = 0; -#if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; - } -#endif /* RTC_TAMPER3_SUPPORT */ - } - - if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) - { - sTamper->MaskFlag = 0; -#if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; - } -#endif /* RTC_TAMPER3_SUPPORT */ - } - - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ - (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ - (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK); - - hrtc->Instance->TAMPCR |= tmpreg; - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set Tamper with interrupt. - * @note By calling this API we force the tamper interrupt for all tampers. - * @param hrtc: RTC handle - * @param sTamper: Pointer to RTC Tamper. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); - assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); - assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Configure the tamper trigger */ - if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) - { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); - } - - if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) - { - sTamper->NoErase = 0; -#if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; - } -#endif /* RTC_TAMPER3_SUPPORT */ - } - - if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) - { - sTamper->MaskFlag = 0; -#if defined(RTC_TAMPER1_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_1) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; - } -#endif /* RTC_TAMPER1_SUPPORT */ - if((sTamper->Tamper & RTC_TAMPER_2) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; - } -#if defined(RTC_TAMPER3_SUPPORT) - if((sTamper->Tamper & RTC_TAMPER_3) != 0) - { - sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; - } -#endif /* RTC_TAMPER3_SUPPORT */ - } - - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ - (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ - (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK); - - hrtc->Instance->TAMPCR |= tmpreg; - - /* RTC Tamper Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate Tamper. - * @param hrtc: RTC handle - * @param Tamper: Selected tamper pin. - * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) -{ - assert_param(IS_RTC_TAMPER(Tamper)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the selected Tamper pin */ - hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper); - -#if defined(RTC_TAMPER1_SUPPORT) - if ((Tamper & RTC_TAMPER_1) != 0) - { - /* Disable the Tamper1 interrupt */ - hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1)); - } -#endif /* RTC_TAMPER1_SUPPORT */ - if ((Tamper & RTC_TAMPER_2) != 0) - { - /* Disable the Tamper2 interrupt */ - hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2)); - } -#if defined(RTC_TAMPER3_SUPPORT) - if ((Tamper & RTC_TAMPER_3) != 0) - { - /* Disable the Tamper3 interrupt */ - hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3)); - } -#endif /* RTC_TAMPER3_SUPPORT */ - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Handle TimeStamp interrupt request. - * @param hrtc: RTC handle - * @retval None - */ -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); - - /* As Tampers and TimeStamp are sharing the same EXTI line, exit when no more pending event */ - while( - ((__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET) && (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)) -#if defined(RTC_TAMPER1_SUPPORT) - || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)) -#endif /* RTC_TAMPER1_SUPPORT */ - || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)) -#if defined(RTC_TAMPER3_SUPPORT) - || ((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)) -#endif /* RTC_TAMPER3_SUPPORT */ - ) - { - - /* Get the TimeStamp interrupt source enable status and pending flag status */ - if((__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET) && (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)) - { - /* TIMESTAMP callback */ - HAL_RTCEx_TimeStampEventCallback(hrtc); - - /* Clear the TIMESTAMP interrupt pending bit (this will clear timestamp time and date registers) */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - } - -#if defined(RTC_TAMPER1_SUPPORT) - /* Get the Tamper1 interrupt source enable status and pending flag status */ - if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)) - { - /* Clear the Tamper1 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - - /* Tamper1 callback */ - HAL_RTCEx_Tamper1EventCallback(hrtc); - } -#endif /* RTC_TAMPER1_SUPPORT */ - - /* Get the Tamper2 interrupt source enable status and pending flag status */ - if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)) - { - /* Clear the Tamper2 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - - /* Tamper2 callback */ - HAL_RTCEx_Tamper2EventCallback(hrtc); - } - -#if defined(RTC_TAMPER3_SUPPORT) - /* Get the Tamper3 interrupts source enable status and pending flag status */ - if((__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != RESET) && (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)) - { - /* Clear the Tamper3 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); - - /* Tamper3 callback */ - HAL_RTCEx_Tamper3EventCallback(hrtc); - } -#endif /* RTC_TAMPER3_SUPPORT */ - - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief TimeStamp callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file - */ -} - -#if defined(RTC_TAMPER1_SUPPORT) -/** - * @brief Tamper 1 callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file - */ -} -#endif /* RTC_TAMPER1_SUPPORT */ - -/** - * @brief Tamper 2 callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file - */ -} - -#if defined(RTC_TAMPER3_SUPPORT) -/** - * @brief Tamper 3 callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file - */ -} -#endif /* RTC_TAMPER3_SUPPORT */ - -/** - * @brief Handle TimeStamp polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) - { - if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) - { - /* Clear the TIMESTAMP OverRun Flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - - /* Change TIMESTAMP state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -#if defined(RTC_TAMPER1_SUPPORT) -/** - * @brief Handle Tamper 1 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} -#endif /* RTC_TAMPER1_SUPPORT */ - -/** - * @brief Handle Tamper 2 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -#if defined(RTC_TAMPER3_SUPPORT) -/** - * @brief Handle Tamper 3 Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} -#endif /* RTC_TAMPER3_SUPPORT */ - -/** - * @} - */ - -/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions - * @brief RTC Wake-up functions - * -@verbatim - =============================================================================== - ##### RTC Wake-up functions ##### - =============================================================================== - - [..] This section provide functions allowing to configure Wake-up feature - -@endverbatim - * @{ - */ - -/** - * @brief Set wake up timer. - * @param hrtc: RTC handle - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) - { - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; - - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set wake up timer with interrupt. - * @param hrtc: RTC handle - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) - { - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - /* Disable the Wake-Up timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* Clear flag Wake-Up */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; - - /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); - - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); - - /* Configure the Interrupt in the RTC_CR register */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); - - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate wake up timer counter. - * @param hrtc: RTC handle - * @retval HAL status - */ -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Disable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); - - tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Get wake up timer counter. - * @param hrtc: RTC handle - * @retval Counter value - */ -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) -{ - /* Get the counter value */ - return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief Handle Wake Up Timer interrupt request. - * @param hrtc: RTC handle - * @retval None - */ -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Clear the EXTI's line Flag for RTC WakeUpTimer */ - __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); - - /* Get the pending status of the WAKEUPTIMER Interrupt */ - if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET) - { - /* Clear the WAKEUPTIMER interrupt pending bit */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - /* WAKEUPTIMER callback */ - HAL_RTCEx_WakeUpTimerEventCallback(hrtc); - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Wake Up Timer callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file - */ -} - -/** - * @brief Handle Wake Up Timer Polling. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - } - - /* Clear the WAKEUPTIMER Flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - - -/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Write a data in a specified RTC Backup data register - (+) Read a data in a specified RTC Backup data register - (+) Set the Coarse calibration parameters. - (+) Deactivate the Coarse calibration parameters - (+) Set the Smooth calibration parameters. - (+) Configure the Synchronization Shift Control Settings. - (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Enable the RTC reference clock detection. - (+) Disable the RTC reference clock detection. - (+) Enable the Bypass Shadow feature. - (+) Disable the Bypass Shadow feature. - -@endverbatim - * @{ - */ - -/** - * @brief Write a data in a specified RTC Backup data register. - * @param hrtc: RTC handle - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Read data from the specified RTC Backup data Register. - * @param hrtc: RTC handle - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval Read value - */ -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @brief Set the Smooth calibration parameters. - * @param hrtc: RTC handle - * @param SmoothCalibPeriod: Select the Smooth Calibration Period. - * This parameter can be can be one of the following values : - * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. - * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. - * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. - * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. - * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses - * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field - * SmoothCalibMinusPulsesValue must be equal to 0. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* check if a calibration is pending*/ - if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) - { - tickstart = HAL_GetTick(); - - /* check if a calibration is pending*/ - while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - - /* Configure the Smooth calibration settings */ - hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Configure the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc: RTC handle - * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. - * This parameter can be one of the following values : - * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. - * @arg RTC_SHIFTADD1S_RESET: No effect. - * @param ShiftSubFS: Select the number of Second Fractions to substitute. - * This parameter can be one any value from 0 to 0x7FFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - tickstart = HAL_GetTick(); - - /* Wait until the shift is completed*/ - while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Check if the reference clock detection is disabled */ - if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - } - else - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: RTC handle - * @param CalibOutput : Select the Calibration output Selection . - * This parameter can be one of the following values: - * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. - * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) -{ - /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Clear flags before config */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; - - /* Configure the RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)CalibOutput; - - __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Enable the RTC reference clock detection. - * @param hrtc: RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Disable the RTC reference clock detection. - * @param hrtc: RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Enable the Bypass Shadow feature. - * @param hrtc: RTC handle - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set the BYPSHAD bit */ - hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Disable the Bypass Shadow feature. - * @param hrtc: RTC handle - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) RTC Alarm B callback - (+) RTC Poll for Alarm B request - -@endverbatim - * @{ - */ - -/** - * @brief Alarm B callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file - */ -} - -/** - * @brief Handle Alarm B Polling request. - * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Alarm Flag */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RTC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c deleted file mode 100644 index f60505f99..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c +++ /dev/null @@ -1,5675 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_tim.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer (TIM) peripheral: - * + Time Base Initialization - * + Time Base Start - * + Time Base Start Interruption - * + Time Base Start DMA - * + Time Output Compare/PWM Initialization - * + Time Output Compare/PWM Channel Configuration - * + Time Output Compare/PWM Start - * + Time Output Compare/PWM Start Interruption - * + Time Output Compare/PWM Start DMA - * + Time Input Capture Initialization - * + Time Input Capture Channel Configuration - * + Time Input Capture Start - * + Time Input Capture Start Interruption - * + Time Input Capture Start DMA - * + Time One Pulse Initialization - * + Time One Pulse Channel Configuration - * + Time One Pulse Start - * + Time Encoder Interface Initialization - * + Time Encoder Interface Start - * + Time Encoder Interface Start Interruption - * + Time Encoder Interface Start DMA - * + Commutation Event configuration with Interruption and DMA - * + Time OCRef clear configuration - * + Time External Clock configuration - @verbatim - ============================================================================== - ##### TIMER Generic features ##### - ============================================================================== - [..] The Timer features include: - (#) 16-bit up, down, up/down auto-reload counter. - (#) 16-bit programmable prescaler allowing dividing (also on the fly) the - counter clock frequency either by any factor between 1 and 65536. - (#) Up to 4 independent channels for: - (++) Input Capture - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending on the selected feature: - (++) Time Base : HAL_TIM_Base_MspInit() - (++) Input Capture : HAL_TIM_IC_MspInit() - (++) Output Compare : HAL_TIM_OC_MspInit() - (++) PWM generation : HAL_TIM_PWM_MspInit() - (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() - (++) Encoder mode output : HAL_TIM_Encoder_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - Initialization function of this driver: - (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base - (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an - Output Compare signal. - (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a - PWM signal. - (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an - external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. - (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. - - (#) Activate the TIM peripheral using one of the start functions depending from the feature used: - (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() - (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() - (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() - (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() - (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() - (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). - - (#) The DMA Burst is managed with the two following functions: - HAL_TIM_DMABurst_WriteStart() - HAL_TIM_DMABurst_ReadStart() - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup TIM TIM - * @brief TIM HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); -static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig); -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @defgroup TIM_Exported_Functions_Group1 Time Base functions - * @brief Time Base functions - * -@verbatim - ============================================================================== - ##### Time Base functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM base. - (+) De-initialize the TIM base. - (+) Start the Time Base. - (+) Stop the Time Base. - (+) Start the Time Base and enable interrupt. - (+) Stop the Time Base and disable interrupt. - (+) Start the Time Base and enable DMA transfer. - (+) Stop the Time Base and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Time base Unit according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Set the Time Base configuration */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the TIM Base peripheral - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Base MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Base_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize TIM Base MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Base_MspDeInit could be implemented in the user file - */ -} - - -/** - * @brief Starts the TIM Base generation. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in interrupt mode. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Enable the TIM Update interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in interrupt mode. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Disable the TIM Update interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in DMA mode. - * @param htim TIM handle - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to peripheral. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); - - /* Enable the TIM Update DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in DMA mode. - * @param htim TIM handle - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions - * @brief Time Output Compare functions - * -@verbatim - ============================================================================== - ##### Time Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Output Compare. - (+) De-initialize the TIM Output Compare. - (+) Start the Time Output Compare. - (+) Stop the Time Output Compare. - (+) Start the Time Output Compare and enable interrupt. - (+) Stop the Time Output Compare and disable interrupt. - (+) Start the Time Output Compare and enable DMA transfer. - (+) Stop the Time Output Compare and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Output Compare according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the Output Compare */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the TIM peripheral - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Output Compare MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize TIM Output Compare MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Output Compare signal generation. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM OC handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions - * @brief Time PWM functions - * -@verbatim - ============================================================================== - ##### Time PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM OPWM. - (+) De-initialize the TIM PWM. - (+) Start the Time PWM. - (+) Stop the Time PWM. - (+) Start the Time PWM and enable interrupt. - (+) Stop the Time PWM and disable interrupt. - (+) Start the Time PWM and enable DMA transfer. - (+) Stop the Time PWM and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM PWM Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the PWM */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the TIM peripheral - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize TIM PWM MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the PWM signal generation. - * @param htim TIM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode. - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim TIM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Output Capture/Compare 3 request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions - * @brief Time Input Capture functions - * -@verbatim - ============================================================================== - ##### Time Input Capture functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Input Capture. - (+) De-initialize the TIM Input Capture. - (+) Start the Time Input Capture. - (+) Stop the Time Input Capture. - (+) Start the Time Input Capture and enable interrupt. - (+) Stop the Time Input Capture and disable interrupt. - (+) Start the Time Input Capture and enable DMA transfer. - (+) Stop the Time Input Capture and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Input Capture Time base according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the input capture */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the TIM peripheral - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM INput Capture MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize TIM Input Capture MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Input Capture measurement. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim TIM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement on in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions - * @brief Time One Pulse functions - * -@verbatim - ============================================================================== - ##### Time One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM One Pulse. - (+) De-initialize the TIM One Pulse. - (+) Start the Time One Pulse. - (+) Stop the Time One Pulse. - (+) Start the Time One Pulse and enable interrupt. - (+) Stop the Time One Pulse and disable interrupt. - (+) Start the Time One Pulse and enable DMA transfer. - (+) Stop the Time One Pulse and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM One Pulse Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() - * @param htim TIM OnePulse handle - * @param OnePulseMode Select the One pulse mode. - * This parameter can be one of the following values: - * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. - * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) -{ - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_OPM_MODE(OnePulseMode)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OnePulse_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the One Pulse Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Reset the OPM Bit */ - htim->Instance->CR1 &= ~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - htim->Instance->CR1 |= OnePulseMode; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the TIM One Pulse - * @param htim TIM One Pulse handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_OnePulse_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize TIM One Pulse MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM One Pulse signal generation. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions - * @brief Time Encoder functions - * -@verbatim - ============================================================================== - ##### Time Encoder functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Encoder. - (+) De-initialize the TIM Encoder. - (+) Start the Time Encoder. - (+) Stop the Time Encoder. - (+) Start the Time Encoder and enable interrupt. - (+) Stop the Time Encoder and disable interrupt. - (+) Start the Time Encoder and enable DMA transfer. - (+) Stop the Time Encoder and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Encoder Interface and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() - * @param htim TIM Encoder Interface handle - * @param sConfig TIM Encoder Interface configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) -{ - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_Encoder_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Reset the SMS bits */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = htim->Instance->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = htim->Instance->CCER; - - /* Set the encoder Mode */ - tmpsmcr |= sConfig->EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); - - /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ - tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); - tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); - tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - htim->Instance->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - htim->Instance->CCER = tmpccer; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - - -/** - * @brief DeInitialize the TIM Encoder interface - * @param htim TIM Encoder handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Encoder_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Encoder Interface MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize TIM Encoder Interface MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Enable the encoder interface channels */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - } - break; - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - } - break; - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - } - break; - } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - } - break; - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - } - break; - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - } - break; - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Enable the encoder interface channels */ - /* Enable the capture compare Interrupts 1 and/or 2 */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - else if(Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 and 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1 The destination Buffer address for IC1. - * @param pData2 The destination Buffer address for IC2. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - } - break; - - case TIM_CHANNEL_ALL: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); - - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - default: - break; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if(Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - else if(Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 and 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ -/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * -@verbatim - ============================================================================== - ##### IRQ handler management ##### - ============================================================================== - [..] - This section provides Timer IRQ handler function. - -@endverbatim - * @{ - */ -/** - * @brief This function handles TIM interrupts requests. - * @param htim TIM handle - * @retval None - */ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) -{ - /* Capture compare 1 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) - { - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - } - /* Capture compare 2 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 3 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 4 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* TIM Update event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); - HAL_TIM_PeriodElapsedCallback(htim); - } - } - /* TIM Break input event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); - HAL_TIMEx_BreakCallback(htim); - } - } - /* TIM Trigger detection event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); - HAL_TIM_TriggerCallback(htim); - } - } - /* TIM commutation event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) - { - if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); - HAL_TIMEx_CommutationCallback(htim); - } - } -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. - (+) Configure External Clock source. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master and the Slave synchronization. - (+) Configure the DMA Burst Mode. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM Output Compare Channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM Output Compare handle - * @param sConfig TIM Output Compare configuration structure - * @param Channel TIM Channels to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef* sConfig, - uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 1 in Output Compare */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 2 in Output Compare */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 3 in Output Compare */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_5: - { - /* Check the parameters */ - assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 5 in Output Compare */ - TIM_OC5_SetConfig(htim->Instance, sConfig); - } - break; - - case TIM_CHANNEL_6: - { - /* Check the parameters */ - assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 6 in Output Compare */ - TIM_OC6_SetConfig(htim->Instance, sConfig); - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture Channels according to the specified - * parameters in the TIM_IC_InitTypeDef. - * @param htim TIM IC handle - * @param sConfig TIM Input Capture configuration structure - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (Channel == TIM_CHANNEL_1) - { - /* TI1 Configuration */ - TIM_TI1_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->ICPrescaler; - } - else if (Channel == TIM_CHANNEL_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); - } - else if (Channel == TIM_CHANNEL_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - TIM_TI3_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC3PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - htim->Instance->CCMR2 |= sConfig->ICPrescaler; - } - else - { - /* TI4 Configuration */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - TIM_TI4_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC4PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM PWM handle - * @param sConfig TIM PWM configuration structure - * @param Channel TIM Channels to be configured - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef* sConfig, - uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the Channel 1 in PWM mode */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the Channel 2 in PWM mode */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; - } - break; - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the Channel 3 in PWM mode */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the Channel 4 in PWM mode */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; - } - break; - - case TIM_CHANNEL_5: - { - /* Check the parameters */ - assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - - /* Configure the Channel 5 in PWM mode */ - TIM_OC5_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel5*/ - htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode; - } - break; - - case TIM_CHANNEL_6: - { - /* Check the parameters */ - assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - - /* Configure the Channel 5 in PWM mode */ - TIM_OC6_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel6 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode << 8; - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse Channels according to the specified - * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim TIM One Pulse handle - * @param sConfig TIM One Pulse configuration structure - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) -{ - TIM_OC_InitTypeDef temp1; - - /* Check the parameters */ - assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); - assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - - if(OutputChannel != InputChannel) - { - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Extract the Ouput compare configuration from sConfig structure */ - temp1.OCMode = sConfig->OCMode; - temp1.Pulse = sConfig->Pulse; - temp1.OCPolarity = sConfig->OCPolarity; - temp1.OCNPolarity = sConfig->OCNPolarity; - temp1.OCIdleState = sConfig->OCIdleState; - temp1.OCNIdleState = sConfig->OCNIdleState; - - switch (OutputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_OC1_SetConfig(htim->Instance, &temp1); - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_OC2_SetConfig(htim->Instance, &temp1); - } - break; - default: - break; - } - - switch (InputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - } - break; - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write - * This parameters can be on of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc TIM DMA Request sources - * This parameters can be on of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t* BurstBuffer, uint32_t BurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((BurstBuffer == 0 ) && (BurstLength > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_COM: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_TRIGGER: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); - } - break; - default: - break; - } - /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM DMA Burst mode - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); - } - break; - case TIM_DMA_CC1: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); - } - break; - case TIM_DMA_CC2: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); - } - break; - case TIM_DMA_CC3: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); - } - break; - case TIM_DMA_CC4: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); - } - break; - case TIM_DMA_COM: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); - } - break; - case TIM_DMA_TRIGGER: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); - } - break; - default: - break; - } - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read - * This parameters can be on of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc TIM DMA Request sources - * This parameters can be on of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((BurstBuffer == 0 ) && (BurstLength > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_CC4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_COM: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - case TIM_DMA_TRIGGER: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); - } - break; - default: - break; - } - - /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the DMA burst reading - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch(BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); - } - break; - case TIM_DMA_CC1: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); - } - break; - case TIM_DMA_CC2: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); - } - break; - case TIM_DMA_CC3: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); - } - break; - case TIM_DMA_CC4: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); - } - break; - case TIM_DMA_COM: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); - } - break; - case TIM_DMA_TRIGGER: - { - HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); - } - break; - default: - break; - } - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Generate a software event - * @param htim TIM handle - * @param EventSource specifies the event source. - * This parameter can be one of the following values: - * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source - * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EVENTSOURCE_COM: Timer COM event source - * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source - * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source - * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_EVENT_SOURCE(EventSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the event sources */ - htim->Instance->EGR = EventSource; - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the OCRef clear feature - * @param htim TIM handle - * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @arg TIM_Channel_5: TIM Channel 5 - * @arg TIM_Channel_6: TIM Channel 6 - * @retval None - */ -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel) -{ - uint32_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - switch (sClearInputConfig->ClearInputSource) - { - case TIM_CLEARINPUTSOURCE_NONE: - { - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Clear the OCREF clear selection bit */ - tmpsmcr &= ~TIM_SMCR_OCCS; - - /* Clear the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set TIMx_SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - - case TIM_CLEARINPUTSOURCE_OCREFCLR: - { - /* Clear the OCREF clear selection bit */ - htim->Instance->SMCR &= ~TIM_SMCR_OCCS; - } - break; - - case TIM_CLEARINPUTSOURCE_ETR: - { - /* Check the parameters */ - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - - /* Set the OCREF clear selection bit */ - htim->Instance->SMCR |= TIM_SMCR_OCCS; - } - break; - - default: - break; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; - } - } - break; - case TIM_CHANNEL_2: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; - } - else - { - /* Disable the OCREF clear feature for Channel 2 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; - } - } - break; - case TIM_CHANNEL_3: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; - } - else - { - /* Disable the OCREF clear feature for Channel 3 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; - } - } - break; - case TIM_CHANNEL_4: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; - } - else - { - /* Disable the OCREF clear feature for Channel 4 */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; - } - } - break; - case TIM_CHANNEL_5: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE; - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE; - } - } - break; - case TIM_CHANNEL_6: - { - if(sClearInputConfig->ClearInputState != RESET) - { - /* Enable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE; - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE; - } - } - break; - default: - break; - } - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the clock source to be used - * @param htim TIM handle - * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that - * contains the clock source information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) -{ - uint32_t tmpsmcr = 0; - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); - - /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - htim->Instance->SMCR = tmpsmcr; - - switch (sClockSourceConfig->ClockSource) - { - case TIM_CLOCKSOURCE_INTERNAL: - { - assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - } - break; - - case TIM_CLOCKSOURCE_ETRMODE1: - { - /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - /* Reset the SMS and TS Bits */ - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - /* Select the External clock mode1 and the ETRF trigger */ - tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - break; - - case TIM_CLOCKSOURCE_ETRMODE2: - { - /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Enable the External clock mode2 */ - htim->Instance->SMCR |= TIM_SMCR_ECE; - } - break; - - case TIM_CLOCKSOURCE_TI1: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - } - break; - - case TIM_CLOCKSOURCE_TI2: - { - /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI2 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI2_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - } - break; - - case TIM_CLOCKSOURCE_TI1ED: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - } - break; - - case TIM_CLOCKSOURCE_ITR0: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); - } - break; - - case TIM_CLOCKSOURCE_ITR1: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); - } - break; - - case TIM_CLOCKSOURCE_ITR2: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); - } - break; - - case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); - } - break; - - default: - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Selects the signal connected to the TI1 input: direct from CH1_input - * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim TIM handle. - * @param TI1_Selection Indicate whether or not channel 1 is connected to the - * output of a XOR gate. - * This parameter can be one of the following values: - * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input - * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 - * pins are connected to the TI1 input (XOR combination) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) -{ - uint32_t tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Reset the TI1 selection */ - tmpcr2 &= ~TIM_CR2_TI1S; - - /* Set the TI1 selection */ - tmpcr2 |= TI1_Selection; - - /* Write to TIMxCR2 */ - htim->Instance->CR2 = tmpcr2; - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); - - /* Disable Trigger Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; - } - -/** - * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) - { - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); - - /* Enable Trigger Interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; - } - -/** - * @brief Read the captured value from Capture Compare unit - * @param htim TIM handle. - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval Captured value - */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpreg = 0; - - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Return the capture 1 value */ - tmpreg = htim->Instance->CCR1; - - break; - } - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Return the capture 2 value */ - tmpreg = htim->Instance->CCR2; - - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Return the capture 3 value */ - tmpreg = htim->Instance->CCR3; - - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Return the capture 4 value */ - tmpreg = htim->Instance->CCR4; - - break; - } - - default: - break; - } - - __HAL_UNLOCK(htim); - return tmpreg; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * -@verbatim - ============================================================================== - ##### TIM Callbacks functions ##### - ============================================================================== - [..] - This section provides TIM callback functions: - (+) Timer Period elapsed callback - (+) Timer Output Compare callback - (+) Timer Input capture callback - (+) Timer Trigger callback - (+) Timer Error callback - -@endverbatim - * @{ - */ - -/** - * @brief Period elapsed callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file - */ - -} -/** - * @brief Output Compare callback in non-blocking mode - * @param htim TIM OC handle - * @retval None - */ -__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file - */ -} -/** - * @brief Input Capture callback in non-blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_IC_CaptureCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_TriggerCallback could be implemented in the user file - */ -} - -/** - * @brief Timer error callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Base handle state. - * @param htim TIM Base handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM OC handle state. - * @param htim TIM Ouput Compare handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM PWM handle state. - * @param htim TIM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Input Capture handle state. - * @param htim TIM IC handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM One Pulse Mode handle state. - * @param htim TIM OPM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode handle state. - * @param htim TIM Encoder handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @} - */ - -/** - * @brief TIM DMA error callback - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMAError(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_ErrorCallback(htim); -} - -/** - * @brief TIM DMA Delay Pulse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - - HAL_TIM_PWM_PulseFinishedCallback(htim); - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} -/** - * @brief TIM DMA Capture complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - - HAL_TIM_IC_CaptureCallback(htim); - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Period Elapse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_PeriodElapsedCallback(htim); -} - -/** - * @brief TIM DMA Trigger callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_TriggerCallback(htim); -} - -/** - * @brief Time Base configuration - * @param TIMx TIM peripheral - * @param Structure TIM Base configuration structure - * @retval None - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) -{ - uint32_t tmpcr1 = 0; - tmpcr1 = TIMx->CR1; - - /* Set TIM Time Base Unit parameters ---------------------------------------*/ - if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - { - /* Select the Counter Mode */ - tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - tmpcr1 |= Structure->CounterMode; - } - - if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - { - /* Set the clock division */ - tmpcr1 &= ~TIM_CR1_CKD; - tmpcr1 |= (uint32_t)Structure->ClockDivision; - } - - /* Set the auto-reload preload */ - tmpcr1 &= ~TIM_CR1_ARPE; - tmpcr1 |= (uint32_t)Structure->AutoReloadPreload; - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = (uint32_t)Structure->Period ; - - /* Set the Prescaler value */ - TIMx->PSC = (uint32_t)Structure->Prescaler; - - if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = Structure->RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediately */ - TIMx->EGR = TIM_EGR_UG; -} - -/** - * @brief Time Ouput Compare 1 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~TIM_CCMR1_OC1M; - tmpccmrx &= ~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= OC_Config->OCPolarity; - - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) - { - /* Check parameters */ - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; - } - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS1; - tmpcr2 &= ~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= OC_Config->OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= OC_Config->OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 2 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR1_OC2M; - tmpccmrx &= ~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4); - - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 4); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; - - } - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS2; - tmpcr2 &= ~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 2); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 3 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC3M; - tmpccmrx &= ~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8); - - if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; - } - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS3; - tmpcr2 &= ~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 4); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Time Ouput Compare 4 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC4M; - tmpccmrx &= ~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12); - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS4; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 6); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Ouput Compare 5 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, - TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the output: Reset the CCxE Bit */ - TIMx->CCER &= ~TIM_CCER_CC5E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR3; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~(TIM_CCMR3_OC5M); - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC5P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 16); - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS5; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 8); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR3 */ - TIMx->CCMR3 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR5 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Ouput Compare 6 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure - * @retval None - */ -static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, - TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; - - /* Disable the output: Reset the CCxE Bit */ - TIMx->CCER &= ~TIM_CCER_CC6E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR3; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~(TIM_CCMR3_OC6M); - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)~TIM_CCER_CC6P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 20); - - if(IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS6; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 10); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR3 */ - TIMx->CCMR3 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR6 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef * sSlaveConfig) -{ - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the Trigger Selection Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source */ - tmpsmcr |= sSlaveConfig->InputTrigger; - - /* Reset the slave mode Bits */ - tmpsmcr &= ~TIM_SMCR_SMS; - /* Set the slave mode */ - tmpsmcr |= sSlaveConfig->SlaveMode; - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Configure the trigger prescaler, filter, and polarity */ - switch (sSlaveConfig->InputTrigger) - { - case TIM_TS_ETRF: - { - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI1F_ED: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = htim->Instance->CCER; - htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); - - /* Write to TIMx CCMR1 and CCER registers */ - htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - - } - break; - - case TIM_TS_TI1FP1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI1 Filter and Polarity */ - TIM_TI1_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI2FP2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI2 Filter and Polarity */ - TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_ITR0: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR1: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR2: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - default: - break; - } -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 - * (on channel2 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) - { - tmpccmr1 &= ~TIM_CCMR1_CC1S; - tmpccmr1 |= TIM_ICSelection; - } - else - { - tmpccmr1 |= TIM_CCMR1_CC1S_0; - } - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI1. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= TIM_ICPolarity; - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 - * (on channel1 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8); - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI2. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC3S; - tmpccmr2 |= TIM_ICSelection; - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - * @retval None - */ -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8); - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx to select the TIM peripheral - * @param InputTriggerSource The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) -{ - uint32_t tmpsmcr = 0; - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source and the slave mode*/ - tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. - * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. - * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. - * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. - * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. - * @param ExtTRGFilter External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) -{ - uint32_t tmpsmcr = 0; - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @param ChannelState: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_TIM_CHANNELS(Channel)); - - tmp = TIM_CCER_CC1E << Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint32_t)(ChannelState << Channel); -} - - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c deleted file mode 100644 index 754c1a711..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c +++ /dev/null @@ -1,2243 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_tim_ex.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer Extended peripheral: - * + Time Hall Sensor Interface Initialization - * + Time Hall Sensor Interface Start - * + Time Complementary signal break and dead time configuration - * + Time Master and Slave synchronization configuration - * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) - * + Time OCRef clear configuration - * + Timer remapping capabilities configuration - @verbatim - ============================================================================== - ##### TIMER Extended features ##### - ============================================================================== - [..] - The Timer Extended features include: - (#) Complementary outputs with programmable dead-time for : - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to - interconnect several timers together. - (#) Break input to put the timer output signals in reset state or in a known state. - (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for - positioning purposes - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending on the selected feature: - (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - initialization function of this driver: - (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutationEvent(): to use the - Timer Hall Sensor Interface and the commutation event with the corresponding - Interrupt and DMA request if needed (Note that One Timer is used to interface - with the Hall sensor Interface and another Timer should be used to use - the commutation event). - - (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() - (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). - - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** -*/ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup TIMEx TIMEx - * @brief TIM Extended HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define BDTR_BKF_SHIFT (16) -#define BDTR_BK2F_SHIFT (20) -#define TIMx_ETRSEL_MASK ((uint32_t)0x0003C000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState); - -/* Private functions ---------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions - * @{ - */ - -/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * -@verbatim - ============================================================================== - ##### Timer Hall Sensor functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure TIM HAL Sensor. - (+) De-initialize TIM HAL Sensor. - (+) Start the Hall Sensor Interface. - (+) Stop the Hall Sensor Interface. - (+) Start the Hall Sensor Interface and enable interrupts. - (+) Stop the Hall Sensor Interface and disable interrupts. - (+) Start the Hall Sensor Interface and enable DMA transfers. - (+) Stop the Hall Sensor Interface and disable DMA transfers. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. - * @param htim TIM Encoder Interface handle - * @param sConfig TIM Hall Sensor configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) -{ - TIM_OC_InitTypeDef OC_Config; - - /* Check the TIM handle allocation */ - if(htim == NULL) - { - return HAL_ERROR; - } - - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIMEx_HallSensor_MspInit(htim); - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ - TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->IC1Prescaler; - - /* Enable the Hall sensor interface (XOR function of the three inputs) */ - htim->Instance->CR2 |= TIM_CR2_TI1S; - - /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1F_ED; - - /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; - - /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ - OC_Config.OCFastMode = TIM_OCFAST_DISABLE; - OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; - OC_Config.OCMode = TIM_OCMODE_PWM2; - OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; - OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; - OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; - OC_Config.Pulse = sConfig->Commutation_Delay; - - TIM_OC2_SetConfig(htim->Instance, &OC_Config); - - /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 - register to 101 */ - htim->Instance->CR2 &= ~TIM_CR2_MMS; - htim->Instance->CR2 |= TIM_TRGO_OC2REF; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the TIM Hall Sensor interface - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIMEx_HallSensor_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Hall Sensor MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize TIM Hall Sensor MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Hall Sensor Interface. - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall sensor Interface. - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM Hall Sensor handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Enable the capture compare Interrupts 1 event */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts event */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM Hall Sensor handle - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Set the DMA Input Capture 1 Callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel for Capture 1*/ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - - /* Enable the capture compare 1 Interrupt */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - - /* Disable the capture compare Interrupts 1 event */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * -@verbatim - ============================================================================== - ##### Timer Complementary Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary Output Compare/PWM. - (+) Stop the Complementary Output Compare/PWM. - (+) Start the Complementary Output Compare/PWM and enable interrupts. - (+) Stop the Complementary Output Compare/PWM and disable interrupts. - (+) Start the Complementary Output Compare/PWM and enable DMA transfers. - (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM OC handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: -{ - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * -@verbatim - ============================================================================== - ##### Timer Complementary PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary PWM. - (+) Stop the Complementary PWM. - (+) Start the Complementary PWM and enable interrupts. - (+) Stop the Complementary PWM and disable interrupts. - (+) Start the Complementary PWM and enable DMA transfers. - (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - } - break; - - default: - break; - } - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode on the - * complementary output - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if(((uint32_t)pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode on the complementary - * output - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * -@verbatim - ============================================================================== - ##### Timer Complementary One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM One Pulse signal generation on the complementary - * output. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) - { - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Enable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation on the complementary - * output. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - /* Enable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - - /* Enable the Main Ouput */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the complementary One Pulse output */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - - /* Disable the Main Ouput */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure the commutation event in case of use of the Hall sensor interface. - (+) Configure Output channels for OC and PWM mode. - - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master synchronization. - (+) Configure timer remapping capabilities. - (+) Enable or disable channel grouping - -@endverbatim - * @{ - */ - -/** - * @brief Configure the TIM commutation event sequence. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with interrupt. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Enable the Commutation Interrupt Request */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with DMA. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Enable the Commutation DMA Request */ - /* Set the DMA Commutation Callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; - - /* Enable the Commutation DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in master mode. - * @param htim TIM handle. - * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that - * contains the selected trigger output (TRGO) and the Master/Slave - * mode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef * sMasterConfig) -{ - uint32_t tmpcr2; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); - assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ - if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); - - /* Clear the MMS2 bits */ - tmpcr2 &= ~TIM_CR2_MMS2; - /* Select the TRGO2 source*/ - tmpcr2 |= sMasterConfig->MasterOutputTrigger2; - } - - /* Reset the MMS Bits */ - tmpcr2 &= ~TIM_CR2_MMS; - /* Select the TRGO source */ - tmpcr2 |= sMasterConfig->MasterOutputTrigger; - - /* Reset the MSM Bit */ - tmpsmcr &= ~TIM_SMCR_MSM; - /* Set master mode */ - tmpsmcr |= sMasterConfig->MasterSlaveMode; - - /* Update TIMx CR2 */ - htim->Instance->CR2 = tmpcr2; - - /* Update TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param htim TIM handle - * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig) -{ - uint32_t tmpbdtr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); - assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); - assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); - assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); - assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); - assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); - assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - - /* Set the BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); - MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); - MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT)); - - if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); - assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); - assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); - - /* Set the BREAK2 input related BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT)); - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); - } - - /* Set TIMx_BDTR */ - htim->Instance->BDTR = tmpbdtr; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the break input source. - * @param htim TIM handle. - * @param BreakInput Break input to configure - * This parameter can be one of the following values: - * @arg TIM_BREAKINPUT_BRK: Timer break input - * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input - * @param sBreakInputConfig Break input source configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, - uint32_t BreakInput, - TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) - -{ - uint32_t tmporx = 0; - uint32_t bkin_enable_mask = 0; - uint32_t bkin_polarity_mask = 0; - uint32_t bkin_enable_bitpos = 0; - uint32_t bkin_polarity_bitpos = 0; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_BREAKINPUT(BreakInput)); - assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); - assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) - { - assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); - } -#else - assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - - /* Check input state */ - __HAL_LOCK(htim); - - switch(sBreakInputConfig->Source) - { - case TIM_BREAKINPUTSOURCE_BKIN: - { - bkin_enable_mask = TIM1_OR2_BKINE; - bkin_enable_bitpos = 0; - bkin_polarity_mask = TIM1_OR2_BKINP; - bkin_polarity_bitpos = 9; - } - break; - case TIM_BREAKINPUTSOURCE_COMP1: - { - bkin_enable_mask = TIM1_OR2_BKCMP1E; - bkin_enable_bitpos = 1; - bkin_polarity_mask = TIM1_OR2_BKCMP1P; - bkin_polarity_bitpos = 10; - } - break; - case TIM_BREAKINPUTSOURCE_COMP2: - { - bkin_enable_mask = TIM1_OR2_BKCMP2E; - bkin_enable_bitpos = 2; - bkin_polarity_mask = TIM1_OR2_BKCMP2P; - bkin_polarity_bitpos = 11; - } - break; - -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - case TIM_BREAKINPUTSOURCE_DFSDM1: - { - bkin_enable_mask = TIM1_OR2_BKDF1BK0E; - bkin_enable_bitpos = 8; - } - break; -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - - default: - break; - } - - switch(BreakInput) - { - case TIM_BREAKINPUT_BRK: - { - /* Get the TIMx_OR2 register value */ - tmporx = htim->Instance->OR2; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set the break input polarity */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } - - /* Set TIMx_OR2 */ - htim->Instance->OR2 = tmporx; - } - break; - case TIM_BREAKINPUT_BRK2: - { - /* Get the TIMx_OR3 register value */ - tmporx = htim->Instance->OR3; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set the break input polarity */ -#if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \ - defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ - defined (STM32L496xx) || defined (STM32L4A6xx) || \ - defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) - if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) -#endif /* STM32L451xx || STM32L452xx || STM32L462xx */ - /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } - - /* Set TIMx_OR3 */ - htim->Instance->OR3 = tmporx; - } - break; - default: - break; - } - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIMx Remapping input capabilities. - * @param htim TIM handle. - * @param Remap: specifies the TIM remapping source. - * - @if STM32L486xx - * For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4): - * - * field1 can have the following values: - * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog) - * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 - * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 - * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 - * - * field2 can have the following values: - * @arg TIM_TIM1_ETR_ADC3_NONE: TIM1_ETR is not connected to any ADC3 AWD (analog watchdog) - * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 - * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 - * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3 - * - * field3 can have the following values: - * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO - * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output - * - * field4 can have the following values: - * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output - * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output - * @note When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant - @endif - @if STM32L443xx - * For TIM1, the parameter is a combination of 3 fields (field1 | field2 | field3): - * - * field1 can have the following values: - * @arg TIM_TIM1_ETR_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog) - * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 - * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 - * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 - * - * field2 can have the following values: - * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO - * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output - * - * field3 can have the following values: - * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output - * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output - * - * @note When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant - * - @endif - @if STM32L486xx - * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3): - * - * field1 can have the following values: - * @arg TIM_TIM2_ITR1_TIM8_TRGO: TIM2_ITR1 is connected to TIM8_TRGO - * @arg TIM_TIM2_ITR1_OTG_FS_SOF: TIM2_ITR1 is connected to OTG_FS SOF - * - * field2 can have the following values: - * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO - * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE - * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output - * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output - * - * field3 can have the following values: - * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO - * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output - * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output - * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output - @endif - @if STM32L443xx - * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3): - * - * field1 can have the following values: - * @arg TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1 - * @arg TIM_TIM2_ITR1_USB_SOF: TIM2_ITR1 is connected to USB SOF - * - * field2 can have the following values: - * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO - * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE - * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output - * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output - * - * field3 can have the following values: - * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO - * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output - * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output - * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output - * - @endif - @if STM32L486xx - * For TIM3, the parameter is a combination 2 fields(field1 | field2): - * - * field1 can have the following values: - * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO - * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output - * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output - * @arg TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output - * - * field2 can have the following values: - * @arg TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO - * @arg TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output - * - @endif - @if STM32L486xx - * For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3): - * - * field1 can have the following values: - * @arg TIM_TIM8_ETR_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD (analog watchdog) - * @arg TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1 - * @arg TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2 - * @arg TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3 - * - * field2 can have the following values: - * @arg TIM_TIM8_ETR_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD (analog watchdog) - * @arg TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1 - * @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2 - * @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3 - * - * field3 can have the following values: - * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO - * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output - * - * field4 can have the following values: - * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output - * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output - * @note When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant - * - @endif - * For TIM15, the parameter is a combination of 3 fields (field1 | field2): - * - * field1 can have the following values: - * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO - * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE - * - * field2 can have the following values: - * @arg TIM_TIM15_ENCODERMODE_NONE: No redirection - * @arg TIM_TIM15_ENCODERMODE_TIM2: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively - * @arg TIM_TIM15_ENCODERMODE_TIM3: TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively - * @arg TIM_TIM15_ENCODERMODE_TIM4: TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively - * - @if STM32L486xx - * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO - * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI - * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE - * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt - * - @endif - @if STM32L443xx - * For TIM16, the parameter can have the following values: - * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO - * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI - * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE - * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt - * @arg TIM_TIM16_TI1_MSI: TIM16 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock) - * @arg TIM_TIM16_TI1_HSE_32: TIM16 TI1 is connected to HSE div 32 (note that HSE div 32 must be selected as RTC clock source) - * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO - * - @endif - @if STM32L486xx - * For TIM17, the parameter can have the following values: - * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO - * @arg TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock) - * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32 - * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO - @endif - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) -{ - uint32_t tmpor1 = 0; - uint32_t tmpor2 = 0; - - __HAL_LOCK(htim); - - /* Check parameters */ - assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); - assert_param(IS_TIM_REMAP(Remap)); - - /* Set ETR_SEL bit field (if required) */ - if (IS_TIM_ETRSEL_INSTANCE(htim->Instance)) - { - tmpor2 = htim->Instance->OR2; - tmpor2 &= ~TIMx_ETRSEL_MASK; - tmpor2 |= (Remap & TIMx_ETRSEL_MASK); - - /* Set TIMx_OR2 */ - htim->Instance->OR2 = tmpor2; - } - - /* Set other remapping capabilities */ - tmpor1 = Remap; - tmpor1 &= ~TIMx_ETRSEL_MASK; - - /* Set TIMx_OR1 */ - htim->Instance->OR1 = tmpor1; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Group channel 5 and channel 1, 2 or 3 - * @param htim TIM handle. - * @param Channels specifies the reference signal(s) the OC5REF is combined with. - * This parameter can be any combination of the following values: - * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC - * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF - * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF - * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) -{ - /* Check parameters */ - assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_GROUPCH5(Channels)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Clear GC5Cx bit fields */ - htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1); - - /* Set GC5Cx bit fields */ - htim->Instance->CCR5 |= Channels; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions - * @brief Extended Callbacks functions - * -@verbatim - ============================================================================== - ##### Extended Callbacks functions ##### - ============================================================================== - [..] - This section provides Extended TIM callback functions: - (+) Timer Commutation callback - (+) Timer Break callback - -@endverbatim - * @{ - */ - -/** - * @brief Hall commutation changed callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_CommutationCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Break detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_BreakCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions - * @brief Extended Peripheral State functions - * -@verbatim - ============================================================================== - ##### Extended Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Hall Sensor interface handle state. - * @param htim TIM Hall Sensor handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @} - */ - -/** - * @brief TIM DMA Commutation callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIMEx_CommutationCallback(htim); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param ChannelNState specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. - * @retval None - */ -static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) -{ - uint32_t tmp = 0; - - tmp = TIM_CCER_CC1NE << Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << Channel); -} - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c deleted file mode 100644 index 8aa955c85..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c +++ /dev/null @@ -1,3448 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_uart.c - * @author MCD Application Team - * @brief UART HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The UART HAL driver can be used as follows: - - (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). - (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: - (++) Enable the USARTx interface clock. - (++) UART pins configuration: - (+++) Enable the clock for the UART GPIOs. - (+++) Configure these UART pins as alternate function pull-up. - (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() - and HAL_UART_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (++) UART interrupts handling: - -@@- The specific UART interrupts (Transmission complete interrupt, - RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) - are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() - inside the transmit and receive processes. - (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() - and HAL_UART_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware - flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. - - (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) - in the huart handle AdvancedInit structure. - - (#) For the UART asynchronous mode, initialize the UART registers by calling - the HAL_UART_Init() API. - - (#) For the UART Half duplex mode, initialize the UART registers by calling - the HAL_HalfDuplex_Init() API. - - (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers - by calling the HAL_LIN_Init() API. - - (#) For the UART Multiprocessor mode, initialize the UART registers - by calling the HAL_MultiProcessor_Init() API. - - (#) For the UART RS485 Driver Enabled mode, initialize the UART registers - by calling the HAL_RS485Ex_Init() API. - - [..] - (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), - also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by - calling the customized HAL_UART_MspInit() API. - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup UART UART - * @brief HAL UART module driver - * @{ - */ - -#ifdef HAL_UART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup UART_Private_Constants UART Private Constants - * @{ - */ -#if defined(USART_CR1_FIFOEN) -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ - USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ -#else -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ -#endif - -#if defined(USART_CR1_FIFOEN) -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \ - USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ -#else -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ -#endif - -#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ -#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ - -#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ -#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup UART_Private_Functions - * @{ - */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart); -static void UART_EndRxTransfer(UART_HandleTypeDef *huart); -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAError(DMA_HandleTypeDef *hdma); -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); -static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); -#if defined(USART_CR1_FIFOEN) -static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); -static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); -#endif -static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); -static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); -static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); -#if defined(USART_CR1_FIFOEN) -static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); -static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); -#endif - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in asynchronous mode. - (+) For the asynchronous mode the parameters below can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - (++) Hardware flow control - (++) Receiver/transmitter modes - (++) Over Sampling Method - (++) One-Bit Sampling Method - (+) For the asynchronous mode, the following advanced features can be configured as well: - (++) TX and/or RX pin level inversion - (++) data logical level inversion - (++) RX and TX pins swap - (++) RX overrun detection disabling - (++) DMA disabling on RX error - (++) MSB first on communication line - (++) auto Baud rate detection - [..] - The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API - follow respectively the UART asynchronous, UART Half duplex, UART LIN mode - and UART multiprocessor mode configuration procedures (details for the procedures - are available in reference manual). - -@endverbatim - - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible UART formats are listed in the - following table. - - Table 1. UART frame format. - +-----------------------------------------------------------------------+ - | M1 bit | M0 bit | PCE bit | UART frame | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 0 | | SB | 8 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 0 | | SB | 9 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 0 | | SB | 7 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - +-----------------------------------------------------------------------+ - - * @{ - */ - -/** - * @brief Initialize the UART mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) - { - /* Check the parameters */ - assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); - } - else - { - /* Check the parameters */ - assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); - } - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In asynchronous mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Initialize the half-duplex mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check UART instance */ - assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In half-duplex mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Initialize the LIN mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart UART handle. - * @param BreakDetectLength Specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection - * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check the LIN UART instance */ - assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - /* Check the Break detection length parameter */ - assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - - /* LIN mode limited to 16-bit oversampling only */ - if(huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - return HAL_ERROR; - } - /* LIN mode limited to 8-bit data length */ - if(huart->Init.WordLength != UART_WORDLENGTH_8B) - { - return HAL_ERROR; - } - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In LIN mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); - - /* Set the USART LIN Break detection length. */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Initialize the multiprocessor mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart UART handle. - * @param Address UART node address (4-, 6-, 7- or 8-bit long). - * @param WakeUpMethod Specifies the UART wakeup method. - * This parameter can be one of the following values: - * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection - * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark - * @note If the user resorts to idle line detection wake up, the Address parameter - * is useless and ignored by the initialization function. - * @note If the user resorts to address mark wake up, the address length detection - * is configured by default to 4 bits only. For the UART to be able to - * manage 6-, 7- or 8-bit long addresses detection, the API - * HAL_MultiProcessorEx_AddressLength_Set() must be called after - * HAL_MultiProcessor_Init(). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check the wake up method parameter */ - assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In multiprocessor mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) - { - /* If address mark wake up method is chosen, set the USART address node */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); - } - - /* Set the wake up method by setting the WAKE bit in the CR1 register */ - MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief DeInitialize the UART peripheral. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - huart->Instance->CR1 = 0x0U; - huart->Instance->CR2 = 0x0U; - huart->Instance->CR3 = 0x0U; - - /* DeInit the low level hardware */ - HAL_UART_MspDeInit(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_RESET; - huart->RxState = HAL_UART_STATE_RESET; - - /* Process Unlock */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Initialize the UART MSP. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_MspInit can be implemented in the user file - */ -} - -/** - * @brief DeInitialize the UART MSP. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_MspDeInit can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group2 IO operation functions - * @brief UART Transmit/Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the UART asynchronous - and Half duplex data transfers. - - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected - - (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() - - (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() - - (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() - - (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() - - (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() - - (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. - Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - - -@- In the Half duplex communication, it is forbidden to run the transmit - and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. - -@endverbatim - * @{ - */ - -/** - * @brief Send an amount of data in blocking mode. - * @note When FIFO mode is enabled, writing a data in the TDR register adds one - * data to the TXFIFO. Write operations to the TDR register are performed - * when TXFNF flag is set. From hardware perspective, TXFNF flag and - * TXE are mapped on the same bit-field. - * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp; - uint32_t tickstart = 0U; - - /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - while(huart->TxXferCount > 0U) - { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - tmp = (uint16_t*) pData; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); - pData += 2U; - } - else - { - huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU); - } - huart->TxXferCount--; - } - - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO - * is not empty. Read operations from the RDR register are performed when - * RXFNE flag is set. From hardware perspective, RXFNE flag and - * RXNE are mapped on the same bit-field. - * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t* tmp; - uint16_t uhMask; - uint32_t tickstart = 0; - - /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - uhMask = huart->Mask; - - /* as long as data have to be received */ - while(huart->RxXferCount > 0U) - { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - tmp = (uint16_t*) pData ; - *tmp = (uint16_t)(huart->Instance->RDR & uhMask); - pData +=2U; - } - else - { - *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); - } - huart->RxXferCount--; - } - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in interrupt mode. - * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - huart->TxISR = NULL; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - -#if defined(USART_CR1_FIFOEN) - /* Configure Tx interrupt processing */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - /* Set the Tx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->TxISR = UART_TxISR_16BIT_FIFOEN; - } - else - { - huart->TxISR = UART_TxISR_8BIT_FIFOEN; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the TX FIFO threshold interrupt */ - SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - } - else -#endif - { - /* Set the Tx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->TxISR = UART_TxISR_16BIT; - } - else - { - huart->TxISR = UART_TxISR_8BIT; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the Transmit Data Register Empty interrupt */ -#if defined(USART_CR1_FIFOEN) - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); -#else - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); -#endif - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in interrupt mode. - * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - huart->RxXferCount = Size; - huart->RxISR = NULL; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - -#if defined(USART_CR1_FIFOEN) - /* Configure Rx interrupt processing*/ - if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) - { - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->RxISR = UART_RxISR_16BIT_FIFOEN; - } - else - { - huart->RxISR = UART_RxISR_8BIT_FIFOEN; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - } - else -#endif - { - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->RxISR = UART_RxISR_16BIT; - } - else - { - huart->RxISR = UART_RxISR_8BIT; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ -#if defined(USART_CR1_FIFOEN) - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); -#else - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); -#endif - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in DMA mode. - * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if(huart->gState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Set the UART DMA transfer complete callback */ - huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmatx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmatx->XferAbortCallback = NULL; - - /* Enable the UART transmit DMA channel */ - HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size); - - /* Clear the TC flag in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in DMA mode. - * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if(huart->RxState == HAL_UART_STATE_READY) - { - if((pData == NULL ) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Set the UART DMA transfer complete callback */ - huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmarx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pause the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) - { - /* Disable the UART DMA Tx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) - { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Rx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Resume the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - if(huart->gState == HAL_UART_STATE_BUSY_TX) - { - /* Enable the UART DMA Tx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - if(huart->RxState == HAL_UART_STATE_BUSY_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the UART DMA Rx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Stop the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / - HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ - - /* Stop UART DMA Tx request if ongoing */ - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel */ - if(huart->hdmatx != NULL) - { - HAL_DMA_Abort(huart->hdmatx); - } - - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if(huart->hdmarx != NULL) - { - HAL_DMA_Abort(huart->hdmarx); - } - - UART_EndRxTransfer(huart); - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = NULL; - - HAL_DMA_Abort(huart->hdmatx); - } - } - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = NULL; - - HAL_DMA_Abort(huart->hdmarx); - } - } - - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - -#if defined(USART_CR1_FIFOEN) - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } -#endif - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* Reset Handle ErrorCode to No Error */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = NULL; - - HAL_DMA_Abort(huart->hdmatx); - } - } - - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - -#if defined(USART_CR1_FIFOEN) - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } -#endif - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if(huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = NULL; - - HAL_DMA_Abort(huart->hdmarx); - } - } - - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) -{ - uint32_t abortcplt = 1U; - - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ - /* DMA Tx Handle is valid */ - if(huart->hdmatx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. - Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; - } - else - { - huart->hdmatx->XferAbortCallback = NULL; - } - } - /* DMA Rx Handle is valid */ - if(huart->hdmarx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. - Otherwise, set it to NULL */ - if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; - } - else - { - huart->hdmarx->XferAbortCallback = NULL; - } - } - - /* Disable the UART DMA Tx request if enabled */ - if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable DMA Tx at UART level */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmatx != NULL) - { - /* UART Tx DMA Abort callback has already been initialised : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) - { - huart->hdmatx->XferAbortCallback = NULL; - } - else - { - abortcplt = 0U; - } - } - } - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmarx != NULL) - { - /* UART Rx DMA Abort callback has already been initialised : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - huart->hdmarx->XferAbortCallback = NULL; - abortcplt = 1U; - } - else - { - abortcplt = 0U; - } - } - } - - /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1U) - { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Clear ISR function pointers */ - huart->RxISR = NULL; - huart->TxISR = NULL; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - -#if defined(USART_CR1_FIFOEN) - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } -#endif - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; - - /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) - { - /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ - huart->hdmatx->XferAbortCallback(huart->hdmatx); - } - } - else - { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - - /* Clear TxISR function pointers */ - huart->TxISR = NULL; - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ - HAL_UART_AbortTransmitCpltCallback(huart); - } - } - else - { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - - /* Clear TxISR function pointers */ - huart->TxISR = NULL; - -#if defined(USART_CR1_FIFOEN) - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } -#endif - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ - HAL_UART_AbortTransmitCpltCallback(huart); - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if(huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; - - /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear RxISR function pointer */ - huart->pRxBuffPtr = NULL; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ - HAL_UART_AbortReceiveCpltCallback(huart); - } - } - else - { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear RxISR function pointer */ - huart->pRxBuffPtr = NULL; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ - HAL_UART_AbortReceiveCpltCallback(huart); - } - - return HAL_OK; -} - -/** - * @brief Handle UART interrupt request. - * @param huart UART handle. - * @retval None - */ -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) -{ - uint32_t isrflags = READ_REG(huart->Instance->ISR); - uint32_t cr1its = READ_REG(huart->Instance->CR1); - uint32_t cr3its = READ_REG(huart->Instance->CR3); - uint32_t errorflags; - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); - if (errorflags == RESET) - { - /* UART in mode Receiver ---------------------------------------------------*/ -#if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) -#else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) -#endif - { - if (huart->RxISR != NULL) {huart->RxISR(huart);} - return; - } - } - - /* If some errors occur */ -#if defined(USART_CR1_FIFOEN) - if( (errorflags != RESET) - && ( (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != RESET))) ) -#else - if( (errorflags != RESET) - && ( ((cr3its & USART_CR3_EIE) != RESET) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) ) -#endif - { - /* UART parity error interrupt occurred -------------------------------------*/ - if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); - - huart->ErrorCode |= HAL_UART_ERROR_PE; - } - - /* UART frame error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); - - huart->ErrorCode |= HAL_UART_ERROR_FE; - } - - /* UART noise error interrupt occurred --------------------------------------*/ - if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); - - huart->ErrorCode |= HAL_UART_ERROR_NE; - } - - /* UART Over-Run interrupt occurred -----------------------------------------*/ -#if defined(USART_CR1_FIFOEN) - if( ((isrflags & USART_ISR_ORE) != RESET) - &&( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) || - ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != RESET))) -#else - if( ((isrflags & USART_ISR_ORE) != RESET) - &&( ((cr1its & USART_CR1_RXNEIE) != RESET) || - ((cr3its & USART_CR3_EIE) != RESET))) -#endif - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - - huart->ErrorCode |= HAL_UART_ERROR_ORE; - } - - /* Call UART Error Call back function if need be --------------------------*/ - if(huart->ErrorCode != HAL_UART_ERROR_NONE) - { - /* UART in mode Receiver ---------------------------------------------------*/ -#if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_RXNE_RXFNE) != RESET) - && ( ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != RESET) - || ((cr3its & USART_CR3_RXFTIE) != RESET)) ) -#else - if(((isrflags & USART_ISR_RXNE) != RESET) - && ((cr1its & USART_CR1_RXNEIE) != RESET)) -#endif - { - if (huart->RxISR != NULL) {huart->RxISR(huart);} - } - - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || - (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))) - { - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ - UART_EndRxTransfer(huart); - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if(huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - - /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Call user error callback */ - HAL_UART_ErrorCallback(huart); - } - } - else - { - /* Call user error callback */ - HAL_UART_ErrorCallback(huart); - } - } - else - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ - HAL_UART_ErrorCallback(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; - } - } - return; - - } /* End if some error occurs */ - - /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ - if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); - /* Set the UART state ready to be able to start again the process */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - HAL_UARTEx_WakeupCallback(huart); - return; - } - - /* UART in mode Transmitter ------------------------------------------------*/ -#if defined(USART_CR1_FIFOEN) - if(((isrflags & USART_ISR_TXE_TXFNF) != RESET) - && ( ((cr1its & USART_CR1_TXEIE_TXFNFIE) != RESET) - || ((cr3its & USART_CR3_TXFTIE) != RESET)) ) -#else - if(((isrflags & USART_ISR_TXE) != RESET) - && ((cr1its & USART_CR1_TXEIE) != RESET)) -#endif - { - if (huart->TxISR != NULL) {huart->TxISR(huart);} - return; - } - - /* UART in mode Transmitter (transmission end) -----------------------------*/ - if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) - { - UART_EndTransmit_IT(huart); - return; - } - -#if defined(USART_CR1_FIFOEN) - /* UART TX Fifo Empty occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_TXFE) != RESET) && ((cr1its & USART_CR1_TXFEIE) != RESET)) - { - HAL_UARTEx_TxFifoEmptyCallback(huart); - return; - } - - /* UART RX Fifo Full occurred ----------------------------------------------*/ - if(((isrflags & USART_ISR_RXFF) != RESET) && ((cr1its & USART_CR1_RXFFIE) != RESET)) - { - HAL_UARTEx_RxFifoFullCallback(huart); - return; - } -#endif -} - -/** - * @brief Tx Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_TxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Tx Half Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_TxHalfCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_RxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Half Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_RxHalfCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART error callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_ErrorCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Receive Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions - * @brief UART control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the UART. - (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode - (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode - (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode - (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode - (+) UART_SetConfig() API configures the UART peripheral - (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features - (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization - (+) UART_Wakeup_AddressConfig() API configures the wake-up from stop mode parameters - (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter - (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver - (+) HAL_LIN_SendBreak() API transmits the break characters -@endverbatim - * @{ - */ - -/** - * @brief Enable UART in mute mode (does not mean UART enters mute mode; - * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Enable USART mute mode by setting the MME bit in the CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_MME); - - huart->gState = HAL_UART_STATE_READY; - - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Disable UART mute mode (does not mean the UART actually exits mute mode - * as it may not have been in mute mode at this very moment). - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable USART mute mode by clearing the MME bit in the CR1 register */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); - - huart->gState = HAL_UART_STATE_READY; - - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Enter UART mute mode (means UART actually enters mute mode). - * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. - * @param huart UART handle. - * @retval None - */ -void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) -{ - __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); -} - -/** - * @brief Enable the UART transmitter and disable the UART receiver. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_TE); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enable the UART receiver and disable the UART transmitter. - * @param huart UART handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_RE); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - - -/** - * @brief Transmit break characters. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Send break characters */ - SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief UART Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Error functions ##### - ============================================================================== - [..] - This subsection provides functions allowing to : - (+) Return the UART handle state. - (+) Return the UART handle error code - -@endverbatim - * @{ - */ - -/** - * @brief Return the UART handle state. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. - * @retval HAL state - */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) -{ - uint32_t temp1= 0x00U, temp2 = 0x00U; - temp1 = huart->gState; - temp2 = huart->RxState; - - return (HAL_UART_StateTypeDef)(temp1 | temp2); -} - -/** -* @brief Return the UART handle error code. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. -* @retval UART Error Code -*/ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) -{ - return huart->ErrorCode; -} -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup UART_Private_Functions UART Private Functions - * @{ - */ - -/** - * @brief Configure the UART peripheral. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg = 0x00000000U; - UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED; - uint16_t brrtemp = 0x0000U; - uint32_t usartdiv = 0x00000000U; - HAL_StatusTypeDef ret = HAL_OK; - uint32_t lpuart_ker_ck_pres = 0x00000000U; - - /* Check the parameters */ - assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); - if(UART_INSTANCE_LOWPOWER(huart)) - { - assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); - } - else - { - assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); - assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); - } - - assert_param(IS_UART_PARITY(huart->Init.Parity)); - assert_param(IS_UART_MODE(huart->Init.Mode)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); - assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); -#if defined(USART_PRESC_PRESCALER) - assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); -#endif - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure - * the UART Word Length, Parity, Mode and oversampling: - * set the M bits according to huart->Init.WordLength value - * set PCE and PS bits according to huart->Init.Parity value - * set TE and RE bits according to huart->Init.Mode value - * set OVER8 bit according to huart->Init.OverSampling value */ - tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - - /*-------------------------- USART CR2 Configuration -----------------------*/ - /* Configure the UART Stop Bits: Set STOP[13:12] bits according - * to huart->Init.StopBits value */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure - * - UART HardWare Flow Control: set CTSE and RTSE bits according - * to huart->Init.HwFlowCtl value - * - one-bit sampling method versus three samples' majority rule according - * to huart->Init.OneBitSampling (not applicable to LPUART) - * - set TXFTCFG bit according to huart->Init.TxFifoThreshold value - * - set RXFTCFG bit according to huart->Init.RxFifoThreshold value */ - tmpreg = (uint32_t)huart->Init.HwFlowCtl; - - if (!(UART_INSTANCE_LOWPOWER(huart))) - { - tmpreg |= huart->Init.OneBitSampling; - } - MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - -#if defined(USART_PRESC_PRESCALER) - /*-------------------------- USART PRESC Configuration -----------------------*/ - /* Configure - * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ - MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); -#endif - - /*-------------------------- USART BRR Configuration -----------------------*/ - UART_GETCLOCKSOURCE(huart, clocksource); - - /* Check LPUART instance */ - if(UART_INSTANCE_LOWPOWER(huart)) - { - /* Retrieve frequency clock */ - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: -#if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq()/UARTPrescTable[huart->Init.ClockPrescaler]); -#else - lpuart_ker_ck_pres = HAL_RCC_GetPCLK1Freq(); -#endif - break; - case UART_CLOCKSOURCE_HSI: -#if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE/UARTPrescTable[huart->Init.ClockPrescaler]); -#else - lpuart_ker_ck_pres = (uint32_t)HSI_VALUE; -#endif - break; - case UART_CLOCKSOURCE_SYSCLK: -#if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq()/UARTPrescTable[huart->Init.ClockPrescaler]); -#else - lpuart_ker_ck_pres = HAL_RCC_GetSysClockFreq(); -#endif - break; - case UART_CLOCKSOURCE_LSE: -#if defined(USART_PRESC_PRESCALER) - lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE/UARTPrescTable[huart->Init.ClockPrescaler]); -#else - lpuart_ker_ck_pres = (uint32_t)LSE_VALUE; -#endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; - } - - /* if proper clock source reported */ - if (lpuart_ker_ck_pres != 0U) - { - /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ - if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || - (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) - { - ret = HAL_ERROR; - } - else - { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_HSI: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_SYSCLK: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_LSE: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; - } - - /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */ - if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) - { - huart->Instance->BRR = usartdiv; - } - else - { - ret = HAL_ERROR; - } - } /* if ( (tmpreg < (3 * huart->Init.BaudRate) ) || (tmpreg > (4096 * huart->Init.BaudRate) )) */ - } /* if (tmpreg != 0) */ - } - /* Check UART Over Sampling to set Baud Rate Register */ - else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_PCLK2: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_HSI: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_SYSCLK: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_LSE: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; - } - - /* USARTDIV must be greater than or equal to 0d16 */ - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - { - brrtemp = usartdiv & 0xFFF0U; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - huart->Instance->BRR = brrtemp; - } - else - { - ret = HAL_ERROR; - } - } - else - { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_PCLK2: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_HSI: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_SYSCLK: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_LSE: -#if defined(USART_PRESC_PRESCALER) - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); -#else - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); -#endif - break; - case UART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; - } - - /* USARTDIV must be greater than or equal to 0d16 */ - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - { - huart->Instance->BRR = usartdiv; - } - else - { - ret = HAL_ERROR; - } - } - -#if defined(USART_CR1_FIFOEN) - /* Initialize the number of data to process during RX/TX ISR execution */ - huart->NbTxDataToProcess = 1; - huart->NbRxDataToProcess = 1; -#endif - - /* Clear ISR function pointers */ - huart->RxISR = NULL; - huart->TxISR = NULL; - - return ret; -} - -/** - * @brief Configure the UART peripheral advanced features. - * @param huart UART handle. - * @retval None - */ -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) -{ - /* Check whether the set of advanced features to configure is properly set */ - assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); - - /* if required, configure TX pin active level inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - } - - /* if required, configure RX pin active level inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - } - - /* if required, configure data inversion */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - } - - /* if required, configure RX/TX pins swap */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - } - - /* if required, configure RX overrun detection disabling */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - { - assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); - MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - } - - /* if required, configure DMA disabling on reception error */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - { - assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); - MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - } - - /* if required, configure auto Baud rate detection scheme */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - { - assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); - assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - /* set auto Baudrate detection parameters if detection is enabled */ - if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - { - assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - } - } - - /* if required, configure MSB first on communication line */ - if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - { - assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - } -} - -/** - * @brief Check the UART Idle State. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) -{ - uint32_t tickstart = 0U; - - /* Initialize the UART ErrorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - /* Check if the Transmitter is enabled */ - if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } - /* Check if the Receiver is enabled */ - if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } - - /* Initialize the UART State */ - huart->gState= HAL_UART_STATE_READY; - huart->RxState= HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Handle UART Communication Timeout. - * @param huart UART handle. - * @param Flag Specifies the UART flag to check - * @param Status Flag status (SET or RESET) - * @param Tickstart Tick start value - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is set */ - while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); -#endif - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - - -/** - * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -#endif - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; -} - - -/** - * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndRxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Reset RxIsr function pointer */ - huart->RxISR = NULL; -} - - -/** - * @brief DMA UART transmit process complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - - /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) - { - huart->TxXferCount = 0U; - - /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - /* DMA Circular mode */ - else - { - HAL_UART_TxCpltCallback(huart); - } -} - -/** - * @brief DMA UART transmit process half complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - - HAL_UART_TxHalfCpltCallback(huart); -} - -/** - * @brief DMA UART receive process complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - - /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) - { - huart->RxXferCount = 0U; - - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - } - - HAL_UART_RxCpltCallback(huart); -} - -/** - * @brief DMA UART receive process half complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - - HAL_UART_RxHalfCpltCallback(huart); -} - -/** - * @brief DMA UART communication error callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - - /* Stop UART DMA Tx request if ongoing */ - if ( (huart->gState == HAL_UART_STATE_BUSY_TX) - &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) ) - { - huart->TxXferCount = 0U; - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - if ( (huart->RxState == HAL_UART_STATE_BUSY_RX) - &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ) - { - huart->RxXferCount = 0U; - UART_EndRxTransfer(huart); - } - - huart->ErrorCode |= HAL_UART_ERROR_DMA; - HAL_UART_ErrorCallback(huart); -} - -/** - * @brief DMA UART communication abort callback, when initiated by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - huart->RxXferCount = 0U; - huart->TxXferCount = 0U; - - HAL_UART_ErrorCallback(huart); -} - -/** - * @brief DMA UART Tx communication abort callback, when initiated by user - * (To be called at end of DMA Tx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Rx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); - - huart->hdmatx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if(huart->hdmarx != NULL) - { - if(huart->hdmarx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - -#if defined(USART_CR1_FIFOEN) - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } -#endif - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -} - - -/** - * @brief DMA UART Rx communication abort callback, when initiated by user - * (To be called at end of DMA Rx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Tx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent); - - huart->hdmarx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if(huart->hdmatx != NULL) - { - if(huart->hdmatx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -} - - -/** - * @brief DMA UART Tx communication abort callback, when initiated by user by a call to - * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) - * (This callback is executed at end of DMA Tx Abort procedure following user abort request, - * and leads to user Tx Abort Complete callback execution). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent); - - huart->TxXferCount = 0U; - -#if defined(USART_CR1_FIFOEN) - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } -#endif - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -} - -/** - * @brief DMA UART Rx communication abort callback, when initiated by user by a call to - * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) - * (This callback is executed at end of DMA Rx Abort procedure following user abort request, - * and leads to user Rx Abort Complete callback execution). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -} - -/** - * @brief TX interrrupt handler for 7 or 8 bits data word length . - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) -{ - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - if(huart->TxXferCount == 0) - { - /* Disable the UART Transmit Data Register Empty Interrupt */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); -#else - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); -#endif - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - else - { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); - huart->TxXferCount--; - } - } -} - -/** - * @brief TX interrrupt handler for 9 bits data word length. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) -{ - uint16_t* tmp; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - if(huart->TxXferCount == 0) - { - /* Disable the UART Transmit Data Register Empty Interrupt */ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); -#else - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); -#endif - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - else - { - tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FF); - huart->pTxBuffPtr += 2; - huart->TxXferCount--; - } - } -} - -#if defined(USART_CR1_FIFOEN) -/** - * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) -{ - uint8_t nb_tx_data; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - for(nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) - { - if(huart->TxXferCount == 0U) - { - /* Disable the TX FIFO threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - break; /* force exit loop */ - } - else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) - { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFF); - huart->TxXferCount--; - } - } - } -} - -/** - * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) -{ - uint16_t* tmp; - uint8_t nb_tx_data; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - for(nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0 ; nb_tx_data--) - { - if(huart->TxXferCount == 0U) - { - /* Disable the TX FIFO threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - break; /* force exit loop */ - } - else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != RESET) - { - tmp = (uint16_t*) huart->pTxBuffPtr; - huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU); - huart->pTxBuffPtr += 2U; - huart->TxXferCount--; - } - } - } -} -#endif - -/** - * @brief Wrap up transmission in non-blocking mode. - * @param huart pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable the UART Transmit Complete Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - /* Tx process is ended, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Cleat TxISR function pointer */ - huart->TxISR = NULL; - - HAL_UART_TxCpltCallback(huart); -} - -/** - * @brief RX interrrupt handler for 7 or 8 bits data word length . - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) -{ - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - - /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); - - if(--huart->RxXferCount == 0) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - HAL_UART_RxCpltCallback(huart); - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} - -/** - * @brief RX interrrupt handler for 9 bits data word length . - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) -{ - uint16_t* tmp; - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - - /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - tmp = (uint16_t*) huart->pRxBuffPtr ; - *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr +=2; - - if(--huart->RxXferCount == 0) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ -#if defined(USART_CR1_FIFOEN) - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); -#else - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); -#endif - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - HAL_UART_RxCpltCallback(huart); - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} - -#if defined(USART_CR1_FIFOEN) -/** - * @brief RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) -{ - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - uint8_t nb_rx_data; - - /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) - { - for(nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask); - huart->RxXferCount--; - - if(huart->RxXferCount == 0U) - { - /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - HAL_UART_RxCpltCallback(huart); - } - } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was - disabled (i.e. one interrupt per received frame). - */ - if (((huart->RxXferCount != 0U)) && (huart->RxXferCount < huart->NbRxDataToProcess)) - { - /* Disable the UART RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - - /* Update the RxISR function pointer */ - huart->RxISR = UART_RxISR_8BIT; - - /* Enable the UART Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} - -/** - * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) -{ - uint16_t* tmp; - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - uint8_t nb_rx_data; - - /* Check that a Rx process is ongoing */ - if(huart->RxState == HAL_UART_STATE_BUSY_RX) - { - for(nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0 ; nb_rx_data--) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - tmp = (uint16_t*) huart->pRxBuffPtr ; - *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr +=2; - huart->RxXferCount--; - - if(huart->RxXferCount == 0U) - { - /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - HAL_UART_RxCpltCallback(huart); - } - } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was - disabled (i.e. one interrupt per received frame). - */ - if (((huart->RxXferCount != 0U)) && (huart->RxXferCount < huart->NbRxDataToProcess)) - { - /* Disable the UART RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - - /* Update the RxISR function pointer */ - huart->RxISR = UART_RxISR_16BIT; - - /* Enable the UART Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} -#endif - -/** - * @} - */ - -#endif /* HAL_UART_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c deleted file mode 100644 index 363a37943..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c +++ /dev/null @@ -1,900 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_uart_ex.c - * @author MCD Application Team - * @brief Extended UART HAL module driver. - * This file provides firmware functions to manage the following extended - * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - * - @verbatim - ============================================================================== - ##### UART peripheral extended features ##### - ============================================================================== - - (#) Declare a UART_HandleTypeDef handle structure. - - (#) For the UART RS485 Driver Enable mode, initialize the UART registers - by calling the HAL_RS485Ex_Init() API. - - (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. - - -@- When USART operates in FIFO mode, FIFO mode must be enabled prior - starting RX/TX transfers. Also RX/TX FIFO thresholds must be - configured prior starting RX/TX transfers. - - (#) Slave mode enabling/disabling and NSS pin configuration. - - -@- When USART operates in Slave mode, Slave mode must be enabled prior - starting RX/TX transfers. - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @addtogroup STM32L4xx_HAL_Driver - * @{ - */ - -/** @defgroup UARTEx UARTEx - * @brief UART Extended HAL module driver - * @{ - */ - -#ifdef HAL_UART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup UARTEx_Private_Functions UARTEx Private Functions - * @{ - */ -static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); -#if defined(USART_CR1_FIFOEN) -static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); -#endif -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions - * @{ - */ - -/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Extended Initialization and Configuration Functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in asynchronous mode. - (+) For the asynchronous mode the parameters below can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - (++) Hardware flow control - (++) Receiver/transmitter modes - (++) Over Sampling Method - (++) One-Bit Sampling Method - (+) For the asynchronous mode, the following advanced features can be configured as well: - (++) TX and/or RX pin level inversion - (++) data logical level inversion - (++) RX and TX pins swap - (++) RX overrun detection disabling - (++) DMA disabling on RX error - (++) MSB first on communication line - (++) auto Baud rate detection - [..] - The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration - procedures (details for the procedures are available in reference manual). - -@endverbatim - - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible UART formats are listed in the - following table. - - Table 1. UART frame format. - +-----------------------------------------------------------------------+ - | M1 bit | M0 bit | PCE bit | UART frame | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 0 | | SB | 8 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 0 | | SB | 9 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 0 | | SB | 7 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - +-----------------------------------------------------------------------+ - - * @{ - */ - -/** - * @brief Initialize the RS485 Driver enable feature according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart UART handle. - * @param Polarity Select the driver enable polarity. - * This parameter can be one of the following values: - * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high - * @arg @ref UART_DE_POLARITY_LOW DE signal is active low - * @param AssertionTime Driver Enable assertion time: - * 5-bit value defining the time between the activation of the DE (Driver Enable) - * signal and the beginning of the start bit. It is expressed in sample time - * units (1/8 or 1/16 bit time, depending on the oversampling rate) - * @param DeassertionTime Driver Enable deassertion time: - * 5-bit value defining the time between the end of the last stop bit, in a - * transmitted message, and the de-activation of the DE (Driver Enable) signal. - * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the - * oversampling rate). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) -{ - uint32_t temp = 0x0; - - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - /* Check the Driver Enable UART instance */ - assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); - - /* Check the Driver Enable polarity */ - assert_param(IS_UART_DE_POLARITY(Polarity)); - - /* Check the Driver Enable assertion time */ - assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); - - /* Check the Driver Enable deassertion time */ - assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); - - if(huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, CORTEX */ - HAL_UART_MspInit(huart); - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DEM); - - /* Set the Driver Enable polarity */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); - - /* Set the Driver Enable assertion and deassertion times */ - temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); - temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); - MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @} - */ - -/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions - * @brief Extended functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of Wakeup and FIFO mode related callback functions. - - (#) Wakeup from Stop mode Callback: - (+) HAL_UARTEx_WakeupCallback() - - (#) TX/RX Fifos Callbacks: - (+) HAL_UARTEx_RxFifoFullCallback() - (+) HAL_UARTEx_TxFifoEmptyCallback() - -@endverbatim - * @{ - */ - -/** - * @brief UART wakeup from Stop mode callback. - * @param huart UART handle. - * @retval None - */ - __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_WakeupCallback can be implemented in the user file. - */ -} - -#if defined(USART_CR1_FIFOEN) -/** - * @brief UART RX Fifo full callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UARTEx_RxFifoFullCallback (UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. - */ -} - -/** - * @brief UART TX Fifo empty callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UARTEx_TxFifoEmptyCallback (UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. - */ -} -#endif - -/** - * @} - */ - -/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides the following functions: - (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode - (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality - (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address - detection length to more than 4 bits for multiprocessor address mark wake up. - (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode - trigger: address match, Start Bit detection or RXNE bit status. - (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode - (+) HAL_UARTEx_DisableStopMode() API disables the above functionality - (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt - (+) HAL_UARTEx_EnableSPISlaveMode() API enables the SPI slave mode - (+) HAL_UARTEx_DisableSPISlaveMode() API disables the SPI slave mode - (+) HAL_UARTEx_ConfigNSS API configures the Slave Select input pin (NSS) - (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode - (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode - (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold - (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold - -@endverbatim - * @{ - */ - - - - -/** - * @brief By default in multiprocessor mode, when the wake up method is set - * to address mark, the UART handles only 4-bit long addresses detection; - * this API allows to enable longer addresses detection (6-, 7- or 8-bit - * long). - * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, - * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. - * @param huart UART handle. - * @param AddressLength This parameter can be one of the following values: - * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address - * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) -{ - /* Check the UART handle allocation */ - if(huart == NULL) - { - return HAL_ERROR; - } - - /* Check the address length parameter */ - assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the address length */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Set Wakeup from Stop mode interrupt flag selection. - * @note It is the application responsibility to enable the interrupt used as - * usart_wkup interrupt source before entering low-power mode. - * @param huart UART handle. - * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. - * This parameter can be one of the following values: - * @arg @ref UART_WAKEUP_ON_ADDRESS - * @arg @ref UART_WAKEUP_ON_STARTBIT - * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart = 0; - - /* check the wake-up from stop mode UART instance */ - assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); - /* check the wake-up selection parameter */ - assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the wake-up selection scheme */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); - - if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) - { - UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); - } - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* Init tickstart for timeout managment*/ - tickstart = HAL_GetTick(); - - /* Wait until REACK flag is set */ - if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - status = HAL_TIMEOUT; - } - else - { - /* Initialize the UART State */ - huart->gState = HAL_UART_STATE_READY; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return status; -} - - -/** - * @brief Enable UART Stop Mode. - * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Set UESM bit */ - SET_BIT(huart->Instance->CR1, USART_CR1_UESM); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Disable UART Stop Mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear UESM bit */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -#if defined(USART_CR2_SLVEN) -/** - * @brief Enable the SPI slave mode. - * @note When the UART operates in SPI slave mode, it handles data flow using - * the serial interface clock derived from the external SCLK signal - * provided by the external master SPI device. - * @note In SPI slave mode, the UART must be enabled before starting the master - * communications (or between frames while the clock is stable). Otherwise, - * if the UART slave is enabled while the master is in the middle of a - * frame, it will become desynchronized with the master. - * @note The data register of the slave needs to be ready before the first edge - * of the communication clock or before the end of the ongoing communication, - * otherwise the SPI slave will transmit zeros. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableSlaveMode(UART_HandleTypeDef *huart) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* In SPI slave mode mode, the following bits must be kept cleared: - - LINEN and CLKEN bit in the USART_CR2 register - - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - /* Enable SPI slave mode */ - SET_BIT(huart->Instance->CR2, USART_CR2_SLVEN); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->SlaveMode = UART_SLAVEMODE_ENABLE; - - huart->gState = HAL_UART_STATE_READY; - - /* Enable UART */ - __HAL_UART_ENABLE(huart); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Disable the SPI slave mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableSlaveMode(UART_HandleTypeDef *huart) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Disable SPI slave mode */ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_SLVEN); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->SlaveMode = UART_SLAVEMODE_ENABLE; - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Configure the Slave Select input pin (NSS). - * @note Software NSS management: SPI slave will always be selected and NSS - * input pin will be ignored. - * @note Hardware NSS management: the SPI slave selection depends on NSS - * input pin. The slave is selected when NSS is low and deselected when - * NSS is high. - * @param huart UART handle. - * @param NSSConfig NSS configuration. - * This parameter can be one of the following values: - * @arg @ref UART_NSS_HARD - * @arg @ref UART_NSS_SOFT - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ConfigNSS(UART_HandleTypeDef *huart, uint32_t NSSConfig) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_SPI_SLAVE_INSTANCE(huart->Instance)); - assert_param(IS_UART_NSS(NSSConfig)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Program DIS_NSS bit in the USART_CR2 register */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} -#endif - -#if defined(USART_CR1_FIFOEN) -/** - * @brief Enable the FIFO mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Enable FIFO mode */ - SET_BIT(tmpcr1, USART_CR1_FIFOEN); - huart->FifoMode = UART_FIFOMODE_ENABLE; - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - /* Determine the number of data to process during RX/TX ISR execution */ - UARTEx_SetNbDataToProcess(huart); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Disable the FIFO mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Enable FIFO mode */ - CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); - huart->FifoMode = UART_FIFOMODE_DISABLE; - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Set the TXFIFO threshold. - * @param huart UART handle. - * @param Threshold TX FIFO threshold value - * This parameter can be one of the following values: - * @arg @ref UART_TXFIFO_THRESHOLD_1_8 - * @arg @ref UART_TXFIFO_THRESHOLD_1_4 - * @arg @ref UART_TXFIFO_THRESHOLD_1_2 - * @arg @ref UART_TXFIFO_THRESHOLD_3_4 - * @arg @ref UART_TXFIFO_THRESHOLD_7_8 - * @arg @ref UART_TXFIFO_THRESHOLD_8_8 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) -{ - uint32_t tmpcr1 = 0; - - /* Check parameters */ - assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); - assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Update TX threshold configuration */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); - - /* Determine the number of data to process during RX/TX ISR execution */ - UARTEx_SetNbDataToProcess(huart); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Set the RXFIFO threshold. - * @param huart UART handle. - * @param Threshold RX FIFO threshold value - * This parameter can be one of the following values: - * @arg @ref UART_RXFIFO_THRESHOLD_1_8 - * @arg @ref UART_RXFIFO_THRESHOLD_1_4 - * @arg @ref UART_RXFIFO_THRESHOLD_1_2 - * @arg @ref UART_RXFIFO_THRESHOLD_3_4 - * @arg @ref UART_RXFIFO_THRESHOLD_7_8 - * @arg @ref UART_RXFIFO_THRESHOLD_8_8 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) -{ - uint32_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); - assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Update RX threshold configuration */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); - - /* Determine the number of data to process during RX/TX ISR execution */ - UARTEx_SetNbDataToProcess(huart); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup UARTEx_Private_Functions - * @{ - */ - -/** - * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. - * @param huart UART handle. - * @param WakeUpSelection UART wake up from stop mode parameters. - * @retval None - */ -static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) -{ - assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); - - /* Set the USART address length */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); - - /* Set the USART address node */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); -} - -#if defined(USART_CR1_FIFOEN) -/** - * @brief Calculate the number of data to process in RX/TX ISR. - * @note The RX FIFO depth and the TX FIFO depth is extracted from - * the UART configuration registers. - * @param huart UART handle. - * @retval None - */ -void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) -{ - uint8_t rx_fifo_depth; - uint8_t tx_fifo_depth; - uint8_t rx_fifo_threshold; - uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1, 1, 1, 3, 7, 1}; - uint8_t denominator[] = {8, 4, 2, 4, 8, 1}; - - if (huart->FifoMode == UART_FIFOMODE_DISABLE) - { - huart->NbTxDataToProcess = 1; - huart->NbRxDataToProcess = 1; - } - else - { - rx_fifo_depth = 8; /* RX Fifo size */ - tx_fifo_depth = 8; /* TX Fifo size */ - rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); - tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - huart->NbTxDataToProcess = (uint8_t)(tx_fifo_depth * numerator[tx_fifo_threshold])/denominator[tx_fifo_threshold]; - huart->NbRxDataToProcess = (uint8_t)(rx_fifo_depth * numerator[rx_fifo_threshold])/denominator[rx_fifo_threshold]; - } -} -#endif - -/** - * @} - */ - -#endif /* HAL_UART_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c deleted file mode 100644 index 6c4a08326..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c +++ /dev/null @@ -1,2397 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_ll_usb.c - * @author MCD Application Team - * @brief USB Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization/de-initialization functions - * + I/O operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. - - (#) Call USB_CoreInit() API to initialize the USB Core peripheral. - - (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. - - @endverbatim - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -/** @defgroup USB_LL USB Low Layer - * @brief Low layer module for USB_FS and USB_OTG_FS drivers - * @{ - */ -#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) - -#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx) || \ - defined(STM32L452xx) || defined(STM32L462xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ - defined(STM32L496xx) || defined(STM32L4A6xx) || \ - defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) - -/** @addtogroup STM32L4xx_LL_USB_DRIVER - * @{ - */ - - - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -#if defined (USB_OTG_FS) -/** @defgroup USB_LL_Private_Functions USB Low Layer Private Functions - * @{ - */ -static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); -/** - * @} - */ -#endif /* USB_OTG_FS */ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions - * @{ - */ - -/** @defgroup LL_USB_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization/de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ -/*============================================================================== - USB OTG FS peripheral available on STM32L475xx, STM32L476xx, STM32L485xx and - STM32L486xx devices -==============================================================================*/ -#if defined (USB_OTG_FS) -/** - * @brief Initializes the USB Core - * @param USBx: USB Instance - * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(cfg); - - /* Select FS Embedded PHY */ - USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - - /* Reset after a PHY select and set Host mode */ - USB_CoreReset(USBx); - - /* Deactivate the power down*/ - USBx->GCCFG = USB_OTG_GCCFG_PWRDWN; - - return HAL_OK; -} - -/** - * @brief USB_EnableGlobalInt - * Enables the controller's Global Int in the AHB Config reg - * @param USBx: Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) -{ - USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; - return HAL_OK; -} - - -/** - * @brief USB_DisableGlobalInt - * Disable the controller's Global Int in the AHB Config reg - * @param USBx: Selected device - * @retval HAL status -*/ -HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) -{ - USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; - return HAL_OK; -} - -/** - * @brief USB_SetCurrentMode : Set functional mode - * @param USBx: Selected device - * @param mode: current core mode - * This parameter can be one of these values: - * @arg USB_OTG_DEVICE_MODE: Peripheral mode - * @arg USB_OTG_HOST_MODE: Host mode - * @arg USB_OTG_DRD_MODE: Dual Role Device mode - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode) -{ - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); - - if ( mode == USB_HOST_MODE) - { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; - } - else if ( mode == USB_DEVICE_MODE) - { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; - } - HAL_Delay(50); - - return HAL_OK; -} - -/** - * @brief USB_DevInit : Initializes the USB_OTG controller registers - * for device mode - * @param USBx: Selected device - * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - uint32_t index = 0; - - /*Activate VBUS Sensing B */ - USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; - - if (cfg.vbus_sensing_enable == 0) - { - /* Deactivate VBUS Sensing B */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN; - - /* B-peripheral session valid override enable*/ - USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; - USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; - } - - /* Restart the Phy Clock */ - USBx_PCGCCTL = 0; - - /* Device mode configuration */ - USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; - - /* Set Full speed phy */ - USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL); - - /* Flush the FIFOs */ - USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */ - USB_FlushRxFifo(USBx); - - /* Clear all pending Device Interrupts */ - USBx_DEVICE->DIEPMSK = 0; - USBx_DEVICE->DOEPMSK = 0; - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK = 0; - - for (index = 0; index < cfg.dev_endpoints; index++) - { - if ((USBx_INEP(index)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) - { - USBx_INEP(index)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK); - } - else - { - USBx_INEP(index)->DIEPCTL = 0; - } - - USBx_INEP(index)->DIEPTSIZ = 0; - USBx_INEP(index)->DIEPINT = 0xFF; - } - - for (index = 0; index < cfg.dev_endpoints; index++) - { - if ((USBx_OUTEP(index)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) - { - USBx_OUTEP(index)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK); - } - else - { - USBx_OUTEP(index)->DOEPCTL = 0; - } - - USBx_OUTEP(index)->DOEPTSIZ = 0; - USBx_OUTEP(index)->DOEPINT = 0xFF; - } - - USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); - - if (cfg.dma_enable == 1) - { - /*Set threshold parameters */ - USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6); - USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN); - - index= USBx_DEVICE->DTHRCTL; - } - - /* Disable all interrupts. */ - USBx->GINTMSK = 0; - - /* Clear any pending interrupts */ - USBx->GINTSTS = 0xBFFFFFFF; - - /* Enable the common interrupts */ - if (cfg.dma_enable == DISABLE) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } - - /* Enable interrupts matching to the Device mode ONLY */ - USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\ - USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\ - USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\ - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - - if(cfg.Sof_enable) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; - } - - if (cfg.vbus_sensing_enable == ENABLE) - { - USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); - } - - return HAL_OK; -} - - -/** - * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO - * @param USBx: Selected device - * @param num: FIFO number - * This parameter can be a value from 1 to 15 - 15 means Flush all Tx FIFOs - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num) -{ - uint32_t count = 0; - - USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); - - do - { - if (++count > 200000) - { - return HAL_TIMEOUT; - } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); - - return HAL_OK; -} - - -/** - * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx: Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t count = 0; - - USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; - - do - { - if (++count > 200000) - { - return HAL_TIMEOUT; - } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); - - return HAL_OK; -} - -/** - * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register - * depending the PHY type and the enumeration speed of the device. - * @param USBx: Selected device - * @param speed: device speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode - * @retval Hal status - */ -HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) -{ - USBx_DEVICE->DCFG |= speed; - return HAL_OK; -} - -/** - * @brief USB_GetDevSpeed :Return the Dev Speed - * @param USBx: Selected device - * @retval speed : device speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode - */ -uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) -{ - uint8_t speed = 0; - - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) - { - speed = USB_OTG_SPEED_HIGH; - } - else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)|| - ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ)) - { - speed = USB_OTG_SPEED_FULL; - } - else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) - { - speed = USB_OTG_SPEED_LOW; - } - - return speed; -} - -/** - * @brief Activate and configure an endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - if (ep->is_in == 1) - { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); - - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) - { - USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - } - - } - else - { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); - - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) - { - USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP)); - } - } - return HAL_OK; -} -/** - * @brief Activate and configure a dedicated endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - static __IO uint32_t debug = 0; - - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) - { - USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - } - - - debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); - } - else - { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) - { - USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); - - debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE); - debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL; - debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ - ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); - } - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); - } - - return HAL_OK; -} -/** - * @brief De-activate and de-initialize an endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; - } - else - { - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; - } - return HAL_OK; -} - -/** - * @brief De-activate and de-initialize a dedicated endpoint - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); - } - else - { - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); - } - return HAL_OK; -} - -/** - * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) -{ - uint16_t pktcnt = 0; - - /* IN endpoint */ - if (ep->is_in == 1) - { - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - if (ep->type == EP_TYPE_ISOC) - { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); - } - } - if (ep->type != EP_TYPE_ISOC) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num; - } - } - - if (ep->type == EP_TYPE_ISOC) - { - if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) - { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; - } - else - { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; - } - } - - /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - - if (ep->type == EP_TYPE_ISOC) - { - USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma); - } - } - else /* OUT endpoint */ - { - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (ep->xfer_len == 0) - { - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; - } - else - { - pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); ; - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); - } - - if (ep->type == EP_TYPE_ISOC) - { - if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) - { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; - } - else - { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; - } - } - /* EP enable */ - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); - } - return HAL_OK; -} - -/** - * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(dma); - - /* IN endpoint */ - if (ep->is_in == 1) - { - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - - if(ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - } - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - } - - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num); - } - - /* EP enable, IN data in FIFO */ - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - } - else /* OUT endpoint */ - { - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (ep->xfer_len > 0) - { - ep->xfer_len = ep->maxpacket; - } - - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); - USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); - - /* EP enable */ - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); - } - return HAL_OK; -} - -/** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated - * with the EP/channel - * @param USBx: Selected device - * @param src: pointer to source buffer - * @param ch_ep_num: endpoint or host channel number - * @param len: Number of bytes to write - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(dma); - - uint32_t count32b= 0 , index= 0; - count32b = (len + 3) / 4; - for (index = 0; index < count32b; index++, src += 4) - { - USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src); - } - return HAL_OK; -} - -/** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated - * with the EP/channel - * @param USBx: Selected device - * @param src: source pointer - * @param ch_ep_num: endpoint or host channel number - * @param len: Number of bytes to read - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval pointer to destination buffer - */ -void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) -{ - uint32_t index=0; - uint32_t count32b = (len + 3) / 4; - - for ( index = 0; index < count32b; index++, dest += 4 ) - { - *(__packed uint32_t *)dest = USBx_DFIFO(0); - - } - return ((void *)dest); -} - -/** - * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) -{ - if (ep->is_in == 1) - { - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0) - { - USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); - } - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; - } - else - { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0) - { - USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); - } - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; - } - return HAL_OK; -} - - -/** - * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx: Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - if (ep->is_in == 1) - { - USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) - { - USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - else - { - USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) - { - USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - return HAL_OK; -} - -/** - * @brief USB_StopDevice : Stop the USB device mode - * @param USBx: Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t index; - - /* Clear Pending interrupt */ - for (index = 0; index < 15 ; index++) - { - USBx_INEP(index)->DIEPINT = 0xFF; - USBx_OUTEP(index)->DOEPINT = 0xFF; - } - USBx_DEVICE->DAINT = 0xFFFFFFFF; - - /* Clear interrupt masks */ - USBx_DEVICE->DIEPMSK = 0; - USBx_DEVICE->DOEPMSK = 0; - USBx_DEVICE->DAINTMSK = 0; - - /* Flush the FIFO */ - USB_FlushRxFifo(USBx); - USB_FlushTxFifo(USBx , 0x10 ); - - return HAL_OK; -} - -/** - * @brief USB_SetDevAddress : Stop the USB device mode - * @param USBx: Selected device - * @param address: new device address to be assigned - * This parameter can be a value from 0 to 255 - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address) -{ - USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD); - USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ; - - return HAL_OK; -} - -/** - * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down - * @param USBx: Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) -{ - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ; - HAL_Delay(3); - - return HAL_OK; -} - -/** - * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx: Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) -{ - USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ; - HAL_Delay(3); - - return HAL_OK; -} - -/** - * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx: Selected device - * @retval HAL status - */ -uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t tmpreg = 0; - - tmpreg = USBx->GINTSTS; - tmpreg &= USBx->GINTMSK; - return tmpreg; -} - -/** - * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx: Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t tmpreg; - tmpreg = USBx_DEVICE->DAINT; - tmpreg &= USBx_DEVICE->DAINTMSK; - return ((tmpreg & 0xffff0000) >> 16); -} - -/** - * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx: Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t tmpreg; - tmpreg = USBx_DEVICE->DAINT; - tmpreg &= USBx_DEVICE->DAINTMSK; - return ((tmpreg & 0xFFFF)); -} - -/** - * @brief Returns Device OUT EP Interrupt register - * @param USBx: Selected device - * @param epnum: endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device OUT EP Interrupt register - */ -uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) -{ - uint32_t tmpreg; - tmpreg = USBx_OUTEP(epnum)->DOEPINT; - tmpreg &= USBx_DEVICE->DOEPMSK; - return tmpreg; -} - -/** - * @brief Returns Device IN EP Interrupt register - * @param USBx: Selected device - * @param epnum: endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device IN EP Interrupt register - */ -uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) -{ - uint32_t tmpreg = 0, msk = 0, emp = 0; - - msk = USBx_DEVICE->DIEPMSK; - emp = USBx_DEVICE->DIEPEMPMSK; - msk |= ((emp >> epnum) & 0x1) << 7; - tmpreg = USBx_INEP(epnum)->DIEPINT & msk; - return tmpreg; -} - -/** - * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx: Selected device - * @param interrupt: interrupt flag - * @retval None - */ -void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) -{ - USBx->GINTSTS |= interrupt; -} - -/** - * @brief Returns USB core mode - * @param USBx: Selected device - * @retval return core mode : Host or Device - * This parameter can be one of these values: - * 0 : Host - * 1 : Device - */ -uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) -{ - return ((USBx->GINTSTS ) & 0x1); -} - - -/** - * @brief Activate EP0 for Setup transactions - * @param USBx: Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) -{ - /* Set the MPS of the IN EP based on the enumeration speed */ - USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; - - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) - { - USBx_INEP(0)->DIEPCTL |= 3; - } - USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; - - return HAL_OK; -} - - -/** - * @brief Prepare the EP0 to start the first control setup - * @param USBx: Selected device - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @param psetup: pointer to setup packet - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(psetup); - - USBx_OUTEP(0)->DOEPTSIZ = 0; - USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; - USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8); - USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; - - return HAL_OK; -} - -/** - * @brief USB_HostInit : Initializes the USB OTG controller registers - * for Host mode - * @param USBx: Selected device - * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - uint32_t index = 0; - - /* Restart the Phy Clock */ - USBx_PCGCCTL = 0; - - /* Disable the FS/LS support mode only */ - if((cfg.speed == USB_OTG_SPEED_FULL)&& - (USBx != USB_OTG_FS)) - { - USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; - } - else - { - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); - } - - /* Make sure the FIFOs are flushed. */ - USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */ - USB_FlushRxFifo(USBx); - - /* Clear all pending HC Interrupts */ - for (index = 0; index < cfg.Host_channels; index++) - { - USBx_HC(index)->HCINT = 0xFFFFFFFF; - USBx_HC(index)->HCINTMSK = 0; - } - - /* Enable VBUS driving */ - USB_DriveVbus(USBx, 1); - - HAL_Delay(200); - - /* Disable all interrupts. */ - USBx->GINTMSK = 0; - - /* Clear any pending interrupts */ - USBx->GINTSTS = 0xFFFFFFFF; - - /* set Rx FIFO size */ - USBx->GRXFSIZ = (uint32_t )0x80; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80); - USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0); - - /* Enable the common interrupts */ - if (cfg.dma_enable == DISABLE) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } - - /* Enable interrupts matching to the Host mode ONLY */ - USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\ - USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\ - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - - return HAL_OK; -} - -/** - * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the - * HCFG register on the PHY type and set the right frame interval - * @param USBx: Selected device - * @param freq: clock frequency - * This parameter can be one of these values: - * HCFG_48_MHZ : Full Speed 48 MHz Clock - * HCFG_6_MHZ : Low Speed 6 MHz Clock - * @retval HAL status - */ -HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq) -{ - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); - USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS); - - if (freq == HCFG_48_MHZ) - { - USBx_HOST->HFIR = (uint32_t)48000; - } - else if (freq == HCFG_6_MHZ) - { - USBx_HOST->HFIR = (uint32_t)6000; - } - return HAL_OK; -} - -/** -* @brief USB_OTG_ResetPort : Reset Host Port - * @param USBx: Selected device - * @retval HAL status - * @note (1)The application must wait at least 10 ms - * before clearing the reset bit. - */ -HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) -{ - __IO uint32_t hprt0 = 0; - - hprt0 = USBx_HPRT0; - - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); - HAL_Delay (10); /* See Note #1 */ - USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); - return HAL_OK; -} - -/** - * @brief USB_DriveVbus : activate or de-activate vbus - * @param state: VBUS state - * This parameter can be one of these values: - * 0 : VBUS Active - * 1 : VBUS Inactive - * @retval HAL status -*/ -HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) -{ - __IO uint32_t hprt0 = 0; - - hprt0 = USBx_HPRT0; - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); - - if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 )) - { - USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); - } - if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 )) - { - USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); - } - return HAL_OK; -} - -/** - * @brief Return Host Core speed - * @param USBx: Selected device - * @retval speed : Host speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode - */ -uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) -{ - __IO uint32_t hprt0 = 0; - - hprt0 = USBx_HPRT0; - return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); -} - -/** - * @brief Return Host Current Frame number - * @param USBx: Selected device - * @retval current frame number -*/ -uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) -{ - return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); -} - -/** - * @brief Initialize a host channel - * @param USBx: Selected device - * @param ch_num : Channel number - * This parameter can be a value from 1 to 15 - * @param epnum: Endpoint number - * This parameter can be a value from 1 to 15 - * @param dev_address: Current device address - * This parameter can be a value from 0 to 255 - * @param speed: Current device speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode - * @param ep_type: Endpoint Type - * This parameter can be one of these values: - * @arg EP_TYPE_CTRL: Control type - * @arg EP_TYPE_ISOC: Isochronous type - * @arg EP_TYPE_BULK: Bulk type - * @arg EP_TYPE_INTR: Interrupt type - * @param mps: Max Packet Size - * This parameter can be a value from 0 to32K - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) -{ - - /* Clear old interrupt conditions for this host channel. */ - USBx_HC(ch_num)->HCINT = 0xFFFFFFFF; - - /* Enable channel interrupts required for this transfer. */ - switch (ep_type) - { - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_STALLM |\ - USB_OTG_HCINTMSK_TXERRM |\ - USB_OTG_HCINTMSK_DTERRM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_NAKM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - } - break; - - case EP_TYPE_INTR: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_STALLM |\ - USB_OTG_HCINTMSK_TXERRM |\ - USB_OTG_HCINTMSK_DTERRM |\ - USB_OTG_HCINTMSK_NAKM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - } - - break; - case EP_TYPE_ISOC: - - USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ - USB_OTG_HCINTMSK_ACKM |\ - USB_OTG_HCINTMSK_AHBERR |\ - USB_OTG_HCINTMSK_FRMORM ; - - if (epnum & 0x80) - { - USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); - } - break; - } - - /* Enable the top level host channel interrupt. */ - USBx_HOST->HAINTMSK |= (1 << ch_num); - - /* Make sure host channel interrupts are enabled. */ - USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; - - /* Program the HCCHAR register */ - USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\ - (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\ - ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\ - (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\ - ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\ - (mps & USB_OTG_HCCHAR_MPSIZ)); - - if (ep_type == EP_TYPE_INTR) - { - USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; - } - - return HAL_OK; -} - -/** - * @brief Start a transfer over a host channel - * @param USBx: Selected device - * @param hc: pointer to host channel structure - * @param dma: USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL state - */ -#if defined (__CC_ARM) /*!< ARM Compiler */ -#pragma O0 -#elif defined (__GNUC__) /*!< GNU Compiler */ -#pragma GCC optimize ("O0") -#endif /* __CC_ARM */ -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) -{ - uint8_t is_oddframe = 0; - uint16_t len_words = 0; - uint16_t num_packets = 0; - uint16_t max_hc_pkt_count = 256; - uint32_t tmpreg = 0; - - /* Compute the expected number of packets associated to the transfer */ - if (hc->xfer_len > 0) - { - num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet; - - if (num_packets > max_hc_pkt_count) - { - num_packets = max_hc_pkt_count; - hc->xfer_len = num_packets * hc->max_packet; - } - } - else - { - num_packets = 1; - } - if (hc->ep_is_in) - { - hc->xfer_len = num_packets * hc->max_packet; - } - - /* Initialize the HCTSIZn register */ - USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\ - ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID); - - if (dma) - { - /* xfer_buff MUST be 32-bits aligned */ - USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff; - } - - is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1; - USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; - USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29); - - /* Set host channel enable */ - tmpreg = USBx_HC(hc->ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc->ch_num)->HCCHAR = tmpreg; - - if (dma == 0) /* Slave mode */ - { - if((hc->ep_is_in == 0) && (hc->xfer_len > 0)) - { - switch(hc->ep_type) - { - /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - len_words = (hc->xfer_len + 3) / 4; - - /* check if there is enough space in FIFO space */ - if(len_words > (USBx->HNPTXSTS & 0xFFFF)) - { - /* need to process data in nptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; - } - break; - /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - len_words = (hc->xfer_len + 3) / 4; - /* check if there is enough space in FIFO space */ - if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; - } - break; - - default: - break; - } - - /* Write packet into the Tx FIFO. */ - USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0); - } - } - - return HAL_OK; -} - -/** - * @brief Read all host channel interrupts status - * @param USBx: Selected device - * @retval HAL state - */ -uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) -{ - return ((USBx_HOST->HAINT) & 0xFFFF); -} - -/** - * @brief Halt a host channel - * @param USBx: Selected device - * @param hc_num: Host Channel number - * This parameter can be a value from 1 to 15 - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) -{ - uint32_t count = 0; - - /* Check for space in the request queue to issue the halt. */ - if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18))) - { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - - if ((USBx->HNPTXSTS & 0xFFFF) == 0) - { - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; - do - { - if (++count > 1000) - { - break; - } - } - while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - else - { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - } - } - else - { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - - if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0) - { - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; - do - { - if (++count > 1000) - { - break; - } - } - while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - else - { - USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - } - } - - return HAL_OK; -} - -/** - * @brief Initiate Do Ping protocol - * @param USBx: Selected device - * @param hc_num: Host Channel number - * This parameter can be a value from 1 to 15 - * @retval HAL state - */ -HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) -{ - uint8_t num_packets = 1; - uint32_t tmpreg = 0; - - USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ - USB_OTG_HCTSIZ_DOPING; - - /* Set host channel enable */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; - - return HAL_OK; -} - -/** - * @brief Stop Host Core - * @param USBx: Selected device - * @retval HAL state - */ -HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) -{ - uint8_t index; - uint32_t count = 0; - uint32_t value = 0; - - USB_DisableGlobalInt(USBx); - - /* Flush FIFO */ - USB_FlushTxFifo(USBx, 0x10); - USB_FlushRxFifo(USBx); - - /* Flush out any leftover queued requests. */ - for (index = 0; index <= 15; index++) - { - value = USBx_HC(index)->HCCHAR; - value |= USB_OTG_HCCHAR_CHDIS; - value &= ~USB_OTG_HCCHAR_CHENA; - value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(index)->HCCHAR = value; - } - - /* Halt all channels to put them into a known state. */ - for (index = 0; index <= 15; index++) - { - value = USBx_HC(index)->HCCHAR ; - value |= USB_OTG_HCCHAR_CHDIS; - value |= USB_OTG_HCCHAR_CHENA; - value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(index)->HCCHAR = value; - - USBx_HC(index)->HCCHAR = value; - do - { - if (++count > 1000) - { - break; - } - } - while ((USBx_HC(index)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - - /* Clear any pending Host interrupts */ - USBx_HOST->HAINT = 0xFFFFFFFF; - USBx->GINTSTS = 0xFFFFFFFF; - USB_EnableGlobalInt(USBx); - return HAL_OK; -} - -/** - * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) -{ - if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) - { - /* active Remote wakeup signalling */ - USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; - } - return HAL_OK; -} - -/** - * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) -{ - /* active Remote wakeup signalling */ - USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); - return HAL_OK; -} - -#endif /* USB_OTG_FS */ - -/*============================================================================== - USB Device FS peripheral available on STM32L432xx, STM32L433xx, STM32L442xx) - and STM32L443xx devices -==============================================================================*/ -#if defined (USB) -/** - * @brief Initializes the USB Core - * @param USBx: USB Instance - * @param cfg : pointer to a USB_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(cfg); - - return HAL_OK; -} - -/** - * @brief USB_EnableGlobalInt - * Enables the controller's Global Int in the AHB Config reg - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) -{ - uint32_t winterruptmask = 0; - - /* Set winterruptmask variable */ - winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; - - /* Set interrupt mask */ - USBx->CNTR |= winterruptmask; - - return HAL_OK; -} - -/** - * @brief USB_DisableGlobalInt - * Disable the controller's Global Int in the AHB Config reg - * @param USBx : Selected device - * @retval HAL status -*/ -HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) -{ - uint32_t winterruptmask = 0; - - /* Set winterruptmask variable */ - winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; - - /* Clear interrupt mask */ - USBx->CNTR &= ~winterruptmask; - - return HAL_OK; -} - -/** - * @brief USB_SetCurrentMode : Set functional mode - * @param USBx : Selected device - * @param mode : current core mode - * This parameter can be one of the these values: - * @arg USB_DEVICE_MODE: Peripheral mode mode - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(mode); - - return HAL_OK; -} - -/** - * @brief USB_DevInit : Initializes the USB controller registers - * for device mode - * @param USBx : Selected device - * @param cfg : pointer to a USB_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(cfg); - - /* Init Device */ - /*CNTR_FRES = 1*/ - USBx->CNTR = USB_CNTR_FRES; - - /*CNTR_FRES = 0*/ - USBx->CNTR = 0; - - /*Clear pending interrupts*/ - USBx->ISTR = 0; - - /*Set Btable Address*/ - USBx->BTABLE = BTABLE_ADDRESS; - - return HAL_OK; -} - -/** - * @brief USB_FlushTxFifo : Flush a Tx FIFO - * @param USBx : Selected device - * @param num : FIFO number - * This parameter can be a value from 1 to 15 - 15 means Flush all Tx FIFOs - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(num); - - return HAL_OK; -} - -/** - * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - - return HAL_OK; -} - -/** - * @brief Activate and configure an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) -{ - /* initialize Endpoint */ - switch (ep->type) - { - case EP_TYPE_CTRL: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_CONTROL); - break; - case EP_TYPE_BULK: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_BULK); - break; - case EP_TYPE_INTR: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_INTERRUPT); - break; - case EP_TYPE_ISOC: - PCD_SET_EPTYPE(USBx, ep->num, USB_EP_ISOCHRONOUS); - break; - default: - break; - } - - PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); - - if (ep->doublebuffer == 0) - { - if (ep->is_in) - { - /*Set the endpoint Transmit buffer address */ - PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - /* Configure NAK status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - else - { - /*Set the endpoint Receive buffer address */ - PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); - /*Set the endpoint Receive buffer counter*/ - PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); - PCD_CLEAR_RX_DTOG(USBx, ep->num); - /* Configure VALID status for the Endpoint*/ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - } - } - /*Double Buffer*/ - else - { - /*Set the endpoint as double buffered*/ - PCD_SET_EP_DBUF(USBx, ep->num); - /*Set buffer address for double buffered mode*/ - PCD_SET_EP_DBUF_ADDR(USBx, ep->num,ep->pmaaddr0, ep->pmaaddr1); - - if (ep->is_in==0) - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - /* Reset value of the data toggle bits for the endpoint out*/ - PCD_TX_DTOG(USBx, ep->num); - - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - else - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - PCD_RX_DTOG(USBx, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - } - } - - return HAL_OK; -} - -/** - * @brief De-activate and de-initialize an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) -{ - if (ep->doublebuffer == 0) - { - if (ep->is_in) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - else - { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - } - } - /*Double Buffer*/ - else - { - if (ep->is_in==0) - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - /* Reset value of the data toggle bits for the endpoint out*/ - PCD_TX_DTOG(USBx, ep->num); - - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - else - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - PCD_RX_DTOG(USBx, ep->num); - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - } - } - - return HAL_OK; -} - -/** - * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep, uint8_t dma) -{ - uint16_t pmabuffer = 0; - uint32_t len = ep->xfer_len; - - /* IN endpoint */ - if (ep->is_in == 1) - { - /*Multi packet transfer*/ - if (ep->xfer_len > ep->maxpacket) - { - len=ep->maxpacket; - ep->xfer_len-=len; - } - else - { - len=ep->xfer_len; - ep->xfer_len =0; - } - - /* configure and validate Tx endpoint */ - if (ep->doublebuffer == 0) - { - USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, len); - PCD_SET_EP_TX_CNT(USBx, ep->num, len); - } - else - { - /* Write the data to the USB endpoint */ - if (PCD_GET_ENDPOINT(USBx, ep->num)& USB_EP_DTOG_TX) - { - /* Set the Double buffer counter for pmabuffer1 */ - PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr1; - } - else - { - /* Set the Double buffer counter for pmabuffer0 */ - PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr0; - } - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, len); - PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); - } - - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); - } - else /* OUT endpoint */ - { - /* Multi packet transfer*/ - if (ep->xfer_len > ep->maxpacket) - { - len=ep->maxpacket; - ep->xfer_len-=len; - } - else - { - len=ep->xfer_len; - ep->xfer_len =0; - } - - /* configure and validate Rx endpoint */ - if (ep->doublebuffer == 0) - { - /*Set RX buffer count*/ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); - } - else - { - /*Set the Double buffer counter*/ - PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - } - - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - } - - return HAL_OK; -} - -/** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated - * with the EP/channel - * @param USBx : Selected device - * @param src : pointer to source buffer - * @param ch_ep_num : endpoint or host channel number - * @param len : Number of bytes to write - * @retval HAL status - */ -HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(src); - UNUSED(ch_ep_num); - UNUSED(len); - - return HAL_OK; -} - -/** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated - * with the EP/channel - * @param USBx : Selected device - * @param dest : destination pointer - * @param len : Number of bytes to read - * @retval pointer to destination buffer - */ -void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(dest); - UNUSED(len); - - return ((void *)NULL); -} - -/** - * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep) -{ - if (ep->num == 0) - { - /* This macro sets STALL status for RX & TX*/ - PCD_SET_EP_TXRX_STATUS(USBx, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); - } - else - { - if (ep->is_in) - { - PCD_SET_EP_TX_STATUS(USBx, ep->num , USB_EP_TX_STALL); - } - else - { - PCD_SET_EP_RX_STATUS(USBx, ep->num , USB_EP_RX_STALL); - } - } - return HAL_OK; -} - -/** - * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) -{ - if (ep->is_in) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); - } - else - { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - } - return HAL_OK; -} - -/** - * @brief USB_StopDevice : Stop the usb device mode - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) -{ - /* disable all interrupts and force USB reset */ - USBx->CNTR = USB_CNTR_FRES; - - /* clear interrupt status register */ - USBx->ISTR = 0; - - /* switch-off device */ - USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); - - return HAL_OK; -} - -/** - * @brief USB_SetDevAddress : Stop the usb device mode - * @param USBx : Selected device - * @param address : new device address to be assigned - * This parameter can be a value from 0 to 255 - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address) -{ - if(address == 0) - { - /* set device address and enable function */ - USBx->DADDR = USB_DADDR_EF; - } - - return HAL_OK; -} - -/** - * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx) -{ - /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ - USB->BCDR |= USB_BCDR_DPPU; - - return HAL_OK; -} - -/** - * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx) -{ - /* Disable DP Pull-Down bit*/ - USB->BCDR &= ~(USB_BCDR_DPPU); - - return HAL_OK; -} - -/** - * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadInterrupts (USB_TypeDef *USBx) -{ - uint32_t tmpreg = 0; - - tmpreg = USBx->ISTR; - return tmpreg; -} - -/** - * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - - return (0); -} - -/** - * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - - return (0); -} - -/** - * @brief Returns Device OUT EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device OUT EP Interrupt register - */ -uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(epnum); - - return (0); -} - -/** - * @brief Returns Device IN EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device IN EP Interrupt register - */ -uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(epnum); - - return (0); -} - -/** - * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx : Selected device - * @param interrupt : interrupt flag - * @retval None - */ -void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(interrupt); -} - -/** - * @brief Prepare the EP0 to start the first control setup - * @param USBx : Selected device - * @param psetup : pointer to setup packet - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t dma ,uint8_t *psetup) -{ - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(psetup); - UNUSED(dma); - - return HAL_OK; -} - -/** - * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) -{ - USBx->CNTR |= USB_CNTR_RESUME; - - return HAL_OK; -} - -/** - * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) -{ - USBx->CNTR &= ~(USB_CNTR_RESUME); - return HAL_OK; -} - -/** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx : pointer to USB register. - * @param pbUsrBuf : pointer to user memory area. - * @param wPMABufAddr : address into PMA. - * @param wNBytes : number of bytes to be copied. - * @retval None - */ -void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) -{ - uint32_t n = (wNBytes + 1) >> 1; - uint32_t i; - uint16_t temp1, temp2; - uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); - - for (i = n; i != 0; i--) - { - temp1 = (uint16_t) * pbUsrBuf; - pbUsrBuf++; - temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; - *pdwVal++ = temp2; - pbUsrBuf++; - } -} - -/** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx : pointer to USB register. -* @param pbUsrBuf : pointer to user memory area. - * @param wPMABufAddr : address into PMA. - * @param wNBytes : number of bytes to be copied. - * @retval None - */ -void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) -{ - uint32_t n = (wNBytes + 1) >> 1; - uint32_t i; - uint16_t *pdwVal; - pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); - for (i = n; i != 0; i--) - { - *(uint16_t*)pbUsrBuf++ = *pdwVal++; - pbUsrBuf++; - } -} -#endif /* USB */ -/** - * @} - */ -/** - * @} - */ - -#if defined (USB_OTG_FS) -/** @addtogroup USB_LL_Private_Functions - * @{ - */ -/** - * @brief Reset the USB Core (needed after USB clock settings change) - * @param USBx : Selected device - * @retval HAL status - */ -static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t count = 0; - - /* Wait for AHB master IDLE state. */ - do - { - if (++count > 200000) - { - return HAL_TIMEOUT; - } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0); - - /* Core Soft Reset */ - count = 0; - USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; - - do - { - if (++count > 200000) - { - return HAL_TIMEOUT; - } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); - - return HAL_OK; -} -/** - * @} - */ -#endif /* USB_OTG_FS */ - -#endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || */ - /* STM32L452xx || STM32L462xx || */ - /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ - /* STM32L496xx || STM32L4A6xx || */ - /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ - -#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/main.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/main.h deleted file mode 100644 index 41096aedb..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/main.h +++ /dev/null @@ -1,90 +0,0 @@ -/** - ****************************************************************************** - * @file : main.h - * @brief : Header for main.c file. - * This file contains the common defines of the application. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MAIN_H__ -#define __MAIN_H__ - -/* Includes ------------------------------------------------------------------*/ - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private define ------------------------------------------------------------*/ - -#define B1_Pin GPIO_PIN_13 -#define B1_GPIO_Port GPIOC -#define LD2_Pin GPIO_PIN_5 -#define LD2_GPIO_Port GPIOA - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* USER CODE BEGIN Private defines */ - -/* USER CODE END Private defines */ - -#ifdef __cplusplus - extern "C" { -#endif -void _Error_Handler(char *, int); - -#define Error_Handler() _Error_Handler(__FILE__, __LINE__) -#ifdef __cplusplus -} -#endif - -#endif /* __MAIN_H__ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/stm32l4xx_hal_conf.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/stm32l4xx_hal_conf.h deleted file mode 100644 index 5de43fcb2..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/stm32l4xx_hal_conf.h +++ /dev/null @@ -1,430 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_hal_conf.h - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2018 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_HAL_CONF_H -#define __STM32L4xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "main.h" -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ - -#define HAL_MODULE_ENABLED -/*#define HAL_ADC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_CAN_MODULE_ENABLED */ -/*#define HAL_COMP_MODULE_ENABLED */ -/*#define HAL_CRC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_DAC_MODULE_ENABLED */ -/*#define HAL_DCMI_MODULE_ENABLED */ -/*#define HAL_DMA2D_MODULE_ENABLED */ -/*#define HAL_DFSDM_MODULE_ENABLED */ -/*#define HAL_DSI_MODULE_ENABLED */ -/*#define HAL_FIREWALL_MODULE_ENABLED */ -/*#define HAL_GFXMMU_MODULE_ENABLED */ -/*#define HAL_HCD_MODULE_ENABLED */ -/*#define HAL_HASH_MODULE_ENABLED */ -/*#define HAL_I2S_MODULE_ENABLED */ -/*#define HAL_IRDA_MODULE_ENABLED */ -/*#define HAL_IWDG_MODULE_ENABLED */ -/*#define HAL_LTDC_MODULE_ENABLED */ -/*#define HAL_LCD_MODULE_ENABLED */ -/*#define HAL_LPTIM_MODULE_ENABLED */ -/*#define HAL_NAND_MODULE_ENABLED */ -/*#define HAL_NOR_MODULE_ENABLED */ -/*#define HAL_OPAMP_MODULE_ENABLED */ -/*#define HAL_OSPI_MODULE_ENABLED */ -/*#define HAL_OSPI_MODULE_ENABLED */ -#define HAL_PCD_MODULE_ENABLED -/*#define HAL_QSPI_MODULE_ENABLED */ -/*#define HAL_QSPI_MODULE_ENABLED */ -#define HAL_RNG_MODULE_ENABLED -#define HAL_RTC_MODULE_ENABLED -/*#define HAL_SAI_MODULE_ENABLED */ -/*#define HAL_SD_MODULE_ENABLED */ -/*#define HAL_SMBUS_MODULE_ENABLED */ -/*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ -/*#define HAL_SRAM_MODULE_ENABLED */ -/*#define HAL_SWPMI_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ -/*#define HAL_TSC_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/*#define HAL_USART_MODULE_ENABLED */ -/*#define HAL_WWDG_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_I2C_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED - -/* ########################## Oscillator Values adaptation ####################*/ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal Multiple Speed oscillator (MSI) default value. - * This value is the default MSI range value after Reset. - */ -#if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. - * This internal oscillator is mainly dedicated to provide a high precision clock to - * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. - * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency - * which is subject to manufacturing process variations. - */ -#if !defined (HSI48_VALUE) - #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. - The real value my vary depending on manufacturing process variations.*/ -#endif /* HSI48_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ - -/** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for SAI1 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source - * frequency. - */ -#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI1 External clock source in Hz*/ -#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ - -/** - * @brief External clock source for SAI2 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source - * frequency. - */ -#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)2097000U) /*!< Value of the SAI2 External clock source in Hz*/ -#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ - -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 0U -#define INSTRUCTION_CACHE_ENABLE 1U -#define DATA_CACHE_ENABLE 1U - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver - * Activated: CRC code is present inside driver - * Deactivated: CRC code cleaned from driver - */ - -#define USE_SPI_CRC 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32l4xx_hal_rcc.h" - #include "stm32l4xx_hal_rcc_ex.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32l4xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32l4xx_hal_dma.h" - #include "stm32l4xx_hal_dma_ex.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32l4xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32l4xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32l4xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32l4xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32l4xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32l4xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32l4xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32l4xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32l4xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32l4xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32l4xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_FIREWALL_MODULE_ENABLED - #include "stm32l4xx_hal_firewall.h" -#endif /* HAL_FIREWALL_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32l4xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32l4xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32l4xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32l4xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32l4xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l4xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l4xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l4xx_hal_lcd.h" -#endif /* HAL_LCD_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32l4xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32l4xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_OPAMP_MODULE_ENABLED - #include "stm32l4xx_hal_opamp.h" -#endif /* HAL_OPAMP_MODULE_ENABLED */ - -#ifdef HAL_OSPI_MODULE_ENABLED - #include "stm32l4xx_hal_ospi.h" -#endif /* HAL_OSPI_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l4xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32l4xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32l4xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l4xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32l4xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32l4xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32l4xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l4xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_SWPMI_MODULE_ENABLED - #include "stm32l4xx_hal_swpmi.h" -#endif /* HAL_SWPMI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l4xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_TSC_MODULE_ENABLED - #include "stm32l4xx_hal_tsc.h" -#endif /* HAL_TSC_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32l4xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32l4xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l4xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l4xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l4xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l4xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32l4xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_GFXMMU_MODULE_ENABLED - #include "stm32l4xx_hal_gfxmmu.h" -#endif /* HAL_GFXMMU_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_HAL_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/stm32l4xx_it.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/stm32l4xx_it.h deleted file mode 100644 index 574256a07..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/stm32l4xx_it.h +++ /dev/null @@ -1,67 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_it.h - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * - * COPYRIGHT(c) 2018 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L4xx_IT_H -#define __STM32L4xx_IT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" -#include "main.h" -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void SVC_Handler(void); -void DebugMon_Handler(void); -void PendSV_Handler(void); -void SysTick_Handler(void); -void OTG_FS_IRQHandler(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L4xx_IT_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/usb_device.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/usb_device.h deleted file mode 100644 index e5bad535e..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/usb_device.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - ****************************************************************************** - * @file : usb_device.h - * @version : v2.0_Cube - * @brief : Header for usb_device.c file. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_DEVICE__H__ -#define __USB_DEVICE__H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx.h" -#include "stm32l4xx_hal.h" -#include "usbd_def.h" - -/* USER CODE BEGIN INCLUDE */ -void MX_USB_DEVICE_DeInit(void); -/* USER CODE END INCLUDE */ - -/** @addtogroup USBD_OTG_DRIVER - * @{ - */ - -/** @defgroup USBD_DEVICE USBD_DEVICE - * @brief Device file for Usb otg low level driver. - * @{ - */ - -/** @defgroup USBD_DEVICE_Exported_Variables USBD_DEVICE_Exported_Variables - * @brief Public variables. - * @{ - */ - -/** USB device core handle. */ -extern USBD_HandleTypeDef hUsbDeviceFS; - -/** - * @} - */ - -/** @defgroup USBD_DEVICE_Exported_FunctionsPrototype USBD_DEVICE_Exported_FunctionsPrototype - * @brief Declaration of public functions for Usb device. - * @{ - */ - -/** USB Device initialization function. */ -void MX_USB_DEVICE_Init(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USB_DEVICE__H__ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/usbd_cdc_if.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/usbd_cdc_if.h deleted file mode 100644 index 2a4f7dad4..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/usbd_cdc_if.h +++ /dev/null @@ -1,158 +0,0 @@ -/** - ****************************************************************************** - * @file : usbd_cdc_if.h - * @version : v2.0_Cube - * @brief : Header for usbd_cdc_if.c file. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CDC_IF_H__ -#define __USBD_CDC_IF_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_cdc.h" - -/* USER CODE BEGIN INCLUDE */ - -/* USER CODE END INCLUDE */ - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @brief For Usb device. - * @{ - */ - -/** @defgroup USBD_CDC_IF USBD_CDC_IF - * @brief Usb VCP device module - * @{ - */ - -/** @defgroup USBD_CDC_IF_Exported_Defines USBD_CDC_IF_Exported_Defines - * @brief Defines. - * @{ - */ -/* USER CODE BEGIN EXPORTED_DEFINES */ - -/* USER CODE END EXPORTED_DEFINES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_Types USBD_CDC_IF_Exported_Types - * @brief Types. - * @{ - */ - -/* USER CODE BEGIN EXPORTED_TYPES */ - -/* USER CODE END EXPORTED_TYPES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_Macros USBD_CDC_IF_Exported_Macros - * @brief Aliases. - * @{ - */ - -/* USER CODE BEGIN EXPORTED_MACRO */ - -/* USER CODE END EXPORTED_MACRO */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables - * @brief Public variables. - * @{ - */ - -/** CDC Interface callback. */ -extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; - -/* USER CODE BEGIN EXPORTED_VARIABLES */ - -/* USER CODE END EXPORTED_VARIABLES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_FunctionsPrototype USBD_CDC_IF_Exported_FunctionsPrototype - * @brief Public functions declaration. - * @{ - */ - -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); - -/* USER CODE BEGIN EXPORTED_FUNCTIONS */ - -/* USER CODE END EXPORTED_FUNCTIONS */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_CDC_IF_H__ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/usbd_conf.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/usbd_conf.h deleted file mode 100644 index a884e818a..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/usbd_conf.h +++ /dev/null @@ -1,204 +0,0 @@ -/** - ****************************************************************************** - * @file : usbd_conf.h - * @version : v2.0_Cube - * @brief : Header for usbd_conf.c file. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CONF__H__ -#define __USBD_CONF__H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include -#include -#include -#include "stm32l4xx.h" -#include "stm32l4xx_hal.h" - -/* USER CODE BEGIN INCLUDE */ - -/* USER CODE END INCLUDE */ - -/** @addtogroup USBD_OTG_DRIVER - * @brief Driver for Usb device. - * @{ - */ - -/** @defgroup USBD_CONF USBD_CONF - * @brief Configuration file for Usb otg low level driver. - * @{ - */ - -/** @defgroup USBD_CONF_Exported_Variables USBD_CONF_Exported_Variables - * @brief Public variables. - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CONF_Exported_Defines USBD_CONF_Exported_Defines - * @brief Defines for configuration of the Usb device. - * @{ - */ - -/*---------- -----------*/ -#define USBD_MAX_NUM_INTERFACES 1 -/*---------- -----------*/ -#define USBD_MAX_NUM_CONFIGURATION 1 -/*---------- -----------*/ -#define USBD_MAX_STR_DESC_SIZ 512 -/*---------- -----------*/ -#define USBD_SUPPORT_USER_STRING 0 -/*---------- -----------*/ -#define USBD_DEBUG_LEVEL 0 -/*---------- -----------*/ -#define USBD_LPM_ENABLED 1 -/*---------- -----------*/ -#define USBD_SELF_POWERED 1 - -/****************************************/ -/* #define for FS and HS identification */ -#define DEVICE_FS 0 - -/** - * @} - */ - -/** @defgroup USBD_CONF_Exported_Macros USBD_CONF_Exported_Macros - * @brief Aliases. - * @{ - */ - -/* Memory management macros */ - -/** Alias for memory allocation. */ -#define USBD_malloc (uint32_t *)USBD_static_malloc - -/** Alias for memory release. */ -#define USBD_free USBD_static_free - -/** Alias for memory set. */ -#define USBD_memset /* Not used */ - -/** Alias for memory copy. */ -#define USBD_memcpy /* Not used */ - -/** Alias for delay. */ -#define USBD_Delay HAL_Delay - -/* DEBUG macros */ - -#if (USBD_DEBUG_LEVEL > 0) -#define USBD_UsrLog(...) printf(__VA_ARGS__);\ - printf("\n"); -#else -#define USBD_UsrLog(...) -#endif - -#if (USBD_DEBUG_LEVEL > 1) - -#define USBD_ErrLog(...) printf("ERROR: ") ;\ - printf(__VA_ARGS__);\ - printf("\n"); -#else -#define USBD_ErrLog(...) -#endif - -#if (USBD_DEBUG_LEVEL > 2) -#define USBD_DbgLog(...) printf("DEBUG : ") ;\ - printf(__VA_ARGS__);\ - printf("\n"); -#else -#define USBD_DbgLog(...) -#endif - -/** - * @} - */ - -/** @defgroup USBD_CONF_Exported_Types USBD_CONF_Exported_Types - * @brief Types. - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CONF_Exported_FunctionsPrototype USBD_CONF_Exported_FunctionsPrototype - * @brief Declaration of public functions for Usb device. - * @{ - */ - -/* Exported functions -------------------------------------------------------*/ -void *USBD_static_malloc(uint32_t size); -void USBD_static_free(void *p); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_CONF__H__ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/usbd_desc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/usbd_desc.h deleted file mode 100644 index fb856014f..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Inc/usbd_desc.h +++ /dev/null @@ -1,156 +0,0 @@ -/** - ****************************************************************************** - * @file : usbd_desc.h - * @version : v2.0_Cube - * @brief : Header for usbd_desc.c file. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_DESC__H__ -#define __USBD_DESC__H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - -/* USER CODE BEGIN INCLUDE */ - -/* USER CODE END INCLUDE */ - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_DESC USBD_DESC - * @brief Usb device descriptors module. - * @{ - */ - -/** @defgroup USBD_DESC_Exported_Defines USBD_DESC_Exported_Defines - * @brief Defines. - * @{ - */ - -/* USER CODE BEGIN EXPORTED_DEFINES */ - -/* USER CODE END EXPORTED_DEFINES */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_TypesDefinitions USBD_DESC_Exported_TypesDefinitions - * @brief Types. - * @{ - */ - -/* USER CODE BEGIN EXPORTED_TYPES */ - -/* USER CODE END EXPORTED_TYPES */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_Macros USBD_DESC_Exported_Macros - * @brief Aliases. - * @{ - */ - -/* USER CODE BEGIN EXPORTED_MACRO */ - -/* USER CODE END EXPORTED_MACRO */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_Variables USBD_DESC_Exported_Variables - * @brief Public variables. - * @{ - */ - -/** Descriptor for the Usb device. */ -extern USBD_DescriptorsTypeDef FS_Desc; - -/* USER CODE BEGIN EXPORTED_VARIABLES */ - -/* USER CODE END EXPORTED_VARIABLES */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_FunctionsPrototype USBD_DESC_Exported_FunctionsPrototype - * @brief Public functions declaration. - * @{ - */ - -/* USER CODE BEGIN EXPORTED_FUNCTIONS */ - -/* USER CODE END EXPORTED_FUNCTIONS */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_DESC__H__ */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h deleted file mode 100644 index d937b2e81..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h +++ /dev/null @@ -1,179 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_cdc.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief header file for the usbd_cdc.c file. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2015 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_CDC_H -#define __USB_CDC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup usbd_cdc - * @brief This file is the Header file for usbd_cdc.c - * @{ - */ - - -/** @defgroup usbd_cdc_Exported_Defines - * @{ - */ -#define CDC_IN_EP 0x81 /* EP1 for data IN */ -#define CDC_OUT_EP 0x01 /* EP1 for data OUT */ -#define CDC_CMD_EP 0x82 /* EP2 for CDC commands */ - -/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ -#define CDC_DATA_HS_MAX_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */ -#define CDC_DATA_FS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ -#define CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */ - -#define USB_CDC_CONFIG_DESC_SIZ 67 -#define CDC_DATA_HS_IN_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE -#define CDC_DATA_HS_OUT_PACKET_SIZE CDC_DATA_HS_MAX_PACKET_SIZE - -#define CDC_DATA_FS_IN_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE -#define CDC_DATA_FS_OUT_PACKET_SIZE CDC_DATA_FS_MAX_PACKET_SIZE - -/*---------------------------------------------------------------------*/ -/* CDC definitions */ -/*---------------------------------------------------------------------*/ -#define CDC_SEND_ENCAPSULATED_COMMAND 0x00 -#define CDC_GET_ENCAPSULATED_RESPONSE 0x01 -#define CDC_SET_COMM_FEATURE 0x02 -#define CDC_GET_COMM_FEATURE 0x03 -#define CDC_CLEAR_COMM_FEATURE 0x04 -#define CDC_SET_LINE_CODING 0x20 -#define CDC_GET_LINE_CODING 0x21 -#define CDC_SET_CONTROL_LINE_STATE 0x22 -#define CDC_SEND_BREAK 0x23 - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ - -/** - * @} - */ -typedef struct -{ - uint32_t bitrate; - uint8_t format; - uint8_t paritytype; - uint8_t datatype; -}USBD_CDC_LineCodingTypeDef; - -typedef struct _USBD_CDC_Itf -{ - int8_t (* Init) (void); - int8_t (* DeInit) (void); - int8_t (* Control) (uint8_t, uint8_t * , uint16_t); - int8_t (* Receive) (uint8_t *, uint32_t *); - -}USBD_CDC_ItfTypeDef; - - -typedef struct -{ - uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4]; /* Force 32bits alignment */ - uint8_t CmdOpCode; - uint8_t CmdLength; - uint8_t *RxBuffer; - uint8_t *TxBuffer; - uint32_t RxLength; - uint32_t TxLength; - - __IO uint32_t TxState; - __IO uint32_t RxState; -} -USBD_CDC_HandleTypeDef; - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern USBD_ClassTypeDef USBD_CDC; -#define USBD_CDC_CLASS &USBD_CDC -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, - USBD_CDC_ItfTypeDef *fops); - -uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff, - uint16_t length); - -uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff); - -uint8_t USBD_CDC_ReceivePacket (USBD_HandleTypeDef *pdev); - -uint8_t USBD_CDC_TransmitPacket (USBD_HandleTypeDef *pdev); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USB_CDC_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c deleted file mode 100644 index b2ca5f164..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c +++ /dev/null @@ -1,925 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_cdc.c - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief This file provides the high layer firmware functions to manage the - * following functionalities of the USB CDC Class: - * - Initialization and Configuration of high and low layer - * - Enumeration as CDC Device (and enumeration for each implemented memory interface) - * - OUT/IN data transfer - * - Command IN transfer (class requests management) - * - Error management - * - * @verbatim - * - * =================================================================== - * CDC Class Driver Description - * =================================================================== - * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices - * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus - * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007" - * This driver implements the following aspects of the specification: - * - Device descriptor management - * - Configuration descriptor management - * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN) - * - Requests management (as described in section 6.2 in specification) - * - Abstract Control Model compliant - * - Union Functional collection (using 1 IN endpoint for control) - * - Data interface class - * - * These aspects may be enriched or modified for a specific user application. - * - * This driver doesn't implement the following aspects of the specification - * (but it is possible to manage these features with some modifications on this driver): - * - Any class-specific aspect relative to communication classes should be managed by user application. - * - All communication classes other than PSTN are not managed - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2015 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_cdc.h" -#include "usbd_desc.h" -#include "usbd_ctlreq.h" - - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_CDC - * @brief usbd core module - * @{ - */ - -/** @defgroup USBD_CDC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_CDC_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_CDC_Private_Macros - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_CDC_Private_FunctionPrototypes - * @{ - */ - - -static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, - uint8_t epnum); - -static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, - uint8_t epnum); - -static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev); - -static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length); - -static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length); - -static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); - -static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length); - -uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length); - -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = -{ - USB_LEN_DEV_QUALIFIER_DESC, - USB_DESC_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x01, - 0x00, -}; - -/** - * @} - */ - -/** @defgroup USBD_CDC_Private_Variables - * @{ - */ - - -/* CDC interface class callbacks structure */ -USBD_ClassTypeDef USBD_CDC = -{ - USBD_CDC_Init, - USBD_CDC_DeInit, - USBD_CDC_Setup, - NULL, /* EP0_TxSent, */ - USBD_CDC_EP0_RxReady, - USBD_CDC_DataIn, - USBD_CDC_DataOut, - NULL, - NULL, - NULL, - USBD_CDC_GetHSCfgDesc, - USBD_CDC_GetFSCfgDesc, - USBD_CDC_GetOtherSpeedCfgDesc, - USBD_CDC_GetDeviceQualifierDescriptor, -}; - -/* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ - 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ - - /*---------------------------------------------------------------------------*/ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0x10, /* bInterval: */ - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; - - -/* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ - 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ - - /*---------------------------------------------------------------------------*/ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0x10, /* bInterval: */ - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; - -__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, - USB_CDC_CONFIG_DESC_SIZ, - 0x00, - 0x02, /* bNumInterfaces: 2 interfaces */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT , /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SIZE), - 0xFF, /* bInterval: */ - - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00 /* bInterval */ -}; - -/** - * @} - */ - -/** @defgroup USBD_CDC_Private_Functions - * @{ - */ - -/** - * @brief USBD_CDC_Init - * Initialize the CDC interface - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_CDC_Init (USBD_HandleTypeDef *pdev, - uint8_t cfgidx) -{ - uint8_t ret = 0; - USBD_CDC_HandleTypeDef *hcdc; - - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - /* Open EP IN */ - USBD_LL_OpenEP(pdev, - CDC_IN_EP, - USBD_EP_TYPE_BULK, - CDC_DATA_HS_IN_PACKET_SIZE); - - /* Open EP OUT */ - USBD_LL_OpenEP(pdev, - CDC_OUT_EP, - USBD_EP_TYPE_BULK, - CDC_DATA_HS_OUT_PACKET_SIZE); - - } - else - { - /* Open EP IN */ - USBD_LL_OpenEP(pdev, - CDC_IN_EP, - USBD_EP_TYPE_BULK, - CDC_DATA_FS_IN_PACKET_SIZE); - - /* Open EP OUT */ - USBD_LL_OpenEP(pdev, - CDC_OUT_EP, - USBD_EP_TYPE_BULK, - CDC_DATA_FS_OUT_PACKET_SIZE); - } - /* Open Command IN EP */ - USBD_LL_OpenEP(pdev, - CDC_CMD_EP, - USBD_EP_TYPE_INTR, - CDC_CMD_PACKET_SIZE); - - - pdev->pClassData = USBD_malloc(sizeof (USBD_CDC_HandleTypeDef)); - - if(pdev->pClassData == NULL) - { - ret = 1; - } - else - { - hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - /* Init physical Interface components */ - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); - - /* Init Xfer states */ - hcdc->TxState =0; - hcdc->RxState =0; - - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_HS_OUT_PACKET_SIZE); - } - else - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_FS_OUT_PACKET_SIZE); - } - - - } - return ret; -} - -/** - * @brief USBD_CDC_Init - * DeInitialize the CDC layer - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_CDC_DeInit (USBD_HandleTypeDef *pdev, - uint8_t cfgidx) -{ - uint8_t ret = 0; - - /* Open EP IN */ - USBD_LL_CloseEP(pdev, - CDC_IN_EP); - - /* Open EP OUT */ - USBD_LL_CloseEP(pdev, - CDC_OUT_EP); - - /* Open Command IN EP */ - USBD_LL_CloseEP(pdev, - CDC_CMD_EP); - - - /* DeInit physical Interface components */ - if(pdev->pClassData != NULL) - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); - USBD_free(pdev->pClassData); - pdev->pClassData = NULL; - } - - return ret; -} - -/** - * @brief USBD_CDC_Setup - * Handle the CDC specific requests - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t USBD_CDC_Setup (USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - static uint8_t ifalt = 0; - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - case USB_REQ_TYPE_CLASS : - if (req->wLength) - { - if (req->bmRequest & 0x80) - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, - (uint8_t *)hcdc->data, - req->wLength); - USBD_CtlSendData (pdev, - (uint8_t *)hcdc->data, - req->wLength); - } - else - { - hcdc->CmdOpCode = req->bRequest; - hcdc->CmdLength = req->wLength; - - USBD_CtlPrepareRx (pdev, - (uint8_t *)hcdc->data, - req->wLength); - } - - } - else - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, - (uint8_t*)req, - 0); - } - break; - - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - &ifalt, - 1); - break; - - case USB_REQ_SET_INTERFACE : - break; - } - - default: - break; - } - return USBD_OK; -} - -/** - * @brief USBD_CDC_DataIn - * Data sent on non-control IN endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - if(pdev->pClassData != NULL) - { - - hcdc->TxState = 0; - - return USBD_OK; - } - else - { - return USBD_FAIL; - } -} - -/** - * @brief USBD_CDC_DataOut - * Data received on non-control Out endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - /* Get the received data length */ - hcdc->RxLength = USBD_LL_GetRxDataSize (pdev, epnum); - - /* USB data will be immediately processed, this allow next USB traffic being - NAKed till the end of the application Xfer */ - if(pdev->pClassData != NULL) - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); - - return USBD_OK; - } - else - { - return USBD_FAIL; - } -} - - - -/** - * @brief USBD_CDC_DataOut - * Data received on non-control Out endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - if((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFF)) - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, - (uint8_t *)hcdc->data, - hcdc->CmdLength); - hcdc->CmdOpCode = 0xFF; - - } - return USBD_OK; -} - -/** - * @brief USBD_CDC_GetFSCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_CDC_GetFSCfgDesc (uint16_t *length) -{ - *length = sizeof (USBD_CDC_CfgFSDesc); - return USBD_CDC_CfgFSDesc; -} - -/** - * @brief USBD_CDC_GetHSCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_CDC_GetHSCfgDesc (uint16_t *length) -{ - *length = sizeof (USBD_CDC_CfgHSDesc); - return USBD_CDC_CfgHSDesc; -} - -/** - * @brief USBD_CDC_GetCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length) -{ - *length = sizeof (USBD_CDC_OtherSpeedCfgDesc); - return USBD_CDC_OtherSpeedCfgDesc; -} - -/** -* @brief DeviceQualifierDescriptor -* return Device Qualifier descriptor -* @param length : pointer data length -* @retval pointer to descriptor buffer -*/ -uint8_t *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length) -{ - *length = sizeof (USBD_CDC_DeviceQualifierDesc); - return USBD_CDC_DeviceQualifierDesc; -} - -/** -* @brief USBD_CDC_RegisterInterface - * @param pdev: device instance - * @param fops: CD Interface callback - * @retval status - */ -uint8_t USBD_CDC_RegisterInterface (USBD_HandleTypeDef *pdev, - USBD_CDC_ItfTypeDef *fops) -{ - uint8_t ret = USBD_FAIL; - - if(fops != NULL) - { - pdev->pUserData= fops; - ret = USBD_OK; - } - - return ret; -} - -/** - * @brief USBD_CDC_SetTxBuffer - * @param pdev: device instance - * @param pbuff: Tx Buffer - * @retval status - */ -uint8_t USBD_CDC_SetTxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff, - uint16_t length) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - hcdc->TxBuffer = pbuff; - hcdc->TxLength = length; - - return USBD_OK; -} - - -/** - * @brief USBD_CDC_SetRxBuffer - * @param pdev: device instance - * @param pbuff: Rx Buffer - * @retval status - */ -uint8_t USBD_CDC_SetRxBuffer (USBD_HandleTypeDef *pdev, - uint8_t *pbuff) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - hcdc->RxBuffer = pbuff; - - return USBD_OK; -} - -/** - * @brief USBD_CDC_DataOut - * Data received on non-control Out endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - if(pdev->pClassData != NULL) - { - if(hcdc->TxState == 0) - { - /* Tx Transfer in progress */ - hcdc->TxState = 1; - - /* Transmit next packet */ - USBD_LL_Transmit(pdev, - CDC_IN_EP, - hcdc->TxBuffer, - hcdc->TxLength); - - return USBD_OK; - } - else - { - return USBD_BUSY; - } - } - else - { - return USBD_FAIL; - } -} - - -/** - * @brief USBD_CDC_ReceivePacket - * prepare OUT Endpoint for reception - * @param pdev: device instance - * @retval status - */ -uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) -{ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData; - - /* Suspend or Resume USB Out process */ - if(pdev->pClassData != NULL) - { - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_HS_OUT_PACKET_SIZE); - } - else - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_FS_OUT_PACKET_SIZE); - } - return USBD_OK; - } - else - { - return USBD_FAIL; - } -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h deleted file mode 100644 index 013a5c14a..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h +++ /dev/null @@ -1,167 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_core.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief Header file for usbd_core.c file - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2015 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CORE_H -#define __USBD_CORE_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_conf.h" -#include "usbd_def.h" -#include "usbd_ioreq.h" -#include "usbd_ctlreq.h" - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_CORE - * @brief This file is the Header file for usbd_core.c file - * @{ - */ - - -/** @defgroup USBD_CORE_Exported_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ -#define USBD_SOF USBD_LL_SOF -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_FunctionsPrototype - * @{ - */ -USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id); -USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass); - -USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); -USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); - -USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup); -USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata); -USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata); - -USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed); -USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev); - -USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); -USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); - -USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev); - -/* USBD Low Level Driver */ -USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_DeInit (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Stop (USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_OpenEP (USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_mps); - -USBD_StatusTypeDef USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr); -USBD_StatusTypeDef USBD_LL_Transmit (USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t size); - -USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t size); - -uint32_t USBD_LL_GetRxDataSize (USBD_HandleTypeDef *pdev, uint8_t ep_addr); -void USBD_LL_Delay (uint32_t Delay); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_CORE_H */ - -/** - * @} - */ - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h deleted file mode 100644 index bf8825227..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_req.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief Header file for the usbd_req.c file - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2015 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_REQUEST_H -#define __USB_REQUEST_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_REQ - * @brief header file for the usbd_req.c file - * @{ - */ - -/** @defgroup USBD_REQ_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Exported_Types - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_REQ_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_REQ_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_REQ_Exported_FunctionsPrototype - * @{ - */ - -USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); - - -void USBD_CtlError (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); - -void USBD_ParseSetupRequest (USBD_SetupReqTypedef *req, uint8_t *pdata); - -void USBD_GetString (uint8_t *desc, uint8_t *unicode, uint16_t *len); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USB_REQUEST_H */ - -/** - * @} - */ - -/** -* @} -*/ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h deleted file mode 100644 index 8fbe81e4a..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h +++ /dev/null @@ -1,330 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_def.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief General defines for the usb device library - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2015 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_DEF_H -#define __USBD_DEF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_conf.h" - -/** @addtogroup STM32_USBD_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_DEF - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_DEF_Exported_Defines - * @{ - */ - -#ifndef NULL -#define NULL 0 -#endif - - -#define USB_LEN_DEV_QUALIFIER_DESC 0x0A -#define USB_LEN_DEV_DESC 0x12 -#define USB_LEN_CFG_DESC 0x09 -#define USB_LEN_IF_DESC 0x09 -#define USB_LEN_EP_DESC 0x07 -#define USB_LEN_OTG_DESC 0x03 -#define USB_LEN_LANGID_STR_DESC 0x04 -#define USB_LEN_OTHER_SPEED_DESC_SIZ 0x09 - -#define USBD_IDX_LANGID_STR 0x00 -#define USBD_IDX_MFC_STR 0x01 -#define USBD_IDX_PRODUCT_STR 0x02 -#define USBD_IDX_SERIAL_STR 0x03 -#define USBD_IDX_CONFIG_STR 0x04 -#define USBD_IDX_INTERFACE_STR 0x05 - -#define USB_REQ_TYPE_STANDARD 0x00 -#define USB_REQ_TYPE_CLASS 0x20 -#define USB_REQ_TYPE_VENDOR 0x40 -#define USB_REQ_TYPE_MASK 0x60 - -#define USB_REQ_RECIPIENT_DEVICE 0x00 -#define USB_REQ_RECIPIENT_INTERFACE 0x01 -#define USB_REQ_RECIPIENT_ENDPOINT 0x02 -#define USB_REQ_RECIPIENT_MASK 0x03 - -#define USB_REQ_GET_STATUS 0x00 -#define USB_REQ_CLEAR_FEATURE 0x01 -#define USB_REQ_SET_FEATURE 0x03 -#define USB_REQ_SET_ADDRESS 0x05 -#define USB_REQ_GET_DESCRIPTOR 0x06 -#define USB_REQ_SET_DESCRIPTOR 0x07 -#define USB_REQ_GET_CONFIGURATION 0x08 -#define USB_REQ_SET_CONFIGURATION 0x09 -#define USB_REQ_GET_INTERFACE 0x0A -#define USB_REQ_SET_INTERFACE 0x0B -#define USB_REQ_SYNCH_FRAME 0x0C - -#define USB_DESC_TYPE_DEVICE 1 -#define USB_DESC_TYPE_CONFIGURATION 2 -#define USB_DESC_TYPE_STRING 3 -#define USB_DESC_TYPE_INTERFACE 4 -#define USB_DESC_TYPE_ENDPOINT 5 -#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 -#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 -#define USB_DESC_TYPE_BOS 0x0F - -#define USB_CONFIG_REMOTE_WAKEUP 2 -#define USB_CONFIG_SELF_POWERED 1 - -#define USB_FEATURE_EP_HALT 0 -#define USB_FEATURE_REMOTE_WAKEUP 1 -#define USB_FEATURE_TEST_MODE 2 - -#define USB_DEVICE_CAPABITY_TYPE 0x10 - -#define USB_HS_MAX_PACKET_SIZE 512 -#define USB_FS_MAX_PACKET_SIZE 64 -#define USB_MAX_EP0_SIZE 64 - -/* Device Status */ -#define USBD_STATE_DEFAULT 1 -#define USBD_STATE_ADDRESSED 2 -#define USBD_STATE_CONFIGURED 3 -#define USBD_STATE_SUSPENDED 4 - - -/* EP0 State */ -#define USBD_EP0_IDLE 0 -#define USBD_EP0_SETUP 1 -#define USBD_EP0_DATA_IN 2 -#define USBD_EP0_DATA_OUT 3 -#define USBD_EP0_STATUS_IN 4 -#define USBD_EP0_STATUS_OUT 5 -#define USBD_EP0_STALL 6 - -#define USBD_EP_TYPE_CTRL 0 -#define USBD_EP_TYPE_ISOC 1 -#define USBD_EP_TYPE_BULK 2 -#define USBD_EP_TYPE_INTR 3 - - -/** - * @} - */ - - -/** @defgroup USBD_DEF_Exported_TypesDefinitions - * @{ - */ - -typedef struct usb_setup_req -{ - - uint8_t bmRequest; - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -}USBD_SetupReqTypedef; - -struct _USBD_HandleTypeDef; - -typedef struct _Device_cb -{ - uint8_t (*Init) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx); - uint8_t (*DeInit) (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx); - /* Control Endpoints*/ - uint8_t (*Setup) (struct _USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req); - uint8_t (*EP0_TxSent) (struct _USBD_HandleTypeDef *pdev ); - uint8_t (*EP0_RxReady) (struct _USBD_HandleTypeDef *pdev ); - /* Class Specific Endpoints*/ - uint8_t (*DataIn) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); - uint8_t (*DataOut) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); - uint8_t (*SOF) (struct _USBD_HandleTypeDef *pdev); - uint8_t (*IsoINIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); - uint8_t (*IsoOUTIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); - - uint8_t *(*GetHSConfigDescriptor)(uint16_t *length); - uint8_t *(*GetFSConfigDescriptor)(uint16_t *length); - uint8_t *(*GetOtherSpeedConfigDescriptor)(uint16_t *length); - uint8_t *(*GetDeviceQualifierDescriptor)(uint16_t *length); -#if (USBD_SUPPORT_USER_STRING == 1) - uint8_t *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev ,uint8_t index, uint16_t *length); -#endif - -} USBD_ClassTypeDef; - -/* Following USB Device Speed */ -typedef enum -{ - USBD_SPEED_HIGH = 0, - USBD_SPEED_FULL = 1, - USBD_SPEED_LOW = 2, -}USBD_SpeedTypeDef; - -/* Following USB Device status */ -typedef enum { - USBD_OK = 0, - USBD_BUSY, - USBD_FAIL, -}USBD_StatusTypeDef; - -/* USB Device descriptors structure */ -typedef struct -{ - uint8_t *(*GetDeviceDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetLangIDStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetManufacturerStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetProductStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetSerialStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetConfigurationStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); - uint8_t *(*GetInterfaceStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); -#if (USBD_LPM_ENABLED == 1) - uint8_t *(*GetBOSDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); -#endif -} USBD_DescriptorsTypeDef; - -/* USB Device handle structure */ -typedef struct -{ - uint32_t status; - uint32_t total_length; - uint32_t rem_length; - uint32_t maxpacket; -} USBD_EndpointTypeDef; - -/* USB Device handle structure */ -typedef struct _USBD_HandleTypeDef -{ - uint8_t id; - uint32_t dev_config; - uint32_t dev_default_config; - uint32_t dev_config_status; - USBD_SpeedTypeDef dev_speed; - USBD_EndpointTypeDef ep_in[15]; - USBD_EndpointTypeDef ep_out[15]; - uint32_t ep0_state; - uint32_t ep0_data_len; - uint8_t dev_state; - uint8_t dev_old_state; - uint8_t dev_address; - uint8_t dev_connection_status; - uint8_t dev_test_mode; - uint32_t dev_remote_wakeup; - - USBD_SetupReqTypedef request; - USBD_DescriptorsTypeDef *pDesc; - USBD_ClassTypeDef *pClass; - void *pClassData; - void *pUserData; - void *pData; -} USBD_HandleTypeDef; - -/** - * @} - */ - - - -/** @defgroup USBD_DEF_Exported_Macros - * @{ - */ -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) - -#define LOBYTE(x) ((uint8_t)(x & 0x00FF)) -#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8)) -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) - - -#if defined ( __GNUC__ ) - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ -#endif /* __GNUC__ */ - - -/* In HS mode and when the DMA is used, all variables and data structures dealing - with the DMA during the transaction process should be 4-bytes aligned */ - -#if defined (__GNUC__) /* GNU Compiler */ - #define __ALIGN_END __attribute__ ((aligned (4))) - #define __ALIGN_BEGIN -#else - #define __ALIGN_END - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #elif defined (__TASKING__) /* TASKING Compiler */ - #define __ALIGN_BEGIN __align(4) - #endif /* __CC_ARM */ -#endif /* __GNUC__ */ - - -/** - * @} - */ - -/** @defgroup USBD_DEF_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_DEF_Exported_FunctionsPrototype - * @{ - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_DEF_H */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h deleted file mode 100644 index b476307c5..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h +++ /dev/null @@ -1,128 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_ioreq.h - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief Header file for the usbd_ioreq.c file - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2015 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_IOREQ_H -#define __USBD_IOREQ_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" -#include "usbd_core.h" - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_IOREQ - * @brief header file for the usbd_ioreq.c file - * @{ - */ - -/** @defgroup USBD_IOREQ_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Exported_Types - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_IOREQ_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_IOREQ_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype - * @{ - */ - -USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, - uint8_t *buf, - uint16_t len); - -USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev); - -USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev); - -uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , - uint8_t epnum); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __USBD_IOREQ_H */ - -/** - * @} - */ - -/** -* @} -*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c deleted file mode 100644 index 0158829c5..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c +++ /dev/null @@ -1,565 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_core.c - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief This file provides all the USBD core functions. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2015 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" - -/** @addtogroup STM32_USBD_DEVICE_LIBRARY -* @{ -*/ - - -/** @defgroup USBD_CORE -* @brief usbd core module -* @{ -*/ - -/** @defgroup USBD_CORE_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBD_CORE_Private_Defines -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USBD_CORE_Private_Macros -* @{ -*/ -/** -* @} -*/ - - - - -/** @defgroup USBD_CORE_Private_FunctionPrototypes -* @{ -*/ - -/** -* @} -*/ - -/** @defgroup USBD_CORE_Private_Variables -* @{ -*/ - -/** -* @} -*/ - -/** @defgroup USBD_CORE_Private_Functions -* @{ -*/ - -/** -* @brief USBD_Init -* Initializes the device stack and load the class driver -* @param pdev: device instance -* @param pdesc: Descriptor structure address -* @param id: Low level core index -* @retval None -*/ -USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) -{ - /* Check whether the USB Host handle is valid */ - if(pdev == NULL) - { - USBD_ErrLog("Invalid Device handle"); - return USBD_FAIL; - } - - /* Unlink previous class*/ - if(pdev->pClass != NULL) - { - pdev->pClass = NULL; - } - - /* Assign USBD Descriptors */ - if(pdesc != NULL) - { - pdev->pDesc = pdesc; - } - - /* Set Device initial State */ - pdev->dev_state = USBD_STATE_DEFAULT; - pdev->id = id; - /* Initialize low level driver */ - USBD_LL_Init(pdev); - - return USBD_OK; -} - -/** -* @brief USBD_DeInit -* Re-Initialize th device library -* @param pdev: device instance -* @retval status: status -*/ -USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev) -{ - /* Set Default State */ - pdev->dev_state = USBD_STATE_DEFAULT; - - /* Free Class Resources */ - pdev->pClass->DeInit(pdev, pdev->dev_config); - - /* Stop the low level driver */ - USBD_LL_Stop(pdev); - - /* Initialize low level driver */ - USBD_LL_DeInit(pdev); - - return USBD_OK; -} - - -/** - * @brief USBD_RegisterClass - * Link class driver to Device Core. - * @param pDevice : Device Handle - * @param pclass: Class handle - * @retval USBD Status - */ -USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) -{ - USBD_StatusTypeDef status = USBD_OK; - if(pclass != 0) - { - /* link the class to the USB Device handle */ - pdev->pClass = pclass; - status = USBD_OK; - } - else - { - USBD_ErrLog("Invalid Class handle"); - status = USBD_FAIL; - } - - return status; -} - -/** - * @brief USBD_Start - * Start the USB Device Core. - * @param pdev: Device Handle - * @retval USBD Status - */ -USBD_StatusTypeDef USBD_Start (USBD_HandleTypeDef *pdev) -{ - - /* Start the low level driver */ - USBD_LL_Start(pdev); - - return USBD_OK; -} - -/** - * @brief USBD_Stop - * Stop the USB Device Core. - * @param pdev: Device Handle - * @retval USBD Status - */ -USBD_StatusTypeDef USBD_Stop (USBD_HandleTypeDef *pdev) -{ - /* Free Class Resources */ - pdev->pClass->DeInit(pdev, pdev->dev_config); - - /* Stop the low level driver */ - USBD_LL_Stop(pdev); - - return USBD_OK; -} - -/** -* @brief USBD_RunTestMode -* Launch test mode process -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef *pdev) -{ - return USBD_OK; -} - - -/** -* @brief USBD_SetClassConfig -* Configure device and start the interface -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status -*/ - -USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) -{ - USBD_StatusTypeDef ret = USBD_FAIL; - - if(pdev->pClass != NULL) - { - /* Set configuration and Start the Class*/ - if(pdev->pClass->Init(pdev, cfgidx) == 0) - { - ret = USBD_OK; - } - } - return ret; -} - -/** -* @brief USBD_ClrClassConfig -* Clear current configuration -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status: USBD_StatusTypeDef -*/ -USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) -{ - /* Clear configuration and De-initialize the Class process*/ - pdev->pClass->DeInit(pdev, cfgidx); - return USBD_OK; -} - - -/** -* @brief USBD_SetupStage -* Handle the setup stage -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) -{ - - USBD_ParseSetupRequest(&pdev->request, psetup); - - pdev->ep0_state = USBD_EP0_SETUP; - pdev->ep0_data_len = pdev->request.wLength; - - switch (pdev->request.bmRequest & 0x1F) - { - case USB_REQ_RECIPIENT_DEVICE: - USBD_StdDevReq (pdev, &pdev->request); - break; - - case USB_REQ_RECIPIENT_INTERFACE: - USBD_StdItfReq(pdev, &pdev->request); - break; - - case USB_REQ_RECIPIENT_ENDPOINT: - USBD_StdEPReq(pdev, &pdev->request); - break; - - default: - USBD_LL_StallEP(pdev , pdev->request.bmRequest & 0x80); - break; - } - return USBD_OK; -} - -/** -* @brief USBD_DataOutStage -* Handle data OUT stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata) -{ - USBD_EndpointTypeDef *pep; - - if(epnum == 0) - { - pep = &pdev->ep_out[0]; - - if ( pdev->ep0_state == USBD_EP0_DATA_OUT) - { - if(pep->rem_length > pep->maxpacket) - { - pep->rem_length -= pep->maxpacket; - - USBD_CtlContinueRx (pdev, - pdata, - MIN(pep->rem_length ,pep->maxpacket)); - } - else - { - if((pdev->pClass->EP0_RxReady != NULL)&& - (pdev->dev_state == USBD_STATE_CONFIGURED)) - { - pdev->pClass->EP0_RxReady(pdev); - } - USBD_CtlSendStatus(pdev); - } - } - } - else if((pdev->pClass->DataOut != NULL)&& - (pdev->dev_state == USBD_STATE_CONFIGURED)) - { - pdev->pClass->DataOut(pdev, epnum); - } - return USBD_OK; -} - -/** -* @brief USBD_DataInStage -* Handle data in stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev ,uint8_t epnum, uint8_t *pdata) -{ - USBD_EndpointTypeDef *pep; - - if(epnum == 0) - { - pep = &pdev->ep_in[0]; - - if ( pdev->ep0_state == USBD_EP0_DATA_IN) - { - if(pep->rem_length > pep->maxpacket) - { - pep->rem_length -= pep->maxpacket; - - USBD_CtlContinueSendData (pdev, - pdata, - pep->rem_length); - - /* Prepare endpoint for premature end of transfer */ - USBD_LL_PrepareReceive (pdev, - 0, - NULL, - 0); - } - else - { /* last packet is MPS multiple, so send ZLP packet */ - if((pep->total_length % pep->maxpacket == 0) && - (pep->total_length >= pep->maxpacket) && - (pep->total_length < pdev->ep0_data_len )) - { - - USBD_CtlContinueSendData(pdev , NULL, 0); - pdev->ep0_data_len = 0; - - /* Prepare endpoint for premature end of transfer */ - USBD_LL_PrepareReceive (pdev, - 0, - NULL, - 0); - } - else - { - if((pdev->pClass->EP0_TxSent != NULL)&& - (pdev->dev_state == USBD_STATE_CONFIGURED)) - { - pdev->pClass->EP0_TxSent(pdev); - } - USBD_CtlReceiveStatus(pdev); - } - } - } - if (pdev->dev_test_mode == 1) - { - USBD_RunTestMode(pdev); - pdev->dev_test_mode = 0; - } - } - else if((pdev->pClass->DataIn != NULL)&& - (pdev->dev_state == USBD_STATE_CONFIGURED)) - { - pdev->pClass->DataIn(pdev, epnum); - } - return USBD_OK; -} - -/** -* @brief USBD_LL_Reset -* Handle Reset event -* @param pdev: device instance -* @retval status -*/ - -USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) -{ - /* Open EP0 OUT */ - USBD_LL_OpenEP(pdev, - 0x00, - USBD_EP_TYPE_CTRL, - USB_MAX_EP0_SIZE); - - pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; - - /* Open EP0 IN */ - USBD_LL_OpenEP(pdev, - 0x80, - USBD_EP_TYPE_CTRL, - USB_MAX_EP0_SIZE); - - pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; - /* Upon Reset call user call back */ - pdev->dev_state = USBD_STATE_DEFAULT; - - if (pdev->pClassData) - pdev->pClass->DeInit(pdev, pdev->dev_config); - - - return USBD_OK; -} - - - - -/** -* @brief USBD_LL_Reset -* Handle Reset event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed) -{ - pdev->dev_speed = speed; - return USBD_OK; -} - -/** -* @brief USBD_Suspend -* Handle Suspend event -* @param pdev: device instance -* @retval status -*/ - -USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) -{ - pdev->dev_old_state = pdev->dev_state; - pdev->dev_state = USBD_STATE_SUSPENDED; - return USBD_OK; -} - -/** -* @brief USBD_Resume -* Handle Resume event -* @param pdev: device instance -* @retval status -*/ - -USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev) -{ - pdev->dev_state = pdev->dev_old_state; - return USBD_OK; -} - -/** -* @brief USBD_SOF -* Handle SOF event -* @param pdev: device instance -* @retval status -*/ - -USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev) -{ - if(pdev->dev_state == USBD_STATE_CONFIGURED) - { - if(pdev->pClass->SOF != NULL) - { - pdev->pClass->SOF(pdev); - } - } - return USBD_OK; -} - -/** -* @brief USBD_IsoINIncomplete -* Handle iso in incomplete event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - return USBD_OK; -} - -/** -* @brief USBD_IsoOUTIncomplete -* Handle iso out incomplete event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - return USBD_OK; -} - -/** -* @brief USBD_DevConnected -* Handle device connection event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev) -{ - return USBD_OK; -} - -/** -* @brief USBD_DevDisconnected -* Handle device disconnection event -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) -{ - /* Free Class Resources */ - pdev->dev_state = USBD_STATE_DEFAULT; - pdev->pClass->DeInit(pdev, pdev->dev_config); - - return USBD_OK; -} -/** -* @} -*/ - - -/** -* @} -*/ - - -/** -* @} -*/ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c deleted file mode 100644 index 49330c667..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c +++ /dev/null @@ -1,782 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_req.c - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief This file provides the standard USB requests following chapter 9. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2015 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ctlreq.h" -#include "usbd_ioreq.h" - - -/** @addtogroup STM32_USBD_STATE_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_REQ - * @brief USB standard requests module - * @{ - */ - -/** @defgroup USBD_REQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_FunctionPrototypes - * @{ - */ -static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_SetAddress(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_SetConfig(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_GetConfig(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_GetStatus(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_SetFeature(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static void USBD_ClrFeature(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req); - -static uint8_t USBD_GetLen(uint8_t *buf); - -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Functions - * @{ - */ - - -/** -* @brief USBD_StdDevReq -* Handle standard usb device requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -USBD_StatusTypeDef USBD_StdDevReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req) -{ - USBD_StatusTypeDef ret = USBD_OK; - - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - - USBD_GetDescriptor (pdev, req) ; - break; - - case USB_REQ_SET_ADDRESS: - USBD_SetAddress(pdev, req); - break; - - case USB_REQ_SET_CONFIGURATION: - USBD_SetConfig (pdev , req); - break; - - case USB_REQ_GET_CONFIGURATION: - USBD_GetConfig (pdev , req); - break; - - case USB_REQ_GET_STATUS: - USBD_GetStatus (pdev , req); - break; - - - case USB_REQ_SET_FEATURE: - USBD_SetFeature (pdev , req); - break; - - case USB_REQ_CLEAR_FEATURE: - USBD_ClrFeature (pdev , req); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - - return ret; -} - -/** -* @brief USBD_StdItfReq -* Handle standard usb interface requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -USBD_StatusTypeDef USBD_StdItfReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req) -{ - USBD_StatusTypeDef ret = USBD_OK; - - switch (pdev->dev_state) - { - case USBD_STATE_CONFIGURED: - - if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) - { - pdev->pClass->Setup (pdev, req); - - if((req->wLength == 0)&& (ret == USBD_OK)) - { - USBD_CtlSendStatus(pdev); - } - } - else - { - USBD_CtlError(pdev , req); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - return USBD_OK; -} - -/** -* @brief USBD_StdEPReq -* Handle standard usb endpoint requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -USBD_StatusTypeDef USBD_StdEPReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef *req) -{ - - uint8_t ep_addr; - USBD_StatusTypeDef ret = USBD_OK; - USBD_EndpointTypeDef *pep; - ep_addr = LOBYTE(req->wIndex); - - /* Check if it is a class request */ - if ((req->bmRequest & 0x60) == 0x20) - { - pdev->pClass->Setup (pdev, req); - - return USBD_OK; - } - - switch (req->bRequest) - { - - case USB_REQ_SET_FEATURE : - - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - USBD_LL_StallEP(pdev , ep_addr); - } - break; - - case USBD_STATE_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - USBD_LL_StallEP(pdev , ep_addr); - - } - } - pdev->pClass->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - case USB_REQ_CLEAR_FEATURE : - - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - USBD_LL_StallEP(pdev , ep_addr); - } - break; - - case USBD_STATE_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr & 0x7F) != 0x00) - { - USBD_LL_ClearStallEP(pdev , ep_addr); - pdev->pClass->Setup (pdev, req); - } - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - case USB_REQ_GET_STATUS: - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if ((ep_addr & 0x7F) != 0x00) - { - USBD_LL_StallEP(pdev , ep_addr); - } - break; - - case USBD_STATE_CONFIGURED: - pep = ((ep_addr & 0x80) == 0x80) ? &pdev->ep_in[ep_addr & 0x7F]:\ - &pdev->ep_out[ep_addr & 0x7F]; - if(USBD_LL_IsStallEP(pdev, ep_addr)) - { - pep->status = 0x0001; - } - else - { - pep->status = 0x0000; - } - - USBD_CtlSendData (pdev, - (uint8_t *)&pep->status, - 2); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - default: - break; - } - return ret; -} -/** -* @brief USBD_GetDescriptor -* Handle Get Descriptor requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - uint16_t len; - uint8_t *pbuf; - - - switch (req->wValue >> 8) - { -#if (USBD_LPM_ENABLED == 1) - case USB_DESC_TYPE_BOS: - pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); - break; -#endif - case USB_DESC_TYPE_DEVICE: - pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); - break; - - case USB_DESC_TYPE_CONFIGURATION: - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - pbuf = (uint8_t *)pdev->pClass->GetHSConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_CONFIGURATION; - } - else - { - pbuf = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_CONFIGURATION; - } - break; - - case USB_DESC_TYPE_STRING: - switch ((uint8_t)(req->wValue)) - { - case USBD_IDX_LANGID_STR: - pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_MFC_STR: - pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_PRODUCT_STR: - pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_SERIAL_STR: - pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_CONFIG_STR: - pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); - break; - - case USBD_IDX_INTERFACE_STR: - pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); - break; - - default: -#if (USBD_SUPPORT_USER_STRING == 1) - pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue) , &len); - break; -#else - USBD_CtlError(pdev , req); - return; -#endif - } - break; - case USB_DESC_TYPE_DEVICE_QUALIFIER: - - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - pbuf = (uint8_t *)pdev->pClass->GetDeviceQualifierDescriptor(&len); - break; - } - else - { - USBD_CtlError(pdev , req); - return; - } - - case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: - if(pdev->dev_speed == USBD_SPEED_HIGH ) - { - pbuf = (uint8_t *)pdev->pClass->GetOtherSpeedConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; - break; - } - else - { - USBD_CtlError(pdev , req); - return; - } - - default: - USBD_CtlError(pdev , req); - return; - } - - if((len != 0)&& (req->wLength != 0)) - { - - len = MIN(len , req->wLength); - - USBD_CtlSendData (pdev, - pbuf, - len); - } - -} - -/** -* @brief USBD_SetAddress -* Set device address -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetAddress(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - uint8_t dev_addr; - - if ((req->wIndex == 0) && (req->wLength == 0)) - { - dev_addr = (uint8_t)(req->wValue) & 0x7F; - - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlError(pdev , req); - } - else - { - pdev->dev_address = dev_addr; - USBD_LL_SetUSBAddress(pdev, dev_addr); - USBD_CtlSendStatus(pdev); - - if (dev_addr != 0) - { - pdev->dev_state = USBD_STATE_ADDRESSED; - } - else - { - pdev->dev_state = USBD_STATE_DEFAULT; - } - } - } - else - { - USBD_CtlError(pdev , req); - } -} - -/** -* @brief USBD_SetConfig -* Handle Set device configuration request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetConfig(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - - if (cfgidx > USBD_MAX_NUM_CONFIGURATION ) - { - USBD_CtlError(pdev , req); - } - else - { - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - if (cfgidx) - { - pdev->dev_config = cfgidx; - pdev->dev_state = USBD_STATE_CONFIGURED; - if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL) - { - USBD_CtlError(pdev , req); - return; - } - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - case USBD_STATE_CONFIGURED: - if (cfgidx == 0) - { - pdev->dev_state = USBD_STATE_ADDRESSED; - pdev->dev_config = cfgidx; - USBD_ClrClassConfig(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - - } - else if (cfgidx != pdev->dev_config) - { - /* Clear old configuration */ - USBD_ClrClassConfig(pdev , pdev->dev_config); - - /* set new configuration */ - pdev->dev_config = cfgidx; - if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL) - { - USBD_CtlError(pdev , req); - return; - } - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - } -} - -/** -* @brief USBD_GetConfig -* Handle Get device configuration request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetConfig(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - - if (req->wLength != 1) - { - USBD_CtlError(pdev , req); - } - else - { - switch (pdev->dev_state ) - { - case USBD_STATE_ADDRESSED: - pdev->dev_default_config = 0; - USBD_CtlSendData (pdev, - (uint8_t *)&pdev->dev_default_config, - 1); - break; - - case USBD_STATE_CONFIGURED: - - USBD_CtlSendData (pdev, - (uint8_t *)&pdev->dev_config, - 1); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - } -} - -/** -* @brief USBD_GetStatus -* Handle Get Status request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetStatus(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - - - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - case USBD_STATE_CONFIGURED: - -#if ( USBD_SELF_POWERED == 1) - pdev->dev_config_status = USB_CONFIG_SELF_POWERED; -#else - pdev->dev_config_status = 0; -#endif - - if (pdev->dev_remote_wakeup) - { - pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; - } - - USBD_CtlSendData (pdev, - (uint8_t *)& pdev->dev_config_status, - 2); - break; - - default : - USBD_CtlError(pdev , req); - break; - } -} - - -/** -* @brief USBD_SetFeature -* Handle Set device feature request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetFeature(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - - if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) - { - pdev->dev_remote_wakeup = 1; - pdev->pClass->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - } - -} - - -/** -* @brief USBD_ClrFeature -* Handle clear device feature request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_ClrFeature(USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - switch (pdev->dev_state) - { - case USBD_STATE_ADDRESSED: - case USBD_STATE_CONFIGURED: - if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) - { - pdev->dev_remote_wakeup = 0; - pdev->pClass->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - } - break; - - default : - USBD_CtlError(pdev , req); - break; - } -} - -/** -* @brief USBD_ParseSetupRequest -* Copy buffer into setup structure -* @param pdev: device instance -* @param req: usb request -* @retval None -*/ - -void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) -{ - req->bmRequest = *(uint8_t *) (pdata); - req->bRequest = *(uint8_t *) (pdata + 1); - req->wValue = SWAPBYTE (pdata + 2); - req->wIndex = SWAPBYTE (pdata + 4); - req->wLength = SWAPBYTE (pdata + 6); - -} - -/** -* @brief USBD_CtlError -* Handle USB low level Error -* @param pdev: device instance -* @param req: usb request -* @retval None -*/ - -void USBD_CtlError( USBD_HandleTypeDef *pdev , - USBD_SetupReqTypedef *req) -{ - USBD_LL_StallEP(pdev , 0x80); - USBD_LL_StallEP(pdev , 0); -} - - -/** - * @brief USBD_GetString - * Convert Ascii string into unicode one - * @param desc : descriptor buffer - * @param unicode : Formatted string buffer (unicode) - * @param len : descriptor length - * @retval None - */ -void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) -{ - uint8_t idx = 0; - - if (desc != NULL) - { - *len = USBD_GetLen(desc) * 2 + 2; - unicode[idx++] = *len; - unicode[idx++] = USB_DESC_TYPE_STRING; - - while (*desc != '\0') - { - unicode[idx++] = *desc++; - unicode[idx++] = 0x00; - } - } -} - -/** - * @brief USBD_GetLen - * return the string length - * @param buf : pointer to the ascii string buffer - * @retval string length - */ -static uint8_t USBD_GetLen(uint8_t *buf) -{ - uint8_t len = 0; - - while (*buf != '\0') - { - len++; - buf++; - } - - return len; -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c deleted file mode 100644 index 093afad86..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c +++ /dev/null @@ -1,236 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_ioreq.c - * @author MCD Application Team - * @version V2.4.2 - * @date 11-December-2015 - * @brief This file provides the IO requests APIs for control endpoints. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT 2015 STMicroelectronics

    - * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_IOREQ - * @brief control I/O requests module - * @{ - */ - -/** @defgroup USBD_IOREQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Functions - * @{ - */ - -/** -* @brief USBD_CtlSendData -* send data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be sent -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlSendData (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len) -{ - /* Set EP0 State */ - pdev->ep0_state = USBD_EP0_DATA_IN; - pdev->ep_in[0].total_length = len; - pdev->ep_in[0].rem_length = len; - /* Start the transfer */ - USBD_LL_Transmit (pdev, 0x00, pbuf, len); - - return USBD_OK; -} - -/** -* @brief USBD_CtlContinueSendData -* continue sending data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be sent -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlContinueSendData (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len) -{ - /* Start the next transfer */ - USBD_LL_Transmit (pdev, 0x00, pbuf, len); - - return USBD_OK; -} - -/** -* @brief USBD_CtlPrepareRx -* receive data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be received -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len) -{ - /* Set EP0 State */ - pdev->ep0_state = USBD_EP0_DATA_OUT; - pdev->ep_out[0].total_length = len; - pdev->ep_out[0].rem_length = len; - /* Start the transfer */ - USBD_LL_PrepareReceive (pdev, - 0, - pbuf, - len); - - return USBD_OK; -} - -/** -* @brief USBD_CtlContinueRx -* continue receive data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be received -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlContinueRx (USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len) -{ - - USBD_LL_PrepareReceive (pdev, - 0, - pbuf, - len); - return USBD_OK; -} -/** -* @brief USBD_CtlSendStatus -* send zero lzngth packet on the ctl pipe -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlSendStatus (USBD_HandleTypeDef *pdev) -{ - - /* Set EP0 State */ - pdev->ep0_state = USBD_EP0_STATUS_IN; - - /* Start the transfer */ - USBD_LL_Transmit (pdev, 0x00, NULL, 0); - - return USBD_OK; -} - -/** -* @brief USBD_CtlReceiveStatus -* receive zero lzngth packet on the ctl pipe -* @param pdev: device instance -* @retval status -*/ -USBD_StatusTypeDef USBD_CtlReceiveStatus (USBD_HandleTypeDef *pdev) -{ - /* Set EP0 State */ - pdev->ep0_state = USBD_EP0_STATUS_OUT; - - /* Start the transfer */ - USBD_LL_PrepareReceive ( pdev, - 0, - NULL, - 0); - - return USBD_OK; -} - - -/** -* @brief USBD_GetRxCount -* returns the received data length -* @param pdev: device instance -* @param ep_addr: endpoint address -* @retval Rx Data blength -*/ -uint16_t USBD_GetRxCount (USBD_HandleTypeDef *pdev , uint8_t ep_addr) -{ - return USBD_LL_GetRxDataSize(pdev, ep_addr); -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Nucleo-L4A6RG.elf.launch b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Nucleo-L4A6RG.elf.launch deleted file mode 100644 index 8f4f1aefd..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Nucleo-L4A6RG.elf.launch +++ /dev/null @@ -1,67 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Nucleo-L4A6RG.ioc b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Nucleo-L4A6RG.ioc deleted file mode 100644 index 482a7ac93..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Nucleo-L4A6RG.ioc +++ /dev/null @@ -1,192 +0,0 @@ -#MicroXplorer Configuration settings - do not modify -File.Version=6 -KeepUserPlacement=false -Mcu.Family=STM32L4 -Mcu.IP0=NVIC -Mcu.IP1=RCC -Mcu.IP2=RNG -Mcu.IP3=RTC -Mcu.IP4=SYS -Mcu.IP5=USART2 -Mcu.IP6=USB_DEVICE -Mcu.IP7=USB_OTG_FS -Mcu.IPNb=8 -Mcu.Name=STM32L4A6RGTx -Mcu.Package=LQFP64 -Mcu.Pin0=PC13 -Mcu.Pin1=PC14-OSC32_IN (PC14) -Mcu.Pin10=PB3 (JTDO/TRACESWO) -Mcu.Pin11=VP_RNG_VS_RNG -Mcu.Pin12=VP_RTC_VS_RTC_Activate -Mcu.Pin13=VP_RTC_VS_RTC_Calendar -Mcu.Pin14=VP_SYS_VS_Systick -Mcu.Pin15=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS -Mcu.Pin2=PC15-OSC32_OUT (PC15) -Mcu.Pin3=PA2 -Mcu.Pin4=PA3 -Mcu.Pin5=PA5 -Mcu.Pin6=PA11 -Mcu.Pin7=PA12 -Mcu.Pin8=PA13 (JTMS/SWDIO) -Mcu.Pin9=PA14 (JTCK/SWCLK) -Mcu.PinsNb=16 -Mcu.ThirdPartyNb=0 -Mcu.UserConstants= -Mcu.UserName=STM32L4A6RGTx -MxCube.Version=4.25.0 -MxDb.Version=DB.4.0.250 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false -PA11.Mode=Device_Only -PA11.Signal=USB_OTG_FS_DM -PA12.Mode=Device_Only -PA12.Signal=USB_OTG_FS_DP -PA13\ (JTMS/SWDIO).Mode=Trace_Asynchronous_SW -PA13\ (JTMS/SWDIO).Signal=SYS_JTMS-SWDIO -PA14\ (JTCK/SWCLK).Mode=Trace_Asynchronous_SW -PA14\ (JTCK/SWCLK).Signal=SYS_JTCK-SWCLK -PA2.Mode=Asynchronous -PA2.Signal=USART2_TX -PA3.Mode=Asynchronous -PA3.Signal=USART2_RX -PA5.GPIOParameters=GPIO_Label -PA5.GPIO_Label=LD2 [green Led] -PA5.Locked=true -PA5.Signal=GPIO_Output -PB3\ (JTDO/TRACESWO).Mode=Trace_Asynchronous_SW -PB3\ (JTDO/TRACESWO).Signal=SYS_JTDO-SWO -PC13.GPIOParameters=GPIO_Label -PC13.GPIO_Label=B1 [Blue PushButton] -PC13.Locked=true -PC13.Signal=GPXTI13 -PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator -PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN -PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator -PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT -PCC.Checker=true -PCC.Line=STM32L4x6 -PCC.MCU=STM32L4A6RGTx -PCC.PartNumber=STM32L4A6RGTx -PCC.Seq0=0 -PCC.Series=STM32L4 -PCC.Temperature=25 -PCC.Vdd=null -PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=true -ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=3 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=false -ProjectManager.CustomerFirmwarePackage=C\:/Users/Stefanth/STM32Cube/Repository/STM32Cube_FW_L4_V1.11.0 -ProjectManager.DefaultFWLocation=true -ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32L4A6RGTx -ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.11.0 -ProjectManager.FreePins=false -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x200 -ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=1 -ProjectManager.MainLocation=Src -ProjectManager.PreviousToolchain=TrueSTUDIO -ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=Nucleo-L4A6RG.ioc -ProjectManager.ProjectName=Nucleo-L4A6RG -ProjectManager.StackSize=0x10000 -ProjectManager.TargetToolchain=TrueSTUDIO -ProjectManager.ToolChainLocation= -ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART2_UART_Init-USART2-false-HAL-true,4-MX_RTC_Init-RTC-false-HAL-true,5-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-true,6-MX_RNG_Init-RNG-false-HAL-true -RCC.ADCFreq_Value=64000000 -RCC.AHBFreq_Value=80000000 -RCC.APB1Freq_Value=80000000 -RCC.APB1TimFreq_Value=80000000 -RCC.APB2Freq_Value=80000000 -RCC.APB2TimFreq_Value=80000000 -RCC.CK48CLockSelection=RCC_USBCLKSOURCE_HSI48 -RCC.CortexFreq_Value=80000000 -RCC.DFSDMFreq_Value=80000000 -RCC.FCLKCortexFreq_Value=80000000 -RCC.FamilyName=M -RCC.HCLKFreq_Value=80000000 -RCC.HSE_VALUE=8000000 -RCC.HSI48_VALUE=48000000 -RCC.HSI_VALUE=16000000 -RCC.I2C1Freq_Value=80000000 -RCC.I2C2Freq_Value=80000000 -RCC.I2C3Freq_Value=80000000 -RCC.I2C4Freq_Value=80000000 -RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CK48CLockSelection,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,LCDFreq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value -RCC.LCDFreq_Value=32768 -RCC.LPTIM1Freq_Value=80000000 -RCC.LPTIM2Freq_Value=80000000 -RCC.LPUART1Freq_Value=80000000 -RCC.LSCOPinFreq_Value=32000 -RCC.LSI_VALUE=32000 -RCC.MCO1PinFreq_Value=80000000 -RCC.MSI_VALUE=4000000 -RCC.PLLN=10 -RCC.PLLPoutputFreq_Value=80000000 -RCC.PLLQoutputFreq_Value=80000000 -RCC.PLLRCLKFreq_Value=80000000 -RCC.PLLSAI1PoutputFreq_Value=64000000 -RCC.PLLSAI1QoutputFreq_Value=64000000 -RCC.PLLSAI1RoutputFreq_Value=64000000 -RCC.PLLSAI2PoutputFreq_Value=64000000 -RCC.PLLSAI2RoutputFreq_Value=64000000 -RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSI -RCC.PWRFreq_Value=80000000 -RCC.RNGFreq_Value=48000000 -RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE -RCC.RTCFreq_Value=32768 -RCC.SAI1Freq_Value=64000000 -RCC.SAI2Freq_Value=64000000 -RCC.SDMMCFreq_Value=48000000 -RCC.SWPMI1Freq_Value=80000000 -RCC.SYSCLKFreq_VALUE=80000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.UART4Freq_Value=80000000 -RCC.UART5Freq_Value=80000000 -RCC.USART1Freq_Value=80000000 -RCC.USART2Freq_Value=80000000 -RCC.USART3Freq_Value=80000000 -RCC.USBFreq_Value=48000000 -RCC.VCOInputFreq_Value=16000000 -RCC.VCOOutputFreq_Value=160000000 -RCC.VCOSAI1OutputFreq_Value=128000000 -RCC.VCOSAI2OutputFreq_Value=128000000 -RTC.Format=RTC_FORMAT_BIN -RTC.IPParameters=Format -SH.GPXTI13.0=GPIO_EXTI13 -SH.GPXTI13.ConfNb=1 -USART2.IPParameters=VirtualMode-Asynchronous,Mode,WordLength -USART2.Mode=MODE_TX -USART2.VirtualMode-Asynchronous=VM_ASYNC -USART2.WordLength=WORDLENGTH_8B -USB_DEVICE.CLASS_NAME_FS=CDC -USB_DEVICE.IPParameters=VirtualMode,VirtualModeFS,CLASS_NAME_FS -USB_DEVICE.VirtualMode=Cdc -USB_DEVICE.VirtualModeFS=Cdc_FS -USB_OTG_FS.IPParameters=VirtualMode -USB_OTG_FS.VirtualMode=Device_Only -VP_RNG_VS_RNG.Mode=RNG_Activate -VP_RNG_VS_RNG.Signal=RNG_VS_RNG -VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled -VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate -VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar -VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar -VP_SYS_VS_Systick.Mode=SysTick -VP_SYS_VS_Systick.Signal=SYS_VS_Systick -VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Mode=CDC_FS -VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_FS -board=Nucleo-L4A6RG diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Nucleo-L4A6RG.pdf b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Nucleo-L4A6RG.pdf deleted file mode 100644 index b4e6fcaef4e7bbc9f6998d5ae7af7394050ad881..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 253594 zcmeFYbyOYOmM>fc4ess|2<}dR5Ind$!GgOJJh(%E;10oq2Pe1$x8QEUH%^eRl5_9v zdrtTL#(VvG^yoi&?@_RKRjpOOxu(y#HjUyd2_`mXPDGmZjnPR&PI6XqJ0nYSK|vM? z3u|XnM-~a|H_oQ7OpWbKOj%x=+P-x*C+Ff}d-1}_+0pck4WfH`hMJsH8Y_0o8N>3p zkRJ^N%=rv&6pL$b)!ysM?j*eld`zR5v$N7lig!|^$)~GOhYQ}NMI`Q5th$0QkcLbz z3&L0EG%%eXL|^7?FH2-Qp@m&U1QSF7MNiSK4PoOrU5!#DKBbxUaH0g+rs7y#uI64; zEj(i_%cWLT!xx_s6{mCc`fQ}l{YE~OWRi3H1+GA$#gsRrYuQ|L!c3QK`eMRWg$xx8 zqkkS=7-LwPMjm<6hM5qz-{zueaQva*%Xq)SRpSdz?+(AGCSG>cgJ{HUrYy@aL%u86 zlv>+JO)cH!*72AgAtF}qBVjxD6i-iEytfkDvxUEVqLwy!t}P@?aAVWpKjS2i${8r5 zzv@}j-6_hYe>1#NGH>rpGEpwaXPGHo){M1fS&7cJ6!={}yFO@jOuJ==Y@x|LL2lkq z2kFAI&NUdCir?a}#9&1*tuajH!eKtEX}inVXVWsRWCY!%4uhPtir%@fOhI1llJi|0 zS3^`YeWjZ#7PbqF#JssGU89llh%B>w=JBd>`olXi_cvei)*;mcNfap=SvL@#(6Lug zgoKv)n(jSgt*jjOaj~e=TTg;i(&e9a4t(~aqFBy~j`U|z$w0sxjdZPn?h6rSP7XD2>-5ySC@SH@8qM%R5>wg|lj~!MBIV-TFJO0vdxE zU$FjI1p%E5-DuxieY6C>&gk%=_ro1{8a{)z{kNm9-_<-o5x<9(L^QQE`I{7hpFpWY zWdB3@K;aX!vvoGLb#@~EC6LN2svh>HEQ)X5nzAUHI@!568k;(SHz_*W8LOB&lk2d6 zLQKx0YU=Jx&LV9C-uCiu|Hc0HUs{hv0-W)eRI`z@{hm^Sot)#>hZo=roZ1n58adbR zD{`hL7H?kKx$CfkU%B|W$ay*0^6C*n<`BOBTG|bXBG_$6Hv8&-S^VM z*-6pVQOwT9-p=+HEZ)B>9w#ps2j@Rj@A3QNDu6B{AuRzwJplkH@C`gJ0Ac_F92`6x zECM_{{L`lhh{)I|$Vf=Y1ejQ8*d&Bxq$GsI#N^b>wB(eGRK&z|JkJ?f**G~l$!Ph6 zc-aM+IXKyWO#=1w=~HARWPB79e0B>Sfhe9Ody7Y7QgEfTxJKc=!Z_G|y=1p3`%3ar5x<@r%6@mync_mQhhv zQ`gYc(l$0RHG6ArVd>=T;_Bw^;TiZoC^#fEEIdBpLt;|$$CT9Ey!?W~qEE#o)it$s z^$lMdn>xF?dwTo&2L>l5r>19Szt7FDt#52@ZSU;v{Wyi3onKsDUEkdPq6-Ru{(~&= z?;nKyg)R(`t|u@s&@k}7=z@CU1|HBDFt8MCaG0V>@NXQjDB1lHuwTaIRDFF)#i4wH zW8^rFh)d16Msxa$wBMBdpAi=DpQ7v^g#8;`^8hk56v#Yi3_uvTx~0qYL;T<4f7jrD zW#E5h;J;D^=#$DFtJL1~Sy-xHvYT^gsAe7Y=vfJC8wA@UT4~E7Z+L zgwS)Av9o`|Z``zR6}MJ*Z5d3Z8RF{MYC0r{A6z)Z^pER^F+LgEydV}oUGjwB4&CJnW|58 zBpmS_-fNLN=|)w|<#o=dcp<1YrJBQp%l%_Cg&$Axk`E@4IXI8~KR5m?O6(Q4bq^S* zLqXl1X3G8IhN#ZRti5Q$O7T9ttbZt~!+#1jLy}^xTz*LLl#|uKz_MXJFG{Yz9red$LAtJr&2=F=olNtL9o4Rn=G3n4NcAD;)Lz>~b_6#VI(=b}8A(S6O z9q-bkQ}(8;)#Q|Q5S*Kfxg`8F5f%=~%=?mSh=WIAycFR{3b@|uKdVcr-K$WS9XMce zVQAj@lEO?Sjhv?RRWmkplOU?G16I-&(kP7jgWu%#{k&(%%edhk3-0Q@32pp0=(#*e z)KTnWoQ(|WjD9B2;rnzzZuozAKvQ-1uKa{EKe8^fGftH<#J%bcHE~N+5_>~-{n2}4eqqQs5}>s99&xEOrFQWev+8FELIjVZzVbJPttTfB;FX<>Ls z9c-t5+qpP zCm(@${1$r1qQ2x?LVc}>5gk@3`!hZ@jp7?G(wMHD?&Jf=}c+XUr86be`uB}Y3FBPwdpoSly{i? z)Kin77t!rX+l_9KWA-+Ba$t(u@x8=1DFq6(d#%{Oi~(Ay|^8_%7u1-TegGrE)N zJJ-J>eH;vg33l&xjDG}}F)ph{B(P6B)wvTseYfI&$h2*-%CT&~ErV!l?KM*|QAB-c zM&p(+!pQRXW0!`921r`5l|*3wCm+VwsS}VZ3H0xxFtaaz%)G)1P~sjXB0xY5ss{{g z*D}8B@Cx9-ZXLG1XW;slscXY%9~j^W;eAEySwnYc4h?&BaZd`FkkdYU-85nuevu-6jw1hAA1_nzHsZg}Ids^cBmibowDjB$NP`ihHWAJ6H8Q7aYM%LyZZ z@pH7P2ym(Wm+Vbg*TI|OL<*%8_Yjk0^eTe5vhz26@h*c>&Iwix5P=V{$~-y0CApq3 zZXj%46mw&Oj53w-%X0M5Hw&KT_ytf~TU(pZk#NuKL>R@}p-EBI==A7Bcs%p#c(#H# z62*)j_~igu1ey<;c)iA&`QoOI0qKf|viI`RoN!RqFaq|AG$CK;Jhg-|;S-Y3`<*2f zKY)M!zcR}EKb?z#LH!gpBX?0}VVS5fb&X^_dVa(zm_A4hlS+d8$^Jl}lIkO{#x>!) zv!e3|e8o9_1PF_r!pA@J6Eb8P5bpMB8oNwWoE1nZ?MyJQ%N>2i#x)O!tbrOJvE&u> z$XU|qbFfYA{ygZv5if*!nm831fDi$Lu^jC_e}zQCgfr^fX_fy7jJ7pA0s#yw4_r!Q zWY_NKnKq9=s@_;9XLBC?2hF+aO#M|Ll_Q?jEmE-vuLim>x3ThCfm8VC$0Kk}-SP-* zs8(Gci+ZfRuP-2yqkkF2o#;Yn=ZctJBLNJd^HG&6lF;A`iJc;K&7w;RqLj!Yhm%mt z5uPS~_ys3c(lg-!YZ&ckQ~SeH7UAn@z`0g~^#%F0^C6PZPbt00K|SW(endv=IZ@KT z!9Z4NUlSaA1e!}9fz|l4M<7ZOURK=6;r|zeI9fLgnyx7E33o9gJDqbJr&X`IGCKk# zvna_fbn(9@Y5WwvtH@mIc>d*4rt+Sfgou){*&xCd05hH*7x=}(=mVE5S@bzxCcdntQtd=O-K2$vQsI?h2@Ab1$q)`O97u4$Nkv5QKj}(vDO;`^P@~+ z6q}t55v%u-U!i*iZcR8UEhRkf6~?NX8`rhFV-iLHrQ%}e0r9B)dPy^6T{xJTQZnEO zVslIh6Cu~=Hi$4}3ghMXMDvD)6~(;TPR~&)Ruml^!ls@o5~8O=?{u&1iuVJQph@9NCkPcJCSM<0XDx>D%S?X za{?F)Jo4xZ+B@1*vMU$gJ4}7w(-L6Myu$FE=*iwZuGeL3bJ2$;z42IVP(%ZSI-oe; zQX3xO7yT7LHW++uZ=5a%oOM05k>O5N4I;Fm|G~L@fFo)a36(_dD5)Jz7OGGBC4g_$ zMp@HDagWk`HnJ?=1pSq6fWR2Minx=(Nv65)()1&6BJJ@A^cLr>qlL(i)vVM8EeRG( z97X!&_6~o*I0ByL@lnCs_W;i48eEUS)9sM^C4)x*COPZQGD(r-A*ZW2E8S!XOQ2cODX z;k&gB!fa@oCMrnHb3SxYxKoFg2C4VXDtfYKX6!4M3nZml?$YIk!(l6l1OHuzlXli! z%q`1(0BEqzZ3?W_Ulct8R1Xo4fMN3^a8G0*?XivldsnaSsrOL82@u6pBXo93^~2`7 zz=rNvZu*Imo4nmQ!*2+6J+MLvz0-OG$RiAXBJQo+YN62jKLVQ~CoA^>hrZ{^)80;s z4by^LZ#>MmauU=gs~TlKQ(mI02KJK&AP5E^6blk?D!vmsSs135D3Yrc8R>X3Oh_N? z6)ytaNcq{~UXSHicmS<n?sTXC_b^ryD;JQ{tPD2(?-Etfo+6;B#2{(js)x)tI_2{nI$I!1hh4G2sIuyGI~* zroI%ubF#~7l?2l(%s3eTe8|;<+OQ;VP+wXQN?ZN5KEutP>97t-tBCFCd!=t>y&RD* zphhO+M&-?+(xbYZRk2yETG|a8oO|9|zs&_reZoiX!wEGuO96_=z)Mg(Dw4Bqsa{t!YO)6_ zBgVx_is?rG3BMoz?cglvbtd{AI-7hS61z0OAdmB>Sz~Kc@H}kqo>?qq+@86nLNpNdhcN_x;iIJQ}a&@9n34Hmv4cGTd5j=Kp5ww)h=8#)c&iwV#P zy|PH0{dYuEYvuYw4^v7MBti=SNNk9CnVYfj#gu+*7t))J6SaG$b*a+}YLjQkJxGO*3HVPMz?;WiV_r&6A@;5>}*sR>7KYe!B;n@?6fr?@bdfL{TrbHcoLa%4_J~Hv|wl zVg$R9j1pm@5xes3fPI-m-v=Q^-vb6vK=*XH@cx9cL>gMhT%EP8@HT$iaV1tl+y`@g3`UIr#@ks=dpQZEA)fRimhA*UzvDHKeU{(4`e(e?}-j zc}`_quDR%Iw%bIm;j&QlO;#U^$mbx2nN?&9%v$a;8abDQA7pS=?w!HlYn;#&aJdL8 z(brzt({`E8_{PJ1T(b9*Ca5dV2tsZz2_GwNGlOy$Kag*+?Nw@3oUBnLnKXw;VcHgo zj$LCIz$&3Ye!eF{s+0Q&^do^#D$PMQV`xj;3C7B@i&2T=3ihedsL(>w)?4w2KLWA1 zpfc)@gNj30XQXQ76=0aMsaQrrgoNJ@^Z9E(AK=KU;CVxEXSeO+t)^dAxs(}p68Io8 zzjGg?@Q@&?AExj2=kEqe!4Jqnc$?n6X!rA3*BYCkld^UW`ftpmiD&-eopiSj3#)j- zxMHp)j#-TF&+WY1))8{CJlOn-o95MNhcpKUkj{`vzwBNJ-;kXf{DfTrmt#R@Q&1A8 zyeQ1Bu%TV2w0Mp>O{S);EqIlTNmT&pt?!!JW;buI&TMzjBhXT}X+aV(SiirjCwu_W zdvWMEUC84lILSc=p42w2sL?yR&8@~^QxGNVcU9< z{V72om*C~;f;;VNsoI}uz?P`it;*>@8DB>2n;|KcWU@q`v|l>0xz55EIOyG2=($~?9W6?mR{Sn z1ZmnbYd>%4S942_1ip3If5o`prhNw1NB+qHP9GyLl@BjPXL33S6{N>Fz!h6hdPqoU zz`Zns_HdwrR5Ht&WL}8-ZWbB*a!T#@v=jTK&<`ia3m4CH2>44&u9J@NF^|lP+8Zo# z!{^y27W)Wgs;HwV4-J@bqPKc^-c&nihg~XMOVqAZc?`i{P8U*r1jZUJ-+SeCtio7l zL;GPHX4Z{Z&1!S%Gq$8cF6S5e+Z&>FoQg+bjz+O9E`t{6OM;}IWW{bNK{}f}s3s{- zEE?A8A#a z2!l6|Ky9x;Rjx7ycW>4;Y8B+CuRDYsWfm7^C)5AzWv2wM?y#RKTEcNXoHc>X`n6bI z-DnaOx2I=Fyjhr$(Ku{ub)q3gs4c?JR&lX4thGiLGzu;Os|=ZuBQYRCElFy}EXGSF zPOx%>#$I8#-zgPn|Fc&t=7RPuxDFy+kg00YlR5EV5jvxgPMWL!`HHFGIe|X@PBfgH z*ED0mgX)-p^iQZ1X4L07E@EgU~Qd3eh``YP<1L=C^$Inxp)YUa_ zjg_0fqg4|xQsa@`ywZE%X8n4zO4!+$_fXZQrRt=)>zL)^OR+-!d?|u_7k8O#82>X? zq<9g6QOog0E8H>Xn!=^~im@N{q`E5>R#7W^Rd25%zv;kJ75B2uSHG@5eMd1qzcYl9 zCL|;_!11bz%{-uAOXf2|HxG>Wa;_iK9$u>ZbT%$`Q&O6pV09-I1#Imkxy|W&*l_m5 z*!UbVY{3Qs+dstvpWI(v+vZ&!i= z8AP$-5!f%-c?g}PgBH;B!0O(r?Q(o8CraEq6UOPdbe~M5nqo|T1H-oHdY1>!2d_Lw zu7GG^w6tmOk|vQbED~9rA&MNXYR|eA3`K4n;F;;G-!z_kYPva_TtBlce&6D_kRk6* z>*}7TP|G~0rb;h`eHTI>lY}!lK$?OVQu{Ukb;2Bp{=kIl7mg6Kw#de1X+}5Pfq@-P zsB}Lt(El`+q8G2$FsV;c^%O~p6f>f>I@BB+_15=`Kf#lj6`4Ej(CM2guKe%Q1@*d-aB4}8`^^il$$id>)x`R7`(>@6KopByDQ52@DH5!Qtxxr9n?@wP?sClWs) zX64=B+q|g2`zr7-To^PLXegF!l%v=omhPv3lrVO_Yt@Hn!|Q=G8eg|r_QJOU39la>!{ zT%m`8Gu5d?0-@-#+nT*m=o<4F`KtQt;ga%*r>cTTj{wE-PYYi#$T*+xdr}^1HB?zV zoWx*EsBx|T@M+h?VnKa|e4=*uXnF}{uc?VOJ9$tSWFy&jFk4KWYmsxVI$OI zm9Zp8O;7X&^_9&T>Jo9>UYxtvYr=VHLskb zlcx!$DRL}IruSGqK%ya7t=*&L`ygXbt`@ap9z4u*!CsFIKcqhgY4xex{^eHlEmxi> zkyotJB((_&nEfW*maD6g$WMV$l}J)-HMu`Yt*Lv6`ov`S6_b~Tu{l!(c}*%!YyAAS zvwg@n#&~8W!R5&E&UPwJs2YSC0~AfkH)ct$r~5Ofq3By`$;u)N-Vt!*&VV1A;(P?p zwOXF2uUT@^EUr5DC{q2{yHO^nQKf*6O-Hu4VRJq1^m(|%`}oUI!=}v4&uL~Tq_CS} zh?2zU;$~tVD9N32^s=Fc`UIRmdC3laf2c}P#W+0z)jTE;UJ^-dU@TeU1MI#+4K zk-7caH1U%3toAPxzP-)lt@^VY$VSwsYC0*?F08bFAPmu*W<2apZVceq$}PNLG$Hq% zoQ5U_&_o!t$|N$@hS|Ss>U=lWsP?VVkur&9pB=Bqj^*9q?SSSbhSJQWopJVxGFl(i zCPYrEPiCF3t2ZZ#E{-FplTEL{DyYrg@T%B>-C=6tHDTwE3B=pz)i6%K2o$tkIDk$QPzB(Pih

    slD z(^~3aH5xr|`BD1_4v(Iq;0_V`@m+s^YRU5Q8a?f`cLvU!-M-H`Lx|K{FWnZe3=>1s zznOMC6Oi!2Dr3PdXM8OF6?r9{N(b5~g4D;Yv3FvFy4v47&t?ruwW7?`X1GQ-!a+*U7N`Ax1LWLtqS=ToM zCvvdx8Dbb;TD+E_vFXd!z%XL>#T8S@RmW~_7_a|{#*5GlO^%qzdkID~1^yg3Nu+R( z52Ly+A70k`nOZq`h?r&>yDG~X8ApCLkiElCW5YSDymbpGt7x|E)jb6!*n!^C@;+_O zo*tbU8XAwyeLunSUyU@a*^qiwl(h8QwoObIS+RLO8nCi53BwkYeUQP#q!uNk7iXWd zR26W@8NvHtvbx|Tlvn(lVdOs9POQ7INfyfK85zbz-gk8iB4he<9yJwA^D_6ZnrYx)*xT zopr|)bS@G3Hz^C-xN5hqzahn6H{vLoxy1!P&>MR=3qCs&&2TG9%9VzA^20z*UuU|O zqG~T)H^}E7Oqf80=rgwC?h${;*IbLhNeI}Wn$Cm1!5m&KulH{2qkObK+$}r^I7e^_ zJUC|Z__TO_uqjqJWA0+H_pYis)XjHj94Y;CUIMc_{=@NUnWw)qMGJ z3rLTchX1BgBntjDL(2a(L$dsf@@V9gLP!rl&O6cJQvrQN z#sHfsQl48<;J8K8Aj7jrpl;rB$KwD@7;bMLO=K%;N@?7SJSrB#ZXR?#$( zXGRqolEaC{Bevo!v22EPo{Gq+CLZ0!OMD(TgW$JgMU`>_U3_%)lf-ju7}P%&mj(FyP?ok}sfnp#l)MZdA+pI&K>vR$FZ$KQ~sq9ITogqjMFK1Y6d4Irh`%_qpB5C3-M{7YXI<(~{75o%Dx zQzaF;bn7FAtB)Is%XcrQZNFS@N_{KDy%4(rFfh@BoA4jWhMsb|B(ZXIWAwD62EurD zJyg5AK18i(@*ut1Ff|R}y?@zT>V^hE0emZGgcJb&1?8@_|AxfXd`JX<3q%9@ml_Bl zN4R|O5C30!9PZ61kl<+ihD1j(0RT>rMIh6N1eB!7fY^>2aLK^|=mY?3R7<|1N=m!v z7DWtI!`&AutS_g_11`1|a`QqTa@K_;?aue7H6M#~^c8Aq^)W+bohN2Wr$!`*`W$|> zj`{ogpMRFl`WrN*@%%rNSE4w7CvQh#2Xw#@VYPq+F(2TM4kt5>xAfuoP|(gPkeSn^5p?#orgZKu%AP2%m9gS#lht{Ft>*azzW;-FWO7)UwEv4W?Xm9@-4aNK1GTu z%6>MUm)6a{+uA*vPsV)%=`Q;EZ%H>1$ql`L^UXD&(7a%*2Y5GCNSjJFWT>eaV9Y-> zBe+GW-WTa#oCWlk!cZ?#e~rMBNs6=8feO;Eq%IZ^}sl zc&sGA(TZF(BQT4AqfW5@#~FV3S+1xe%cHSoc6~GYB1(Ne;Cl8o%OwxmTDB!a)kw4r zF2s7YUaG0A*kIu@^o4&@<_hW%ccp8ZQ@o6qhlFzda3%ZpA{zn*Hy@96fG!wnfCCb; zqT7d#bEOcpQl-9sk9|8(0X3V1S7jiKm<{wgJTFO$zt*p@J)gqYI@VLF zD%Y}dK$DN;M*y|P4Wxsl>Hq12Outhg-qlW=FVC9SH;oO)@nX&F(`#%A>RKm?ClJS8 zeFjfTu$|3_Jf9UR0SGOucIQLVX@f`3g_#;roCn!LewxKyjkuD z?uqE`#p#hE&Z2?Jbw2a^z)ggoc9^$S0t27hw@rtM*@J~^+dd*=^&sCgGn3acX=xr* zqBCXb)je0&)b+-}5R_v)a|bN|cX!KI0I6ByDyG_c^JJ`;rZQ-oA2GO^5lMjF2MI9p zbc79a6#u*{pu<4i4k1u`e+WkN%wsS*XUx2M2cL;lAnRX?P#^qQdSCyJ=o|w6J{v%W zZS+Gf8)JS=SJ5aro=B^US{~!b|4_J7;HwO!Kn$H%3mIc_+g)r_3pxVtZOS8L@Vh0~@J`9s5?GddXq&4PqDTAvy zW+~YK=TRDyX*iC1i^+(0lI^esO675n}3H4`76@TZxfOxhgg9yw~o+3{k*a*s>WX3#y&M!Iu1?0 z4O##QnQ)orodgJT?l)kWZOno|GxV>JzF{;B;X#J}_B4I>hNex@?{k@i>!2yR5`-XlqO8*MB>ZsTWh;gG8~4AB0r;%UILDAEDn| zZKeDU#o`0cwNLr&%_bzE8JK>A$u(cxUgRFfiXdmARku}z9N_6Yjk@1oufvZ$U0JPFL?qX4pwNfI;c4@X^J-#8 z_(i{>mUbU}e(jw-g&&z(8(%B4jf+s2@aFNIl&^qV`*aL+_*emu3v+f*AMa%SjsgEJ z27dF`^Ypux_)kCVlV6AVyA=4pn3CVs#Q*R7|C{rVo^m5vd-Rlw(6#grG+s{$XacVc;H_Znc>;o|t`{G7Q>|Y4)Cx042^40o}bP32aYJhYJ$TP@nzg%pirxxZIVq%h5n9$twf*Dr&7JEDc7jq`s6Aknl=`ypq4`soz$- z^YA>_0r#FvkzRkAE(#%?ICe$;T7Cb+6$bG}r*eBZ9GzmhZbl9lz?|#Ly+=d_oS#O` zN<3mKc|vzzU=`kSOr9!kES?+&uz~oY@}rM z0mziDSWL-oV0?Y2_2n&qH_SQfO$hNW zZXU2j^&MzLE?3{78PT~cs}Tk2=I$QoCOQp~7#_xkM2kNK6x_Y{WFK;`twK@hKBDW- z3mW02`;1kqC`e`67aAo9h?!SKvUIQZ z3zsfat0##mwU8K(pn~^r&O&=&B%7!cS|EMJ5F%x+r>!G~ys$%S*XrFaiswN&y zfo;a~1@UZ4@~4~B5_ImtO$fmw1)MEAGaG%qS&yJeOUX0RbbL{hCE3tESD~9A8;I@Z9}D+>d$(XYVZBlH9vXDs|uteEfUz)P^dj$WXDD^ua-B~F-`Nuw=%}q!k;6J z6n`g|9ofMB=IJC9Q0u5V9ZvIjB#}Xu%6kqy@ zQP66QDej0ZS9J$3)gA&^N8lbS8(PIPS?=a!BKK2KX&V#*qS7uK+bLE576jG%&k0OU zvW)QtB=#6FH=WTeRJVDuIgF-c2jk;s^F$-N6)Xe9ljH5#bC*pbXA@2bZrC!A@c#oXFIlD=%uf=gntn1A;?#z3*Ay>9x$rI_-ym2?w zaN0NepbOkn{u)o(FDJL=%C)1#j6gAYXvT|qe5_O_Ney@Vy61L-qW3slR-npIwQ<%P zOEll{a^d9scTn|1g@;dLqa;;@jItHQeR}zrU1=tQ7f?4zj=9QVvrj{vtYzCj2uTew zKX7@nf^O!uHL_dVJr6 zJAbBm`HW01jCE)_@Ogf8#e66%QWfP5;29Pm?ZUi#4;r+GS-`gjG%Qa$4UTe5%6AJMXJ+!r8F+uxAV zMhjJKTCwX0{pdnvdNEQZA@`#Gm~q6SA|lq{_$o zu6ciFVHUIWWS6~Ej=l~W8Ukctd32Q7;fc00{+b37Yx*0K_@r5AAyHCeQ49QK6zSI) z_kiN6*Rd4OXbk7`z@F$SuO_Xy$v+J6@Kf&7N%_BquSI5>&?wMEbENHG*XTxM(-Hwl z;?IgizzX*dT_djkP7S2xhKFPChS#nMEw0^J5p=MHE~Ukw#S6$hL=>_Z5JhbIya?wXTmb8J0#@qWVk*aRksNzO_Lxo&zM z84M}Bsh1h+ipvr=q5h7)u|8AHPj_+yKD+X*{NAMc`uZ%kU9!KWJBKQ*P^DRn&O7Ky z#?;0q~1Hky(cV$jcOBZ;3p zZeYF7^2lT0Q3z3sde4-?T$jD}i;(qVLWaHCaV5=I?XGWE(NkvH7Cd7G*nFl|4Xegz zQmARk8#$DMVP?MBA&7;g-pYPf{vu17%3~vZ`TCH0aW3=3JA@Bv%lJu=61`seN|oJc zC^l6I{ob+T*vT8o4s{@q%UjGo{B^uIo@lirdHIAL!lI*1zO*bi2 zK83hC;{c^)sz19Wj+|=8%1!HEkLcWd7b%zDW4Rr=3G)luXs)~gP{0?}2vtA@aS!y% zmPo$H5wKRKBMeTzI6*G3ntL`)i#}ZIcR)^9AZsr`hv`4R-!4C(zPSflr`Ga+56G_i z|IXoAZ^QuUgM}9O$}ji~RCzGX2#Zyys}D!=011fXD-YxgLfqJ`zj&A=jXGba05*<< zO1kSy|BVXO{{dNM?8NmnhX7EvhtlN1Wxjgn(_Qx`TYOqJ>SB^i*(h) z)44C+^wnc;$c*d8SI5>H!tQ)&D|^|eN|EvUDuOrUpDRrlLwMi@ z#|`7;W$&hA(GQ%uTnar5+qF&VW{O9*%EmQnJ2{~SM1%@n{0Es>KES|mMKg7-W{vy zScG^QZ;H~Eb}D!jn)4<8eq$=ZSY;6*ZacE%#wxPCu7;2Lz>^aczai{ zvQCHMb+wEO`5@#pmpZmEbZW_^Tft&HKHK*s>D`s!PL7FA&+@av&cg93IB73xs_9o* zHc1=1ClKfy0`id^1kjuOp}bvjXKrEHhWX+=sgT>Ws;a7ZH%29ksNRZNu?m9jr}jNW znZ_$Sl!pC!veLXFn1*Br-?f>EmFa${5m#nP^Qc)y4AT zPd>+E-foRsMV1GwPsUab75tZCVbV|E%+5$g(s-|H#zf+%@~Pi>O_7o!EJrY*GY0<+ z>6t!s0U@c;UQ7mLG-~NOUF+ug^&d=OXQyh!?EHT2O&Ee7SC?!A-V136e>ehZR*txf zF;8nH>zS#u-^=@@!emm_+2KdCc|c zU`dH~5O;UYLomTmnp8U@lSXE*1sF5jt#abjjRm zein;u3q0Z@$)$r(y5eY)SpNUGMz#>SGe!Kn| z0pymhrm*f8Ga$vgbAPW$;x9fUZDKh>3-@yuw$E88$56FEwv9DxK@n1C_jPw(>TkZk z1((f(Y1O@mD- z713q6VwWdSswg9p^^t$Td^yWMeLF&@lTO>WB68n#w}?Rh=>{ncb$9WSw&F$e%Ok49 z{;UPMs6bi<;!9oZovGiDUM1)qzKL9xlb=6V4U-AM-_`Vq5g&Bz1{G@8jP7y`&~+NV zM=Qg8yi9lh#(YZ@e?qo@p=k^zo}S}?>G;9avEGtC7E&?$5}u9`9#?6bl9J`R$>Cw!sb3I0#|+=- zaP!P0+Qn}*4GTrlA%4FQI_0s5TlXBEd~4s;i1g@@YLqBSl!6)NJq~GClFyj) zX)}t^cjP~e?MpO@97JA$6;PA8=-yEXRM4JOZYc42(c!Nml&#l7#&5r#! zV8@OX4?>^=d1a>(0QH3X0+MB;5daPm0EY2zcI>a+*?}`Mg#X1E|6U(9>ccM=`UpQc zpn?qr5XUd)119n7r|kF_vZ|x|Czm&}nNKwo8`zW)G_6|Fe7!=)T5#P9e2YhwW2bxM zvT*w2rKq-jj1W6Ru!UVVO@#Oz-0WA|mE>{dV^(amYGB%svU~@|lJhI)0;Qt)OZoO5 z>+<~m=g;a$)L2?xOiQ*3+fS|Btut*aNZ%J`GgdAzI3mNJy|83oX|xXTmi>57ddS1% zWzMUlPZn+AaTj-zWd`NJA6?j3FbnpC49&q5XW;j|F%T>FmTyn&Nb#FZXCm&3o#{Gi zC+EN%*Gg=>ML%eV_Ak#VkDtsm0FQ;H>Yl&OUvy3r5r_txpnG)v_OsXNfLRJADjlZ18Wh%K3e>< zHlDTnxDA5%yKX^&%86>LL7~#U)0`}SZoc<-esu5e3K##P%jXCA{*S)Q|NKS0ataVH zb;OZb9z|n{CF7X{%(uz&NB1M#BJR35W{h~!Us!871n4EmEO=4&Oh<1erxaRV_={E^ zF~mCTbVa@e6V3GVF{1MgNTpwByc~{TOUY_|fO}~wxdA$)jTXfNZs4DN$$yBRssHHL zB+0U(zZ8y$3VF7GavF#D+*T_G=rS`dk{rIWetRCE4kn%5OU%WQl_DN%)Oi2h`HnCy z+4c^K;$ci|W?tp$Ij`sIkZ|FsGFQ&JJ46XA^8nC~x;FiUFD2aO*kH0_WxVDi#Bt$i;RE{p-)MmdE-OC#{$%cK!` zKBm#>)856BB2*H-N3PLJ@R`F^YtVU@yv}ezNR71V(bhrkZOqBut0$lex-sITNp|`o zJOT}WHqMI0m^(S3c8rGu>xjv^hbv~(uou_vO^PX=i=IR47JT~AP|6)~>BGAz+4}Pf zv;FjIv*%;;ZF;NtEyjpli9Rc&$Y!KOC{Golp?NV0xBqGZfmDayK?&+0dDc#qkPEv_ z>n;8UUJ3nF%7R9RF*j)EhKISQLq&CjmJ;XyZ7!AlGY4u(9noyXOxX(74 zT{6LiC8Mv^p4H=V3t1Sf*D4Dt4}Z8=ipt%3jGItRfg4w>J%8x$Z!N@a;0SiiX?0_$ zi(S)ZQNfvv3@+i1gmbuTdF`lWpY9-DHbYMU$Jg8DKrWX0{9qkRbNTq?X|3!a!Ho9- zOzp%-YofyTqrngYQw^tld&@%bm`+90tA5H+4zlOu-(0RC zfD8&b%)d;B9YE)5u@BCH6zzI2!lheGGb?#Tt)!|lOf8Vjr17KFb0Zv{h>Z(*n<>5x z($>7liyaveRso7?CndVr2wkB37>4X%Y=Ue^-FYt7!zk!aG_>7>GH%KJ;eI%7W!a-i z^+UgEDz!v&^Hr}Bfj9~r!jSh_Xd<}2&vkSH3@5@y&=U2zORk6IO<2!sW;H_~xVc${ zjxz}K%fQngC2^6{;dq;V``g3j4_#|3B%{`;E3z)sJdgPXRk1>%N7GU|Jt-=g*|=|+ z2?k2t`+K0QA8k0?mOihH_!rvYyR+aWOm!8|RmTffR3AqnTOGhODIoGmGb5_g;$f^Me@d5B4+<-9_qnt|SWAOHpI% z)CrK$!lP*=A4fgqwC1;vN&I+MYHmGY%$oh;u?_&xAL7JQKQQGbhH5-Bce5zbHr(UL zoV5V3x+bwU1a|^S7*`;7aIoQrcXbZxk-A0cXBF_ohA=O&tqFmRDBGZx;3fAq453>y z;@UEA*nP&Z_IJ#!45u7f$Lj<(IQOpKj@S9O2hU0ARY5bL2H|Q|&xK3`324}&q&q6! zy#J075mxU-h8+bigqkBL0i|At0B32%~=EK6{``{l5>O*owkpWtVTFqicb zD|ctK*n|SJ@~vZ$Bmrx#OwZExePzG5q1+KHO1+EBZ;EL%3>o*Y&JDzDCF} zqu|VTR(i5@4&1HuV3tsNC4i9BiM926@E$b2Z(M|OT31hj{?l?7Q^ig_EnZ0T06%JP z)LiMgn<3KMdqE3J9onx;W;aRH-PE?ha@iG!TRU-fikII}u&R4p_}A)=yxDgE6MX>B zpoXpiI-K#kqnOWj;By{jt?h@x13eY-SCe~2#PDj2dmqJ6BQWP8G;M>n%)R2;;xn`v zB9|P)Fn1^6g2DM0hHy1yUV^vzulC{f#jIoNbSups3bK$l`iBzZf5NGMHT(Mm$NH16 ze=_^23}Um$@FxerI+x}N#_P1d+eYy&8=xb41R?khX-Wok5;b3yPa+N|_nHGCyL2g6 zGS)h($Xz?y>&4kF$sazvGpUN5C#4B^Nh)FgDB7@;V)ycy$1?$Y)dwojw6Za7$`{wF z0yb5?S+yl$V`%4idmPgBC7!w%{^vD=EX8sPa>oxHu$v^1Gj!hfBPZHdM{wAlawngO z5JjDlLq`f=``Bqrg9&lr)^dgAw3MYU0CH&O5WV>H7V;(o_O#k>LESuIt0-QuHYiCJ$U$E3x zM86#CSneBO{RAg7!JFoA4Rb3uaAh1HlNk-XWnsnWy`h()Opo8Do54b-^_25EL#$#Yq*zTT*+;qLq~q``m?CmZ z+kqJK(d>@-+jm$V(rRS+3qPZ%U@y0z^xNY1w_DAJR6xJSUkc1WHcF@lt5n7t1wNG9 zmsT7R*a$hL9e!9XiuM-?AArilk2ifj~RO)-!!xt+DiLZNI7o2cJRo zk18o&sLd+DIn!oT&Qry#`|g2Q%9kAZmsSG#Zx5wXi+F_DHOG9Tww$zM8W+8vWJd8; znoHj6z9ahG2w9x>sswXLrAt5$lPzK!1TKr8aoi23{?g;#!PkymU?Wl^GEw+Sb%nfh zVZHv0XlhSfv9@Z0)zWfr(w2_k`%XPJoXhZjGUxGmw|u45DExlUdE0brI}@pq$R{eX zJZBJ`YYGC58AAA@$vD2H|Ew!cE9Q`XM{Qr26oPklQ>xqfkW1aMDXpJlMqiSq#=1_d zPX@7ddM0#h8$a?Z+weDq_5V8SKyfH#j~S#!kBRzGdee@dYB?kA;}f7av(|4&PC#cg zKy?JP#QTrZ$T$CIe`TK8I-4B5EM+->X|U4rqElsD-OF9Jz9e>}zFJ)9t2AfnSb#s> z2A#Gx#{eA-{@e#m6{=kApdnFXY!D$)@d^JoB=@oAibsgGAq2_~vD7f?SS!(YT+|*a zUUDr3TOhkGefpgAIscQ+vN8UrGN}7>YyK#HJ&URfFg&2qF(3y-&iI{(81}!816^P< z0#*hZWP<_{Q(s?j%<0C;ni@yQ&>2iIDI`RCi_uaF;`YVIMo57Y0|P~@>>vT&5JjfL z0m_aS(!IGk!|BZD?qv zm)L#GNz7=wtpUD8(@e`9PjI$)g|9=)x9R5k?zQsU&`hE88SiJFdQ+=7E*mM@^{DtW zQfnRcDz+9z5t#gZCsY&kgs(DI3mI)fXepHe#P{2`Kj?>`-;2SKe%eM!t~o@c-yy+;v!db5e>0h$P5gDw@qZ_GN+gDUiR;6RhZ1vZzXTA^&d9#p%# z0{DQg;OFMBZunQTY4O>P#%B-4vZ{7%n)9;8l2R_>p+#}HyWzmkG7OL~pDzHlboie( ze-*??{n{QjyFUaV67?@11L6XS0RW~*Nx2jRfW@CiX!`T}UzI0-L+sCf4g9t#$H1CO zr+*V*ZvffYKme-l@1QavDFEnDK&Y$$4KY}6Ksi5n0<(vHm1jd`*3;C}>Y#>t1)5tB zGwA2TJ13Mky&-Riq5U-#}#`gZSo_CEVO z_uPHY51wbetg2d4^{#i$F~=OEZnkV{QcF_y@J?oTTso0WLDY5A=3jKG{93g|_+8z> zE`<;XY5&$7^tT5!adkL&O)nhYgm=yEa11VxyA-u2itTO!(4U%+{sZ7O5`k|vn)@;)iolhX+k1lp7i~r`BQLKV z{)&eeYx1oGhb!|~@Yc_o@t!caC6<4wgd`axa3esuW_7{{yQ_JAd^G-Jvv#}*{a zTF2A?h}L7%N^nKxXg_~U`yxZ&dgoe}@Hd}#QSbTmC3w3eHvHgvN8r*3a4SzChO_L% z!Fm-W9;V*4$H(M7#Wfewf~tKSL+x;mlc}8=;4m+?a3~wL)4RViR(Vlznjk{C9w-<8 zpq#>%)bm5`#x}IB@580OC{EygOrF*4li4R1y7u+9rx$?b3ghBDP*vnD@77C*Ac_E} zo?^rBI!<`7`Fx4(enx!_#7AcX$bl>>Qn141g$oyt!pxfI0pe*(Z!^$%{?k=unRpyr zZx7&W(SIU(+<t5b2sr;l`=}DEFRj2wEP$b@7rSXu>6JL!;=xb8vmsz>O7?%w;J@cR zcsEx5yz}PyPV{!JqCansUcXB=FXo|e%9CYPOz#g$#|#(>-i;j+49UUW;hezCl6b^y?giz#bsU7 zni5)b%re4gqBuO&AE;Z>HZf0}?xsM{Ih?CGM;FaQK~XqHJ`Y)XNe_zDy)?eAa^VxK zMk~R98Q5wINH&!NP`0%YVI?4|@@qxq=k|YLRRv4upQ(SS)c^A~HPFZ}EAOAHa8c=V zaL*55shL87s}#!X&UEIf51Mhkco~uD_c0fBBuo?}Cu$h_;O`zl+3?l?IM`9}4m0}B z^ykyz*YU60|Ji*H7UF@lbppw zu8r(*!8IHcKx_Fqp!b9m;b19r6?bdHUz)&dxn|&No!Z!Jb;wG~bz5`oegM>9*r_Kg zuOKcCarIx#pNovsG}*1AB9~8_grq>6%GgN+l~X%mqW29PmIfBs`Sg-D{Y-|lm-1r5 zU89r!_Orx?BUKMdQh`Q4fG?-B0r(V#sutp6P|~L}3_5!F<;JZCZI6l%wR>SAOW*rG zxr6V3uSjUGMo@}zVtyHq{<8hwejjq;z0|mL^{vc#pH^$l>v)Qm-t9pdYkQ0ddiI9$ z{^#h0U9H|XSlZx_1_FT}Y3#{43FJy^|2aT7+Z)>9Z>%&VUU(PQv+7&m1CE z<}UEU!D2SZAwdvOwxR}_kPmOTuPOcduSP8}GzmRF!d#KlU>U1qgtL?6`Pqlm(v9O@C zQ+@J2SG8uMm|@lE1S^$7r%7nNg*LQPJlo#FdKX|L&yQ?@r+{b`@sOi3mDt5u>$|9t z$8Bi6&dU^-I?f6z@?@3@dfGX8!q^ylF|S@ZXPpX6NAo%yKbCKwAr}?toPb0e6=I`{ zc0^jcTzLC99^QeG{H3ZyNj_n9pXNJ@7j?)(Y^>-X+-D`xEijJabhEhFx*{j3v4ufL z0!WRk7>$!1=GHj=5bq|eP;PhXE)ZP04L9o7!!zSd=%{;-a<|aNN^O}lM=m^sW`Hk` zIqsXp!8K?Bo1>X8a>gnuh+t)*Xjd?Da0}TWsFwCvpr=><)rB-VsKytVOuef=Gq+THHvjT`nu4?U;U`?sGaNk%DuFwn-rB< zTzU^^f6JYsIaZ(NUc<#d@hN5EQzz+q9spV39#lZ-*tX`yQ0fA?Np7PC6e66l&ARj2 z#L^erb}S9^WvvA%27lYb+T)0z>z< zXZg<6cSk?-6lY)#=}0~HE$U_V-YCZsp$(LeCLc%^Y(NpFp9t^izW6NsYZ+(Ftre?XrtFGD+cuigqZgY*MBI!Eo7zkDR;FWb!-(tOYt(t%bw{n5c+ z`Kp9xY$5jNhy=rYsxkUpCz73K>|egEWQDoAgNGld-l2kzGXJ(!;vW?CuXcdisuphi z@}CYpsDGx3E05AeB5{dR|BuMge{!tGTypi}7I#(IJ1rTu&}l`^tRcg4C}4uwlSOxp zmrrtiw!KqyW0~CzyPK~5T!Mx42Z)(y#HwYtd(ldq5BhEH`Q_w@Blp@AgsN2B(w+gA zV~mA?{zWot;3YYEu-6JZO(4R<`EHM(>7)C}^@CvK&fAttOf6df2Wl zJJD??cL0@Gv+JqZO>rajkCl766RUZvWv43MnU(YSy_DQFf^%5pB3P@LJ;L%f^lovYBMszIsww;D-l3J7KrE)J-Rb#=XWv7H= zW?~Qca6>@ieYKk*$?c@~vgsM3dAj1P%?BaRw6sNpDNPem36MVcpzB)wBa7~FwJE`_@QD4Dvmal-8Hqq<$EQm%BYRL*AU5g)fJ(l(F5iC>7IV0cIRcyLURE&4ojopcXip3Jup2@_Tw_np?P(u)v3(du}{_*Gc~>gx7rUDJnB70L#IhxZufgy zH@78j_`gKRJZ{nC-jG~Fp51Vqt=!~>Bi}Vu0!&Sn8^jat)F&>5iW3cQFXCiSXA-pX zBE?eKh~6vW$iHxU$@~h90@U>+`})J&FtVF771}vodvbpZ7%Am&wU-OT7K*05U7f zDKh5kp-wqn0TqQV9z`h3i4ZbBWYk2xb+kCEp`$f7t1Vlwpj;um!E_++`tj|4jR6r( zd5slJxU-nP3wqNx3ki#JfAbC3Da>6>U7pz5SR-ha*B?8UNLFZ-hvmvzCU%F{i)lF$ zOX;5Q!c@fzpD2bHmE1NKY0~k?DJWZA)Jgk!lUQ?7L(3|q>g#wl5Qw-8(d*?oyy@*5 z097{Fo_gAyCr!z=L4+Qt%$7bL&sQ&jl-JWLKloffkIeYJUzDGoTCc0ajHZgiBwq+6-snt zCE=oypWavf;!hh|ygphoQ3s9*eeRA-8GJ~t*e|tfdx^^4c-Gl1xFkv^bV42{Q*IC? zeqA!EhD5#iT26u%>3f`F(};@7_lYAQr$P0YKSL6yv0k$)>RJE#8-#DZ?GLaq?Zp=Q z+bH!}jE556{no5Kdc*)JwP)O*AG%P8yL9li!zgyDk%fiJeij)+g~U=hwcSI-bQ{}P zZqy*C9)_6&WydqTpk*sX)tbnxXRnYj8md-f%uj6W zK#1H*Q(T2FSEDpnXCBo1 z!}P5(MtGwOu}!zY{Z8?vUuCk`kj@Y9DeC5qsg}k4ClYBw zw##S2w#XC3Y|yDEXfZLuw(Tz|T!x^aB~0NZ)lkK82FVry^a36nXkITm1Gt&y=`4e{w^0 zwk_~}aQ^X;s~=lea=Wqd`bO2@icBbCE}ro~#|kMu@-UaKNuQ?grH7cT+$)4u zs&ux+xYYA|51^=m2uFLgTNk2>Gy#c+_cBfv;jy$++g7~e$yo`*E~iijc^>z0qavw# z#;wM_P^pbtRQtj;lV^tI=W8l6X2@3DhbasFXa^!#sWTkeQxZ#+)VF6(+B)v3#KiP3DA5%sGOpj>%mngP_D#2)YxK+R{*mQc zve(+W0AT)3@`TUdQgVs0rsJk~oC3dVEayFTH<9Ndghdb8G@2?s>>4ZnJA-D-fIg?m zD{n)hr<*a_FI!f<-~FX8^YK7;>Izd_mhK=*wvE<6%?qj~y1N>u988jL%?vI=gZpE3 z$y6$YoryX$*_{nqGX|`C175Z@mIhsR+^wrQ%qrAJIT0re!8ilYUJl(_^rjmxp)-pk z2lR1qlenxwvx|#3RC}$h5-H#BYe$FKFQml2g|1B~h*JF8a6puR8QWgQHhv16>5+O)(9J&TNLG5Z1xy;w^|J=v1`uz%IH1H|vT3uLDUg4aN@ zPAzC4cnuT>PxRm-|88T@mTBf}JN$F^pUjvw-|1nvr{G;25Xo{M?t_0;8H)kItA_xk zwyw!nVoI8)2tQo7gw|Bh!O=h z?lypk4!Yp!Z9Y%}a!6ej2fng3^u_aqC-;Ogg+Gn$faP}hAQvb>je$eSejEM8`0oGg z|3CNVKl%HZ;w^URmmVp3U3^$lw3M(gY6WQ1WQUfZEuQ4@oeQzBUe>9!CFShnI3cfQ zh$xxB&e7fOE8fFhOF3$<#KC!2Ik)oBN*vHJSzV5Wu|9Ew=n**k?7NlfR6QQ^&Ro&T z2L?6G%yT^)sEot{8Ve1pPRo~CW8r95Wmn&=hr-g@Dy~)Ca$&~dTq`0cQ`XJ2DfHt0 z1sQA5p!vG!fdF+g@C@NXqWNp4gK{JL+u3~1+Uuo5CBLRo+L~L&U_A{vdRZ!e5si;d z+_nJ}QnCGxNYC6R3&XDoKMC&kZ32t|pHj#Ng`mg3JCg#Y7@-$X-lR~ zyUa%tpy!w2?B;*Zc;C6z%+pg!7baSIDj|QV7A{s2(8}1qUcBv)M}do~OrUXip%~3G zNJ*6|`RqKQN{Lzbe097TSZPggA3HSp#qt@J(JO|m=oI0%a)O%sXUTdhla+aElWdX> zGkjY%B&`^?o%@rXU*u6P|2<`@e<_uv3J%^(m}=uGf}S+66xUnEpb@clt%$!uRcwzy zpo-MBOBl%MF;K5n!jHS9?U`6l;Vlej_Y{fw%K3@~g_yL2*{=t;qD)$1?%aCs3fv5= zQ{F5;>)Iym_qVBcXwg8)x=>jjS?|}KX4khbk>jiSU-=BEFYzMuZl)Eg1S6mCQK~PG z(bj~>F;Pnz$S?9bF+72QELC6Bh+j1OH}3((hZ{*-#Xmr1J9=jb0NuCw2oO(q++5&3 z<_u!wQ%DmxO6#Evv*t$hrikg2B+$<10(!Z$M^Fn56(Thl^LIcIZ1hq59$P>m{-l_8 zg)?}l*4BtL#Zgov*&~u{$cq_&t^wVlcM#+T&vaz3w7DkYlzh>qBMGuJ7{S_BhR=il z0P!<6ANGTf9f_wn@tkm<&1*C!4RQ`Xt}EAztPguh_du^2PzxNEw!S@Cywf4GY6dji zVizyho3HA6Tn$q@Y+It<1i|KjD;F}hhp_H?l>(A`t*#y(M$QHd$B^$8VWtM^RTWVK zx%P$!w@vM{jUqZq@v$1$`;*I8W`wiOf!&t}$ zZ@Cyg4}%&EP3>LAfC^D`zB#oyh9Lo_NwBhZJ}i` zV~(XbKiEEPSf+P-chETnySBDr>U=i1|3yWOW7TV`A>#CD_pm3Wt2*jtTwPhQ+u;3C z?s6=}Zq$yKRkMF4Ch%4*BT5WaiYmBh-1*Lrft`A+9Kc{7=H82+FW#X8e43v; zj=zu8-ieZF6)&EU{dryz(}S5;rJ{c9I#L_-se%L2i9Wk0IpV}_aGyHZhKDdi#8qzl z*gLE79)a<%qdu|MsCGh^#fSywLIBK*vI`LO+keJ}9}U+D?c5DqLeqvLxHQI8HPU6QfasXy|I zUf8l{``V;g!6HV24ZjNC%XDbZ;(t6_etJcWR5xRTWF3-@4%4iTo(zRv3}qjYHsn=7a{`x`s)<< zb%Nm-FZNUIBshLkWU+Ee(a8$w^2NWwHN06GL1~^X1>CQ*tM9L^;Y{JbPPh-cx_a+c z_E|1cz=vze^A6;S&8D~vo5SE#xmsGa^%Ip;k(vdwy# zVe?n+Z)>U|^q1oloW)4L5Pc$CNLCl)ux&oScSS3l4(oE?m3umv(_hq-PN>OO8_V_O z>&$zU=>k?Ci6xu%QqA5`_T5I4w-(9oRO`kLD5`xOY&x-GE(>D5p@?HN9H=~Eo-lBJ zY{rI`c`GoCbfw@qG`lowC;n{)l^!14+Jj0pmQy!YdiXJnzWJfcN0-&`K9ShtBuYb) zG$Jb$W!pV|dQsIlm02yOxb3QpAGM8HpKDAnQeonpO^VmuAd=}#UYFq#u3_0%`}P-^ zdgWDNuyLW0;{8>8iHwOXQH3o~RZG6-B;aR=xCOLqvj5Cub`xYzEHOU)KYoW3A+s6f z0>8g^>v!M3G>kg>=li;JK#nK?!1KNu;A_%w2w<1!bt4GJ07~;~ZlM29eMnJ|wy&=9 z>b-O)M+&}K6cpO~<#@${@vS5^D*uCP`Uv;a>j_=V$tLpoYZJwB3io#*{f@VR%sU{| zb6rzJ8}-2=mr_l?a~&xdy){+8w1rRb=?gjH8_%2)aNEm2Kng$Q@(~4ZCK5RB!bty( z;*e3YbH1Y#6`~W9`IFTU7K$&+q^P-|m&kqi+XC~C%gw3vbMtEG0^dn7(;D7m;A8%}cqI3`jgk%O5RWgVqSPUnG1HTLDu(-m*J%3N?C!*uca*8;WK-ZH);~bS%7Y;= z!JspBC6$SikF}?F9kn$~&94k?yGys|i~pf9&*E*PWN(-3&KThOrIBp@=8JL$qyfz4 zz@`@49DW!OGT4)_3&&cY@c*u~hp}cr1V~1j&Q#w!Jtw+x$}#h#JO&u3flSX}H}G}F z^ZG)w{e@OsD7^@V|MQ34Lzr_IYbmRZHhR(kl}B)pq*&|b9I%O-G%Y1N0tfM_;mguLY}wD8Y`RL08Cq9O&_nqYp8I@xDn#sqmhE16_1uQv4cmLD2R^CcG+eYkE#I9`OA$U6u!zi?d$&BBTL$sp zhps;Ju0y{o>7pP!fC<44gj>j+!j-R5KWCfKe|B8%^jpBIla_o@oTQF4T-3G+A8MFz*f|yVTwB`G+NBixQ)h_neF7~klh01F<-mgQu!}He zZ2@N@r&^1MC>}mW1!-bs8%Z=vVhF+!5~SnmN55Q21bS0Cq;(pASuwU%$`ice0T&@N z9a)hMo@UG~S3mUa+T}~c8~p6sPk!EF{b`c7nP`VcE*v_xGefv>vjBq;i8dLS5$BkB z8!!z#P(dZ)eD2qciV4e}pWPrK+Rxu%Q)2`KlI4nafn0DS{yvcnVSy{h)ngmWkd6$6 z=4~!PpTxbWJwU}SY+YJ>YEk8uG_ojDbRR{jE){#6wF`O}@+ibha+SJz9L>U7@KpNz z$?j3@4z^m%j_&JYKF#dK?|O1!{0~kXt6cEl0u+z>Qz5G>!X0?}O5KtUC=}{4rul9R}h!>G`OKw*^#PzCLrMB6m;%Qv&r7H(fo22HC+{pu4j z9&?P$@HrwG0>?YIB@IsnL^su=K8{p{^2 zyvu~xT%6)cONP>mUM=&yUM{5Q?rh_3@N%!w7?q5@qRHfBLdRo(2R+OB4B1QiY3M zeM_b>E_t$;)zTriO^DG}6IQU)s3ilD!US z|2f2pT+Uxq3YJm)dhVx#&dZ_~)hn}!>l5!eK0T!eicSNCm zxoIVVdV8HQqd~X~1b9xYy-1jD8$a;7pP&bY-Af zKKnRXXBa8YX3VXi^F&2I0{jT{8At7wr5)~J*?b7Z2YzI~%KAN+{Lk-H83zRVXMp6m zVey7J?^l69rEYASE~-GBrw%Ikh(~FtV;>Yph0wgWStw6>n;mYxj%Dq!E)M(gmFW06BBv7BIt#dU{1zo=MtRx}Vk z4%WA3h$6P)XtJn6t%$NgT@Ko6@1sv(kvXL|+ezKh*Jbgj2-f7?-J05wzHiP1k7xow zzyqZ_Q~2U&^A;m8vAkcx*=6YkF@_y4Oe=SBqY3aUiR3^>vo^91xrS`as3AuKl!pUl z<5PQH04Or5w%*eNC$-;CXf~0$sBC_~y#u=pbiM_P0oep30FIPBI{N|9E{+TkO2JHrtMsW9ywxrs zqOts}buTXVESxoVfAL8A3|+xn6vw;#xn|30(f%U>WlKzDE5vbjEfq0Kejh64Cj@Qz zvtN}V|!B9R;>ETK7uCC{(*^>eyj`moIDiIf*WvSG?&Lu5HlKHJFUlzG42Mo-AVYfeBjThU z?ye_==(Y*_bR|LTlUy@^jf81kA}>Cyvf5^cqXHIa#N0^*spCM(v_m(Tu%iC_D*Ic) zH%{iaVbyltg7KR}Jy`*=VmNh%Ud%1*V+tY`**JJa0EzRi`xRq<2z#|MRszNmTrgi=6N87eJRd{9Wn!k9#w{_i@>sL>8Yj6Uht6;+t?&5d%+iD}{H( zcuYoQy9dZpQXF>hdg6AMC?&UJ>e#*vl3PQC7|XP!<^HGk-Y1xu1c&vxbCCJ8_zQmq zVbPs0#Fhf9>4nP56ZvS=nMBAu_Q4I=HbA-WIZ*TarzKH@NBLbsT-+OR4}$0rW6PU= zlplwG^_+4>Zu$fC!}8P+tsX0Bl{O`#3S50=ee+lyyd(t`oHAZcZ(%cZ2`I+j7LF+%e)d&1O1%8`nzf1u-cndI}p9AyR zs~3(#w)Y2U;qLK0AVj-DHhaT)k6a{pL?hT0{@dL8Wdi;_x8TF~hb@BO^{d|wUSu(Q z%X^4_<-QkZqy6bt_VAU^tv!C1jmwsW$*)sWIl_$4vZ$ZEDcKCY@KTpcMcrx1TkX-e zm-AhhKXiCym%RjXq+BdB1^nxt=}Q(nBy?h>42%J!M6xM+d)388_<4 z1k5C$QU+H%T59y{7B#}s2~s5y{N$}NIy43w!8^l+_1%c)^aWHwl7B6#;qtkNza&zK zMnsvsl;IJk3y#%rI}c_GsA80D_Cp1lm;V@ByO)p^>H;X@iLQ*ff)GC8lrI~f zq6{Pd!+mS~z(?AWWx0pKO3mwnx~P1r-XmweA=|37XvE;-gH$KhZ@S6YC#VKvrK4gk zMx6c*sErBdmHg}_o2nYQ9FcJmZ`x5l8TxQ>@4TFX6OWv$csr61$u_9t8B(rHQe%}8 zGcDP0k?_;Y27!DQ`o;$OEQ|HM`dYJ?#qeA~bhIS0ATps>$))~h^e^vjW$JBL?x!~(Moeuao}H4a|J0}3TG zGNl)|@fUVM{$v&6WqBW44Dee%N|0tHK!G-Hvm4ULtbVpSt2iSg>P?nLNS&DB?q!g7 zN^WVfYV{E`6{#-loReef^0C83+@n%#yAY!YoSt6!ZtByX&QA(LI96=4k9*%&bEuB@ zd^COB|E!$3df|QKr7SlIhNx}&Hl8hm8jniIXpx`^8cp3BEJKp-R0r$ItGS54eG|e* zZLQ;(Q)h?N&A>EdtrXkF=vKTpx{$&OY8iO#L%eKk=skhS_#0399}=v;$^QP&2`zuz z`b}Wdy!;>9W&hTL`%@f&K$i-TvtR{6Cc!gv)nX%;aJbMQfNucN-DtjMB|_k`-Zc^s z)#?KT{CoP?JeRn(OW07rw^@Z-A8KYcR z0&^y@61$8ow)Oxgknh<;E`iDk z;wn98t2=RW^%qAnOqT@cX*)E*1LnXZW!6Si*h}e1scLtPC9tXKPOs{FineW4#|MJz$}Sb1t zX-0qnV$7zeuwPQ<9*y)HEOyyb(UW(w;N}UByPK>)xe^h#drHxXl7S% z+HV?nJjbAM&9QwpTS~L41dr#810^3#brSa<-$E$5_6mF_?50Z=TkB|sywekjdiDiI zH+v3ktp;R94N^H|TCk{`3CIn6Ll8z3fbR9F)q8OJqs6HupuO=o2GPGO+F@eRe1g~r zgbs|F?8!j6tmn}syp|BOy4ZCSq`k=COsF#cj(A6g8&npSG+S z1@d8qO)8S1ZNC`;M8oLWj9=oqUvEe%`{PII^!2u5og#*}sA(6-$IVoqHS(kVs5jEE zx)aaoH=ddzRO#Tv!)ohCu8gcS`i==uC~f~jp`>a4dSK0`&6}LS0=_&dqH#dJaX`!A-y;dF@fct!}COcvKJ1<^s`s0rS@S0f}usf{(hNZY3i~5=cos(6XXKdtEyh-Oh-6*w>c*F{v{+@C{jYCUAg|q@v zpd0kr##Qx@o-oB`SE(wgH@iM^pc}$*pl}!IvkL#IiZ-$UG;;q3+=+g=7SX@f8sBUV zLI8;|ms=Loi%v@PI3k6Z}bKZp(OMW5u3n>|o%jgKhcSgBzAL)j^zGDDB`t^|aqxG`q9LftPG3QQY7A zR*Yjg<(a6_{2pQ|6F)ym>4wNYNzt7S{Pd&`vViI@QC85s67e7KhtW~(ETk+{=xSSJNn95J_sKs zNr>|3D~tMS8a6^M&}ZvOc6~Ad$YTLHN;Z7a7w!QOyaN&rx)^%WQ|C^gx9(*|9_EPZbIW3?IpnXwT&~0{%_paizsR)y0 zE=p^TDEf>}Xf;uw;2Q#Jk6c9Vk`g~iOJVNjUKXzLEJML#W&^K1RN54uVpRsh2GtC8 zP3U#s@asXG!n)K2<|S`mfP7)y3RqHUroutJaBPG^fCljEKYknh|8TD@fIk<(n0%(H zIGibsV({)?jfuQP+l&q~5BC$G%l&GFTm%z^$+WO&QN%KzchldDpp=y-svqk@9`Dq} zRH`nB$Hq<}<88c8;Xb>U0kDTJO7Kje#R3I%P;8yt@Pp;7z_G;Ol zNR!D7&E-G=Q9nK-qp2gY!pD+lcSFCCBz_wd0lE1C%}66|LQGfs$MV^-1PlM9z&k{K+Jc$P9)xeb5U+>9Q~oIc6gqygx{R za>n98Er|Lpov7xpT3@wv?bUGcpD_2NVf4`_R~|P9oD*aQ%T8F9;?F@UeYjVZo`X7~ zO8PoHLPOJkgoJoWl%odUu{s=QH-9|~Oprv9C|~I6OgdBWUrTB8awAe!H9f}sYIRVI zQl6WbC}PH>e=B9}r*_C1vM$uq%m1o_C&q7pRR(##vRufPKC7UgtdD4e{P-lobx$~R z;IXnAJ6ULDVX_mntM8!iV8}w_z_7`GUze*P!z;f_TztrmIoz#@Pht6DoJf)I;QJ?> zyB`irt0%sHfSf&TQ$LLY*xu9!_Pi2j+2gRp&-r?=URyJ3Vmt*ct@l&(!BtT-kxmZ1 z?KTM9T^4e((6eM6n$N7t6^-h$G#pcCPaoXlbOA_7TV>VA9((XDK}O|- zwM=8W-l$r_!QsSD3;LY>P#XbS3X2*RF>NDKz+|ra7L?EmvUL zhLBb=I>4KYg|{3hRH@+%qkHGlw?wx!drj@cuNf{Cscp$Poks9enkkl6kMqkaXG!-X!4ZeJNjhnha}R}rcIEp&DOc;Rm{VCba)g}H~I zdAEV=hMgWjb;JQh24i3$I0A1?6l;Q(qs3FzM=e)>0%TUB;ftDR~xNZp!P*3cw<@DUT^LDYid5{v;0LRk#J7>nsws!Gg@ zqjBtyL0Y5pVd8Jvw?-FPCRHgb3fZS{^e)tr%%ADg+9RT_o5!8MJ;Cv*a^CNfDw*3v z#TgZ6Q+jEdB@T*=`4j?mH=9}q5l*&H)%Y`kk6|Y=&szl8!?kPct0u@~!lVPNx#u1% zm6LzdeNuv9!hKo~Yl#Wh_KR_B6p8{pZIk40x;K$@{aiSESTUMjQ|7_KKRFyV7M33Q zmXqWmb^exl?fC1Q3h3Fk^)?AYakef#U78 zuI@ycW^CzS$Rj2#ZEqe`}w<5h6Ms3zy2r}IWGz=1T(2wY|!}zd$ zLUU1@zoWWGI3}^|!;N>)*W2*Jcg|zke$i566#H?bkuoUb>;r-qE0PF2E49mu<3AdY z{TY*e6`61xM(!@KV4WGp>GYYSfi(UQ%Nz1;`Z&h1XM*Uh(`c8Vb{Eyi32%K0-pWpU z46Nv|$scTPPWc8nIrhZP9Isi)&*om}@^h`k?KS-*b#wuw4xfDRHD#4oCnM-%u-bUe7fo+zAX9%{XD{5xXxOZurkHr>B@Ku~Z z(8ZEEimQjT!Kv!+!SHyAmGSE}&37B`+hae7n4Mew0XhitOg4AtMXoZ5Uo$JA2Jsco zVR~V{{>bD%7|vG{o5@1bw>TqY(J_qx$^;5w_P9b7G<%D-d_Kc>*Jq{F=;q9 z*jODr99n&Uqj!|{SovS?Lj>~va1&q#pMtl#3YB|S!tgt6DKjvGGC`i$H-BsL{`nK3 z%d;v;uc(aOS-yDpEY7Kw3vt?B#RPh`Yity|YQbRkVm?F?)20SwCrN_JhLA35B3ZJ1 zG@aOM6vZWyqOph+blb>*Gk>FCU$TASGuO*n4SU*)7xTEcRtPEe8|fQSkm;y~olAgB z$gD5*;YADvS{PLA*#p*A6>hFg5>ZW_nC}y6a<^}Zs@}ro*L_0lKJ#4uyfo=~sc|`G z#*PqDMG@N!wy-tyq*p$&yvGXayBrCjbFmi-X3Sj`xQ4H|jkQ0VJbY#M5F0o-9Mv{B zqZk3TpN=ZG?(+tOz9iCsTx z(Ss$=;S*Mbn~iJQLw3ej!)lOQ#``)sl%+1tEs1R{`_JnqCchReCZe|qEhh%qyOPb=iZ4?nRK8!VMFI%=2h+tfG$5U8F$6l^cax=X z7}niqn3A9ArT0Hn^_#G?sGcgU0b6e^p5gv{)i*(;1PjfTlgLZ z5!{=D>aE3wR!Q{lj7G($!`@IHt=r;7c675zCoG>FR_6A{(|iyUc&Xh{(kJP z#^xVQ$Ke4@z0Sy8!<7doSx>5&LrhS^{Hwsfyk8O}G6y#B185|Ul&Xatw-vO9*a#K+ zNnszXy3dp(E9vDw_cNQ3g4TU@<4v--d*fZSV7(6rx^Sf5XT7fOUq`zsOR92sl-$hQ$1DWw| z?WQN;m5KdwJVnB=YFW_A!jP8fdezunCM!1*fA^u>pX%4UTAojiiUF0Cg&XO6#aX4A zMlgqab9tpw-+gd-jQyMEox}aSeCjkAihee^8U=G?|fN$2sG{n zhzVF8DqOm6QVEdxy&&PX6sxkUa#Bt2ED>B?FnDp;e5cXH>)2Z=o)I+$-L`HQayz`Y z01upgZ^HR1vuB|COlyz?rgh!R+iQK{)%q2{(qks;#n8I7Pj%2!(11v2`BClBWYL=$ zVSCg#hS&%O_f%6-eT7z9MDE?OI!(H&Sd#PRfo1mB0aI?vk>{4i^I7f$d#7glYaxO$ z{;iQe!s#RA$XC7S^a3sm^Fu9eji+vntYVi930-lgpI&n@yT%W(I9sC%%&9qxl1;6G z2UOurs(k03gmPqog4LN&ea;Z4e(YG@;sw?RBD?F?zGl2E1QIR0vddbY&yKR-gg@#a ziOTMIG_bOk3XsTBAa$5ti-UkrJ7YQ?yL=JbDeU1 zW=kdZr}%^J-3^Q2Q}fUjY)D(|eZW`oU7Tripyex|aeOl&_rCDxY_WLPrBu%KslN#LDXYjA^atexP7ipW zHjs+5F`lDV0Zp6xgR+au=TL|ZG-|QklC8bp8%n9>Bp|b1kA63ItAfGW$JAB&Sh z_bIG48^xUqJh&R&1793t1~)B_skxjxzO5jKRZwW4bkBCJw_|xpKJeOd)cj~}+p=9S zXu{VDm$dw78WV?Dz{-JXCvZHB8W!VJ%gEZXfILR-V#%kH6-jmIoT{!dKMOK!h+-uL z5vPC(n~##O1mXUTPyPU*ya75nlo6~uz$YlyH;1V3P^rnH--BW=W4j`N#OzDOALPPP(U zaRm;goesog+tqa(abTWd*PNL-sb(k1G&TJ*Y9-(qw#NPQCHin{HNuFe5jaBfAYu@& z3O^oP(6RL9UhkgPzoc0zGXvbc0l<5Dg#efIXauDbTaA9zIng)}UBR5S2SAQT_rEgpBMCxqu7D*V;D2uI&9IMrN4VP3+1eX4o;4GzIQxP{;vG`PD%)9aObUs$F~k@t0msXlNN(ubE1Lh)h?Aw^V`UYy0$)1ky0a+oTZ>D?Y7d zs`yS;A8LMX&}ryqq`f`&_M*LJQ`jr>F%=>WQyk}0W zHg&wJT|0f)7M_Cao%L!duciU$UpR{)HB!~Gxnlq-XY1>3mfrwf3Z&|oZrLAdu}i;# z`3KY{8@LUI%jB4;>t!>KSrrv&21z6xVc6rakhuyaODNv#CS_ix2#mvd7*4(9B1*d8 zt$z$*$s&3FDJb3H?)GItOakqFO<5Ofy1%E%!aN}wo_wizCuUQLa8yOoQ|4fA?}bivyp~2=ZyK+_ zC7RF1AV;);^i9x98}O~8*scC5ibgNRw<}ym%pFjqVAFvI?cA-B`04Sj>Xf#86&q0J zECs4y8LRgQ6^tWi1h5YRRgXSETQ`Ter31Mg9UyGH6e+&$_*=oIZEl_5gGVa{CR?qy z>+zD%?i>4BoYEsp6L#E~AwarB*gk)X`^Z{tvVyEl*yl-KubsY?jig%AOazD1fWO0t zzux^b^+ox%Z`Cyh2F*wQnPzZ3Ru)*zU$InTDnE-9mlYl|tU50* zVzu@|)E0iT3YTaEgr)ky+gC1S2v<7w;kq-Hb&2%BUGz3I)Xobue0(&Xzo}!{AIwex zYo)Msm%N{Lb81w=%gd*%KMr#vK4eJekh251ctY0bBV#PE`h#2M9^X~LBf@Ii1Os-Q z8l{sf(q>n#S4YjpNZp=xzx3f_@DchIv{1vH>8CbP?ytrYo9X$6Db%A~<5?tD0+#An z6CBM3X`G3i#cW$QQL6R>W^S0ZFi<$*?)8>g=Z)YllHEByY;>{4aI@hF0%R9R-__3m z7{!5@jz>4+Em4BMK=qCtJCooCIP^9O^2hej%<;;ATyqu$dY5M}mJdlN_ye}))sgs( z^n`g+qpYK)o@uQ1=O|ctmjWn1X-pZVgOGxZ;JRWCb}s?YCdd8)Vaxn&PpdfRIb@;H z_+k$W$WI_JDJ1O-IYK|(?%L9qwJ)V*iTYQ4zY`Z`CwVX_QX6P9@qXg@I8ZDcvFRJq zCw%-|U&0L+M^>Saswc2=l_S2%3?$r4y^4!4HH#HNViI$fSvmktb`{9(1!FJV?$61@ z_2^(P3^#6mq*kEd8`9QcWKUWpb(L|bu-9z+#3+|zr&>8{%)YWzOkVW1VB>VG-jJ-o zTI&rD_}ZZAxCi(JKqQAF^V6}T73&cOfhpO{V$W2eL_n%LCj8f>I+GfIUJNd_3SRX4 zy0tbebU10)CtTSX%(q|rRUQAn0KX4c*ffH=f*)?7w`sX$_NfAIYMl@oL(8)!{lWrv zey|Xt*ch6ilQ%=eqLWYIMa6FvTpUUQJ{QF@SnD)MOD$5+yh88Y#1q=d;=@h$`39IL zh3rqKiUY|V5Q+$`0Y#i}fTmK2y^M8d{qJAWuoS$=WBhZ~@j@lJ)oQuu9c;sDrM0$S zVB)A~393^x|86heyEma9sbQ%sDfZbVc`{$IQ=zQ(Gh@#QdOmfPWyhYh%9g$av!G38 ze(FL0xGKE%SNt*>X?3`kHYw_W0#qWyb(ked0mZ2-{G?up8wiV1fN*yefWG!ly)~4x zBXg_I931R=7^p5`b)>GZPg&Q9SQkGG01s+hlO78Bx1eYs+wzZ~&?O3CAy_XgM}NOh=_h-h#xDXpX)$Eo^7Ip(ip5LIj}md(GUlj!?S4$yUN8|vxQfaGnbr(?Ap!z1v;52`U^x@C3uF_4+D6aRGUJbUG^!!JF>KGk1R>tB~rh5mWRKK8I)6SCa6SN0tcD3CeroHc0I$ z;72Z1$j%wD9>y*45(-{Ddd6j!V*z5%!t`@ngvdu7FL<@cgpra`ur$k?kp2o8Ba6tv zFg`-LXv=Pt+ujfqx@ZL}&U~;>5Ag!=;=Hg_6-$Vqre68FumC+0W0VvpSUT*}lUl!-rE==YcOq(@=$g~8lClgyK zJbQ73YynPX4d_1(&+?fHuzNIkzLu#qP&#D)XoXv2&$}1%jd%tOSx%gb8#NW*#WJ}2 zNG%7gFKTJ3OLGv=>!Eok;iz*yg*hlK`ztp4)xkcSw+G8C$!C@$@)6p2$j_15Zt6SH zU#~$~9I_iiZqv;k>D$rOr`yF?H;O61>NGK5#dn6)TZO$x&Yjp##;WFMF5Up>!12+z zh2S(AyF$_M(-8Lb8wJ9EHPpBQNJB3)PAFpcJ~F%3Rr6@;Mqm(K)5jIV4xSF^f19P5 zpzWBbbpQF}z`rJ$vSVUKkxqemZJ{ID@NUH2L~@ zO{J__QgqU|DpGOj`EtYwWrJ=(!se4mLsMMyq(s4lDY|liM1}j$zyEB1)n;X6txz|^ z?ak`J#Aj)w{owAZT-w9SK`thee7FFHg~Aj7tRO%?omB8$sLWucUEAJHzN{XK>6XD$ z5?7w}5&;Sg?>|WX?f_-~8?GO)Ig!ePj+?9eqdI*<(z@pWP}BOet!*q4vR#&w2MGJw z#|)?SMG9#jYloN^K7!z?K^yEPM4;n`Ww;55k9!Z0)0o}b+0+(_JJc6i$~fKu#>d}J z3t6L@fb6mZ)8}ufv+vcH4i8u6e0Fg0v zf9;u>>Mw*Wr2rgDceb}1&De4;;w@-CEyr~xjJ>HBb{pd^u_nNE*BE+5_vOn&C`uu2 zc%k=Bi>0@FnQbi|MO>p%tnj-DI(z*ZA)aEcp=<0AsJAkv&x2y~qnrLEC^mPz3_bX@ zOofE4wSzfo*z5`e71>K}Gzg`}geZ|My4(K!NA(ELK6kr|GV83!CjYxPo405rbx8 zxg+tgwbY~$i#rjUKPa?X)&}XXQ%KsOvhuCBlrkX2w?A;NH9S4XlP%KIbH#jY2Bc<3 z>UI|LXDYZd9e?N>tF(}NTjsn)a>f4iiGx*yaxFBAICOAz- zn%5!=bY~msm}m$RH(`_9d6ne^7j>fLL%=OSImp zgZy}A#Epv(<9aA${e=R;WP4-rD4DXlZU@0e?*goJR_`<_p_^Wl9fu@7e}VE@N{tLH z*YAm2pxDVeHcR=}!^U@a;qV7M(Vx3pu#pL$Ea-y&n9#|EfVHPvw13lHEPE{D?81*Z zk56?Zcr9sk@tlWfb~b? zyT3VvhYHe5+qJ%`n-owp2Y+V@cqaB~Jn$qu7Cz>- zVAXAqz`CM0i27YxNv$jS_B4(Pk#GYHei$3TcYhXz={d~uo4ak}gqlD@OG%)2=x?BN zd>z+z4UB~yu+S68L5A@Ix1s4^xwSyn#7gh%+-n&U>M`Q43FprN?Y-i9aINutd(|SP zRD7|k?AuB)%YMJ;xc(|M@A6DCCpVjQuKH-88Z1A{3?K62s1uwO+ghqqB$8#6phkQx zD(t6uU1e$gHs#DHOp@@aeG(J6jGq~bqtjd^6S72x83Z!+3cLTij{yBI5IgkH0+q2FEh@$j4 zWBMQu-1MgM13?o0yhJ$%6EDu;6q_#ko0yeAuHw>;KbdlW^4mo5|KGg$+`-AAv}aQc z*B~cJ@CEBTi_5ahKgqrzHKjz!D4s+a%@_nLD?T(7btUY<#QqxT{oPKEnv7s9XB&j+ z-=#xMRl_d#=aFV4i`%J`4o2{jl5dLO|5budGbWOELJBwJ!nj#pJ5k8M=La@W<_{m zv6qz;G#N?~LH5*ly?OWK?Y2#9p_gz>)z6uVo|QJ!QRR*8<0oTCM8c?i+j&Mh0`B8_ z`-pyhZ6ChN74_6v#$)spYh-z!$QVEk!X@mr0c8HaA|0)tCNZPysE%8@C6HuODS^>@ z>dzK_ag9w)dMZB>1G3&$a)y!z0*E8Gq*ms$d|`yJ5?lPd*U@6qzcUsaA`td z^#am}ORln@SxH(0s**lHzyKY3wGXIL5vx9}|1YRle^ze)ciW^zVI7+mbI^mTEAE-O zS8G*wMBD%c{ZYxo{XcFj!m#%ZTnbQ2JXnJ!X+10p>|bqZ=?X=@g=LOVF1PaUH5Pq? zqUCO^-Vtm7t=Lewl2Th3KQ~F@Sw3mbkSa9D27$Frn6mvrxIHr`+MLZJAs_ark2iY_<^ z_(vJ$BxkEmgvH-RP+(_q@H^aqG_1P~@Z&iHqJabXnnk+Lg3!OwBsKo2z)n= zLvnI<*U!UbKlX$pfzV-FTN|f zFMsp6u>*)DPMwUzZMBeR&BJ~EI zAyV0|fz=L+(K}m&q*r|8^|%XK$$fR6=aPzQ{bs6UVJ`wv2l)?~(jU0M7yXcjO|@$q z$WAo$W-wPX(Mu_u#r+sQocdcX|A$roQ z&*he>BnD_ixM3R6i7KR?CH|b~uC{U1mHI5okMTRXyc$@WO2(-&HJ|XD>KIe3EMvE2 zd+_=B(K^WkY>-4&by}KdHiN9AI}=MQho2b=eAFIGBQe_%zIQRW%6v>VcM>!zNqdRv z`P_|4rW1)4$)O)~v{02_R%~JNU0Muj1Dhsz5LC%B3`#CB_x@7ifwQ zdhJ`it-`R1%cy$EdP~3i+6KY6P;COTaib4BPr$=J@nWW${u3b{<9Fxpz9Cv%K>7OL z!!=1Rgz7&+|KCf-Q+urEHy*QRW;YT-ZKx4(E=LXu zF$tK(iWO-Obyw{-59Z?gUW@{k&&D+iE$lk5za)xM)cll>d(4E6gr~j=7r)8A8fAOT zs$4HI0HV}47w~3a>Z+Zzq`EDNDnXNDnSF7^yO|ABGC7dk zjU_ioG~ybv7F-cRfaeuR zE^rhYpm(rz_#NO}n_4GYJUEW0qXD3(Y&s5VpaKgpWos~R ze*@W#C$OCW^~n4AlZ#Wrtx$Owqf=9G1z+h0PdGw%vhgPi ztClL%&g*;fRXSM~eIN4CXYVdm@xQY|-kZmFbfX%go7j>GAfmFlitS_k$cAZYe?2`; zE;I;8SFV2`YcgBWYKtS@yy8=TYFFjCdesg9Q`+k2X5~Bq_zb-5ikkt5F;4$G3V^I- zDdXRiAA|R2STukjn{P0%?o$Q-S-Q~0<@I9mE)u7__1ikz z_eE(;4xS9+lJzk>dws7MR<3k|YI~Dwp2M3sVh&v*It$Jh(gu0OC|k%|UlH;>Q!_iB zhb!C}pH=VS>ZIAfW1nUA*DA0*BNN9E5f&HZ-%3|VSosUY(3fc_^Ob?ZIiq^XxwLI| z%3p7t$lv^}qmzYz)M%}XIZ3$-iM5vWLKM%lS=EDJ-NRq;vQ(j!tFx=yL3)`GyJYEd+ap! z4(M}EZhl*JZ|pgO2vPli;0Yx*Z;+;itXY33I>S#Oi;g(w$+kspZfVYpp8S5$dW@ae z1m{@F3XHW;&~8Q8)zpbyxgG19@V4%~=-~=IIzEo6IBgJbnCRXl92>4ndXMBhv@`%= z@uPi-JOC^lwdNN0uAUy=mqz=K~yf3f`qvXC^`pv8!31Z#BfgjLO2IqqQ>jQFau+)DGWc=|l-~~_c#Uqf) zKy_d?h*{P4cpG<|qDdk4?5MjW+uzMYR%$514io^xZ@dB=y@IGOS4R~R-z&DRUe%rJ zf|Q?CY&ADF&zPRmM;U#U%Zw!fbNFiAgSMT_TBrTV9Md8J^9&v$MeTl#uCX!Vb1|fZ z6J5mNfaQ;k_gMGD6_aJRCYR+7-3kPt3*SYA}R8(VGmzBFEu~m8i+K1gGDZKJxk|)o3Q&1E! zf4O4vSALIzR1L#I?&04qaC%2+PB-JiUexwlE;Wg~xmu3*b;;N+UfG+Qy8Wh*&SAP} z5mC#L`5xb-ll(I%3~3r|Z!?BACO-jh!&xgiOaf^dThgUKt=uIqj{&VTAA~TEhLqdA z2k4t1FHjkD&u$Yrxn3;RmcD|pO6wHwjqRw^2dIDVQK^@icE~LHT;yG@kXMv8z&Ag@ zvY3G|baQNz|CP}99b}DZrY-JDL{r33z-N{BpwSVEwp5(c5IjS~@+%h4inW^y?KyeD zM!Uj4z#G~GG2GAFnYsjKb4@8@j~7PuOr3KZzN(9LA%lC>lWLkKTdP~8d@8Hf!MG~L zMtU|n*du&XZ>?m5LJ8XvA)nMT99Gm^kt|#$OH=^l=H;*wr}A`tLWv4gh;u|Fo%BXK zq5COp0Fi@tR7>IsHO5hzlgdHu*OU&xlw2pT%}w(R-sn|$`)+$wN&cBdbz6Y=O8*KH z#~4Vpv;4a=k|Pa5D@vi`uwRv7M{v|_mJQI=oU)wK?Q@)9*Ckdu`%Fb+QGC!ZfS|lO zw+a`79*kewF$K+W3)@ZgYikob*4=pN5V+LZs&!#UJ*NOA%4IuV(QKA1A<%%ZxbxSA zRa8aT#$gcq;!F;b-J;LO`7y+L=%y~X?@TOFwwYZE*1QMk5@%PSb649WWDa=S;M1g4 zZ)oqrM|C^4%51vt3#0*&(d3~u!2f%;pZPu4yS3%DZFGKn-PCdR(M^7Zss&}7sV#e__71HZ7X+0fRg>Dp76HR{3$ye>TH?K^T(4xe*p=GxoJ9>KngaiffeX|YGGbP}On+TOPid#JRjoDiPQtSzX90Ff7)qg9 z%XG@5M`TV*{MXUl9BZ{J3TL}3T!fGJhqBIZuW&AFe;|5eVD|Nf9_(nw}|8pq0LB&Jt`6gN*ZMe(5j z`sC@aON&d#zo*}JPrkSBv{2h5GfC>Nb^`35o04-WK_&Id9zTi(IxWZ;2N`A<`Ndng43Xsh2+{1m2leOT5AZm~l z#goOPEG+-ae!i;;;^;0M#ab>|OSQl)X_*c6e=B#PNd0*swf=MVYY%co9o&oZusT@R zKD{pfio!`ECu#Ot!ExRt+AU)oSwK>)vZx|~IG9Zn5w!70PW%IUbpyUyQF%n4R%9mm zE%5X;N47HM@b2W=8bJmaywITiOcjsoqL_!R3$)Y=izQ7HoTeRI5M;@z(Cp}wo}N!5 zYBet3D6sW7_^l|Gw7CQ0KymXpetm%8$q@W-a z<>u2&+~Kk$X{P69oC*~ioUXn&2h;7%q=#T8<~@UlL8@1y2X=(n-H=AmjeX#$b&$Wq zmpaG$p(&I7@kH7&7}9ZEmHsuOA{wYamRBGYrbKCrQK!%rZ2^PLmUGI`h?XEBCBsju zOW7$LTptz~fV?zdGbLre#*mQ{ryfD+$G|vd!8qdaOG72b$C1*UYravHgL^F_jF7Q1 z#f(0dUpA|?LFn?bS47(2P~o>b(`fDIcdD4$)1*67K4kAg;wtQ@N^`VSbI?HoXh8W= z?QeKP!banB!9C+^j5Z+QO_{M)-`W7e2H>(#e@h0ClZ#`IL=M_ja2QlV3oBx@s@r-! zTH{Qbsb=R%nAz{GS4+&CxMtZ=>{8vmmTr0&!o9>Z<6++w0?j_qk`a(L-b7TiX%Rv; zIej5}K>1sku0Me`gj4^i1w-FbGR?~(myIZHl8&!?jl5zCg!$HJPZeJ9fg|&%nHdKi z3Y;*LWJ;-gT(G>X3Efs$M`!r04A~rWnM69%vw29l;=oKVMgbs@`e8~43 zL<2-$>;yvZ8sh|51|RpK!#3^El`_tX9}ScJ4T)Rh#l!S2@GHG(Kqzg6?fx)(w1h5! zBXPX8NQLWWjzu_s;cL`u>}B1A)SWFF=zW=Tsnl=GZQT7D0X&ozP%=QfI3eHH&^x#{ zV>wLOr(#X0*o^0@@hJvH5_|~nm-z@Y4LY_Tx5;(PHrbu%z7>EQWcmVJ6&E-5#)NtX zi_8K8`yd`X#6(GB*0Va37daQxH=1hV6EtK7Xl2FFftr6P#+ClDGybHMA@AQ6Sz^7Z znuBFospL$P<>g4Dh>T>rkjYW0>w!L#SsaSDsRQ|hKYzh)cJzduHaOR&9V3Mf*&Z2P=DZQf@twqNuNM&m!YCo

    nV|?GAW^!F z3TQ1&jz8fn*!wc-$62(HZV+ab2B!6t|KZw~N=TE{e4w>;IvXN<*O4wcWzkOUv_L+A z{%Nt1Bw}oNW3LZTGQzEJ4`BW7o;9UZ+xVFh|A0o7k)xL%6_u3Xa!<$RAGhcGM90RC zF0cv%1>?Mp3jM$D=V0jn$9?>_|K&_^gu6VA9E&5+2HlMOswB!Dq+mY%$xOy%vRwQ} zyunOajadga4bLcm>CJb#^N0*RM+OQ>;L{9mH+V4Q4iPBr)ZJ%M!vltot)Tk3u!9pB z2`RVLKVOf#RTkn0MB%`&AYjtQk(oXN%z}*FuqssH9yh-!-zWd+4KR9gAP&j_#CMW_ zSv-H=JMQj=tvP(Q7%K2EF+QQE?-X&FX|`2y$O_xjdY*i~{LU~aOY{n_OiwxE*PT^4 zY{Zmr>g?{ZsT|0liJsHpF^Z-#L`U}Rl;$C=!r05s1pSP>DwE&dkWjn8`0ZGXhxhU$y zhDiacRy_6NQY{2VnIAIp#r^7@QBA`2%u@Nb&TmKt-52?eKeT>Me1fTWN_dRKFDR|z zk0sA?38-BP+8os_@~O{!KAPpjlVtw6q>6B!l$7ByRO&^}ILT63(3ogD6bWmlRglZV zg&xRc>p>m@CHh zkF!CAW8OaqmlUi?WOdyIBSxiBwzRKUn3QLZLcbLiEv$-`lS;Xvea~&NMn@f^&-Qir zQf(UGMO)bZy?$DarlwO&C(_W;tAt2B028YoqUjkY*XC|k{*_-F1^Go$S}Fk<@$)Mt z`fx7Vy2J^0BYua17&C9F(zh1KU)9-z5om&@XeJfbG7;^W{9d^W^C&2o>7$ZQawOnP zmu@`2)u8li7a$zsFj|OzHmVN{V(L@tXdzmhc7$&y z&dRy7aLCk2DR|n;4uxuNiIe*0kc*Nrdbrbi76D_K9Uh>^7Oq28o5+{>D%C+XzQ^TOzeH+&E=l=m+}K zC6V1j0Zn7OX|uX4rVp*RZ0~`TOh8oQ1k}eLFya*+gHzXs8ZY^T&nw}U{>$z%~a5&Kn6 zE5UuMILB@LRf`5W$6TTun+v`3$TGcf;xVtr9Prm zLQi@D2r2l_9l)E4lpxMuxWeuYk-dSz!G}G43o0B^S-_bLWDeFZ`c;K`+aY^C0&g>| z1E23g0tUVqgu<96onO6XKy3I7u!qVZ_rJ35QOmT_&3#A(0_xPIT*;`kOs{SEDA4}` zVd%og!yi&1w-~=?9#QKNLe#5xn$K1Yn4XSii{2a28*%dOTF^R5_|_O4>33m# z;xQNN2GEuy2ByY979F;ANr*#~WY#tv$AY9HXPb|9at~5n^x2(f#mNyWv>6Cq11F(p zT*J0PN8;;Ra^i&fs&9A{SJp5>T>g$-UrM@MS z#2>Eu1C(>Ucp1aXvY2vX4A}!efT>-Raxk>K&6cnk(EZ?LEqFJ&l6laSS9%}Rxi_a{ zZ5XAHUKVjg)6pCD)IRYPu?)jK|}eljc`!!p$r!}Dr)Gxixh zjgE{IZ5~qgY3R+O`_PSXK&9+);gbc?kw%xr40mMrew0Fs6`>Dn%i8Ds7GdWOGQ)|w z^ZB7K->YRcEy5lT8cI*~3>H;fxER!q35A->!%WyStN{neOq+v8A80((`18Q((*CLO z*mYT?nMnB7-r0ArieFUU>5f**;f}dQKBUMABdlKsf(~ol3Y))2!?Hy8_ zxeCuZwa0f*fC9M%mm$8XF}AsXS4)%PR7|^Ri(PkE*-5y#?I@opI|dH3uPL3l za$_V&K~&UptCu4jUE1Iic1f%KTaf*Gg7`me`D&N#o*BwobB@MPAcro-0zkye@+tsA zJJhpNL9#o*cFXFselsp5I2PGXbI0;z-X8XKc< zY07P0;LL%{3jV>{>YI2@X3#5|5jw4k1$)v6nXNNWuJN+=6ZEv=r|B(7y3_Uy2f|_K z%fCSLa*)f!m4;%(s%y(|*zF>8wGaS{Kx&yGJN=9BN48t7-_DBv)7R1nDI3M(dlO3d zDRCLb*3|z~3YDnfM&9m4R$nVPgsz(qMs4V{?{~G!fA3M&;OiX(yUQ4JmnOD?%R}D# zz4Iw+8v3sx7w86mb_<&WGKVg?l@H)D0Zj0&#_W5Jh02wH&3oeFV=0yQg;DG(eT0=| z8JkSGW1NhRmFJnNCTS`_H?`6(J)B8hD@WpzAr)e7|w%Q2tjunrgXm zcI*n5`Dqrqv9{_f&*|bsdENE4ft=d&sqGN-I{qjnS zpLGuNA|>6=_~{7=`XP?l+#8;8S!pFwle`jj*2SJD=hPB1sWIFQo}64?5L~TW_@3p5 z&LB7O0gt&E^okD|CmJbjdu73aUb86~%`UEZ;YTU~evKHq%lAY6pES+S0|f|#RcPjf zS9k8n4*tM!K9i>1yK%c|iOtHZgVu5Z9z*{SkihF=+$YYN zNa1OieA19995ZbEiIsy;R75M*->v?u9N&U#Thvi`rTZ`miJxrMFZQmNy@lKAvT8v| z2Ym+Gw1NdHkDpBe0WO}^n>{EXJMgD8#lM;kf9q<<_WUW`&A2x!yT51cSYAXC@$m(e zQRUCRMOpDr!BX0-R!&k7t-2g+7jfhtwE-fLS78Qms0XS*XP-HRGfz57?{oB95XggO zj^5#m+*-SOH{5|$P*5ki);fQ2*o~C_J5$^HXwqs5a6HyWSNm~$G6$F>Vd@N54VEa^ z9twPpyItTI+qofHU8gZ&NS>w2pVPtI!^sy&x@3!8Sc+!EY&cb^A{Y-8xwesVEGuP$B_{j!eQ zOIz(V02yg0U@T?wh(p*!+CE54yrWPGfRZ&seqN|hc(f`S3>IX-kA^Ksua6EiNR`U# zA7F`7#}9R6af(5X%$KX^7;1lA%szs{E4q0Mw)SIiF zv9c(Q$_0X7e2u>kCfL(`L-Dn_`gAnhUdS`Zv_m?L30V4i(GrR9bh3Y8?PXk6UXjtp zSi~ex1X^11Ba^=;-pOb#Sap{F-cMU`(e*Z!U4CxCExP~_haib%O^mj$ zMz+hpj&B&LUv6V1P{57}2may&Xc~?;0tMq==*GXZ$8c|RcxXHLFA&J=_o9Pj&t+9D z6XFk4mBqIcfPjeo_p;VavKDtwz!e8W_yDAVIT+=$DiK0brfX#kC)_wxo#zpaRL2X- zKGajOGhi6yH-N>J>n00?YlI!QY5iyPJplxI)lm!m-+L6|<;jW~Yel!5UGoVK(m=a) z?NIqybF3ocE@#wHY`EzanUv~jHVn|XI%I*shc&stVQ}(stJrlWucj7pv=Ko^iu=IV zC|f!(AdF=1cz6!rvuoz0Aiu`8?mlV4nMI%p;}cSNqmGuV-XG+qoX97S&(zmg(vI@c zest4P;CG_5f>1Q(iL1Ztd$!aUEjSQM5V}U!be{>l=A%sLv=r&Z9B6kXUJa~r@(^ro zRWh@V-Cxl%RfxjKp<2DGN z^*P!sEXQ^fRlqZ*+G{t=M;vGbyFg)TR3(-a(b!#A<@US82mOsayP`hs(o!r_bmIKw zt*gkZV{67}dsX=9@7&)@wbZmGq%3Sk$Xg2%!U{GmvDS*S)3^8q z#XuhAdN3j=eUCjBRzSlm?&lCHtwiw^10i*kXIZ*zByPc?T?2MwEvL$5{x_*}3-3~0 zd_0Pu_eBXSudf~!n(0pDXHqX21j{Y}?qAI-sqj{47q9UgP!|EMwA_ZSl~IXI__%?O zrFyozf8D92ylPRTKZaXUZ}+q7FZ4G$01E=<3;_f3Wx4Ca5Nkg75V^3{gO+r^y8#bRhJB`WJ8J>X}MD2Gm%j z%$UbV2feKPDfT9P!T{+Ze@WXRyhowWkFC)tuwjKfP7!cC{g(C8TAQBc%ksp<>Ujy! zv^xbKSO~K{dKnk~+~x5N{gz+YRs54ZYh@iT?Pb2LhiO9Ke7{U3V?%hw;=wGN3$jM% znc}I6lXH$7dX%$PAdN5iGvpUymG}dl`k`6XYs14wY!b~O($!%&T&@D6lX*{U`QCp< z4D_U18>7!KFF18*?-{8)z*$tWODnufL8Xr#poqaXNB{1lzWChaBA8Qi65tcUeFF~e zm(p9A08-hz>^X^&yr@^`KvCzPVoOXJ)BardfCwY&&bKrc5qnva#D$mnWAo?inDQ?P zFj2mDX1OgivgX)-QnVNP3O?zJ>A67GqAd7Ps`Fs1DzZ6{{fJnJM~mVeGNU`JBxqb) zmn~lxrj_*YDX$B9_~%Lt+PnVJzi#&kBd#XFYZFjcR2a#|?#c zCy}tFJs1Kj&EJ;nb)oQ47bsC#9F*I!TmjksZ4{2|XH4bl;s!rX86Y>*uI~NLy2o^b zBlkJjuN4cY0$#bGmDxU0;5iJ>==)KsH;9n0Dy+ODQMczuXiCAM2ve%uG z3poUka9k&`CuC;Z`BbpAdc;AYNqEq`otf*6f6^mByP;CKJo;{o&LMss0Z?y+eCo60 zzYq@Y->z84E;48t;I63itfn?xF>-u`zjj`%wKad$NgXUKT3$hKNKi%gnEV*?LkGu4 zdV7{PlGxCKrkbBt4hbP>)S3N2qCX34BqQHm+uVZhygY(&NZ^WSrl(Db9V;%fyO0y? zJtXppAO7^T#Wsb_(y6$sc*qSPMUV95vN)lMFHWOSqyLyEB#Uc&%{le<3b!e~i}90V z>WSp?Kxy_m`Nmn_n-S9kyCQ`wafr{$lbC@ggzgmA+zn4TMW6rKdy8VizEaqpbf`3o zk&vTij%_%39gWxtW>MZq1pPY8m~lF4ZDvy^bj-DZeOekKPv>g=fRA$AI26-PvN{Zn_9xU8vtnV;Hu*?%Wm9?ybb{*{+yHD%XApLr3EZt2~m*yE9fHznJKdQK}sm87fPka4v7+`(ZuuHt_X1{xHJ;D3)(0Y9TM~ z^`1H1hG_7%Pf@~H+P3(6OafQrO|O1VHHEb@e#OK#XYMH_(lTe0C*!Ou2nR6w4&TM! zLJ9K34#^|AP4?-ZD#>+L+bJ1VB~ti1I|&EmJN^}7AbiLLGGOE0j_a2yk2H-HrG4Xo zCJWoT@xwEEc%s4V%s+dn|5KR^vt{VuNg;He=K?UwGSCj4zf0Y<7x^>os#->`dBo84 zqVmJLo`_nzI>B7FC+A3$tvlez8=aRaF|?4g>(~&N4G0!fH6Z0SX zlLo`#KJ<_0ugs;Rg&df^e?LZ#eY#Bsq`(K-SdoX=tEiq2y=@jA}+g`r<=D>T6+@ZA}<8 z%Fr#~VCWDZyc+uqoJ<*a4n)~mKw-;2N+<%llL%dV7b{o|=yB;rq zd#%0!Zvvj0TsiFnCWX4R(d%vglVc~{K9Xmw_^&%HZyy&J28i~ud}k}fOjT9 zJ04ZirZ6~CrN}D(#3N;w*cIK=(8iB5_jq#t`RIoNG8@(>J(Uc_^hUs2DJaX?b>P6D z&K)yX%LD87TIK!(3m&as|L4vhzyOQeFSZUa>IxO)INa)a<=x#rJzeSE7c$~Z9~-`< zip?<7&#)fXRnYn9(&#tj(KvKdCyrXU)Mc0|kiJlUYVYe#CfiJ3<+z?y-!>-JM~Jsm zeH%P_A^A0I!)VcgY%{V{31j;wh2hXvB$@K=$C~2hpD)`8~NOK`}HE$md1V&oK67z`0n?ds5-PBK&cnLK;u2V zRusD;9U9<9VH9$agMmOSLp(stNQKT=+zIkTto;kLZC4GP`QIefCv@b@^r$V}O_PCq z#WzH6^@1Cy>jQu$z$FW?xBb^s|DO|!*}vr(AiF=`szYn$aYVkOA?psVmvRYU>6W`5 zoZ2#D?;0yQFmk}FXIvTKT2Bi&x#zM}PZd<+Njq|y;mm^1oq-?GR_|2fU<`k318!1f zi#_mwfxkd>z&sOq%?Y4R;{F2B0z1ln55~RFOD5=+IOH_{kL}8^DB(89&Jy(82`(!f z4R{v=VdW6?4(EUIDRE9%cQ;@dpjDKJWe&N!1u*NzaLMhu`Fi^*yoMrZ;bRn~nM3D; zxLnE#N#n+1y?dRSns!y4?ZWJo$}KNzGQ=va9k{L(fY%MR=>LjfTguxqoBU;|$04BP zr~Vk^zPKn;tzZYtKu@2=SJu1UtmL?=Y2nbzV6$nou+ z2~Ji~w7oQTMg_f7r_xWu-PnAy;#eo(GPjx&>0s2ooZra+x$T8$nV#W?yP0!e5|3uH zWT4;}(oS-@WM6+G#muj;P{}E2o!iWsT;HDDe(_Zdw-jrXlOc{7F~y`{Gdj!eqxK4A z(&0_2c4KO_o>8QE-8Xy7W@mFtW^_qO`IIMO6px45t@`~jJXIsNRR_a`?-vEi$jlX{ z$A!c4tvw5HTAs~{1v;ysRC7Pg_p|0nc1&k?3#Jka3 z0;LaUbx1tMZ`k&8;`G$mai-Y`e7ENo3YHHMo2(ap-ZST^bNV?&i4U^yA=hTv49&y@ zixT?2xSuo2$4t{CZws0{m%T~g1#gS}jt!3iKZM+=`pvp8WK_3l^WcXaA4=8;d=_e2 z*XU%O=NrWYA)k7GktkV~^1`buF>9z%l<%R@@TnF=$ZU-&!3b1Fi~jX%?v?lf^cp>Jf0mRH_VniNuM-LtzwQfE#AKAWCbP1><(!%8R`-jvSR`JNO$>n&_i=>qH;^ z10zR<9CWQSXjo=LQAAyeNbv8$UaKQq2Gcn`PO6YFbEIyI(!F`i8@2dIIrJ+qpmt!( zXxU9*C#WtP`{4Dyz^60~bTjVvBGW=iNwF%%`k?pT=`wRCb%0ygZ6)Cwb_PsBtlE*8 z|A)G_j*F___r(WkBoqN@P(YFHPLY;|A%^bmRv1E2x&)*_y1T)lk?tJ2LqNL6-*WHg z+1qEIbM`&wzJ9O!y7v#A6~nAGYu5UHKk*JF?h$bm%?H`z)X^#SNI@?HN079}E$4ir zoxVuqX^Y#Y+u42`xd$EH+J@DHz3vk<(`{`sdt*Z!LH43)b{iVu5Y zkMn=a5`NDZ{=3WnVn)-TgaiH73m9xn8|>N?{ew-13+aI!vjQWB!TsB$Mo-w}^P4XX zk-ru2cUFIb)YA__{sScESGR!pU+6}2#d>&%mk40sDUX5f(6!k8PsodZd+%QvDwgwZ zIzxc?NA!{$@R4>~h_KocvIsc@*IEPTOyG|%2?XFCKA^UPP2WWoPJEFe9zuU>+0#PJ zu_W`UpN6^JZ)h;^Az$zCMavFs_7QY=47wBx*c^gu2pUx09&I|4C$&%tfIIyjinQzhLM~hGwv9MXXMkLPs1eq!Ttqm1`rUulGx>W9>0dmRn zyKB)~4I5uBlf?*i7B3RKtk>Ip_OaM(P*><>VNIcv1J#|o(w3&vp?ZzdRjk=|5$HSGO=Bjf6|R zR6>ZAB(c#Wlaw|~k)w`PSElw(WTPJ+GsLBqR^?n3nPkt{M%Qu3mnin-jS^-W2F^MP z7v**l6O3DFBZXavJjLMI@z(ZT-c?1qx*}Y^MuQy@+36oJ(o-IwHbfaan+E%u^n7kp z6mAj3y1>S|#}Ebrof7!1+-itqToXmig{eT~t^?@$+FlrzS36_kI%u><*CR;UIs;a82chI2OT#^P`#Put9eBj^BR>qtZ-^ILN6q1)R?0Pro#Lv0Lmv$i zR7UZB@GupOAx0FnBmnmxVVPh-FOT{rToIChFfXFIJ_h=$Bg;j#=OeRoIW5gLeT@GXU!*DXQuBcXfW?3yDD{sEd_jUj9>9p)?!*0$G9PhAj9OAlv604b5_@RP0o4xx zG&g|^AP!qa5iNgRbLCRm2fC}zS371W5zsckyPFPr1_Hdh@qme2`u7#ZNg;#W9o`Ef z7rM?E_?)cAlVBv}N9Jly)D9xXDXyUPD2$P%kfZ1s5ZV-hztwQp_JM;I+9Q4 z{3vH<-?HXZ5K3Kvc^W>jHWJu>|D=fL96qj0)DV^5;M^7OVJ1ITLFrq^!+ zQk^I{O($#F7)fbQQW{)`^m5`Yxy^+@C@)v*xa{nE490-e!z%V`bu&5)LQP7FXo&2MO0p6rnk0KT{aM=5`=*sq$-M4lD$`MU8i{- zu(&#P(5*r~qKk?Xz){K*gH^umG7}g;kF5GH2qX;q%y>&INyia>1h$YuWR{!kn|&}Y1?W?+|aSf1`%Uz62o&0T#-o1I_gd-#+9eS+XQWn{XJFN{kwR@*B6pv>dE z-oi{RmcXgr-TV}VWpuA;Pe;kd;Z0sPud<{NQ=qGJhMABDTB1eXtko!Su^sci@pC%r zFzVqEEKorSkl#@P1jQs^c5^_80nEjL|007owNa(zZDfiO_`iu9`&C0v^SCwA)UKK&xWT-9?x9odrhRP^BQ&Dqb6=MDm z+$n~gm7IMPl>SUGw6DL`m}P3+)u|-+)!{z)I_9XP_~}kibNtNn?Y_wQ{Z9ubj!tJ3 z`N))bBpq&8gAQNz)Lt#Qt<_-X)uC_$*)OKSof!AhEi%B>9$f|k{bJGmJVcoFwoPqS zmSS;6W|fV{$oiKe^*oY>gV-4WEe8}W^U;6+&kqWqVE(eUZIhrxJ||-i+*L$Q&l7Aj zB$KN)iH8$zh7+*!M9kYk&nvq1ry}OlL%Gh~?0lhZj{yA^&7UA;91oy&4V0Bmp?_ID zE6KHH+nuxJEoTae2|Siz`_>xO*D>)x{92>YcP#SQmq~x9>;!=hlz)Ev7L$WCdLOis zb_r^lYUAM+pA*>MIV96M#qL~(OqNnA;qRnT90fJHJ!=#foRcP#FymUTc#S$>*@`a% zqExcZ`JRV4$7AIIIJG}Ik4kZ1%)RmAy{70Qq-fr8aUeemz9*A8AxlOB^4ie4mp9`l zsgbT(Q9Efk{w&>Yqf=FZ;0^J?tM0WZHuicq;l1dchB5sw4P8e|A567K$$Gc6Ga-J4 zRcU(B6;HI!GmqQaZZ5a2kB(TPgkEtWdx}=~IUK*O1x#Y?yBB6i;3;b<#(=q2srOP3 zB~{}DtZJnxW!`J7wV^6eWjzdkyHw4Ft!)|Kb2U_n%u=(!_ejArdS`ps{bc9jL9w71 zE&evz_XqB0Z98IK6gY%&S(l-&r}b9_Npd*g`y5@u)loA3LF(V5HOj^K_}bbET`tFE ztLi504{^F$A`%^I#}=w3qu2RRm07fw%T?X|({)LO{B0^mMzs?3Sw@P>OsmtCRk+-l z^Vzf(KFm%Rt>42N=RYq3Umqm9d0AQE4DB53`_A6`ZuFHre<6lV_q3&pP~YPzW!h5 ziSlRM^Y32&3Xp(#kI_Qbf^&?zC->A@V83b46zOGa@X_KG* zp0^C!pPO{2c1#6OO*bTN{( zuL(WHNk?20mTj`;18)I7EyA3BE{YXP+X9V_?Ux1Iu|KmFWq73hU`&Qu{6RHP)d&9@>8-;1$OaFR< zxU>C1JYUzlf?&crd_mG}4q?e>(lspRBCi-ubBbHus3*&eDJ-;9>JFF(5wFImk;cbJ zhM5IafQW`A#wt&Lf*#Ae3GbJ5r$x=rN^lN5tv`9>YKl_`ml8*D7NcG_2?+%M;%4Fy6_x^4qcEHjdr{bi}{U96LMb@V7>`vEbsPwl9 z7JKQzypq+*pxo+|0mCYz6(#?@pt&|hTs-unQe$C@PLFArMXhUyrJY6X3npv>McTj~~THi#_JL-ODR3_ylu~-V_}a^`%n{7}b#c zjEF^6v`g(LAr2yZQ{Ugqq96I6+oE0U>7-j9iQXZdLT^d?fywf;NRiWbx2~^Uwrp<# zz9U-?e$jX&!aw@w{e7vSQ{5;=o0>wB=0+OJtTv4mOcyrL`=Qjg`EuHcd21 zw{)MF@te~~j`bkxY1tV%z~!@!4P8ebcBeE?mY=tk16rfLWbf9I&WO1gGzr3yO- z^J--|%G+fuJu?=6m*+{SxS9J%yKL`_3ONgOmPHeRtcrI5YUwsvm-U-k4`>(nwhc+f)6$=)n};#(0Dy`~UF-(xHI5S#2S z|5^IWmine2gQ?%w`yGFv+k$w>y>VZ(umau4ZMu?R#ota)64&1jS#EULJ6Ch@ve6d; zvM9?S9PamlIxTNa!XakyHeOWU!d28MN{%y;JsBepsT!d;c$adoIriUhOjQgq>#MMs zE>*d^o8*1eRho=?Q(-gb#({OT7C#99hJ)WP=cC{P{0qZE}Rhu zQXJeH{q@RX-AKdS3p2X1Zbqn`6+L8q{^!!HpFzSRw%A8tdgQPlP(OJ4vf$q1I%YtV zM&taY=(5n(o{m0nuY6v*d!Gl~9)Pil4qV}gCD{dfjy9%qKe>TLI?a@cmof$0^*FqSemTxZrLqZ^z0t+^iDv#On^v@^)~!v$E>!ZsHeciBI|(wDPtN?Bk4h8 z7+jG?UKT@lQGv2d{x$4k?czfnV(%v8VuX7-+}>`)?|3^b1d{vuor|`|S4>!X`&Yto zeP*899gI*nGY=Z(n%)PWhTPe&WWV)MwbyYi@M;4iL3oXxMzQGH2%KRq0dZ*?)v>oU z)=0|E(-`70>ihU7h^=FBu*S|{)p7bO)&z_1hUK-F&4b4JxsV^mH2rsFAR~1X!EyFTz0rLMZv(+(+YGt zed7T`Hznrs%QvgS?9|PWezFpYI}S4c^Td+C9-%Zt*EoVoK0^-B7Oh3d+@!05G1dF2 zDPC2Pyuumg<`V*DM%`)-rZ9p!CK**UujhpGDpGw5C70+Bpyi*UaTu7;DZ=PuzbPHj z?ju5+rNKiuo)R`a zeDbg2rP$MCtAZ5vt84mpJX$nC3d|3RYn3=(&m?b1X%irS`@SH(Ho4Hj^uso2V}FVN z*!z8;)@;K!0Xxu{E%_!m{DTd}SHt9n_jf{M)?fLNB@D(CGRH91cA#Y= z7aq?4EaCxn48uKus%r{x4}m^SXVML#WgQ4l6r7+Bnz>7@7fFfYJuY~wxZA1dd+@`s zk7ZQCG$@eU)0oG&Y_jtAHtgbm#Z9dzo^zh_OCH;tx*HUe-93YLVcL_b=kz%p8iLHD;d5Z`iJUF?4jaZnp%} zvk|RPUZ|$uC1n65i*-CNpyxPfr;G+Yr%M2;mVb9tl|E-qxB#N4)66tk#nyZXI(BnQfZ_mJo9%(HAzeZH!?Oopt4u6NR0tx1iX8@}(^0(!NULgr5 zx?-OA1dsMz`9yqK+G_1*?@g$9RJo~dJF)$j<}#X(crv+jlbP_`$ZDE5cNsm`SZKpQ z&a~(t@}p_A&@UX92FNmu{rHSp3t&dZ7tzxL*8Ae+1>1K=Y0T#v;G{=BMmk6 zrbdCy^jry7JDPe~TB|tqCc^HA9`^*-e|Qom+?6@yT3=XRDCDO`Nm6cMB+p6fJF;aP z-V@s&iy`Cvb^ZU-OAOW(d7icjt?bC_Ij_H6;x}!8lYX2*uBlC(9nQGul2{pZhNLQP zy*3;ZP!Nh_s*KVQYA<~7zyq%n=~}r4J+smk!qWf8&!ukB(ddFNHxJy}&rSN9qhIXB6(cwKQ$Dl)blhuNR*Z!r{C!0j)V?xR8ha9!zt;EE8 z2m)qk>GJ8*BTav!sZ(%eWxNcX6=B_=6H^FC=r-pgw^|4EK3B;-%Y*g$hQ?-ni9`0n zyL%}J(`gB#vfekv{kcBzT=7dDY3<7o(8=77;)lF;>R`6}qhl-UE{o{E6d}+7==yJW zmj*R3Gb$YEN9J}I+0QXb61gX0=QPls_z7EY{W=RzSxVy08NixKS)Cf^dEE5Kc=aQ>)N_4 z1Fy2WvH7wCu4+5p8yeZ5Zv*D8^J8+F_7~;=8^PaP$i3)n_#acA^q=Q4fhfDXyjwm0 z30iNWX40c|uJPxoOCT$43r6{PT|{pS{oB1vkd$K?`a! z<4^ipYniKUQJ@d5eQTToaxm*?Pr+5YIghU&zG#dMPi>Vlh!%nY79eb zi`S@mu%JX!eC-wTa=-{lM)1Rp{IG7w^bzIz!uiWUz~0o~g1M`t`n&{nz63um)@q(a zB|==hn;$*DG&f|mHva5Zv40P`C($3-5w1Un!$Bb+4}riTHa6x{%!gY+dLP?Tbx`$U z3f6H3_-KR~I&OuhNenber*D;DHKNs1IQ{1et=};W`cB-hM4#)v(aavz@Nu~FxI^8z za~E2ZyYwm8(YgCtnLt!E(3mrE3|9~ee-L02brg_I+b0ad#zeU&4OJNB#$kUe&rp)u zITyaSpwq)x{+c*iENY)`1J@CcaBNi8vbYIy48S`V0I2#;P-4#|r}#8i|DBS`5tdee z!BS;)oqL_)^7|DUtvR}x5WI`eF|yAp@jh_lD0S#;eZXgZx+!e2FU#F&8?Eq2@j0s2 zJ>oS6v2AHSz*jAz4pFCciW`q;^36-L7R9A|oPd)vFTF0Gt*?z&BO@P7H%CLxI&Br?0v!6M-n#Zff`L|t3;oxO({x=F}m9wLEqT~B4xfr#3O(nR5D<# z_RCUk^WmlO-s>M!)t-^90+Fjqg_RBqG-Gznu}5O}!2CEx23Fs1HQE0mgS9EXRgFmmvG@ z9ST(eyE}PWTbtbS+WHd52mF$%9Uzw|_9ep1zo}-}l8~c;(WwJR#?BGqXBxL%c-3tH z4{7a}ZZ4l5WbN*)!Np9`sp>gG;<_$Th2@DmR;<*3H>fq~vl@%<9qi6k^!mP9myM!s z-zN8yUdCsf`{3P9uA_T=)b*<=tbYge< zwp0VDP(Ji1FqA?tL&t#N%h#A?itV@jUZk95}32>!QX@$@i|uMUT$V z?{0y#p$-U;hv%s-et?Au8g4_*(UhXY=0^s+lb z?Fn0R#7**4<6N1O4{C9RBn^Lz+PhcbDe0;&1N}HSl#sa&OS}y?yH#qWl~P>Dty@wH@ooJ5kFT;dT+KI1b8pY;413mJnf?T6hKD_L zW}l7@Kq9NqhbwpqXFCU_fpT9_bu{ty?#xVv$Sc6gb~_jVOD~DL{`6ZkpdlQbb@LLZ z4g$l6(@;II;|YU5#=$ZTqAW}MBY79mZur(0SAEg~C~ z5(XbCjgHzeFNjT=YUz5F)sx6Q3IB}K^a-DDZ>%my956P$9>48eh#R^NIav_ZsEM&7 zh7Z3;5uOQHaBHxLIE&-pk@+q(ISeYlQuJXYQ=Q^=t!>l;L;BHfysSu1REVOn;rD1{ zsofca+SG-3oguV#ZNfM+IDLM8Hmd_cV;;pT$QdIcqJ*&%lzF z8XFjU?F#2)N?hDTouA!{jc{4aCiRJGdTcy2uj}v6`>Cn5TjZQ`JfzYa%rs5vKVAB? z4!G&z63?TSK^t?*zP6@R(N6F(idNL^(^MWJW}l^d?N( zm~-A`!jU-=xY4*?VF5Y%;BT5eypyNaRF6=Gx2Q9pvn+3o;W7kr{+^ z|6Z}@KU4Af`!>R!U7f*Zfm&GZ;Oc!no=tg~!Lm6P!nd&K3xNU}|F9TgMmg67sWIg8 zFU@IN+JQF$lTVvN1fBBVB`tdvZj_jzVPY86P^HRHVxlm zww$0miXT=LHnopr$&EI_QT|kk4o}g0d-}A+gr#Yw{Fr)-EU-E&bi_&9k}}&uf4G4#RwB=sz_4Hp9_AiZ^VK5_DiO$U^$+cfMI}=_+q+^ zmxB*psttz%(Q4DkIzBEgo;Qf4c;Dg6Lp`{J6R}``Jh3C-aW2JG!f#|L`944R6Akry z_c(OwhY^XiYm0@uFFht~SAsTWcxl7q*714PXzJIG4prg1OjXP^#~2n4^=l%!=?7^& zcd^4$ezZQ%6=D|Ysg$ZMjcI#G-pgf*1QHXRjen0ZO|;$btcW*t!Vk##dW24H0V~n^ zmXm?;z8Y(+vV+(PHWih{+AZRs&$n6hH9A*jlyhe)Y$RVR*k4vm0CmkzxNx5UNk>?q z?|JxIRh@LGQ+PZbDzDFXr|vh`lS%({qyKjum;Y?v|AP^hk$!iKCtMD3Ji@M1j|nZ_x)I`w#B z<5~w19#h;wwwsIqJ|$i9l(jGy7oZP2JOI1s1Ef^VJOkBWV_YjPwsZ~7H*)*iY>J)| zJM;NlrH=PqY2$jeKJuFKcFwV6mT1oquhw$5YiGYNqkAvGLD<(9TJImj?nnG61$>sm z0hxifF$KudgsY@bD|cc)@^2l^aj{u_7h&Y!I_)@r|DmUJe3KH&C%wLsdXOTC`tloc zyY6vW()xx3Y$OtOfbeYn?yNlRDb_R>0t($@8x zS<{5d7L1Xw^%a#vvj2wE%nhO#Dlq+!-PIyZdd3+E3(Zm5=upFT=@Kys^u_m~r>`_> z`1p!Av1$kwR;95pqPlZFYMP;bu2_jw^%7Nk-Mn-zOT^|;KF0<~&Zc+p7XkJtsspda z!YXWWT84aHNTtC}j(8D*2*S`T#?*&p_erK74%PbVrL``jlEFcECV@i&PD(XlU3TQ= z++q3Mlg6#SwAfRA;|T~~0F2fHZEt8RgWs>fj&Dp)Xdx_B>t)Y~0f#&le=@Y%u%gJp zsrG%tIZmr3JS2EbtSigt#0>{N5B@whj_`f{>(4KfJkI5y!@!lgJOsG(^0O5;T8XMG z{o0RdZ$HF%AL%^SdHdBT3NhBQ>B#wMEf6s%=jxd%SJQb(gMI+`-Ex~BB1D*=d&^K7 zpp2fMLpxU?l4?6ucR_!lHXlnM{kBV%97c}RWi|PnQzBoM0WQxVB$JV;5^#U3fbvWF zc>`>l$^{6}fgrtW$~>pAYqC1IsO2SDk?h;LhgW7_M~<$bY)}03sbGEcl#CMlF3=H? zEyQ)?Pf%#qUsg&wzGdZFR$9%aoZQt~WyTPSRqih|xl}yI;=E|w5=uEQ2`T!^(MJEW zHbQCkdjR*>ofDe)O3uN=6{(_c$cW4%LFg!_#@<*UfWe`Rq@5rzCZ69C2G;c8?7@G% zimFPeTdo^#G?C@2k*5_8I~Lr9o#RviGGqx{NWA9*fciel1mNWL8Mxw&qP0K>p7AUX zpc?f2x&S2rJ>{+nXpM1;-fW5@SOSX&(4ZAHthoR#@Un3#>u?!CC}@uAGA~_gWgBTgi=c~O+kGq^>LxS^x_S{ zhiTPF{d?ZG7XskWH>jzDVJFrvP;5MirlewC&|qthJVyUfCNlNbF3&2BJzdcO526Qw z>k>a}N~zKpL=JL`<=1!d6IEQSS(PWQAsVxLHq`4tjGu?9G`mS12;hH&yNq=`MPzHT zC-TO)AVsItp;xqVm^4{jAUkuQUWV81$8+kHGq|5}Ts>^!Y={rjR1MjSoqz9$c_7Yp z(i2h){iAc1S*2MQyw9XGSDFNVQ?$_ zpvJ|#D2#$AJ^oN?2&-wd$uj;zVifZF{TwLFZbQb_6#7^{5!vglxZ!Y>TleAhSptwQ zWY*lE4i7pVuZeC~0?!PWYq?v4`)Fspa=oUqvg5XTgkWF*!#f(07Zaj;eQ=;@m{#w0 z*<<8Tx~OF^GY}=gD3$OqFb1hxt`=|ON)up3PI*r?c)c-s5x?-gq_*N^!`0Szt2%eu z;$o{Moeq&+S_cN1AyqR$ZO&~U;YQK`xEdQr*V}DzLDdbsZ;Sr0MySNhNr=z)L99WJ ze3pp(1`;fcA!v?ffO%7$MJnNEflNW^p<+kzv$JeYTk^3fa0IrR0fdn~h(ukg*rl96 zRqVW1$h}18AFRaxF2?xJ_mz2GSfK&ogq5?1b`E=~NG9Y8Y&?JYIl4(^?B#X1DggSb zJ*$)Tqep(cuMeOLGo+$_f&#UnSCp~)zs9W$kw4e#=vy=J_%4GBFDv^yj3E#kh^)vc zu{JX|Cgn@7HHR1^s>l_MYGKWuX&vFw$?6%L%(}Pz&TkW)s!#mz*2Qia$3tH1BK4H0 zPx>LczXFg&FVWLSVkAk#_%`0vu^@}c-Vmm<2gH*>!l8*GO+JN6`1x9=vsqL-Rz6tm z(yAnWQ9eSy`UOpCleE{bG;L7Zm4s`?qzLVqXBhYQ0;44G%uzJNt>Zm1!!C46a|u2U z9KagU!&cN8koW4IFXe!=rus_5-D1PK#kLBB87;}Dd}>o~j$Axf-}qm6wo4%aC|=u`@92 zo+2J~3_o81OXk$U6vfoF_h(aWHWsRjcT{@m^m})QN1t+=V4>lH4$XM!ceruWdc(a= zc}R!}JYX~$LG|P+g8P6K6kb2ITBo#?k}^H+%MestBqkh2-lTYAycvzUQ2nT6POSK( zIdnr#*XVPabI~~0VA4t?LWJuM@l^sSm`Id8uUGoWxK^T29h91Na>bBiH;gRAPjkHK zCv3lkkcg)`>vOn^$!>T!-~EHTplXtPsiZe?5aw{6<3)7z~*Odg|Y$&0$wj3mi;)QI* zAtS|k989ldhYPNxr%CclMvacpW`ZW;7t$p4k=e}Jddi+B{a@qXmKS=b3T>qSyR*%| z7-Ji6|HWL`y24fT>i%T{q8(_aWXGTVlS=WwGHUsA|6gS?CmJ(Et*H+1Hm&{wJSw=3 z`lZ$jY`2j!co^sKE;EE(5s+zFALi*st6IsKTmyV44L zAviUma;2Q@H8goY#jOi)gOJrmZmQ{CjU~8M3Guj(!4Q!Q2rJCN?tB0%+>o->d@I<| z9S|T*&jA3Uj|J>mGHP9#k5$(FX!&SOUv-)~O%trRQC$F&2#gg$h^um7oypR15bs`< zY8P@pkPIUKr}##Bs&V(R*hzl{Ra z6nawyT>?gDEETWE*-IB20OBySK8b$NmAR~iPea@X?~jeC=a<4jqy@u65VFYEPngZr zGPEq+zMX+iw<4sH+{l1nuMe~yd;jQK4FEptf>~ zT%B%N7uN595ihBk_^>t;JP+4ewi7xp)??J3YKDI+wYS$N{%(;r1$d+dS=}qgI!M;E z+GVeC2Jvk+_7~8^OIV*XyFQ@JHo^)ZjuT}k4``r#hn44(XLX&^$xHenD61(6?@U!! z0wtV^|4P*x6r?nwnW=^zz#e5#b9aPCNJf(Q$r-h9zz>vCkeflZ2*yZB! z++c3Bj}uX$ndjNN54;a(?B4Z#RN+BIKJ?j~_r8;GBfFDxxRl|>xD|6Ij!5;HuRIMKVOIuKU|QmGthM{0ZZDNB1cF`%jtaqRHHEVSG2xJMsN{psQ5AH{E_2^0b>L4 zmk@g7^bc*`C<33Z{l~MC4y>>vX_xrt6+O}Y!6mJf^sqIAZVBv^e@~|}18A=0DFZ(T zqr)ApH>iP2@^d8{wiE_qRL8vfQ~V~6xF?DlD(?9r^+gIQFgZ{`4z%YSh)nfje@QZ1 zgY|)Dh3YyFAe!6})fD`Lwe{yv@;`o6oAkG%JX6PijSHecsAQQF zR>W)qV4O}vtVRyo$*z*B^|$|6=0a84*Av{wLx=Cb-3Gue z&IbnhLy`h(%9Yi)_AL7=n10=|_x6WhuOFq5_Ept1J}$GTZi-Zdat?%SxA&fq-zH=F z%0Ay*L%C76$yR!9MT)K3XpKP$g%frC zf#UcCC3{H0IpdYBMI{8&wtqpIqn{v}Fx=zG6R#mL^h>8M3W>}Tt_u0m*^lee^s$WZ z4c*gY1Gl}3V%o@3J0C3cRj5K4dMhG4SzY(MmbH?IH(zI>nj%{a@zYv-^&0X%6BrvN z{CVM-I!=NX4-8e8B50s7GufNC_DEades`Dk4xDQWINw5pt)>)aBYgB%OH7Y$%c zuHEp+XDk2?AIBA9BdB0-x^IB^I{g#$N>aj%Rw=Ka{M?2~u~O>$_lOTq{Efv?+z8D+ zGsGL;^N&%o4w}A`hfV|fZ=A|D4~AW`=OOSSl4tjriclGf#msw8QPSJ%&6+Bu-pxkWiv9XdQhDY*;R2V<7SM6-_oT%#iG{=tYdLmrtEWcsKEgK~3%wTJsOY zDIvHbK?Mt*WgWS1IJocV-+#uJTz`vA<(*n$SUE;lR~JSr`^XS4v-f#}u&l6+)ZeQM z^$4j_L5}B*wBy{26sp&|J|gFH$8;fF9FV?BdfSF>aiQf1;XUx*WTPSfkd0rl@!8brVN$tzeWHVz zEjdrj#ai#BicQWd>`jhEv{x>iSYlSDy-PZXNU*1~vW+H{#aiW=*K^EkKqaPZJxU2c zOLduJeaGZVVZWtZ5x*_XUF~?^i^VKX&87*Tw}Du&8-z^EchlWSDuBH3USmRZZB}%z zS@fFSdh)lGUp~En3ZF3$0DU_IS|c+&!+?H+?$qSJZW%$Ffg;Wr@rPTR@V4~`{O=f9T=#k0n9pUb^5f}VHPKd?6;8cF6k=ynNAg?pc8UEji%L$47qWbY-_nufY~ z*XS5NS$vW#%Me4;bv6`7@j~X+a4uT=pq0+|_n=vg=-6!%FAR}Lj7HLGn7iT@i?SAH zm#!Xgw^u%o>S}*MjxVE|vQ@sCKW}xta28&Z({6Rd#CpFrmAyK z#8()YvLwweLlpE(Db$cl>xOkFV{PQBZv}U9EQf2|K)tqPg(oRk8c~8TG;+ z!k)`uR|H{$cB%f9bG(^cOWjWs@g~S9gErI_$4kMh*P~+ zS9mrgXk|D{lif*zT_sp$k~h$q-ob_R(nnsUw*Ea!8kuDuqfokOj5=*>bc+^B4>EJx zkWaztg?ic?WY42Y-qZq)9nJ1sC_`Ish_swyCz5!mY0m|RG;~&7eU}nZs+OVQI}?K| ztum0fDu`(7ONEHH)HT}(g_7|Wh{0ut`Fr%OgoElB=JzV$wJAY-7y9D$_!t__%GhcB zCzLIo$gyfV4wQ6X@j0sQf~K7`<}jB;966k>l7`1hZy5_1;aZE*&Kmk?K{g-Uu^h4X zU7|!(uADT#uW2>Qz9A)Is3j`A&u-#(a`rs-a#9dKoF_j$hp{^HNd$9)O1$~DDDD|~ znyuukCK9b>jxfWU5DDrr7?8OFWwufP_4Z||hLKes=#<~70q(DeP@M^Y&dN|Sm1Smp z#Jn)UMiTrmn4D!*5F1d8e}Rk!3cwHwU=$eY98nUuX1&xPBaI!z7YRc15qU9Lal=;NuvThhz6Im6rG<`?a#eHZq6Hf744a+9NyOn@q+#AL>HBD&ugI}@pboaV+ zvjdL6et->}D4d59BD-~4s5^iodaoKg6c$LJTnrbmyDLayq3U+Hn=X4Yn zqI`lplh|g4I0VMtSaN^;60SJVPwVT6L;lp`8#Ts|<1EnlcRND+JZECf=&Vp!FZFA{ zi~_;K7kcc^!bLySKqgWY=t>&ugUB?GP0gRu(KevuUqv{gu^-C5S%GXpW|$9AYA<}{ zD^hC(8rgO##6bDT)6{BvcTmWEz#+=K<1+HKyevzS_B$1RS*6*W0aNVT{yN4s@@Tce zq8YeVo^pL$MlFSodAjwA*YSr0R>#E09VjUUG~+ZW78I7i7i`GkzAI_*|C;0$F+=S_y)I0; z4C*>qt`&FM9Hb6oY(0wWtGXxQ=X9JVWzD!i^d=pr!>|stAVy;vBOb@{?g1`nEzC8) z^z_a^t)V&wS}|AB{Jtlau?ZM}*9%YLb@5CF@jQ%}!>g0D8ZsfCRp%{9cbUtQF(nP@G0@OIdV^8{xXVc zVMj*|4?M9>bt5)4Nq`h)|Mr#f@HseP6Y6mz_uAK2`m~HGp-V)l?x?%K%Ea#c^Ozw{ zAyIvZ2)Z;wj`YS-$ay8Fg4QHwjaYAQ>#iko+SoyjP1Ayif^j<;V-2ljBogx=NJh&h4dV?3y3#KH;AN_U|A$l;PJ**i7NNzXj zH@iT;B=Yx_bPG3%{cMkiL0D@Cc7et-8c%X!o&{*75^8;bf8+0Y z32n6QGS#=PP0}xV(qyGBOCXm+?S({_f^-}h;L>_1MtZ7d5^WYttK6n_5BY`KW#G4K z(jfUgO9z^2FLt4iV^8;m3fGD38AUsZ}@hG_~u(pm|~T1EQ=5Mp{%jj!wf6rTL$UInG{?kqCZ z2c0BlsWGdSAbuCxA6G}=d7Fy-I|qDwzwEv}yu;iz!6Sp@nJiTO+J0n&H!rrR)8>s! z|ATVJ|JWPq4}~_u0ndLrL~ANNzRvy$a#cqDy^Qi_8{uDN(*CtR`VR=lpHPnf)hoOG z?~KdB!He6sco)(q+&aH2r|NG31kJhOh4Gj|($i~zsdTa`#_79x_r z=~#bRG5TCQ$P}2rClLic69)kHo=RsW#;B&2mjby!$<$y6sM?OG+UDRN&aC!Qf8&r9 zG&AJz5;Bjh=(^j19i9LLG3~V$WCCq>Tq_Sop9t1N1;BYK{niF#Qz1yaU!4lR*1$f9 zufmHF{+{32`xGzPiW)n`Z9gqy-^_-8Y9^zez5HXt6AzQHwOX6>mQgoh4xYvz`<*XU z?8rGFO6bX(A1_ruc-y_j7cmxZKV2WQa%bT184P`Bl0PfqVMjZR{f&aS|7i-9vZDC8 z&}4df+aB*7a0W+(bA;tp0A#I`_rdqDdkJ*di3eJlj4{rNxcntgWV`OAG{p_2+P4;A z$_PC$_l4@X{i>G&kGa!rxHci`l<&A%Lzb`9(ACVXB|mGTQS)+*BJf z=_9+lqb5xovd_ykX_lq?(eaF_VIWu3nU^(rcY#IPqikdnE3hz(QL*4Il2Q^l?`g$B%x}R$_YKS#Im_Czyy~f&taL}NN$FUO9 z_WsJ9E-T-{J|;L*5|l#YP*ZJ(&!6m(7+$Egwcbr|k|YoD0=@>I&fCJe?&b?%=x%Qy z&}9ke5g~c+8^`=eKt&{)ygc#qiWaXz;8+=uSN^wiOG16b-gg1F!NozuD}`tCYwk#V z!}f9McEy9wvTGmnMECFuecoiru$$*+!1WX|bO#iMXTDVAO*fZtEFSi~7uq4=6hi1) zg&hx9uko!#kR(eEdu(Yo|1sOYo*buxspSK@a6YnPNPqpLMJ;J;&F5&Q z5rHe`@G(=<^#}LXc7c{;!x2*5v|;4_iYJhwC5N;Dy$IhG7R8I)7> z78b8!1-U6k7`~P?hdq@^19f0P-dpkje)M_ueix@aBL~c+8C({ztJu3AqNh(T{l!Qp z)M(tIk&Dp4zqC(Yoc^s|1b%+|bk1{K*BY3a_?m!HeoY-<@C0pV1d5=;-9W`GFcgLm z6#voUkA6o3Uf&AWKLp$ezzf6~c(h}__q*$yb*+;=<>*K`VdHi#ryX>r1DwDU*@{rb zX$NK_FFl%y+O{OA=&!eTz0c|@v>l<}#`B@madn6f!XOAfbMqJp?nG1&&I~zH;Lcd0 z6NheL&wX^V$;5;V&{o+BnDUG7C!}ZxBf76aXIB=zKx~lukwO(9T4EO_NXS4=FFHG^SU_S1MrfYyHuo z$#u&4806uFcqe620LY;0lDGB3mqgO)Y_BO2;g~lVuK&K?j zBL}^_%ym<6Az+8NTYmMZi)Ds(s0Sx9QJCS52su6ZRf`Cg0Eaw5!ZSR^w-Ig9BK6Nf zj(q!bS(DW*1}Y(o6OzVE=VfzQHxi6}(mxK4hx;#0Z!~2kDeTd(b$pBR7MB!^<2mS7 zwAr~zb01?7L=YV6qlxUxJDB*U(Kk#`Fn=9nV#I)RJ|>f;UbE*PetmQZ;ZjE9>|oNT z_rg{j)zkhsCHYc=ggAwrf`csV8vI%WH=dcH?+JrXDalhS5toe>T_VPA=a)b{1^9JnlS4ZL$^_~l%^@4D#IW}~`gchW+ElEk2)zyR5?ll$CD)EhPyUguU zCVIu{jHdSUPIoK4q$e21MbbB9T)8O747VR9kP;3sI~9+} z#B{DPY`6JScB=cWn^(RM?JjUJT_p*@*>yIFja;ROtl!%E|HymmsHpn=e{>M(MnD>* zySs*v7U__XZfTHa00jl$iS? zu$awk_TCfw{dvbLblCX`>mW2*Tt)~ha>`{igTLr7uAB5s*q0(o>sHK@#aL|`dSmJoLKbcMjnw`Q}^fWe4oT@kA- zx^1m97Qgii3-3htLYl;Gm%y)5JmeNhAcXG|lQT`KKnm+m`vZgwz(bD3sce6;s% z$Fn1BJ8%eKVqyZGtZFJ|u;NatQxqT@KePuHFWSk}9XR9BcytF^X$kvys|Sg_s5j}l z#5-?U)=YJvs211w=a9Wrh0O(LL7^}sEs8aDnA4+oPrB`_Ux19+FXj2mG#97(G4tqw z24z{SJ6|O^spp`rqlZ~{>3A$~rO5I0CViffCNg=Z*)T#SpD{Z&aap@ezw%+Z~x>(0i9XTa1RrFPp#!T zk3oKna#4VYqj$JBkzFi4W;OQ;_w{=0TSfbdN+l4s+Zmy+_Gmf%*q#Rl)q~Yg<_FvZ zYX~?|t_Yj*j{^8BWLa%ZcHE+GgTWPXDgOAk&}HKHuNP(AXe7pkP0SJPqw0F7@{|^c z$Iz=cTd8J@pIz%k)AkHF-+$i!efszeTJ7Pk*;0#`_z5VRGx7+($B~dfRiW)T=9VIV zb-+Zs=CUiiYE{k7#`#RHn2uq7t-hXDn&P#ggL){n%g|}Ry}Ga0m*ohM8)cw zwWs+1M>xm0>!y{{cT{-w?{+(LnTtS8b5<0(sx?(!lkDI^dTi&J!IQes=E0C8Drz07 z;Pgo6eAhDBO_}nL95>6{95&~oeF|u%Yz@C7F!Bl?_Ny;5Z#r?(a&XEt>q%NV`Ye&I zGY1uos)0AYgU<*|W^T=_<%Kr;(={ZBq{$`YH%+AW#d|B|*3i`qCKDm!;$=uKS&V^a zJk`GIYFAHgG>rlLBati;G)2Dd?+@0B}e_%fc^yzL0z@ zOKZSZG4$al+n7sv_H?GpdNM`!_!DfG@GaZ?ypHjAt)*pr<%E$r5!)HmfCOal56~7L zVQp%AkkctlRmWr0qAq-U%PMjui5nV^k1K=gmH^IU(0b13pd`6p?3l}1x!Nt~?6S3| z2+I?^xn_jH0RJ{kIqQXiPyrrcCI$M(D^PNEx;F%>wB#(o&`nlG4TWiqXtRy;gvFEH z%nRUc0&F~NfjUhBXdOda2ip9cSRBRPg!2GSwIveM z+@?jR!BM5rsshx+H~`tM=S`N^?b=1u)WJwfqsWBW-&h!n zTM&})?JcL##zeWckqlfs9^TjvxQY`6vft(iI_%{)QCH=#7l07csbxQa%lmB`WcSp7 zelPvJk_e5@fsAk)fmrBfJ0X?6C>O(`KmQW5uhlY&zlRoux{yM=SX%peH%Y+fTxhNJfa1f<3kS> z&OZ3X`Lnk-O+c4V@}5dATGFM;+0gxPyu*8|AoI0L-)O^Yv(y0*%O3rgy%XvrsW?m}!8%_5}@7kcY>Dul5;c~)qN54I#pxwmU70smb?*1^VJ z90wZzh5E0Ntx+s{W>2QhgPhD9gH_4rSJQAS+M;!v0wS zCMM?raDO-uD*nXt{7b*?|C$;0JJbfGK=3&>3^SWR;WM+JtK-@gsYcb7nk&45s(G@YS%k$(1Q%)AB}!!xYnu>D0cw}wfcmdqZBTw z2L6JoRT?!DIzxqb@yM0xQAjpLmja{om}w#U=Xjo0aJq+NFp~ zjXNsbM7+&HJ=nhy{noR$&q*}Ur5GJgu%Pht#r{5GP|#dZr+!OgZR3!WWle@~j=-^L zj>+en{E@mJAd(v)i3d?%S;=M#n(E(ty%4;(2jaeA8IXgp#6SA(k^kLXxiLeux2FuL zao>rrEAlv_Apfo}`4Ec!#RGP&mK*dcAJW6o?HD_cB6P~V-VM?Sdns*lC( zp0K}63Nn;{qR+-y6eC2v>tbdv)nU4+yNJ=_Z7iExi2;e7W!({-t~%E{=!qlWGsqJ0 zaYD==b2%-2Ho;L15YX&fz-zIkG2Fj&gAv%Lk-b)W_maa&Ppp1R?foWa^g0U12ZWVfa5BHSbS8~6%(S! zKdXWgK36%_cxtuB&nx#4x4Mfi5;NY8hYcG-qamxt(eRf0m;CNWkRsI!S&+yt1o}IF zKF0i;-n0(KtG`(*{+a~-H;)mCe(epH&*3ZpO*y-eNnks- zD@fIsp1K`|jwS?hRq=*FBRp6gq=i~$^VSt;8iNP)!s;5ISjDip;I71kr|&wd^3{vr zWGc^^n-9K%`{ct;nWH8~%>821Ayur!Ifwb(0LR=lUIi~$l3rRV9n?P3fHC;}I}kL> zgKi=XZdmdTZv37=ZkxMAmG_c)IXi##ZZ9ggu}JSr=6%=~L`Kl9x^1o z0lx&YhSw$iZ?rWIRH|Cy1nVMGVsN=>nW$qFOi<^9$jQTvD}hW(3M2ED3_}zB>qa0w z(Gh#^91?8jeU5-C3mUaK{4PW!sR$P5bcJdNsAqEnnHYipZ(9gmHp>MC&$!v*5xwIUI$tc1`}G*qOV3Z57h zRadVywS{SOe=UteRv?y0K(GogXNSFO{#c*7kGjNoM>hs(@PlHfu;bpl2kv!Yaptez z3eh~~J-#}`Q39pL6Y8jFs=n-_Z>^4K3u3ZO@b=zn%-}sxhUJ?ugj3ZTcz&@od$A`;$boXBEkJd)22A_1+jQ3>=?q0!apXvf?o%D}0a)dq_7gS$tn-!G`)>qH z6oH+ZK%|KcUV%5818eX?S*=o@J#cp;L18|?U7pfFvu@QayJ{XJpw4rSyg$jCZEip5nd)Q)?G^y!SrCIMAzWlxl= z0am7I8qE`mzCPDJf5iixpJ2rQ<}Ux2eMbwC{hQ1{VX3P>||^=#Ym{MqEg+Mt}OiSHMHkE?5;Is0h#TMEJ(va zS&h>ZQ=t1~hL$%nAOBvTsrSAx_>pJ7EOx0USJaH?Yr4iHqre_(x;ymfdP$LKZU7Qk z5*$?O`6;MxSEl$eC^k+`!)5d?dGwcJh}jlg=An7)g%E^$BQ_UP=&rD6sCcy7jwD{2 z8-z0JJUP;VftshdlZ?R|F-C8t)eXiHL0ZxPeO1nZ8j0sXVk8jLB}1v$CdMgdU2eEi zazUg|nI^_FZ&=+_DXit~l&i_Sv=j#jU4oq5J{NMbu`P`_eyEYmd!|pwvVn9b9dS@- zS5+)iQ~CtiR^|tYau`wvPJB?X;_0;lpleVYQyQ?vMTZ_$@Ps|*srYP3+;%~LAY*Xr z{jhQC{h-&dcoTF0-bpDf`UjUtW~A_`ovkHH*ZGAjJ}+Q6E-8_V-VA*2YMODOSCl#3 zgG3rsTk_{O;FC2Vzgfa;{iZ*rhOB#j%9xjwD>NvefwN_Z@;ZQZ-sUMw9Q2y2*NRr| zj@|+ZkGwcAW!Ea19OA3@07mg2gOw*h-UE$qO-#(inGneojtHL8G<|G{`g%M@Y$@t! z#++F{bV|Era41FCfyUQOXH6F9cx&vSHXk`N{(1oH0Zi02In$oynIF$^cVjE<-8g$? zAy=YuB=HSEHQLwSRu zH`J~6-(9T!@sa*Dul>LK-Pr(yq<>mB6xX^!(Xi;k!@YWOk?j(HT~h58?`neRBMq@7 zO;c^BG<4;xXG_5w+knCexGTD51|a(a`X`V`<7=e+n`>EsUWqQzW(!op!;r;0<>|fC z2@>DPvMJN`YrTRlXYS@!k;$JY1s3JM-h(6HJ&1C-{^g`7--pjcy$@0-^Q4V8KyqGUEALQH(AlqUXp2BNRi z**_ca!z`&ze{p zo;b|oxkbd~BJ^9-Wcphd%x+`dGk&BOrZcTWoy9Qz*>j_?Xa1%*;E7nle770Fy$}+{ zO%(k;_(I^(IlJ;vW&8~jqJ$9VebwOmqt(Rw?0HsE2Hxx^Cq%1GuBdHL+Gh6gsA_MD zrZTg8GaVE%SqzGTj$JaK(wAzFQ7@x}irbA}1_yK&x&Q_M8jui9AjZHAt2uA(0LQ%} zY%yk%sg|_(IB`LS_;qqLN(4TF%jnRG1kl&?t)NlHy!XZ?rxtm5hJEyz6&=11CicWq zppWN@=Cuz#c%@eZ$P<~tUz!%6EA(IOMxQKh;qb8Sk&=0^G9a4xMUJh^siEYl0!#Aa zOz2HLkkV{A>%7sSXg=O1-A{3k8ANZ69PAOZB=ZbC%ikPR`KNu9srKDPth(7t8a&L zm)Dx?^`QFY5Q@C4C6Kc!17GT^j05_tPzV2szKB z$D1%e>>%Q0-1+mbuXETo{B95yN+DkqZ%=9e*C``*7AQ_0=If5!d=@yke&h}P;5HIS zS>tAh5|DMLJ-xI*n6h)wZEti(-!5AcF;G;;>4q*92Zmg=c!TltoGQPblMtB5qj9_d zQp#pv2oHRSKy&S7vh?lb6sUHB6ybabg|fiJ*Bo%+CE zTXN$n@G)2uVwVxgV{lYE)KF}-a_Sr3ipn}5NbUz#t=_8+-yp-uv)o+ZKZG~+P(;@B{f22oMY> z7Qf>z-pJ~|4`hM5xSUr9dzqKi zM~{5kJ@f7Lr&X}BYH1!z;5wN%)4mkMOMIN}%%v)BgP8aJWBw5;GIS!X^P=4Wo1bE2=6_psK&d`bPlzy@(K zYiXnZRM0_L}O_NsXjx@=*;;HGyz2_V3qNH8%t3K>?GLUl;(RORM61-PXK?sq_r6gM^pql>BF#UOBitP9g?cT z83Os3N`8R$ia8H}*cv!;>$>gm1mXkvL)a?|3;kbC{1iCa&x-)*jO{O1jqg%wct=@k z1JH3%F3`Rgj77>?BCE5!tJiPML2BUJ50DBDr&A%gMpB{bX4#W+>8(g0?=14xO^i-U9 zVMd0&BUsj$LxC;=R~5`{h^Xx+ex&?x(lTm#WO?N1J08z{O#c)}0Rh5zn}@H96G4x? zBhf=_gt})-5kEk#xxb^JavlNsxppSZ8PH?WE&>(*hsaUp!-?N?qJpUt%U8^qNctu! zvaXEoGC(GTkxD?8Qfl4)Z}ZLH4yA1BdA`H6FZPK{K!(AsI*2;rVwKXaAEf>J<>b}Y zrR>v(+QgFJ84|>Nq)wvv4BvZFX5WE7Kf9Qllw3KR>}#V(Lwko({_f3JZ;IAZkb9Lb z*moI?Z#KoDWx&zAN~JkZ+1dND{LGGYg(Z}E*5Rc%NWwW

    IyGjpk%obN zyK;J-pP%yX7_POnmPx$HSEl`F%R$3qc&QwQH^(vXc5q=p7=)uw)H?YtXwx%6mkicg zxU4nJjZyN()TKr|7|ezBc3^j<1lS3^YV7$0R7zHD*okh;U758<5?=+q(for;zj2Y>Ku5mw-+ih7HX;4r#XXMx*P_C~ zLWljA?NWwPPZy+_Tn$2vz$Ju9h9Yj)=MS|~gBt}-s^80D9{kO#`!$5azb?%wa~4{8lFFP}jkJicEGJ{f~c zN1Hx?*&)LS0X6UF%kA60CsW=2J^5n{{L?+h@UHuAK>J1JQUg}xbh!x}X{sBd7gix_ z@g}9U1=#)i;o>3;iPMs%xk*Kdl~0xP0-)kM*Ck&s=27;%s+Nl+lvHKBh?IBpIX}vY zZFMU$IT~9|re)T8H2S{KPUPK(==|!vorcd5MSgV|a%_Esl3GY%bU}fl%nE zA)H_haAwmYLg{g~bN3aHk)&ZDhACU6E5txvmku5`5$SmYstmS8zeL zYVYnqgGc)_OA<5ZOn01>>y|URr%WRZUu$u!s62d~-z5&2JnnyROP07+{~k=d}|Qriay+N}Mz zo|?>WNx0x2CJGN z?|=RXDz974t{Xj|I}&fn3Uizoo)u#wl_pQ3-XK%h6}`AQL3vdzdg+v=eN9u{-)JC9 z-_$4D2r9IZjD8G6Uuvc>6$YTYpBq2_M9ocv){cDsBhpT{{#!JT?$E ziBfN;rDes=Dh5eih4*V6p;q8w_%kV!OQ}bceKj;+?`jK*NOzk}HNsG;s~p{b(5!cJ zIoC8Q&+W#_wN@`Xy9wH4ZmGfj^gUlGbU|@KF)tD^X87|p-3;0T!@!q^zUQUxCYxm< zTz9SNqjw!_yj-fd&k<2Wz8OSwxAQE8e0BJek+OR6K``XNKuhqBvO9wdQIr+UoaUs6itB{%$s|(LKZ|4UHX||5}h=FL^ z_6ZO)V?|RZ2V6j&n!)HoXTNjp0flFJ!DVH8y}0+5zMG9F@At=8?B-R$UVYwrZ!aON z!3ry4E8-#<&6|kY9?Fbk_-)o$u1DTq1M$&)Hu86LSrb|g-!#Qz2q(zXrw>_K(Z3Lw z&k4GaR1Vz$1@^W(t=nn(8G7qfa#m3^@c z)7u+x>E6n)>nA|av#p`&p2lExvGZwL;~1#Fu7f_ciB|m-JiPayI+WEL0gGIL@Ua}u zoswZmLblUQ2kM%LbbGMI1lBEyXGcx7lbi(4D5z<~!`rjFRpvZa$KPN`nOY@%v1LF@7i;t+PY3W7h^Ixy zQ$UCsa?%7^H$XDI%mnYs1Pbp=*claoJeRy*b^w^@y{t{}RkPNw*$#)#DH2N}yFSL%aeQ@neBIulvN|aO z>v4L}YhY0G0L;A8SU!0tP#jwr2k_1Na50s85{N9CD%eo>BnQg%ZhKgaJtYiX_R^Kia{azZ44p7**dD)K#0-SN3qeeh{YI zXp)YwD_jtoZ)F(=7DJB06J5o zC}W7sEyqsJ(dKiL?J5%WzC;D$;AG;IAKz1}J*ThDBzbYyg6f&or|MDx-&4KN%nwFg zG?vJFuWhC-H1O(fqA6^XMF@_+n_=-gzL=YRJtEqs~oXQm!%I48v**&o1|3#bK~fl|Ks%$ML5*1=J-D4qq4oPBJpv>15cdAqxs`; zUUJ4wWf7^H38{aJoXVS)>*4XsAt85n>IxL8Y7IM6bU!R#hvN4=MxNuQ4iF<%{`Yjf zdf!ZRV-;`0K6Tr}j$pB=SLPUdo@TkbTPJsfx_sSB-xn@ zRZhHA=A9*yN~9n8A5Yx9{PV@eu*MeYLlc7do|^OI-~5m zy@p8GgF+jtoVTfO_2z!^hpDz_sBPR?NGNFIrXZq?HqF%j(QWtMmD;ViAT^0Go|6?R)*S?3TxgF0|K^J5e^4S9g zlT;dKOe^Ep=v;GtLJw$AvxthYfMOFtccAs)g)F4hF9XZVqG6@fNnY^Pa$>8eH~2iv zjwKG9IeG`|CUvsH7<{ImC7Q-g)$Xbr7<}G6k|KY$glr*+1~NfBrC?z??L|$T5M{N{ zl_5h4leDCZ%a2N7jP?O6fn_N2s#M72o$&c=*Rr)hMG$u%Y!u3|^H9bVdYjn12;3+w z{Q8|2vqJem6s8+pj@Jmk5qrZTH_TH=W}!Jij5l@69rYpinlP(2YH|1DC3j2@Rgyp< z3U$zs$?fG(nN`i`?ta|k@$T?8M>=`8cwpVCpC|b0bR*cNG%Kp-gHfEaEh%kfMvkZt z>Dc=~5(4!$bQ%1YkpwISx0%Z6zs^+tH=LDp{5~rw;LlD2lI1e<%hZft00|StI~^q@ zy={0F0oA2cuQxi1zjOsKe<|?~1T;SvzaM;8KL>hC;Cqmj)^A3}`ma)Y&RE_JqvoT> z?}AT{ZgoisTFrid^21t>77z2z-g-xxY!0B3aZO}NDO-bmk)Gu{K~&;z&`B212W;4s)vOh>PiujZQ353-+@s^BjZU)JtrqVqpAC) zHl1G~oUjmBTA@{tGr%SrU2#`Jm!ii{G0)ImgmbFYQKFx@E?AwbOO393HKG`6N;4uD zkZ#qh{BErIag5T4ug$0S`G}0S3&h<#q46VZ2@Ov(5HurzjpXitS~r%bNNG}tX>m6( z#v*x8S{z9kmWgw*5BX_zQ@`6<&TpQ_8&fybB;}c>C&iKY0qSjw6O*hnv)6}NTrKBD zj;@E#qjq#0)m*Cl&Ht&_8d5b8CeFlQP&#$~#XC5xSD>GW*k@X2f^B6*c9eo_3kB=Ig2BF(;v(pSCQhWbW< zg4Y&FCYp(q_!zKF5s ztbmXsdc%mqt`2c~;|Kv*@YVHM5VFUuNfCoq9T@Ws z0ZAIdG^c`jGH7+=^#~C`3WLKGC z?wX&~^mjyP`dz6@!0%`zg z+L*3mQF9;SRG+c1J#Ahms}p5!b`vPMDzuXEHtUYcQ-wJ8EA7psCx9Z$Jet*|vbBU2 zcc4#d>)l8;mII70&=OZdwpOFu=-NRjhVY>2mO+i0 zf7}2QYTz^C4m@ugi8t}l1A(^6oNGG9vrCSbG4_U3 z4mFZc{(XcdzQf0k>?dSqgH@DJhFS-6c{`&;?H<-B* zi8EO%nE^SO>h36$-Sh81nvIoNPHudR(+MTayl{0eUNFULs<^BW-k=b{=d`^yXQ;2_ zn5#&yxE4{#FdSlrjI5epm~Dqt&lrUttcZshSuKbwNLfdj|Kd{Xh4>DYQLt!QDJe;g zu3Yo8Vw@|_)XavRM{7;J#auqHEiA$;SkgJZvl=aCTAQ+p-5WA2hYyzzdoxP4#y?tnJ&ws$#T z+i<*f@8>t`YW1H@d`$4?A_Royu1$d@*|wD*SZ@k`d0gb5etmz>be=pql2c<=ex#+p z;C0Dd#eIA`9)sL)8c{b9{LW9o2;F|<=lqkl$6_-MC6(Td3xMf}uKjAz#Vhk|reBWs z>yZnORgH+7bNR-J?C)PcH-x>}eRXXtbS?0>4>G7S1$em}OxEyr+Q2>nt%$0{RG@U$ z@-Nr`TPB0GZ?Ey(Z5M2hy=j%jU=b*J1m#R=R|pyNE1km29QagXF~Lb~D=}@7W*Nuk zA3Her9GHTX9@K&(ZJMI_V&KaU(XYeITIXpiE{bM2Z@hYd;>{C$CA{-KK|d;=-kXuN zRN)&oZWzgv_L_A-p=i!kvIn|uQZcEg9y_$1tu2FhFY?5i}Dl)O&?xE*M11?Wja=)-WkYkEXFMg$!S;?Vd9&% z2hR6%)vE&>c!YlSuN$E1Tctp~nqS4&0kGL`+k6P+eB6WgI{EDBG?;be4MS0aQN?A= z0nh^lF#W&J7kz^OTyfYfJMkVI_W%b18?Vxq06M}5r&T12v)5h?rrHt>47ejg3!hJ4f7my}@ohywR3gPaPnbgm|Slxf&- z9Far_RlYZbFgJu)Mq-gcFO3$FWG3n?2R0rl+&X6O`s5)77Gp)1UB_uK!&ECZiDhbWOfY1MG~)~p^#a#zve#U8vNkl$gM%K(ZO zyT+95*}}7E2m&h&0EIzpF;D`O|IB<&u;iDW!m18P7i^EVG!#*tX+NdlcDFJu5vP3G z8L+P(;aBcA&>!7s9x3D73g~ndtA9&=bLh%FxQ+yJnyakYjIgJkJ$XgVM0r`VnYy9E zeTlX)ogRd*KxTa%356X)5W86VPqA3~(LZAEm(>f+fx5t@QVve^O$;QcCzP@dfg3g` zbeZK!pt0)4&~rRCoO&NhF0G5Zlv0$T`6bP)R8Heu;I&G~W_793{}>_n7lN+bE7?`* z4f9f{L;HH_J(iWa&z2jD{Hg4IDvj@q6`7B-)A zwQ*9&=^e#S<=34DK^)vlHHo@sPo@Au58NN%h8mt1ai=)FeM2#95c}f!4-l_lCGtQ( zezdtH=D5XuT*ds)n8_L+?rf(JM`2)Z6W38Q~|73a;kqvI0( zk9QF5bMCyd)&XA{#)VE}Rk)RUppjcR=;Ir5B^^F34Q1RMP@JpkvUicp!x4doNEYa` zOh5m35{@@V{oGCBxgsGBB6C4gc~pl{o7VymYlFSh=}wTo0W1CMhe4dCh#hU4)(0C}S zx0L#@MZ4=JzKKH@B}!`}-JSIee(zH_w^2D@r5cr*?my95XnP;W>3K{Kfew?tnJ1pB zcK4j5nsyCdO!0sa$x2a3M2y@jW@WI;Y0*W4KxRR^H`e^eB+>4dnuX>k1p_Egx$BOF zi^IcT7v!MlfYj0^R%}J}9;t^1Fm;N?n^h?ipdW*$q#>IV;FKbK2VsU&UAVH34gCBzppLPPEQWK6RU8RD{1~O`hnbDMq zvV&0B#5#h9Eq}ddgi=Jv(6?k-63R2373opO3Cq-330JuY?P&$PxSpzDfke6(Ih-}M ziNe&*Vmmu@=dDNNn3_atI-dc_H!R&-%7z>2y4O7Ia6gCE10XL6q5AcCKqBqGf0AWu zLScK$+OZ^``gH;>gyoYg=$2eW_~w?-&{F&ZWHJkek+>OX|LqTwWLm&(fANqk>~I$% zUB7Nm%nr!bW-yq2lP0ox&DbI#w~3`!HQH1t+uxVrKY??A`uWkh`cyzm?)cR&1D@Cv zb&~nuqKG6$5PGRYq25#T-P)Sb)g^C@Vz-Eu7hAX5S*~_7?kc1`1^PM49i|`DjMD*) ziz8)*!u)oR^CwPw8Y^&bzOPi1AKWCdL%&R56gryMgfS+=EW)#RVXB(9vu9f%v;AY4 z8@_%>#d(l(8PhFc`ZdC`B|XZ2her|L34d!uZhLb=kp9VIDYB(iQqXWB;iP?m>86|= z9_honNJ5nN5n6kH=zIT82>kzC;9IvfsLXxm?LD%!uvoWIIy@bwEX=p3J!Og5@3mt= z7|&iYL!S#>M%Sv^jjIPK|MP?R;{#D_2;^EG^FZTR56U36y1YsAcAztw5;HTJHK5H* zaLF`RxN1HX3OYG^aZjG|b29&@e5qD0Jq-S-t_>Rv-P8PvZYs(n9tht-@>t)?I&stZCG_ku2 z=qt7ZiW^Z~Z?F3MYf||8J6uv8G%8S-%9%)6q97KEr3a8}*AACZm|+maR@trtq&;HK; zQATNmi3PW^-J5W$YI|Nasx3s=FznXKA`bc#DxD5`=UtzYM zT>ucAoQ0~RCo?STUyT2Vzz0ez%F>7V;UQ%XiQ&~9k}rZWqL{9Y%5PvYfCN*xuFRTc z&|^ZqTc?4+KJdk%X2@Ro%}x6)z@PPf!V??KS4u^ke=-)Bzg+!6E@%zTtI~f|#Zr@Z z%cQv#Z-TqOhY!L7mH;9_aN5tF_0O_PhTVp@OYnl!DKxjfraogvwaTE&vi7AiO>y7r zS+!zEhZ1Lj3|}3A#FCw-4y(F?f}EJoc?a$3=PTR!g7lC)Rf?<5h-d0SJ=7 z&3z2d9FnbLMnE!_s-QqA!)TY(e1Gd~yJXxsJ5n)EHz|0La-?vs&E?=%C4Ax2GJEjg zF$}wEJT|h(XlF3jRJ8q5-_fMY2Vg{hZ5orE9gvwRD=?wTSU(vdQruc z>NxNx$=WlpvWC$i_Z;qXhk`lj91N*Uw{D%LA;y!rxqIgC>eIADbaK|d2g96NtLVc! zX+!5zrBQl_F!fmHGEhNrpYPbARy)`klg!P?`}#B2Hit4+DL*)uLJJm%jaYapgKS0Z zow6ygG%+^A7*a;#m4CRGUeVO$DL>+g9CPN1?h2hOwVCZTwIMf{QABmc@P7Wd@wHlx z(9^G3{ve7%d1d3?Q!-#=4em@O&^F#fh13IInm^E`Hd6Ic_sZ7MF$}tM=$2gNL{k5| z^0fL%!*1$JA5(bWjAP0e6I=G{K~Yb?#)^#UJhi!**#&9ShG6DpMtXY5-puSQY$a77 zp4nsN<;@>9#H~M!Q)DMn%+`bUCqycMxe=*7&kJ)V$~h<7kLBIy8x0>F&Uernw}dO- zAyFhRuSIUqV`JM>O7m5Cz|=?pB{t-63yPZFASAODvF~H>ml)2&w!k*kXp53~wo;Cm zX@|>`Sh}|2Rdn^$Hnw!7HcBDZe72UYJw8rx1sL=IUpUVI`gj%P^~!KE?YG3k7+;lf zRR>UKxTieC?bZ2aQ4g?|pBS(Y_wceQk#CguM~uvGP3T@rOj|p-eG>KCOg!Hx;}Obv zkG;WbUTS2pU}(S^Dd)Z4q1M>H1`WDXK^-`S5(lE#p3e+h9S0HBC>7B}uG=~a0OapW zxzR>qu~n-YW2MpDmtW3_O7C%*MWQFtVIoF&AcpIXve9`N?K-4nfgbkb#}iZBIf8zZ z88^6^0+)AuIecErQD{-KTe3bwd^4RFa~ZYEd!aDEee>{SR@|Ov#du;=X?#`Q%q+v0 zVfA5MnEGoLuQsqJ$wvH^QGx)`^W&0_Gg1WM8Tt)!1TW$Hl3RPq=d7A{WBgO87&P=1 zZYrvKwiOOiDa)3sxZ^t<9f_v&L*w_9?TC8=72ovDUwEBDSN1e*QcvtPAHR7P%U*}U ze9}(E%Sa6pekyT6a=PT7qEE;kVO|DU)5ejJDSHzsIG99^-!+Zn zLX{eJ74=nnz>li4qMC6(R55X=FiHR+ZBr2utf|*;TV%B5$;{k;Lt^g5K(y;D zQk&po46;a}Efr^r*eOFa+T&R_e3D8}M{)?-Dz;1a5PWU~p>6z`tEhiAxGQESRUUlA zS9t~~X}<)>B$SQ8!*kGh)iEcX&d%Hz{=9m*P|t{xK1>Vd8R(j*s>ED`v%ArZD!y&m zQPs1F`*bhBY7*}?p*n2rV43H@sm zVtiC)|p~* zHPI|~;k$cg^M&;~bkeXM7)DTHBg>)gG9mc&{s+0t zVl6c!y?qXeiI1w7ip?bLba@Sg#B1^wMdOxsUo=^&1n~{JlSYNSzQni5M8Czm((%tI z2Pmbsn0=Fz4RN8Az9mYn49h%)qfy9c8$VIo;sy4+hF%OtPx}`poEZC_64u0clLw>j z46w9(@+_E>oCrSmU$~WVxnDb18}jsxxzElKIi#$KFB&2qWrx zBg$+GOmUpT6RZZ@G+kwqR?lhKM3*>8&dOXDjVGyONAqH*_>%ERIQ;TDUhm(xeq?=M zO&*9+iebDn@cC5qD{CZtaqNiY+1ro_*^hOzlxT2J-0>O1_)1E&tP_<_U2jd3v6oR>_q4jSF_Li{}-=+Cl7SvN!3i0EpWXqHXqSVRD!4P8NOeCAnfZbg+VO_L*f<;QLlpI~NjwTTVE zqU~hoO&_`~H#SudK4!6)4vKCIx^K@j+%{RTz*^(U>Q%v4x_Y@$Yh%6mISs{F5$%Y! zZDKC_tXZ!VM%j;6Z6{()+aqIGzJ)q_QOK!E06Gkjd8hUiYbEzl^B-762%$`-I+ea` zAh*b%9cLJIKdVl%Y9xZ#y?bBHb6|df8=_eyfFtI2hCePh#6~JihoBf_5LjyDee|P`VMgYaHL~v9AN3NDH56IA zw&J`la>~!vku{r-j#Qcp#x{tK4fxyT!te}>nP$))?FoyY9BAqu^tQc(x;w)Z0cI#F9Br`638fEtl%>(lhjktu$$KH6@82 z+ih~a%VzHckz;**|DdDNw$N`vUB>PcBIyHfMKiR^HZnO;?EF$|y&YYhi)5m&E9x1( z6$Bh7-Y!d$B?{C62&;i8K3ip{JFKwGXP;{8r{A@>D_y%yl8|fu`(^3=*~JTZ%L?gW z$FW@?h5@}cp4t;qgAq?Lv`ka`~>A z{qa+6qGjj^YOdDt_y|`nkss#3SNinfa|Y(MW5%b^CRwExMX-s zBvxh6x;fW;8RN^eGf?X?yz}U()&FAet)t@Dw!P8D2^t6*Adoi@g1fs1cX!FFWbf>goqf+4=bm@p825YQ`=eoW*Q!<3Rn=>)IppHRpNX@3Mar1m6`TH=Vp3zfys!p$*QaJaCUdbjr9hfGSt1vwbXHQd{Z0BC)<4lA5 z3StQhEa9kN+o--yEbrT<$W~A1A52bbbe4&j!&~K&qeXfPV+2Re zOc%<-C^4S6TZ)Uht~3Z|!0nuW6coTB3OOw}kw@gYFl!rqmZH>jw^v|?xkdqSf!-Ol z^c>yXzIxO+U8Qz&(>u%b(yCLKPMtkC#X_V^(0Gp9zHGH&3I~4wb6%a-|UhLvdeJ zVb4mnVt8H?qg~(OZuxQ&5&#q%L1K?^|HXrqEBgB9&aq_kRnH&b!QDQx@=YyHABxdc z4TM=HQgvQ#Tvn>kxkTPbIlWo9l4IA7r(OkI-yiaGTM?!r8|cxGuaMp8qe+X5Mi&IyKrqlW!*g?LfScFsfNdyzE1hVtCk5J|E-bkKm&;wD0C5Ju zWWJ%8rn*I-_u60lMh}WSqzY%7djNi3S=Q`M7Wt|RY$M4hxp5__(j9M@g?2;|5VN*tCgWh5cZ+sm?^)plOq4A9mK%Uz6@!EJ&B#)rO z0_YHV6g3_^ZoCNkt8608nEjAT%zC`Z>+--XwKut=nhut2wp2Yw#LqY{%czeqS#^F^ zcn<%$Ck@obDm4k))%R0ngse%0_u!2i$&OV_U`u{J75awO0b4p&(SXjN#Z14q@E`V& z&dvJlwaK7+^S2b`4ba)T8R2Fug8N6DRBJCgcW=KD6Kk#)?t`;udo0iF?Mc#wttefE zYvyN!lu`Zp2IkK4_V@SbZ^R5O%HCB$rcFsCiOY7I2P$PKo2JsM)p#ZHWwJN7&FT7_ z=-onp zLAY_hlGAlvHpcK`&V1>A4{Lj z0`-ZXE*uu*91^Nr$huv(sv9Nc(ua{IL@mMfpczj7L8Y z=bojWzqE-|xPX3VD#e|X-9d?7cuG{8maS7t} zWC_pUk8y1d&x_dWXtyWIE3aSH;vveFNj-ili;NvJ>ALLChnXdQ_jq_jIzjP4*V96l z_gd*bU;-vfV3<`so<-AL2Mkp)ek&5m)zVaJGtVi=oY4hj(D=Rzuu(6j$r`MxR9MSnv4DQ-jP?=<@Z-f8P+eG7#JHkFYY5Q6pGJM+v zttoe^vWYcFZw`^4zE}}(CCuM49aWNo(6(kidIx2b{7#9pzDO~9v6KQw%L98 zX3}&{wtm+XFbu_55J_Zbid5R9InM60G`N|oqvwq58s?}0dMPd}O^YefV)flR(hv42N#lLjU1LAjrZDw?&Vy_ZSKx{v*+el z#tvyC-iwK3di00HV8QRcgG!_Z-d{mI1b}eo+m}Ov_irHpMzaSQknsSYNeZlo=$tp@ zZKPs6^CWO_lhIyRtPhjUGmh?At(gvvN(2cMS!5+u{1$MsK~ENhtkS-2VN0e=%1h#B zrJ~$%6RPfY>jHGQVIz;wp++9jg*RJ;Ry26Wm(RsJB^BpHlh>)t)pgFUw?(xnh*Q4t zI#zykT5>2n-j@z2qxP^Dk(L2$pn-2EqvTL>aW@Lg=6{r;f7_`9py{6hkr5Tlz_+RWmUqo4A3U{ zFX;Kda*ou~^ZzB({vOM3ql+q_JRf;L+q#z9q1Ge%EYF-hsUEr+TFNV>U^@Z|L6O|u z;~)Pxz$RBp2%9P97Q?j~er`4f5~7dEJWC(fP&KFm!JxLIfVgc(f=Ul^HA(v4awuk~;xKu)76w#sb>OIflc+2=%tA(`y z9FBd>Wv+s9c?2-qMdoOFBj%It$nqEY;!`-s{_sw`A^LfF{B0)m%T?EO{4WexBvwQ7 zg*wR`2-x{>V2~z@IAX5pcwQviK2mLdv+jI7wLhLGvvkX~7*A_LUS=9=0GSpK*vZN5 zpZBkzPDK>Mu@R1FO(PdW$>#=fqj>xRgj2F|bf@J>v*ZmcyI&~jH>Jc(hNsI^Lw5S4 zL`7yiWTLk4V~_n4^)58qdge%gE7j`X4MFPV#+vuukY=dSLmMFKqUxL>8Nc_C-CB6b z$#;fuyG?dFCY^@07l&8ekOC{3001dIB6eK+=m#yZwxoZDYIL?YP-z_L>-QRr02?7k zVQh2SVOBUzndU&3`F>_*!0?`Ah+TP*CJv1%u4Z`jiqoQRvY_{j&)xW%v(Gb;7XihG z5h7$(32#?O_4~l~+|$#2Hj6QVs1e)|h-RVn_+LRYjE=k%M#_q-thAqx4 zc-$c`@gz-S^W?bfX5Slwp{a>P>R_)!cZ4lcq# zJo=2a%&(N8S&vd2J<#y&7*4`eW~z;eA2jni_JaPTBbwWb>;Uh3zDv`Ekpx>Q)jeC=0BdHKP{!LlWhbGhOh#B}k z+TX(*^#sJ@)jNVtuU`GDG1cGY;{moBARj*tC{MvLY7JW4h-D|B9<0sQ)*w$(A(6++ zP_?-6`+Xzp2w87!)i_<1uH1dor~6eCzS-Q}+8XDXqm>F9^1UjHMKmwZ%)fFYQ&E*e zc)6@{p6qR~c;#}vm6smVhVLA?PmWN08y-z>35aeCOb9flS`8~VDX)Mx-1;BbWEa34^b zLDny?49qau{URR9TTbJRE4LRe)U-UE?khdAYxVHUeET$E0#9Zbt_s&S1kr2`2S!nb z{~0@VNlRy0rsV^g$VxHZrMD#E6q zsU?Sm^TWI`d{X|7=Z5KaF~1X+alQkXFfX;Ve$fv7Q#Xyc>TlAZ_K$#vI?_|%>OyDb z57#LiAhZIE&3<_?I|y8&Uc}yg1_M@2&{IIKj`YUwM*1sAkK!w6SlVqGu!3B!m-xc> zO1gUD$;XirD+oH5QIIOHcjcaFjnOd)_&VPP&S7&a#d7@d#G;4zx|09rFOthu=1LXj zMzh{9WQMFrjCC=Wp8I4*ez|+4KH3$?``T zlZE20WW>5?(9XdF&x*V)?zZU#%~>$~Q2qEejVQSRcA0-bDjL4kplBn9n**g^@w}He zA1;7ol^qW{rWL^5hMsfx9?RKMI1OsQh@9_${rs7$n_O5QraKj>cixU)(__)RY`Dm( z$SU1D{DDj!-9fCXQ5XW!-p%2qNsh^Y-GZy@DPBHMn>k{l34?aAKtf zqNx&Pp2+K=lLG%WM}F)|>NWwK*OfH`znf+SIisSr5#)RcQLy>Y`yKLvk4o5=CEnjl z73a)sfnH6>b&`44Eq8eV41OfvFqhIeuXAE>`xw@&&lCYF6EGA4gWm%+|8rrD>RnQ8 zf1W(eOdBw-Dfx%j?`R_KT}FrT1TECX6z$|Bk-I+RocjD^&xp(zgpqmmitG(lo}A|a zQNZJotdZTcS}$_<-ffEFYmCDWt8cqhu4nC@*%j>Yo2u0%k^X!ziJ#x7t7hO_>Q8cI z&GvEg%4Vs5d4uJ9?sXBL@-192`5rD*1?A;=b^H#TrG5H=a(?xURm6*;z?>rY@QE*> zf)8rcX!t%#)ULhPApiQ^6)-Rc7d(M};FkKQws?SY(`~W!6%w!_{LU11@c8+iqgl`| zZg-=vu;uIm2}+X$+==jv!a+#zC$HU58vkv)47Ow>InM`Wc`((7!qr2(aI#BwBBzdw z@kqkV89~B@gGiI>GcS{wy^{sWJMy6nP7kR`QfJ((svwR*M6HfMw)c;Xx&1x~Ltx$* zOgzYVV>rb4o-z%sk|NR7_dHkNKI_%1%&z+ost^cZtQYRKUTzKR;x1xKU*yBPxZa;~ z9-i{r%@YTPt*TV6*tCkHzbq5_{E-G+b8iI9)o7HC2+2@jZ?Do)CbmA(l$+wbC}}H{ zIXw0jWgQ;l9T<@YOcz-HSQX!BhwM@-`1(nis zJPzle&uioNT0qE9rYX>h<4IR4S^-boT5XwJrS_W=8aa~BV%25df=}^@jW1-Z##B#c zkV6mw{w0%f7cF);BcIb@yGQ=G38=6j{PJO;z#j?~#WOk@+K=5e0*nPE>2corOIXqP z_2{>8d;P&2l1Gd>1Ke;i$z!Lmt!-HBY>-ArP&*6pOg`f+NmU8~sl)}Pp^9~i2C_rHj}Jwhg>MxY93bNd=6E|^y=qw}7O_?-8N zt-7dDfu_#n^oxkud5spj6kCcI<%B9wvI%VdMYy=V-)K?bnXS~PCqr{V#TizTTX16^ z9WAg_XImdYDuy(TFB4HftM#uANo5XZoytU3 zbzIBd&yl}J6bftLO7H2o!VF|9=(IF)DGn`9sg6Ubn&ZP1xg5_f$=Kj$4w_=H(y#SL zWXW&lY~Hc=9Zq(*C3-PvRaD+-`B1|?VD@vXG;zz9H z2LET!b1LtP2}zZ{Gswqv`z3o-oLOql`>=d9p=NlD^aO(C3JjJE+Vg z+yJVzfZF3BRdogVP5{eUN9v=z&6CZOq9$h5>4}@SdzW89Q1Qy#pR_pdwSkN|KH^VV zt_97zCNE7r3FPpnFcxt2-pFZS+Zy)B+1bpRuTN)(2o~Y*wP1s|Y@?2n#t$T z+(Wrt;Gjy?9~hV+u8)lFt(V|}4nB1)Me~KUb3z183K-dnhdWky+J}y9xSC+!p>1qr zunjMA%!XVUd9ynHp4h(nme|&WBG2xT`R^$QMO`YBXr}C|cNw<~aU9Uc1gTC7 zu{WeMIr`9Jtdgss*F6?hMdH16O&@8WM;O_&va(2xpLWk)u%+WB>1ONe>WRct1>DEu z7qc5bR;rlpEe0yL8q~iPe9eL%H33ho93)Mhz0lr%Je_BbaFJAfIN>Am`3q0zAP*Sp zuC=DuYHGIUx)`9tNNA?07Z@)C=AuNJT9ec0d~x7p6E>oNK!q;4&sZIv=8(b#EU(Uw z-_{n13s*2%yy;lMv8;nO12j@n45%+RfVD(D`R3oWM1R#5&DZoQB9*FAvf81jc`q4j z_nBkaOrKOew~ocA*nddD%K)Gu2oZ%3hwlV7ZjjqvsU&XnL_&t-0k!+SA6w$SZ}IYD za3Bte5Blwz63`T%^-NikzKvqMg|`xrJILwx1$F{@1M1^IZzDI*WE)@Q{ z2{_Qt-9dwb|LjiUOmyJ{tNNCDU8u9mWG(%!E8&kWZlj)mJC4+w4K6|kn&eD@p)bFK zY`y;I?4@i-|Eu1Hq%l;OkY4&Mi&r73R$#ZWx(@Z^5)jtt z;?ySfY=>Rs4CKpN?iiN)>~~cLXv*U0UT95T#=XZ^Oc&;kI!aX8KO2u}G(L+--k0OE zzu6?x9F||I;CagL??^iC&0=L;zER9>RP!nJ^?M=F27_tIMKq?VsFOz(3Szr$y-YKj znsZW68y3wL=j#~DeW=%aYb1i}LRlV_o2$K8co}jtjzn17_1uAN&C0;TS1syw$SXA* zicuk&9wR5V9qU2&N$7zbo5~Lvb#+Fy2U?<6cPX~0g{2jt{lmXKZgd3^-(L@?terCYaG(T|Tp-lA92G($j6yyLTrrMc-LT zDU)u$-J+{^++LLf9+SA=Jtp9O#vp z8onSY&L%Khq-XUy;IoIkW#rj0%kStyUymhK?1AKBu8M5+#Q3i)EXzej$V22p12tyP^ER6ZJ;IcF2FZI zyfuBLKKwrBVNx7CQrq(WDe5`NbjO{S9lpqjWteQAH?%-}Nm>A|Hf86PLypgY~ zwIiX;nMVClPmQXCFOmL8DX~7+dK7-(8?Ou(OUq1%L9JTmQDUzwAIL7BmT0AWb6P%^J;X?$42a(=AvyLa{eVY@^Npht zdaH3rSlr%0svp`I=&y0R2gIL>V@=%t0hsQOu6L}mj8T<%a;C;;rs&CXu z>OCWn4s11HNbC(js8TG8&^CwN0;x}tncOTa8PVmSxS#NbJ$pTp)zGs5`vJhghg(k3 z17rh0Yg2+$eOwF~HWx;)39jP5wEcknb(Z)S?=fDs=p3<_H=a&h#cyr@#Rl$Ave9b2 z`>z&nwC@l1Z-Nhj+3WLH5M^;P<0<%VBNgeJiNY^0n7`_zmr%)F+yY|Qv>snUS&9>d zCf`;Fj6YTgU8_N76N+Q{Q4-@|?xf`ciL6=fvWnJ_OqMkG`$C<3+r!;k!ng?ul}R27 zE5>X&iazo(bte-U6xq^iu5zmgES5ZQiD+j76_nR0S8&@Y7gRvDWZA(Qppm5V1Alzn zOYWX)AGZ#gFYCDRo9Z5t9`D}ve#sd;4Wwsinex2cTZKONUtvWb@*C(Y$K~}MTuvo^ zWr-5)!>*f}?=5^n>~xm7VE@g(68Hmuu5)7*dMTyWk~0-uik9(O z<@nC~;g1GhX7gTya6m$_5eg{7J9)EH7dGx{3|xWCbk2_!fRS$Kwg6Zb2%<~e-Dv<7 z*=f*dp@$UFa?zBWF-kSwNb4|+2grtLM@nCG?7 z<8{X)h)2(MQWcpU**n3&G$Nqs1~ci7Qm5uM9h-8(xb?>_e?MS)*;i17wZMkXkMEIP zS>l!&xpXUejZ_6x*gDH$ioo%0+-n)(m$;5z*Vm>13vJu)urd7f7U|W8YmOB5L^&dS zpA+FPFOyT-cf|QKia>5fMpKj1GB^-vbGVvh&5z>u1nR9$LzftVMEQySwMff^3MqqV zuXy_n5&G4`4F_Nn_+eBI68K0bu--m%cguL8a2p3GR`7EyoNs!4E>aN0_4+5w-cuaS)Lz;yTDH#SkyO5&pz!T?GERxM9bc#C zWu2#i8vK%6bipy1D%_^s?m0~4fI^#yJ7N6pYehJ|!fw_PiY!A-7tb{rQt^ss=5`j! zqT|QRSkmuiCQLV632|WRT-~kptc+`-40QcAz!Zrf&`Q(>O=0|A3VL8YRE_){cs1!j zvZQWAPirAdk(;>jAXvlnr3AuuI}UdbZF>%q0Ij#GzBdLpN)D3$DcG(1_~nJ{pQ@WdIj-OXEYIoVz5!H>+%kj z*K{8W$t`*{Eh&6MtJnEhI~qs?8yM1X+@hU$C|tEUV&Vj69)_{Zp7Wv^H>k*AnKBw$ zJ5}j6+fw^ePEIknv@=IujLM;vx}>cz^N2Ybk*nd}Q!;pM)9TP^#k#4+biu7!UO@dW z@2uJ&F!ORC*3U+@gs=-G;|`Wu+iM&ENR(7>cvV{PRz?k6s;uv1?pUAJw9hB!lt@AE z4ouG!wb&lKhz#xh;H`?W4j;07Tumg=~|c6B&z4=+`n0_t`2VGFtc(b zXGrJesL}AQx@oiOcoQp!fFB1u!GL1x>Dfjt@H=h6%o`P>v;Q0=+Pv(DR>*zd?V*SK zkj2VKxil@8B#Q`2#_xLD?i*5*KjZ2iZj_<1_&<7Ql!5mFBccP)J`0Mk+0~va#d_vr?=w!bLEszFqUs9;DnyD*2^q5@U$_j zw>ha(r$%&&(!h8!``8Z0k-l>fz}%?HksbLGCS*;u|K2KUFXapGgq+f;^(CB+*F=5F z)xFf$f-<#;)4gH&vO^F6!f^tdM3G`Toga3e$;e2nrnwXJ$Za&jtD{_J4|7#06|K+u zPVhYCw0C?=Z+oUa@Qpm8*Rx80PWa`CL{DWJO&9N6#%$BKb#HS!CGG-J(cNencORbL z!Z|G55CA2+c9Y}Ng)79(g$ux@`Nrt`fGMB_tbDD2_2OG#ZTMd{(EipS;jaxE|64tL zKg2IR{5S`6?fJbgGTa*Mp~>?ro%8y-px2SC`#oVa<}zHm(F5dh#j3j9%c&;{H{_E_ z{7!Yics}?1D+mr4-$RDhw=?eaYOU{(fEj`?64}ebcSeZ_`s$*KgPrx^IU@1S3^&v^~YCdx-8sw)~OBvHv!XW$EZzc*qPH#9}4yh zDKO`wG2@>(-M<2ccX}`{4=aHQO!^MT%ShF0AhhcCO6QKncKWM?sul%;92|b3xfGi_RV#WTnUz_0%Hw^&L~{aB!mr0STG>+sQ7`De;#_( zMs!T4DYKq*5eY*&?kk{w{6MGHMEWFIj^MPYwsp+n=_unnTb5^myGA@+q%@r?XWN2A z%$;Se5Nh2*7?|k18=(~sbP@X9`sdIy2sm&Ljv&_bvN9yu4WnTj>0cSNe`rW}HDbLp zJTF%kC?dgD^vKy85m^NYca0Ab<1AgyqGY$}tOC}%>;g21gx**Z4%jPp6sk%+dB!jL zv7+`(Xm4<0SaL^lOf>Iv`uRLBdoL~x^PIPR8-sb=zh55>o` zkr|)XhfdAdvm$H z63<*f7m((=dU-;Nnt+Zt|9MB40$_kT$f`1(uAq5P@4+$#Sn&7Y_Vyl#u&p6$i+vG+ zurMb+YhGE-;J({w8 zWwgu^;&n3Lk@*DICE7sp(brW;D4K1swB75j26nx@f?M`8jaeijS2wcBJe^PLJ!n{d;x}Ct2mlDc3^9htou2w0flt4!4C79Y%jrC-_!b z`vu|fpSh#z)Yd0=Z-G@LAk;fI&6Y=g^ohn!v*81eMqw(%bfrt?gefrfFgD;Sn((Ps zQ6y$B`Stygl0HRmR?I*FIacV0a!AYf zU=|$4!KZ(uVWSWMgT}SrL2;Iw&^khK)IMz z{7zaid3AXxrSCqSJs#2;oR5;1`*1MOwfQgM$w8zRii;I2l@b;IK_Ym4!Fh)eaY9VJI6yo`bH9D&j<7F_8H}CC;S1E|>6c52)d2h)U2jqzrsKo>0-(m+_iO z+p$J2L|w*L{e_olHdqdXR>@d^<6Zclz*j+B*}6>qJK;)!i~A|dn%N15IxWssWz(9n z;}8jQ@kcKRW&k!RYq++pR>>5gSF-*NK9t$fi4`c$CTBw5M?kN{PCIn{>PkfSl(LafkX zXrstEN)rOMvVA*TaW@4bWqYe}{oB5$5)6UIhAdOl(r;<`(8ePsO|OYUuPdUlXe4Y& zAw=;x-$`AVoBWDDiwgd~7Zngm`uY|R9g8xZttto1j>>snB1C(0&D0TJo#95;w&$2R z66)1)C*nC-40jLZw=*E|$mbG*90@s>6DJfXQw-^c=fI{`=O`S7eFO|hshk7$m!nS8 z{Bg!i@e{J;KJv_;sBtw&<)1ka#$nI1XVs@1L`ojXAv-FEq17zj?UP}+*(Ybj#|nR{ zjUT?y>^zpSE&`ea$(~2Sy3<6 zdq7h*3go}!R6Ek^n_pA@MAHUN0^cqt|!8m_b`J{pn9Nv^!t@sSSK6yJ}f2uOg zlXWZOoG5=4*eJe($85{Nu?hC8o`XhMyLwWXr?N z@w6hSo5|rrFsi?VZy&;(J;$D#6tShVZ9hu&i0oMdVag@I@p?sxR^olsl5l)lE@%5N z222R(mK0-}K~Y^S^;9jF!U$sbGR<%$22mjX$S-Ww#+}C_+9>Si1jDFeX@)@(`$QF{ z-{R!*9f9?$nY+7^i=o>bAchtgUpPPYYX2TX|7Y89@Yd$nm4E9@e&*Cn>BMRArfc)n z#@_*Wzt%FJRM%9M2lv$^bL#g$?_3i1%+5!5mIM~;Md5ewR2O5LeSG!?0w-Q+W z_RCF0X`HDQxJ9t=I(Q726zT_(7VL`!c&aBe9FS){r$qcG|;U%Y}2+H(?kf?U*_(Ps(q=OVXs+n?9cx z-@iUq5jTlOoY>g2diaEHMU zrHLe-(6%oY(4zSxPQDUYQ(%jtS&;8OBb&z4C8U??&41}f=^pJBlhr2qj7l0Er zH4m6^QkP}z}#hb8A73Yw%fzBvI22Ado-4H zMk{1Z(m17er2iNqKxe6lAq1D&oK2aaN3v8eO>0=oMQIo)l6ZPq8t)<4Q&Uq{cSsj+ zro$dBKV8_=9-ytL>f>o6J`~oHx2-nLJvP>`+E!LQYMi_yhFU+b>2jYI8yVf(l?-OS z*1Ung`zy$JhHiJy$=Esx`_t@cy9Ca}aQWtArUt(P(O!ZK;Vdv5XqiOt3*_$8f!D;W zzS>2yj696FL4G>*yb*L+Pi7@N+LEW#w_n^e8Do5Pj1D>%lQ<(nn!r{@$~@=qxk=bA z5RmL{Tx9hrPLKTazP?2t2$s?$`hC*|K9H$&_%G!r1c@!%8;i1I3Od7D+ju|8bOzdD zXWUmh^zqzd9iSSn{HG!m8Un8?n7~L=X-9@nGsAm`G?O#KE^|}BBL+3sBAaJL{LE|R zG#UgQn#MUeWL|5=8?_5(bFHcB5(E{OS|QDyQ4zx4T$*0^fM!K#cL{oER(&u9#|QB( zAEqt>c(RQel7{>?kdf(hD8v*Ra1Pz-L4iffN9KHVYJ4r*a_3dlxW5HRm8t{y#;+jL zNw0y^s@q$g!;JrUWA1K_|MJTk7eg?P$o;1TO#M2;C4aX8_-9tj|6O|k<%Hl|?5h`> zPQ%>+rG$yzy;&mqd&yjz@kKvbD@z0QGSYK_eX6@)bp7(`@y zq*U{Z_EJXW)&krlZ;$(px=8D}2KtWd2Y5%7?^lQP>s|UT^QM7r?-2<2flT@H4Y)iw z=E68`hSx*ZN$p2b{G}62iyyflH^bW`egC3P+)k9iX}Q>C`7jk#0hL;bdWbGgMTE|*6$^{Af9PYFPmXkf%ig0U zHuI-R{p*pci28{uNpZZ#@^BHz>E6$aiY)fXs~R;p$rD>qB*_&w2n@U@&jpfH%PWEa zR|^wyZ05JgIio3duDK@zmk4S=sT3Y4|B0ysAZi+-g!hHJSv5&#BG_yY4%Q06E`b=3 z;divupS4i4n$QP|ZyozoxXA1LDo_{CvdzKz*f8ezdCR;p^gS^!d$gE2*+AvLgiZe* zC=o1(`j=HMrK!p9=!B4=co204o6(=;^CvIeM$MGj=1k;70}QDC3ghL(6c95Ke8 zw+hqdjM5*_49{j>Q&4|A$U(*6?B^ZxtJje<5$OU zJ*=HGl`$)&6bEuhVJ5KU52GhSvwEx!Jd(FKTwxSD$l&~RCyB2ge$1L1a5blh#p)mq zWQ&Xm4Th-**b*F&6B6Ep2J^n8;jVwNmtbfEV-H>C z#XY2xd4azi5ZRNx(t5o%{7gUeb+owm=CLGZXAY&9ZbsC6#=}op&e?sg7UMPn23RcI zgw9N4%-z*ZUCWck4LVwn<}yv!AYSEQ|CrQjD1}oK;Up=XH=mh*Qof6^qU$c5HT_gG z78vm;G@298lvpMhc!N=$W`U56T@r9I#FNo;MwHYWp!DDqhIdqW?|6noVO@vPA$@R^ zH=Pw&;DD26={enVWW)vG3+o<&TN9Yw;XHMqe9$a#>jtDe(;Czyu+c)!3HXEnB*s5h z%7cg%-#p=PB{V`;2OW`@#hu+vah1iTv2#EuE!@)6;w83v*ps~7Ba>6lB0)cKCOh)OWgR;7GmS&DH?LdnuZg~jhhc0ewsMi|V zwH!2$p#+(oTB*qG^Gg2h5{HhP5g4%;l{_>#j(O@+bASf-XD(wElXEy9oLnwGB!-OS znmkKlupugfBLWhJpX72iZ%|)DpyA=uXxV%~uumw)9}w*8%szQ7yD>#VU6>Thtv3g9 z50>ZhuGAJdzqiE~zO?yjw|KGcoizO0(ZdmVQejN8>xUv#=^<6cL?0;}UNU5+5k93_5$zcWy|gy`(%yk%6U0pN(8-%2jX377_;Oe0GaZqOYGcB)sYhoA?MuL zqI!f@PkmT%xfhGJr@0LKJNqZ7QxO%ZS390 zF66kFj0Gr!N|XnK2(9T^$D4;1>bviTB?w$&GRY*?G&#b^92sV*ecIy zZCxK5L!A7W&}^+=3$?>gAw__R6P04+x1G%~wmtY>u+Y87$GrZGSv(N!cz1pgoXVda zIBF@H&Bzo7|4BhUGieejm4r!%Ds^A3qQ2_WZ~YZ$c#UCvnHh(Ez`=`U* zufyLzd;j03{%6$y3CQb|Z??i>MO6P_?eK4LiJhzn@zCNvhEnQ!ijfGOr6QXpNH|$# zMp;lGJi*qysdpyW^SJV?a*_rLd=moaOMohMCmB&XS6^M2^0r70Q&ef5(s6@-)cTKV=Ldu13j9`6FPv?u8eH4Jsu6ywdc zCQ#4*4IspE{B#^|ZW7izAr-IFW`PqdmHf)Y!g#}U?ifQq7WMtuf4exFfvNao*}H3;|-clq%^pjZ$2+&GO&Dn|LyhI0C^hm zcw#b9X*6hL%NuiVtBUp}Gkc?7N97Q?iHIFur{sza>1rInAbWkL&G8y&FZl}c4Q{;S zk+^wM>wI%#PI|!wln<6GzC#RuZ&C_0N%+4_{?}X=GoVz>`InmnJhScJ?$VDN>Gl0a z{X6!=Sp3U;qy5y3Xm!kv|%A$?&8S zY-RX5cRz+;wHgHChDdI3ttIH;?0c~93|-P37Mct zeoClvSq^=HiC^G^8#K~qIP29p2Bf64UkO|hIBl}^;)3$k7Zk5+;sj%xI;vT zbX~E<6g;py$GW@rz!6w@-pM+7TyPr$R`Ioolt(%}p-hC{T@+`8h06pncT>hTLwyk; zy}ncn(^OP9 zk7X^oJUVTqgAZUFj-^Dn2=@@I%~$4(z-$qID+d^n0kPgF5bpeE^1CSKP+J|LmEPn0 zJ@og+E(zqfnPkf|> z{dcPPalsF&_&7l2{e020bhSOr`LVRF9{eJ=t=N$$@IH0Fr{aq7K|Z&03%WqdmF3vT z!n~YQ<(@Q!KgD%U$g?iem)em*Sp|m~I;2<5z;rFd27=0xKh<2UR#9}nN!35OH9ap5 zDIn0*u+blw17IjOjSv0Z>)hQrRrDG%<*~`?;`+H^})iUg-qa<57TPRd&|kt$ zNYx-69UW_mmmb=YkhWo~g0nTj2IS({yevXA5UxuDg_M!Q64|Cg^Kg`nD)pYNDh@0; zm+pd3I`2V91W0cM37tGCM{cC~gZaD@Y33`J=;*4yfu?H+1l|_W_Edz3_Mu1}F~(gt zN2H#Blxh>rVy7Rb`zg3JftZl4c*kD53pPCq;*uxMb)tDSLtX(=Vrp?G<`S3hHVE-O z7HwLL;RB#&+{x{0ON{8DUDzBg6!wfn(f65JN>>~fuO0FfpXAtE!lS2BFG-~49|9p& z3;wNJ@BD2rX>)wAtFmGEOL&+yjV<2b~TwckO&O&|;~zmGRn z`p3)(hYJgtm9j44CvtTAK4Kp82`GEF&qmBSnE2xBi)GfYd?I;%TjmoavmM~eg}ud1 z!Klg^aHA)WtN+p;TuY^Fq*IR@FfF;BmNRd5rovkIKyuAV_zQKqtB%RCE%H6M*+KYM z(*{*;eift6GMF(qkxa@xEH%P5_RW__oP2V!6;{*Zw34kh;#jOHcJ2`O6gOYlG0O@O zuF828JY~8Tn6k9Dk0$jda2?;%K>0v@m@-Z3G?ghHcv(5k?kKe#EJ*T;ut=Y1GF*bC zq@@e8>tKn%ym?{m-IcZ>`c%owVV|O5^2DBea74=?3kgyOQRgxm#uGhTsS56klaCI+ z?jT0#lreL$m|rthT+*|l3Z+}|5mn^mAqm_LbJGVXstsa#a(QMP6Zf-5S}Y00jH7lS zQtu#k&kI2B7Y(bq1}b>9x1wgGJ*>`5EkdsKAe0QsVE9-x5buM~oDseaH#5{%`o_4i zwm)0yDZ3{*X&8+}bP$?%K8F=TDVBnXn)1}2C;{1-nZku*Z+;e6@%o^-XQ&D5+&pNo ze4L|OlX*&XlJ_vfGuk^3Q1I@!%lqbq@GX`x`=8O)S8{&PVQxv^+E+;(QCE4d36A1W z5L@B9Sc|l@d!C^e%~Fisvj;VHEo2Dta^%wmRe=r_RbgJ-`ov-Sij~8aq@2@&+C+R| z=pb_iC4ovhza0+4Y_+xUK2dX5q@FF=S^$maJpy3k^kM-GU{){hky8mm%9 z_U`z#Du^C^8fyP?9~-GA6?Q--2=Lj-N-%lJmWfa1v<$-31r?;)DwXf5%qSh-_0<>B z<*WI_8H&L2eP}7B*=ACvbAyS0l;B;iY{`E`FD>VDhU*w+fRWY&kNHMf{17i18v9Dd z37!Mu`jR9x#$uVEU5>AV#Df}6F-S~zi%?dG5U2bP{)O@UcCBmzw~$x9n)-`H774!3 zM9_+K;7t0Z2%8+T?fm>iE(cg@0P zF`(jH-0N5hZwIus3XKnO6vC6+52X-UG3V}9o`Im3ms^-U$ z#MOP7PUkv7Br17|+`0i|HKeAn{h|6j*wPj);`U-ek32%aFJO;n%;ZK*kGD+Bn)st+ zAujgwkn%Xodi1X#MhcJJ2G4R}&@sqv#K|3&FmyT;ugkW%j~s3zWC7vXg;&0?%1Cxi z4`If#L<7}dcU8A;h)89$p@4lS4P;uZ^TG;S5#!o ztyDE6h<858^Jx|j#08v#>`x2u@$e7K%gj_zEt!%Lf+TYyGp3awC?8aoqaxp)7R6J; zMJ2Sjy*uVTN7c8}-p~YF?0kME;BbF^m5%_MlMU)gP+tL=?X7g4c^t%aT!&ai1LoHO zEWGF3&?Yn@#YiVMNGG=J`3VkA*8+JeMrLLa-(nfU?}u9}kuq>N@7Rw%s?fGZ>f%Vq zP5Xb?d+V^O_IBTU(jX-zAYFoVcOxYtA>EzQT~1m+x>TgQ8zw0r-3`)6hjiEU44zf4 z_3ZULd+)Q~bG_HO&L3Vn<`_)JoQ&}scYN>9H$iw(Fpd+O6S~IOA zF@eN zN-pLC(Or;CX`BQd7u1`n`OPA^PK|(uIO7(XJnBnfclJ!T9U~F7^M?S6M03~I&Q~Ae zt|w;!d`V#5OJbii^&g-%As~K#oQ`_&*tBGRMYHLgii~!a8Y|f|-6rn{54V9djj@bM zk{n}hkt=12+fLbck5+J##G|m~Fn)U#s(bbZyo2cmC|e7OS{`Y1T5=ZH6&|P$I)?^->QbUY;IRjZB9^M#DK=KAc^eS zoxI1zTPR1jr_o#Gv0P1U|EWT4+G%6&_OsF}TkL}lex0MY$mjTsa2Zlvm;C-PWDy|C zL3-(k?lMtC*;{%RF6wWxXacO{P^p}^pFZ~cEQ^xuuiiSze}?Oic)Ns6r{8e`Fa+qg z!9X1P2XcL|GhbJ8ry)!%OJDzK3`*?6GK@lE6B)ZC-!+<(8W_Tbd5z~1^~>nM7MyKZ z2XuZyWJ`5Qf`KuTmlFyU|Z|jbl?JO=)JIJ z5=!`s(E?Rl7eM#Nhi&23Ay>FqGgM^cxL zzQcf{IQ7+CS=apKObmWf5kJnzF*3ZJtlJWg3N#JT%6q*qw!*70nTRmf^xAh3>l8w_c*f_ipnw zCTT08x^+L>|cYL8vr_zJ3R z)J|TGGf{I-4H^q7Y_zjEs;c;lS{!1&fQwPH6%@u-@Sh!fQMs5iU-@E*GmzJe7OvnL zMmt_rUpvl*(OB1VI`%RV^|FJ^OwQa7A|tUL!Utz7fN{6`gbYdUQG)5i1mS747|t|c zjVeXOTjirr0k=xJoGNRf?>P15TE$+53C#5rCr!!xvF?SnRV)tDJs zmZwc7iXY7y3IZ-g3RKe71=M&3CEc`CaJ$-^ib%9P!DlEN9{Z2F)|yA^VrOOomEUYp z4EK4mQrlZH-m-aE)6{=_eNZcbYq;r(ZmSaO{TV}=s^OHd6vCGowR?)Wd&ZZB=I(j& zEM<0kZy!!Hq|)E58&Zh*o=D)FZwFJWj3;32ll+8YUz$~_Y?4UwmAfmAoI|p&cHTvl z)^2{r4)VHod&ArFv=5JlKcY26|Y zO$h|wFn$UcTwk_*dC8ZK;UCs_qXz*70p8i&Vu;*Il34@lpDipvn&{X40|bmcXfgO5 zokLd8IodH@5Sm<-8Ats%)rAcSg}A>H4yqigzY{brdL0RrX--OR7Rlxvb_3dh>j&hf zHVAgIM1%TNUWJrFdW^%vR}Uus#ICbUJAMExex)dY!YZsr6wezdRsV#)`^!?KIv`QD zG%O&RxuB=%Dz1eDBX!J?veZl@GM zIt=np|0^VRbc!&4A@cuL1-soTPxHhu5J~!rSWM+hIn=#7> z1b4z4r+I?LGwTI@fUp!RD#obbSPDSKw6tIM_Fq)Capxu8%1 zUXiQ0L5!x}#7I~7Jl5W02!)_qNqxGbW!p36hH=>199P+iERKAk(ScIA2|eqc$s^}C zGO8gm`<~2Zth5D8lA7@$qIxSM%O)qGZZjp1JZ{3dWapnk)pbEGAccMcTqC;Rg3{7@ z1$1yvZz=HX)Zei#`n~Fjq21kb%mQ4v`lz=_CA#v4=e>fv+6AUq$U4P!;@OB@3(Ic1 z;gkBn$WBiS*_}7bv6Xh(nyXdN>>!GUfF~|t*8sr?)Fm9Xwh0Vj*9c1A~?+L5=GY^P-0 zC=x`PdL@b;A) zMl?!4+$}9HV(hA1<3}zU{OGc|hm;%hDai(#o15X+#*0auyz7nHpJrYRly_r2V|mOb z-c957uziD=+ab#Hp-@X1%OzFWf$g_R8z!5qFww()j<-FGSXl(GM#z#=oyLjHxopRv zM4bkK#UT#VFIl&Iy3e+(Ql><{JuPSQMTi&$dO>dl0}kxIqS+2;3@S zbC3!Te?&^nnJz)q-y1k3n(Ac7T$TWk zdmX?>WV8X_cnAj~TFA!TD_=sE-2;@)-bv-L!PgRyg@e z8(;p5z+9l3t4}%wC{}i-e#ZiK9Z&sx9C$>06M7W|JZ`go-T>@7Mmev{6U}|Ao)fUL zb1!``h^}v?b_0=lR#}=O#0#rDXmfi+lU&6nBx@u~yJMMV0x+KNMJ@)wz;pbke}e#E z^<6B$nYvdPumPibxITZ{0?mw?P8ddXsg|rO3yHCfQ;!zYRM*y6Xd2aY$5g6IMZpoX zQZzVB<%W&qw0_(-`^`^U0$M4yiy4EuIZ)zYOS+t_4QRtHZZ%;CylA(aypC}FKwyfLA#5F90rSIU_%k!_ zGum=t6>*a4L}t!Yn{mx{iq}f*b(1X;$8;CFC3P<3k4N503zc5w&_C#KA~?bHM(@re zK56ZliIW@OXt+_S@>L-uZ_FM=-!dDf zzFiKjetViAn=I!m(CgUNL@NK60wAHnp$v|>ZOAKW-=i=4^(3uNK4E+^w6mx6@0#WF z55%T^UW|(d6U}b`6J;f@4HcbUIs>$${uZ#s{DD&zEwj9Atnj*YU&7BFZbbkVbwWPD zL*zBmmBP2GkWg-XvvBV)jxK>o1ljM@PsX^9hX-t^snYZrH$gYf*NzrI7F}ZLg}ze} zS}*ZdioirT(6#7~$Ag*+v?UAhkm3(6GB#&mUYC0p7!k4^jY4d1EfxL%bYH&c2BH{V$C>8)sz*7Etmj!wDDO?39dfsS11wOupW3S^(Xt z8qlf56LN6+DpxPN6cVn-aSU|5vIZx}@;7sw!zy*kKG3jb++>LMlIC%}cgWMUgm~hr zsg=)lv1r(Y!u|mDH!UU<5T}`jOHv9?e$!N`m9~usjp-71QlPo+tHBYH07`>q)hMVG zfUeyI&i9nFi1EePRnGIm(n+L(;aArWN`6HZ0`1f-OVP&@K!1r{#yB2^lEK#z4sH2* zy!Jc?s0nQUDTG$ZERQ9Kr90RcrwmdGxrEC*dWZ4C%wl5dkwj#rBRyd3;_3x=t=NiA_39vPdOKy?Uw=fb3VL%nqR5D1w*1Bk^H zx<7BhPMXV`BkbqU>qs{n%g`vrvi9wZtuE&M>8Ph8T37773<`{;JB4z4%V?|VWQ&|I z2vhI!7Ip7(-BIO&&_fAT&y!2nkm04%u|mOW9+zN}Zg!Q3eW2S=y%2V zUiBPTb&Zq;{(hFsu-_IBPIrw;<;XWkH3X6pxNXUnII)}&?o>@o_6Zbo$DkGl%5ciu zzKF6vnLDr!l8iqvtfS~V6*RbhWydMRf0t_=LYQQeYN)B}_PSRu(76{_-{2T6fQ6Z@ zCZ&{QZx1h=wcgxjug%QWNZVhOq)IFPpY`PbRo%EU!13+A8@}oN0m__;`zcKR{3@1Qeb{BG=1l*T_Yx z>cDJpv})R&y}}*5Y9WX|xXPRc8UZ$cw8ZXZNh#kA$C!&clxBF8gcK$03+oW!UMLSIZ5S!j#~Yn5e0U4FWZgMNAX4+J+vlu+dB zL*VAz2cG(VW8esub2O2Yn*u=7;GDLqRjr7q{__jcKX3fMy?^>PY&(t3NJO91^#~e* znLim*Kzw!jIgRWRYLQd?{hQ9HVQ7;W?0?=dr- z_D5GNM4aIv_TBadFuc4(3bt0LOkRr7mg?$Ht!!L)=wdobJ`?-*CsGG58ywOBf^OZm zE#PW0Xa{D>8q%OhvQSR&Pa9lv>Qe`tcdvRW1*};^)HbXwX=F)05y?G;5pY3Fg)&z} zP{-`;cTmu{uYYYcJ02c{Yz%K8T3}L6|NKe+bP*`&xTg*+By-}wRCb1RI2_P?MI;Zw~%to0y(wtjx}vU8SkEu}!hN0L)wH z4)~IU78tGjG>P!i-o~dx$pm$&ngbhHyexA*PVhz5cK0RTo zyM|uZ*wRK$&1#2!daXp^_8P|*QFf(J+iFT(xmc-ZMUCc}qxccz#W4XaqQJ%dj3NG_ z-od3bmpHh7L)#os^cbII>l)o9gdR@iXFDUx>4BdXeox9tb{(C!bCuO7L|$<-qvHFL zPg}94U?V<>PBX)JdmU_Mdv5bI zbc`pu-1>b?mKrggnNG`O$nKuDimI*@l!X1u%K4^!Fg!b-Qk*Z}iZ9bYER=rNGpcxs zgq_NJaO7FB_I>RQubn1S6&x>(x>bGb@dK3i3o~`hDs-Fmq^~Ec;uX;+z=Z&}7hBFJ zC!1ZWgINP4Cd97@&#(Uz5#973tt{Ya^s9Yv{C~Hk0;6}vyg2{vX-4pyVa_L#WQPy? zz*0aszCf~tSYPvUzyX80xJD3I;>fjv}OY{*ER)h4q4ho){lx9U$Lh0xxm5kFv7lnRqrrOa-{lsi8v`x*kl)8 zYL+r)eiys-&56G{;R%Od?+)9pZs`t(I3g47$71<2*SEzDhat z?u|Et6pFw-($9b*DNuwT^C*%mqEc+|-`^EaT(nq^C?hE9YV#vA|CE8}>G3JrX=1sK^qR`u02Ws?EfvmF8E;|9%eo?}je! zU;nQUUi?ZcEj9irM!DbZBlD1I5?KBD3_VVrgYFvdJ0n^>BMSv9W{$L%V(}> z`$o=v5--q?BWZ0 zHu(f6cj({*Zcty|XzPUN>aOFkXAk8Mv7O)|Sqfq}NY)1B&dld@JX+Ti>S8r9leuvD zn!TrU1Ea->jid$2aLLkGd}&q}DNS8qa*{07>1hfx>xq$>Axtt>#l~F^7^y#v>GS;o z0$XjOroC2+kIl9i+AsVE8(U4OzJB7en#s;O)fV|Go9sJA`(4&0MzAl5P3Crt$o`6% z`=(~7$HG?`d{FFw0$@9U$2j}wlY`(`zpch#8k=Aj@>)ba9mbf$5@F#rSFzgr*=+mV zNe&9Y(D=$aRzdkqO%;$~F_KqBtcK>9+9D^e$U2cQYO&GD99 z|0#eTWe(6?1)z0IR=;a?5p)4fw{sEDKYg2oA0g)q?~iEBcKWW-y3woO5@Efs;zVm- zpAkS7A$D{V3N=o34t~+n?iKWxdPYb|mn3zICq{dS2jm+lG?9~bR4VPnn3oCj(3Zv( zUk2t+`C#*IYo>(c)E7ZnF)Zt$!E#OsQS|l>z8<}qHkgX_!7Ln#44e;Pu;5wE7aBJi zv!frR_q6d+Po`bUzV>d0N)<#Yd@o9d>gieHcT8ave?eD=D|P;q4yGdG1XXG8^fR3% z_FI*(MfDqVz=8NNf=8I=pqC|DbZ`t%tP~umpX<^^ zYw?|NTZ39g_QFh?u{B!NGbNL!7qSPsOt>(ck1^ZsaOB+An-i^P6xYx`jF2hfZl0Bv zu5iBVxOQy=rZ#cW4ngj0owjQ7L-#f4;oB=+@V!rAjuU)oCt+5!ziW83Lu49&Y&-ad z9M<;bJv?llQ%sMlUiQ(o64!|wTWy6HXZt}tZzRh_l+$;J-Rl()A(K-%CXV3mC=@&~j6Fy#8**hyf=WJ{dQ!`jno5@_E|79{`gWy4CJ zp4TL8?`zC6mNsg1I#C<=vhu3I37!?~NA&o9QVGrZPGeMbY3D?|D=%4(!I+s8gFb?GHs?F>*p_#RKSTYt4zz07vY z0YKugL?71|dO~jf%35|8fy8_|_4awwk#2MC2j?@a7q%~j+Zn^ZbDvUKtdv;bTyE%M z96+&Ay;LFG!@<#eY5S@DF;~kYNUoLHuA{cRec>Q>1=9FXb{QFEN0A^uq+`xRokXS! z|8%nbJ+f)e-2sH3R6QIuEmv@h;AswR)px)sXbs#ZP+&#{_s)Y5@Vh)}@`~tAueTzw_s7-qMF< z3e#sjEZ8cQwP8%byp&fT){@r_8AkHcF_@>nXek8kJDZMY*zbAHt;LED042JUH*kk= zIWCVbu-afHI6`I+=OG}!kpNW}Bav$7U*{y#gpNE0OJY&-$lO!0MJ}Ss$~Syb8|#b{ zXk95lY(rj3(6OKmL z(d1Ra;qfrP(`KPf*~PAzT&ej=0+q_-P4ZRp%_Lw_@vqbR|D!s6n3aOXrFQEY3_bIk z=se~nvF(GgQqqKAT<{llPlw^JB|yd0Z&(y|R>unef!#;P7TzEanLCcVle1;x9E)nZ z*PjLksf`a1;mAG1Ux``dvIj91XJ}wFIg1qJ^|H(wvq?q5p>eP$fZTRP@xJp;)Ub+d z7J|2GO3)|cP?8sR07wX1Xj8{mlcD)5>uJ38&+JhvDv`UqZdKno2ll9z$oQ@wgU+L8 za*E}-xWM0cbrejHVm}NpD=d(_v8t)k1d4O#WEX&W{AD3%wAd_7v99X#qoF}gH&c8A z(JyQe3ODb@ie%fB;@4B)&E~gvS70b}fm}wfV5J;a?mOyOp9?R>#Ov7kQ(PGNvV--y z+FHmbHCI%Y2_g&v_R>SXji}^VDXoBfXsz>$c zDygI@`f@#&ZC4%>ixN-CSzb(eMtn{m z@Z#f zmR-2rS>))FepOV(&@AEAO?uR3IJ8E26)IIC0&TiC8m9jq_pGeE&kvwYYnb^G)hG)U zvS!u1ssW(W{;SYtppZY3TH3O}6@8@FU)FmrP*>7ZBR}`;gyTe5B*e&<{{aJ+&Dm@8 z*?9QtyEwqUAt;lU<_z0L_db2H~Zh`@Dksvx1j_TI$NyjWCd>iV=t$0v(&G zbo2)dBHyp`?%;t6aO2&boEH##fS_j(aOpzl&{* z@gqcne*Nb>pW~ka{dw z+JqP*`7qpiDmVv#@CS=z^{935Igqn)9N3n8KSO@fkV;4Sum`p8o4P>OzSUsKUdgGM zoZJUnDkMt_6AYNsp2F#^vH6e@)1)yMxQW<==<7FmkAgC_i`@`xM%DIFt^J7KVl5j& zV0;(e*jm74CApVmSmq^Ah9YV%_~&28DWbnp;5IwdpZ%oh`mt&KD`xKZl}g%iJ7({v z)|UCwP7ba)go8~zGyp3JZRsgh`1Oej{`2V?{MxXKKAEgU?EvbdtoKlY$tiB7x~H_{ zt2rPS9IHoa2iOW8b~uC30zFmbAE5oUlL_ZcA*n9w+Ul_Lh5c6o8Ja3}-8!XCI-Q?W zirVhp!cRHA0A%B8DSE7rnR1lMwS@r53SzOer58^qd93aez@uB*)wk=2WdCY`>h=mQ zt`+`dI7c|$8C!3z(*rN7H*{UiMKt@iXd;#uE@m2cv_RtnWwPGf2UDMz9va=!1y&4u z1*EV+N6I7TcNC!cuR#H{2Y6`kdw^~n9b7YgAX2k4O)`h<%n&WG`QgJvt z%dUYowE@Z`hZ&#RaZ9@ziE7!kxD7O?PMP?ZdY9$=0t+z;p71M+2YQq-rO8}Whe24kw)J+$Rk`1 zlFQ1E>Egq3=S-$eqE&8+miJ7Ac4Opz?bqYNz?x7sNc`GCGQDVZsAdK+`5h@5heZvsD%F9|zdoA5i_%0l>Si zs)vf2}EED?9Cpq{7jPFA3}D29zaa~I31-1on1(D z?opCPIQB=C4trU;9;r8xo=$4yHNjJO!N^m*)4qjlD!|!`{Brj9Kb3Vue*z6gmxJB` zCw^22n#indx&L^EzkNL5fQw%b00a9c?@|1}fByS-$Q6$BZuMIclE*CUwn>|M3~F)k zv9>VA=fRTL;O;mfX5Kg@+_AE63znvATJ26npE@hyADSIkX`awfNR-Qfr8Y*|=#$Dj z6L}6J^-H4N&DjAKvq`eDwmXA#WSQB|D< znoUFMIUD=B2y2@CRr104Oj}H?fASvx=p0=b{MY7rY8v0f|Os03a zW0I&(ba93fG()Lzj(ufrgE^$nE|JbIQ-o?Jo7X6kq}OBD_pUUc;Ax*lO~ANTf3ykst7#J3&VtaNgvHZ zbKTWc*wYb4Sm)DEsa=QA9o(Qq6EiL@;Y6X#Mv#sfRd)W~`XQ86xLltg&8D#$3uZ1& z1MSA?RNhB~-lsv8JZmXIyoAIKX=~1KIX6D#69}P>%+Ec-iUSdqrjZDEd$z0w9ou9- zkG#ezeSAEbWI5R3w=Q#@K+{9*-4PCqbCRZ`?McCmKrpB&YIp|ihztyupmsSLc^ z2P`NOskKG8Ko!ads6ufsT@#kz4n}BkL3NqY#A87D4^LcIi(qf#eSgA$(>wbx zMBQExOe~VaL>Q<=Qc+iS;C!SvZ{gX={>=tQmEA@8W?8M(-9LTopTCBms*6)U6&-*7 z83`xH#KdC-^5{&o7+iU(HxJU|E+6y(HP0diz=*>~A8@If2H#rMR>+0@L%HgH9|%~^1l!(E0@X-1ArUmT~! zAr;j_Ou~q(AtB((IQzn(`PeP!)P`R3N!9prqz6IcfVvZqF${Rz@+%@BOsq_t>9QX$ zm`6}o)+ud18!aD5Tux@)+Z}6QL$fAreOEP(_uh%X4(Dr;BYMP$$i+OKN308xnge7a zSNml6G#xqX%KK~gg7j?53%EN6)jjZy55$#MqQJju{-gqd;0KE?Yms|k@cW~z9;ZK8G!GHkoCd@xt)U{9VS>XC!Na9M zA=wWbe1v<&Vw^xyq3jCR4tNKJojfc^c=4#(Yf%7B*%$&qJ&ei?D{(c`8uJvfjXuwu1#o1Nhd9jZl52KzGo17%+nmu_7v33f%cV@hKf=H`3!`|2S6FL1&Gps_H-o)32E(lMm^gr4`wsmYUmm&WNC z#Fn-#I&l>{kBUZf-b|j>2-n05OQ1F>=#qxu?)<9@fkTu~j}Z9o%wGamHmX+5kh`1a z*tf&8K*t?5OG@#KggiyDQ!1{!KT+N-;Kaj*p$mX)ZHob@lK7zjA|hL$%X*3jq#vz; zK;#P=$*lSTf;fY(AAALrV&dQkvbovcnb5vZCRR0_`#&tKOS<f?Xjey71p-t-DgFHx*(L1lK=kf`la>F$7H86!F1*$YcPS{ z#O;de81rGI=<{kjHb+3Xy(CR)Ug6@-MZH&bFb)>7KMbx{7TU9*&)z0KK$yIxu{P{q zHr8#;D{2#+yJqxg%m~&DVv^#uMN1eM*@8daSw3LDHQqQ|jkM54dKFwZ&Gk->Hh5!a zA6@SC%blav(I89M{fKx{wp1b^tIoxmVll@l?rA-*_WWX04ylg`FHFz55!o?d$RF(B zOOC~&kjt|V8bA4G3#yipcJI z#Z-(<7|-}=70I0h<_tD*c5JGPg??(0$o(WGhFmF4=K;S4e{vvX`hpb0N4KU{(+m=G z8#0L}HoHXskjK9cdUTU_2sG3Kv)h@ctC*~bS0>l7H{@@4%+2_{Hka^9oo$$M|B0GU z_g8BEMMY||A`(-9d+a(B=iqaV7mo(%2P+qysALHvh6q4xBc4%j7^KxF?bN@>=4)5G zPP2aq`|$NSu7F<~khyGY0nX5`8MT;%M+s_=)$rgUR6_j69v57c+vl^f@8Sp#X zuH-L;LO|lsNjAL#pNNmGs{s`5{!GnR4U7Db0QtX_U;eXyGqCFlpX^=mJi1WpC;38O z?W9e}2lDH2=oVsAJ9v_~h{?_%Tl$Ij_!}M3?n!0TR29C~1S-gzrHJl~ef9`g1-D>} z++R7EWn<|7l**Bc8X0m%iZ zPet-pRh;cYJflLKKjr5go(*&FqYu{Ija(_vy0VJkh>}L3!q^c2p6OtE@h|DM5w`dj z0d#&UEJpSi3T0X@9awXPz1V?7{*`6oDBTKOzE7=zXaxwJ0l7{QJ|O#y=2{Xt?wRW0 z`;GfX2b)_!Gohv1KSR(t5`Lv;2;=6u+r6n1xJc1bE&`fH*M zB3g|zN*67R>Vh(oI1_0JOkB_iyaH6mpO0tNa2FU_)viN61kyi*l(K~%(%rMux%_gi zFzg--8WP+0^0WO|x`Hx-^knsns0UjG86W zvqz)z+Fhf}TgM7$$U>s<0pna{J|198mkg=*VwrXE(%f5J7gq$ERDR>>aJ#cLdE>>U z-ow?JbAW9F*+8haJqbt5kbsJ#e0?`V}^mVjSgcnhQ zT4whHS?pCv0^pa;Bf1F)k;YMPFVqd=EaufqIi~Tnbje<%az)zkk3AC~C_H@nK!Ms<`pszr+F(?Nqik_! z&RrxMr=JP>xt|}F&StI~xGKtf1+r6iZsSY-j^TAEeEOAKdnAwZ?txliAdq;H|0}K4 z-|hRK(O@;Ww@lLBWcrf)2W>UPzecRPI1<2p)e;K+PMvlwYp3n}x7prb{HXtNoEo{^ zWg#FE=$a$Dm_LJPyt{{C0kd?+>vljCI4p|aAKiv0SHH#o#`!E(rspK3I`w2o8}(K|%*dM69io;s z3lU(nmr=nMAZY?L9D9vq2S7r9pNn$BxO!yO`fViCc7DQgt=%w5^2xRk<^m*$Y?M`@d1|sJ*70a zQ(hi~>+xMQ`i%1nU5aeVpakRj)pZfC>Dfj(NBQb!;Uoc64zC?{JVag%l7M1=Q$hUo z?*K_$74tjAu%|MFgN%Ke?31NrEKLwSVA00|44Zh=xrq~LEWVR>&OSfy}&P6km}w8MP3plajqe<83_Kx z@5ub#@2K%NzoV!g6uz#}F5&vp#V}A?QXhfKp787(x6)!?+Q<}u%e=gk{bn6x(m%i)_(_O%meGbD%5N(14Q#n?Qvqcb8xPv zpCK|GW;z7phDa6;fZgBn#5#+ zFehu#qKbjRj1I@XVuZYS;ubCiWlW_JwW(+b75KAh$^Iw{>vz1}tMcVzWzO{*Nr=Jv z)tnKGjxw!q^&cP9j{BV$gd5jw@`1iW>caMC1wx1gmFY|jN20Vczy%7{g)_6A)|=Vo z{fwWqF*4AM*GVv!?&x(%7gvU5A+-$}ffdZ{>wKoX2eC-U`L@!xs=tev6$eR41Y>K#_K(QS_W<%H^_;my!yY2%kQ6ObOJ(yU|V`Y$*M-fpkv z-()p|ERxWQK@;useN#L&-?};qS4)qGO?174axbE zk)!Fa6K-xs6omEk1htgGA|F$l8_aLxl$cKAx``hlSIU5}pD*pKthN-KlSR@`CIq^6 z=9pR9k{t}(DU_d*e(`0HHe@zlS4bBt)i((aNz|TvO!6u^3ir)e-i=&csnM)pG1eIl_O6bHC_py(O+o*823}%D zZqt$FsAh9@IHBOSCYrQ`j=|GKVMWg<1<%}B^!4?W=7gmfV%F#T)WK$qt#7;gR4`C6 zP{>cxoJP>|T?F_x!U#4IEfsrWq9t&Vh{`>>GY)1;ro`uVBJ#f~*e3=`;A9WPmQz;{ z7Xp1J6Jqmvl1i5?I0lV|##$d?0TBkD&fbWo5qlL$s@2Gkbci0nFmwgb_Z5slEs}H$ zU_xExJtNJUSM||`iu04*y@5dE2Gv*?R~kjB;n|amittQ?(<9?yoQX#@<$Q!w=eV#R z6MI7p?M0T2FW)o^C*+nilE#B}{(m80{y+KfWVs#WSvp&{1s`4QT2)BjM%-@!p$_oi zd`yl=U;ud6@zZ5R31Hz&Tfk;o!W#PzEZ|AW=4F31sC;%5*SZi+)`0^khNN#_)F@o< zq+K&veXjWCL!^szBmL6fybC_iu=^I-NsSTn_QlyR2Utt_(p%QDStdTz6eW;=MIK@6 zZQTZtL`f!MJ*8Yw$755X?i<0AOONA<1Hr=`TI_iK_R&_to2AyrXQZfq@(TJ^M?I+2XU>-XeK9qjvE{M2OX7`1>RFi5>{1kk10H4jZm)I zh@=EC@=8EfI+o{QPz585Qv>i=|ms(yFxiJ<`S@T&QN5R6OLCy1~-rL08u%Iq~vAK(jSH0s#ml z@L-^h@aSdQuXt`;7{Ln)9+K_HPv@H3_=J5Q_^XDU(?mKDSF{X7))PlU(<7_?k`_XA;ta47zF4w6rx;slqsYz7g~c@tcGjc#gnTH-^4fY#3jU?kktXEnx6jA+DSC zai}WuhSI846oc2yC&0TyzcjTh{Y~s_W42`!^gN+{Pr{-Fo$VsVRkbxG-<; zYVuuxij2PcwMT8*?VG5*5{UqS;r+Sn^u$Kw^3LWWCmq9DY5I(gv%es&-Lu#>Mu35k zNk$o;JZ%Y_td8_eA?$iF{b)|lLRqgj8Nd1kFVHMUD{F!GVVE`xq77Y%k)SG2do@pr zoWI9t^V&dziD|{3W|>+B7qe9n(e!kXYsin`*3m!OBUuSuFxdh zgmrz6ivS9-El|Ok5>Top!GX4D{{YEu6qr?^!4hO8;I2zlD7S>{iK6*Sx`Y?T5a(+f zZdxKC9d4voOBfcmS=)AK_2WR|J&;vOxvw!4NQBtb|G}IF%yRxwTL$K5JiDQFgMd0g z5wZE+uIGQ_&wq8qT3rGEI{OF6S)J`CD=u9@{hheGQBjQl;F^H@HLVi)HLY@q%A$~0 z??6*nn!su~)`GcX&;!;)2L2(2ckdWH07WJ`wbdFz6d{$!LOS|m`m&iPfCevU`0j)Z z2tTC%v?cl|zp&*e2FQPf2LgzN^K4D!wwGhSZKy_&$OXY;>yY|_o&OhmZvj=;mSqiJ z9D=(Cg1fs*@DSWdg1fr}4G>%d1Si4W9YP51?(P=c?dChY_o^zd`c-vxRrUAx_m9p< z25|Sehm5`NSu)pLbEyqH)?5d=OP8B1u4@T>c}{`nAT$#tIdtm>sP^awXm=j`0AT*u zQkRQAKo9&r%RsuYmJgNvxuNv{0BCMq0K6aYT%Ae}bv{2pFPE_+AdybIJ2ncro}DJ@k>?1UxCGX(Q?j7ODsY95T?RGtpg!DEQ9?JpZvM3Fbj&?-wmF-j(Yj#-81p5438Wwy+J*3X$ z#|n}(kZQ%c>Ll+EP(trxXM9yn6!EpI_(Gz`2YI$*{r6W<881-Y?`w07W>3!*+l2Ov zkyV!Wkajh|Hh5XCO1-ZU8Ma2;JxdqY$w(C1bGxq)Ar6Yq?=CV=m_9Db)<6%zenaRh z5Wda{a}Y5&RRCSSs9+TWRU`u+9xKNLfl{*Lfifv2d+ZWnm@}_EoU5tZkEQ?Av_?$V zZ(_r_DC0PMhvXb;+~*iW7#K9uAJ8-!`WrD(IRSqx(Q-D1Xkq3-31dx~k0vq7L z37jb?TYX3KOV5IA=}%mDzHbjmS?T>!(c3oG8k>B$zmIxlnWyNTaXBqU+8-nj3E_|U z>>&JhOKr2l;QT^tRXq?3C{v*OkMjRNdQDXWr}irPqm5puTNEXwNS_ZBkUC;fj&dZ` zx;MW1kb*^aSSMa1CBn1fsj@xhG@mF{KYl>zHbKV`U4#vliBI$dP-bBL6tX3wO<`^b zO&$+j>alV;L`T@d2h`*LYFr|=Nhm1)Ry~b^3b(w*Ea@GVnQ8&49+6=_k@6o7Jgkb5 zlr)2cw_-Th)Y7l^r^ObiaSEqJcv$copG*9%o{K3LJ{VcE}(JngM4-M(0r0hr!B?%O&%L;1yHJK zuG{Bzt%}+Y-Q;~*s_ftWrO@9E52;DN=H14E@UAQs-Y_2rghl$c0p^8&NokhZXgldg ztE41D19)g(nOnQOvK&SBZbzW>VityFNnebS<9OG@+jelj1Ep5TuFNSp0g+)0Ks1tB zfNNC;_!<`#x@(=@VA?NS-0A?_|4GO8>|jp!{%jr3x!Xqh+!EN#IfN`Sf`9*_P%KGg~$mzY?U4rXSM?_m{U&YLpOS{QBU3j7;eY%_pDkF zc=-L@mGCttPz(ah&s*VTpd|h^N%*=D&|^~jn~R&wWrvvR6WB~SNQnL+{J4=UMG36u zBCyi-y*(G4BRk3=);0nSOPR&0cB7|AJg`SyNr7TAioUF zx)UNfS^%E17a8|z+Mj)CvdNZJLeRJ9j(eotwYo%KI8#qd?)6TQVG1GkrC6KjjmnOe zlYSy9fUP8*$Qu_B{M@)eM>wgTeh8L|NBej-q-jWD#|DE7Rr0xk(NwLW{+RPi=D?*x z-*F-0$e_{<2h%F;Nn6h1rE34u-;sz1KTNDqO?po>^piH~1+NjH3eMQVw-VnmhC<`e%isXutlay);S zXas-u+kE(`YAi01-in8k9se!;Fyo8&e8@ngmyrgft(|O;> z?l9DV-dg*ZI5YEl4+TCm$AzD@?!z*SW=+qVN~@{6$OQBT1Ia>~b!a~r&1(j|BR@k|0Ju4R!E+Ze=DaErO z$n9-)^B&?H#Z9)+aeKpp?B}v>BRqFc_njcX`x$t$s;Ozbl;M*)!e(hNH%giRfp1Gn zczXKY?VHE@Gj7bq9UNR-UUnHs_PB-hvh}HIi{z>b+C^QU0weynpx3{= zoWvh8}18?SYal3r0z-d-vYVngq`=|vdd=eKxI4`0e z?187tsAzDk(zYbKVX7F1zTrSqiuLRnyuz{lSrO`(FL!=%>-VDJTRcvHpbEflUHRZX z!24x_fv5OaqA2K9@*biiUb@>F8`lKNR~w;sg7Pm=EQh?Gxk>3vRp0S2*p@NRD8vzg z#mJCIQs_dx8o}7MZA&O8I6;Qi;vKQg^ik(LUFY4oTN|jEB!M7jbuRnCym>i_I?5$V z6JhhXSdrlqwW#mcKCO;Gshkb)<$o>m=~J}|ei#Nr1HKlB0y0pq4tgE z5d!^!=S5JmLKFK=H-T@z!Gfh?7h$p1@dXSX1wQ#vf4=k24`05M3`L?;ojdVD+We~< zhLp%Lg}0?Bo>PIpfAn9}M)giGk!gI$3BVpi40K<%fu5hlG;u(1xHMLYceYQ zC4nN@Rlhk&xBDhVI3)>(+w>OaoIR>8RB|JF)I_Y!bjy;#>hA`NA{R(r=3f|^Jmo%8 z-dP#ot;Q@3ED09%d14vgb(i&nIo{+Gt6^^^@|A!yyvS~@{OJu6538g*n{&|%#P|Jm z*C$j$Eh-0XO)B@;UkOE57DRsUB2P-aKS;ob;@NQ{2C5`w^}=QQM}n}SYibu+`IbsK z6R~u367=pL(ZD;bPQ z*B)|7lcX-G)kk(iM&EcJ)}ndvhL;5S)dZO+3zn30pC`vmHM8e04>}rBB$y6Xc{Q zl*4x3qY+=;L&xO#LfgEoWsdK&Qt;YrsLSHva;VpGS>IF(3_AK*_m$HTa+o0B4! z)Y}Q(DV5lW}Kb#Cxn7WKK+-SPsWx~I{+*+1ujdSR=w``{GY371ejb@z* zUnk!4J7H++cZW9!g*%(3U`ez809TH`v0i^(5?qX?C1-2*e97LB7Ru&eIZ_Ib*i$uD zbFOdJ4ZRW%O$v#Su#%5x#W@pc_mDG;CO$W|%Ooj*0s%8KV%8Trw%ZP0c##@vIt(X~ zJIseNeqWS6xTAo9^#e4f|C0o(r+nL~=j$I{!6~R3vG$WyT0!cB5YhAqGi~v^L*??J z%BD}htgU3@pxfN&+NF%oc8q-Ih+)UO&a-hl0!LG)G503O@C3cFzCPik#D=;y5{tk8 zMk!tq*8AwC#}rlkiP+_(m%-jEGDmAuJl1)!rflfA{sX=&<%s@ z0o^;AUz&7?0tjleIKPIJZbsPTK=MA36wCW4xpT~eH&-8*ntomSUaCG}UoKQDRUpZj z36}f7ps9X6)ig@m=kj&>^OYIxwUsUXjk2Scj%W76LNz8lV>DAdqe@sXYD&JK?=Xm# zP)qCiK=0&Mv&0(I>TF&kc&Mdi0R6tU;&495Tl4biMfbJN+UtTfVeE(aVl_tSmrKt{ zIFj(X07b+E`Y~0^M{=ny8PH&moj)x(KCVRIuO*V`i+vUkGC)<7-WP$pOl>_!1PbzB zRDb}b)ByGRD(s={zNoI0jfM#aOU2RwUJ>;Wm_G@LI7`4UMPpC?HUxaaLsF3Mj6hXe zfeh`7ZKSMeLxBNt?{!lYt1V9(UQ;vOGw+KgOig@!m7U(PkSTM1V=Ur;BWI$Y(V+;H zpT~en7pNoW3;GHPw|<^;3T$|WPR8Bw4?r&xdtj&Ooe}oI!mUAWK!(svwCGvZIvARU z>oft$nhAjzHTvE=o&oKpO$osJEd^mdqxkj}glC$n2#Xr#O}((=Sd&xx-kGQcdOBYT zwbAeD{TjXJw=a}mCf{;e`Z(t;403!55pvLRhkaIMLSumjwHcV!pq)_|{hD|Zl zx6adHtjVT@Mo6p3{HmLJOamD`WjcKC=gbbILQ%ljlsq4+;m6cS;TJ8=u*ddwihcHV zut;OZFBvwjYOziFQAgvun&Qh1t@(&580h;m$2I{CDa|afWXjR)DUkb)Y-b{FJ(pPM zhRWfiU3Zz|h82XORrcXCA|)Jex;BInX3yBYnW)P++1tMUVC=JWa61B{gL;Etk#R8z zC=gFYn3&&y$0rpYxL)`y*A#FPziyX)H#EUaS{qdn|8;nL`ZyEuT-9!%sw4Ij46!)v z1zhqL(|K4}nuc<{9FGbnoK98-?+3BW&k@Z9yd<8}q4E**X|J#cW*1|e&D0S)gbi?3 z)B6;0UPLy$hHF?~Dv-A};wUM~T8vOrxvC74V$!(|iALfPIH%?%vhUQ4tNPsFS;n`o z9($}k%#>^xERU$u*zAiBx2T`+M4HmRr)~Sw9-Qny5HS5p!KK-^Z*D~SL}WH}WKC9> z-)o?{0-?FAp5|(6 z&A>opHIW%L?=bu)`rcArDF44MoY7+A=Lb$7g|HPV|1RL6#7H2$zD?1 zj^G1)5zd?+MoG;Yyp87D=1mF!+5u9kK?ES-L0Z1pB>@MW&#z-u@X2q&i_X0W)uEn2 zal6Q7mnIsU!otQt|#aT zJx>q|?Oyb+Ac-k%t#Qi$``$`{k%6pj!-E0JraI-Fu_HVrZ1yUXq&rEiC z&k({k)^$k@u+P?mIXy}5l1yD9;xBz)PAcQsrx)!W$y}BJ=5d5X8W@ zHj1Z?N9Nw+4=uTft@HGsWGBR^U;h(RQz@{I1jq*GHUacg{mjK3A+H0$+$NmJfpPg|pE92PZ&Q zl{wXXnRu2g6>k_xt+4p=giA)5SB#BEa9=VXn6-gp!d$hhk$893^nDP1Hr)A)*kila z!zB|bdzAT8&=`$6O->L+L}~1)gzbl`aHd(-A?~MJHRn4_q<0E)IF!r$(&;)0HwrH{ zkVuB|e}HT(@PRB;Llb}ie+8xo#f4Al_DQZTffI=u0p#qvt}{ArTcUz$5Q}V4_Y$f) z5scE7M&nTno?4ooat^wQuW1Bd1W9inpC=ZKZq*RFJUF;)pI|}kXqWwE9Cc~+LcH{n zSTk|`*LxZ4jDjk`%K+JUs*@0vNa4|~wQ4Ki_$T2`Xxf3!zU7NdScbwI5*GbQ={9Vo zlZPh5?)!>g5-oPUrHIyceB_&OAMIjbs;Tfrm+eEWFQ*ysw7z)6||-YgJUcmpsOB*4&J%l{eWQP2Mu zm*MqlLKhdu-AzFlr|hXn>jgr&xxWZq|7d zy%vZOiJnV(9&#CV?pM|NLDfzn>uHUFwae{L$EziCvkhBtptMXsy$o+uf@vwMX@j%^!_dKEc<9_l~jNDPQ~gIBW_$=G9_zhoCC7{FWXl= znAhPt9wY`HBXANDChcXrRh4AAEG}_<@F#p+2TkRopr{X~)S)5GN}mCxvSqTA0F7X_ z@}**zcjFV@#5+*0L;K#K@7jd!a|{sq;o*$MQHk=3)-kZ4l9PwZOT7vm7bPgkHaO&> zL3g!UZ1BGzk8EKDG>A0>1a!a-q%y4)pu!_5v{NsO^1$nxynaMMjX1t z+Y{nQJ}K6)gQ@U~_VQ{RfsHT-_xYyc754+g^w|4#QDE+jd{OMmf@79V7+r}?;j!Xt z$pAEm`E=jc&-?5+j=-GZy>*6mGUg#mjd|OaE)^Y_0%)>>vY{aoc%TY6c5*@$E*!`K zA%odWq-$&NsB2Lt(Bifs+Q>E6eq}jwS;lih@(uB>DaqzLXA;w^hWWRhsdu&{EA->V z!W)zYfPCJsjb$7V5yqc`i&tcrY{iQ$@DTI9k~%IG{{R_w0(zmYKxZu$U@Ek+6k%O2 z1>T%p0L^QDwqTCdS#+P_$ty67@by$67DU=Z6z=`Q8=n;wpgq@&?m(o08VaA93UD=# ze*GW$7wQuK%q563RzyhEWDenWWv!}ns$4NHXFlk=(Dd}l?4z)(itgU3P^YI|$ru3uND)_6Q&ys+Li7&C>gv&tf)Jc-fn-~nA zofn>{j@KsHRpl{ELX)o4N%sDQxB=l$`-CBSH-N#t2Ml^u;l=d+-Hxohrb5{lRK-B4 z?{5>Z{*kqR%f#M4l~jS;@(-S;j*;J~`7Iil`JCdOFh2wU)<%YL-{#MavA;X6!G_U} z+x!WGmd4tQUbGDQe$sq{MSKNEZB<2B_G_EDtra;hdq+1MUb5#O^PiNpBNh6)t;d?9 zz9&x@nOoT7zCsKBCRxcB#o!OGrzXnqBpfqiVhR|QF4ip@*|+7Ho9>yCop%G{MQIOo0F4@)MIMqv8SNw`>ebE3t0v|m z%os-+P|zeV1udU<*9WQ7tcR})c%bh-ciFJ(gnXA)kvpQ$Dlh`gMRJNc2}J#Zz==zg zyiO3sz;#uV*i4E9VW*h|mR%TY7*Rck@WofzEF%{HYEZ4K+o2a+?uOGkD#66xmRwF- zL2&&*_#}v{UN6Jp!^eM38q&uSzkM1rO}Zk@`>H)WN_#MLO^f5s+$zVdBQ8bK(CG@k zE$X&svB3aU%znWo`*`bp{yfkO7i4XySQ|sCW~Rp26Ye)+!sf$fsd7gJ$R-d!>M8)T z326ASx{S3=o0Ma(<(erJb3cQPe3(FHjzOUC1Ypo&jcW2`Cr6opB`&$@Y@=Dkc#t}n zbkr0cPB4gtcRTIqd&*Dp69BsZ*h2U2v4svOtKVA$z#2~#Z0!x5EFO*_*}IRoafuoA z01BYlzW9DU-4l_SPHTXsgYB=96=8rJg|=Cal4^wkEFzK7-N_%)6aI*{0$@cZL4EFw zYiA~^l;q%(ZpcbZ?Q}x!hGf-xOR~hCFbYx8VvTsk+5LyN+@2=K{f3E7il%W)p;U%2( zePPG8K(sxV&g?96kn^R^lcQGBtGpKzmoD31E(r7#p=*3M{la7YMNLzx9Cvz$;l|x_ zfA%O<S+*9Nla~!gtPFBz_>2u}#UVD)DEK+bf+6LMm zTlWJLb>)3`*=x|o)PjD81%bWuG z_%V}GMMTPY)4QtQg*Vs%9)vESM=`rM>g=>ojOXz#xhM|^`YjcKWYG?g+&hOT`q>Vv z+Hw@>?Du=71ot;T*$GwX6UU||Z>4FmxWEF9WI?9=PX1Ima_dm<0J|Cnsu6NL`sEaT zs+G_O2$#^Jtv7(=dQBY|n){JAk_7x8gr=6S(U$Ke90E@$`OU91QQ9u~Xel2~d|2T?4Auf{4bJ_&cox|_84V^jQ3kU8mJ z&1f&f2M*BFgxq%^k8r^cZzyc5LjppFSk=GFqW=*e^+(tIf8n=we&@IT)@EgnK;m?& zG*9T)%mlCx+)H5~Re2M?Z&=H0YDt#Mt*92Ed_o{&M8aU<7>>GT!{>A%7-nsqRn35I zl)mbFX2ip^tn!saG%5$g#m{StZ#p4c+qIC;<4Ewd1K@Z)xSbR4It6xRm3j~YCH*ls zi+g2yj2wJj#~NVz$;Dpe2mAc}fb%;GfaW8>0a2nT=M=p#KVNQemhePM)Gsc%Z{l9( zv)LKEtur2mLEGCL{tW6FVAAD5PUpl_9ZnsqI0Z~F+czV1Xv0inuoHmN3-oL!^CRZf z1q&bfMOnsEph3LdCcS{ld0m%sfHNu&%;=bSW=Q^8Q~T4GjZZ-c@7$K8g8^K2;V*U z%qN%l04B>0xEYm4H)D>TJP16`(dj@k@mu2wPA7;4FDJJM!>eEdq@*=BQKz^&TNy27 zH`W#0DN0n1$9u7>rL@Oa`gs~d`zEIAr0Yby0!QLi2QOj$f}MRj4;I9@lBT*V`=GN? zhE?;;Yt?lAfG~SwkgqHg&+u{b;!i4%e;?j~x3S5rs`Csh$nuBpdab2Pmw!QVOivHS zL`AAwJi&=pc+H#zWXnZ1(V-w9(+TKq=K;uC2skm3Nq1I0_i7}^AFoXTs3ssx`s>l< z%%dFO9Avno2%hrwaJvj*&ll1$9Wx3DPZH|!5{FynE@6~CS(vRm+#y8FEvbyF#CsSI ztkDoMw;>T@I_U%5uCU{)_GDTN2?Hi3_6)x5tB4H!5pPIePKLwG<|*y9In`u*Msiv* zE>XhePeqq|rNi`~H=Z=q<#2f5)(F)QHRl^O5s?Z(aXq4ZG1?ayS7BqyAdcR zHN$i&5s2t`J^tgDJ_=KXGenje55kj=X~tx1xX#8pa@pYZl2y@8+ zCx4vH^b;+-0{XUY3Mb$Lw~9Y1yn_o^=eJKb-zpq;^>+}&XOGAc2R2KqO9YW>_3{Gk z3H+Wq^OiF>mU6*)Aq}XQL2xHni^5>R3~&?Ri?RqR-g2*`5q@iT4p8RU(9cZ}8}LDS zcZ^*Fc%Hw^BZesitTPMs33E*TtGS0Hysz+2s2)~%bZuU>(#3v-?Y&jc&2YPlk=qul zkVnd;MStV5p?7S@#v-M!x^;X}(=pZ@w}9m^Q~~>{q6rE2HG4(@scFvZ%1RxYSJ0KR zhg&ifafE46j=pdra3H5oKCd(TIRJd~pPDROLi>*mF!QC|BbY~hB3HaS&qj8pW-8|K zR1_5H5!sriF?nIF@uEsDbLvG7xmtKf=b^D-UncVDNx0YEWTJFMiY$Slh{Q+5bY*^K zs9MqC{XtRg_fGR6E9uYc&oUL5XmJkJjNjzjP8Ve5V~;CNaw6_uTM6|-YE^cJ1(=!> z=~-xVgE`^Y8vP7VaS(A0GsB>-cO{Bd%k_B$IIY)7m!7az%~w>{z~x#>sJ+Je(;EFt6A< zgdnp%(*fO0JI6LSp%!z=2tAH#hUX+ZBW%s)Enk%L$Wu4Y#LmDqa1UNxB=?jmThig= zgRc~|-d(zLxqE)wXkA=9liuaO6cbQ^@O&<^jnNtAisFT7!xHepAWM1PCWsf8ARN@%|I$L&ciH z9em!SX8oq2*-7w)yqBM_;4R>VzM8?Emv~Kp_GsC)rv8ABqX-+1t?@HCjpX;JDdgn8 zxGXyh%@^1qd-~xtOYf=VTZ}h?GUwQi9H468X*Mhst^*oB!-ekz*$#O(YiQ9-=;`sX zJyIW*$FkqtpaQ(XX*{1xkJ?d+09I(0bvoIM0Yw;3iX`$n8OJSHleRrf;vXO)H61zW zBOA^;_ba@OX2p43zzjyYd4>~A2T?@vYZPq6#rhCrYG^64@dv8){F8* z=npN8Sb8ikj_L!}BbxPG*HgC|aV28#iHtSTr1A@EJ)B%dN#m@>3JcxCo1+`%+o+=v zwp&1ks2Kgo;br#d>?O$qU*xMxQ+lj6!dHx?l=;upw#~O`QJMt1V z#Ah$I@N^EdWud6>Azn$#d&rnL#CoR7i=K+u=B$^VUHr0}CdB44R(!LHi%sj}k)ndy z{&nbd!?<;6sbPKG5Ju)40np0Ho=Ti;YMympkl@f0px4GcL)Yu8PVsqYZ6lys$d zMno8Po`%%9p5s2{#R9eJG7A;zXHT~zW2A?;8m#*#&dCcdig0SVE|oa!o)M-vvNyOG z?g65W=S1ngif{xa`MY0m-gTf`;7+@`N=~_#xQOAn#`TG1q5BKzLcE*t+{To-4qQWQ zS~QX2&@#4^o{-W*A_D^N}FOB-luD*EysxB-ok3|Y|1J@&ewrA~QsW5XEJ5qv$(=aH{rXdqx9cZ`g1 znya?yy+2UJ+4uL^Axp!qRuqWBqKTlli7xcjyv_(f8ht2#89`ypZ-)0cu8e4wxIUQJ&#oj4m(4%mx5nVVxU zQ>rth=;>3~zShX587cu1+FzMpd6a?Gt`RN?Cyec--2kahe@8(@1b=xx`TfI_#@2_2 zYM_R7?qg#?a{lL1`_v*9#IX6a<7>S*5JSR z4mY)2nGXpmbp-lcU1=J#r=bByLvjkn!4y`otUOwT@XD0*0ld`dYmEM(4%6Dc{q{lh;v+)^mw#+E3-(LgNjju~~d+Ol*@m5`CjFXJ) zO~veuy>AijWkh$P-#BdqAeCw|wX9Wj_BKTaVyhwMYH8pHh;=`r&;Fc95!TbK(tI`M z;OR&VE8=EBJv~WcJ&vl?Mmho!^GlCu6iL`%3awU9xO7#yM+A6lN)NtQYY!TuU5uw8*d^ zeeiMXH~JPfx5F~$hLsqPoUmwx3dad=fJ3sf-oZ|C>kLE(VjdNZT1f#qYN{($kPcpf z$|2C&^W6<8*4c(k4hjPg@;X6g2klby(1c<1Pa%4T-*ow+hX=3mifz8{>mLCV7k+sR zBmfr4?KUcSSe-K7hBB;wlbkZ_k{Vji^pMu4-A@Y1y)8I{&0ehA{b29#+r+DMGsTta6&-^=DHTz+YjDl;J9`TSNu(> znZ95dm>>k6ZiS91>kqb^ORYqX0u0lk(7_PK!lv(IqNTQIpp@745H*u6L$ZP>@l9j= zeFb|96BXsWFI^M3?LI{@6`$a%O(qg2`J}n~go5$hf^KD)N-h#7x?JIHQj2`P`nRR-(f8_c z6ATs#cpBj0QeadOE>`2QvSaJmZ%Jaw%(uLCQh~ebtq6lf6YaB_Q`LI5@v@4;;J;$tC)XdSUMc z=XmITs|c;xFwrC2TvJ8L4h?2_Nf*Q_Kft3(w@nU9|VaajSgb;VuhZR_ZaiS7MKg4 zqE8F&{}MAf%{jKw>uR!Phr0?ef=k7Z9>x!a(JUCzP48ZoFkGIBm^7)Yy>);_XA&ir zRE_%P%LP;&wEu&eDFllk?JoxBzs5TG9sS{-sJZ=5egD6vga#7*0a8G`Pfidf+I`|n zB1{SaE(7o*5n>7KL7#8VSsn{M%dOxRlH)Y9r8<(UqhHn-|1E3O_te_LCEX8qfQ1@? zlb3LO^V2Vp0m?B;5&J-l?+pYI=RjddcN(~!`?u>yf#s>6md8f_f3iIG)24%*W(KKX ze%TiAZ+kEG_x9{@@lP8x0w?z$H*_lMcN;o3=ujKih;y<2n@q82&#QbWZGnC}Ojp zjm%%{$R8NypDiz7n13-8zZqtL?f)0A0dlI=;QYO%{+)UI-_`%!tDing|NGhaIi~qH z?gsnso%{Q44`Ewj@B>h?+kq5D_UY*@1=6rLdzM9|{NHeCT}v#k&`tZ}+nJ;cmmh!C2q=@jF`sizlq?q%5SsH>3gr%#!9-PR0(*l2-ao#?OrnZHBOac~I<{q{z;RBOe4n|CZ|&3E)$(kMJYk1f&sxqU$)#Rcl~4pNL@MA?aD zW-b)joZIrbw6wI@3lSdgV1p4DkI&hsGE!d-?Y^wITOmo~8;|#A)`%2-%+|7pgZc2p zc}Vd>v(BsiWUZW>pDo%Hvt%F!UP)1lZ1af{=l6D(<5l zl~!Haw_PljM%v@bKeDdfi}?1(P;auYj%FecjfyNsBFRNr=qa%K#d^D5?bS9!ytmwE znwhud?n+APHrbapm18`eeHBo$H?oSCvP(oTWMKC6tNeB$`+ylEm`8{W5CvfOT49bi zG|2mdon!rV=YWk9x3zIHwsCSK{be_mnN{8GjF}bnO^unAjU8>B9Sn^ffvXf9YzEo|aW|m|leLN{;At7c> z1p^CX!^c%~Yg1sI?bp|V6-9jq;J-o2`O7=xjg8Fp#cbVlSb!fnc{xdWH~_VEp+6ry z7x40bdho2Q-0VM{d`n`#@;V<{(3SfW#&-X3n=ciH81SmBD!le6RlSlkvd2W-CU2j0 z&PTls!Q`*Z5t*cY5?nI1oZ($lGL(Uyil-+mmU*o;Bn1l{^bX{VHoq{8` zM0`9nb~G47oUHyapljr`OVQnM$K8;o`I+_-T0HmjVZzVHu$J!c)Ry!FZOgwA=5Hda zx0ooiy;b3^qm*S-B!6+W*xvwgzsF68bh%Nnv;-LL` zb;o5k)U(UY=A$ByxjqtoD}{WhQYH6`gV!Va<#XX(h_#z578jlzT%oPg&ZG?AN;}Wj zG~O~`@YY{Li{^;Fa9sO{(V5YJdwP8vvXtD*K{yt!6eh_+jR0M^al#yr8`O|_lPap2 z*Kzb;Z%{baq(&{B6bnqa_X3~tVkImlc%~12^&~Qp*evZH-Y;_G^q;ecWY3hM+Q?tw zF(nAd4}O}(A?Hw5yhwZY`i2*sbKc_Jb60dvga+m;3#a_CJc)1I0%xz=uHIIy_VUJs z%xS-SQAK(XXc6!tM~yw9LMV!%it$V*Fioi8$mhTDUBh0 z1Out5%rTP(?Qf;g-?xwB+H|X%r%rZF}q7B_4D$YD>GtdZ9uP4$V-t+451M2O{H;HtMtB9vV-I z?~-hyCb@+sdiBkzuN=K)sO!SKyrFC)G>(}faa(=%OhF-7cFsygv#`Z?^4vq1QCGd^ z3OG8rH{VrSXl{f(M|q>3{~+=%f$~D5^1I`it@s|+V*06?HV~BXG!xh9Q{ArAMhlfa z)^@@5Qs={p;BlbW(W&A2=SVF5{jkM+PxJ+e5?ZcsaOt@X6#Spe>aLWJWynlMupi3$pC@t|v5f;WhULum26jy%IzKw$hhUfgw3dI-{ zv95OJ*20ne$Mm6qL>SCnq-fvfg&(8M|RkJ zsmgmLHAFf5)VLavGWFGGSyZ?Nmi4@q09^&Lkh#BwuZjvsJ#cmD>J{>i$gW6szL?SF7+#b==$m17TYk&kU~LNOd-^P)c6oa$nEm7;a3W-QS#eR;qRUykLKurFSkpeJIrp`>fP25{e`_kg;~I<079`#t##*7?srP}v$JBrY{c z$%yTrv$cye z7{4yJ8w@rRY&U5MIMhX8AAN|&GI!~ryi#_gX#mF4poy=qG*AV-r(tq{P-H3eOno`Z z!(xbm$tt(TE3*2&v3nOQLR@cPEy#A%tJ-aFG{E+=n|&bHTP^qx&6yevYQe+Hp$uh;$#rh>(d)uHDo z=(VM#^BtB#GpCyVaD;a?gh0FjRtU}*GeewFT&UQ6wg0ZT*(;@GvPSX)0je^_b{Qyq z+f~3rAG~V+tPDRo*ZDMjH$MOZkHnS1Lthsy>*6@#(_35t7#7G@L;Kr`r8D?sg706Z z6)&<4c_SAsbipLCQ}D+7cB{y{Xp?vc({V>}56l-@JvIp~^60~X&8oSy83-JGwI|;> z<=3)%Mm8QkD%@3j5DJ~W$P8%?Gg*5gUpvc@{2=hsZir9NEbYfj$#q&G;{w!PU5vxB z3R}Npf9&w0byX+@fld0DFf94!>HUNpO>B)R^O2V666_OhrX>3UrS7a!hR0a`UfrYY zJ03F-3L=K$!6&6J#&{cXPaqpV(TscD&S!#NNx27k>pnlR(i)iDmy^WVoF~ax@!kn| zoy~TuNAK|6*h7{(mU`bIiR8P~*E`G|smLI~WLq}@%rkHy(tZj{wL7Do6J}0j%ljs1 z-2K-NousyvJUSA*9^r{PZg<8HT*Usi-#i!c*#|ZDbBgJGBYB9+z}H%vHOq^Kel;f0 zg!E#k44p$LdpymN8a{Wp#`o?B>bvQf7YF<6>c`E}FmFv`=3?A)og+g9MECY&qs~!9 zyZ664*S_>K{G1GqO8<-(VKizJ(A>>s5CV=gE-|u0f1kbX#bvyYMNmbUAsLdEx$ebe zydUt&FkusU%W!+X~SxbISS$UWxk;ywaoL|DWoW*dFtS|2#q9VB`MDE4BQ^ zD_yaANl%^nY%}`me}oWYHR9(_1D=Zs#+eB&`KAnSN+cH}M5n}oL!(%K=eOtMF-|#P zGxQbV-CSeym5<-6wjnD>b4r}$-pR{(makl7Cts!%`WD>AhuJhr`5p33TP0T}qaI1s zv2ys!O14Ae5r|G@SLhOpk{42N==x@&8)Fd6w~fHl;Ui<}nL#H7bcq=o7F1T)&1!~P zA*pf&(Gfx=Mttg#lrqjLsvNbS-3hhgP~}RdBScP&a1kUNZ#VksPH=G%`LUxs`Bu+? z8%Y`)7FAZ*&&~{5CAZ)g&z>`omZr{*%#@i|U6ra#J9AREugmK`e{t2Aq&r73{t8h- zeOjis9$rR0QMQLj*Tgw3bwJeg@dpMY6C5gb#Ehhzfq~~HCI)QmCrL?t15QRJd{pej z8A+uB;iT;39|z!t*va~fXPNaUZ?vtS6~8vP-shtg#(j3PuZ)0SltxpT{PJZNB42DV z72~~7tvAam{n3bv{&eMwFrS&qt#QM=w}+_&*Zc>wyYaJyIs1q2cH0Dbz3;NR8z=Q^ zZ5HLfAqS#X*_QCX|Is3hz{%8PT6Xs4GRE~=Zk*Rx<}r)aU0W4pU1ztOCKiO?zK8ZsrlPIe*j!0>I@ z>*HGa?*lx}msBZ65+tAGd?e)>-6HE+nOhj{O5+8dQ_vAm=@T59y;OlWOP4yK@>Ff4 z*U%`>bGj(yoaDEvv#ZuO51&&4OI;4ZY;_lTVRZ7|@jdZrqtNxv<24#xK2M_`;`;Q! zpQrp~F1Bf?dzz6&EV*kH2NqK=rMlOI;4`HOcd?OGPE5go&Bx|%Lhd=SeEJQa`v-Y) zVoJgbiMJTCm&@-7atUjVQdA?KB`>~EBjDYO{(Q~p$Ym!Tv!nridHbn40Y$_iM|+vX#Dj_)edCIY+Z?$0>0s0Nlpd`_Lk~( zDr)MDjh`h5ztC0*yl|ABD&JDWG@=~JPg)w%(88bkVW-ENh*DhogKg*f$JW<9t9FKW zuVclS^#Z@6^Yz-e2H)JSPk&sacqevob4V$B28HPQ?T}0N=BAx-JLQZd)z*bqq~x_< zr5Qqw>*kFK<&6K$tKzA`qtQmwPkvi3!mS9$V>{M|@7+ zhbIafP#*Q`Ly6zU*%((puL@*Rt)C+g$K*0yaFVJDU*y`@iDwT5F&XY-&p@{y=HzG`VJ)oH#WR6p%a?NlwWSs(BfVDl=UT#qYUMqblMp1W_N6aabNX; z=*qMts>BCWu^+PZ2absMKRTjcZ2kXONAw%e_V*!5ZXULu{7`)SE62|)SV2cO*bUYE zS^uZGFAs-*tVi>)SuW={fiEIdt9T$F{&g*xtML9-_UKfvv zc<8l%m#Y)pq}=*;(YI^E#r=s0_q_B**^k3Zx@k{kwL~mqvo%FO4qNJ`9TWwAGbpq+ z$gno3wl;W$=_W(x*uBM!t!k8iEV6+}OUicWJOGHnG>i`>j2vM~iP?V4Zwz zK?U2l$E>HTmTwdmabEh~a3+a|zBJVA%K1j6;H&M!1p-VX{^L<%U!?sA7kW0~+M3*j z!|*YD+OSiD`MabaC2-0LOUu5|YpQ4U^sp>G5TG47S*WUh4ZhEbHL~jh8dltP&j{l* z)ARkQQj>!`ihX1Iuz^qgun@Oyvv=%HsK`jPRW3mp_?u%sf~s?$3^gBo?ql)g{4_gp z^MZs2pF*UMi2Ks$D6vt ztTJ35;ms@@$sT#-K_N+}w{nb1De)A}yd8Orex_5fDG@HwJRj=FQjKbS^7($lfScmY zx?USjSM_^Q6+L3au#7|_Q~2Q+QD#l*C~lxh`J|L+wcmZuZI-J z-UU<$NADlY+QigTnyk640##k}#3NDF9C1G6qUJ>Kzg|xX=8**t-7z-WY+e?Bx9C$cH1K zD5}t}yl(54Zt-JUvpr^NHn2!4roVO3W%+ z>>AH1Rci_V7(Z$i;nY@iJoDmAVf(#z1KXp|C-OB_+;-?VfHB}Mz5X~>&^=GNn$P~@ zT^&Jn2kkSe27AJ8W+m=?=o-+-(z!M4PFcJ_V0ucj#(|Jg8-D?TQ>F(Wopbdi=(`5d zoAw`IGBLT7_i9JlIoEXhll=z0My7SFH7{E=V#2&|(m{<-z2K0$A2l^a~Qjty&R+Bg*kpMIbHFI2$Cmyvd+oBH3 zJGNElTyFi@@`XY=#!Vs>T~UIyhpWxPIs0t2BOi;J)9XC0jNQqtv9QCtXzDZ*A~28r zjji@!-U(UZz-(IvuKV|M$20GTNE+Z#FUSlH$H7D%CDX{v^mm0G}Ke)1fbcc3r?ux7H{;)(`+7 zEw);j0)S@_2*BWEN{Yqk4UNFi<&;}qMz^Rj?|2$vJ=Au{q~AkS==iiR(h6UyoWt2UXTe|v?PGu~}S8rzMqkDQ=J!g?lRhZMw zr!3)v)-$f%er5^$mMz^ifl{$TI@!@(&GC1$udz(mYZuHZcwx%TP|Yl%Z#5>*&QHFk zM@Z}qJvVRS6Rmw#Qt7h&o#`{`k)2!K&3&4hdTrNevQ$(G{MGOB2~unAY0pGfLX)KO z(cW9`*Csy9c)7mrpX}<@bLvpAcNf(dgD3Sg6@EL>Co3s$oU?Gx?=Xj#Nm|y)EYXR$ znd+P0Tf6F>e#kmyG?GxH?GYb%fGA@X*D;KTFno!Mr_--TLPcGnX>kbdTtB3fGz_nB zaNpLz)=tUEV?UYIj~1sD?!}qqqQ8er9y@sJjA2Bya;tIw&oWc=lSfUEZIYrfSH9sC zc=`DCne|8gTkphB_FH9JyGK9nz=TwKN6?8A?C=lYV*!l?`SQ9}4|4 z=25>v*v%Uw>Un-RIAAGSj`^MS^x-K4ZqTSindfHpeZ{gR4}?kU(g(&p>>C~ZMEUpo zNwI9)ajW@ujtRf1PndDmrQ~JQS9VwERPL>ep;<;Rm0a=tp2Yg%6NYu@?6CJqNxWkG zImHLfl+SpyWr&3)8o7VjrBgnq?EGwac_|~adYX5H|H<9AXZn_$6@x~SZ(ILxv`VhI z?knE9G@kn|*eYgnmeH^5wCqU65XbwB5^uvNFKZyT4nBRo$3tGJ^0-0b$!vS8(+gGs z(3^(z8jmu~C4>TU%1$o%q^YTYoxe;FZ?))G@a@Btw=P#{EApUOMj3qFJbnoNc+O(A zhkoKkT;K;+h31SLulBv6+o~2@;ob2E7tdr&V(eeU1;iXtlIM^M_BlT)Hg8?HxNm;Z zYxaFpXxQ`b=cI4Sits%2XIgGeIVfSbDMaC}W1!5F6OM-m|Jh(IHgJScWu!jzG>mSr zfv%?iqRY~o&6l9fCpWNtnEQO-rLn;f7i$nlp>FaIgQx;7wg)qX<(~!z+pN00yq(nk zL5-=FYnoK|sxl=kUT5o-+Gt-G$bqkl@z`l3rlaaR2PKumI$<9^>1}6gkDRd``J|`4 zurSRz<>ocNb;`}jhvdO6AXSwP`S{NbJcW*1CQ;KVXW+bB3LUB9@v|7v@@Z|nzJFW*&Y3SMrQJnz$7Yb zvta%;MEA||?@F>VysEq%BU*K}77c>2lRu9f+b5Ae>4@XhH zFpFAmjVQA=K9;LxCeN4`m)&MaBact3ySL6FeoR?O2V-m%_W6kA&kE)TOVz*nn&&S! z-aoM?)04_z}m zT7IWn*rfG^L>2S+-1N|p#awJh#jGvnMx;p~yO+9$pYMWFmB4rjzOdgv^83SCVr;Y5 zHLZ~mtM82qDPMZICTbV!KQ=!1r@P&o$Mc73Z{>)`nre?+S^b|~@crG<1QeS3XhM2? zuXCaXd+^&?lkwEvOqlo33ryo>-e<^6i)Ny=obRKZQQE9JtU6*pedA1J2J=F9bA`VT z^;=9TQutCSZ^tuma4zz&eSyk`4Gg8PnJ^?&WCAT z(v8L^SH|w})l|b04-r@6RpU|EB1)f^Zp`@hcM)Ons%H_wE_FOL_a3KkykPId)|EJug?ZHRm?z@u zgg&rZ?O@J{xRckAVk;jEwK?|@=+b4y+|TAr4{9l$jMx_I{F-T$Hx_m>7@F-WK6XNG zoG{BgLFq-p1y|mBoI+9p{>%Mi?=!rt?KztuWDtt^;RH|3t;YiVu;4x`=J`vwz~cd` z`_d%tIX2miux{PK+FrRqFI0@47Wb{2^THMrw*>$*W_%QLu z@|T(A9Ve1a8XZf1ioV)E+$^9Ul014Qi$jjfxxQQG<)he)5$06JjT-MS zIRLzuwx>o&ZaUfToYoDpC#w_ItQT&IiSZ$kKMHe9eqIWB9_F$;PV9i1>HP& z)gy+lUbJhv|9eELu-=eq^lb|^4r}?i(ySv*W$9Mf&3Bub>8x+pUflUa=zPF{z^NY! zoL~5Ohn6%8!k)|N7=0DG+&-PV=$x%5U7!6-&Ed5Kx>3+luajPR*ZvZ&EAPKdoeE}l zeADnOgSUsjAPqab!zd@~dZ6p|!a(KME*23;ET`|I!S^T0o-kvh+c zHiZZShew=zJRwlWt+{6ut1G?cmgwSG(tK{c-()Mz*E^%3o#l|i<0# zSm4Z1d9}%RaSrR*RGX2I>3x!X%lq~eaf;k}$UR*q9rs{PhR>yDW0nGGQHHHP*1Oy(~O6ppKC^Ddj>CUoHA)M2*+SP9GaiM9KxC#db67tD)dB> zw`8HH!tYchUC!52`)W-WTC7g;T-zYpvK`f{JFXP}Gpyg=btsq1b<1bheJysS^^UXJ z9s9a`CUfH^4@cX#4>gwG94fJP^2^lp>63;Rj&P1-cXK>rp7mLrLPE=(9IrB0$aq<0 zNXyWV#>p;KqnczkW)~I?VWVz%w>^A_n+_CL6uQv+%quLa&LX}Z z_U#&LBV8=Exw!iTtB?Z=#t zlvHsw23{p;zM(_x~S}uN8reli+C+LcKT^A#_oM=-$EAfew z4jK+0H>_M(GM%Nv_6u0YOyGV*D+&g`_|{k)la}MmQN5hi*eP=Uo3?2&=a<@cqa64Xx)eYc$58iRGd9MheN<0*b6wQuH5%UOX}b+Y$&zpxFDE8g?$ zeVtk|cKR;NIaXapT_)>9NWqaqdrxQ8?&DAGG5Of(R&&~0x%m|mbBc2*O*3VmRQ=22 zlAFI^F{TT7^evU63HwU2qpf;%H!1-|OW@*a=iqQ;7W{sviJ zz6E#5l%E%WcHL_`Nnu+$KI0D^Pw6noy{mk8JAb(Po!xSIDJKbV z`Kblf!Px2A$ZUVSP_T)=$%lU`F%H!adcWVvIs0VVs@-A7{K>4-i9hL-wc=0wAq4*L zZ8U{t|I?a~`eYQG{56E3?0-3>iukL&e;5=)z4`y@sA+gAn%#HAr0+qiVx7fy(e?+Q zTiR^WyWQm4GbII#bq9s*7_1mR*?jBjGE=+kxY76CZTg!1-{!aV5}7r zJ=YY@n-&Mne0_C^%arbO*KFp&I9?^~Ns|cH%9@D5of;0ZVNDk<_@c^uyiDVGt94#y zPkkyi+-or(q`6cu#9TeKx!SHJ-mE|<_tT!bjJfnEjc8`*r!-Oy|q zj=^Tn$)fL?xzx$ZD>lo@J(dNuifE)yjs*cWy3dIS+zHsm9tW*`?8ZDndgHz&IvBrQ zK0IW1L}{jOl}80u(JcO-mig%G(RT0IR3cw5^qEvUd=B#3*xi%3pJVS<{zB557O`nK zMoY@kIa0QI@aX+0R?lGNYnu-T)}^sX_~WGZHH?H0JbON~NuhXY?@70i-Zb$V2s4}Z z!q;x;+^+W@+Br>|Z9S}Zko3YD@Rdd9hlWT4X(y7zjcqv&2VJk%nm8CUFb91<_BqF< zJM$i&qt2zAE&3(9h0GAowr@+jH}=GrL*aSV~|N1Haesy>4;qwjLVGxBOdiqXOp;nvZ{dAi& zy*B)o)}LEnV9MO zc!Wj2ZjY!pca|>`o9T9wW^8V3@9ld7TdVqfJI`{wY*!oL);k~=$os>3;(U7dq`R3P zs!Afhl`WGubed6Y8~b-cdB=WJsh_b!Qnn20l^1q*ey+z7tzzsh?QZ6VX`5%n5Wk@y z4}wj$e)nIR<*EtAR`>)K6XhC3uPh&Q-gN&9HgTW%htb$vE`_{=>mBd>VP@yU1vQgz z9D5!2Dc{FF^joED+?}J{pEHG2T;9c(oqSWVDHo{mOSYdav0SVi&e{I6j9o9+Hl4e# zLo3qb)ApvT%iH&K#wpQoodS@ln-SKBK zY>OJAA){Iq797{y!fft&y5GK*g^I>u$edbQ}P`~(a(HF$+z1Dj9d1y8*dql zWq3@eG)cc78bX33yYhH+#FS5OGrHO}g>gP%D`ywx(VaiaQft>dwv6v;y3?%mZDb*z z*Ow>h@&ZePSml@LpDzL}Mw~@|a4j==T)2O1eR4#soP42PFjErI|Fz`!cXu~nNUCo~ z>Txj*s0y_>Om@b@pLx0Rg^fN5$3XP1+ds~o^R92YGJ1`0Qo zJw(1Ef*{Y;0QHD2b_8*l3`_cJ4a7U)?FqnTA_#Ed z#f9i#?JW0O3v%VY$}eM)G#F4zhC?x{k`ez^G7SvK)sqgO%^;8zn-MtNs${a&|Ji2B zLA_NpP%CB0uW^Hc#SDlB0`$hii%)$e;c zk+R_t_oEjrb3Wf1snk+oi$;D0!JG33r$Hw zfE&LYqiCW671Xto9Z(?c!K4HR6bLG%oyupj3TlJEoIn8;L#FsI7Jbz82YfXkI*?pl0GGkQUK?pEsww?1KOPbMi)&$QN&PT3i~x@li5KID2i)HuoVOon3GiPNEWt` zBTfXu->9V6zX~Qr7`4h@qwq`RN>V|r6i(F41ZF9117`@{!4jfJw6wG%xC8g6|FaD% zvlmDfaP|VB0}~9TebqQhR-!VFI^$9B0F6U}wt?~dJLy1-Je^$#_J3m!3ZxKd4~Q;k z4-Hrp4b=8fWe6&JR!9$q=88SQY-T`m2l5cWKxbF`bL30}QN`O?xB_nrAUQ#t2CT*hz`mQ&ct88QwjeK!QadN3$d#!oWB=KFsobP!5NK)}od0oR%k7$puM;3^10IUQ>V0fQ9+rw{|E1%AEL;n(=U zpud*iXiE20+$d{*YW1Lakj@YUg-L%9i1;^o6!}#0C>BA$9fm*1fdR)Nek~`_t8)#- z0ad&U-i~A~`-^LkUsDJ077Awwts`hMSfFA(lBF8(S`cwHIXD!Cg(6@$7z~C+;iRD$ zF(_0_LRJ-cs|YzM{O6~D*tB%DAUKH=DX+hP%Rpt&kW=F3o)9~dJKmZ|kg*`ypOTP} z1*k#Z;t*dm;jLsDh&4Fp1Jy0i(ddXC0x+f1Yr~?~V*t>P)@CFIyIvj^OD;s#V1UHnuIoH`?cb+=N-@ z8w?-FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data goes into FLASH */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .integrity (NOLOAD): - { - . = ALIGN(4); - *(.integrity) /* .integrity internal integrity protection of NVFile */ - *(.integrity*) /* .integrity* internal integrity protection of NVFile */ - . = ALIGN(4); - } >INTEGRITY - - .nvfile (NOLOAD): - { - . = ALIGN(4); - *(.nvfile) /* .nvfile persisted NV storage for the TPM */ - *(.nvfile*) /* .nvfile* persisted NV storage for the TPM */ - . = ALIGN(4); - } >NVFILE - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH - - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(4); - } >RAM - - - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/main.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/main.c deleted file mode 100644 index a1ce0419d..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/main.c +++ /dev/null @@ -1,401 +0,0 @@ - -/** - ****************************************************************************** - * @file : main.c - * @brief : Main program body - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -#include "stm32l4xx_hal.h" -#include "usb_device.h" - -/* USER CODE BEGIN Includes */ -#include -#include -#include -#include "TpmDevice.h" -#include "StmUtil.h" - -/* USER CODE END Includes */ - -/* Private variables ---------------------------------------------------------*/ -RNG_HandleTypeDef hrng; - -RTC_HandleTypeDef hrtc; - -UART_HandleTypeDef huart2; - -/* USER CODE BEGIN PV */ -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -void SystemClock_Config(void); -static void MX_GPIO_Init(void); -static void MX_USART2_UART_Init(void); -static void MX_RTC_Init(void); -static void MX_RNG_Init(void); - -/* USER CODE BEGIN PFP */ -/* Private function prototypes -----------------------------------------------*/ - -/* USER CODE END PFP */ - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/** - * @brief The application entry point. - * - * @retval None - */ -int main(void) -{ - /* USER CODE BEGIN 1 */ - - /* USER CODE END 1 */ - - /* MCU Configuration----------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - - /* USER CODE BEGIN Init */ - - /* USER CODE END Init */ - - /* Configure the system clock */ - SystemClock_Config(); - - /* USER CODE BEGIN SysInit */ - - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_USART2_UART_Init(); - MX_RTC_Init(); - MX_USB_DEVICE_Init(); - MX_RNG_Init(); - /* USER CODE BEGIN 2 */ - InitializeITM(); - fprintf(stderr, "\r\n\r\n=========================\r\n" - "= Nucleo-L476RG TPM 2.0 =\r\n" - "=========================\r\n"); - printf("Nucleo-L476RG TPM 2.0\r\n"); - - if(!TpmInitializeDevice()) - { - _Error_Handler(__FILE__, __LINE__); - } - - /* USER CODE END 2 */ - - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - - /* USER CODE END WHILE */ - - /* USER CODE BEGIN 3 */ - if(!TpmOperationsLoop()) - { - _Error_Handler(__FILE__, __LINE__); - } - - } - /* USER CODE END 3 */ - -} - -/** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) -{ - - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInit; - - /**Configure LSE Drive Capability - */ - HAL_PWR_EnableBkUpAccess(); - - __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI - |RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; - RCC_OscInitStruct.HSICalibrationValue = 64; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 1; // <-- This one gets dropped by V1.11.0 add me manually back in when CubeMX ran - RCC_OscInitStruct.PLL.PLLN = 10; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; - RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - /**Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART2 - |RCC_PERIPHCLK_USB|RCC_PERIPHCLK_RNG; - PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; - PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; - PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - PeriphClkInit.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - /**Configure the main internal regulator output voltage - */ - if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - /**Configure the Systick interrupt time - */ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); - - /**Configure the Systick - */ - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - - /* SysTick_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); -} - -/* RNG init function */ -static void MX_RNG_Init(void) -{ - - hrng.Instance = RNG; - if (HAL_RNG_Init(&hrng) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - -} - -/* RTC init function */ -static void MX_RTC_Init(void) -{ - - RTC_TimeTypeDef sTime; - RTC_DateTypeDef sDate; - - /**Initialize RTC Only - */ - hrtc.Instance = RTC; -if(HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_DR0) != 0x32F2){ - hrtc.Init.HourFormat = RTC_HOURFORMAT_24; - hrtc.Init.AsynchPrediv = 127; - hrtc.Init.SynchPrediv = 255; - hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; - hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; - hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - if (HAL_RTC_Init(&hrtc) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - /**Initialize RTC and set the Time and Date - */ - sTime.Hours = 0; - sTime.Minutes = 0; - sTime.Seconds = 0; - sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; - sTime.StoreOperation = RTC_STOREOPERATION_RESET; - if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BIN) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - sDate.WeekDay = RTC_WEEKDAY_MONDAY; - sDate.Month = RTC_MONTH_JANUARY; - sDate.Date = 1; - sDate.Year = 0; - - if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BIN) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - HAL_RTCEx_BKUPWrite(&hrtc,RTC_BKP_DR0,0x32F2); - } - -} - -/* USART2 init function */ -static void MX_USART2_UART_Init(void) -{ - - huart2.Instance = USART2; - huart2.Init.BaudRate = 115200; - huart2.Init.WordLength = UART_WORDLENGTH_8B; - huart2.Init.StopBits = UART_STOPBITS_1; - huart2.Init.Parity = UART_PARITY_NONE; - huart2.Init.Mode = UART_MODE_TX; - huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart2.Init.OverSampling = UART_OVERSAMPLING_16; - huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart2) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - -} - -/** Configure pins as - * Analog - * Input - * Output - * EVENT_OUT - * EXTI -*/ -static void MX_GPIO_Init(void) -{ - - GPIO_InitTypeDef GPIO_InitStruct; - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pin : B1_Pin */ - GPIO_InitStruct.Pin = B1_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pin : LD2_Pin */ - GPIO_InitStruct.Pin = LD2_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct); - -} - -/* USER CODE BEGIN 4 */ - -/* USER CODE END 4 */ - -/** - * @brief This function is executed in case of error occurrence. - * @param file: The file name as string. - * @param line: The line in file as a number. - * @retval None - */ -void _Error_Handler(char *file, int line) -{ - /* USER CODE BEGIN Error_Handler_Debug */ - dbgPrint("PANIC: EXECUTION HALTED %s@%d\r\n", file, line); - /* User can add his own implementation to report the HAL error return state */ - while(1) - { - } - /* USER CODE END Error_Handler_Debug */ -} - -#ifdef USE_FULL_ASSERT -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t* file, uint32_t line) -{ - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, - tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ -} -#endif /* USE_FULL_ASSERT */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/stm32l4xx_hal_msp.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/stm32l4xx_hal_msp.c deleted file mode 100644 index 85c46f9e1..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/stm32l4xx_hal_msp.c +++ /dev/null @@ -1,225 +0,0 @@ -/** - ****************************************************************************** - * File Name : stm32l4xx_hal_msp.c - * Description : This file provides code for the MSP Initialization - * and de-Initialization codes. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" - -extern void _Error_Handler(char *, int); -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ -/** - * Initializes the Global MSP. - */ -void HAL_MspInit(void) -{ - /* USER CODE BEGIN MspInit 0 */ - - /* USER CODE END MspInit 0 */ - - __HAL_RCC_SYSCFG_CLK_ENABLE(); - __HAL_RCC_PWR_CLK_ENABLE(); - - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - - /* System interrupt init*/ - /* MemoryManagement_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0); - /* BusFault_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0); - /* UsageFault_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0); - /* SVCall_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0); - /* DebugMonitor_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0); - /* PendSV_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0); - /* SysTick_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); - - /* USER CODE BEGIN MspInit 1 */ - - /* USER CODE END MspInit 1 */ -} - -void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) -{ - - if(hrng->Instance==RNG) - { - /* USER CODE BEGIN RNG_MspInit 0 */ - - /* USER CODE END RNG_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_RNG_CLK_ENABLE(); - /* USER CODE BEGIN RNG_MspInit 1 */ - - /* USER CODE END RNG_MspInit 1 */ - } - -} - -void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng) -{ - - if(hrng->Instance==RNG) - { - /* USER CODE BEGIN RNG_MspDeInit 0 */ - - /* USER CODE END RNG_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_RNG_CLK_DISABLE(); - /* USER CODE BEGIN RNG_MspDeInit 1 */ - - /* USER CODE END RNG_MspDeInit 1 */ - } - -} - -void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) -{ - - if(hrtc->Instance==RTC) - { - /* USER CODE BEGIN RTC_MspInit 0 */ - - /* USER CODE END RTC_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_RTC_ENABLE(); - /* USER CODE BEGIN RTC_MspInit 1 */ - - /* USER CODE END RTC_MspInit 1 */ - } - -} - -void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) -{ - - if(hrtc->Instance==RTC) - { - /* USER CODE BEGIN RTC_MspDeInit 0 */ - - /* USER CODE END RTC_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_RTC_DISABLE(); - /* USER CODE BEGIN RTC_MspDeInit 1 */ - - /* USER CODE END RTC_MspDeInit 1 */ - } - -} - -void HAL_UART_MspInit(UART_HandleTypeDef* huart) -{ - - GPIO_InitTypeDef GPIO_InitStruct; - if(huart->Instance==USART2) - { - /* USER CODE BEGIN USART2_MspInit 0 */ - - /* USER CODE END USART2_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_USART2_CLK_ENABLE(); - - /**USART2 GPIO Configuration - PA2 ------> USART2_TX - PA3 ------> USART2_RX - */ - GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF7_USART2; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN USART2_MspInit 1 */ - - /* USER CODE END USART2_MspInit 1 */ - } - -} - -void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) -{ - - if(huart->Instance==USART2) - { - /* USER CODE BEGIN USART2_MspDeInit 0 */ - - /* USER CODE END USART2_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration - PA2 ------> USART2_TX - PA3 ------> USART2_RX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); - - /* USER CODE BEGIN USART2_MspDeInit 1 */ - - /* USER CODE END USART2_MspDeInit 1 */ - } - -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/stm32l4xx_it.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/stm32l4xx_it.c deleted file mode 100644 index 030611243..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/stm32l4xx_it.c +++ /dev/null @@ -1,212 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l4xx_it.c - * @brief Interrupt Service Routines. - ****************************************************************************** - * - * COPYRIGHT(c) 2018 STMicroelectronics - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" -#include "stm32l4xx.h" -#include "stm32l4xx_it.h" - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* External variables --------------------------------------------------------*/ -extern PCD_HandleTypeDef hpcd_USB_OTG_FS; - -/******************************************************************************/ -/* Cortex-M4 Processor Interruption and Exception Handlers */ -/******************************************************************************/ - -/** -* @brief This function handles Non maskable interrupt. -*/ -void NMI_Handler(void) -{ - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ - - /* USER CODE END NonMaskableInt_IRQn 1 */ -} - -/** -* @brief This function handles Hard fault interrupt. -*/ -void HardFault_Handler(void) -{ - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - /* USER CODE END W1_HardFault_IRQn 0 */ - } - /* USER CODE BEGIN HardFault_IRQn 1 */ - - /* USER CODE END HardFault_IRQn 1 */ -} - -/** -* @brief This function handles Memory management fault. -*/ -void MemManage_Handler(void) -{ - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ - /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } - /* USER CODE BEGIN MemoryManagement_IRQn 1 */ - - /* USER CODE END MemoryManagement_IRQn 1 */ -} - -/** -* @brief This function handles Prefetch fault, memory access fault. -*/ -void BusFault_Handler(void) -{ - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_BusFault_IRQn 0 */ - /* USER CODE END W1_BusFault_IRQn 0 */ - } - /* USER CODE BEGIN BusFault_IRQn 1 */ - - /* USER CODE END BusFault_IRQn 1 */ -} - -/** -* @brief This function handles Undefined instruction or illegal state. -*/ -void UsageFault_Handler(void) -{ - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ - /* USER CODE END W1_UsageFault_IRQn 0 */ - } - /* USER CODE BEGIN UsageFault_IRQn 1 */ - - /* USER CODE END UsageFault_IRQn 1 */ -} - -/** -* @brief This function handles System service call via SWI instruction. -*/ -void SVC_Handler(void) -{ - /* USER CODE BEGIN SVCall_IRQn 0 */ - - /* USER CODE END SVCall_IRQn 0 */ - /* USER CODE BEGIN SVCall_IRQn 1 */ - - /* USER CODE END SVCall_IRQn 1 */ -} - -/** -* @brief This function handles Debug monitor. -*/ -void DebugMon_Handler(void) -{ - /* USER CODE BEGIN DebugMonitor_IRQn 0 */ - - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - - /* USER CODE END DebugMonitor_IRQn 1 */ -} - -/** -* @brief This function handles Pendable request for system service. -*/ -void PendSV_Handler(void) -{ - /* USER CODE BEGIN PendSV_IRQn 0 */ - - /* USER CODE END PendSV_IRQn 0 */ - /* USER CODE BEGIN PendSV_IRQn 1 */ - - /* USER CODE END PendSV_IRQn 1 */ -} - -/** -* @brief This function handles System tick timer. -*/ -void SysTick_Handler(void) -{ - /* USER CODE BEGIN SysTick_IRQn 0 */ - - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - HAL_SYSTICK_IRQHandler(); - /* USER CODE BEGIN SysTick_IRQn 1 */ - - /* USER CODE END SysTick_IRQn 1 */ -} - -/******************************************************************************/ -/* STM32L4xx Peripheral Interrupt Handlers */ -/* Add here the Interrupt Handlers for the used peripherals. */ -/* For the available peripheral interrupt handler names, */ -/* please refer to the startup file (startup_stm32l4xx.s). */ -/******************************************************************************/ - -/** -* @brief This function handles USB OTG FS global interrupt. -*/ -void OTG_FS_IRQHandler(void) -{ - /* USER CODE BEGIN OTG_FS_IRQn 0 */ - - /* USER CODE END OTG_FS_IRQn 0 */ - HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); - /* USER CODE BEGIN OTG_FS_IRQn 1 */ - - /* USER CODE END OTG_FS_IRQn 1 */ -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/system_stm32l4xx.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/system_stm32l4xx.c deleted file mode 100644 index c76fe45ee..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/system_stm32l4xx.c +++ /dev/null @@ -1,353 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l4xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32l4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * After each device reset the MSI (4 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to - * configure the system clock before to branch to main program. - * - * This file configures the system clock as follows: - *============================================================================= - *----------------------------------------------------------------------------- - * System Clock source | MSI - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 4000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 4000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- - * PLL_M | 1 - *----------------------------------------------------------------------------- - * PLL_N | 8 - *----------------------------------------------------------------------------- - * PLL_P | 7 - *----------------------------------------------------------------------------- - * PLL_Q | 2 - *----------------------------------------------------------------------------- - * PLL_R | 2 - *----------------------------------------------------------------------------- - * PLLSAI1_P | NA - *----------------------------------------------------------------------------- - * PLLSAI1_Q | NA - *----------------------------------------------------------------------------- - * PLLSAI1_R | NA - *----------------------------------------------------------------------------- - * PLLSAI2_P | NA - *----------------------------------------------------------------------------- - * PLLSAI2_Q | NA - *----------------------------------------------------------------------------- - * PLLSAI2_R | NA - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Disabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** @addtogroup STM32L4xx_System_Private_Includes - * @{ - */ - -#include "stm32l4xx.h" - -#if !defined (HSE_VALUE) - #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (MSI_VALUE) - #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ - uint32_t SystemCoreClock = 4000000U; - - const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; - const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; - const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \ - 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U}; -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000U; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= 0xEAF6FFFFU; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000U; - - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000U; - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) - * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value - * 4 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U; - - /* Get MSI Range frequency--------------------------------------------------*/ - if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) - { /* MSISRANGE from RCC_CSR applies */ - msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; - } - else - { /* MSIRANGE from RCC_CR applies */ - msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; - } - /*MSI frequency range in HZ*/ - msirange = MSIRangeTable[msirange]; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR & RCC_CFGR_SWS) - { - case 0x00: /* MSI used as system clock source */ - SystemCoreClock = msirange; - break; - - case 0x04: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - - case 0x08: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - - case 0x0C: /* PLL used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; - - switch (pllsource) - { - case 0x02: /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm); - break; - - case 0x03: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm); - break; - - default: /* MSI used as PLL clock source */ - pllvco = (msirange / pllm); - break; - } - pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; - SystemCoreClock = pllvco/pllr; - break; - - default: - SystemCoreClock = msirange; - break; - } - /* Compute HCLK clock frequency --------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/usb_device.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/usb_device.c deleted file mode 100644 index 8301f6af7..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/usb_device.c +++ /dev/null @@ -1,173 +0,0 @@ -/** - ****************************************************************************** - * @file : usb_device.c - * @version : v2.0_Cube - * @brief : This file implements the USB Device - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#include "usb_device.h" -#include "usbd_core.h" -#include "usbd_desc.h" -#include "usbd_cdc.h" -#include "usbd_cdc_if.h" - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* USER CODE BEGIN PV */ -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE END PV */ - -/* USER CODE BEGIN PFP */ -/* Private function prototypes -----------------------------------------------*/ - -/* USER CODE END PFP */ - -/* Return USBD_OK if the Battery Charging Detection mode (BCD) is used, else USBD_FAIL. */ -extern USBD_StatusTypeDef USBD_LL_BatteryCharging(USBD_HandleTypeDef *pdev); - -/* USB Device Core handle declaration. */ -USBD_HandleTypeDef hUsbDeviceFS; - -/* - * -- Insert your variables declaration here -- - */ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* - * -- Insert your external function declaration here -- - */ -/* USER CODE BEGIN 1 */ -void MX_USB_DEVICE_DeInit(void) -{ - USBD_DeInit(&hUsbDeviceFS); -} - -/* USER CODE END 1 */ - -/** - * Init USB device Library, add supported class and start the library - * @retval None - */ -void MX_USB_DEVICE_Init(void) -{ - /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ - - /* USER CODE END USB_DEVICE_Init_PreTreatment */ - - /* Init Device Library, add supported class and start the library. */ - USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS); - USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC); - USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS); - /* Verify if the Battery Charging Detection mode (BCD) is used : */ - /* If yes, the USB device is started in the HAL_PCDEx_BCD_Callback */ - /* upon reception of PCD_BCD_DISCOVERY_COMPLETED message. */ - /* If no, the USB device is started now. */ - if (USBD_LL_BatteryCharging(&hUsbDeviceFS) != USBD_OK) { - USBD_Start(&hUsbDeviceFS); - } - /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */ - - /* USER CODE END USB_DEVICE_Init_PostTreatment */ -} - -/** - * @brief Send BCD message to user layer - * @param hpcd: PCD handle - * @param msg: LPM message - * @retval None - */ -void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) -{ - USBD_HandleTypeDef usbdHandle = hUsbDeviceFS; - - /* USER CODE BEGIN 7 */ - if (hpcd->battery_charging_active == ENABLE) - { - switch(msg) - { - case PCD_BCD_CONTACT_DETECTION: - - break; - - case PCD_BCD_STD_DOWNSTREAM_PORT: - - break; - - case PCD_BCD_CHARGING_DOWNSTREAM_PORT: - - break; - - case PCD_BCD_DEDICATED_CHARGING_PORT: - - break; - - case PCD_BCD_DISCOVERY_COMPLETED: - USBD_Start(&usbdHandle); - break; - - case PCD_BCD_ERROR: - default: - break; - } - } - /* USER CODE END 7 */ -} - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/usbd_cdc_if.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/usbd_cdc_if.c deleted file mode 100644 index 46acaf9d4..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/usbd_cdc_if.c +++ /dev/null @@ -1,392 +0,0 @@ -/** - ****************************************************************************** - * @file : usbd_cdc_if.c - * @version : v2.0_Cube - * @brief : Usb device for Virtual Com Port. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_cdc_if.h" - -/* USER CODE BEGIN INCLUDE */ -#include -#include -#include "StmUtil.h" -#include "stm32l4xx_hal.h" - -/* USER CODE END INCLUDE */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ - -/* USER CODE BEGIN PV */ -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE END PV */ - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @brief Usb device library. - * @{ - */ - -/** @addtogroup USBD_CDC_IF - * @{ - */ - -/** @defgroup USBD_CDC_IF_Private_TypesDefinitions USBD_CDC_IF_Private_TypesDefinitions - * @brief Private types. - * @{ - */ - -/* USER CODE BEGIN PRIVATE_TYPES */ -#define CDC_RTS_MASK 0x0002 -#define CDC_DTR_MASK 0x0001 -void TpmConnectionReset(void); -int TpmSignalEvent(uint8_t* Buf, uint32_t *Len); - -/* USER CODE END PRIVATE_TYPES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Private_Defines USBD_CDC_IF_Private_Defines - * @brief Private defines. - * @{ - */ - -/* USER CODE BEGIN PRIVATE_DEFINES */ -/* Define size for the receive and transmit buffer over CDC */ -/* It's up to user to redefine and/or remove those define */ -#define APP_RX_DATA_SIZE 2048 -#define APP_TX_DATA_SIZE 2048 -typedef struct -{ - uint8_t bReqType; - uint8_t bRequest; - uint16_t wVal; - uint16_t wIndex; - uint16_t wLength; -} USBD_SETUP_PKT, *PUSBD_SETUP_PKT; -extern RTC_HandleTypeDef hrtc; -/* USER CODE END PRIVATE_DEFINES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Private_Macros USBD_CDC_IF_Private_Macros - * @brief Private macros. - * @{ - */ - -/* USER CODE BEGIN PRIVATE_MACRO */ - -/* USER CODE END PRIVATE_MACRO */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Private_Variables USBD_CDC_IF_Private_Variables - * @brief Private variables. - * @{ - */ -/* Create buffer for reception and transmission */ -/* It's up to user to redefine and/or remove those define */ -/** Received data over USB are stored in this buffer */ -uint8_t UserRxBufferFS[APP_RX_DATA_SIZE]; - -/** Data to send over USB CDC are stored in this buffer */ -uint8_t UserTxBufferFS[APP_TX_DATA_SIZE]; - -/* USER CODE BEGIN PRIVATE_VARIABLES */ - -/* USER CODE END PRIVATE_VARIABLES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables - * @brief Public variables. - * @{ - */ - -extern USBD_HandleTypeDef hUsbDeviceFS; - -/* USER CODE BEGIN EXPORTED_VARIABLES */ -USBD_CDC_LineCodingTypeDef LineCoding = -{ - 115200, /* baud rate*/ - 0x00, /* stop bits-1*/ - 0x00, /* parity - none*/ - 0x08 /* nb. of bits 8*/ -}; -volatile uint8_t CDC_RTS = 0; // RequestToSend -volatile uint8_t CDC_DTR = 0; // DataTerminalReady - -/* USER CODE END EXPORTED_VARIABLES */ - -/** - * @} - */ - -/** @defgroup USBD_CDC_IF_Private_FunctionPrototypes USBD_CDC_IF_Private_FunctionPrototypes - * @brief Private functions declaration. - * @{ - */ - -static int8_t CDC_Init_FS(void); -static int8_t CDC_DeInit_FS(void); -static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length); -static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len); - -/* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */ - -/* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */ - -/** - * @} - */ - -USBD_CDC_ItfTypeDef USBD_Interface_fops_FS = -{ - CDC_Init_FS, - CDC_DeInit_FS, - CDC_Control_FS, - CDC_Receive_FS -}; - -/* Private functions ---------------------------------------------------------*/ -/** - * @brief Initializes the CDC media low layer over the FS USB IP - * @retval USBD_OK if all operations are OK else USBD_FAIL - */ -static int8_t CDC_Init_FS(void) -{ - /* USER CODE BEGIN 3 */ - /* Set Application Buffers */ - USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); - USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); - return (USBD_OK); - /* USER CODE END 3 */ -} - -/** - * @brief DeInitializes the CDC media low layer - * @retval USBD_OK if all operations are OK else USBD_FAIL - */ -static int8_t CDC_DeInit_FS(void) -{ - /* USER CODE BEGIN 4 */ - return (USBD_OK); - /* USER CODE END 4 */ -} - -/** - * @brief Manage the CDC class requests - * @param cmd: Command code - * @param pbuf: Buffer containing command data (request parameters) - * @param length: Number of data to be sent (in bytes) - * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL - */ -static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) -{ - /* USER CODE BEGIN 5 */ - char parity[] = {'N', 'O', 'E', 'M', 'S'}; - uint8_t stop[] = {1, 15, 2}; - switch (cmd) - { - case CDC_SEND_ENCAPSULATED_COMMAND: - - break; - - case CDC_GET_ENCAPSULATED_RESPONSE: - - break; - - case CDC_SET_COMM_FEATURE: - - break; - - case CDC_GET_COMM_FEATURE: - - break; - - case CDC_CLEAR_COMM_FEATURE: - - break; - - /*******************************************************************************/ - /* Line Coding Structure */ - /*-----------------------------------------------------------------------------*/ - /* Offset | Field | Size | Value | Description */ - /* 0 | dwDTERate | 4 | Number |Data terminal rate, in bits per second*/ - /* 4 | bCharFormat | 1 | Number | Stop bits */ - /* 0 - 1 Stop bit */ - /* 1 - 1.5 Stop bits */ - /* 2 - 2 Stop bits */ - /* 5 | bParityType | 1 | Number | Parity */ - /* 0 - None */ - /* 1 - Odd */ - /* 2 - Even */ - /* 3 - Mark */ - /* 4 - Space */ - /* 6 | bDataBits | 1 | Number Data bits (5, 6, 7, 8 or 16). */ - /*******************************************************************************/ - case CDC_SET_LINE_CODING: - { - LineCoding.bitrate = pbuf[0] | (pbuf[1] << 8) | (pbuf[2] << 16) | (pbuf[3] << 24); - LineCoding.format = pbuf[4]; - LineCoding.paritytype = pbuf[5]; - LineCoding.datatype = pbuf[6]; - dbgPrint("CDC_SET_LINE_CODING: %lu-%d%c%d\r\n", LineCoding.bitrate, LineCoding.datatype, parity[LineCoding.paritytype], stop[LineCoding.format]); - break; - } - - case CDC_GET_LINE_CODING: - { - pbuf[0] = (uint8_t)(LineCoding.bitrate); - pbuf[1] = (uint8_t)(LineCoding.bitrate >> 8); - pbuf[2] = (uint8_t)(LineCoding.bitrate >> 16); - pbuf[3] = (uint8_t)(LineCoding.bitrate >> 24); - pbuf[4] = LineCoding.format; - pbuf[5] = LineCoding.paritytype; - pbuf[6] = LineCoding.datatype; - dbgPrint("CDC_GET_LINE_CODING: %lu-%d%c%d\r\n", LineCoding.bitrate, LineCoding.datatype, parity[LineCoding.paritytype], stop[LineCoding.format]); - break; - } - - case CDC_SET_CONTROL_LINE_STATE: - { - PUSBD_SETUP_PKT setupPkt = (PUSBD_SETUP_PKT)pbuf; - CDC_RTS = ((setupPkt->wVal & CDC_RTS_MASK) != 0); - CDC_DTR = ((setupPkt->wVal & CDC_DTR_MASK) != 0); - dbgPrint("CDC_SET_CONTROL_LINE_STATE: RTS=%d, DTR=%d\r\n", CDC_RTS, CDC_DTR); - // Reset any ongoing cmd transfers - TpmConnectionReset(); - break; - } - - case CDC_SEND_BREAK: - - break; - - default: - break; - } - - return (USBD_OK); - /* USER CODE END 5 */ -} - -/** - * @brief Data received over USB OUT endpoint are sent over CDC interface - * through this function. - * - * @note - * This function will block any OUT packet reception on USB endpoint - * untill exiting this function. If you exit this function before transfer - * is complete on CDC interface (ie. using DMA controller) it will result - * in receiving more data while previous ones are still not sent. - * - * @param Buf: Buffer of data to be received - * @param Len: Number of data received (in bytes) - * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL - */ -static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) -{ - /* USER CODE BEGIN 6 */ - if(!TpmSignalEvent(Buf, Len)) - { - return(USBD_FAIL); - } - - USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &Buf[0]); - USBD_CDC_ReceivePacket(&hUsbDeviceFS); - return (USBD_OK); - /* USER CODE END 6 */ -} - -/** - * @brief CDC_Transmit_FS - * Data to send over USB IN endpoint are sent over CDC interface - * through this function. - * @note - * - * - * @param Buf: Buffer of data to be sent - * @param Len: Number of data to be sent (in bytes) - * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY - */ -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) -{ - uint8_t result = USBD_OK; - /* USER CODE BEGIN 7 */ - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef*)hUsbDeviceFS.pClassData; - if (hcdc->TxState != 0){ - return USBD_BUSY; - } - USBD_CDC_SetTxBuffer(&hUsbDeviceFS, Buf, Len); - result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); - /* USER CODE END 7 */ - return result; -} - -/* USER CODE BEGIN PRIVATE_FUNCTIONS_IMPLEMENTATION */ - -/* USER CODE END PRIVATE_FUNCTIONS_IMPLEMENTATION */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/usbd_conf.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/usbd_conf.c deleted file mode 100644 index 6bec5fa31..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/usbd_conf.c +++ /dev/null @@ -1,894 +0,0 @@ -/** - ****************************************************************************** - * @file : usbd_conf.c - * @version : v2.0_Cube - * @brief : This file implements the board support package for the USB device library - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx.h" -#include "stm32l4xx_hal.h" -#include "usbd_def.h" -#include "usbd_core.h" -#include "usbd_cdc.h" - -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ - -/* USER CODE BEGIN PV */ -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE END PV */ - -PCD_HandleTypeDef hpcd_USB_OTG_FS; -void _Error_Handler(char * file, int line); - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* Exported function prototypes ----------------------------------------------*/ -extern USBD_StatusTypeDef USBD_LL_BatteryCharging(USBD_HandleTypeDef *pdev); - -/* USER CODE BEGIN PFP */ -/* Private function prototypes -----------------------------------------------*/ - -/* USER CODE END PFP */ - -/* Private functions ---------------------------------------------------------*/ - -/* USER CODE BEGIN 1 */ -static void SystemClockConfig_Resume(void); - -/* USER CODE END 1 */ - -void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state); -extern void SystemClock_Config(void); - -/******************************************************************************* - LL Driver Callbacks (PCD -> USB Device Library) -*******************************************************************************/ -/* MSP Init */ - -void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) -{ - GPIO_InitTypeDef GPIO_InitStruct; - if(pcdHandle->Instance==USB_OTG_FS) - { - /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ - - /* USER CODE END USB_OTG_FS_MspInit 0 */ - - /**USB_OTG_FS GPIO Configuration - PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP - */ - GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* Peripheral clock enable */ - __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - - /* Enable VDDUSB */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - HAL_PWREx_EnableVddUSB(); - __HAL_RCC_PWR_CLK_DISABLE(); - } - else - { - HAL_PWREx_EnableVddUSB(); - } - - /* Peripheral interrupt init */ - HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(OTG_FS_IRQn); - /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ - - /* USER CODE END USB_OTG_FS_MspInit 1 */ - } -} - -void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) -{ - if(pcdHandle->Instance==USB_OTG_FS) - { - /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */ - - /* USER CODE END USB_OTG_FS_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration - PA11 ------> USB_OTG_FS_DM - PA12 ------> USB_OTG_FS_DP - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); - - /* Disable VDDUSB */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - HAL_PWREx_DisableVddUSB(); - __HAL_RCC_PWR_CLK_DISABLE(); - } - else - { - HAL_PWREx_DisableVddUSB(); - } - - /* Peripheral interrupt Deinit*/ - HAL_NVIC_DisableIRQ(OTG_FS_IRQn); - - /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */ - - /* USER CODE END USB_OTG_FS_MspDeInit 1 */ - } -} - -/** - * @brief Setup stage callback - * @param hpcd: PCD handle - * @retval None - */ -void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) -{ - USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup); -} - -/** - * @brief Data Out stage callback. - * @param hpcd: PCD handle - * @param epnum: Endpoint number - * @retval None - */ -void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff); -} - -/** - * @brief Data In stage callback. - * @param hpcd: PCD handle - * @param epnum: Endpoint number - * @retval None - */ -void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff); -} - -/** - * @brief SOF callback. - * @param hpcd: PCD handle - * @retval None - */ -void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) -{ - USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData); -} - -/** - * @brief Reset callback. - * @param hpcd: PCD handle - * @retval None - */ -void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) -{ - USBD_SpeedTypeDef speed = USBD_SPEED_FULL; - - /* Set USB current speed. */ - switch (hpcd->Init.speed) - { - case PCD_SPEED_FULL: - speed = USBD_SPEED_FULL; - break; - - default: - speed = USBD_SPEED_FULL; - break; - } - USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); - - /* Reset Device. */ - USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); -} - -/** - * @brief Suspend callback. - * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) - * @param hpcd: PCD handle - * @retval None - */ -void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) -{ - __HAL_PCD_GATE_PHYCLOCK(hpcd); - /* Inform USB library that core enters in suspend Mode. */ - USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); - /* Enter in STOP mode. */ - /* USER CODE BEGIN 2 */ - if (hpcd->Init.low_power_enable) - { - /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ - SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - } - /* USER CODE END 2 */ -} - -/** - * @brief Resume callback. - * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) - * @param hpcd: PCD handle - * @retval None - */ -void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) -{ - __HAL_PCD_UNGATE_PHYCLOCK(hpcd); - - /* USER CODE BEGIN 3 */ - if (hpcd->Init.low_power_enable) - { - /* Reset SLEEPDEEP bit of Cortex System Control Register. */ - SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - SystemClockConfig_Resume(); - } - /* USER CODE END 3 */ - USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); -} - -/** - * @brief ISOOUTIncomplete callback. - * @param hpcd: PCD handle - * @param epnum: Endpoint number - * @retval None - */ -void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); -} - -/** - * @brief ISOINIncomplete callback. - * @param hpcd: PCD handle - * @param epnum: Endpoint number - * @retval None - */ -void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum); -} - -/** - * @brief Connect callback. - * @param hpcd: PCD handle - * @retval None - */ -void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) -{ - USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData); -} - -/** - * @brief Disconnect callback. - * @param hpcd: PCD handle - * @retval None - */ -void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) -{ - USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData); -} - -/******************************************************************************* - LL Driver Interface (USB Device Library --> PCD) -*******************************************************************************/ - -/** - * @brief Initializes the low level portion of the device driver. - * @param pdev: Device handle - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) -{ - /* Init USB Ip. */ - if (pdev->id == DEVICE_FS) { - /* Enable USB power on Pwrctrl CR2 register. */ - /* Link the driver to the stack. */ - hpcd_USB_OTG_FS.pData = pdev; - pdev->pData = &hpcd_USB_OTG_FS; - - hpcd_USB_OTG_FS.Instance = USB_OTG_FS; - hpcd_USB_OTG_FS.Init.dev_endpoints = 6; - hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; - hpcd_USB_OTG_FS.Init.ep0_mps = DEP0CTL_MPS_64; - hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; - hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; - hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; - hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; - hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE; - hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; - hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; - if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) - { - _Error_Handler(__FILE__, __LINE__); - } - - HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); - HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); - HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); - } - return USBD_OK; -} - -/** - * @brief De-Initializes the low level portion of the device driver. - * @param pdev: Device handle - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_DeInit(pdev->pData); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Starts the low level portion of the device driver. - * @param pdev: Device handle - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_Start(pdev->pData); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Stops the low level portion of the device driver. - * @param pdev: Device handle - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_Stop(pdev->pData); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Opens an endpoint of the low level driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @param ep_type: Endpoint type - * @param ep_mps: Endpoint max packet size - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Closes an endpoint of the low level driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Flushes an endpoint of the Low Level Driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Sets a Stall condition on an endpoint of the Low Level Driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Clears a Stall condition on an endpoint of the Low Level Driver. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Returns Stall condition. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval Stall (1: Yes, 0: No) - */ -uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; - - if((ep_addr & 0x80) == 0x80) - { - return hpcd->IN_ep[ep_addr & 0x7F].is_stall; - } - else - { - return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; - } -} - -/** - * @brief Assigns a USB address to the device. - * @param pdev: Device handle - * @param dev_addr: Device address - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Transmits data over an endpoint. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @param pbuf: Pointer to data to be sent - * @param size: Data size - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Prepares an endpoint for reception. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @param pbuf: Pointer to data to be received - * @param size: Data size - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) -{ - HAL_StatusTypeDef hal_status = HAL_OK; - USBD_StatusTypeDef usb_status = USBD_OK; - - hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); - - switch (hal_status) { - case HAL_OK : - usb_status = USBD_OK; - break; - case HAL_ERROR : - usb_status = USBD_FAIL; - break; - case HAL_BUSY : - usb_status = USBD_BUSY; - break; - case HAL_TIMEOUT : - usb_status = USBD_FAIL; - break; - default : - usb_status = USBD_FAIL; - break; - } - return usb_status; -} - -/** - * @brief Returns the last transfered packet size. - * @param pdev: Device handle - * @param ep_addr: Endpoint number - * @retval Recived Data Size - */ -uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) -{ - return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); -} - -#if (USBD_LPM_ENABLED == 1) -/** - * @brief Send LPM message to user layer - * @param hpcd: PCD handle - * @param msg: LPM message - * @retval None - */ -void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) -{ - switch (msg) - { - case PCD_LPM_L0_ACTIVE: - if (hpcd->Init.low_power_enable) - { - SystemClock_Config(); - - /* Reset SLEEPDEEP bit of Cortex System Control Register. */ - SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - } - __HAL_PCD_UNGATE_PHYCLOCK(hpcd); - USBD_LL_Resume(hpcd->pData); - break; - - case PCD_LPM_L1_ACTIVE: - __HAL_PCD_GATE_PHYCLOCK(hpcd); - USBD_LL_Suspend(hpcd->pData); - - /* Enter in STOP mode. */ - if (hpcd->Init.low_power_enable) - { - /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ - SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - } - break; - } -} -#endif /* (USBD_LPM_ENABLED == 1) */ - -/** - * @brief Delays routine for the USB Device Library. - * @param Delay: Delay in ms - * @retval None - */ -void USBD_LL_Delay(uint32_t Delay) -{ - HAL_Delay(Delay); -} - -/** - * @brief Static single allocation. - * @param size: Size of allocated memory - * @retval None - */ -void *USBD_static_malloc(uint32_t size) -{ - static uint32_t mem[(sizeof(USBD_CDC_HandleTypeDef)/4)+1];/* On 32-bit boundary */ - return mem; -} - -/** - * @brief Dummy memory free - * @param p: Pointer to allocated memory address - * @retval None - */ -void USBD_static_free(void *p) -{ - -} - -/* USER CODE BEGIN 5 */ -/** - * @brief Configures system clock after wake-up from USB resume callBack: - * enable HSI, PLL and select PLL as system clock source. - * @retval None - */ -static void SystemClockConfig_Resume(void) -{ - SystemClock_Config(); -} -/* USER CODE END 5 */ - -/** - * @brief Software device connection - * @param hpcd: PCD handle - * @param state: Connection state (0: disconnected / 1: connected) - * @retval None - */ -void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) -{ - /* USER CODE BEGIN 6 */ - if (state == 1) - { - /* Configure Low connection state. */ - - } - else - { - /* Configure High connection state. */ - - } - /* USER CODE END 6 */ -} - -/** - * @brief Verify if the Battery Charging Detection mode (BCD) is used : - * return USBD_OK if true - * else return USBD_FAIL if false - * @param pdev: Device handle - * @retval USBD status - */ -USBD_StatusTypeDef USBD_LL_BatteryCharging(USBD_HandleTypeDef *pdev) -{ - PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*)pdev->pData; - if (hpcd->Init.battery_charging_enable == ENABLE) - { - return USBD_OK; - } - else - { - return USBD_FAIL; - } -} - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/usbd_desc.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/usbd_desc.c deleted file mode 100644 index 1bd6b60af..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Src/usbd_desc.c +++ /dev/null @@ -1,405 +0,0 @@ -/** - ****************************************************************************** - * @file : usbd_desc.c - * @version : v2.0_Cube - * @brief : This file implements the USB device descriptors. - ****************************************************************************** - * This notice applies to any and all portions of this file - * that are not between comment pairs USER CODE BEGIN and - * USER CODE END. Other portions of this file, whether - * inserted by the user or by software development tools - * are owned by their respective copyright owners. - * - * Copyright (c) 2018 STMicroelectronics International N.V. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted, provided that the following conditions are met: - * - * 1. Redistribution of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific written permission. - * 4. This software, including modifications and/or derivative works of this - * software, must execute solely and exclusively on microcontroller or - * microprocessor devices manufactured by or for STMicroelectronics. - * 5. Redistribution and use of this software other than as permitted under - * this license is void and will automatically terminate your rights under - * this license. - * - * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A - * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY - * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT - * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" -#include "usbd_desc.h" -#include "usbd_conf.h" - -/* USER CODE BEGIN INCLUDE */ - -/* USER CODE END INCLUDE */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ - -/* USER CODE BEGIN PV */ -/* Private variables ---------------------------------------------------------*/ - -/* USER CODE END PV */ - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @addtogroup USBD_DESC - * @{ - */ - -/** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions - * @brief Private types. - * @{ - */ - -/* USER CODE BEGIN PRIVATE_TYPES */ - -/* USER CODE END PRIVATE_TYPES */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines - * @brief Private defines. - * @{ - */ - -#define USBD_VID 1155 -#define USBD_LANGID_STRING 1033 -#define USBD_MANUFACTURER_STRING "STMicroelectronics" -#define USBD_PID_FS 22336 -#define USBD_PRODUCT_STRING_FS "STM32 Virtual ComPort" -#define USBD_SERIALNUMBER_STRING_FS "00000000001A" -#define USBD_CONFIGURATION_STRING_FS "CDC Config" -#define USBD_INTERFACE_STRING_FS "CDC Interface" - -#define USB_SIZ_BOS_DESC 0x0C - -/* USER CODE BEGIN PRIVATE_DEFINES */ - -/* USER CODE END PRIVATE_DEFINES */ - -/** - * @} - */ - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros - * @brief Private macros. - * @{ - */ - -/* USER CODE BEGIN PRIVATE_MACRO */ - -/* USER CODE END PRIVATE_MACRO */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes - * @brief Private functions declaration. - * @{ - */ - -uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); - -#ifdef USB_SUPPORT_USER_STRING_DESC -uint8_t * USBD_FS_USRStringDesc(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); -#endif /* USB_SUPPORT_USER_STRING_DESC */ - -#if (USBD_LPM_ENABLED == 1) -uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -#endif /* (USBD_LPM_ENABLED == 1) */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables - * @brief Private variables. - * @{ - */ - -USBD_DescriptorsTypeDef FS_Desc = -{ - USBD_FS_DeviceDescriptor -, USBD_FS_LangIDStrDescriptor -, USBD_FS_ManufacturerStrDescriptor -, USBD_FS_ProductStrDescriptor -, USBD_FS_SerialStrDescriptor -, USBD_FS_ConfigStrDescriptor -, USBD_FS_InterfaceStrDescriptor -#if (USBD_LPM_ENABLED == 1) -, USBD_FS_USR_BOSDescriptor -#endif /* (USBD_LPM_ENABLED == 1) */ -}; - -#if defined ( __ICCARM__ ) /* IAR Compiler */ - #pragma data_alignment=4 -#endif /* defined ( __ICCARM__ ) */ -/** USB standard device descriptor. */ -__ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = -{ - 0x12, /*bLength */ - USB_DESC_TYPE_DEVICE, /*bDescriptorType*/ -#if (USBD_LPM_ENABLED == 1) - 0x01, /*bcdUSB */ /* changed to USB version 2.01 - in order to support LPM L1 suspend - resume test of USBCV3.0*/ -#else - 0x00, /*bcdUSB */ -#endif /* (USBD_LPM_ENABLED == 1) */ - 0x02, - 0x02, /*bDeviceClass*/ - 0x02, /*bDeviceSubClass*/ - 0x00, /*bDeviceProtocol*/ - USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ - LOBYTE(USBD_VID), /*idVendor*/ - HIBYTE(USBD_VID), /*idVendor*/ - LOBYTE(USBD_PID_FS), /*idProduct*/ - HIBYTE(USBD_PID_FS), /*idProduct*/ - 0x00, /*bcdDevice rel. 2.00*/ - 0x02, - USBD_IDX_MFC_STR, /*Index of manufacturer string*/ - USBD_IDX_PRODUCT_STR, /*Index of product string*/ - USBD_IDX_SERIAL_STR, /*Index of serial number string*/ - USBD_MAX_NUM_CONFIGURATION /*bNumConfigurations*/ -}; - -/* USB_DeviceDescriptor */ -/** BOS descriptor. */ -#if (USBD_LPM_ENABLED == 1) -#if defined ( __ICCARM__ ) /* IAR Compiler */ - #pragma data_alignment=4 -#endif /* defined ( __ICCARM__ ) */ -__ALIGN_BEGIN uint8_t USBD_FS_BOSDesc[USB_SIZ_BOS_DESC] __ALIGN_END = -{ - 0x5, - USB_DESC_TYPE_BOS, - 0xC, - 0x0, - 0x1, /* 1 device capability*/ - /* device capability*/ - 0x7, - USB_DEVICE_CAPABITY_TYPE, - 0x2, - 0x2, /* LPM capability bit set*/ - 0x0, - 0x0, - 0x0 -}; -#endif /* (USBD_LPM_ENABLED == 1) */ - -/** - * @} - */ - -/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables - * @brief Private variables. - * @{ - */ - -#if defined ( __ICCARM__ ) /* IAR Compiler */ - #pragma data_alignment=4 -#endif /* defined ( __ICCARM__ ) */ - -/** USB lang indentifier descriptor. */ -__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = -{ - USB_LEN_LANGID_STR_DESC, - USB_DESC_TYPE_STRING, - LOBYTE(USBD_LANGID_STRING), - HIBYTE(USBD_LANGID_STRING) -}; - -#if defined ( __ICCARM__ ) /* IAR Compiler */ - #pragma data_alignment=4 -#endif /* defined ( __ICCARM__ ) */ -/* Internal string descriptor. */ -__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END; - -/** - * @} - */ - -/** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions - * @brief Private functions. - * @{ - */ - -/** - * @brief Return the device descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - *length = sizeof(USBD_FS_DeviceDesc); - return USBD_FS_DeviceDesc; -} - -/** - * @brief Return the LangID string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - *length = sizeof(USBD_LangIDDesc); - return USBD_LangIDDesc; -} - -/** - * @brief Return the product string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - if(speed == 0) - { - USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); - } - else - { - USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - -/** - * @brief Return the manufacturer string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); - return USBD_StrDesc; -} - -/** - * @brief Return the serial number string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - if(speed == USBD_SPEED_HIGH) - { - USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); - } - else - { - USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - -/** - * @brief Return the configuration string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - if(speed == USBD_SPEED_HIGH) - { - USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); - } - else - { - USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - -/** - * @brief Return the interface string descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - if(speed == 0) - { - USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); - } - else - { - USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - -#if (USBD_LPM_ENABLED == 1) -/** - * @brief Return the BOS descriptor - * @param speed : Current device speed - * @param length : Pointer to data length variable - * @retval Pointer to descriptor buffer - */ -uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) -{ - *length = sizeof(USBD_FS_BOSDesc); - return (uint8_t*)USBD_FS_BOSDesc; -} -#endif /* (USBD_LPM_ENABLED == 1) */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/mx.scratch b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/mx.scratch deleted file mode 100644 index a4d6e0b19..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/mx.scratch +++ /dev/null @@ -1,91 +0,0 @@ - - -D:\VS\brianTPM\Samples\Nucleo-TPM\L4A6RG\\Nucleo-L4A6RG -C -..\Drivers\CMSIS -C:\Users\Stefanth\STM32Cube\Repository\STM32Cube_FW_L4_V1.11.0\Drivers\CMSIS -TrueSTUDIO -0 - - - - - - - - - - - - - - - - - Nucleo-L4A6RG - STM32L4A6RGTx - 0x200 - 0x10000 - - custom - - true - swd - - 1 - - - - - - - - - - - - __weak=__attribute__((weak)) - __packed=__attribute__((__packed__)) - - - - - - - USE_FULL_LL_DRIVER - MBEDTLS_CONFIG_FILE="mbedtls_config.h" - - - - - ..\Inc - ..\Drivers\STM32L4xx_HAL_Driver\Inc - ..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy - ..\Middlewares\ST\STM32_USB_Device_Library\Core\Inc - ..\Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Inc - ..\Drivers\CMSIS\Device\ST\STM32L4xx\Include - ..\Drivers\CMSIS\Include - - - - - - true - false - - - - Inc - - - Src - - - Drivers - - - Middlewares - - - - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/startup/startup_stm32l4a6xx.s b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/startup/startup_stm32l4a6xx.s deleted file mode 100644 index 15a7f5a31..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/startup/startup_stm32l4a6xx.s +++ /dev/null @@ -1,563 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32l4a6xx.s - * @author MCD Application Team - * @brief STM32L4A6xx devices vector table GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address, - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF1E0F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* Atollic update: set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - -LoopForever: - b LoopForever - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex-M4. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_PVM_IRQHandler - .word TAMP_STAMP_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_2_IRQHandler - .word CAN1_TX_IRQHandler - .word CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_SCE_IRQHandler - .word EXTI9_5_IRQHandler - .word TIM1_BRK_TIM15_IRQHandler - .word TIM1_UP_TIM16_IRQHandler - .word TIM1_TRG_COM_TIM17_IRQHandler - .word TIM1_CC_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word DFSDM1_FLT3_IRQHandler - .word TIM8_BRK_IRQHandler - .word TIM8_UP_IRQHandler - .word TIM8_TRG_COM_IRQHandler - .word TIM8_CC_IRQHandler - .word ADC3_IRQHandler - .word FMC_IRQHandler - .word SDMMC1_IRQHandler - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word TIM6_DAC_IRQHandler - .word TIM7_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_IRQHandler - .word DMA2_Channel5_IRQHandler - .word DFSDM1_FLT0_IRQHandler - .word DFSDM1_FLT1_IRQHandler - .word DFSDM1_FLT2_IRQHandler - .word COMP_IRQHandler - .word LPTIM1_IRQHandler - .word LPTIM2_IRQHandler - .word OTG_FS_IRQHandler - .word DMA2_Channel6_IRQHandler - .word DMA2_Channel7_IRQHandler - .word LPUART1_IRQHandler - .word QUADSPI_IRQHandler - .word I2C3_EV_IRQHandler - .word I2C3_ER_IRQHandler - .word SAI1_IRQHandler - .word SAI2_IRQHandler - .word SWPMI1_IRQHandler - .word TSC_IRQHandler - .word LCD_IRQHandler - .word AES_IRQHandler - .word HASH_RNG_IRQHandler - .word FPU_IRQHandler - .word CRS_IRQHandler - .word I2C4_EV_IRQHandler - .word I2C4_ER_IRQHandler - .word DCMI_IRQHandler - .word CAN2_TX_IRQHandler - .word CAN2_RX0_IRQHandler - .word CAN2_RX1_IRQHandler - .word CAN2_SCE_IRQHandler - .word DMA2D_IRQHandler - - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_PVM_IRQHandler - .thumb_set PVD_PVM_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_2_IRQHandler - .thumb_set ADC1_2_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM15_IRQHandler - .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM16_IRQHandler - .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM17_IRQHandler - .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak DFSDM1_FLT3_IRQHandler - .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler - - .weak TIM8_BRK_IRQHandler - .thumb_set TIM8_BRK_IRQHandler,Default_Handler - - .weak TIM8_UP_IRQHandler - .thumb_set TIM8_UP_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_IRQHandler - .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak ADC3_IRQHandler - .thumb_set ADC3_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak SDMMC1_IRQHandler - .thumb_set SDMMC1_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_IRQHandler - .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - - .weak DFSDM1_FLT0_IRQHandler - .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler - - .weak DFSDM1_FLT1_IRQHandler - .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler - - .weak DFSDM1_FLT2_IRQHandler - .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler - - .weak COMP_IRQHandler - .thumb_set COMP_IRQHandler,Default_Handler - - .weak LPTIM1_IRQHandler - .thumb_set LPTIM1_IRQHandler,Default_Handler - - .weak LPTIM2_IRQHandler - .thumb_set LPTIM2_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Channel6_IRQHandler - .thumb_set DMA2_Channel6_IRQHandler,Default_Handler - - .weak DMA2_Channel7_IRQHandler - .thumb_set DMA2_Channel7_IRQHandler,Default_Handler - - .weak LPUART1_IRQHandler - .thumb_set LPUART1_IRQHandler,Default_Handler - - .weak QUADSPI_IRQHandler - .thumb_set QUADSPI_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak SAI1_IRQHandler - .thumb_set SAI1_IRQHandler,Default_Handler - - .weak SAI2_IRQHandler - .thumb_set SAI2_IRQHandler,Default_Handler - - .weak SWPMI1_IRQHandler - .thumb_set SWPMI1_IRQHandler,Default_Handler - - .weak TSC_IRQHandler - .thumb_set TSC_IRQHandler,Default_Handler - - .weak LCD_IRQHandler - .thumb_set LCD_IRQHandler,Default_Handler - - .weak AES_IRQHandler - .thumb_set AES_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak CRS_IRQHandler - .thumb_set CRS_IRQHandler,Default_Handler - - .weak I2C4_EV_IRQHandler - .thumb_set I2C4_EV_IRQHandler,Default_Handler - - .weak I2C4_ER_IRQHandler - .thumb_set I2C4_ER_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak DMA2D_IRQHandler - .thumb_set DMA2D_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/include/PlatformData.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/include/PlatformData.h deleted file mode 100644 index 4fe76c855..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/include/PlatformData.h +++ /dev/null @@ -1,126 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -// This file contains the instance data for the Platform module. It is collected -// in this file so that the state of the module is easier to manage. - -#ifndef _PLATFORM_DATA_H_ -#define _PLATFORM_DATA_H_ - - -#include "Implementation.h" - -// From Cancel.c -// Cancel flag. It is initialized as FALSE, which indicate the command is not -// being canceled -extern int s_isCanceled; - -#include - -#ifndef HARDWARE_CLOCK -// This is the value returned the last time that the system clock was read. This -// is only relevant for a simulator or virtual TPM. -extern clock_t s_realTimePrevious; -// This is the rate adjusted value that is the equivalent of what would be read from -// a hardware register that produced rate adjusted time. -extern clock_t s_tpmTime; -#endif // HARDWARE_CLOCK - -// This value indicates that the timer was reset -extern BOOL s_timerReset; -// This value indicates that the timer was stopped. It causes a clock discontinuity. -extern BOOL s_timerStopped; - -// CLOCK_NOMINAL is the number of hardware ticks per mS. A value of 300000 means -// that the nominal clock rate used to drive the hardware clock is 30 MHz. The -// adjustment rates are used to determine the conversion of the hardware ticks to -// internal hardware clock value. In practice, we would expect that there woudl be -// a hardware register will accumulated mS. It would be incremented by the output -// of a pre-scaler. The pre-scaler would divide the ticks from the clock by some -// value that would compensate for the difference between clock time and real time. -// The code in Clock does the emulation of this function. -#define CLOCK_NOMINAL 30000 -// A 1% change in rate is 300 counts -#define CLOCK_ADJUST_COARSE 300 -// A 0.1% change in rate is 30 counts -#define CLOCK_ADJUST_MEDIUM 30 -// A minimum change in rate is 1 count -#define CLOCK_ADJUST_FINE 1 -// The clock tolerance is +/-15% (4500 counts) -// Allow some guard band (16.7%) -#define CLOCK_ADJUST_LIMIT 5000 - -// This variable records the time when _plat__TimerReset is called. This mechanism -// allow us to subtract the time when TPM is power off from the total -// time reported by clock() function -extern uint64_t s_initClock; - -// This variable records the timer adjustment factor. -extern unsigned int s_adjustRate; - -// From LocalityPlat.c -// Locality of current command -extern unsigned char s_locality; - -// From NVMem.c -// Choose if the NV memory should be backed by RAM or by file. -// If this macro is defined, then a file is used as NV. If it is not defined, -// then RAM is used to back NV memory. Comment out to use RAM. -#define FILE_BACKED_NV -#if defined FILE_BACKED_NV -#include -// A file to emulate NV storage -extern FILE* s_NVFile; -#endif -extern unsigned char s_NV[NV_MEMORY_SIZE]; -extern BOOL s_NvIsAvailable; -extern BOOL s_NV_unrecoverable; -extern BOOL s_NV_recoverable; - - -// From PPPlat.c -// Physical presence. It is initialized to FALSE -extern BOOL s_physicalPresence; - -// From Power -extern BOOL s_powerLost; - -// From Entropy.c -extern uint32_t lastEntropy; - -extern int firstValue; - - -#endif // _PLATFORM_DATA_H_ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/include/prototypes/Platform_fp.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/include/prototypes/Platform_fp.h deleted file mode 100644 index 8f514ba3b..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/include/prototypes/Platform_fp.h +++ /dev/null @@ -1,443 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*(Auto) - Automatically Generated by TpmPrototypes version 2.2 February 10, 2016 - Date: Mar 23, 2017 Time: 03:31:52 PM -*/ - -#ifndef _PLATFORM_FP_H_ -#define _PLATFORM_FP_H_ - -//** From Cancel.c - - - -//***_plat__IsCanceled() -// Check if the cancel flag is set -// return type: BOOL -// TRUE(1) if cancel flag is set -// FALSE(0) if cancel flag is not set -LIB_EXPORT int -_plat__IsCanceled( - void - ); - -// Set cancel flag. -LIB_EXPORT void -_plat__SetCancel( - void - ); - -//***_plat__ClearCancel() -// Clear cancel flag -LIB_EXPORT void -_plat__ClearCancel( - void - ); - - -//** From Clock.c - - - -//***_plat__TimerReset() -// This function sets current system clock time as t0 for counting TPM time. -// This function is called at a power on event to reset the clock. When the clock -// is reset, the indication that the clock was stopped is also set. -LIB_EXPORT void -_plat__TimerReset( - void - ); - -//*** _plat__TimerRestart() -// This function should be called in order to simulate the restart of the timer -// should it be stopped while power is still applied. -LIB_EXPORT void -_plat__TimerRestart( - void - ); - -//***_plat__TimerRead() -// This function provides access to the tick timer of the platform. The TPM code -// uses this value to drive the TPM Clock. -// -// The tick timer is supposed to run when power is applied to the device. This timer -// should not be reset by time events including _TPM_Init. It should only be reset -// when TPM power is re-applied. -// -// If the TPM is run in a protected environment, that environment may provide the -// tick time to the TPM as long as the time provided by the environment is not -// allowed to go backwards. If the time provided by the system can go backwards -// during a power discontinuity, then the _plat__Signal_PowerOn should call -// _plat__TimerReset(). -// -// The code in this function should be replaced by a read of a hardware tick timer. -LIB_EXPORT uint64_t -_plat__TimerRead( - void - ); - -//*** _plat__TimerWasReset() -// This function is used to interrogate the flag indicating if the tick timer has -// been reset. -// -// If the resetFlag parameter is SET, then the flag will be CLEAR before the -// function returns. -LIB_EXPORT BOOL -_plat__TimerWasReset( - void - ); - -//*** _plat__TimerWasStopped() -// This function is used to interrogate the flag indicating if the tick timer has -// been stopped. If so, this is typically a reason to roll the nonce. -// -// This function will CLEAR the s_timerStopped flag before returning. This provides -// functionality that is similar to status register that is cleared when read. This -// is the model used here because it is the one that has the most impact on the TPM -// code as the flag can only be accessed by one entity in the TPM. Any other -// implementation of the hardware can be made to look like a read-once register. -LIB_EXPORT BOOL -_plat__TimerWasStopped( - void - ); - -//***_plat__ClockAdjustRate() -// Adjust the clock rate -LIB_EXPORT void -_plat__ClockAdjustRate( - int adjust // IN: the adjust number. It could be positive - // or negative - ); - - -//** From Entropy.c - - -// return type: int32_t -// < 0 hardware failure of the entropy generator, this is sticky -// >= 0 the returned amount of entropy (bytes) -// -LIB_EXPORT int32_t -_plat__GetEntropy( - unsigned char *entropy, // output buffer - uint32_t amount // amount requested - ); - - -//** From LocalityPlat.c - - - -//***_plat__LocalityGet() -// Get the most recent command locality in locality value form. -// This is an integer value for locality and not a locality structure -// The locality can be 0-4 or 32-255. 5-31 is not allowed. -LIB_EXPORT unsigned char -_plat__LocalityGet( - void - ); - -//***_plat__LocalitySet() -// Set the most recent command locality in locality value form -LIB_EXPORT void -_plat__LocalitySet( - unsigned char locality - ); - - -//** From NVMem.c - - - -//*** _plat__NvErrors() -// This function is used by the simulator to set the error flags in the NV -// subsystem to simulate an error in the NV loading process -LIB_EXPORT void -_plat__NvErrors( - int recoverable, - int unrecoverable - ); - -//***_plat__NVEnable() -// Enable NV memory. -// -// This version just pulls in data from a file. In a real TPM, with NV on chip, -// this function would verify the integrity of the saved context. If the NV -// memory was not on chip but was in something like RPMB, the NV state would be -// read in, decrypted and integrity checked. -// -// The recovery from an integrity failure depends on where the error occurred. It -// it was in the state that is discarded by TPM Reset, then the error is -// recoverable if the TPM is reset. Otherwise, the TPM must go into failure mode. -// return type: int -// 0 if success -// > 0 if receive recoverable error -// <0 if unrecoverable error -LIB_EXPORT int -_plat__NVEnable( - void *platParameter // IN: platform specific parameters - ); - -//***_plat__NVDisable() -// Disable NV memory -LIB_EXPORT void -_plat__NVDisable( - void - ); - -//***_plat__IsNvAvailable() -// Check if NV is available -// return type: int -// 0 NV is available -// 1 NV is not available due to write failure -// 2 NV is not available due to rate limit -LIB_EXPORT int -_plat__IsNvAvailable( - void - ); - -//***_plat__NvMemoryRead() -// Function: Read a chunk of NV memory -LIB_EXPORT void -_plat__NvMemoryRead( - unsigned int startOffset, // IN: read start - unsigned int size, // IN: size of bytes to read - void *data // OUT: data buffer - ); - -//*** _plat__NvIsDifferent() -// This function checks to see if the NV is different from the test value. This is -// so that NV will not be written if it has not changed. -// return value: int -// TRUE(1) the NV location is different from the test value -// FALSE(0) the NV location is the same as the test value -LIB_EXPORT int -_plat__NvIsDifferent( - unsigned int startOffset, // IN: read start - unsigned int size, // IN: size of bytes to read - void *data // IN: data buffer - ); - -//***_plat__NvMemoryWrite() -// This function is used to update NV memory. The "write" is to a memory copy of -// NV. At the end of the current command, any changes are written to -// the actual NV memory. -// NOTE: A useful optimization would be for this code to compare the current -// contents of NV with the local copy and note the blocks that have changed. Then -// only write those blocks when _plat__NvCommit() is called. -LIB_EXPORT void -_plat__NvMemoryWrite( - unsigned int startOffset, // IN: write start - unsigned int size, // IN: size of bytes to write - void *data // OUT: data buffer - ); - -//***_plat__NvMemoryClear() -// Function is used to set a range of NV memory bytes to an implementation-dependent -// value. The value represents the erase state of the memory. -LIB_EXPORT void -_plat__NvMemoryClear( - unsigned int start, // IN: clear start - unsigned int size // IN: number of bytes to clear - ); - -//***_plat__NvMemoryMove() -// Function: Move a chunk of NV memory from source to destination -// This function should ensure that if there overlap, the original data is -// copied before it is written -LIB_EXPORT void -_plat__NvMemoryMove( - unsigned int sourceOffset, // IN: source offset - unsigned int destOffset, // IN: destination offset - unsigned int size // IN: size of data being moved - ); - -//***_plat__NvCommit() -// Update NV chip -// return type: int -// 0 NV write success -// non-0 NV write fail -LIB_EXPORT int -_plat__NvCommit( - void - ); - -//***_plat__SetNvAvail() -// Set the current NV state to available. This function is for testing purpose -// only. It is not part of the platform NV logic -LIB_EXPORT void -_plat__SetNvAvail( - void - ); - -//***_plat__ClearNvAvail() -// Set the current NV state to unavailable. This function is for testing purpose -// only. It is not part of the platform NV logic -LIB_EXPORT void -_plat__ClearNvAvail( - void - ); - - -//** From PlatformData.c - - - - -//** From PowerPlat.c - - - -//***_plat__Signal_PowerOn() -// Signal platform power on -LIB_EXPORT int -_plat__Signal_PowerOn( - void - ); - -//*** _plat__WasPowerLost() -// Test whether power was lost before a _TPM_Init. -// -// This function will clear the "hardware" indication of power loss before return. -// This means that there can only be one spot in the TPM code where this value -// gets read. This method is used here as it is the most difficult to manage in the -// TPM code and, if the hardware actually works this way, it is hard to make it -// look like anything else. So, the burden is placed on the TPM code rather than the -// platform code -// return type: int -// TRUE(1) power was lost -// FALSE(0) power was not lost -LIB_EXPORT int -_plat__WasPowerLost( - void - ); - -//*** _plat_Signal_Reset() -// This a TPM reset without a power loss. -LIB_EXPORT int -_plat__Signal_Reset( - void - ); - -//***_plat__Signal_PowerOff() -// Signal platform power off -LIB_EXPORT void -_plat__Signal_PowerOff( - void - ); - - -//** From PPPlat.c - - - -//***_plat__PhysicalPresenceAsserted() -// Check if physical presence is signaled -// return type: int -// TRUE(1) if physical presence is signaled -// FALSE(0) if physical presence is not signaled -LIB_EXPORT int -_plat__PhysicalPresenceAsserted( - void - ); - -//***_plat__Signal_PhysicalPresenceOn() -// Signal physical presence on -LIB_EXPORT void -_plat__Signal_PhysicalPresenceOn( - void - ); - -//***_plat__Signal_PhysicalPresenceOff() -// Signal physical presence off -LIB_EXPORT void -_plat__Signal_PhysicalPresenceOff( - void - ); - - -//** From RunCommand.c - - - -//***_plat__RunCommand() -// This version of RunCommand will set up a jum_buf and call ExecuteCommand(). If -// the command executes without failing, it will return and RunCommand will return. -// If there is a failure in the command, then _plat__Fail() is called and it will -// longjump back to RunCommand which will call ExecuteCommand again. However, this -// time, the TPM will be in failure mode so ExecuteCommand will simply build -// a failure response and return. -LIB_EXPORT void -_plat__RunCommand( - unsigned int requestSize, // IN: command buffer size - unsigned char *request, // IN: command buffer - unsigned int *responseSize, // IN/OUT: response buffer size - unsigned char **response // IN/OUT: response buffer - ); - -//***_plat__Fail() -// This is the platform depended failure exit for the TPM. -LIB_EXPORT NORETURN void -_plat__FailDetailed( - char * file, - int line, - const char * func - ); -#define _plat__Fail() _plat__FailDetailed(__FILE__, __LINE__, __FUNCTION__) - - -//** From Unique.c - - - -//** _plat__GetUnique() -// This function is used to access the platform-specific unique value. -// This function places the unique value in the provided buffer ('b') -// and returns the number of bytes transferred. The function will not -// copy more data than 'bSize'. -// NOTE: If a platform unique value has unequal distribution of uniqueness -// and 'bSize' is smaller than the size of the unique value, the 'bSize' -// portion with the most uniqueness should be returned. -LIB_EXPORT uint32_t -_plat__GetUnique( - uint32_t which, // authorities (0) or details - uint32_t bSize, // size of the buffer - unsigned char *b // output buffer - ); - - -#endif // _PLATFORM_FP_H_ diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/Cancel.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/Cancel.c deleted file mode 100644 index fb5d7e3dd..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/Cancel.c +++ /dev/null @@ -1,81 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//**Introduction -/* - This module simulates the cancel pins on the TPM. -*/ -//** Includes, Typedefs, Structures, and Defines -#include "PlatformData.h" -#include "Platform_fp.h" - -//** Functions - -//***_plat__IsCanceled() -// Check if the cancel flag is set -// return type: BOOL -// TRUE(1) if cancel flag is set -// FALSE(0) if cancel flag is not set -LIB_EXPORT int -_plat__IsCanceled( - void - ) -{ - // return cancel flag - return s_isCanceled; -} - -//***_plat__SetCancel() - -// Set cancel flag. -LIB_EXPORT void -_plat__SetCancel( - void - ) -{ - s_isCanceled = TRUE; - return; -} - -//***_plat__ClearCancel() -// Clear cancel flag -LIB_EXPORT void -_plat__ClearCancel( - void - ) -{ - s_isCanceled = FALSE; - return; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/Clock.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/Clock.c deleted file mode 100644 index 95d267741..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/Clock.c +++ /dev/null @@ -1,246 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//** Introduction -// This file contains the routines that are used by the simulator to mimic -// a hardware clock on a TPM. - -// In this implementation, all the time values are measured in millisecond. -// However, the precision of the clock functions may be implementation dependent. - -//** Includes and Data Definitions -#include "PlatformData.h" -#include "Platform_fp.h" -#include "TpmFail_fp.h" -#include - -//** Simulator Functions -//*** Introduction -// This set of functions is intended to be called by the simulator environment in -// order to simulate hardware events. - -//***_plat__TimerReset() -// This function sets current system clock time as t0 for counting TPM time. -// This function is called at a power on event to reset the clock. When the clock -// is reset, the indication that the clock was stopped is also set. -LIB_EXPORT void -_plat__TimerReset( - void - ) -{ - s_realTimePrevious = clock(); - s_tpmTime = 0; - s_adjustRate = CLOCK_NOMINAL; - s_timerReset = TRUE; - s_timerStopped = TRUE; - return; -} - -//*** _plat__TimerRestart() -// This function should be called in order to simulate the restart of the timer -// should it be stopped while power is still applied. -LIB_EXPORT void -_plat__TimerRestart( - void - ) -{ - s_timerStopped = TRUE; - return; -} - - -//** Functions Used by TPM -//*** Introduction -// These functions are called by the TPM code. They should be replaced by -// appropriated hardware functions. - -//***_plat__TimerRead() -// This function provides access to the tick timer of the platform. The TPM code -// uses this value to drive the TPM Clock. -// -// The tick timer is supposed to run when power is applied to the device. This timer -// should not be reset by time events including _TPM_Init. It should only be reset -// when TPM power is re-applied. -// -// If the TPM is run in a protected environment, that environment may provide the -// tick time to the TPM as long as the time provided by the environment is not -// allowed to go backwards. If the time provided by the system can go backwards -// during a power discontinuity, then the _plat__Signal_PowerOn should call -// _plat__TimerReset(). -// -// The code in this function should be replaced by a read of a hardware tick timer. -LIB_EXPORT uint64_t -_plat__TimerRead( - void - ) -{ -#ifdef HARDWARE_CLOCK -#error "need a defintion for reading the hardware clock" - return HARDWARE_CLOCK -#else -#define BILLION 1000000000 -#define MILLION 1000000 -#define THOUSAND 1000 - clock_t timeDiff; - uint64_t adjusted; - - // Save the value previously read from the system clock - timeDiff = s_realTimePrevious; - // update with the current value of the system clock - s_realTimePrevious = clock(); - // In the place below when we "put back" the unused part of the timeDiff - // it is possible that we can put back more than we take out. That is, we could - // take out 1000 mSec, rate adjust it and put back 1001 mS. This means that - // on a subsequent call, time may not have caught up. Rather than trying - // to rate adjust this, just stop time. This only occurs in a simulation so - // time for more than one command being the same should not be an issue. - if(timeDiff >= s_realTimePrevious) - { - s_realTimePrevious = timeDiff; - return s_tpmTime; - } - // Compute the amount of time since the last call to the system clock - timeDiff = s_realTimePrevious - timeDiff; - - // Do the time rate adjustment and conversion from CLOCKS_PER_SEC to mSec - adjusted = (((uint64_t)timeDiff * (THOUSAND * CLOCK_NOMINAL)) - / ((uint64_t)s_adjustRate * CLOCKS_PER_SEC)); - - s_tpmTime += (clock_t)adjusted; - - // Might have some rounding error that would loose CLOCKS. See what is not - // being used. As mentioned above, this could result in putting back more than - // is taken out - adjusted = (adjusted * ((uint64_t)s_adjustRate * CLOCKS_PER_SEC)) - / (THOUSAND * CLOCK_NOMINAL); - - // If adjusted is not the same as timeDiff, then there is some rounding - // error that needs to be pushed back into the previous sample. - // NOTE: the following is so that the fact that everything is signed will not - // matter. - s_realTimePrevious = (clock_t)((int64_t)s_realTimePrevious - adjusted); - s_realTimePrevious += timeDiff; - -#ifdef DEBUGGING_TIME - // Put this in so that TPM time will pass much faster than real time when - // doing debug. - // A value of 1000 for DEBUG_TIME_MULTIPLER will make each ms into a second - // A good value might be 100 - return (s_tpmTime * DEBUG_TIME_MULTIPLIER); -#endif - return s_tpmTime; -#endif -} - - - -//*** _plat__TimerWasReset() -// This function is used to interrogate the flag indicating if the tick timer has -// been reset. -// -// If the resetFlag parameter is SET, then the flag will be CLEAR before the -// function returns. -LIB_EXPORT BOOL -_plat__TimerWasReset( - void - ) -{ - BOOL retVal = s_timerReset; - s_timerReset = FALSE; - return retVal; -} - -//*** _plat__TimerWasStopped() -// This function is used to interrogate the flag indicating if the tick timer has -// been stopped. If so, this is typically a reason to roll the nonce. -// -// This function will CLEAR the s_timerStopped flag before returning. This provides -// functionality that is similar to status register that is cleared when read. This -// is the model used here because it is the one that has the most impact on the TPM -// code as the flag can only be accessed by one entity in the TPM. Any other -// implementation of the hardware can be made to look like a read-once register. -LIB_EXPORT BOOL -_plat__TimerWasStopped( - void - ) -{ - BOOL retVal = s_timerStopped; - s_timerStopped = FALSE; - return retVal; -} - -//***_plat__ClockAdjustRate() -// Adjust the clock rate -LIB_EXPORT void -_plat__ClockAdjustRate( - int adjust // IN: the adjust number. It could be positive - // or negative - ) -{ - // We expect the caller should only use a fixed set of constant values to - // adjust the rate - switch(adjust) - { - case CLOCK_ADJUST_COARSE: - s_adjustRate += CLOCK_ADJUST_COARSE; - break; - case -CLOCK_ADJUST_COARSE: - s_adjustRate -= CLOCK_ADJUST_COARSE; - break; - case CLOCK_ADJUST_MEDIUM: - s_adjustRate += CLOCK_ADJUST_MEDIUM; - break; - case -CLOCK_ADJUST_MEDIUM: - s_adjustRate -= CLOCK_ADJUST_MEDIUM; - break; - case CLOCK_ADJUST_FINE: - s_adjustRate += CLOCK_ADJUST_FINE; - break; - case -CLOCK_ADJUST_FINE: - s_adjustRate -= CLOCK_ADJUST_FINE; - break; - default: - // ignore any other values; - break; - } - - if(s_adjustRate > (CLOCK_NOMINAL + CLOCK_ADJUST_LIMIT)) - s_adjustRate = CLOCK_NOMINAL + CLOCK_ADJUST_LIMIT; - if(s_adjustRate < (CLOCK_NOMINAL - CLOCK_ADJUST_LIMIT)) - s_adjustRate = CLOCK_NOMINAL - CLOCK_ADJUST_LIMIT; - - return; -} - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/Entropy.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/Entropy.c deleted file mode 100644 index 75c72b878..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/Entropy.c +++ /dev/null @@ -1,104 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//** Includes -#include "stm32l4xx_hal.h" -#include -#include -#include "PlatformData.h" -#include "Platform_fp.h" - -#define MIN(a,b) ((a) < (b) ? (a) : (b)) - -extern RNG_HandleTypeDef hrng; - -//** Local values -// This is the last 32-bits of hardware entropy produced. We have to check to -// see that two consecutive 32-bit values are not the same because -// (according to FIPS 140-2, annex C -// -// 1. If each call to a RNG produces blocks of n bits (where n > 15), the first -// n-bit block generated after power-up, initialization, or reset shall not be -// used, but shall be saved for comparison with the next n-bit block to be -// generated. Each subsequent generation of an n-bit block shall be compared with -// the previously generated block. The test shall fail if any two compared n-bit -// blocks are equal. -extern uint32_t lastEntropy; - -extern int firstValue; - -//** _plat__GetEntropy() -// This function is used to get available hardware entropy. In a hardware -// implementation of this function, there would be no call to the system -// to get entropy. -// If the caller does not ask for any entropy, then this is a startup indication -// and 'firstValue' should be reset. - -// return type: int32_t -// < 0 hardware failure of the entropy generator, this is sticky -// >= 0 the returned amount of entropy (bytes) -// -LIB_EXPORT int32_t -_plat__GetEntropy( - unsigned char *entropy, // output buffer - uint32_t amount // amount requested - ) -{ - uint32_t random32bit; - - if(amount == 0) - { - firstValue = 1; - return 0; - } - - if(firstValue) - { - firstValue = 0; - } - - for(uint32_t n = 0; n < amount; n += sizeof(random32bit)) - { - if((HAL_RNG_GenerateRandomNumber(&hrng, &random32bit) != HAL_OK) || - (~firstValue && (lastEntropy == random32bit))) - { - return -1; - } - memcpy(&entropy[n], &random32bit, MIN(sizeof(random32bit), amount - n)); - lastEntropy = random32bit; - } - - return (int32_t)amount; -} diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/LocalityPlat.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/LocalityPlat.c deleted file mode 100644 index a38bbb368..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/LocalityPlat.c +++ /dev/null @@ -1,66 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//** Includes -#include "PlatformData.h" -#include "Platform_fp.h" - -//** Functions - -//***_plat__LocalityGet() -// Get the most recent command locality in locality value form. -// This is an integer value for locality and not a locality structure -// The locality can be 0-4 or 32-255. 5-31 is not allowed. -LIB_EXPORT unsigned char -_plat__LocalityGet( - void - ) -{ - return s_locality; - -} - -//***_plat__LocalitySet() -// Set the most recent command locality in locality value form -LIB_EXPORT void -_plat__LocalitySet( - unsigned char locality - ) -{ - if(locality > 4 && locality < 32) - locality = 0; - s_locality = locality; - return; -} diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/NVMem.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/NVMem.c deleted file mode 100644 index 78b163678..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/NVMem.c +++ /dev/null @@ -1,558 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//**Introduction -/* - This file contains the NV read and write access methods. This implementation - uses RAM/file and does not manage the RAM/file as NV blocks. - The implementation may become more sophisticated over time. -*/ - -//** Includes -#include -#include -#include -#include -#include -#include "StmUtil.h" -#undef INLINE -#include "stm32l4xx_hal.h" -#include "PlatformData.h" -#include "Platform_fp.h" - -#define NVINTEGRITYMAGIC (0x44494E54) // TNID - TPM NV Integrity Data -typedef union -{ - struct - { - struct - { - uint32_t magic; - time_t created; - time_t lastWrite; - uint32_t writeCount; - uint8_t nvDigest[WC_SHA512_DIGEST_SIZE]; - } sig; - uint8_t nvSignature[WC_SHA512_DIGEST_SIZE]; - } s; - unsigned char b[0x800]; - unsigned int w[0x200]; -} IntegrityData_t, *pIntegrityData_t; - -__attribute__((section(".integrity"))) const IntegrityData_t nvIntegrity; -__attribute__((section(".nvfile"))) const uint8_t nvFile[NV_MEMORY_SIZE]; - -//**Functions -static BOOL NvHash2Data(uint8_t* data1, uint32_t data1Size, uint8_t* data2, uint32_t data2Size, uint8_t* digest) -{ - wc_Sha512 hash; - if(wc_InitSha512(&hash)) - { - dbgPrint("ERROR wc_InitSha512() failed.\r\n"); - return FALSE; - } - else if(data1 && (data1Size > 0) && wc_Sha512Update(&hash, data1, data1Size)) - { - dbgPrint("ERROR wc_Sha512Update() failed.\r\n"); - return FALSE; - } - else if(data2 && (data2Size > 0) && wc_Sha512Update(&hash, data2, data2Size)) - { - dbgPrint("ERROR wc_Sha512Update() failed.\r\n"); - return FALSE; - } - else if(wc_Sha512Final(&hash, (byte*)digest)) - { - dbgPrint("ERROR wc_Sha512Final failed.\r\n"); - return FALSE; - } - wc_Sha512Free(&hash); - return TRUE; -} - -static BOOL NvErasePages(void* dest, uint32_t size) -{ - BOOL result = TRUE; - uint32_t pageError = 0; - FLASH_EraseInitTypeDef eraseInfo = {FLASH_TYPEERASE_PAGES, - FLASH_BANK_1, - ((uint32_t)dest - 0x08000000) / 0x800, - (size + 0x7ff) / 0x800}; - - // Open the memory protection - for(uint32_t m = 0; m < 10; m++) - { - if((result = (HAL_FLASH_Unlock() == HAL_OK)) != FALSE) - { - break; - } - dbgPrint("WARNING HAL_FLASH_Unlock() retry %u.\r\n", (unsigned int)m); - // Bring the flash subsystem into a defined state. - HAL_FLASH_Lock(); - HAL_Delay(1); - } - if(!result) - { - dbgPrint("ERROR HAL_FLASH_Unlock() failed.\r\n"); - goto Cleanup; - } - - // Erase the necessary pages - for(uint32_t m = 0; m < 10; m++) - { - if((result = ((HAL_FLASHEx_Erase(&eraseInfo, &pageError) == HAL_OK) && (pageError == 0xffffffff)))) - { - break; - } - dbgPrint("WARNING HAL_FLASHEx_Erase() retry %u.\r\n", (unsigned int)m); - } - if(!result) - { - dbgPrint("ERROR HAL_FLASHEx_Erase() failed.\r\n"); - goto Cleanup; - } - -Cleanup: - HAL_FLASH_Lock(); - return result; -} - -static BOOL NvFlashPages(void* dest, void* src, uint32_t size) -{ - BOOL result = TRUE; - - // Parameter check - if(!(result = ((((uint32_t)src % sizeof(uint32_t)) == 0)))) - { - goto Cleanup; - } - - // Erase the required area - if(!(result = NvErasePages(dest, size))) - { - goto Cleanup; - } - - // Open the memory protection - if(!(result = (HAL_FLASH_Unlock() == HAL_OK))) - { - goto Cleanup; - } - - // Flash the src buffer 8 byte at a time and verify - for(uint32_t n = 0; n < ((size + sizeof(uint64_t) - 1) / sizeof(uint64_t)); n++) - { - result = FALSE; - for(uint32_t m = 0; m < 10; m++) - { - uint32_t progPtr = (uint32_t)&(((uint64_t*)dest)[n]); - uint64_t progData = ((uint64_t*)src)[n]; - if((progData == *((uint64_t*)progPtr)) || - ((result = (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, progPtr, progData) == HAL_OK)) && - (progData == *((uint64_t*)progPtr)))) - { - result = TRUE; - break; - } - dbgPrint("WARNING HAL_FLASH_Program() retry %u.\r\n", (unsigned int)m); - } - if(result == FALSE) - { - dbgPrint("ERROR HAL_FLASH_Program() failed.\r\n"); - goto Cleanup; - } - } - -Cleanup: - HAL_FLASH_Lock(); - return result; -} - -char* NvMakeTimeStamp(time_t time, char* nvTimeStamp, uint32_t size) -{ - struct tm* timeInfo = NULL; - timeInfo = gmtime(&time); - snprintf(nvTimeStamp, size, "%04d.%02d.%02d-%02d:%02d:%02dGMT", - timeInfo->tm_year + 1900, - timeInfo->tm_mon + 1, - timeInfo->tm_mday, - timeInfo->tm_hour, - timeInfo->tm_min, - timeInfo->tm_sec); - return nvTimeStamp; -} -//*** _plat__NvErrors() -// This function is used by the simulator to set the error flags in the NV -// subsystem to simulate an error in the NV loading process -//LIB_EXPORT void -//_plat__NvErrors( -// int recoverable, -// int unrecoverable -// ) -//{ -// s_NV_unrecoverable = unrecoverable; -// s_NV_recoverable = recoverable; -//} - -//***_plat__NVEnable() -// Enable NV memory. -// -// This version just pulls in data from a file. In a real TPM, with NV on chip, -// this function would verify the integrity of the saved context. If the NV -// memory was not on chip but was in something like RPMB, the NV state would be -// read in, decrypted and integrity checked. -// -// The recovery from an integrity failure depends on where the error occurred. It -// it was in the state that is discarded by TPM Reset, then the error is -// recoverable if the TPM is reset. Otherwise, the TPM must go into failure mode. -// return type: int -// 0 if success -// > 0 if receive recoverable error -// <0 if unrecoverable error -LIB_EXPORT int -_plat__NVEnable( - void *platParameter // IN: platform specific parameters - ) -{ - BOOL result = TRUE; - uint8_t tpmUnique[WC_SHA512_DIGEST_SIZE]; - uint8_t tpmUniqueSize = 0; - tpmUniqueSize = _plat__GetUnique(0, sizeof(tpmUnique), tpmUnique); - - // Start assuming everything is OK - s_NV_unrecoverable = FALSE; - s_NV_recoverable = FALSE; - memcpy(s_NV, nvFile, sizeof(s_NV)); - - // Perform integrity verification - if((nvIntegrity.s.sig.magic != NVINTEGRITYMAGIC) || (platParameter)) - { - // Initialize NV - IntegrityData_t newIntegrity = {0}; - - if((result = NvErasePages((uint8_t*)&nvIntegrity, sizeof(nvIntegrity))) == FALSE) - { - dbgPrint("ERROR NvErasePages(nvIntegrity) failed.\r\n"); - s_NV_unrecoverable = TRUE; - goto Cleanup; - } - if((result = NvErasePages((uint8_t*)nvFile, sizeof(nvFile))) == FALSE) - { - dbgPrint("ERROR NvErasePages(nvFile) failed.\r\n"); - s_NV_unrecoverable = TRUE; - goto Cleanup; - } - - newIntegrity.s.sig.magic = NVINTEGRITYMAGIC; - newIntegrity.s.sig.created = time(NULL); - if((result = NvHash2Data((uint8_t*)nvFile, sizeof(nvFile), NULL, 0, newIntegrity.s.sig.nvDigest)) == FALSE) - { - dbgPrint("WARNING NvHash2Data(nvFile) failed.\r\n"); - s_NV_unrecoverable = TRUE; - goto Cleanup; - } - if((result = NvHash2Data(tpmUnique, tpmUniqueSize, (uint8_t*)&newIntegrity.s.sig, sizeof(newIntegrity.s.sig), newIntegrity.s.nvSignature)) == FALSE) - { - dbgPrint("WARNING NvHash2Data(tpmUnique, newIntegrity) failed.\r\n"); - s_NV_unrecoverable = TRUE; - goto Cleanup; - } - if((result = NvFlashPages((uint8_t*)&nvIntegrity, (uint8_t*)&newIntegrity, sizeof(newIntegrity))) == FALSE) - { - dbgPrint("ERROR NvFlashPages(nvIntegrity) failed.\r\n"); - s_NV_unrecoverable = TRUE; - goto Cleanup; - } - dbgPrint("Initialized %dkb NVFile.\r\n", sizeof(nvFile)/1024); - memcpy(s_NV, nvFile, sizeof(s_NV)); - s_NV_recoverable = TRUE; - } - else - { - uint8_t nvDigest[WC_SHA512_DIGEST_SIZE]; - if((result = NvHash2Data(tpmUnique, tpmUniqueSize, (uint8_t*)&nvIntegrity.s.sig, sizeof(nvIntegrity.s.sig), nvDigest)) == FALSE) - { - dbgPrint("WARNING NvHash2Data(tpmUnique, nvIntegrity) failed.\r\n"); - s_NV_unrecoverable = TRUE; - goto Cleanup; - } - if(memcmp(nvDigest, nvIntegrity.s.nvSignature, sizeof(nvDigest))) - { - dbgPrint("WARNING NV signature invalid.\r\n"); - s_NV_unrecoverable = TRUE; - goto Cleanup; - } - if((result = NvHash2Data((uint8_t*)nvFile, sizeof(nvFile), NULL, 0, nvDigest)) == FALSE) - { - dbgPrint("WARNING NvHash2Data(nvFile) filed.\r\n"); - s_NV_unrecoverable = TRUE; - goto Cleanup; - } - if(memcmp(nvDigest, nvIntegrity.s.sig.nvDigest, sizeof(nvDigest))) - { - dbgPrint("WARNING NV integrity measurement invalid.\r\n"); - s_NV_unrecoverable = TRUE; - goto Cleanup; - } - } - char created[50]; - char written[50]; - dbgPrint("NVFile loaded (%dkb, %s created, %d writes, %s last)\r\n", - sizeof(nvFile)/1024, - NvMakeTimeStamp(nvIntegrity.s.sig.created, created, sizeof(created)), - (int)nvIntegrity.s.sig.writeCount, - (nvIntegrity.s.sig.lastWrite) ? NvMakeTimeStamp(nvIntegrity.s.sig.lastWrite, written, sizeof(written)) : "NEVER"); - -Cleanup: - HAL_FLASH_Lock(); - if(s_NV_unrecoverable) - return -1; - return s_NV_recoverable; -} - -//***_plat__NVDisable() -// Disable NV memory -LIB_EXPORT void -_plat__NVDisable( - void - ) -{ - return; -} - -//***_plat__IsNvAvailable() -// Check if NV is available -// return type: int -// 0 NV is available -// 1 NV is not available due to write failure -// 2 NV is not available due to rate limit -LIB_EXPORT int -_plat__IsNvAvailable( - void - ) -{ - // NV is not available if the TPM is in failure mode - if(!s_NvIsAvailable) - return 1; - - return 0; -} - -//***_plat__NvMemoryRead() -// Function: Read a chunk of NV memory -LIB_EXPORT void -_plat__NvMemoryRead( - unsigned int startOffset, // IN: read start - unsigned int size, // IN: size of bytes to read - void *data // OUT: data buffer - ) -{ - assert(startOffset + size <= NV_MEMORY_SIZE); - - // Copy data from RAM - memcpy(data, &s_NV[startOffset], size); - return; -} - -//*** _plat__NvIsDifferent() -// This function checks to see if the NV is different from the test value. This is -// so that NV will not be written if it has not changed. -// return value: int -// TRUE(1) the NV location is different from the test value -// FALSE(0) the NV location is the same as the test value -LIB_EXPORT int -_plat__NvIsDifferent( - unsigned int startOffset, // IN: read start - unsigned int size, // IN: size of bytes to read - void *data // IN: data buffer - ) -{ - return (memcmp(&s_NV[startOffset], data, size) != 0); -} - -//***_plat__NvMemoryWrite() -// This function is used to update NV memory. The "write" is to a memory copy of -// NV. At the end of the current command, any changes are written to -// the actual NV memory. -// NOTE: A useful optimization would be for this code to compare the current -// contents of NV with the local copy and note the blocks that have changed. Then -// only write those blocks when _plat__NvCommit() is called. -LIB_EXPORT void -_plat__NvMemoryWrite( - unsigned int startOffset, // IN: write start - unsigned int size, // IN: size of bytes to write - void *data // OUT: data buffer - ) -{ - assert(startOffset + size <= NV_MEMORY_SIZE); - - // Copy the data to the NV image - memcpy(&s_NV[startOffset], data, size); -} - -//***_plat__NvMemoryClear() -// Function is used to set a range of NV memory bytes to an implementation-dependent -// value. The value represents the erase state of the memory. -LIB_EXPORT void -_plat__NvMemoryClear( - unsigned int start, // IN: clear start - unsigned int size // IN: number of bytes to clear - ) -{ - assert(start + size <= NV_MEMORY_SIZE); - - // In this implementation, assume that the errase value for NV is all 1s - memset(&s_NV[start], 0xff, size); -} - -//***_plat__NvMemoryMove() -// Function: Move a chunk of NV memory from source to destination -// This function should ensure that if there overlap, the original data is -// copied before it is written -LIB_EXPORT void -_plat__NvMemoryMove( - unsigned int sourceOffset, // IN: source offset - unsigned int destOffset, // IN: destination offset - unsigned int size // IN: size of data being moved - ) -{ - assert(sourceOffset + size <= NV_MEMORY_SIZE); - assert(destOffset + size <= NV_MEMORY_SIZE); - - // Move data in RAM - memmove(&s_NV[destOffset], &s_NV[sourceOffset], size); - - return; -} - -//***_plat__NvCommit() -// Update NV chip -// return type: int -// 0 NV write success -// non-0 NV write fail -LIB_EXPORT int -_plat__NvCommit( - void - ) -{ - BOOL result = TRUE; - char created[50]; - char written[50]; - IntegrityData_t newIntegrity = {0}; - uint8_t tpmUnique[WC_SHA512_DIGEST_SIZE]; - uint8_t tpmUniqueSize = 0; - - tpmUniqueSize = _plat__GetUnique(0, sizeof(tpmUnique), tpmUnique); - memcpy(&newIntegrity, &nvIntegrity, sizeof(newIntegrity)); - - if((result = NvHash2Data(s_NV, sizeof(s_NV), NULL, 0, newIntegrity.s.sig.nvDigest)) == FALSE) - { - dbgPrint("WARNING NvHash2Data(s_NV) failed.\r\n"); - result = FALSE; - goto Cleanup; - } - if((result = NvHash2Data(tpmUnique, tpmUniqueSize, (uint8_t*)&nvIntegrity.s.sig, sizeof(nvIntegrity.s.sig), newIntegrity.s.nvSignature)) == FALSE) - { - dbgPrint("WARNING NvHash2Data(tpmUnique, nvIntegrity) failed.\r\n"); - result = FALSE; - goto Cleanup; - } - - if((memcmp(newIntegrity.s.sig.nvDigest, nvIntegrity.s.sig.nvDigest, sizeof(newIntegrity.s.sig.nvDigest))) || - (memcmp(newIntegrity.s.nvSignature, nvIntegrity.s.nvSignature, sizeof(newIntegrity.s.nvSignature)))) - { - newIntegrity.s.sig.lastWrite = time(NULL); - newIntegrity.s.sig.writeCount++; - if((result = NvHash2Data(tpmUnique, tpmUniqueSize, (uint8_t*)&newIntegrity.s.sig, sizeof(newIntegrity.s.sig), newIntegrity.s.nvSignature)) == FALSE) - { - dbgPrint("WARNING NvHash2Data(tpmUnique, newIntegrity) failed.\r\n"); - result = FALSE; - goto Cleanup; - } - if((result = NvFlashPages((uint8_t*)nvFile, s_NV, sizeof(s_NV))) == FALSE) - { - dbgPrint("ERROR NvFlashPages(nvFile) failed.\r\n"); - result = FALSE; - goto Cleanup; - } - if((result = NvFlashPages((uint8_t*)&nvIntegrity, (uint8_t*)&newIntegrity, sizeof(newIntegrity))) == FALSE) - { - dbgPrint("ERROR NvFlashPages(nvIntegrity) failed.\r\n"); - result = FALSE; - goto Cleanup; - } - dbgPrint("NVFile written (%dkb, %s created, %d writes, %s last)\r\n", - sizeof(nvFile)/1024, - NvMakeTimeStamp(nvIntegrity.s.sig.created, created, sizeof(created)), - (int)nvIntegrity.s.sig.writeCount, - (nvIntegrity.s.sig.lastWrite) ? NvMakeTimeStamp(nvIntegrity.s.sig.lastWrite, written, sizeof(written)) : "NEVER"); - } - else - { - dbgPrint("NVFile unchanged (%dkb, %s created, %d writes, %s last)\r\n", - sizeof(nvFile)/1024, - NvMakeTimeStamp(nvIntegrity.s.sig.created, created, sizeof(created)), - (int)nvIntegrity.s.sig.writeCount, - (nvIntegrity.s.sig.lastWrite) ? NvMakeTimeStamp(nvIntegrity.s.sig.lastWrite, written, sizeof(written)) : "NEVER"); - } - - -Cleanup: - return (result != TRUE); -} - -//***_plat__SetNvAvail() -// Set the current NV state to available. This function is for testing purpose -// only. It is not part of the platform NV logic -LIB_EXPORT void -_plat__SetNvAvail( - void - ) -{ - s_NvIsAvailable = TRUE; - return; -} - -//***_plat__ClearNvAvail() -// Set the current NV state to unavailable. This function is for testing purpose -// only. It is not part of the platform NV logic -LIB_EXPORT void -_plat__ClearNvAvail( - void - ) -{ - s_NvIsAvailable = FALSE; - return; -} diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/PPPlat.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/PPPlat.c deleted file mode 100644 index 8e0b8a8a2..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/PPPlat.c +++ /dev/null @@ -1,81 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//** Description - -// This module simulates the physical present interface pins on the TPM. - -//** Includes -#include "PlatformData.h" -#include "Platform_fp.h" - -//** Functions - -//***_plat__PhysicalPresenceAsserted() -// Check if physical presence is signaled -// return type: int -// TRUE(1) if physical presence is signaled -// FALSE(0) if physical presence is not signaled -LIB_EXPORT int -_plat__PhysicalPresenceAsserted( - void - ) -{ - // Do not know how to check physical presence without real hardware. - // so always return TRUE; - return s_physicalPresence; -} - -//***_plat__Signal_PhysicalPresenceOn() -// Signal physical presence on -LIB_EXPORT void -_plat__Signal_PhysicalPresenceOn( - void - ) -{ - s_physicalPresence = TRUE; - return; -} - -//***_plat__Signal_PhysicalPresenceOff() -// Signal physical presence off -LIB_EXPORT void -_plat__Signal_PhysicalPresenceOff( - void - ) -{ - s_physicalPresence = FALSE; - return; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/PlatformData.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/PlatformData.c deleted file mode 100644 index e6092e6fd..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/PlatformData.c +++ /dev/null @@ -1,76 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//** Description -// This file will instance the TPM variables that are not stack allocated. The -// descriptions for these variables are in Global.h for this project. - -//** Includes -#include "Implementation.h" -#include "PlatformData.h" - -// From Cancel.c -BOOL s_isCanceled; - -// From Clock.c -unsigned int s_adjustRate; -BOOL s_timerReset; -BOOL s_timerStopped; - -#ifndef HARDWARE_CLOCK -#include -clock_t s_realTimePrevious; -clock_t s_tpmTime; -#endif - - -// From LocalityPlat.c -unsigned char s_locality; - -// From Power.c -BOOL s_powerLost; - -// From Entropy.c -uint32_t lastEntropy; -int firstValue; - -// From NVMem.c -unsigned char s_NV[NV_MEMORY_SIZE]; -BOOL s_NvIsAvailable; -BOOL s_NV_unrecoverable; -BOOL s_NV_recoverable; - -// From PPPlat.c -BOOL s_physicalPresence; diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/PowerPlat.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/PowerPlat.c deleted file mode 100644 index 8d250cdcc..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/PowerPlat.c +++ /dev/null @@ -1,114 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//** Includes and Function Prototypes - -#include "PlatformData.h" -#include "Platform_fp.h" -#include "_TPM_Init_fp.h" - -//** Functions - -//***_plat__Signal_PowerOn() -// Signal platform power on -LIB_EXPORT int -_plat__Signal_PowerOn( - void - ) -{ - // Reset the timer - _plat__TimerReset(); - - // Need to indicate that we lost power - s_powerLost = TRUE; - - return 0; -} - -//*** _plat__WasPowerLost() -// Test whether power was lost before a _TPM_Init. -// -// This function will clear the "hardware" indication of power loss before return. -// This means that there can only be one spot in the TPM code where this value -// gets read. This method is used here as it is the most difficult to manage in the -// TPM code and, if the hardware actually works this way, it is hard to make it -// look like anything else. So, the burden is placed on the TPM code rather than the -// platform code -// return type: int -// TRUE(1) power was lost -// FALSE(0) power was not lost -LIB_EXPORT int -_plat__WasPowerLost( - void - ) -{ - BOOL retVal = s_powerLost; - s_powerLost = FALSE; - return retVal; -} - -//*** _plat_Signal_Reset() -// This a TPM reset without a power loss. -LIB_EXPORT int -_plat__Signal_Reset( - void - ) -{ - // Initialize locality - s_locality = 0; - - // Command cancel - s_isCanceled = FALSE; - - _TPM_Init(); - - // if we are doing reset but did not have a power failure, then we should - // not need to reload NV ... - - return 0; -} - -//***_plat__Signal_PowerOff() -// Signal platform power off -LIB_EXPORT void -_plat__Signal_PowerOff( - void - ) -{ - // Prepare NV memory for power off - _plat__NVDisable(); - - return; -} diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/RunCommand.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/RunCommand.c deleted file mode 100644 index f53275c0c..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/RunCommand.c +++ /dev/null @@ -1,91 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//**Introduction -// This module provides the platform specific entry and fail processing. The -// _plat__RunCommand() function is used to call to ExecuteCommand() in the TPM code. -// This function does whatever processing is necessary to set up the platform -// in anticipation of the call to the TPM including settup for error processing. -// -// The _plat__Fail() function is called when there is a failure in the TPM. The TPM -// code will have set the flag to indicate that the TPM is in failure mode. -// This call will then recursively call ExecuteCommand in order to build the -// failure mode response. When ExecuteCommand() returns to _plat__Fail(), the -// platform will do some platform specif operation to return to the environment in -// which the TPM is executing. For a simulator, setjmp/longjmp is used. For an OS, -// a system exit to the OS would be appropriate. - -//** Includes and locals -#include "PlatformData.h" -#include "Platform_fp.h" -#include -#include "ExecCommand_fp.h" -#include "StmUtil.h" - -jmp_buf s_jumpBuffer; - -//** Functions - -//***_plat__RunCommand() -// This version of RunCommand will set up a jum_buf and call ExecuteCommand(). If -// the command executes without failing, it will return and RunCommand will return. -// If there is a failure in the command, then _plat__Fail() is called and it will -// longjump back to RunCommand which will call ExecuteCommand again. However, this -// time, the TPM will be in failure mode so ExecuteCommand will simply build -// a failure response and return. -LIB_EXPORT void -_plat__RunCommand( - unsigned int requestSize, // IN: command buffer size - unsigned char *request, // IN: command buffer - unsigned int *responseSize, // IN/OUT: response buffer size - unsigned char **response // IN/OUT: response buffer - ) -{ - setjmp(s_jumpBuffer); - ExecuteCommand((uint32_t)requestSize, request, (uint32_t*)responseSize, response); -} - -//***_plat__Fail() -// This is the platform depended failure exit for the TPM. -LIB_EXPORT NORETURN void -_plat__FailDetailed( - char * file, - int line, - const char * func - ) -{ - dbgPrint("TPMFAIL: %s (%s@%d)\r\n", func, file, line); - longjmp(&s_jumpBuffer[0], 1); -} diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/Unique.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/Unique.c deleted file mode 100644 index 0e3b88d3c..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/Platform/src/Unique.c +++ /dev/null @@ -1,85 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//** Introduction -// In some implementations of the TPM, the hardware can provide a secret -// value to the TPM. This secret value is statistically unique to the -// instance of the TPM. Typical uses of this value are to provide -// personalization to the random number generation and as a shared secret -// between the TPM and the manufacturer. - -//** Includes -#include "PlatformData.h" -#include "Platform_fp.h" -#include - -char tpmUnique[WC_SHA512_DIGEST_SIZE] = {0}; - -//** _plat__GetUnique() -// This function is used to access the platform-specific unique value. -// This function places the unique value in the provided buffer ('b') -// and returns the number of bytes transferred. The function will not -// copy more data than 'bSize'. -// NOTE: If a platform unique value has unequal distribution of uniqueness -// and 'bSize' is smaller than the size of the unique value, the 'bSize' -// portion with the most uniqueness should be returned. -LIB_EXPORT uint32_t -_plat__GetUnique( - uint32_t which, // authorities (0) or details - uint32_t bSize, // size of the buffer - unsigned char *b // output buffer - ) -{ - const char *from = tpmUnique; - uint32_t retVal = 0; - - if(which == 0) // the authorities value - { - for(retVal = 0; retVal < bSize; retVal++) - { - *b++ = *from++; - } - } - else - { -#define uSize sizeof(tpmUnique) - b = &b[((bSize < uSize) ? bSize : uSize) - 1]; - for(retVal = 0; retVal < bSize; retVal++) - { - *b-- = *from++; - } - } - return retVal; -} diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/include/StmUtil.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/include/StmUtil.h deleted file mode 100644 index fec385f93..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/include/StmUtil.h +++ /dev/null @@ -1,33 +0,0 @@ -#include - -#ifndef NDEBUG -#define ITMSTDERR (0) -#define ITMSIGNAL (1) -#define ITMCMDRSP (2) -#define ITMCHANNELS (3) -#define dbgPrint(fmt, ...) fprintf(stderr, "%s: " fmt, GetLogStamp(), ##__VA_ARGS__); -#define dbgPrintAppend(fmt, ...) fprintf(stderr, fmt, ##__VA_ARGS__); -#define itmPrint(__channel, fmt, ...) fprintf(g_itm[__channel], "%s: " fmt, GetLogStamp(), ##__VA_ARGS__); -#define itmPrintAppend(__channel, fmt, ...) fprintf(g_itm[__channel], fmt, ##__VA_ARGS__); -#else -#define dbgPrint(fmt, ...) ((void)0) -#define dbgPrintAppend(fmt, ...) ((void)0) -#endif -#define logError(fmt, ...) dbgPrint("[ERROR] %s (%s@%u) - " fmt, __func__, __FILE__, __LINE__, ##__VA_ARGS__); -#define logWarning(fmt, ...) dbgPrint("[WARNING] %s (%s@%u) - " fmt, __func__, __FILE__, __LINE__, ##__VA_ARGS__); -#define logInfo(fmt, ...) dbgPrint("[Info] %s (%s@%u) - " fmt, __func__, __FILE__, __LINE__, ##__VA_ARGS__); -extern char logStampStr[40]; -extern void* g_itm[ITMCHANNELS]; - -#define ITMFILENO (4) -#define ITMCHANNELNO (32) -void ITM_Out(uint32_t port, uint8_t ch); - -char* GetLogStamp(void); -int BlueButtonTransitionDetected(void); -void SetDutyCycleIndicator(bool on); -void KillUSBLink(void); -void SetRealTimeClock(time_t tm); -void ReadMcuInfo(unsigned char* serial, uint16_t *flashSize, uint16_t *mcuType, uint16_t *mcuRev); -void PerformSystemReset(void); -void InitializeITM(); diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/include/TpmDevice.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/include/TpmDevice.h deleted file mode 100644 index e683570be..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/include/TpmDevice.h +++ /dev/null @@ -1,78 +0,0 @@ -#define SIGNALMAGIC (0x326d7054) //Tpm2 -#define MAX_TPM_MESSAGE_SIZE (sizeof(unsigned int) + 2048) - -typedef enum -{ - SignalNothing = 0, - SignalShutdown, - SignalReset, - SignalSetClock, - // IN {UINT32 time} - SignalCancelOn, - SignalCancelOff, - SignalCommand, - // IN {BYTE Locality, UINT32 InBufferSize, BYTE[InBufferSize] InBuffer} - // OUT {UINT32 OutBufferSize, BYTE[OutBufferSize] OutBuffer} - SignalResponse, - // OUT {UINT32 OutBufferSize, BYTE[OutBufferSize] OutBuffer} -} signalCode_t; - -typedef struct -{ - unsigned int magic; - signalCode_t signal; - unsigned int dataSize; -} signalHdr_t; - -typedef union -{ - struct - { - unsigned int time; - } SignalSetClockPayload; - struct - { - unsigned int locality; - unsigned int cmdSize; - unsigned char cmd[1]; - } SignalCommandPayload; -} signalPayload_t, *pSignalPayload_t; - -typedef union -{ - signalHdr_t s; - unsigned char b[sizeof(signalHdr_t)]; -} signalWrapper_t, *pSignalWrapper_t; - -typedef struct tpmOperationsFlags_t -{ - unsigned char resetRequested : 1; - unsigned char powerOffRequested : 1; - unsigned char executionRequested : 1; - unsigned char responseRequested : 1; -} tpmOperationsFlags_t; - -typedef struct tpmOperation_t -{ - tpmOperationsFlags_t flags; - int cmdSize; - int receivingCmd; - int rspSize; - unsigned char msgBuf[MAX_TPM_MESSAGE_SIZE]; -} tpmOperation_t; - -extern volatile tpmOperation_t tpmOp; - -int BlueButtonTransitionDetected(void); -void SetDutyCycleIndicator(bool on); -void KillUSBLink(void); -void SetRealTimeClock(time_t tm); -void ReadMcuInfo(unsigned char* serial, uint16_t *flashSize, uint16_t *mcuType, uint16_t *mcuRev); -void PerformSystemReset(void); -void HAL_Delay(uint32_t Delay); -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); - -bool TpmInitializeDevice(void); -bool TpmOperationsLoop(void); -void TpmConnectionReset(void); -bool TpmSignalEvent(uint8_t* Buf, uint32_t *Len); diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/include/user_settings.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/include/user_settings.h deleted file mode 100644 index a4d7e9cd1..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/include/user_settings.h +++ /dev/null @@ -1,54 +0,0 @@ -/* settings.h - * - * Copyright (C) 2006-2017 wolfSSL Inc. - * - * This file is part of wolfSSL. - * - * wolfSSL is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * wolfSSL is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA - */ - - -/* Place OS specific preprocessor flags, defines, includes here, will be - included into every file because types.h includes it */ - - -#ifndef WOLF_CRYPT_USER_SETTINGS_H -#define WOLF_CRYPT_USER_SETTINGS_H - -#ifdef __cplusplus - extern "C" { -#endif - -#define SINGLE_THREADED -#define NO_FILESYSTEM -#define NO_OLD_WC_NAMES -#define WC_NO_HARDEN -#define WOLFSSL_SHA384 -#define WOLFSSL_SHA512 -#define WOLFSSL_AES_DIRECT -#define WOLFSSL_DES_ECB -#define WOLFSSL_KEY_GEN -#define HAVE_ECC -#define ECC_SHAMIR -#define USE_FAST_MATH -#define WOLFSSL_PUBLIC_ECC_ADD_DBL -#define LIBRARY_COMPATIBILITY_CHECK -#define WOLFSSL_USER_IO - -#ifdef __cplusplus - } /* extern "C" */ -#endif - -#endif diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/src/StmUtil.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/src/StmUtil.c deleted file mode 100644 index fc0cc6335..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/src/StmUtil.c +++ /dev/null @@ -1,136 +0,0 @@ -#include -#include -#include -#include -#include "stm32l4xx_hal.h" -#include "usb_device.h" -#include "StmUtil.h" - -// RTC initialized by MX_RTC_Init -extern RTC_HandleTypeDef hrtc; - -typedef unsigned char DEVICE_UNIQUE_ID_T[12]; -#define DEVICE_UNIQUE_ID (*(DEVICE_UNIQUE_ID_T*)(UID_BASE)) -#define DEVICE_FLASH_SIZE (*(uint16_t *)(FLASHSIZE_BASE)) -#define DEVICE_TYPE (*(uint16_t *) (DBGMCU->IDCODE & 0x00000fff)) -#define DEVICE_REV (*(uint16_t *) (DBGMCU->IDCODE >> 16)) -char __attribute__((section (".ram2"))) logStampStr[40] = {0}; -void* __attribute__((section (".ram2"))) g_itm[ITMCHANNELS] = {0}; - -GPIO_PinState BlueButtonLast = GPIO_PIN_SET; -int BlueButtonTransitionDetected(void) -{ - GPIO_PinState PPButton = HAL_GPIO_ReadPin(B1_GPIO_Port, B1_Pin); - if((PPButton == GPIO_PIN_RESET) && (BlueButtonLast == GPIO_PIN_SET)) - { - // Now pressed - BlueButtonLast = PPButton; - return 1; - } - else if((PPButton == GPIO_PIN_SET) && (BlueButtonLast == GPIO_PIN_RESET)) - { - // Now released - BlueButtonLast = PPButton; - return -1; - } - // No change - return 0; -} - -#ifndef NDEBUG -#define ITM_PORT_BITS (0xffffffff) -void InitializeITM() -{ -// CoreDebug->DEMCR = CoreDebug_DEMCR_TRCENA_Msk; /* enable trace in core debug */ -// ITM->TCR = ITM_TCR_TraceBusID_Msk | ITM_TCR_SWOENA_Msk | ITM_TCR_SYNCENA_Msk | ITM_TCR_ITMENA_Msk; /* ITM Trace Control Register */ -// ITM->TPR = ITM_TPR_PRIVMASK_Msk; /* ITM Trace Privilege Register */ -// ITM->TER = ITM_PORT_BITS; /* ITM Trace Enable Register. Enabled tracing on stimulus ports. One bit per stimulus port. */ -// *((volatile unsigned *)(ITM_BASE + 0x01000)) = 0x400003FE; /* DWT_CTRL */ -// *((volatile unsigned *)(ITM_BASE + 0x40304)) = 0x00000100; /* Formatter and Flush Control Register */ - - for(uint32_t n = 0; n < ITMCHANNELS; n++) - { - char fileName[10]; - sprintf(fileName, "ITM[%02u]", (unsigned int)n); - g_itm[n] = (void*)fopen(fileName, "wb"); - } -} - -void ITM_Out(uint32_t port, uint8_t ch) -{ - while(ITM->PORT[port].u32 == 0); - ITM->PORT[port].u8 = ch; -} -#endif - -void SetDutyCycleIndicator(bool on) -{ - HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, on ? GPIO_PIN_SET : GPIO_PIN_RESET); -} - -char* GetLogStamp(void) -{ - RTC_TimeTypeDef time = {0}; - RTC_DateTypeDef date = {0}; - HAL_RTC_GetTime(&hrtc, &time, RTC_FORMAT_BIN); - HAL_RTC_GetDate(&hrtc, &date, RTC_FORMAT_BIN); - - sprintf(logStampStr, "%04d.%02d.%02d-%02d:%02d:%02d.%03dGMT", - date.Year + 2000, - date.Month, - date.Date, - time.Hours, - time.Minutes, - time.Seconds, - (int)((1000 / time.SecondFraction) * (time.SecondFraction - time.SubSeconds))); - return logStampStr; -} - -void KillUSBLink(void) -{ - dbgPrint("USB de-initialization...\r\n"); - MX_USB_DEVICE_DeInit(); -} - -void SetRealTimeClock(time_t tm) -{ - struct tm* local = localtime((time_t*)&tm); - RTC_TimeTypeDef time = {0}; - RTC_DateTypeDef date = {0}; - date.Year = local->tm_year - 100; - date.Month = local->tm_mon + 1; - date.Date = local->tm_mday; - date.WeekDay = local->tm_wday + 1; - time.Hours = local->tm_hour; - time.Minutes = local->tm_min; - time.Seconds = local->tm_sec; - HAL_RTC_SetTime(&hrtc, &time, RTC_FORMAT_BIN); - HAL_RTC_SetDate(&hrtc, &date, RTC_FORMAT_BIN); -} - -void ReadMcuInfo(unsigned char* serial, uint16_t *flashSize, uint16_t *mcuType, uint16_t *mcuRev) -{ - if(serial) - { - memcpy(serial, DEVICE_UNIQUE_ID, sizeof(DEVICE_UNIQUE_ID)); - } - if(flashSize) - { - *flashSize = DEVICE_FLASH_SIZE; - } - if(mcuType) - { - *mcuType = DEVICE_TYPE; - } - if(mcuRev) - { - *mcuRev = DEVICE_REV; - } -} - -void PerformSystemReset(void) -{ - dbgPrint("Executing NVIC_SystemReset()...\r\n"); - HAL_Delay(1); - NVIC_SystemReset(); -} diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/src/TpmDevice.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/src/TpmDevice.c deleted file mode 100644 index 07b1aa893..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/TPMDevice/src/TpmDevice.c +++ /dev/null @@ -1,964 +0,0 @@ -#include -#include -#include -#include -#include "StmUtil.h" -#include -#undef INLINE -#include "Tpm.h" -#include "TpmDevice.h" - -volatile tpmOperation_t tpmOp = { 0 }; -extern char tpmUnique[WC_SHA512_DIGEST_SIZE]; - -uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); - -#ifndef NDEBUG -#define TPM_RC_MAX_FM1 (TPM_RC)(RC_FMT1 + 0x03F) - -typedef struct -{ - uint32_t index; - char* str; -} lookup_t; - -const lookup_t tpm_cc_table[] = -{ -#if CC_NV_UndefineSpaceSpecial == YES - {TPM_CC_NV_UndefineSpaceSpecial, "TPM_CC_NV_UndefineSpaceSpecial"}, -#endif -#if CC_EvictControl == YES - {TPM_CC_EvictControl, "TPM_CC_EvictControl"}, -#endif -#if CC_HierarchyControl == YES - {TPM_CC_HierarchyControl, "TPM_CC_HierarchyControl"}, -#endif -#if CC_NV_UndefineSpace == YES - {TPM_CC_NV_UndefineSpace, "TPM_CC_NV_UndefineSpace"}, -#endif -#if CC_ChangeEPS == YES - {TPM_CC_ChangeEPS, "TPM_CC_ChangeEPS"}, -#endif -#if CC_ChangePPS == YES - {TPM_CC_ChangePPS, "TPM_CC_ChangePPS"}, -#endif -#if CC_Clear == YES - {TPM_CC_Clear, "TPM_CC_Clear"}, -#endif -#if CC_ClearControl == YES - {TPM_CC_ClearControl, "TPM_CC_ClearControl"}, -#endif -#if CC_ClockSet == YES - {TPM_CC_ClockSet, "TPM_CC_ClockSet"}, -#endif -#if CC_HierarchyChangeAuth == YES - {TPM_CC_HierarchyChangeAuth, "TPM_CC_HierarchyChangeAuth"}, -#endif -#if CC_NV_DefineSpace == YES - {TPM_CC_NV_DefineSpace, "TPM_CC_NV_DefineSpace"}, -#endif -#if CC_PCR_Allocate == YES - {TPM_CC_PCR_Allocate, "TPM_CC_PCR_Allocate"}, -#endif -#if CC_PCR_SetAuthPolicy == YES - {TPM_CC_PCR_SetAuthPolicy, "TPM_CC_PCR_SetAuthPolicy"}, -#endif -#if CC_PP_Commands == YES - {TPM_CC_PP_Commands, "TPM_CC_PP_Commands"}, -#endif -#if CC_SetPrimaryPolicy == YES - {TPM_CC_SetPrimaryPolicy, "TPM_CC_SetPrimaryPolicy"}, -#endif -#if CC_FieldUpgradeStart == YES - {TPM_CC_FieldUpgradeStart, "TPM_CC_FieldUpgradeStart"}, -#endif -#if CC_ClockRateAdjust == YES - {TPM_CC_ClockRateAdjust, "TPM_CC_ClockRateAdjust"}, -#endif -#if CC_CreatePrimary == YES - {TPM_CC_CreatePrimary, "TPM_CC_CreatePrimary"}, -#endif -#if CC_NV_GlobalWriteLock == YES - {TPM_CC_NV_GlobalWriteLock, "TPM_CC_NV_GlobalWriteLock"}, -#endif -#if CC_GetCommandAuditDigest == YES - {TPM_CC_GetCommandAuditDigest, ""}, -#endif -#if CC_NV_Increment == YES - {TPM_CC_NV_Increment, "TPM_CC_NV_Increment"}, -#endif -#if CC_NV_SetBits == YES - {TPM_CC_NV_SetBits, "TPM_CC_NV_SetBits"}, -#endif -#if CC_NV_Extend == YES - {TPM_CC_NV_Extend, "TPM_CC_NV_Extend"}, -#endif -#if CC_NV_Write == YES - {TPM_CC_NV_Write, "TPM_CC_NV_Write"}, -#endif -#if CC_NV_WriteLock == YES - {TPM_CC_NV_WriteLock, "TPM_CC_NV_WriteLock"}, -#endif -#if CC_DictionaryAttackLockReset == YES - {TPM_CC_DictionaryAttackLockReset, "TPM_CC_DictionaryAttackLockReset"}, -#endif -#if CC_DictionaryAttackParameters == YES - {TPM_CC_DictionaryAttackParameters, "TPM_CC_DictionaryAttackParameters"}, -#endif -#if CC_NV_ChangeAuth == YES - {TPM_CC_NV_ChangeAuth, "TPM_CC_NV_ChangeAuth"}, -#endif -#if CC_PCR_Event == YES - {TPM_CC_PCR_Event, "TPM_CC_PCR_Event"}, -#endif -#if CC_PCR_Reset == YES - {TPM_CC_PCR_Reset, "TPM_CC_PCR_Reset"}, -#endif -#if CC_SequenceComplete == YES - {TPM_CC_SequenceComplete, "TPM_CC_SequenceComplete"}, -#endif -#if CC_SetAlgorithmSet == YES - {TPM_CC_SetAlgorithmSet, "TPM_CC_SetAlgorithmSet"}, -#endif -#if CC_SetCommandCodeAuditStatus == YES - {TPM_CC_SetCommandCodeAuditStatus, "TPM_CC_SetCommandCodeAuditStatus"}, -#endif -#if CC_FieldUpgradeData == YES - {TPM_CC_FieldUpgradeData, "TPM_CC_FieldUpgradeData"}, -#endif -#if CC_IncrementalSelfTest == YES - {TPM_CC_IncrementalSelfTest, "TPM_CC_FieldUpgradeData"}, -#endif -#if CC_SelfTest == YES - {TPM_CC_SelfTest, "TPM_CC_SelfTest"}, -#endif -#if CC_Startup == YES - {TPM_CC_Startup, "TPM_CC_Startup"}, -#endif -#if CC_Shutdown == YES - {TPM_CC_Shutdown, "TPM_CC_Shutdown"}, -#endif -#if CC_StirRandom == YES - {TPM_CC_StirRandom, ""}, -#endif -#if CC_ActivateCredential == YES - {TPM_CC_ActivateCredential, "TPM_CC_ActivateCredential"}, -#endif -#if CC_Certify == YES - {TPM_CC_Certify, "TPM_CC_Certify"}, -#endif -#if CC_PolicyNV == YES - {TPM_CC_PolicyNV, "TPM_CC_PolicyNV"}, -#endif -#if CC_CertifyCreation == YES - {TPM_CC_CertifyCreation, "TPM_CC_CertifyCreation"}, -#endif -#if CC_Duplicate == YES - {TPM_CC_Duplicate, "TPM_CC_Duplicate"}, -#endif -#if CC_GetTime == YES - {TPM_CC_GetTime, "TPM_CC_GetTime"}, -#endif -#if CC_GetSessionAuditDigest == YES - {TPM_CC_GetSessionAuditDigest, "TPM_CC_GetSessionAuditDigest"}, -#endif -#if CC_NV_Read == YES - {TPM_CC_NV_Read, "TPM_CC_NV_Read"}, -#endif -#if CC_NV_ReadLock == YES - {TPM_CC_NV_ReadLock, "TPM_CC_NV_ReadLock"}, -#endif -#if CC_ObjectChangeAuth == YES - {TPM_CC_ObjectChangeAuth, "TPM_CC_ObjectChangeAuth"}, -#endif -#if CC_PolicySecret == YES - {TPM_CC_PolicySecret, "TPM_CC_PolicySecret"}, -#endif -#if CC_Rewrap == YES - {TPM_CC_Rewrap, "TPM_CC_Rewrap"}, -#endif -#if CC_Create == YES - {TPM_CC_Create, "TPM_CC_Create"}, -#endif -#if CC_ECDH_ZGen == YES - {TPM_CC_ECDH_ZGen, "TPM_CC_ECDH_ZGen"}, -#endif -#if CC_HMAC == YES - {TPM_CC_HMAC, "TPM_CC_HMAC"}, -#endif -#if CC_MAC == YES - {TPM_CC_MAC, "TPM_CC_HMAC"}, -#endif -#if CC_Import == YES - {TPM_CC_Import, "TPM_CC_Import"}, -#endif -#if CC_Load == YES - {TPM_CC_Load, "TPM_CC_Load"}, -#endif -#if CC_Quote == YES - {TPM_CC_Quote, "TPM_CC_Quote"}, -#endif -#if CC_RSA_Decrypt == YES - {TPM_CC_RSA_Decrypt, "TPM_CC_RSA_Decrypt"}, -#endif -#if CC_HMAC_Start == YES - {TPM_CC_HMAC_Start, "TPM_CC_HMAC_Start"}, -#endif -#if CC_MAC_Start == YES - {TPM_CC_MAC_Start, "TPM_CC_HMAC_Start"}, -#endif -#if CC_SequenceUpdate == YES - {TPM_CC_SequenceUpdate, "TPM_CC_SequenceUpdate"}, -#endif -#if CC_Sign == YES - {TPM_CC_Sign, "TPM_CC_Sign"}, -#endif -#if CC_Unseal == YES - {TPM_CC_Unseal, "TPM_CC_Sign"}, -#endif -#if CC_PolicySigned == YES - {TPM_CC_PolicySigned, "TPM_CC_PolicySigned"}, -#endif -#if CC_ContextLoad == YES - {TPM_CC_ContextLoad, "TPM_CC_ContextLoad"}, -#endif -#if CC_ContextSave == YES - {TPM_CC_ContextSave, "TPM_CC_ContextSave"}, -#endif -#if CC_ECDH_KeyGen == YES - {TPM_CC_ECDH_KeyGen, "TPM_CC_ECDH_KeyGen"}, -#endif -#if CC_EncryptDecrypt == YES - {TPM_CC_EncryptDecrypt, "TPM_CC_EncryptDecrypt"}, -#endif -#if CC_FlushContext == YES - {TPM_CC_FlushContext, "TPM_CC_FlushContext"}, -#endif -#if CC_LoadExternal == YES - {TPM_CC_LoadExternal, ""}, -#endif -#if CC_MakeCredential == YES - {TPM_CC_MakeCredential, "TPM_CC_MakeCredential"}, -#endif -#if CC_NV_ReadPublic == YES - {TPM_CC_NV_ReadPublic, "TPM_CC_NV_ReadPublic"}, -#endif -#if CC_PolicyAuthorize == YES - {TPM_CC_PolicyAuthorize, "TPM_CC_PolicyAuthorize"}, -#endif -#if CC_PolicyAuthValue == YES - {TPM_CC_PolicyAuthValue, "TPM_CC_PolicyAuthValue"}, -#endif -#if CC_PolicyCommandCode == YES - {TPM_CC_PolicyCommandCode, "TPM_CC_PolicyCommandCode"}, -#endif -#if CC_PolicyCounterTimer == YES - {TPM_CC_PolicyCounterTimer, "TPM_CC_PolicyCounterTimer"}, -#endif -#if CC_PolicyCpHash == YES - {TPM_CC_PolicyCpHash, "TPM_CC_PolicyCounterTimer"}, -#endif -#if CC_PolicyLocality == YES - {TPM_CC_PolicyLocality, "TPM_CC_PolicyLocality"}, -#endif -#if CC_PolicyNameHash == YES - {TPM_CC_PolicyNameHash, "TPM_CC_PolicyNameHash"}, -#endif -#if CC_PolicyOR == YES - {TPM_CC_PolicyOR, "TPM_CC_PolicyOR"}, -#endif -#if CC_PolicyTicket == YES - {TPM_CC_PolicyTicket, "TPM_CC_PolicyTicket"}, -#endif -#if CC_ReadPublic == YES - {TPM_CC_ReadPublic, "TPM_CC_ReadPublic"}, -#endif -#if CC_RSA_Encrypt == YES - {TPM_CC_RSA_Encrypt, "TPM_CC_RSA_Encrypt"}, -#endif -#if CC_StartAuthSession == YES - {TPM_CC_StartAuthSession, "TPM_CC_StartAuthSession"}, -#endif -#if CC_VerifySignature == YES - {TPM_CC_VerifySignature, "TPM_CC_VerifySignature"}, -#endif -#if CC_ECC_Parameters == YES - {TPM_CC_ECC_Parameters, "TPM_CC_VerifySignature"}, -#endif -#if CC_FirmwareRead == YES - {TPM_CC_FirmwareRead, "TPM_CC_FirmwareRead"}, -#endif -#if CC_GetCapability == YES - {TPM_CC_GetCapability, "TPM_CC_GetCapability"}, -#endif -#if CC_GetRandom == YES - {TPM_CC_GetRandom, "TPM_CC_GetRandom"}, -#endif -#if CC_GetTestResult == YES - {TPM_CC_GetTestResult, "TPM_CC_GetTestResult"}, -#endif -#if CC_Hash == YES - {TPM_CC_Hash, "TPM_CC_Hash"}, -#endif -#if CC_PCR_Read == YES - {TPM_CC_PCR_Read, "TPM_CC_Hash"}, -#endif -#if CC_PolicyPCR == YES - {TPM_CC_PolicyPCR, "TPM_CC_PolicyPCR"}, -#endif -#if CC_PolicyRestart == YES - {TPM_CC_PolicyRestart, "TPM_CC_PolicyRestart"}, -#endif -#if CC_ReadClock == YES - {TPM_CC_ReadClock, "TPM_CC_ReadClock"}, -#endif -#if CC_PCR_Extend == YES - {TPM_CC_PCR_Extend, "TPM_CC_PCR_Extend"}, -#endif -#if CC_PCR_SetAuthValue == YES - {TPM_CC_PCR_SetAuthValue, "TPM_CC_PCR_SetAuthValue"}, -#endif -#if CC_NV_Certify == YES - {TPM_CC_NV_Certify, "TPM_CC_NV_Certify"}, -#endif -#if CC_EventSequenceComplete == YES - {TPM_CC_EventSequenceComplete, "TPM_CC_EventSequenceComplete"}, -#endif -#if CC_HashSequenceStart == YES - {TPM_CC_HashSequenceStart, "TPM_CC_EventSequenceComplete"}, -#endif -#if CC_PolicyPhysicalPresence == YES - {TPM_CC_PolicyPhysicalPresence, ""}, -#endif -#if CC_PolicyDuplicationSelect == YES - {TPM_CC_PolicyDuplicationSelect, "TPM_CC_PolicyDuplicationSelect"}, -#endif -#if CC_PolicyGetDigest == YES - {TPM_CC_PolicyGetDigest, "TPM_CC_PolicyGetDigest"}, -#endif -#if CC_TestParms == YES - {TPM_CC_TestParms, "TPM_CC_TestParms"}, -#endif -#if CC_Commit == YES - {TPM_CC_Commit, "TPM_CC_Commit"}, -#endif -#if CC_PolicyPassword == YES - {TPM_CC_PolicyPassword, "TPM_CC_PolicyPassword"}, -#endif -#if CC_ZGen_2Phase == YES - {TPM_CC_ZGen_2Phase, "TPM_CC_ZGen_2Phase"}, -#endif -#if CC_EC_Ephemeral == YES - {TPM_CC_EC_Ephemeral, "TPM_CC_EC_Ephemeral"}, -#endif -#if CC_PolicyNvWritten == YES - {TPM_CC_PolicyNvWritten, "TPM_CC_PolicyNvWritten"}, -#endif -#if CC_PolicyTemplate == YES - {TPM_CC_PolicyTemplate, "TPM_CC_PolicyTemplate"}, -#endif -#if CC_CreateLoaded == YES - {TPM_CC_CreateLoaded, ""}, -#endif -#if CC_PolicyAuthorizeNV == YES - {TPM_CC_PolicyAuthorizeNV, "TPM_CC_PolicyAuthorizeNV"}, -#endif -#if CC_EncryptDecrypt2 == YES - {TPM_CC_EncryptDecrypt2, "TPM_CC_EncryptDecrypt2"}, -#endif -#if CC_AC_GetCapability == YES - {TPM_CC_AC_GetCapability, "TPM_CC_AC_GetCapability"}, -#endif -#if CC_AC_Send == YES - {TPM_CC_AC_Send, "TPM_CC_AC_Send"}, -#endif -#if CC_Policy_AC_SendSelect == YES - {TPM_CC_Policy_AC_SendSelect, "TPM_CC_Policy_AC_SendSelect"}, -#endif - {(uint32_t)-1, NULL} -}; - -const lookup_t tpm_rc_globalCodes[] = { - {TPM_RC_SUCCESS, "TPM_RC_SUCCESS"}, - {TPM_RC_BAD_TAG, "TPM_RC_BAD_TAG"}, - {(uint32_t)-1, NULL} -}; - -const lookup_t tpm_rc_formatZeroCodes[] = { - {TPM_RC_INITIALIZE, "TPM_RC_INITIALIZE"}, - {TPM_RC_FAILURE, "TPM_RC_FAILURE"}, - {TPM_RC_SEQUENCE, "TPM_RC_SEQUENCE"}, - {TPM_RC_PRIVATE, "TPM_RC_PRIVATE"}, - {TPM_RC_HMAC, "TPM_RC_HMAC"}, - {TPM_RC_DISABLED, "TPM_RC_DISABLED"}, - {TPM_RC_EXCLUSIVE, "TPM_RC_EXCLUSIVE"}, - {TPM_RC_AUTH_TYPE, "TPM_RC_AUTH_TYPE"}, - {TPM_RC_AUTH_MISSING, "TPM_RC_AUTH_MISSING"}, - {TPM_RC_POLICY, "TPM_RC_POLICY"}, - {TPM_RC_PCR, "TPM_RC_PCR"}, - {TPM_RC_PCR_CHANGED, "TPM_RC_PCR_CHANGED"}, - {TPM_RC_UPGRADE, "TPM_RC_UPGRADE"}, - {TPM_RC_TOO_MANY_CONTEXTS, "TPM_RC_TOO_MANY_CONTEXTS"}, - {TPM_RC_AUTH_UNAVAILABLE, "TPM_RC_AUTH_UNAVAILABLE"}, - {TPM_RC_REBOOT, "TPM_RC_REBOOT"}, - {TPM_RC_UNBALANCED, "TPM_RC_UNBALANCED"}, - {TPM_RC_COMMAND_SIZE, "TPM_RC_COMMAND_SIZE"}, - {TPM_RC_COMMAND_CODE, "TPM_RC_COMMAND_CODE"}, - {TPM_RC_AUTHSIZE, "TPM_RC_AUTHSIZE"}, - {TPM_RC_AUTH_CONTEXT, "TPM_RC_AUTH_CONTEXT"}, - {TPM_RC_NV_RANGE, "TPM_RC_NV_RANGE"}, - {TPM_RC_NV_SIZE, "TPM_RC_NV_SIZE"}, - {TPM_RC_NV_LOCKED, "TPM_RC_NV_LOCKED"}, - {TPM_RC_NV_AUTHORIZATION, "TPM_RC_NV_AUTHORIZATION"}, - {TPM_RC_NV_UNINITIALIZED, "TPM_RC_NV_UNINITIALIZED"}, - {TPM_RC_NV_SPACE, "TPM_RC_NV_SPACE"}, - {TPM_RC_NV_DEFINED, "TPM_RC_NV_DEFINED"}, - {TPM_RC_BAD_CONTEXT, "TPM_RC_BAD_CONTEXT"}, - {TPM_RC_CPHASH, "TPM_RC_CPHASH"}, - {TPM_RC_PARENT, "TPM_RC_PARENT"}, - {TPM_RC_NEEDS_TEST, "TPM_RC_NEEDS_TEST"}, - {TPM_RC_NO_RESULT, "TPM_RC_NO_RESULT"}, - {TPM_RC_SENSITIVE, "TPM_RC_SENSITIVE"}, - {(uint32_t)-1, NULL} -}; - -const lookup_t tpm_rc_warningCodes[] = { - {TPM_RC_CONTEXT_GAP, "TPM_RC_CONTEXT_GAP"}, - {TPM_RC_CONTEXT_GAP, "TPM_RC_CONTEXT_GAP"}, - {TPM_RC_OBJECT_MEMORY, "TPM_RC_OBJECT_MEMORY"}, - {TPM_RC_SESSION_MEMORY, "TPM_RC_SESSION_MEMORY"}, - {TPM_RC_MEMORY, "TPM_RC_MEMORY"}, - {TPM_RC_SESSION_HANDLES, "TPM_RC_SESSION_HANDLES"}, - {TPM_RC_OBJECT_HANDLES, "TPM_RC_OBJECT_HANDLES"}, - {TPM_RC_LOCALITY, "TPM_RC_LOCALITY"}, - {TPM_RC_YIELDED, "TPM_RC_YIELDED"}, - {TPM_RC_CANCELED, "TPM_RC_CANCELED"}, - {TPM_RC_TESTING, "TPM_RC_TESTING"}, - {TPM_RC_REFERENCE_H0, "TPM_RC_REFERENCE_H0"}, - {TPM_RC_REFERENCE_H1, "TPM_RC_REFERENCE_H1"}, - {TPM_RC_REFERENCE_H2, "TPM_RC_REFERENCE_H2"}, - {TPM_RC_REFERENCE_H3, "TPM_RC_REFERENCE_H3"}, - {TPM_RC_REFERENCE_H4, "TPM_RC_REFERENCE_H4"}, - {TPM_RC_REFERENCE_H5, "TPM_RC_REFERENCE_H5"}, - {TPM_RC_REFERENCE_H6, "TPM_RC_REFERENCE_H6"}, - {TPM_RC_REFERENCE_S0, "TPM_RC_REFERENCE_S0"}, - {TPM_RC_REFERENCE_S1, "TPM_RC_REFERENCE_S1"}, - {TPM_RC_REFERENCE_S2, "TPM_RC_REFERENCE_S2"}, - {TPM_RC_REFERENCE_S3, "TPM_RC_REFERENCE_S3"}, - {TPM_RC_REFERENCE_S4, "TPM_RC_REFERENCE_S4"}, - {TPM_RC_REFERENCE_S5, "TPM_RC_REFERENCE_S5"}, - {TPM_RC_REFERENCE_S6, "TPM_RC_REFERENCE_S6"}, - {TPM_RC_NV_RATE, "TPM_RC_NV_RATE"}, - {TPM_RC_LOCKOUT, "TPM_RC_LOCKOUT"}, - {TPM_RC_RETRY, "TPM_RC_RETRY"}, - {TPM_RC_NV_UNAVAILABLE, "TPM_RC_NV_UNAVAILABLE"}, - {(uint32_t)-1, NULL} -}; - -const lookup_t tpm_rc_formatCodes[] = { - {TPM_RCS_ASYMMETRIC, "TPM_RCS_ASYMMETRIC"}, - {TPM_RC_ATTRIBUTES, "TPM_RC_ATTRIBUTES"}, - {TPM_RCS_ATTRIBUTES, "TPM_RCS_ATTRIBUTES"}, - {TPM_RC_HASH, "TPM_RC_HASH"}, - {TPM_RCS_HASH, "TPM_RCS_HASH"}, - {TPM_RC_VALUE, "TPM_RC_VALUE"}, - {TPM_RCS_VALUE, "TPM_RCS_VALUE"}, - {TPM_RC_HIERARCHY, "TPM_RC_HIERARCHY"}, - {TPM_RCS_HIERARCHY, "TPM_RCS_HIERARCHY"}, - {TPM_RC_KEY_SIZE, "TPM_RC_KEY_SIZE"}, - {TPM_RCS_KEY_SIZE, "TPM_RCS_KEY_SIZE"}, - {TPM_RC_MGF, "TPM_RC_MGF"}, - {TPM_RCS_MGF, "TPM_RCS_MGF"}, - {TPM_RC_MODE, "TPM_RC_MODE"}, - {TPM_RCS_MODE, "TPM_RCS_MODE"}, - {TPM_RC_TYPE, "TPM_RC_TYPE"}, - {TPM_RCS_TYPE, "TPM_RCS_TYPE"}, - {TPM_RC_HANDLE, "TPM_RC_HANDLE"}, - {TPM_RCS_HANDLE, "TPM_RCS_HANDLE"}, - {TPM_RC_KDF, "TPM_RC_KDF"}, - {TPM_RCS_KDF, "TPM_RCS_KDF"}, - {TPM_RC_RANGE, "TPM_RC_RANGE"}, - {TPM_RCS_RANGE, "TPM_RCS_RANGE"}, - {TPM_RC_AUTH_FAIL, "TPM_RC_AUTH_FAIL"}, - {TPM_RCS_AUTH_FAIL, "TPM_RCS_AUTH_FAIL"}, - {TPM_RC_NONCE, "TPM_RC_NONCE"}, - {TPM_RCS_NONCE, "TPM_RCS_NONCE"}, - {TPM_RC_PP, "TPM_RC_PP"}, - {TPM_RCS_PP, "TPM_RCS_PP"}, - {TPM_RC_SCHEME, "TPM_RC_SCHEME"}, - {TPM_RCS_SCHEME, "TPM_RCS_SCHEME"}, - {TPM_RC_SIZE, "TPM_RC_SIZE"}, - {TPM_RCS_SIZE, "TPM_RCS_SIZE"}, - {TPM_RC_SYMMETRIC, "TPM_RC_SYMMETRIC"}, - {TPM_RCS_SYMMETRIC, "TPM_RCS_SYMMETRIC"}, - {TPM_RC_TAG, "TPM_RC_TAG"}, - {TPM_RCS_TAG, "TPM_RCS_TAG"}, - {TPM_RC_SELECTOR, "TPM_RC_SELECTOR"}, - {TPM_RCS_SELECTOR, "TPM_RCS_SELECTOR"}, - {TPM_RC_INSUFFICIENT, "TPM_RC_INSUFFICIENT"}, - {TPM_RCS_INSUFFICIENT, "TPM_RCS_INSUFFICIENT"}, - {TPM_RC_SIGNATURE, "TPM_RC_SIGNATURE"}, - {TPM_RCS_SIGNATURE, "TPM_RCS_SIGNATURE"}, - {TPM_RC_KEY, "TPM_RC_KEY"}, - {TPM_RCS_KEY, "TPM_RCS_KEY"}, - {TPM_RC_POLICY_FAIL, "TPM_RC_POLICY_FAIL"}, - {TPM_RCS_POLICY_FAIL, "TPM_RCS_POLICY_FAIL"}, - {TPM_RC_INTEGRITY, "TPM_RC_INTEGRITY"}, - {TPM_RCS_INTEGRITY, "TPM_RCS_INTEGRITY"}, - {TPM_RC_TICKET, "TPM_RC_TICKET"}, - {TPM_RCS_TICKET, "TPM_RCS_TICKET"}, - {TPM_RC_RESERVED_BITS, "TPM_RC_RESERVED_BITS"}, - {TPM_RCS_RESERVED_BITS, "TPM_RCS_RESERVED_BITS"}, - {TPM_RC_BAD_AUTH, "TPM_RC_BAD_AUTH"}, - {TPM_RCS_BAD_AUTH, "TPM_RCS_BAD_AUTH"}, - {TPM_RC_EXPIRED, "TPM_RC_EXPIRED"}, - {TPM_RCS_EXPIRED, "TPM_RCS_EXPIRED"}, - {TPM_RC_POLICY_CC, "TPM_RC_POLICY_CC"}, - {TPM_RCS_POLICY_CC, "TPM_RCS_POLICY_CC"}, - {TPM_RC_BINDING, "TPM_RC_BINDING"}, - {TPM_RCS_BINDING, "TPM_RCS_BINDING"}, - {TPM_RC_CURVE, "TPM_RC_CURVE"}, - {TPM_RCS_CURVE, "TPM_RCS_CURVE"}, - {TPM_RC_ECC_POINT, "TPM_RC_ECC_POINT"}, - {TPM_RCS_ECC_POINT, "TPM_RCS_ECC_POINT"}, - {(uint32_t)-1, NULL} -}; - -char decodeBuf[100]; -#else -char decodeBuf[6]; -#endif - -static char* TpmDecodeTPM_CC(uint8_t* in) -{ - TPM_CC cc = BYTE_ARRAY_TO_UINT32(in); -#ifndef NDEBUG - uint32_t n; - for(n = 0; ((tpm_cc_table[n].index != (uint32_t)-1) && (tpm_cc_table[n].index != cc)) ; n++ ); - if(tpm_cc_table[n].index != (uint32_t)-1) - { - sprintf(decodeBuf, "%s()", tpm_cc_table[n].str); - } - else - { -#endif - sprintf(decodeBuf, "0x%03x", (unsigned int)cc); -#ifndef NDEBUG - } -#endif - return decodeBuf; -} - -static char* TpmDecodeTPM_RC(uint8_t* in) -{ - TPM_RC rc = BYTE_ARRAY_TO_UINT32(in); -#ifndef NDEBUG - uint32_t n; - uint32_t cursor = 0; - - for(n = 0; ((tpm_rc_globalCodes[n].index != (uint32_t)-1) && (tpm_rc_globalCodes[n].index != rc)) ; n++ ); - if(tpm_rc_globalCodes[n].index != (uint32_t)-1) - { - cursor = sprintf(decodeBuf, "{%s}", tpm_rc_globalCodes[n].str); - } - else if((rc & RC_FMT1) == RC_FMT1) - { - if(rc & TPM_RC_P) - { - cursor = sprintf(decodeBuf, "{RC_FMT1 | TPM_RC_P | TPM_RC_%X | ", (unsigned int)((rc & 0x00000f00) >> 8)); - } - else if(rc & TPM_RC_S) - { - cursor = sprintf(decodeBuf, "{RC_FMT1 | TPM_RC_S | TPM_RC_%X | ", (unsigned int)((rc & 0x00000700) >> 8)); - } - else - { - cursor = sprintf(decodeBuf, "{RC_FMT1 | TPM_RC_H | TPM_RC_%X | ", (unsigned int)((rc & 0x00000700) >> 8)); - } - - for(n = 0; ((tpm_rc_formatCodes[n].index != (uint32_t)-1) && (tpm_rc_formatCodes[n].index != (rc & TPM_RC_MAX_FM1))) ; n++ ); - if(tpm_rc_formatCodes[n].index != (uint32_t)-1) - { - cursor = sprintf(&decodeBuf[cursor], "%s}", tpm_rc_formatCodes[n].str); - } - else - { - cursor = 0; - } - } - else if((rc & RC_WARN) == RC_WARN) - { - for(n = 0; ((tpm_rc_warningCodes[n].index != (uint32_t)-1) && (tpm_rc_warningCodes[n].index != rc)) ; n++ ); - if(tpm_rc_warningCodes[n].index != (uint32_t)-1) - { - cursor = sprintf(decodeBuf, "{RC_VER1 | RC_WARN | %s}", tpm_rc_warningCodes[n].str); - } - } - else if((rc & RC_VER1) == RC_VER1) - { - for(n = 0; ((tpm_rc_formatZeroCodes[n].index != (uint32_t)-1) && (tpm_rc_formatZeroCodes[n].index != rc)) ; n++ ); - if(tpm_rc_formatZeroCodes[n].index != (uint32_t)-1) - { - cursor = sprintf(decodeBuf, "{RC_VER1 | %s}", tpm_rc_formatZeroCodes[n].str); - } - } - - if(cursor == 0) - { -#endif - sprintf(decodeBuf, "0x%03x", (unsigned int)rc); - return decodeBuf; -#ifndef NDEBUG - } -#endif - return decodeBuf; -} - -static bool TpmGenerateUnique(void) -{ - wc_Sha512 hash; - struct - { - uint16_t mcuType; - uint16_t mcuRev; - uint16_t flashSize; - unsigned char serial[12]; - } mcuInfo; - - ReadMcuInfo(mcuInfo.serial, &mcuInfo.flashSize, &mcuInfo.mcuType, &mcuInfo.mcuRev); - - if((wc_InitSha512(&hash)) || - (wc_Sha512Update(&hash, (const byte*)&mcuInfo, sizeof(mcuInfo))) || - (wc_Sha512Final(&hash, (byte*)tpmUnique))) - { - logError("Sha512 failed\r\n"); - return false; - } - wc_Sha512Free(&hash); - -#ifndef NDEBUG - uint8_t unique[WC_SHA512_DIGEST_SIZE] = {0}; - _plat__GetUnique(0, sizeof(unique), unique); - dbgPrint("Generated tpmUnique"); - for(uint32_t n = 0; n < sizeof(unique); n++) - { - if(!(n % 16)) dbgPrintAppend("\r\n "); - dbgPrintAppend("%02x", ((unsigned int)(unique[n]))); - } - dbgPrintAppend("\r\n"); -#endif - return true; -} - -bool TpmInitializeDevice(void) -{ - int retVal = 0; - - tpmOp.receivingCmd = -1; - TpmGenerateUnique(); - - SetDutyCycleIndicator(FALSE); - - // Factory reset requested? - if(BlueButtonTransitionDetected()) - { - dbgPrint("Factory reset requested.\r\n"); - if((retVal = _plat__NVEnable((void*)1)) < 0) - { - logError("_plat__NVEnable(1) failed unrecoverable.") - } - dbgPrint("Waiting for the button to be released...\r\n"); - while(BlueButtonTransitionDetected() == 0); - } - else - { - if((retVal = _plat__NVEnable((void*)0)) < 0) - { - logError("_plat__NVEnable(0) failed unrecoverable.") - } - } - - - if(retVal > 0) - { - dbgPrint("TPM_Manufacture(1) requested.\r\n"); - if((retVal = TPM_Manufacture(1)) != 0) - { - logError("TPM_Manufacture(1) failed.\r\n"); - } - } - - dbgPrint("_plat__SetNvAvail().\r\n"); - _plat__SetNvAvail(); - dbgPrint("_plat__Signal_PowerOn().\r\n"); - if((retVal =_plat__Signal_PowerOn()) != 0) - { - logError("_plat__Signal_PowerOn() failed.\r\n"); - } - dbgPrint("_plat__Signal_Reset().\r\n"); - if((retVal =_plat__Signal_Reset()) != 0) - { - logError("_plat__Signal_Reset() failed.\r\n"); - } - return (retVal == 0); -} - -bool TpmOperationsLoop(void) -{ - // Device reset - if(tpmOp.flags.resetRequested == 1) - { - tpmOp.flags.resetRequested = 0; - - HAL_Delay(1); - dbgPrint("Executing _plat__Signal_PowerOff()\r\n"); - _plat__Signal_PowerOff(); - PerformSystemReset(); - return false; - } - - if(tpmOp.flags.powerOffRequested == 1) - { - tpmOp.flags.powerOffRequested = 0; - dbgPrint("Executing _plat__Signal_PowerOff()\r\n"); - _plat__Signal_PowerOff(); - KillUSBLink(); - return false; - } - - // Physical presence button (blue button on the Nucleo) - int ppButton = BlueButtonTransitionDetected(); - if(ppButton > 0) - { - dbgPrint("Executing _plat__Signal_PhysicalPresenceOn().\r\n"); - _plat__Signal_PhysicalPresenceOn(); - } - else if (ppButton < 0) - { - dbgPrint("Executing _plat__Signal_PhysicalPresenceOff().\r\n"); - _plat__Signal_PhysicalPresenceOff(); - } - - // Command processing - if(tpmOp.flags.executionRequested == 1) - { - tpmOp.flags.executionRequested = 0; - unsigned int rspLenTPM = sizeof(tpmOp.msgBuf) - sizeof(rspLenTPM); - unsigned char* rspTPM = (unsigned char*)&tpmOp.msgBuf[sizeof(rspLenTPM)]; - - itmPrintAppend(ITMCMDRSP, "//%s\r\nunsigned char CmdBuf[%d] = {", GetLogStamp(), tpmOp.cmdSize); - for(uint32_t n = 0; n < tpmOp.cmdSize; n++) - { - if(n > 0) itmPrintAppend(ITMCMDRSP, ", "); - if(!(n % 16)) itmPrintAppend(ITMCMDRSP, "\r\n"); - itmPrintAppend(ITMCMDRSP, "0x%02x", tpmOp.msgBuf[n]); - } - itmPrintAppend(ITMCMDRSP, "\r\n};\r\n"); - - SetDutyCycleIndicator(TRUE); - dbgPrint("Executing command %s\r\n", TpmDecodeTPM_CC((uint8_t*)&tpmOp.msgBuf[6])); - time_t execStart = time(NULL); - _plat__RunCommand((unsigned int)tpmOp.cmdSize, (unsigned char*)tpmOp.msgBuf, &rspLenTPM, &rspTPM); - *((unsigned int*)tpmOp.msgBuf) = rspLenTPM; - time_t execEnd = time(NULL); - dbgPrint("Completion time %u'%u\" with ReturnCode %s\r\n", (unsigned int)(execEnd - execStart) / 60, (unsigned int)(execEnd - execStart) % 60, TpmDecodeTPM_RC(&rspTPM[6])); - SetDutyCycleIndicator(FALSE); - - itmPrintAppend(ITMCMDRSP, "//%s\r\nunsigned char RspBuf[%d] = {", GetLogStamp(), tpmOp.cmdSize); - for(uint32_t n = 0; n < rspLenTPM; n++) - { - if(n > 0) itmPrintAppend(ITMCMDRSP, ", "); - if(!(n % 16)) itmPrintAppend(ITMCMDRSP, "\r\n"); - itmPrintAppend(ITMCMDRSP, "0x%02x", rspTPM[n]); - } - itmPrintAppend(ITMCMDRSP, "\r\n};\r\n"); - - tpmOp.rspSize = sizeof(rspLenTPM) + rspLenTPM; - tpmOp.cmdSize = 0; - tpmOp.flags.responseRequested = 1; - } - - if(tpmOp.flags.responseRequested == 1) - { - tpmOp.flags.responseRequested = 0; - if(tpmOp.rspSize > 0) - { - uint32_t chunk = 0; - while(CDC_Transmit_FS((unsigned char*)&tpmOp.msgBuf, 0) != 0); // Wake up the link - while(CDC_Transmit_FS((unsigned char*)&tpmOp.msgBuf, 14) != 0); // Send the header which is the minimum size - for(uint32_t n = 14; n < tpmOp.rspSize; n += chunk) // Send the rest in 16 byte increments - { - chunk = MIN(16, tpmOp.rspSize - n); - while(CDC_Transmit_FS((unsigned char*)&tpmOp.msgBuf[n], chunk) != 0); -// dbgPrint("Sent(%u)\r\n", (unsigned int)(n + chunk)); - } - itmPrint(ITMSIGNAL, "Response(%d)\r\n", tpmOp.rspSize); - } - } - - return true; -} - -void TpmConnectionReset(void) -{ - tpmOp.receivingCmd = -1; - tpmOp.cmdSize = 0; - tpmOp.rspSize = 0; - memset((void*)tpmOp.msgBuf, 0x00, sizeof(tpmOp.msgBuf)); -} - -bool TpmSignalEvent(uint8_t* Buf, uint32_t *Len) -{ - // Pending inbound transfer - if(tpmOp.receivingCmd > 0) - { - memcpy((void*)&tpmOp.msgBuf[tpmOp.cmdSize], (void*)Buf, *Len); - tpmOp.cmdSize += *Len; -// itmPrint(ITMSIGNAL, "Received(%d)\r\n", tpmOp.cmdSize); - if(tpmOp.cmdSize >= tpmOp.receivingCmd) - { - itmPrint(ITMSIGNAL, "Received(%d)\r\n", tpmOp.cmdSize); - tpmOp.receivingCmd = -1; - tpmOp.flags.executionRequested = 1; - } - } - else if(sizeof(signalWrapper_t) > *Len) - { - itmPrint(ITMSIGNAL, "Invalid frame received.\r\n"); - return false; - } - else - { - pSignalWrapper_t sig = (pSignalWrapper_t)Buf; - if(sig->s.magic == SIGNALMAGIC) - { - pSignalPayload_t payload; - switch(sig->s.signal) - { - case SignalNothing: - if((sig->s.dataSize != 0) || (*Len != sizeof(signalWrapper_t))) - { - itmPrint(ITMSIGNAL, "Invalid data size %u for SignalNothing(%u).\r\n", (unsigned int)*Len, (unsigned int)sig->s.dataSize); - return false; - } - itmPrint(ITMSIGNAL, "SignalNothing\r\n"); - break; - - case SignalShutdown: - if((sig->s.dataSize != 0) || (*Len != sizeof(signalWrapper_t))) - { - itmPrint(ITMSIGNAL, "Invalid data size %u for SignalShutdown(%u).\r\n", (unsigned int)*Len, (unsigned int)sig->s.dataSize); - return false; - } - itmPrint(ITMSIGNAL, "SignalShutdown\r\n"); - tpmOp.flags.powerOffRequested = 1; - break; - - case SignalReset: - if((sig->s.dataSize != 0) || (*Len != sizeof(signalWrapper_t))) - { - itmPrint(ITMSIGNAL, "Invalid data size %u for SignalReset(%u).\r\n", (unsigned int)*Len, (unsigned int)sig->s.dataSize); - return false; - } - itmPrint(ITMSIGNAL, "SignalReset\r\n"); - tpmOp.flags.resetRequested = 1; - break; - - case SignalSetClock: - if((sig->s.dataSize != sizeof(unsigned int)) || (*Len != sizeof(signalWrapper_t) + sizeof(unsigned int))) - { - itmPrint(ITMSIGNAL, "Invalid data size %u for SignalSetClock(%u).\r\n", (unsigned int)*Len, (unsigned int)sig->s.dataSize); - return false; - } - payload = (pSignalPayload_t)&Buf[sizeof(signalWrapper_t)]; - SetRealTimeClock(payload->SignalSetClockPayload.time); - itmPrint(ITMSIGNAL, "SignalSetClock(0x%08x)\r\n", payload->SignalSetClockPayload.time); - break; - - case SignalCancelOn: - if((sig->s.dataSize != 0) || (*Len != sizeof(signalWrapper_t))) - { - itmPrint(ITMSIGNAL, "Invalid data size %u for SignalCancelOn(%u).\r\n", (unsigned int)*Len, (unsigned int)sig->s.dataSize); - return false; - } - itmPrint(ITMSIGNAL, "SignalCancelOn\r\n"); - _plat__SetCancel(); - break; - - case SignalCancelOff: - if((sig->s.dataSize != 0) || (*Len != sizeof(signalWrapper_t))) - { - itmPrint(ITMSIGNAL, "Invalid data size %u for SignalCancelOff(%u).\r\n", (unsigned int)*Len, (unsigned int)sig->s.dataSize); - return false; - } - itmPrint(ITMSIGNAL, "SignalCancelOff\r\n"); - _plat__ClearCancel(); - break; - - case SignalCommand: - if((sig->s.dataSize == 0) || - (*Len == sizeof(signalWrapper_t))) - { - itmPrint(ITMSIGNAL, "Invalid data size %u for SignalCommand(%u).\r\n", (unsigned int)*Len, (unsigned int)sig->s.dataSize); - return false; - } - payload = (pSignalPayload_t)&Buf[sizeof(signalWrapper_t)]; - unsigned int expected = sizeof(signalWrapper_t) + sizeof(unsigned int) * 2 + payload->SignalCommandPayload.cmdSize; - unsigned int maxAllowed = sizeof(tpmOp.msgBuf); - memset((unsigned char*)tpmOp.msgBuf, 0x00, sizeof(tpmOp.msgBuf)); - tpmOp.rspSize = 0; - itmPrint(ITMSIGNAL, "SignalCommand(%d)\r\n", payload->SignalCommandPayload.cmdSize); - - // Set the locality for the command - if(_plat__LocalityGet() != payload->SignalCommandPayload.locality) - { - _plat__LocalitySet(payload->SignalCommandPayload.locality); - itmPrint(ITMSIGNAL, "SetLocality(%d)\r\n", payload->SignalCommandPayload.locality); - } - - if((*Len == expected) && - (payload->SignalCommandPayload.cmdSize <= maxAllowed)) - { - memcpy((void*)tpmOp.msgBuf, (void*)payload->SignalCommandPayload.cmd, payload->SignalCommandPayload.cmdSize); - tpmOp.cmdSize = payload->SignalCommandPayload.cmdSize; - tpmOp.flags.executionRequested = 1; -// itmPrint(ITMSIGNAL, "Received(%d)\r\n", tpmOp.cmdSize); - } - else if((*Len < expected) && - (payload->SignalCommandPayload.cmdSize <= maxAllowed)) - { - unsigned int dataSnip = *Len - (sizeof(signalWrapper_t) + sizeof(unsigned int) * 2); - memcpy((void*)tpmOp.msgBuf, (void*)payload->SignalCommandPayload.cmd, dataSnip); - tpmOp.receivingCmd = payload->SignalCommandPayload.cmdSize; - tpmOp.cmdSize = dataSnip; -// itmPrint(ITMSIGNAL, "Received(%d)\r\n", tpmOp.cmdSize); - } - else - { - logError("Invalid command size.\r\n"); - return false; - } - break; - - case SignalResponse: - if((sig->s.dataSize != 0) || (*Len != sizeof(signalWrapper_t))) - { - itmPrint(ITMSIGNAL, "Invalid data size %u for SignalResponse(%u).\r\n", (unsigned int)*Len, (unsigned int)sig->s.dataSize); - return false; - } - itmPrint(ITMSIGNAL, "SignalResponse\r\n"); - if(tpmOp.rspSize > 0) - { - tpmOp.flags.responseRequested = 1; - } - break; - - default: - itmPrint(ITMSIGNAL, "Unknown Signal %u received.\r\n", sig->s.signal); - return false; - break; - } - } - } - return true; -} diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/syscalls.c b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/syscalls.c deleted file mode 100644 index 35a949cb2..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/Shared/syscalls.c +++ /dev/null @@ -1,296 +0,0 @@ -/* -****************************************************************************** -File: syscalls.c -Info: Generated by Atollic TrueSTUDIO(R) 8.0.0 2017-10-17 - -The MIT License (MIT) -Copyright (c) 2009-2017 Atollic AB - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. - -****************************************************************************** -*/ - -/* Includes */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "stm32l4xx_hal.h" -#include "StmUtil.h" - -extern RTC_HandleTypeDef hrtc; -extern UART_HandleTypeDef huart2; - -/* Variables */ -#undef errno -extern int32_t errno; - -uint8_t *__env[1] = { 0 }; -uint8_t **environ = __env; - -/* Functions */ -void initialise_monitor_handles() -{ -} - -int _getpid(void) -{ - errno = ENOSYS; - return -1; -} - -int _gettimeofday(struct timeval *ptimeval, void *ptimezone) -{ - if(ptimezone) - { - struct timezone* tz = ptimezone; - tz->tz_minuteswest = _timezone / 60; - tz->tz_dsttime = _daylight; - } - - if(ptimeval) - { - RTC_TimeTypeDef time = {0}; - RTC_DateTypeDef date = {0}; - - if((HAL_RTC_GetTime(&hrtc, &time, RTC_FORMAT_BIN) != HAL_OK) || - (HAL_RTC_GetDate(&hrtc, &date, RTC_FORMAT_BIN) != HAL_OK)) - { - errno = ENOSYS; - return -1; - } - - struct tm local = {0}; - local.tm_year = date.Year + 100; - local.tm_mon = date.Month - 1; - local.tm_mday = date.Date; - local.tm_wday = date.WeekDay - 1; - local.tm_hour = time.Hours; - local.tm_min = time.Minutes; - local.tm_sec = time.Seconds; - ptimeval->tv_sec = mktime(&local); - ptimeval->tv_usec = (time.SecondFraction * 1000 * 1000 / time.SubSeconds); - } - - return 0; -} - -int _kill(int32_t pid, int32_t sig) -{ - errno = ENOSYS; - return -1; -} - -void _exit(int32_t status) -{ - while (1) {} /* Make sure we hang here */ -} - -int _write(int32_t file, uint8_t *ptr, int32_t len) -{ -#ifndef NDEBUG - if (file == 1) //STDOUT - { - HAL_UART_Transmit(&huart2, ptr, len, HAL_MAX_DELAY); - } - else if (file == 2) //STDERR - { - for(uint32_t n = 0; n < len; n++) - { - ITM_SendChar(ptr[n]); - } - return len; - } - else if ((file >= ITMFILENO) && (file < ITMFILENO + ITMCHANNELNO)) - { - for(uint32_t n = 0; n < len; n++) - { - ITM_Out(file - ITMFILENO, ptr[n]); - } - return len; - } -#endif - errno = ENOSYS; - return -1; -} - -void * _sbrk(int32_t incr) -{ - extern char end; /* Set by linker. */ - static char * heap_end; - char * prev_heap_end; - - if (heap_end == 0) { - heap_end = & end; - } - - prev_heap_end = heap_end; - heap_end += incr; - - return (void *) prev_heap_end; -} - -int _close(int32_t file) -{ - if ((file >= ITMFILENO) && (file < ITMFILENO + ITMCHANNELNO)) - { - return 0; - } - errno = ENOSYS; - return -1; -} - - -int _fstat(int32_t file, struct stat *st) -{ - if ((file >= ITMFILENO) && (file < ITMFILENO + ITMCHANNELNO)) - { - st->st_mode = S_IFCHR; - st->st_size = 0; - return 0; - } - errno = ENOSYS; - return -1; -} - -int _isatty(int32_t file) -{ - if ((file >= ITMFILENO) && (file < ITMFILENO + ITMCHANNELNO)) - { - return 1; - } - errno = ENOSYS; - return 0; -} - -int _lseek(int32_t file, int32_t ptr, int32_t dir) -{ - if ((file >= ITMFILENO) && (file < ITMFILENO + ITMCHANNELNO)) - { - return 0; - } - errno = ENOSYS; - return -1; -} - -int _read(int32_t file, uint8_t *ptr, int32_t len) -{ - errno = ENOSYS; - return -1; -} - -int _readlink(const char *path, char *buf, size_t bufsize) -{ - errno = ENOSYS; - return -1; -} - -int _open(const uint8_t *path, int32_t flags, int32_t mode) -{ - unsigned int channel = 0; - if((strlen((char*)path) == 7 ) && - !strncmp((char*)path, "ITM[", 4) && - !strcmp((char*)&path[6], "]") && - (sscanf((char*)&path[4],"%02u", &channel) == 1) && - (channel < ITMCHANNELNO) && - ((flags == 0x601) || (flags == 0x10601))) - { - return ITMFILENO + channel; - } - errno = ENOSYS; - return -1; -} - -int _wait(int32_t *status) -{ - errno = ENOSYS; - return -1; -} - -int _unlink(const uint8_t *name) -{ - errno = ENOSYS; - return -1; -} - -int _times(struct tms *buf) -{ - RTC_TimeTypeDef time = {0}; - RTC_DateTypeDef date = {0}; - - if((HAL_RTC_GetTime(&hrtc, &time, RTC_FORMAT_BIN) != HAL_OK) || - (HAL_RTC_GetDate(&hrtc, &date, RTC_FORMAT_BIN) != HAL_OK)) - { - errno = ENOSYS; - return -1; - } - - struct tm local = {0}; - local.tm_year = date.Year + 100; - local.tm_mon = date.Month - 1; - local.tm_mday = date.Date; - local.tm_wday = date.WeekDay - 1; - local.tm_hour = time.Hours; - local.tm_min = time.Minutes; - local.tm_sec = time.Seconds; - - buf->tms_utime = mktime(&local); /* user time */ - buf->tms_stime = 0; /* system time */ - buf->tms_cutime = 0; /* user time, children */ - buf->tms_cstime = 0; /* system time, children */ - return 0; -} - -int _stat(const uint8_t *file, struct stat *st) -{ - errno = ENOSYS; - return -1; -} - -int _symlink(const char *path1, const char *path2) -{ - errno = ENOSYS; - return -1; -} - -int _link(const uint8_t *old, const uint8_t *new) -{ - errno = ENOSYS; - return -1; -} - -int _fork(void) -{ - errno = ENOSYS; - return -1; -} - -int _execve(const uint8_t *name, uint8_t * const *argv, uint8_t * const *env) -{ - errno = ENOSYS; - return -1; -} - diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/USB_Hookup.jpg b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/USB_Hookup.jpg deleted file mode 100644 index c207456be8b93d52b8ca9c48e30845eb3f190dd5..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 838421 zcmbSyXFyX~*X{{+5FHB^P*Gt}snUXqf{m((lz@O3l_DTXR3wp>SO!!S5s(@kRB956 z(gFm?D1u6eg(jpB0TUEWB18x=g}ZUynfLqg{kZoYIGn{kyO&j-wa!fc%tz=qS4S5| z2nK^e&fo`{8CrP4;Zk@g1i86Eh7bfTgft;tXda+o;3mVCLTcbSAKX>2-+s|c09_B$ z{x?rMOy^(v4Qwkk2fT;P=7gF5%D)W!-v_h!MXv<(=j-9n++TShNO9x$f9Uxi3oU-t z1Kus1TWI+!KWKNMexcPb+8EHYJ)FH3gB!N*+_}gQDEw#`1|71|X5-Pw=&0FuU{t^Q z{_A<}R5<#gDLUlhMk~|prWWQ9WU<|R$FA)byDZE%n%nF$x87x84M7{O=KV7UwTP<^ z{-rP6*!^LeK)x&fM)57Up;7{4+MS*t>K8rSGJ{{>}qan**i8Aoaid zrS>>o?ce&z>2v-~uS%c$FWs2F;6H7Fl}KOoANn^ytN&Z}dHTv<>0rLpI@053+nNjJ zMXf76?N=Y>Zr@=IrKkUwe)vzH&9`rV2>VZ+V3i-L{j&xOK0ciD4?XYm;nuKs|*zH1<%=an7u%quvG92Ucj3-x{x%_;@AGz81C)`UVz=b66E-&AB(`O zfO2Z4;MH8v)7d)0AZU&S82vwaU|^>Ip(nrz_=g?`x&NVI;JnPPE7ngO>eTr{6)@=b)$ml${5y`jx&Oq<@B1|Cf-k8?#t958<-W$9A*mJ3e$(_!er1i^cDI9em+7f zXeCSwwhOic1_wEo!WO|6!dTE7r~_(;UO)_}2U-hT1KSI;2YD=Ed}svfgIpmvWDD&9 zKX#BOc)t$j2y=k#0c{Atdlpmx6&6M~v>0%-02l()um>gvCBH$ly%+{#<3LdN~Q0q@f49d1cZO{kM`T%Hu9SjX}1i+5KDd&?3HcW=1K5pr)aj8CDGh{hkOi zrTwQ{D*(N5ySbIaK5MwS$v!K%jfs_wIoxE&KF6IVaPxzX2e-p5Ev(^i2-+8NOD-${khi1!a{+nkI%*L;D@7eTa z|E3GT8UAnjnt#(p(E4BL8lcXp*&^UF1NUs(27f<)17Zpa26yb=|NmM|@Lps4-|4}i zKM?mi~ZuU7V z_2>OB5_jY2Q$c4p21lQY+!%BU6>{O!MoZJ3J5i{Op=Rc$JD?dhbO2I=!DfH|bIqAI zXZD&uckY~d3+69aFncdtq_Jq>LiL3U7N~2gt7|L<*Mdb$mTE3uGE2`^GFyDM6!=}d zaKXaa9RF|E%wN#5g$q8;`#cA>8B$vYo3jiy^8&C-2%N`X7Z~8L>z}>9NL>SDs09lN zn=?lZbavicAZlR=v*LX2vU$rlneUsw!sFC}&F5EITuFPhP;dX!XIh@`zw29`zHoJs z`l{7y)@uK5ux0BuLn~{z&5oVB4jgoFbaHla_3}pe_#X4~4+;(mJrfol5p^*di@OvP zd+m?Jr0X|sCZ}iI%goBo$<2FQP*_x4Qc5CMRoB$kQR^ETpSQkfYk&Fbbw^isPjBCc z{sGp|@W>~=VD$5svGEDXkI5K7aW>j|HdBuh?vHW#P*GX^);hTcl^{`CaSuh4<>K^sR<|ADvKhj`hXWsp6joPL~av|WAc<6D+LHC2>sht53VXhhSbDtZ1R zS#1YnU%y#hfY4p}Wd>sTYjqkMoO|UeGpUQb?94iXkNiP7%3YcpAWjfxPm^`(RlK=r zqG$_)x1EGP@AoZxuj8;GNWST7>{QYB3g>vY;u+{n#470rW8YEU_89+tdaLwTos{j+ z4{f$^kbJZYh;NltnosW=Kjho1vYF0*=Km=+y7uLD)X1M7UM<-$#{I7K8p}9|`m|)p z$0KLE(Iy?Q8v@Rn98M|d3HIG^A%$nO^qx47)^g9}@$0CD>_6!?;|bedn?1TST z4#vKV!ya)p&4yJ@k|kO%N11La(s!)rt9aUbKlcDS1^eg68Axk)AjLG;ak0pR zh+0$9kTLbv1n-DI4*MMMeE|Pyt*KMdiy1}|f0WHY)lG3%*bNcKd@m*+K!vC#=NC7v z-tMmF7=YffRC<7r=-qsCbG<~v=p{|i8sFitzfuxx%2ULqJ8n1>f>qQ86gWJjYUlWk zq+#Ds29$foTBxOMG4WOYm09HGwQ+L9wqkQ;E1K;QBX2p$m{9Z{e>iDCqoZ7RNXfFa z+m>eIaU&nTAi!V)snJ_%^-Z6vse({>@9v_gRX!u%P#p?hj2|Hr(Ug8Dr7C|& zh8>^iNmGf@p9ab7T)&n{?ZoCL3!{L;U3xQ+Mgm{2uf~75Z*F`Wl6cm{u>+48=FqvM zm@DM9!A6$xJhSiRR%LTF9@Oi$O2b%d&oLxs+>(<*<_?0ElXWiY`1LZv;0zR-Hv^f? zBL(?z*mVjgu@J$#D%SD zd2Bf^autimEt0@r^~jvr!v$BxDE6l z+PJkVlkt&CE}OtDb}njEFsNe0&6cAbN4UKjHsX~V!s<2F#UNNT-x+8_u|-mdEuJt` z5+qQG{e!y*ON307(AB`AeqehQq1Me|usll^P78P=YYD9BFEq>WUd~-^T~EX?rTCB; zD726(?+A|EUn!-=_k7V|pnV0%;fIv#Iz8QJt^CfHgUH-)pG`eBojv3iMybs-)z62< z`_x6Ff)LEK)}E+$HcS`-b6JDOF`f4*+vr}#WAQV8Toc6WrEsCAEX$UPo!oG9xsfqSA}rcr6vKSKpSJCJ6ENB zF#-{=KAp@Cdl>kJA@i;+TW)7zCzf0B|8Sx4(cyHtjWo<}ZX98NInU8&SwUEEJ1;xW#hfoR zs=I5()s4nWnTJ(hEdk3Ne^?p*?pD5~*vJ!&;AXN_U0uS7P>vmDs4xf|(LQ;trzO9x z;8BJ&7eiE%YuDw+VR_QJpS|vu7`@sfJPQRqws7vTm-qYSG(u7VGWVW#T0z)@C}~1o z4x5N$O!OsX>(sP!2(kBXcks+!tArce6&giG&K;fCm7=X0bK=>D;(4uZgv|3aCCjZX zn6s?~$xLU5!DxB#(*Y&l`(oKOHtF``_Do4!->v)|X3SbLJT*9%J<)S|Ue%+OgS!354gqV7I(J#!iMT^Vn?23200piUbzcMg3yQuk-oda}Ee1g9A3%K70P zkFt}Y*x{Y#N?u;NV{lqFRyhM%Z{Z%#&n0DS_h}cfz}i_=s5vRSCDw2)WIdbKRXNx$ zR<&QI!=2=G8!pomXRu#n7mC1(zxSXfl;X@8sK~ZcL)U(=0Np!?4?#8``C#y2x!FCT zPhr|0#O!IGeA+0N%8v-nNeP(7DQf(moz+;%Fc8uLFia0JbYLn+(K`)!i4TB2hlvf$;GL*%dkcdC$;idvVdjfb{)?0p}+b;WnsHOjD2P z9y@S`Uy_oGa&O2E5ms~kbNxesDg#+qwPuZ00gJs~(IhPLnBe=KML+Vc zQnbuK-?~SRer}NS`Z6=N-L%r{9JE6Y%|MsD>XdymP)k@E4(_Cs98TpQ7XjW}*n4x4 z<+@a5Ux`sXGph*0L&F-eg$VhJ8A#I^y)%f_=`>EjW@LRbV7WcFQ=5VQ!g*R+{6LX; zHgcdlH3YW zf%G;{7wLs;}XYJ+D_G(|f_@w1n2u4Z@ zmepNTjz!dQ`(^I(8o_Z>iPZjw;ezrq^ULkLsk$yp6h=8e2}Q?=j#BDB#nXk>o~!S+ zgbpUt%?6P}5q80mO0jZ5-fB$)0!@Oy_~%J34a0qOxv!m*DI=9MSFMtf#;=w!sp6w*Rq;1fz56T`%p{d=Ub%A# zV+O)L40~sEA0^qPTDiz*Sv&2Hnvm@&*2&4w46kQP%*MT>R~cYCHt#DpCpHNiWLPCD zf`471UUU~GK|L!*83)+6NsflCVK+GPn%(^rO#1Vtaj}Op&(vMcrp9_@A-R=|272=4 z^_$pzNkJ1Me72OXjmiC5i%VbyIm2h5T7|vv^sO8kZ{L{=obC%cwjd=ni$RU*&b?-l zrkd14A!K-o2cyTjr2sBVenb?6g3S>Ae0_PwM5TS3l$3AjoFnrK5O5#Vm(+>Pru~52 zT3-_P`FP=b?Wca0wRLp_7N$Mj`E}|!)LRA8#7%pZ@%k1o7sCp%NT?Dw@0ildy;{*5 zNXM-dzKj)Na`6&NuUyyaAihs&zc52Rxr32PoF@OleeNhK!c`8IF3z_Qh02K2VH1k< z1>dRPm0PjiY3j-k@?MMIxMdx#3MTDGq3+jesZaJfzcq@^WWvWouAMl`d2;$736}00 zn}x}iQyTxQc6>JkxVO}g{JR$oE6xlz2tjaZd|$3=ay>-VHzx-xC^YPzFXSyPk`_FwsWV>dE3oGxgP1AaY+kVKh1fvRg32g^{_d1v2012y0?gl*F5u-H8!fL%ZPi-`DfNa!+MqXw+${ zx2ri-*HFn*HSfGo6$NGu+8N4jNaZ5fM?%ARCJOt}L-GvqoK2&955a0nSDxPT6#EN1oYcpix>F)IEzYY z^O(t_dJ~#5F9ScoK8yCx-+b}2k(0cApw{<6{)-+@w23KKo-IZ_uC}z_zx8plQnUKg z^W<$6T*{V>>)o(Ix5ou6h?e41-$la~_bo5|3Gss(|7126xHr3(ad@8T^QrA#kc%LYRF>gmgo<39Z{S>I@N3VO`h%?P{D5ymJ_@UlGWb)E^+?Dt^zTrF}r z+X*wrJOpDVVArFE%lE^{qx=n%`4#=Sp920Ec90PUBHlP1#Mvb@O<(zFo6pXBd9>-wfvl_DhYpd$E(WnjZJ5T%ij#?#B%oE zDLQ74Sa5ZRy?^%8>Xf|GYj*c=%H?f}F?brfToujgXb!JBL?7MOaQ(5+KE=r@jT^8l z{xwbBoB6})c3h^Zb?6{@j9ERMmnFb@)TiE)mYSd!2kw8B-}d!zBf($~J$BWeZ3fX^ z$pNccCbqrl?jsM5)eUK{nt=koc4O%El)JB&-Na^WR`$(1=R0Qqydi&CKgZ?Jy% z%T6m>-Xxj!NYKW@d& z&SM*}U$W1}(_4=qR+ujkC9ujD6A^dtlg2hT&)Tk_2~@w!=;lX=R%r)3J*L_RBxX{w z&as0g5@9rEh&1UwJ?-Pfsmz*zCVS4;4cK8Cdmn8+?wH*99*u~MFIQN}*Nh||rhL0N ziZXXjt6L9LSlci;4NjE@h8Laty{X=>!cu((YHFGE%~GwW%s>yjsDrP7ArNhHAKgu5 z(ByRC(ca6b5zF(mC`8QqTpf9D=-De9KA9`%gR0-HeL^Kcp~$A1du8pJ?Xossk&t^h zRS>E&p)_Qr@Zi|4=ZEd>2O}zwvBUSSc)ymUW<3sFOn*UXEGFU*2yjr#eK@Y4%Dvv1 zy2qS8HL%&D2_?m&XCT){db&H`eoqy9ce#u@K16fMY2&4bLdgdoI}oGJOZ~zyx!6RX zK%R*sLqD$@LmdgZi(ZwY+I~Q zHR+_co|!1;VXxfa!G+Bc*1%YfaCpO`fwd1$Hyf0dnrD6TjA!1Pf!>j{Tz|0GKzH!0 z<9sx+u-+jfe6(7whZh|*raU23E5n*(xy~|dcW;tFPt>g+w1u&E*<)G8Mw7a1#)JUV z$P;?D)8Teg9Iq@(tA5=Wpz*z%d%Gnd2rHf{W!Jvxm0gne^l{hSUW-SHk5)x~=6%X>v|T@sHf>X!b=py8zSq`Pi)4qF6l6%(?4s&~=|K9*8|+3BQ8^b{dD zh`MS5&x*+|Iy?hqxEZA^jx;l-;eldOWg}9F8J@2%b8LVP@US~@AL8w}wdOI*zCTY0 z>8%ZCli$ZUC!@__TvJTwALy+ zrNzIn%+p89gG!k4zWvxy&UWV(`mIG=mU%0B26WE&$bmvxWBWtbBH%`cRx7SxrBPd+q=mF#z&6LG5tQV#MQxmGaPl5; zW4`$4(|B5o4_C>8;Ke;arpIPrKTl<{=&?zGw5zF8^m09OKMTT5a<`>^xDErE9U)YP z6O#r5MBUh=$Qfv_v8yK$@H=Re9um1s)54?W2LxrDXwNUQ4G z1DuUCf$aP?w?;InAnRI+!9q44T9+~k?~(IjFQY$Iws!@Hy>_yAHVjwx;as+=GTH6f zw8}8>pnjT|o!ZE=VIDY)KaCH;WJjA0eGq%Dr{&C(1&H4Fl-|uWY3Fuw*OE;Jk%kQb zf+-Bchin-|ih=IWU{NITJ)md-$zyQi+ame~+AEyFb#31b_Ej@2Pq9yrFbf0 z@6NymWMGZ*S@z2OIJBK~++-&q=B-k)_u`t4PUZwya2^YR5TX%)T~2#Nb>7YSU=87RJo)*`Y` z41?JLi?;g6kl$WRR;~fhe4i|no_xPGLP5vn50$L{%k9}E?jgZi{dlnLi>{LMiBSnG z?E?+R%$TZf50k$vR!?IUJ?UGyY2Yw-fu1eli>F-P2Iy&dX*RIP+^G+oS*g~=EfX`|C*E7>C5pKgfo>Eow zq@`Q!dtYCZ`pRpZBxnZOp(v0YMMW71oAFX9erinPHrmKWG%XAG=^b}Rghw%{0IqQl zo#!o7X$P5OrU;GY`(h8e@yy&a@qtXmZm;YJroynSrZ3}l;3FK`Kad?8&rnz`+lD-) zmUUb=TOml@UK2s2qGT;1mX7FS!q}PnomHkYP%a)A=X)17(krESp?(BK2cR)+2lD}@ zF{EqJ9sgGcudNzjVUH-OCdRh24HDPOlI5RsxFKzd? z>@c=cEROG?WA{A5QoQsK>{PiRn~%01P#K=*tRrf%U#q@)2N2)9;dYGhjXWzE8^q02 zk*L_1h`3t8swljvx1nA}V3o#5*0x9pKv&RQetL)WK^Gd6cXOqcG0$Y1rfVy8&8L&V z(z#jM)P`v1va5f3DOzh=zFH`G?T;nvvDYSMplGt=r~XN91AYXps_DBeWK+>%qP)i_ zCZ!%Fqkps|jnUc<#M6}#rU;hv%|erxT$S*^=$d*xz*2>z!cf^h6nnJ*GgNG>K&u+iTT_j-J=%J=8&!aF=WYTgXgN4mSBLJJ3u#}z`#hLeDg-XvF>r+>M?_Ml(?;%RkFl&CViYaEl9 zMo*+SJNO{j1`~FZTDiGDH!H*0q*N)%=$oN;wO!y+&bCS^X)6g)0~K<%t^HE_)=>1( zXkDHwx&vPB)MxudU$XT~>Gztko5NO10DjB%>KwRAk_gmSvh`dgpRJ&)WAeroWsJ>KX^WTZ{*pHo zYV;XqkaM|H#ubm(@9)^ec^DZ#O5%?6QQYh^q`@Qda+US{l#RDEE;idF@Q4DkP4`V- zu?6)JS-QH*>3m(tV5O3GuNUQX^v({IR|8#dy649(Qdf_J$Lf=Nchf__T)P#rIe`&b zKlgOjscBd@rti#Lw7B%e;t}l99bc~xX(Ib=h70YrW}slg0G$-VPYY|>`{qrx#Y^o++y5s@*dC%9LK4QS* z=BE}Mi!3(H7I#sQjkxC!7KF({wD*nC9~@Xu5uRpBjKF|GNZQM&x^n9+M(g9LI+}g$ zp1vjHCbq&ip^;VOS*HMt6rG^mD#hA!0|6>QZFEc(xC0GPYhh`&I5cOXaz$(fuNe`a zi`HWSR865y;yJ$mmS=q?b=r@RR9$J1O+L(^i%}TYLl^G4*v_S02^xfmkdy**ib!P^aWxdE4y_a2`lpOSd?UJb44b-6 z9gd2ZABd-gA@=xAhoL&R<9(3RnmY@^fIrN~zgM&B(vZ*f&H-Q&-OM5l9!G_s0JvE4 z($e%}d5!&`|J9*e7C^U|yKAQwanlD}2x*F%Ua^{w6!iscVW!hEk;H$!zxq5wUL7#f_8~h*!&36nP?N5p3$jpQ67yn))i4ry6BBS z*01Kjt?YYjo0+ii(i|KR)3mmi=Ui-tMe+ByZy zX}4F)8^0?0dHSvIrM`v@vKIeE`bgpf291>-q8uEOW@T|-pdQdKd3G|?N3p^mu;sI; zm!-+3P(MrBG|5Kl?^Z%W)p{Bp=yQAjiK?7DR1eHl-ZvnB9IJ5lt&StqBxEkxMPIcJ z?ekJfvVebr^M?FG@gce~gj*=%+wf93@7udMxkq?XLi5+desu~SPEJn*2>NAYW{U(Z zt1pyOu1UjSewl@D73%jpwXJoh$9gP60`h6n`jTxEKyJ#%$PUhN+f!mxQf{dfo$)(i z;IYdpxXLW=t|+WOg+BO5Z5{o&n`7szOUO)88M}brA|5Q{?5?vVOq0`{Y#7hvoehQI z_RT>4eYWEAEK$W(vin&w^5c$M`gis+W})QJ#OJRk>iDCAV&hTtg6}gB&-*!3my3~- z%RJu^FP+fBmRmR)GZY6zLTOQ8SwDstZIhUGIk0Bsq*joo>aE<0+?>xZ(%`?$PsV^5dfb@u6ad6|v#H1()r zHuw|QB?9v_96!<3I$>!E7ZYb~g2J>v&tx|oKyxP)HGPP?-`0Uuzue8{9~W|XLN6V3 zzof?UD2ygJsUs-N$u|>;eqdC!TTEzxf2gz_Wxk+}X75~=RGcxHhb7VkkzJ;6AW-)g zhK6Et$rXs_j@%7%P;Kk|62jQhJKNq5(UUIM^O}JTC@Koo-Oiq%j;lKta4z75dRwX3 zIcN0<*vn6@@2K=MERaoH2u*LfAxN5!%R=R+ zGBysVEZ8)2nxJIcnf=QhYkKwi^jD03b(Bq7r>ntBULN5U}tuJB(;lnYVC7n7n{rcxSJU5{L$;=c&zy zbCV@BEXTy4;`p(2$54I?MoLf4zTOcv-!Sg!%M7xOP4K{0nH$4eBn=ppS84O)84lsdg8)mzJD~*7o z^1oHR>%H14UAxw=1)Ldm1wGULJc}ZYk`QV=jN;4O6$`!>d3|*WC|%fjY^!dY!aJ8m zyUzR*-ql`!28w!k)z;K7IY5@PuA?t&KB!meN?U|FcZ6&eFipdTQ4Q>g_!{6H#0&z4 zw0FzTHd%{UN)p<1(C{JtDcMf~DXtBHU!|)>y$9!=F`-6*4Ii3#yaI=2y9nkZr&sZ$ zrE+G6sBJmyxf_tOz{`HQJHC0s62(@sY@}b0q%>fr$a~!$A+E4^Lc+zaAU+ELyo=iQ z+q}PpswQ`oavs+8l5Z@!jd}?p33`b5DeY{WVjeD@axg#P>4cCBPjuf1Vk?)j|(w)16o3M3Udgi>g zv{mW@dsa*nlGD6_>hM>M1C^_Jm(eCh`C!GXdLYdXPM3uoNX%&?lf$*T(5=A1m8#3n!Arq?{OAFGV0)&){ z8Gg9Xclx|E!hU=8c7%-1qRfjQsGAS`iD$lexNMi*OAz*2z-R<4xmAE6%4;=Rg#B{H zME8hNZuUKsxkddr3NS9hWa$lc^4fa|y`#~~ol0SS64VM zLmc@MtZob0Okc@omDU0oERxf47rFxkp=)FSgqr-UX7c<{LOI`}I-Z7~=rM19C(>qC9m0G{+Z8@ z-5SDcS6(=IIBD-5r12_P*Cl-F`jh-t8I4 zrp<)IZGC%KVOKW<&fm0#u5uoVLdEa%L zJ<5`Gbh2?OTelmqEev3emw!DDGz<7`D}9%_FJV;F*xJG6rk8%3BtB)^jLXqok-3md^FkD63u=qXX7LOJiC%KwJ0>e zmt`mBawt-KZFc-ylV_-oW;;Y=xeIwWW9h5GGxcM1{{qdP>?JS0zgETdq1_+#9{IEA z^@!xIBeP~nsvmW{@%6;33X0+YpK^m7fXSue9QJHWKbW}Y)j$d%#ST?`>vc7m85tCK zT+c{+U8q3~N61{0WrX3;Z(<ew*5cPqiGMT$&BH6R`P1EU>$>J5H|vV>kF-~lF9sG8`HpG_ zsB<4s>ObOlBOGW0d4A0Ulk2lzd^I_6|^)m zo8EI!n8tF6?=`|RbG*s%_%q6T#%$lFs$T0o8)8gCvii)I$7~edlE$x@J|472cFCYQ z+yA@imp;{7<%Y0*A;Box^>a?m%YCd;tm<~Zz9 z78@aM6(t67H}q!Qv2V_+yy)qGAo4LoA+qp$naL@oI`E4(iI{P-?}Ad^3FFSPr;#Wc z9!Z-dnVB$~?kj+L-hf9vf1KhUp6S%WipySos;+8n<#M>pzoxb}$=!HkzpvPoRS=Di z6gZmHW?r{%JJKU=dDrP$ZseEe=xcPLjG^#eCo?V()mo$>RemCFW6i1Me)=H@o&>0K z-jlvz(!`+%Ynkr@GLIYa=lYWeLf_RG4t)MPA>1(e`){26At?`hr(@XOp*gSEsa#4L zN9(v5!`oEP{I!xdT(0*>Gr2nEO7*Oq>+$_9wV5jLk5x%hL6m`d#+xud*UB7vbXGaC zG}&b0RiRxUSL$D8@)w%Ul|_VS2BX;U#!5ybsaoqR5OLerQ604I2{EGXyn`7G`)E1{ zF?w?-ftAiNW9HLbcn_DayR)q&R4_V?53EV%J-792TXtgUxL3+wkrB9aJZqoE(@cdi zy>*gQjM;)?BKERr0vWjoU-+nu?Fzi)htpa@Iws#Tjs$Zz4`qf|s})_BlCKr4X{y#8 z27ZBlApTaH)DV`x7tH(kZUx81qFgz)gPY&Tl#kU1_K&r{Yw*w8aYNLpSO77V z!h#ql18bJH(`K3U;`6 zx`NPDLtNzgi5GW8f>uph0}OGp$UZKq(08yNxYusZNsLUL)^updL%kH)#KwgL==cgi zyv130gU-dc?qdGK1*XBA{j|;9xd##i#S$7n6gh;PN;Knr1VbQcZGwx&=(y>;T-Kgc{Aj>L{mpvm!+v3D4(Ll4mEO0+%kd|ew zZet_&uCjRmf`^BSLN)}=q4L3|-ZFT6!&caCrhK1DJ3fwx6)UjBbs=^6O#mytX&`vp zS;mVA+j1}VrG)Tj4Tzn~=7*NVB!Zygz5=u$@_mU%(Wx6eS_oV9)pIv7M$V+lypkUb z*kZfAZ!3k&BcHwcZxSwbB3k?d8MRk9+V?xONR~;M+)QkKR=&mOIR$qq3Csb1XO-U? z6h>^y^FK3)*aTcd#63D^JvvYS(8>{c?wNr;TDceuIt}`Vj?|u`o9KSESqc!?uBRS) z$SlX-8;~^TPT&ubN=buAu%@vEL%}Br$~;_xnt46@c6-_UK5XIBMw?|%4PVy+EBr{W zRm{Y9-wVJvJWNeA0oo%E%p*x~YHNQ6=Cz8c-^%dzlAuXiR4@O1N`5GrHs;)iG$9Pw zW7F+(p8!9k7g3#kgh!)^6Iht6pve5(0A*#~W&O1H>IWT6=d!8`b`ghe?#}5E$*7(c ze%U5KZ+@o+;1K^LM|0tpyo`v%-6H?s)CTWl>(Ac)W5BVrCV@9x?D!}EFJv~}?^@o# zs_8$)zh%QX*A`gA|lp8WpYy3V!P z(bg>z;nbr-Lwei9a8h7r*pse$dQ1zzP_Z{YaW%kJ)$qbg%or23yWkpnAviM!fGOQN zet@3h%&yCPfICO@BLTJNi56j?v_e1ZgY;|zQO;}i>X=ic@62nX=>Vt$E<1-u^$0FJ z!zs%8OG8mrLDN}xj)K;G#b~hIVZ)g@KPF2*o$d+}iB!4~CvZX2KIA^N(2&5(Ho$9) z%yp6Z=AAuBSi+?b7K_a+GF^G{aRC}=HT39-5DTsdB7oF8+(fj;H$+d;0H1x@yRp1=LIyuG~}c)n6BqiT|! zI%s4^8Sxy512;gi32&`d?nziJ2$7M}M&F$F1;%_tHe(q&1l7T7JtRHF;h8a&V~bz) z;)4z87F4Cg-Dl#{X`Y2>%)+m_N1N-j7KDbDht%#VPmV0lWELcV*tO`46CyD3TjBSfr zU}PZKmk|Z5nBv#94JyNw^Ex9Kd$HF*(`%df8e+ZXP%sBCbTY7u1hMty?wCRN(nqC@ zqD^(cf^*$#(rWSYD&r~PfpJ9HZzwr~rYtUYlfRNocNb)w-Dn@z?CU0_RcCVtVVu zXtXD6?e*MrUThJ91q|n=+Le(uX!SB$_}EZg67a0xP|i!!txpit?>MkJ!4BbWnEsoSrmz8mAh!)7}zT#G*ZCEPdQ|{N>=wCjyOM2A#My)TZK(>YZahq z0l?{ToAJc3f=7&Y;@=nu0E`PmFSqS9NNU5x?$LDt>&CShoY z%6es#)orE}U@qjq7D$f?(9%h)_sVbN4F=Y# z_1}tF^HOh%+(cz z8LeKE^Rp@awN&>Kau}J`D38`U(Hju8ic|iQ>AyPb_x&}lz-`YP^grDuZ|;Bl)o-A> z;y$7yyGx5T&>Rc^7o|4LiQ=V7M8r54*#QzfCTuD#sp; zuW-JG{Ejav8at|d{L;H7tIONRu(KlZ$ih$2UjuG!r5-mF1@f?u`^u9Zm3(}VqOb=M z#J07iiquZz^p>dtn{OofdEM)ce-_1*r1%?AE(y`O^J;qz#D9+;S=@Cw2bSc*y)*d} zgWdfVcWj#18|T}ePbGZYRx*~CJKb8s`f6im{QbU>6{Y0#5W4I=x5$9=@%3g(-Qt)X zBMWXPERq}G-~F@~F8i+GJZ_gwP!?&uz4G6Yv>~}WI2skSo&s-U z)273GmH~HrR!NV5O7jjINO$9%s~lxIU3#noH>R;u=-+xUq=O&Q%?6~VTn3`J>1=6l zK*S_@{J14J@n$MphZiAr858AON|yy{r971qKzw)BhmOx*C1%WK!-^tW#2g6-RvaR~ zf0}ZSf_fAYR#22;By@Ie2|!_yjdE<2GUAVXV6R5FH*W#oO5`tDb$A3w!aw zdZ7ydZmQ|n@AYyVQE5_fV5KZuUVBKum6-M+haPEd>OMhpEPM>&C`;R(v9C>3%B=(( zcC|EMI-IC&?IkU}GlKhU-)ZZMUI3HO4 z>Xc7nOHf1jSDRB3pq)G|m6uGn2%Y#(zDN)b9OJA{8RlvCdc)V)tQ6O*Vl5ry9U5BJ*f(*I2E#7ECEwr^@?>2Kwhdk5HVd7ocVKvYmLu@gB9eQQ~j zrcSqn0`2VVevfq>IJCTs*Xr@g<~;SRiHku%I9o!{vhI#TY0~+mkY!cEwQ}BfL-*~n ze4BCLkCtYCD&cGmEQWLFKQ%q{BWXmPx=Pg^4_RDnouGs|4lo0=pKn%+k1o3vr=}Xm z^Ys*6+iiWa9CXgp1f?S!J0BV0hR3JnxBRa@2^^RWA=h?DvK}N-6L?uEB~ici3~V2J z2)@OLSs~c0NO?Jk$xF+Rzdg_Jsn08!yUO;!w)EY)*(gZk9(SVK-`epshzptMrp_Ou zfjH}vX*fa*_T3!QHIQwV-)Rw6T}5fLe|B$^~k*Z)?FeQ;QKL`jtgbD z_?~NF=rCCDQN2hd>(pJxCNqX>z`4?aE=$ zw(vzYpZnwMk!dadYCfM2m#xN(TN3=wp7NvLvX7JZOr{{}RYLQt)U97xR~@T_$5C8v zLd5n?yGfUhx&!e&?I*q}qJ5wGK5;CGwnzINi!TRGkv8ifd4V$TTxvw+xRFQax)(Vj z!{0HvbPyTfgW@Cz0cO7$FuSLPy?^v3iPmt|)`?0igt-B;VHka06Pm!E((@s(i4xB^ zqIYBRBoBPRGEgW(P57kg|L$&(A@6ql7} zH+0hkY@kL6ZXGi@S7P+>KlN#KzLv?B_F;aNP@@NBq-F2KZFvFOm*FuywLz z;%S{PmX+>SA6Q;XXFYCzpgvCGfEaYI_-bthPo${b{G#L7Do)R9efAchaKE5`duRHG z+m-ip=MrA0ieKGz6hNLwO~u_N=rfe5uX0wWc+!#Vf~1@D{S z@+tt*FX-fS0jD}$iO^M4zvZaRveJkbDwzszXa?GD!=MUEhuW1_z;`z6Fs@1h7v~jC z#5d=+?p^rw0ozqM=91KZ4g})O2FnnYq2eimxWI#R5`YeBArVkYK;+I44uB>mJ=25h z#928!Tq+RpE4wqIXb#V86;t)E$HF-CXhMqoh5SZS-m z#JTmHhx3c2jF()l$A!+0*-uJxG*x}9n*~5=g;ou^bIDanrp!c;sRUoIwG|Jl1y z?=HE;ok3NS(frWU+qxmYV^K7*cf_OY@IV?F9e&s+2hEleK3Z?)Yn`WFP;R3&y&dM( z-5+S*MUH0^#YeT~rFC}>;Q_W^gs1~}O4U2NpgimxxZ&ea%jqg#0cQBI!?Kr3AuslU zK`&Q<&{Ar7@WITtZf*DpqF-tF(yT(jWTEATWw+T{tg_EO z4n()zI%f;~5#hd4REL=B{B#7zka$+*6YX2U5!ox!Gwpq;V$|jpsD9Utz5k-RPQa|&#K$gX#SPh-UIj5W68bb!E1LTq~2+a2tNa4iINg~CcX z7)&k!at-}uKmF*Mf#=sIgmR{v#O}SeqK2Id7loi0^^~J!lo~S-xIn<>dT6zTKc#{1 zW28}@#wSg2rhFvL!=l=v1o)%=WFs=2xCoWO!-t{fLS1R^vR9@6-YqT8xOfSe*~V_Q z=aqdcS8NW+cpZvtu1gCL@xi{R8mwIvAT*(gfY(9qwp7k8-D;}OeQ)>GJMvjTzBDuZ z!*cK)SZmvUTArg0KIGy0Z-)d{=}xtEl!P&#)Ts5$1`wWiv`TgX&gU={R(v9w1A@E` zDM(RkZ|b4aZX5@(5h*QS*i=PWT2ni6sF-XyDW|m{MZkvBG0NLt6f!zZ|9ISMBxr+p z*h^y5m)E_>&SwOTk2pLxZ~JP#%J?GSlm=SyPu|uNqt%P8M!WLpro+C#S%#O6c&b$! zQ8osa1CYEYbxV5Z{9e`ME}Lb-3v!|ocs;9E**@uk(zi=27!y?>K(gFAC?GnT(^0PK z-P1B9rX6N!{U4srJ1*(%@&C5(P0d?fEl1H!)6&#jSUG69Q*(eR8kHj#P?}gS8dobv zrsl59+_-Y0qEecggUp>Ek^{PFfFlKD^gDgNkH_!tOyRuW@AE$AHJ%4_mw-GcG?bDk z7|D>_u&c!!ts!Id8^w6aDy&yznAjP*n}=TpHae0Q-v<-t1Xfe(u)z9vfJ=)^$gPa& zH`L%AqfYE(!#;kX z7sEiVwbcdM3enPGO4b*4CbcABiiq;qoI*P3jc9DoMftb!1hBJ9PER?nGlm7;k^i5_ z*WcBslhVK2LrQ0rL<6Kk$?epOrh}xFa+jQ|wa^&wl>fQMxni$Fa8VTw1*J(Ife_XwG&s_`sm~ITD#ONJKS=mi@_0c`_`kY+l_bfQ3llp{){3L^ z-IcF{#Rj%zG}kB*{gz%qH}}Pga4G3Nh;t;+a}fu;x_Iehh5Q(KS_sTSo06RjO%4dJ z1s*9Y(e9lSQ%j{+oqJ9<`)$gd5cc!oh!zl*2JcLUdU^ltVViUbWcEKsk;CJ_my|7G zDwRonC1!HVuGoJ(35|4$n6X?zw>28owr!qN=Ykn$g|Ok1=0Ot}?=|d8_!m1XS~T|y zEXxtjCDpLdxOK_%UL6m$;Fx9nB;oCpbThODmC30Qj;Srz+c!bYy+|1e#J6*@wzZ4w zEzw;*;GWnR4?g{JsSP_-HSW!G3w&EnM4;8$ufcaR=>LuOKe4YY-#-B=Y$oua(I5Zr zIU8DGSxJOVU(w{?n)yZY64N}2J4jRmJPT%Lc!9juMfwm{;12>(&&Wjj_JcUX2wdi?nJO= zrw8F=WclM9`^I6<3wD~drI*fkCqJ`+MV4%3+yD1@p87=`pXO+z3Ou{t(aNg)K&Teh z7X@|>;qv`ad-&fAC7<(l{zUEfx6}NdL$95>ki?r&+uV24QPbh{gvDLcv@kT#IX`Jq zl}a0{J{DXjv$geuI;vN-H1Yo#zAf{m0x8rEIM1$Ry~$qb<1YUU_AT-pM_pIGcs5Q| z-n|JPhP#M-kjr|RwCb7^q^4IcFYb>X_qhCp@LbqO4kO1Cj#zr_mI=nyl#g#j+6UIo zF@=?lggA3=NG7X%`e4&RpI)-J@e-JN)%xNU)ee86--~AO7mroY;$#N;fNMZQG;H;4 zPeHQapsagQ3x7A`-%D?&wtFhjz&vM3+cg5j{cH^iiRl_>SC*XlwlZLk&v|twmRAN( z!0)2MpWR0H0XZUB?`#-Nr0r^RESL>U$&1)&n|h$JG^q6a7zu`PwfA_T!yujFg@K(T zC*r=RgFf;8Zbm2QG}gsz*mt#KX9AN7gk9-iwefo7z_+_dB#vI6DjIqK9oA1Oj}_J{ z2x7nq>4TG7D;lm{I#!IP{d~O>G;1YWcx6ee zI$#NjKuW9btni)!Wwb22^;iHZYeE;tpaF|iaw`;ic7)@0W|da zrFCax-c7pi;}Dl5hOu_W)6{a?p}4dhODt%i@ccgqc2udN$s6)!Sx1E=cuoP1N;aOB zD1cppi1DEU*5+_wO|?m)O%4wO(a_y6{RXxB;m0IOUKO;**tYn?p2i9nt5GfGPUW1h zcv*V`D6^wnW7*YvcU@E!X_-fe&zMVZZJY{tmt^6FqbPtar zm0q^W`XbQ`ie~q)JZ|gj_MPJ_+B|Z$zM1k3!(`>GXx$=lotkW#t>~rm4uibLo-BU!~Z7)8+hUMGA& zy1TLkT>fPbH8|9qC4|?E1Wt&YG<39^^rLv^0*$!gyf-J6FxFXE2{j=9*#B% z@}a&%xP8K1qMa2m+RwoYKB}Y3m+nuQG;(1!<+EMvy+5jNt^BrdBXIsvTGgr-b!N zk!RJf(F1CFS)M@R->YrS2v=nVUN2iUMhh9A?vXP7eRXB@TexU@?h4mw72{j-u~zNq zd-7MK-B`U)kxAp{i@6cWQ|`5}uZB#4a$cKL71OK!=cS5wqKXC^&lF{uJ}?{}mUNBf zD6p@geHI6v{KA#2G^o7RBZt0~6~@|V&_Qu0?=L#Ii+x@rZ7#=6kT^Ek$O3B0k}T>@qdcUNv1l^*n(})4KV|_Ht5Bk_L$b|jCKJa<&*XgG z`s&&OWjt41zF81Jv+9H6+D?T($!_=RzNb2c6Op@k4KY= zCm=d3LFpzpEy$<(E^*&7&!aHMY$zY}oDKRf&tY>VTh7Q%5kOc*^#qlV(;WS>juz4y zhxSpR!@2&OEwIzZlof(_AsBB=mq56eDh{J_!!ZT7QjI!*;^qRzTdmGw4)C5E*moLY6M*Dd}B;8N;N9Es<9H`$lmjTP< z|L&q6JpvvRIWV@DLn`w~Etxm5X}IygKmFa6Ye&O(bD9v^yi69IeL+FuQHA7u9^QSk zlY8mXr1|1*kv6ZCPD%lI7oYx{r)W9JH)$_PNMZfU4OwLA+OwAgI0#KRe|(R-!NuEN z|0PwB%3jsNGhDedE+ioS?G#&R-BuE$La&p<+C47MJ7$MtZb;U&bl5W>V1p-F53y^OP?M`swpSV9x) zm|s%#_kF8QY(Gx`CXr|&pD8{!0n6nc+qjA?Y)Jq_{B@K~f|JQDZ*~&;VtoBdG$qRk zQD6-{zhz!L(=m#49FPXDaNG-szK$DOuPQUtn;S8DPq(knd~G+O96HmCKH`75$FynT~O;zt@6e(pq0E-d0-S=HRdN|c<Jg}}w$8lsy) zfZhKcTE*pjNg|@@4FscHwi5@U&jC!1zRqxn=I70t+}J0A%$ucO3~azlf89t^G*H4} zV`l@C;G(=~oeBDei$e#dQ!zQ~_q*4B#k~*|RmIE_Ppby^Tqf87>ijqP1O?s-fgc*K z!(AFeMP>mNok4$*BT_;&`pmh8tY>&p&2fdRykjV8+sTnQ>Q3c)LEn}rQh*z(1hHof@LCw zqa??S57BfGjm$3NNhjz2N7m#7`lO_1Tk&GBoH6U|`jX{v-G1wGVPhxS54dHks@^xWvUg=(01moj?AZd>y}KTJ`w8JU-f@UwJ^e0i?db_&U=wL zQ0D6@=MSmJb3+f4bVb{83X(&$bm?eDBq(RO2Cr?A8Ay%zC6y9SlK*KhxV7BVkqQ+1lw`a2CWxKsm>0a5n{JZo^ll9l*XtonICk8^%gS}wSTZNK+ zlpIkWhG3mWsVkSI6huG$C8a~B1!|RJ>-1~8hsZp9Y+3nFXwtgHW4e!p4B6PPY_n#3 zaTQ&zkIZMw8dzz5J)TQ`grinQyi{pX(2+^$#=WR^i60OmzGsF)$I3VjxAy2z2Ksp* zR-sg2^o>f?R|h7+T$t@2<$F;MZ`rA^^jxlA_N~a>w7m3eaLtTV(oD|3B&G3l2$i$t z!6}FfSiZFGaKeAVp8n@gv$M^yAVB4l?R=n)*b8o>@aZ}{u2w6G2G%9W%ZMDtmQX7m zS@WNIHew*{|s%syKUS z<7(n7IeE5iIY|ach#*L+US~k7K?uu1BA_yU(!?Y)s2q}qU%G%w*!N3nN7Rj3#|P#| zg%_MJ+Z|tbG}TFx>AoPh`{S0>%MW7GH(a8NDvV{S8vuwTdVvpHm$cT2v)9OScSbrS z(yvf|2U6=(>5BnTha0?7IGbIMys-YDJ5XNF4rbQmRkiPo3K)@`6dm}y_64Ib$Ihtf z)tSP?T{^K`qvDIaxdFF{e&elWqMV?X;bL&%mz0EnOdvOU-c5{8A_g4~B8FLLX3;|Q z!9>(f*xuxqdz=)GXBe3*1Zdl_v(WDHJj>r+PW_!Y%bmv6Jdb?$7c$WcQ6sx(L{}qk zbL8%+qwX|_u2B2Cop(bn3!OOjcb||5X?5e`BVJ-xjb$4$nI(JP^cFkUouD;0O#uhW z^(lZs6-^BdFd~_RoY;4%GjKO)5z3>a=FG610gjvTQhidr7;Sz9*uX%4wc(H1-8^tO zkMo(N_ke^a*(hf~K2+MO(RrCn$5}!HXzEiA6Uu&K(+SE2YUqq45P+8$3bK8YAxoMm zVaIX?f2^QWjfAE>-|!FME@KH9uouzq#)HG`Y8RifSz2S%mt=0yt0 zb9OAvo;ZO&{D3)JBHw?hrixxc1GE0-ZCQ0!s|AK@SHaR1p|A>8bWFh`LwV(}ZC6u$ zK+)57SV2hU#{7Lkxv4l2$v*NNKgZ~MaJ&7XV&bt@5e<;2V67N)u90sc1PTSS{dJn4 ze+BKaop~#%qY4;O3Cdsr1XyuCkGuKWE%|9(3sNV@UQhAwp)O1zJxcu|9D`)-V*(Ybx0x74Lu3{35*i+G!1^5e1UBh$c=rM0e$dXUCzU0v>Mm7NR)%})`+KGfzcT$8wf83>x&mQS$0JIF1I?BD^T6={m#c@_hI|`FFGS(I`mN) zN4)|+NF+;8<|mOd_XUl~?n&5^5(2C53kwgY2rg|M0CAWYzhc{tQ~Kt9MN{T3D~;Us zfQsT%AT|R8QukJIQQ1jq$v3Kj1IWfCJBdz0aQBo+OlLBbn^ADBxegStoQ*%WMlW11 zLv%*b{@X+-Vu-0P@whL*%1CH4atpqL5R?r}-#{?&q%+dI$$QvLAbY>|lbMt#x!<28 z;t*L)D||tAj92BEtprsf;BF+elm@KWg+X}&CwyG>2|tV9F*Lsv`D?K7z;^%5SWy^w z^JA#Z*xc~d()5Q~n;DuT*|?q*P=AW?kP4~J7?6%$urD}HYR5|2tds=N`1pq_jsEJ$ zd}J~Y|5M2)g-s)^7QfXtkZTjUvZsA$_C}b3@c%S2>#zgB2Ay{zW9fdcMZn#WXj*m} z0}|o1$AK2bKCvaZP@;MrHJZql;&5&CC`^C&c;sCOE@d-7eWim+N8qWf3UqSIX#1@z z3C*CYkjZipp*Cctl*4<#FVi0F4rX^Rc=gpR^Kw$!U3)>XP)Z}ap-u$rvIa=DfT5~+ zPrTf8F;o!hlnAhb?y z2AHDBE}K#hP30rfrgR6IX^wN!_WqLJ=&4IvBnwsJ#RLx3k)B^Dz$LfYuR?n=BoI*b z+i`2fa?eEt+IRSbNmlffku9T@`ksg`?p+~6IsnFD^K4yIW!`E|a37e`;xb=7;uEN~bC79)DMA zuZ#9Okg|>ixV-6~l{c?Z;o-*9h46u(`*Qo>Uf}vHDBbW%AcC=H zxNfVm*`?U*)z7`ybe(uvmKZKxy^tzrke43AK7VV4ehf12@^mI>Z*6jx_XyWD#LxFS z>`8lI)Q8&=g^p1xg~eFlTjH{IWR;VY({sUlWiDA)So)=ub(ONhMl&LETWypc3EJe_ zJrvEJr1>O$cv{X2fFs|C^34%6-mRad<72*IS1W~?E=pd#+t=uLw^)1j|skR@xV(Fi&8sy^&qdwRsNWU)u z?tZkzT@fYtW~9lF%U%vzJSVjnWOZLr`;}--Kj+*#0=#8KS4&XbZ-qJtqd96!?uHC7xCbzcYHRBeRx}7}CmdVTIE^a)#Eb5syw;<=yDB_{^ zYy@^%OA8+fcD8jT+wPiv?5nNr`?9z(hNRRTLkr#Uv4s6cCNr^o5-TO&vBzP^LuKFHtzYbY%M)iy=!f8(1Rm2=dIA=V1K5oXHID;o$q+Bv&W5)0F zdX+WD_d~7e+4x(xdu8&mj;guCZt8_A$DZSu}XD zukY3V)oMC6@Xe#%FcwytcalcRC{+V-z;0|x`#LqGhZS`{90TYS`dRZnKGadUd`oLe zTPLA$9wmxMM}G1IusPQ{_v{T_dg+)IKAkY@>acgcl)vwW&^l_%^1gpL+U#lcxlb2} z;a-(8q+Jt;PWh`5f9=xxD#usDvYlqJ_sR9@ZA(_Od;1Np=-HoQPLFs@b&W%BP;s>@ zuOAM|Z$t;FkE0pk{PNW;66y0olc}g9{G`{S8%u@u-nSI0RfxntraJXsYtF089gjB{ zVPV$Vl#Tm*ouQ-Rv#F!hPeXMeKY<&&`*-Isnpb&T+(QDjhH>m=^YeO}oL#(f{yFkK?Sb743FQgKcB;Au#iD4uKVMm)UMlYy!Le06Nok^XcXyKH$@`H9qGQHr+JuBkd;Bsf8 z#ST^>Oar{g0y6`q-rPHs9gbIE*E3c7LClX@X8y^&PRuNZj`=E+CtvS4B%VAX@fy_^ z|IlH8!AnxzwCc_BEot90-+iS=5?oVnG{%?#NKtq)p$bw}B z)6YLkeLI5^O@p;W)4!va7lUd$V}&y@y;Qp$ z{=fC0b#s9ELgnE`Hs6Z`6nOiy%aY~GXb_Hp8$1NXL&gsgJej@MbYCDwp!52Hx9eRvY!akr8u?B)bT(Fb<$1;w!H8Zs(FGIgC$)E zIrv+02sn@cY$U%NH>tRDt-ADLK~D)UKn;=9j>^PKOfG(j)SWJQJEFE4$1F;gCh>C$ z=9rtp@sVMtjeAT$qOsp~{xIfiROMo03ZQknNj6F+n5Eiy64_Ilnr+d)DXkf$~1qq{e_MM*h;I8C3^O-Zqq);oq!E*corJ;_t zPx;qMJalf#?d0W?o{q5&Y61ReCx732^MBe$!sIrKocHAfzw-KU^UGyBX5+0fEKF(g z>Y_2mMYqyf;=O2*);N8NzE*IPHpolRa_fC4k>0YjetUIa2Y!#OH%vSBbwVW~Tk=Y6Q9^;J zXX2OC!rYV_*G2I`?K4_-`P_5x-=;(-no=H#4(IKaJJmZ})bX7fxF0~%4H%>Vloknu9S-WtiK8N3Qg zYUd`&B$V1T{{6MqZT^HCOO79YUJuzc^5ZRj1ylG->Jgd0%iSBrKP%CAdn+9_x&Hru z&AxHK$sZZj;>i?UC5K><|GD;oa)F z15xtJ&+duEa=bCGOy~tBgZEyoJ0Wsk$xoiGSdQ1!f#o>%|1MKOe37VUEU?>p$(+k;e{Q3y zs{vw?yz==n{MVX;n;M_wO8z20c^~>74D>Il`4%wAK6uZUA%OAw1NDJrIgkI)4i+$} zr5ovZrmrbnmt|fP946b6(-f54N?=5^J7D?8jqjyyBE5(0J@aYP>1c3Y9dXThB$6+G zkMk!lpBFiZzka+{GN~`QzVPT_H8%FahauvJXithHMa-^$@eu%%eTi;;dieLArhCGSBZ;&972B3DW$VABmJq+BwoG44fINsfilKeF zE&PWDSzU8n0AD%%(f_W#E2cK2l1Gj$Tl@!18;-Np&uNmKl&>VbLHPZ44czx)595^< zBWEmMi+5jJF{O3i^4W8u4+r!=<4p+WB`AT-#+c5x@gL+n7&jU~mRD!j%l#heSTLp^ zL}n?*x)0mcwREdq`oY#03iBk=(o2$2hyi$lLtYzfDw$k@Eoml~jZ2)O12aPxPr>d0 zygRKuurlmP)oxpY?ppQpncr7OWcF%%O4N~M1Kz*#*dM}+a-tjp54Cie@dyzrp9UU% z9;S0|iN{}#z;j*$_eNjW8UZyB?OWeHxEfVy!-`tiJ{~B*^hkCJmV}oqX)}-~7D(nV zsb}cwUs7tLBj9dwYu%y}Up|9+95|p~@I&GC+;VflLf9{<=S2yH?L$8oN>L;p(e?93 zRbN=g*vbO_J-qdgjG_8h^8DC?lCwe5SInE5tDTn~u@8hVE6;>|OEfiEnwZ_*RullP zL*Ofu{lQmeT-0tUdu?_+u+6Sx%)=1kQMi7igrc$kH>WBd-6x++X>OeOm?usCS`U$p z(H4adn?sO%)U0K~ti8kX?WLT??4aOheFJ~*=;}W)|1{pQAv$6hq8l#SSzBp&`$usF z{Pf$rcbvlo=+3A-D0jV#o75~*E}7D%aaCmrP_Fjl4AzjM_W76&lBmh9{D+tD157z@<`hnNRy~iLAb0O~oxr+#f+b`Cs zAqy~f4EhD`5)O;L@_C;;nsjyLyoT+FCnq?Gt<4 z0|1vYwOn2lKH`n<%4Dc`PUM=~_!Dqa+w9G3k88=&!tw7i3VK&l%zxfaXt9`bV9%!SKw04;<8~AQ#Ewqhd%|;%S!ZOI zcCWjLv{qfhK{Xf^U5hHdI&9>S~G?QkYS7?{WfJkMhG&$4BaF_CCkr4 znuTMC*#$dzpE?ip!e-y7ck?*o2ZkD%7+d3kz#D|wwozO+ToXO=atVUMSB?6rd| z(9;=Hw9Hy8XA@-`LM8pKvbWXJFynNQ(UsuF8ItemF|X_W#{G>CotY#>bFTrAleA;X zg51>k1Mg!mNB?%V#pOX-+XYDC@}+H0_WjUGp8=VC_MkF0me{VP-~e3rVd< zt0eBk0FAJmuA8aROJNK{Zhwy|g#I$DZ$-d(T zoNH+vnvHS}LF;xFqldNbx$arG;4>TrpbWisTp9_7mh*Y}y z_`4HxsbT{J0 zjF-%Io(+;|X^4zWJZ*@U46|7Un)Dq@<4NmvM$n3ac3hvk8%9iP6>Ta)$++X&^|-X;L{#L)I6Dg%?~ zT|nk;wy&1R4n!nfocr7QXy-VaVz}dR=r)B4%{uF5A?P}4Da*BtUHCg>7y}6h$3;wh zq9QTOH;%0||Cz=b>OlEfTYGt+u)x@^Akd_Y;|NJ*<%;gg;q(%le*&Ol=4+MQ!>#-rJwMn=vtqcw8Jd{TxS7XEmURpF{yk0A2qKM+w-&^f8@{I{9{PHq*Q&|tCKd~6C9mkOg-%dQAV(|ij*jrkU$vgSefR-*YQuKf)L;ko@gFDH#_ zIe@=k7DX9gfYZL9QSD$A>wQKGb(Ula$nfZ*V2osCSQEXtGSbd-Y~%SKeZ(5nZV0rN zpmGX)fxM6#&TIEbIg_{ofc{(30@@l>Vx0Qh_fFshd%SKWroJJ%F zhlO~vRGC)-k6;E!Kq8Mwzg!+HWU$e{sT&9$u%MpVNoNK(4OgbZj%7IEC>tzHosb?A_<6Z%r9*7QO*9uc& zg7aoyZw1UhUM6QW)OcDouy%yEjoQNpT*d60{+o}`iCitMs8MF(%vp5#IqzC_k+A6A z?;PqTpA}yk2{@msl+DETG`T zGuTh1KOd*+p*w-YRYq&@r}|jXxfh>0K+^@l_xzJtcVJa#gcx+GgnN~llS67{Gdk+^ zXHnIZGp?XJKv{7`#&ZTKt1-{XEB(hwzpcHS^ya#=S*%Y}uPOmS27cFAzlO#OM3-Pe z&(a9L8AnOk3SUN#^>o8F_WYQ){>;O-p5 zf6~`{NeXCO2RMzGRlG+UhIzHWV`yF}DGBbz^!t4RmkN6d$*GFup6BtVu@muik?HU~8<>u(2-KT?J?M6fG+=eifvq5n!#;>kDr^t{Vuk795 zgZLDpw^q{S$cNTR;Ec{*ZCfPiz$1I=K&~!6r>Pm#0g|ldM-SWDZcLbU?WfL#t;4b-{8Z2B71xxy+)c_5)-nwOf67a@SzS z4=d63iaW|32ltTqJ^2fgW3<~XfGeFt5nKqZ(8^G!Y9U;i0E1m@kyKcE}t=dZ4trDw#SMX@5-G8;7|Bb*$t-o3Bet08) zYVjas9IaDXANldC9W9eWXgY zr4Ifir1PU*U8E17PD~7m{<;m>;~C^KWpkwURt9qa)2$!oZ(6CoQ2ALE{^6IDBHPrY z=*Yd{s)pRjO?#y8=N)#Kd%9~o?DUV@-cwB0RrK1UhnO!r=hVHjuA9}p5C^tqxaF8! zAf^fw>W=xOTIX13{HIx*w%px&wZ{GSq_oFdp~H8@t><4zZBDs7ttHNH(A_iGGCXpT z7&q0Dp2|$`TkqMD+&P|CbDnjYecAqoKjqJcYrHopx8A*z>>aH1OY(MZseSsDB9$CI zxGys<9#Gr=_kiKY z%S_Yx!}>Az=JO&}59rPfJsl3HkM>yM*ae)qgMnvlqc%B_R5+jRe2-^~6qiv>%bX&m zplOvQ&VMUI`_+znvQKXPcIfszk8-f<_AYOW2IR+z`Bz$WbL+W7Vmhhq9_&++18cd9 zM7edtpXk~BH)e;JGe?u}TFm?V_>b#p!k|vb4eBo`D-nbhhCMKOU5j*iApAc zi0b_R%nyxfv+;LB)dp9OncdtxC*{3Xwywv41>({cCoXvj@aTX7`hz{t)x#SPy)JCL zDQe55gEI_@o`2;;MdD*arvDa~+$L4x9fu83e*|V`Mm#TI@Aa}RJKWuTeD6&~!(UPf zO7%HCPmHt!$EtEBERK$UKIia#e}3OzC%bJ|Odh&775;#8%V_^8RlcgcwGKNSq*zr* zS3yf}zjn`L`Kg={socL&vgbaiD<#X!*xDVH+B>0I1>0Dgd$pOrO1MnJf9U(PFuQVB z+DbRQ?R8Q*uJl06mAkxZt?}-%>L`l<^_EdfTGFy%sh5wLrIVwhch|u#v-8;y4}Q?a zwC-n97QSHz*dM$@&+QEkY&I>2fKxi}-biTIMDks_jiKQoy~^${OmD{ZnrCBRn(x4F zt_Q!zA9@(3Gvk*y7h$FH2QDoy{rN^RcD(w|Gegip!3HXsjSi#UOlzK6Rs14hzunA! zf9T-Lq}^|-o3DKSVX8QbhV|?&M=o%&vhP@@3e-CJ4-9h3qVI<9i`Oyaqm85s>)xji zY}M2)HS4--`SK0Q!^>#CrYA`IWe>%VmQv+XcIus!_knE@Jss7Fnd~B)_2Q(Q6KAy4 z71J~VQxYK;b4o0Y<@`O`mbDYE^pwyRtgl!&yIUgEduMvQ0c^hD!?f1ukDo~HvGyU^ zgkyLAjr7Kxq8beDXVs}LJuNi)9_2ZGpl2&yD2{Y!acl^v@E#bJ?X!k- zIOshvaf_aTQITgxM8-kbDx(H^M~!{WYgy<`N9Mw@(+4g^o+k`P*%VCiYrXXLIbjd$ z>bqU9T-j_jQL3?ARcFD>r`s3$2UbXSE8#{Ye7UI}GT#4~G01b%kP%C?9wrdx7+eY9K*h}j@ll^zzjN4S+ zUTqVi90lk9)i>s?U~XUNpZZV$x0&p=~Aet%;v z`JA7;@zr6w{vYhi?T7fi_@byYlIhchBbTQRf4tV%=J!wIJ$giltlL;8)l-N?EW?|} zS&!^%>sy12d|&(sR+VztVb%moLNqPA>iOTALVawB%H48J+fM7|E{E+_r`D@8CHrGW z7YR1E4x}!SgR<&Vy8j6HgVw9I6mhU&+#laKb#U)!#>9ue7ToeM_pJ1DFIB4CIJxO8 zvson(e|qqX`L)mjp!heNdKpe+Dz%kNBF?oQ^6oJ+3HvYTd-4~%59VrPQTC8WqJPk3 zfqxQC{F1V6%=;+ZQ!?=B66B@zk5h}Nts03xGx={04OOn$+)n70R@)PRsXclK^S=MU z)W*b*WYO;PU)xiPk^H?^MuJ(7>o+Rjr!p0NrI{A{_g_7!Xhzx?-~ZycPA;^>y(pg| zp)uYPJ56AUqGQYT`z&DzO4!Hsi@B5R*%jw?U2|PMFGr32*9|_|M>Nm}GQ;-_nte#^ z|3}|2RnITwN$+(>wX{$6ktOWqC2tFU61sTtVhVC$dT&dd@RRhaL;Ljyk0zc){GT>~As#Mbnz)B^v3<2M&vl4S87qe5qhPgq{t0(%ay)!WqCVH3x%qm4@Pb z!foH9wk6i_MZSubW`n~J6aV*c6xX>*!Bk-?8LYuwl=Zca3Gf|-p3&LiI$VxKeqc6u z-Z)eqPNfB`Sex^}NxafKYXnGeyp}&zB_qH5ud&CczWYs~B7=Yl(Y0a$P?ICF zYBJFI`yi2F|Lhh-=4z6;&UbGNd<$~PJ=%)ji!SsZ2+`%`JUk<;1vBv3BE-%UpCeh51#Iva{f*E~07NbNE^k}=jfD`DGB=wQ6|SRl z(VJm9j-(ahY7tIaoh8u~vR>4oVc{VSvX{44MCYCU2j^`ie*s=wUT`wgqY|EPQr^iGS7~gVQg4LRmdBGL*N4O0{ zu-@Z&90;jRdt~eQNY_J|2h7}73Z6$1)$SP;RpLoxk!Gla7<>X7fTG`SPCo1`jXpB zh6+A1q~U0$_G4ArH$5L;j|UrcZ}dloww=1$El3!-jaRy=m=+YZC>gsHpF5eSNy5{M zWOmkOP#Hz1?eItLpc`Z&H)>w1$#mf#g;ZXyuSv=Ml+*|m^|>*X5HwhE%A5H`hFwo; zxI$2`{j^(J9O|lmaNIth`Dt~ zalZ1`Z%M4y#*sCIkG`YkwXBTO$J5LiMqj zm^H^kg1CWckFS-+cYVL*&6GLi4hU&vV3r4@7hz{Ax7~zmH*qG3tZ%H+Vl=33m*v>k za8NDeX+oX;$4SZBX2pL5D?p{eW?n0}H^uQSOw*aFqDo;HxyfMe4Ni<2$e0?P%x)dn zE+m6vDBf7YI%v5ff6WV_QSWU~Ik8juZ^-~7W2b6>k!^4X`+V$DqZ>=Iw)JU}IpT2Y z#WfR9y7cqab)P9GPL{4bFH6v?`Vy&)8X4{FD5xVVfo05>5X^^%*`; zzB0n1H`sVFgt{~ELhwx?*@y>iLyLfBgag7Ryob^dt}8H73Bgczib_G}u^C}c?f_X8 z+yh_CL*m{BaJCFmITJfTj>sun4Yef$B#?ySn)vyJ4lv`QIHmK>J!0syN~|FCLTUv$3|DD@eLe}(p++#Ax+gxTdy84N9KTYk z84cL-vn7VPAT9MdKT0Om$hx|J@nU;kO)2giaVJKOAi_vlUw>k0YFTfny5FYP5bC=o>T zccX!L769MG3>fxJ#mJ~@1bhG)*Fzzd3rFf0_zXt zyoyE*Q(*TlWHjl@nFEjchlyBUh?=@wWK_^^W%)in)`7AbpoSzCc^OLZUaluK5z@*$ z;rd9lRO*3Rn(exkfYZ6=zLEvtMbC2ud(Uat%7~}N*>_#eBQZfe-zz?WMrE@N1Egn- zG7^E4(NSr%l5*F0tBOg=2(@|G&*{Cp*B7@+;ZUR>>*i}Rt$0w9RC$qD&>=3z+5)5W zWKnWlSEIELwHUmGJlDS9^&KlZ$h42#29r~e*mbL*BSFecAf&m{6@~`M1(nF_{0FCS zX$HSyyZ~ltZKN_g4X9LIE=~Z^&AuLHq4)^ncm*OPyGY&H^(Ki3M_SfY81YTJlqIW* z(6SE%Qh-bO5lg`=Q9ro~Amq@J0oB0QlVvewF{N)=-Vc1>b|+z*w*Es(nuwF^ts8Rw zEK*=anWKJ^wy&H`3u}{{8aNf+Gf`5L=0o#%RWG;>?rtHz#Z`mVZ|0yU`f^JR z$dEJWkxuUgm0u;i58tR64oo)y!u-HonI9OJNN?TcVdwVbEo{L4%d0UJmkAGmk*AGf z(aovdw|=kiZhN7_7o~d0=rt zNwW^4vc~l7|F{m8D5%pq`w%1hAbBNF)as{6fOa?W^3wb5(7c z8{usU`R+llBo^WWglLAW6M~$>Z@)xNK?Led!_4UY^L(+Fe((D1JiY(N0^908?b*E~ zUfUUS_In=Rq2{pE5!FJ?Gk5H;q?HN4Lgr=wsBBhHh}Rt_lZP_nBTyX(>=`e*RUP$WZbOS=*eCi zo5s7Vh*!taqo4&Zw&3pyZDr)WVBW$z!tRA%%OcwLawhI+%p4n4f#@*fSf|(p&&H@r zojyYMCzp@mHdNk!ekXEhI(SK)Imx^+h0e>J3EtlcA8Xt%d%dNU9gTpHFgq{H-Sbbg zj4m^KADqLC+(|eT-Mm__8kys^p}ws$wW0f6EMQKgE_+X@v3FiT`754N@P~eF$L6J~ zn*E9iB!@rPAU)ZSPVnUy&aOH+lDD_|?SG7u_$i-a&bhl{t|umJI`3avnc7;p-y%={ zxO>s2DX{EVVbx^M&AxNQ#TYI>&d(b&Psi$1!?K;u4Oc!Be~6!gEBL9tJfro{-0PV% z3zl0F{S1rcH6U5Uj7=-*YGis#E~fZ3aB;6N#Z3_%hV`>%;kO zM(h=&r?TL3#??DPmSP637k{67b>SV)lE^wKPYZe2RU`H(+)vuUyb#%DdLiL#y;lg5 zl2;gs-pN=EV5-tz&L50sV+-ik&w`yz>%Wuv6#9}wLo#Pj*SN|cGbtphDN2A9z7be3 z4-v7e&z=d>T1eDVnqz#S>ODT&%FUzu=tX=`e`GGKX(^f`pzl^Ru`HavQxB^U*w+y4 zlryd&)$CmKT|55}J&AMJXG3$&wdCAy=wXk3S@Cx7{(TR*toGkQnWYUoAX>%3fuWHA zi{y_J(ziBz!O{PAh4;Bpw;Z{93H4~lCYNdOyPo+VAk6!fo22HokQKYOoiBr{vkY{F zgR|r%*-wuz*xPvY>`Koah0@Pr-YTkx!Ecl7sl>1CGDeK(>|<&@y8)E(uhKy4BCIQo zfJb0Bf{MqcEqrUG&b3I%JnMNeV3w<}W(0wwj^gpB7DrYWw3w}jT3HIhw4FL?M@eZ> zd&{{*jfA#x`5BF?M|y(GJzaHe!lS{rb-(jQ$0uh_DvJKtv&&6PHfq}XS<)w`J(8TJ zj$y=1wCX}K!v`1q|spQU|56sqoR_HUm z=uWcp?HYvGfO~(;t~69jzL`tU64B-s{6rhkzAMc8 zI|j9KBB;T?x0+fE%8>mCdL^y@bc%aWHHE)2`S^1#m7e78Z>L952NA7;k!OOR+H(e> z$K9(LZ#O?p^@>Rxl0S}&=pxlC$2`$;^w%k!iS`2o*K^K!QCx9Ebup&mTYS+7EHgmF$*+Xsr- z9d$mPcx6EQh87L=g`4v9V`_4RH-%H0m5G3{C9bzP6%^y4NuQsC&&gdw;W{71f_vUZ*4~*j&-8QL5Yk9)*ex%kH z!*(3?I!?sAv_EwE+%F~B2Kc7-WrDF>j*IGn$dqoTl|E0NUB#Vp|IDOh`gSEYKhbxY z7QZ&U=G}IsVy8<>gi$cJPM1n-gcmG7b(r?3y_N%4&h$}J`}MsMvnf4a)yCr=*S#c<9_yUZANWpqQkNKVQ5iYb5$;hRS^kLJ&KblC`CoAKSK#@;+Q_tJv{!p9-n0hRQ7P=pGZftB5 zZ>lkeXZKFsDdJP(@U2 zuTs4T&rh?>cYclrUtK{RO}=Q+v5qaKILbTOO;_)YsX}83*PF!^1_%=xAlJ?k$ zd4}h@NauPO)ET~0)VDWWf@+ps5}ZEnP~DU$Qut1!AmvhDkc6+f*}*GIS!^J1jDiM3 zIs86{=t|Qf>2qTw)0ShiwAxyelhSyc0P7sJX%6qGtDPxE8|Ljj?!dp9Jj~igP5IDe z{#xK!Qq&*i?NxPGBfj0)B-lLblG)0d{Q>JQyC$*%LF)hq$$(S#V@j5hv|ggsn{@V zdKxGFk!qgaJ{cE3$E1?sZ?T>T(#?#%E$PQ^IRn5P&^$aGUm2oFK~oPx@U=TO8{^Mi z?>qVMd-!)g`B~s)`{oTiXQ`$yId%AXh!7RW60_Lgn3~MyC$;de@ce@1@sAutl@R)F zcU9d9$G-lyDwU-!r?b|$PWZc#(HnFTYY!4m=^OLs37o@7kg>4$&+g~7YEYhe7KH?M zoqa`Ej(2{Cm3(g~w96bXLmygZ^>}_RZl>1m6{$Xmb>i*J`09MYR7iTDKxYv0 z^*OB=lN@8EZO&hfOPN-?4iahGhAiRF9y)yB{aQ&+^C>jA_z6=x>?LhaHcLT_cQ6Of$k2oFt_8t&KzJ#?7q(yu__sje$cxL8Y(|9PU&{dB+;;wq$8ID_dH*#oV^MTaYINLym)t<=sR zwtOCbmG-V=(?hS^1a)FAXX#q)Bge)sxj$^T{RpnWfjX?XGUsr_%mt+Neth&;*|qsS zQLduV?asO!2fw6`LOb%a);Fe*Ea(r5xb{*rE9V0}U+Txlm{XVjI(#nI(q6~?4u=9c zZa7%x*)UwSM$#co|*f8;jx-h{vL#)%Vz9ux6Hfu385|yIg}&Q=RBAK z;P}^-SrEy$V)HxMK67s7Xx(VVKlh!zKVMXAtS1q?Ny<9jo$4K&;h!yv|8c#1uPZsZ z!b`sYC&eSG%ed#0iDqLwA2ax|VIyjcQe^MWIc?qJ$!B(i-?ZDY9)-K@GB+$ZrZmi z5(@>M)x}=Au3Ib!v1rOV$SrUk>jXD0(UhqSG$h)D#!Y%y2f^W_o)23gslFpZ7yDJ1 zAfEY$g|}EF2+_%ei8b0{Wo>x+CJC5DnDGgW*wZ@~K`jCa%?Ko0Y=r~H&FkGn!Hb?R zw>~jR%KceMeY`-@m9ee}!qz}SQ3x=86c;k=ndJmrOz9)cqBH9@2u{jUXZV9Q&Rn6> z6B{PssTq9QKMBjS+9TO3yN(5(pS$+%4-vpea+jMZ05av;E`#>pJZW z$OX!Xg(Bz=NqrstkQ(^Ur=8o>C3}A|(uIi*od0PwkS(t;L*p(O)fV{=R5ETnUp7+lMfKng~aGnq{o}rEw8nXD1eEBegHS| zdxalMUEfC*6DbDMMl_=V(YQ0sC8GZ}O?@H4NG7>prltnS;bA|%6N)gIr*qh=3K7et zLs$M_fMlzD%ODBevJ9>Sk4E6d&S#j@5sLui-BreuZ2>w&$Hqzv;)N{5*tw$$YNm~j zz&KF0beZbdaPK23$qXO    -*AVer)j~r;Zz}E};W)K!iiT5RIa|p^}$O zHpDx!J?D8P=BygfQL19y${!q`(lR^{Ks}6SLqyT57aZGcRNr*+uYI1{o z+r~lMDe$5lm|SXyQg8pqMY!78$q}g^m2B0_;P2gE9bP6{O9{J4>EsH>Htj~~2mDGx zJLH;$IH}_Fb|O0@HOV$pX^*N0!5#CHtm*7PO7Fa*YZnD$t~W6C6U)47C_ZT;^Y7ZK zxqYS4LH7)hokW5|y{Ca!<>*+u%FPzB4(Kn- zeXvahO)Xw^!%S&OR$$tD%rrF9okyrqQsJ(aH?MLxCUDfwbN&-?b0li=rHggkV9x{7 zy;3gtK0|7pD@iTRu@g6K_jb_<@dk(gSelR=#v&<7K-t^oKAHEu=RWjq`2(MvK{+Gm zz`y<+%WyMoE=3k!33=m@kOtj>C9Cqc*v$Xq9LS+q2RtYol=rfy0(jhQ$}V_*?9U?= zNp*klIDJQ~fx<|O^r7=A4U&|p7+Tpc&IVu+(aOYh0Q~|8`Py@% zqil_Y?h88A_@FBC2`rARG8|xD$10%%jai(_RJkFQ zy}aLAWz8EB8)qhBzX&Jo^4{(xhXW`qpr!ek1K=gkV}n+XXpE=IV!C9T%^V|?HCbF2 z@voQ2IUyvTnSbm72pA(1?`;k#-hRh`eG4b4AC>rX0;KY9g^vj6*L8x&!hm1}ay)je z^PBtldMzjyaiA6C`r^;X8{e-++84s-909m#d+}?%{gt!FY-Z(6WcE5zLtvECJ{Tnw7iA zS@MN(Mc)re{1gdY!%X+f5-TSd_C*k~sxQd9ES=nt7Tm1*$gM#Fugjpd!OGsB{SzD- zby(-SFE0-%OwmsC=+DI`J{g?dPla1YfF%?7!ERzCsfu;vfy{w^Fe)458ae=eOub8D zuK|qP!j#5Y245Yx`V&S5SnT@>U7vIUjd*8SjjKA)@Wt7(i#Xc?y!9+yB8fKUz9;)Z z8hAtHXBFNFf$0HheCfPP>Ps3RBlLg(C>RFB6o4cmYwe5#l4fW^hF3yTrcLq_Jc-D_ z+|zZ1lcKq#wcsS;?I#~L$0g-*pq2_z8YG*Vsyd$Dyd z*tHu9az~$7_A~$}mCtv81i*6k;?$KQAhGnok+6D08ZZ$D&SLVj>F#^%$^Wdi0>fu5 zEC1tK8>SPslsw`KfC>{vG(e8rpCihefJ`Sm0*ftBvkd9%YXgpmz%*N0LOMr$Q~-0+ z#ruU!wtpus__s)UdTiJy!&RBmC%HMt=MfT4LaM9`RuRrs|(o5%SBbE&r_GujD z^}7{~^=k|e5Aemh)%ugeNd_W1JPc#d1Lx>@y+T-v}`cLjdVr?`CP7EBDZ-HOQpd*;VoDNA$2}`ioW+RlPNq3tid|+Aa{0ULtK@~a3^m@5&W?dS8 z-NTo+l$@IUPQ|HzUNQ)A8**%owYLFULY83eX5$D8{9nt~bB-^)wYf1v7an z`^S0Z?8V5Pu!lQ;QJ>!zfTx@wam!<5!Nwds4bQ_VLgY`gl7b-`w0ziBc8~7~6Ee?^ zoX)syx!#VWz@lk|ld<26#kxIt(kopvY=ungPJ$Y;IQkJ}_*cq@C1I@B~3}5G*#(&1#j?G2VdKn+t{Cu+|krtC)Ct zUN%(BpXs=^H)s40?FZlMtLEQGhi`lgj>L>XJ^*Sb*nE1#|X! zsBPIKn?&V7BuWbX#YJ(Bn;&xztbf;kT8apty;}jxnSb$3cXZPU{RE#jY@%Y>XX1N> zj1>>=uOONF1xWY%Neiq^UNojvdRAQA8^}qUvu!spqZGK$F5A1&5Z|1 z^6nGF?$6q1EoLR;NZ*LARVy1T)vgr-@KRKs7~NvxW=Dq_>BpYkF0<3n$!O-kZ5bT?oe^y*$$O5VO-|_`M~?h$Ex5A`ugv&UPJlVauct-HwWJXbQOfcCp5m z&*xYA-R;~<2WW=3;qNRBtSGx<=%NN0I0$AqGA$Sj^g=JVt1Fhk)jLORsqmW(8%=(Y zW?geCa0m4%QiRS3*LOY1u`7>HT0cUyaIH1OV2WpL>J$SJyu_#))y~d7vA@VqmMRE# z)z@e!1k2f@Nuhza(#|gkOpE~8&KVIVM`o8q(w+fxyEZK^xbWdOLLCB2dyU3pZB5ig*aR0I3?j3U7 zPE{xf2$PkY7+vMekLz5cPLJDBZ-I>cDN{e0DC2dd#Vwh)C0);VK})I6U7e46W&9wS z6!7-Iv159lH!l@1+h=k@e)%;pe>?Wm$ z6a0t0%&r2@vrTgr4H)+D=vpRip;u>@Vmt_jX^N5icPlI`{1X9hid*h@208|cwq+Fi1IHkJO? zhpcE(p0*86L!3mpL#IC|_w5WHtVk*>U@0uV3tWq+_!>(~h_Ghr9c-aL`T_@0wbH(a zLBK{>=n;m?BM;33jBIwLZNGCR9+PjM*8&we-}1QGtEU2t<3dx6&C>~>!lFfP-*=Rl zbCmL&l~^$eaek5S%Xs3uS|A?6k2~|wdCK+Rz(Jfg>VjYKk=g6=taGuaNApOuVaZSu>^wXPX*szi$ z*w>L|EUW6uUNQHA*T=fAoZgl!f}#=Mj1Vx%$<7W0-@1&w^@dG`V&T22sroJcCXqvH z0{RA>5onU34{yA}3BOL!AA?fS7W5;jYvrjl++_KW$GNv#hUCZ48J_$GQPH}FD1>(Y zTU=EM>jbo&L^YHh*X3dPQYGV#rFkF}*Rs{442G}U?`fAZFj~R{ij9uli0Y?d9!2KR zc|qGMY@>uS&$Of)w&A!rA}cl!K6t<$%{U#s%I}pM_-L;V4V4&S9cNnNYOwVw8TNK1 z9br07(d{h-lg>-tQ)jW!E_Wk*zs04R4N?A@od1Z95wpMFA#nb#)L9)W_ujgS_#zGR zALhV-39UL!=b90-JXBdRa%)SOb2OECfpwi)(uv#48OlHUw-OY00&;tDM%kjl3mX=!Lmid6>|r z{@&WJE&3*W>YDQYXxh*cI7q9uu1dHiox+4T(y?>nvCh;;B+^q;@HZYh*~benT7BDf ztTJd#k(|@O)5gtpTwz+v4DpgVl5unq1yQX<1g#B^#;i9H?g1F3dcWmuOaI%`hPNIM z)dq?ETvVWCefR)20P;vo9+n!J_n;nJsg?s96wb4!O%( z_<5_^xMvoz=W=oFLhd04$&U$vpy2Pxs-Yz9@h4zFns`^|Q?NPT-k;Fmqoi>za_7qD z7_tU0EiEW~y6!Ib*M0hBwBrhU4V{<0RyaY@AT>36m#BBYcz?B)pQVJg zYc6}>_3Zj&%$*8AqyRZVw`7vY(DYi))E(_qPq?JUSTSLx-+NO2pOe|a=~a)S!e`db z_2NYr7vf(93%C`-V9_qgVuQDNW4^}$qX_sRvm^bL*{Nh3j_}`4*xzm<8fc}uXxkWI ztpjyC%8E14nAvvki}Gwkbmqxk#GE4tuXZ#pa23-mE2@vLNN>46Y3of|M+hlIGFoWF zQsmT~M#ARSCR+A)y2b^t0k~&z;g)b8QNvei`VVefe>*!cSk8mxk6&?b_)VL-%AjAdzc4cJi> z4#N7;A3!hU`9CIbAxOw1x|9|sXOkU~|KeMOsr56?V7I+5t1rb>AcFLjR)!HYdNi@V zi9S9Rk!KEsA=9Pn%KQ5_!z+MW_oLRAuF>YNK%K)rm{x3z;mR{-LT2yWhgQgfZhB~5 z#pWiq{PUfn$DSrd(czgH{+dMXNQza%=D2Ud1CPF`89-%F=SdNEmFDcTQ;q39OB~J0 zSig5~9OU>G#Wsq@L01P(%w*d+Ah5& zmjkVtl3PEUswFOSG&zUAK|*0D#AY54Gm<+)U>lg83FL(zKZyJ11DrR5IEM$A_A3ag zIVs5&dZ^{B9nqu735_^yvs~j!GSAF^cwY5JqL;ElN60!9X&N9=;C7mdStIKQxNy$2 zsWU*0asUXJqCy;4c2w=)rM4A;6({lMwer=5St{vb*H0;8$EoY~`BXy)p^YPYbhbQL zupOgXlGrSpVn3zWPAF_j)Y4d3NV%OTl6Wxa*yOb|E0`f(@uxe6yJw(5tjFD#Sx;G^ zm8agqX^6Byu{OBHd|Gk~ZL9Rb?U;cL+smdc!UhjsUSJZ+ew7M=}nOm>HO)iVHaj0LX3mMi)W&$f| ztrcn{!#k=?2HvIw;vdKG$To0cKy%;F1*rL`@{d4H(Q6qCtXL$>w8%PXBLZ(a^*Axo zRT2p0xUl{pGuPnWpz?oQUo!I5{(daJJFtABx(rdNJCTxWx~2jH7R4j@BInAZ-hcAV1LM3@l9+imM^V_)LSHC}@Z!#QJi5qi6X6<}_HX;npPp7yT<*E%O72>!J)emqu<$DHty1 zA!0r+`7kdVwLW;di57e5_m7?1XnS&99s?ZCL+NHhPeEiC4`LOmW!>B%85Tq=BOj2F zH#qs8(c*~B9;=x5lwD+iE?k*VX7(d+$+Kle@38R|F}a5(2{?dfB8FD zFa|=W5laj{Lp}^vuQ8H9s}Ghf3&`=J2hsOkcn)eraiVcr#IVTgk#d*{H>7eGa+< zMERI}8Vq`|s}k^O;YV5aAfR~ev-IunM&E$IXT>%e{{`Jq0#w292I0R(jA@}E*GNHk`<9F#65h&wxGfmX( zI*jn=qm5@04g8-oUL3lpYmsQ6wOvW#iR{)D8Pm}!o;Hn`L#Zy~wQ>wAP3wg3nyH39 zb(Etx1aW@mDO2jf9{sn8V^G_FTp8c&6e8y8kB66V8j&~So{q4UkG5wP?~5*tFz3Hw z_toe(o)&VUXF6vnb=zx;M0bWBnaQW{3Hyz6x9cE&L}Oy-nuht|Ak@h_=SNt-v9H@Q!uNZvkzvT!A*YTH}6MuJ-)}HvzBuQ zRxiv9%YQ(zoRTSb^_H=TzM7|3PYb4SKfK=EVP4yT4dNmM4%Z0z+ho)_CV0>j+W&HR z0>Dmh<{4>n%U}p>H14md8zfE&3n@#f9WU4?=OdSho&*Tb*k%9(6I;pXEg_1}vlpDa;|`T@@0I{jjv9=iIL zUjft{T97zNs%id#-*(=#ZoA3p=;iookI$P^vZ*LjDqjaq;CHB1 zhFuyt|LnI03$oc%Y6{nH73eSS9}6DOP`r$X^2HTLHG7le`FB$k7)xw4M>+&jhj{xr zMJz(&Nn_Tu$6WjqRp8>?8fPg?at6LPRS^G7Yv|R5Q>Y_&Aa%E+)y7Lli;>@v%7X!NJHyeWbv9=o!eC7HV zZhWqUns88jfbJCe>oLOYmbgHNr}(2MOAYyrF#xSO`zXiw`+=hW}>F&{NeuLQ+d&?;%fMo1yDvn5v}s;I1j!f9+9dWxj&1F z-S6c2T@bA>AK0V$GWn+(#gHW^%{iQeiX7@K1mh5XflbLH9$R9il}gBZLtpDIN#!zW z9p4*5yQv$7a}r5Zwbn7b(i>0Def9=t(e-ck9)0%v827%Mjr%sOvu7$lORnsIG1CnJ zX7UU|81W=27I*k>TJ`X@vVdv$rLvRwGwqJP_WTkdI<|2RoSr<%blYT9Kx}eS->o;} z9JXyGtO?zLEjJAaxSTq5yB&)a*4iC4=6WYi2)?pln{n}g@cI+W`MzD!Iyk~Y2BZcT zJ14opsN}0mMpy}DhcE#Y;{0U#%6)hNWaaD<81JB*nv>#{R8|$FD1rMJW9pZzgwroO zgyj?1b5MVs&*qb;8!9nOgR&TrHXR2ri3ek?tH1qj1`=T}|Hyzs#|358oLm)BdCktW zs+v)|UD;A#^2syl>H6-WjHx80COTh1=YL$vcKP!c5iC=;0V>4sD8Q21y;gj8I9=x% zWOWRrU~(@0*5zr^*e$Lux$h9-Qt#j(<26lpDEW%KLI-Q# zM%eYLjf0I({g57>;v;jxlV8SZZyS?DKy_goGCS}lO9B_RVkNXezMRe??x)~+5}lOGG7gN(195<`Y;Y4xSNBW#@R33`DorlxkIK1scu zfRHI0xHX{;X@;ZfiEO0)ikZ@Wh(YZ<%qo5*zgXpV)F&H(PW z6j*O~z6rwj)}RO+l%*sEhHL67>^PRP4r2581~+Fv2xsZ=94fMLj%GF@k7{vU*F56a zOC6_!VZ758>3<7OW*7$+CC{Irx7fQI!lPQeJFjaXo4lc@DBNSjUV5=m2Xf9OKY@gc zB}>xCmBj0{vR5|@V_7#KG3#kGjZrP`YYNsGvjwONe2L({Je)C=XtI+EUK9{Iq;p!Z z0sAXJ(O)q{Dk#oaHkSPGN*8|=LITb3+~C^@9pMPj**cIi`x@fm@Ha{_-wn@ew?yOz zKNF8opkZe_+s}s^dRJ%aK5ldw;B_)&21K@AHKdr&ihOxSpQ+jqd^EOv<#~#MLvs2l zEihr(yriI?KAVNR09hf2*SDLj8O{vEe{QCFBjxZYWO%QE!a_7cRlk!b%w{}_l|IFK&(FnKD>TIWAL>%wR&0lGXS zFl=l5^j}na`Uc-?9nJZYhUO;h@S1Y{0QdWso-^|@r=Rm(Q`p@LuCrP2cje=p0UY1h zpG=>^!E-rl&RcwSHOYVHYRl3eofyXsB38(eqb=3S4FwyToWqkdsQq;RrMqwMZdlJ& zXSzM{e0`$oroG6fnOeNt!RDT&+0K_w>N6h=vn)2hpSX=Qf2h4!qx&^kHLFLHs|iCpg}WeU$0*M|8Ku?VLuJ z`7!xw;y6WZzo}WyEJt+y{k&t7tgxw+Hwl?E}GmzcorY`v(+!CLwLN zDE8}u8h!&ib?7tf6desc@0N|L6v@BB@5f6GK4n8z!Hm>HQl&x?cxe($ii8Fsb7%bI z*at_zpJy&2ndj&}u>ZJ9f^#E&A{8%lx;bJ;CV(}<1p?0Lt6{p04|eOGZ0yqo45#;I zkpyT)^Y42D`M<}%^zZm#R%~qha|Z&fN0JGCdgC>e%43&Gc9|R z1=&!~AfxWNGW=-Pk?{Vz8kF+ykPP78z2?5-x2itJEdXWj{JWAGlHk3_1up)&pdSl@ zA0jtG5)rlOv9rprcF9GaAt+;YWOed>JixD+8CvUz(p(UA-o#DS#|=JsIAX4Yo)6g~ z`!V9)3@0fJ(&)B{4N+f0UKZJkSaeu>6zAk-J&p4u$Aq7vLyCf>z7Jc~HjEZFHVqGH z+GlsBpE)I+TOQ0UuR=+7dV!9IbuL2xJjmmQYPL2(m^ODguhHd%0stCV9!oY>ObSm({tU0vkW$L z6;82nhEkZEZn6(>p+~NrFJ|X^$}fR?e-gxK3tfG&y^s>#LkI+TGgp&!bO4;t0?j7> zS+`o~3)cjwP#SgU7NLr78n)Hw^~}UFLVQus)YD48K7W>Yy9Q23n)|#f z)I0S6M`Yl>n(*|M_w+Uf=GJ9r1Px%}YCktgz)cx*_ ztZ`OslI7Cd^I_@Z(ePgLID;%5_A*NBaWu0J5tog-KA2g^sHI`P;C36i7X* z&&jk|jI^_{1p8h408Q`bs|F`w?DY&FrMib(Tl>^vSvTg4RRq$QvEIjaUOp<_xpn2j z8dJTE_MF|~T5oTUAkAL(=tqHS#cgykx?t)))E+sSFr=zuiJIn7fyM#B?p;YBYXiTU z;_%sq^iMM;VHG|+M5p!txD2xl633q_l_6Lpmupm>R$H(VDG9 z=hj`kckRgMi(eW@JOydVCJK*U{PuG^6zm&wPII^e?dNTn>f^%}N3Io%uzdoidJb^8FK^* z+XI>Oo0I4Nf%;M!Ez9E|X~-47s2#hRd#cw{)lbqP3B6TYQ0f&MG{i&zWzQ{fAum#`mL zbrnf~>v5}}`2#x3MBj>cV+2x|y+DKMqff-r%icCV0HGJ4Lr823QdrlIn$LV-e_{$~ zgz|v`ZDd_-oLsPE5T6!wTs=otNpK0$Z)YaBCd1)Sm2L+FV!s|#)lMs0{7o_*% zQ_P~BO>D3EoMSI(ZMYzo49(17qGf*ND}pyR4Mf(>`!Jz_Z%(KpLdt%9cTPG0)JLEv z$SYws+Qq=VB{PCQ9vZvW|AJhSl3idW2$hPaoWGA_7M?0#x)+B{ZO(RmU!X%>sdzn3vxYQ0zTFlPcez zkEN_z)I`q!x9{!#M&C%bzTETx=jC<&+CWJ)WyV|{sW~ZsZRDQ!mfFpptH5u)2QY^~ z1%-?GOu)Do60tEp?}sXmk=m~F_q9Bklq3Rd*c0vWpJM(ao0|Qsi`66cH@mUk#8HdO zW_*Hc;cHlVuSJl}hNg%&;!GVl7xs3=?TIo^V31ar5osag@`odIQ zyLXj6eZrZtni`1cB;v>YKSw$18>;1Ng)XWZAU8jhRgROdLCe55t6YfJ`D>z?Bn`ZI zS`b1=r=!I?aua>NCr4w9aGk%x+ZHSntXcGRBH%dC%7P81B4O4xPh6ROBYVV@*J~ne zVE1>{9)q+~kBu4>r0wTeu~c+2_#~|Z&EIF@);j{|f?C6wQEMg22CE|-j>t~Xe+_(o zlKvjS2N>$VA;gj{lKec_@)k>G+Oo5_^t)W{flCoySWEwGm)0}EUfF!G-=$Yr*mJOf;?X`O*}1;l*ao+U|i2`d}(_GHPfpe9EL zJs!L-f4_S^(f-g?#JKtw^PMkO*f}gGH9$j^Los_D-P+c|4}X41i)`hC?DWHQNnOk% zq|MvE{^P2O!|i&%LDi{MG3>#d=jI~}A^-sfR29rmTj4#Vg?pGovojIva}~Neu>Qr) zpF}K19ux&jpiEA$VA&($aIm{w$RcqRXKe964e`a8b+fjZCgRg88bdOKZ&{%-i-I|ny33I~o4gT4ECN?%II$qeDy-mQA+ z9LjE<=ZZ32j&C)!BytoX4*%4n(6YXpndNk6G zb%_2%w-wgn*klOz5r{vpZFplij-mHp%$sFcW*QP9Z5*H=@B{1bxtxSgzYO6K`QXhz z#dF&E3#jdthg$U1(mKW%exxmwY+b(g<%>qs*7q73EIpLGF?`=kO)rQmhy*DLOx^L@ z%u~2ZUAygzeY|>jeW;u`GLz*}N0?eOzh3Z}PI?rurL; zDHiznMAiO*;z<&9A1JIp>oUVJ3rTVbeNSI(t8X?t@ixD1V#jURllNV!S&ETJqhUG} zkMJEwwBB0%)C^TY%u2c?Nf+$(a}3AvE`*^8-Uk}IxWAoF9oS-f4s^QtwxSOQ7#790 zHkF$X(j_}3M4B3?oTzGhN26ba6VHq$k~cfYPwk*g*iky-<$oY`=`Tank=xA|v}{6- zmp%;g8<>Tf(!*v4c8Y6DI~Sq`ap{HizM9UA^Q?-ZVU{Ey2XuTb_$f`+UamA))8miw;kkF&HnZ8}!)Q%{*m@RfDU#%X3 zSKrl~%a7d+-|_2r$98oic8tDg418PBjPpL5c+TYwPu!_}T^)QJ9a3)i2tDg%t~Ro8 z;MWzX@_XM8qtmIZU(}>l1UJk!pT900Q}s2e7yBlYmCnW6nsnvV0staM>WIlcOww++ zF|t&Jdi{|8bm!;;87uwo3lE)7p=z7=`Mo_AGSCe*Nh4QvKqvn~ARUjcMb&B(WP6aF zcq1#Wkz&}2j+OKB$ z-0?=&+~=qne)R%z1P8n}jafFu| z{yJcMN+1N z8~;|ZE`QRzv&!+JN?X9}N{)khRC0~+VM1b~bn!I>s%C5F-4X9O41U@v|E%BQm+#AA z6y2673oYIML)N#)Gu_62>wJ)OphB!WN)bY+lvQr0gd9eWtA?C5Q4GyiMCH&zb6O=i zpA$0-tArSlGcyaBl8q7D+Ts3P{hrtJ$MbsrY%g2e_j`S>>+^Yk-Ur0Bh08Vbsirqk zs^-`71s5+YBy62Q7gbk*!i}#MHyuEg7VSNi&VuT<%Fg;&e3qGsIlT}9e>7sEU0>IX z)YjU*FLl~ZZ`X`AH-$d^wC70CXYkvDD3B(jp;6_gwm|lbyU(E)^)Mhr7o4BQ0VrC~QNPLj^FIS}0DKurL6Ei;=j&?8zNpZ!g?TkQr3(cM!n8~m1d+EJmdyoJ7g=s0z& z|8}qlzXVF=vb4e^Q3SLb=mG7_*PWQxUqeW?1Fa^+CWa-r7=tWj{Oz zpp|{KEchfMShW2`_&H1~Xk+;Wg11Dd;r>8<*$iNT)sLJgS{wjgJ7i#fB^uhtroZhG z&)+&Q<}~|w95%9OZ)&N4UDh<>VFQkBSdd|A08GxORAIYdOqy(P10DYXPUKYRO*uoT z4Q@?i%Dd+O?K+z-B<)+wF3`p6B-0~{GguNW=3k9Ue&0*)y-3MEI7pS;H6bS;^6LgL z?|OJ>WQlwN+mRAgA?4zukp)Bt)k5aIU@k064mpea26I78=7g1Am1dz(pdvOh6gg;= z$u?gu?ivFe{HlTg#uHM9PS0=#Z9;E<7$i)WJe%*MH30a`OarZnvTNqh1$H6I*Q08( zL}}Iw8xW+MrS?$-SW?ZGTohe2$44o)-95{=9|kuv0#8E1U+Qa75S&5ePfGaWR8g0S zy|aO@prqoEml4v<)+m}?Vc!IzBuEZcN7-*u&1pI`FzL&EL<9aeHzNL;-h3dhr(**= zKQzkph)yL?(WjD0Xox84zG@naE;=;~aw#h8e0NM>28VB!k%Pgz@mDuEm{wb32E`xp zrZZzXu{>P-^J89w+HmRWPiq0*sllhEfsjMs4h1)8Fl$9Vy?A4CyadbEc@Y(dtPq{j zU)Rn|&t@L}j-fdoo7g;YMHhtT?UDSv_UP}FwZMPpumr*xFglgk!6+jUV%DI>xNoGK zw{D^fd_)DteyM!K8GEeX$DPKH7nm^iNNp(b$n28oNSd4dc0C&$?cWlqP!me+ze-uS< zaoIVgQc!>#$9>D)XQH#z*8IstcBpcn(|D0@2Zpv^UETMbJZA4ZJ*1`em&vT@k-Bc}2o6*7{VJ)L;{{0|jRgrwLw3Q|~3g9PP zeD3mE83HJ-B8l}3UP%kQhZa4*r@?dUn6(Z=5O7A7UK{VYJVeAZxT3HfDK!{6fhepM z{5$#3RC*+Q-V4W|+oqVBfws#=UHWNKZT4Faa{*CE4>)?2ez8a&Gb(3ZkWa&OQQK_) z>A6wzm>7r}A3POXBwlIE&(K{m3Gn%tbX?f;Z*2NUJ$#0ALp@^!cr2dmNu`FqDm|Mc z3QxH`AtD_zfb-)ZCl7#Nj?cM1Qk)4UuV-s3Yq1d^0G2L6kutoJ3CwHowEK5l=YUfg{29VY$r2)2a9cl;@C=4>b-;QuP5zV0LbZ<4U+k z!og3wjA#VoQZqpYFd~^O{FefA!tLjkxUcSvTv-smiCs07qNwP}_#K!0fP z^Oq;I*p%mll_-!6fj-u6Jv7S|3jjg@N`H_n((G$}a`d#vQ*hxRTQ)!{IHRE^M>scI zq$v;H>)`%oCV1w;RS>7v4Dt`8K6?jgaOgb$R9!mQ+fo%wd`*}CGVF4*TEYcc+4mJX zvR(r7ILW@^d}J?B44+!_rKiK_ywdZnG$Gi;4^VZCTXrE00g9z3m{?i(@P_xo{L$E?euz2n!SfnHwbq*^@9D8<6L;9 z&}7T-eFfHL4-N>CM}n^(ycS@PoDry3IV`NLt{c{ypLx771zRKoCIQc7I*XWW(!0z%a&oPiPJDfwX=ox+hVQdPo zus&ey)PL#-F((UrL|@+%1f2p9Af-TUlSOWHfF}drLl$Ryf19nVDw?~neGI-fBF>J@ z%4+c}11It*`#rKYrDMfAdWbV9g)~dPAgJqq_pS<}vF7GwWavH{JZISr3x^O{j0-#P zsD*S8G`Go$g8GIw5-eUw(u`iDUZ$W!yO}dqlx>vtm9zG|5=2TyxJy78rdEeD))HXz z(ZtmqFs0CY(_^J&>Q9~U!NP=t*HKs9QS{(vTUdaK6F1hd zlbIo&Hy4njhTLY|W|RW&P(VZwPWC*1yu#rGj`C%ZA`Up!sv|8~-S^h*BXR-vNYHPk ziuxd+w!dU;r5h9fHl=I^kdm8yoPpuHjH2xIH#u*R2uk){r)sk)Shh>Hoeqmm2EFIC zEj!AC_9M;O7r*3BAzGsu1ysdE&c}QV-8lw9QLfhvxjZHarDSkKLrV2NGyIUtN_X^S zfj`@WtJbk<%iYLlSm(l1Cf*S;q>_DC$dcI0-KBsSw=Kl)Zi>M8!ual%;Edtd!q0DV zP7(8bpeKt7SC9!?l)}J?zV;T%eTvlvC*Nj(?W8wWNvWzoIAt$_+>HHC%B&(Zhm^t; z8b#EIiF;U*HuMXv7GpR=bgR73&Od0#S&i3n>@DGf`4^VK%91(vwm)ELq=i;+6Dp z6Tx4(C^_QyjL0VPTtuo}GYJ~sj9!as@;i5=tQ;3H@sES?ZOwr$9De!MW*-qG`+VZ` z=By(l_wN=XRyKB`gXFhVF6r~vi=BpS!!S>Bt+a7PEV7^Dje}pDyb?jowmU#rm~23|Ycsg1Jwc>hBfR4YBZB(dOX| zXSQ%Vrr>6vrOn8l#?dn7BS#*JwAX&FJr>z*#9j$aT3^Uf{A2P~i;S zh4CCl6}lJKGEBxNJXPcqPvyr!FAxM-g#k=DR@MJE`>i-PL96y@=-Ab*9T?%rk44em zMb{SbbE+@HwAFBTBO{{F4(e2&YH<3Btd{C~MuY9btIWd*L-MC5(th7rE8{=Nr(?8J zfrnb>sWe%w4YN;H|J;GAcNQ0`-Cg@#=_m~UW&g~8@hR;s^waEp5lA=$PDGwBac;{# z4x9ySXW7m}?Pu7qudk_w}xfLe42W4I|0+8yqP25xM#>TFd z?yAPS>b~+_6z-JNJ~ast0*5wo{>9P=ghzeq>F*g|p6IozAIOv4@9a^2BqSm&(Gir@8k9^#Bw3l;&%%e;A9MUsO?7#93i=4nrUe-?k@I3xr>eu z&(uzyLYiMgtfMLUZa;l+?iak8r?R)E=|Jk_W;mzzI=(BH_+g*UmUQHl?%lDsNKx5` z?t1gn^PLSrcnj(5%MTCUtX$+n5=_zr77v@OkI1%& zmp(6hwZ1+uUvu_j_v^V~sz)AQe~KTg_cL6xf%oFyvp^Vye^_3wD!r*Zqze8Vkpq`B z-C^%35rrEl7n?veJSM7IHMveNu1pj61+XVFZjv16ntaAAITRleX}i+-NJ>O z0P$(hJx3t(8C=%$AJr+65}d}L;Dz6{4J(u5p7`z@{w*EF12o(XFCE(!(s!sb^?L6U z=3bM3BJ8d{YDG&I@xy;|@}pa|2<^HfMJrWfb_>`oZt_a6|8Ar~XihcN0ultTjU0L%7{t<2y#(w7`AGJUC=vn4% zt|pGJ>Y*>A$MQv*Uw>yXf)RmAx6W+)f+f|SGe)(cO%D>IP#)9G9%YYm?<3n?8fK?! z6mITuuxLMtQRLdZAlhbxhVwS4E|n!NReegq6Rqpvr6XgsB2|Pm`$I{ZMZz_S-%4ys zXBE;urL!9!w`wijyYovm)AUGtz<)X>8A|IeN0C_MX4i!+Tpq za;Wo~({mqQx;O~Evk8yl@6wxXSsy?8L{>Q+yYTvY(t6=j9HkAb6X7^B^eS^8PA>&Wx5P;!l~S5IS4QqNJ5 z!DC)CYq$7$h4YGDk3vEUL_H^6iD(3mcqlfdmxR1*>sDh{{n-rY{I;3o9c_p#u|iMWR+=!3gv>EkmHAFdt~cn=;PFA&{3oxJpkT|+w|JUpV+Ev{EyPL9qQvRGX`)cUwe0 z=6&VMkk0dV1a$-M@9yrd-0+beU&tQ8t9JO3?(${1W0K{;z`L%`0i684*msXcC6fT+ z>{OF1lupvAoRL>i$33zYc0{{`owfX0m+qy+a^@B9^WAf72gno*xMRhN9tNX&VeN+G zM`gM`G*s|U%Tm{tMG-iU-urxzn?>{uT%O)zcA_AhIw_H7Tg&DOT!{hfwIZYs>>sqF zf@{NxvJp<-(0w&yG^AoM4|q8%4gDS}7d?@vPkBL} zJWx`yRP*z+k;H-z`6IUePs;j9f5h=MzP_aovb1g&CXno@GzC zbsd}&e{f5+;$b~dMap={Nq|VcD0q4u9u(iVF)Y z8JR-|0Nk*yX!9~3=s;AhgxyF1j=M16P2|Loto)=Zvdxh_;zhp9S;OrO#w7}bj5xZR z*^dpX5WSo=e5O$rhNW@4KR#ZT_aj<>Fb4S%8| z!+KP{xYMMcVx5zfKPoqzhMxSH(%ACUT(T%Jwr98}mYq>eL8~ReGJzlXJ9izeMjlu#HU zW6@>imPk&x7T6?ygbT1ypScy=zdWuS=4^8!R2S+k z=u96S|Ll_JI*2{yFTx1{b5lMhB%Z@@C*79rA;He{5R+07Rh;2T-g-p zDkEq{Ja^%cwDxSrWaSy<-S``Dna@HRuOwB24O+vIiZhuyOCple$sbs@mGciHka4E8 zqp3pA{GU6?gSY1!1b*tD??wo$1kauJnhdl-IZ467vBH{7Ui%lF;}P;3EZfMa!f)nH z;S2I?XTo*4N$&{_Dx1CQbm)VAPWX zrIp8Dg%5v#1G^5@eJQu828Z7|`)D<|rQG+|Gr~p1qh@ANzb^RgwGxsp31O59GdW}5 zk0QVgE9wEtv3t14mvr}VcJ1c8tZ>fX<#6Suf)fZzuF+TSQi8M!2KMWgvhcbquA9HE zK&Fb^+rjt}S@@z85Wc8vrxXrMvUvGiS5lf=qI&m4G`m*kPn|R`9Vm1FTE87=?c95U zIaS=N$K79#9q8y30Qr@D@k$yr42>BSsM5(SpsC{dEw8lz__np~!LbSR=&}bulX~8E zWs4&ze8Bq=Er=~}Ba&&(l3zd?bV{ZzS8}s*hEid{iVP}u4|O;}bf5Jc%weM$7gFn2 zkv;V$L&4dZ{ML2AD9(xkb`q$ze{x78vYg`1cZ-=(I_Z3}1|`Vg<0$rQdOaWt;@$^X zodoQH(xb?(F*qTEUo3CaVZm!zWCW!7I|Ch+(}~u<@Mvf^Eac)H7bUeE{iq84NMB(s zrblz10PP5@Pk=-ub{CPCb4+jm?UtM?efTZ1n+Y_DcM~ve3W5@O+hJ&A@w!x`Os}xX zu_={)scyo7vzq_(d`~RT4cM8RInIK{0+=fWgtohcn*{jw_asyG1^^HgoWUwRX7j1k z=&$zZmkphlh>OZm=Zqlq7H~vvAu!$t5{Lba;<|^qG{RrptsMkLz5@i1D2-Uyd9lv2wuqB65$UM@oB!%J;)H_x4;#;}-{~L)R4V@6HIH5P`%=G#3epJm$Nj z3)gH-VTDUmGyx6!YhZkmYTEW0A$2%@)&$Tw`UzSl6JkbrvZN1r27Ogr$r=nY9v4^n|Mg@{BO|5a6u5K7u+0q9W9kDLfVDT%vmLiCEym6yrS_o zxM}d6`=}A1LisMQ4oOIXv0eYZQ{dusCTmI3W~>K47O8@dY7@-p;3t&yB22ro0edNZoZHnR;O8Fll(?&U^*9&j4_ z+--Z^vtdzUFq0~B9ceo5mwclA=d}&Op-ogm1a@?2iqRXEx|$DA=&~+hdOiFhbHDra zk%{3dRCVW$8=VR)N<8xY4ChtIPgqa1Wx$sL22T;HJNK$xZ)HO7W8us$*ndo#d|c@8ZhZ=~#pCu{-!6 z{O4>PlYehUS9|eH_sTEe{do6Sxe@tr0&?Y*FfPy|mUR!&pSfSU4-3;xWUNOT=bfGG zaz34U{!O8wMiD-{V)J#Z7vXSQ!ySv7_4v^{wl>Cx%TLoUK~;VuU+)4xD#^*WSLT-s zY}=xh+C8PEHzO0<<2z2}+~{2@gVmim^*oe$wZZemdx+ll+wUBrj}KUO_P-#$_}aC> z?3w52@1FCA>B@H7UpN*hIWCnvfB9YjT=&%|cXM{WlH85`Ex(*YoX!4IBiXKvo3@`~ z{$Z;x%P$9p2KH1k^$nl4{osu1xTP2v+Bv!kTRd)|E`Io3wHp``TnfZ)=RR+=&AKIh z!f#vnuP?ZdHES=*9P(6dA(+|*dl+(JId4g{rn)^>&X7~4*4N(q%;@x)HG`FnaDZve zq$$~yTKR8l=WakQvb~Cyq)jD*+!fQ1#-FO>i5*mODoUo(~SXjKNw zcKg!K`B8mHa8g(1)mR0UPFuUf1@Z1i6H-cm=xnuz*Czxed8=ON<2@9{~30D6=T zl+`r!UIzZsN5nw@D%1m0CzqnSF3ZpT=GG?p^8 z))kNK_f8}S;_k78wfs@km$rZ>)W@I~Yw-t?DSCS8A=j)mw*4|2xEm(DLL6P30zzLR zDcfA4VWkGu0PX{`P8$SPvO@R%WgfU7ZN=wu3Bg=MeBn@T%;%MR)LnSDL;5Aa~+)9ieeK z)*q}9!?xxFTqmYB2{bYJP+b9j!mW?d7-YmKr*7_MEm>fzpu5Ry*ZK$y@U4H0>Nt`Djt!nlvg;Wy$a<)o3nw@y zzA#m|lJ*W9hK{^_Da4<339qi2)KA2w2WMyN9EKhjb}>0aw(`~X9+)ODREEv{8szkS z_5TMSt`xq2A;JB8k<=ySq047vdzRVx{tE7_U<%JIUL6(Jds0K(!xU=S?D$$XOZ+?R zU0-T)n~?)xbB)i+)nZo3Zq&C9BRisaJi(AI>E+t*5{#K@?a^k83jEebs3~2O0q?$2 zK^g@={Aw~Wc!J(l?HP#iXsGk(oBb?YzKdHOI-X8#A}Ol2N9;2L)9|KQ}Taji9q?E`!*3*5F&jr zAd%M+;Gw~WM&cH;&#(2@K6oS?vY*&W-sCGe^4ikq4w+T39ILXQUp%hcg&DNIeSjW? zr&y5#W?jNA)8e{-V8YS&di8e^$&G$tQ==!*8#n>F22i}kOhU;%gzBwDWRXSE%8LD> z)U2-$JcCtK9tqs6OAic|uwI7UMv#!ysON6=dutzL1cIavaHUIvSMJ2 znrSlhDu|+fS{5KEA6!aAqBFoA2_>eWmbx&(<$d$*q!2Z5U<18$Tp2 ztdi^&xpAQ%;JZ9MP6UUkt<_Z>1qM&vAG^&j25q|X?fQ+(ln+%yY=_gVn$+WmUGq|~ z-ocF@sRy9nDw*3X7L0|y5$e-(4}XtVAXo1RbhHo0$c+V_Lmg z4npfs)QkG!`f)#TaZ}Q%q+GzJCRx3!=$MqSL%`Q;vxX+;Y`F{F?N8Q>yoK}GA?&xA zFXzTwKz&nw?}7}A8xQPFolQ$Ti%=WUJCtJ41zbQuF+2!mY%a*Y!iL=Amm1n-JqK4BzC^f_(b$P0mNzJ(^D_j zde;rRX@wNsRHhn+f8~*Hv5HWhOtfTUZ88sim=o~Ier5Mkvx%E?tDdN(_7wIe@Rh8Z zTrE0rNCV&a_Xm94^=znp(w*go8ce~h1*EZlinLZ7F;w+8;`uk`YyrRuEZWj*9Ydsqh ze~$ol@%r36dM{5?$Af#QpYH_Z7P-G10=nkHdwDJFjoCyD>9bEz70ouz_FDQlNrnBD z4a^R}QZ+H8w=<`~nA~di<%IV5%__uyQltF>B2mdCz-p`c6t1^GN=NIjvPK>fekGnk z5e~-n+EBv9<44uO^jS|lzy0a-ginL80@y@5UH%Xml@g_it63g&06eLyuuErhmB{fv zleO)zi2^bv(Xt=-#*&=l;mv=wD+g~;(#W%Kj(v!G0D!pu8l;CTu%vmtk@0v`nNmD)R?HrJq}0FwVShIM_pYw*R5F~Q zAax0_=P$eelWKKf%aFAst44mHflZb&XEp^B!GaOiYT$`bjjFENRGprb6%ja-tduk+ z5aP7fsDaC~rXkp5l7I3tc?Zy>6|hVw*Z>n`(^bYt2g-rcOJ$I0iOx^^+Izm8;R0%W zfsc>C6a_B-I=YR&ksiQJ;f$hPk2~dRGa-7F$IE*t>GZ~e-ElzAWytx4+YdTO&4lll zE9zg;>%b*7Ufi(>w5$H%@gB0xynv(01Q!rXE{e)IDR=2-;S=xjF`*HN0@l7sTABV5pP}yXs7Q;M1P9 z;vO>OUcdn1VbJU7#i>Fo=~D@<%rL1_C0YQVz~e4w(B@QGbgSA*kcCzg83jG51 zF&56Lvim0b8UgvEq_AZDQEF!tN|)!vvCV&KC})riGkU+=h~0p7=>lg;9o7p z%!{<^zRN?`swM@v@xmGmb5b;KGkJ4~bTFA`s>2XgSZI#A^d%jKPmS*vS7m41hV=qQ zwP&t(2Y?!Y+%?TFc{C*~3_#Td*jJuF+k3HHllV;;^B_x z@2bpuzuo11qYn5suP?5I|0m^4>Xr<(LO^p%k$rm*$Fv5Vc0M^m)&jxH{s>mX=Ro^4 ziN(mxJs2$u$wzR${A@f5$N;mNlnQkdUs>8ER9wi4BY3E~IMCs8euJ4-e4}KA4`L`8 z!k2B-geULHmH{omQppc^=i1Am_lN)B<$z17T#y#NYK%UjdRgU!Y-25G%wuUz#DoFl zxE)Po95{~iEx9wLh4AgCg(j0)61_CV10=G`TWoL8*9d)QpZ0z8Iw#Xsc7=GQ!$i0g z7Axny;8hzp>NJ8MwynX~J{YNd`IUUrYD+rZ6I5EEn(!J#+rz*t*gfIXv_Bw zJ1UZ{-#Vb#gR{)pfa0Uw_i=-`ACqM!HEkuUD()T-L}V3c!qRk7sh4+#r*! zqxRA+^8(B(ma`$H1M2pFnpYKR$p)w|^c!9=W}Yc^%Fu5r9`;V}&8MyF^=2=ek?3Sp z^|$2l3w+65@=Y=g8C{1!41CKKfZ`temHubs{f60E2M>!w3HE#UU32k6=BJIk;Qsw= z=CnU!O7jC%;W0s#Du1AA%Ca5bj{gjyhX$*+4IGg0GF{ZdJLOl_sP9-u99(X<-OFIN zI71KWnXEK?vCEwpT0u2OtGWEBekuC)edP1MtKQ+b^=t=bhfxy5->_`?DIhSoRGmDn zl38_>FS|tq+n*Xj?c87zd$c+5MrHj%h;?Z5$7PfF7Ep`FTze5=4TNh8JtzzD$`Oob z=p*?xoM;b4{Sw#d7Dq5VfqU-*u*Ki+m@`>+h=oKHRA1C%Rp+kGy84C< zOW@2mCGesYYBcEZ9IG=HTqx@cNvCf+A403YP?b-(m8 zyXeA}NdC;Z6p=Z_8LHj(!GuI}M+Crk_waA_vpzBi`AOzQgmtmo~Whv zag^`G%TG1>zA48P8516Fj2fwv^sGduO`D9)Tw8NBF7xJgjT}UuJ<{-JNO)X*{M1{2|JU9Vnzt)9cdA0$lfvIZWA}QH7hV`)&c(fLSlPMt_jqAr zZ?fCNvqr7T0i5aMM@gi2>HhX-eAn4Z{mK4wMRw_HtK&3u12j0=K{npxFjvjcDBQ@w z^p5r`t?q!9i_g+s_ijj%pFgj;sw3GtaQ7W%Q~ym`FB-F=wyTQM~B<}Y(9$X!t2c@-aXeSicokz(R53pSN;#cEH~a6sQ5?xvbHYXVZdTa zY&cQGyR@yk*Q)`V46}O@C7TOQ^Mh}6`FowS{ta;3=ODK#1+|BtD8F4=4KZA#!0kk+ z0afx6^Rafz*GBUv)4Mk;CvDq_%b11hYHDyiDXD@+?$X{eM&;OAUS{ty-$gGkb>fy4&TBM5C&ROK( zCd={n5^AK2VDQEzI!NT~u{;cPgKTi9uFp?3{Z3s1cHOVLpAcCvH~}Egh6JAt{C9&a zv=0p_c#fhk;{)~sXN5)BzZ=I5DLDDVmBT^cXg!gF=Tx!;bt|S;!Zsx^KY&T~PG8aK zVlKqz`@rb&0$jq2?kr#|1|+xIN+@?QgOridUknA(M*gaGKpu?-BC_v+ljy3IdM4de z^De{T1ify-v(&_cBxN$S0oODH+S1y`-u&IumGtsn$wSR1{~g5p<1}$#j5wcX^qwl` zb8WY;m8i|eE-uIF|7kbVK5T+c?d*?Um|}pUQY)xDj=XNg;AVunF5mjHAcIx=Ncul1 zDYvnerh1y;5cr#?LuQ^T=GUtd{&xZzHFe`AC5I*UFKBANisj5_xn>bAgBz1oYT((m zus^g6l1+3zJ^nVS-8ZBz0mVHP0j^wgUBV@kT6cV{PB#%82P&n@2la6^w!s;Bm?1^+ zS}!-6F~sV8S?3>Mkg>Si=8=u!Lps(cxY_Xp0?i`?aMBEF^^esHOmWJVkG+?ERBxw` zfsauxCb;Li{RsAjAAe{wXFiG?$_Uy1@)M?Z9V}PtvuA~aDZ$wV7AD!3$MQN}W;hEb zG@Fy!n{drnTh!`5mmGb@>FE0S24f&)d`A+jS> zbac_KocZ;)g9!RScq~wPk#~KwFOp6KZ2}X7a`x+yfnFMR58v#tUdR?u6Ea?o=3g5D zC5dlZFyo&Vw&MLYsFprzl4`IHEz0BcQzzdntjjF(@nbZ+qw4fn(t(1N1-;7#?je7E ztW#0|j%M9TF+k`UV4ebva~D?($tAO(P+*MZ_ABs^rr>K;m;C>#+1~!0jJJ5np5jj# zyPN<>__~5csT}QD;}+-qY^@2DuUm#xrR-8)y)%qX!ZpK`R@Wb6^K^ItmebOmAgG`; zOnpG108jb?=bAlC^n+Hx7+FKWkhK9MVMdhOIi2g7gOlA^XpRK0YG^Wid%7 zRojyRWfiR9oO-?QIz2XTqhwOAr!4<1>1*JsxDW1B5HL3$yXMK=SnXam->6K1kM-7< zb<8Gz_ulaA(%W;lly!$&8q%Ofv|pf%l)swIK&eLf#`(sZX>iYq-tGJ*4*2PGJ3Cdc zME-Pr&I{a9@FLrdxl~1>#x<7rh)bq^b*c;x&us7eXsaNX-ns4QRMHOAH1#s-fYnhK zf~bt^KJAiVl1>={d zz85KYUU4UVzMLv)yrs?l}~D#`QW}LJBcZcN+*H7nIZ>{g(V6 z2Vy3oS#HpWf3r_&EX%#Ul*AJi2g{BN=Rva~bs|8G(crikX?0U$cVvy{rnPrgL% zA!XlJ6%hYM`?T=nn3*Vvj(AfkPKPCM#lq8bv%qd9yEH)h@I1`sNSIA4=UuUoS#kE` zxR&9dc^=xc2h5*nhQP_cOg+8S zM&(vF1>`XW_t=Ch`5XV%Fit$u4*Wd9cT*`e;%*Q*4I|6yMT2`qm*TK_&rzQr?O?V^ zdd|4I;?~?UXmpA+Ww!WZDy3znr`yheCgsKr2IYF}xZrn<*{p-RiPrD8v2ocR*fNPqfa_3#4==&zYYkteEp;5(R zzoS=da`dXWPWSE%06j>F%9Tp&s@d%VG72hAcDkgxYxBfTkgt;eh~*)kg$dGg$DIrz zEN9RQ&&cs-jq3$yn4Csy!#fD4uSeLsMr}4<%)n>i65jYm9?WT~m0B(e7LpWGsVAMr zht!S1yth4f!U#im1z;*69Kj3lNlB>LM+d8n3ENIygpPsHA5wcp6#!$?bhD4smP~+1 z8vD79$=kOCFXan~xbcFQYYV+gUvJl=l$b?lOeh$XB~fYcdb9;d?WHWMvF z0x=!=&ykJ|X{`J-$Z;P*%W~hw(9_ZRY_JqFyS#%?bjqS*CT31p2KeHcN58p)Q}Xo& z|CeY1yFi7PuS1jN4ofvF$b`}srIj^%cU+iaJXL6Gz+A8Vl0Pl92Z(5h~ z&2#_aj!|Gn^JcgKGTxvF9qVoD;ClhsdcP2O4&GOi97D><1D~s{(BE!@(bSYxK)L=- z$oo&~hCJ>!V=sd64Fi5*Duzjpx8!t5%g`fm>S_5low5ewD{#o^Q~76P`bX5NTjEnWmd zXY7})_$klOefHIJ4^={#3Cl8+N0J!o<$3Jx2#NCkPcGTV>tXfH?vW|mzKb|O$o*78 znD@bT2=sdZMiaYYlFPL=$cZ^I1OU^attt4WW6z9!LkPH2(7GV4BFVt3W7c6$m;J&b zy^{$70;XNyes0$m#4mV1GpSP2v9vsCQ>JNS(D-a-*7)T`2}v|48SO>vXS+|!k|R?r zHdnGdAIoN1t315DWqnJm1g>M+hJXK62x#LQ&$c80uHcU3TL-u8`|giOI3Kgku+k}K z`uxg3worBYcJD)uOYqVzsD{8;vbAj5`ux4MkZTM3WHp8_?&E)^9dl9*H(pt-D#hw} zoUgiHm7j$9r6g|>pX9RSjj))p_@2WqI$ZQ*QPt1E94T~fth2$Or;p37#a>hm@?*xn z2$x@VVK*0d26A`a?6&lyJv$#+l_v7vGoRt>^JQVjv&bHd|4-VTeyZ91M)WPDOg)yZl&v}Nwsi)>!o;|HGhqjTxAXIdOrv^km!c>a-R z-hCLSIevZ}ef1M{1`e6H^hqMWrX$+B*;fU^{r489e0bLUEasg{K{{v(KIX2;P-P@v zY@uhZYyN>~9iehML|Z}MYBu!#n#7C5rXluhi}Z4lNl0Gj7Ww|*fWmv*rlF4OaxVtl zv{*5M*Osl#S7me~@Aik2<<@R?Wcw@OFH7Crt129PpzxfNtGXK!b;r`ibYkn&Bi2uc z97eWfKK;nv(<#du@Ab<4+qMQI8Mgm)R3r9CUCBAVWAgdfAK#Y>E1MNlL(fq=x&+gqjT__EsE66~oXGJX_gIrM3obS>GYA3uHI zOchrAd=a?{RWa&mJagjOo_nF1tZHbc61wYa%!Spe*Hpy%vS~jx1Uanykw1Lprw4a* z(mm%br26+eqgIlOXL0!@9O>f<7=hODd&)k%7M&caLe&xP87p`{Gh$rd{ZyBEUK1$K zeU#yBFNpAj#+C57?v&~gb<~ytDT%=twhs#zX+U-_C>D=l@{ke_w-4 z<;9TOu^X_XXT7nS{IX)dM&-Cq0SkW>oCiII!`%zN8SSiQtXN7=p}-37fevNY&{s1A;7bSPM_Io#=ej zq2XXcPkS$c$oKyzj*zJ%98!Dg`c_F?mHwg|7E0BfeqnW($l=n(IoWxs-;9)S-wf0< z4HuPh6q{#H_8-CVOJ6G`R|i8iQ4+bo4iqRV9L9x&$&^lA?EH<#jeA%e4ibURKM%|E=to`$nB_0NHj) z83DeirR`uz+}-&Uum;yEb`UdE7wzkf%mpROYwHZ-eUH>R=0lB`g@Wjx?z0|of)=1u zdl9s*7fetk>`MbkP~!RKu;hafXrWU=3tDy7H}CeI$)QSE3?RmW3FVmsxIN-|JFN=e zE&!Qc}s1UTiXi3#TLCTO!+_Nex&$F9UcA1r%!XZn|6 zdfj7m6+{!zu968JYyobv1TFhds^L$)GLkrp{m_W3e<%Z>n!8#+^-K*q^f zjITGpN+X8@Lz4ZVMyH6!1AWb1;2Fr%rL z{@@-!%T&TKid`?FKshcElqtr&_&Qb|15E+(4yONr5huVG1MVNJkq6VcMqnCF1fTxi zKT((-q|sj~FNc#|Eq!v33?bj~2CoO4QQN(2;_H@n+f^=_1?o1_5Rwa85(^tVa~G-$ z{WdKdVrg!4|uR+-^5I*EX!H*BXiN9Z6rVgNA>NnYcA- zRHXcCR)=pSJMFDF?55~51?eeC-etfNehghLLZgRRAK|zb~!RXLXItutU|3( za^+d_D$K^e2+#{y;*ZTN$v(GolSPnHX+Jujp1lLLfJO>ybtb?S0VXj@m{B0)bwd8) zm0q=Cha|_td8LLQ>!6FJm`vpB0VAZZ02}c7xx=XCC%`e-;40_WrlTe^T`o zXTn($NP7A?b-N7VWbL~<%P(oa3sKvd8shnz%FAqD21~Dswk#p+|I;>w)*Fc7q#Z%) zEcMq!o_G%c!1uWL`&(~}k7@jp44nnQRth&zx*hhH^nt&+ zQ)^?6=676p+G1zURDg5+wK3R8h(sO`ziy$%w;il!q^%eL5_i1>GF8lras(Ws2S7Lf zV^HrcFoi-dYFX$d18?*K#weg{jvFC8sjcHN4Wq+C+N)aD%_ea19!s1%E=OKv_-#4* zS>b{)^r2|zVCS-!NpZ9};Q6;1wKzN@q=)xe?Re#Wx#F;<5rbiy83&WFb<*YUkU_DG zZZ`i~h6LR}%=2tzJP>Ktw*S`riwrep)h$uAbY02E#wku$ciN;@8gh9Viw=u2wPI%a z{rX?a{ahZtyLQ_arE3@<4uJz|A_$rsbN2bGun*7LuNnaE+b`Ro&lGDE4BmXvgRG#6 z`d-y*gCI3iDdyjr-ID2KaQPPc%*(wXD8+29h-m;#pU8CyT-TWAOMm9Rc=Nu(a_P5_ zy38&me|T1al^!jI`rXmwcfh0Bapo7m!nG-H#x9CiZR2e!0RP4&CCdd*Z~@)9!GW&N z!WOR_qe)irYl{`NPJk*bf34j*6pN%=e~$~oPs54)lHC^ROzn9o!>TT8-2SEhTAU%w zJ(%lI#Q;u!3U!2!9L9FeKw zR|1T5>*TK@Du7@d{`EhpG)p(D+*jZBtd2==59VRrZel7@sX9WSBM0~Qk9`LYh=bie z1a2camF#9qIKzN9d$2<+A8?FIkbn%N2TOj8ID9 zY`_~;ysJ{iiXJMgLCVAloL?#ma&$pc49=!A)VsIA=^)kH)Sy|HYLhUb(*@edwEv;% z&Euhb!?%B}%GxHosVGH~Jz1vBR!R1drm|$8kewOjg9sBsh^ffFZ-c?uWiM-tG4{2Y zF@zbj^t<|gpXc?we*Y$8=AQeyuj@R{<9r`}Dc|#Q;vZcBYk7NRzbZT_Dx0v20Qatb zFE)vu(nM@Dz*0_vd#sii}jw$B@AluLdpt01D}8A)p8^&yi_m zbR^|V+8UFyuHn#E(3bfRvM1;IfmMWnPYieb_lj`<383~bLML#uhku&eupgh%2w_(L zGuE!l>N5XdW3uwD5%(~z*I2%{c6g%6QPj84RQxV$tWf*9aZRfsrV@$nOlKN0f%1@F zf=}`y{(C++n}=N?;nQ9ZiriWq~E%UVt69Ne$Y1P%L7Tegt?rK>Oy;L4iJ-N4L}x}tGT_GsomJkN32MklPg1lzFJEL0zj;Pbe=%RD&!W^`TYgRGjO zb3c(zxKr2rRY~_uGLGLyXWXPmK_XmNzA?>L{5@&>V<_60>HM5ESY^IT-UQ^uHXyhD&ixrfd*9#(YVye#o{+!LJ}* za#(aNjy3JkrbQt8ZM(;NqHk$M$ZEnic$}C{%s^HZNvfVY+7|NrmRAV9H0^NM)sNr1 zTrlEVg=_H12#0!V(wO~YMYWzFpQQ%*heKhH>27$tYg{+h6krzuy{1N3$$!3&cLly- z_96QAX@fAf7iDKGGuVAkAa|&lpDjIBNM?3Timv#QKm5vMWBg`G-Yu%$Wws?<@?uRMxgf4OjXWPS+S~7j<~Rz@vGl&MzZ&D zXHM6cgde$*2GD4^T6>)46tjWKk9yPlLbbHQE!=N-cLpsr=8#M5ou-~NARn8%trd_)|KOcmE@VuAFN~Fls1gxNGI9r5kBl932l8CWx>^ zOIL5L&DpgfQgi#7r(GA1QcQHb>!FQ%me=d!=Ewi!+gLa};a@c$I86DZx;Zj0Q?RVg zbj`S4spd^L^LD}dRw@PB30%4HN)EB6tv?UXFYpto{^2HdmAsoM@ImEe!&Z0mclGSV zcG&~Z(7dZS`0BkSt3u~|mxJsb(T7S*`T8PTmy~^GZ6Y26M=sP+=Z?!lrccx|+TRFL z^FNQ>l)=~UXyp?UcCX*lGV+_2{PFtNXq5eyUB9=T+3^}hoLYZ#;aJ+(EGBQq+Vc3; zGV>Il*4~5v@LqQ+?0`pib3#dtKg>7(2}p-&0apC zpe4#QTx`5JSfB>;v-J0Xs?z71aZ}?NLf8y>?`@l%`wmDhgR}T$H#H@!SYQrM4Xu*5oPUP8{~}gqDX-KBhfz&#uag=F@w6n16lGQjhV>`R5wC zayja3e6Bvbrz7)<)eVpU{VO!2aP_6^uG36075y4oC6VQsM?+ebJI&T6XbesT3|QFM zR+K+O*9Yyi^dq`KRISg!Q8uSd(Pcy2j%qq1;qVEgGZD{Fj{!UEgtoFvzjPe)&d}|U zLZp+C*Sl*s#f!W+>0G5oPr?qSv66w@pu1w~MC9>+ju#iMh&(bOCB^pf=tEv}3Ycr3 zU$N>%Oka;E7VI=UOf;-Ly|b=TG4&cXt!r;PkAC>8NcCCuhbxQLKtDgkUxuxsVPg~1s~fZ1|JZNMs{5DGWD*sY& z@&(DIyjw$hZ|z~gZ%KU!(#8TbOqbwuw$;t-Ay2y*%V;6+C7_h(WC7xLJZNq-?xxkE zCY>#yp_vz8d*08XlrR6cQvM+HeNt2PlW@MMSpbb>@Alv6D=!Sj){MHY zuejNnkWMNsFTfF(RO~_nzcb2k*MUgWWbw65m-?UYUZRbTB0ah>-FNDzK7aM@Y4{GZ zSiN$@-MwmXmVvcl6+DnkM1wBimff#Eob=FwWeU>wQ-xb_^z$;ur$| z%V-}KQE|@>u9lan6%gF`WTq?g`_Oct%H@v^0Hmtq3H#T7t~9ApW#Z&uS3-61@1BAZ z67+;w86b&VK0^W-<&3?HfvPz4jJ4z%i!N!JkR9np)1UJKt}%!t6MYbfG_w6G$ssRp z+4s=#xd&DtKhMb=Kd>gC|3rJsj4rTrWu}M-EMB?*?t*~Lel-wIt*rL__hxN)Tj(JC zEuzLUeAQ5gH34cz?ocfFk-+U;^QfhoBN0E#U(-Rm&PDBG5iW?9KNLbC5Bu{c*<#DL z9zINE)Vbq+57$JAvI=w~`zG6fk6e$SqCf~Gbzb)q4_Bl3oWl87s@%A)I(UkPq-2aj zcxo9{@1#?(r#^Wc!c{BcD-KV_;Cu?zQ{Vvqq&(y?PbTGAy(>Y0b8Oz-X8sFHuvzn5 zDc50&JG-j$iH&TvMG|5MIFM@-FFktsY!gKuv6J!AUN>dKl~|ul)n9;fZC-l^EjB0i zcJuXY38PP&H`ZPwcJw9Vr=D)XP|%HgFd@ASZZ=oTTq$q2*VxY9C~3Pu#^KrXt*EF@ zg^{ZR3Q6-ZmLyS`$5wp_7bqW?IG^;mQCcsRVFY`P+psAnEA1y8<#w@1b= zaM%f-jT$uRbFGw*PEm&0UA~j%iSgcf@zA7%kwV5$&E*)$r30<5Lbi}T+jm>YpqSmI z{0frGY}9bi^yl{^_Ic%mryfvWFic0Yj&SDMbctGYvQsN16vyC_;{~ z6xLXtOJ|JN_dJ|ZFkq?~4}e+|%zq`vdooq7%wi$3j-T!?T=)TohO=iaU)tjHrYu2T zys0SrAl@ZP#wAd^B>QJoIXOXfsu)8a?daKIAHyX93iK%gQH@b0Al{PB1lKRo6O?i6 z1193-CHgt;u?Sn>X`HV*h&gPGN^%y!ymB%B1CTbppH!C!H`VxOXPpy+i{B7cmWtp(={n$mAb({mCC%7MkVd10j)qbW~e`J|307`?UI09Lpl%sE^bog7X zW1P{9J$tuN@2o9OhV1zH$neeu>qr>tjEf52Q`is-jzSU9`?LA+P*O0@_HuPzB77 zge~He+;Kqwxn+{y)%)PlXboWPnDNTSZcZAun~JE~;&GIm{88V{)9L3T<~^pdd7Prh z-3LM5RQfqG1Fbq4Zv&U6;Uco^>ip@x)%!(y5YJekNA`L0oEvDNr4?UxsG~Q*cQ77# z7YJMXaXz)5^E&5K7;WHvttiW|w@`Cz3L%fZ$^bAs{@whR8VsZAgk*5v1S2QCPcwu_ z9{NsHI%#M@giKEr-Z&tiJXN#iK>_%qt@8$p^aeCdKu3w^D#SNb%KTr!=L_DJ19Xp9 zhmX|9?SVHTACG`sS+E`12T|}s0M@<6?`78$SeHwJ6r|tF+-^1UE~vkMyL^4@KBD=x ze4b)z-@46~5rH=XHgV4P>?`w3XnVD8G-1D{kF`&&ZHb?Qb6y9Hy-WCF<%yd6Y<$vl z(-Q;6C@$JIY6J6sI^U8xu*<<8Vr>}sJf$^AJLr`D&X<0O^}<@DydBrTm|7Sq_%lW_ z_IQb(%gYkq*X4NF_Hj-FCG4{MZY6f<-@uII4IJrV>4?Byj0IPbZA~ft6!7_4x?(n1 zmuz^1kktlK>A8czCrVT%c}~ttv4|ST3A%H1&yamEaT-{m>Y89ckonVnwV)%f`puZ& zOAAvh61JP1WZB24<28om#mIw!{GE zJ{&;LIaRlgi%j5SL3CObaTb;W_EXKDTx7R@5GhBr2#J8Muhz`ojPI5LU~b&Ib-h8p zHjG!AfthmjEfQPC+ugwgAV4X_4|P?~JMi`tkY@A6BNlmgF=j4!1K6wsBtx#fr9=SK z!F)uJ=33n&HXYssBaiTOMAKcd#p>xYxZfe9kpx*;kRr-HYy=%+ zRg%NOE2Ft;a<4(q9zGxI4|@1(oJ*2dZHe;z_ZAr-bnu%4^var`%O(O8w!0*I4pxSy zExK{%@c&Y)_AfSYe?{-T3{^6`~HfBeX&B^Hi5YlNbEm)pgJxhGKm5 zDE!&G(pqd|=SxEy%y}jk6jB|3Y#)iu%o5@8cyRgR3G+mtyB3XRmyGDExXdLsKOn=vwaSow4;LyGxc?5U0t6^>3++iFfqLO%1))v2=eCcivf7bcMxnCTzRZ`0 z19I7TsE`UQ6jq_ujuLUY2WM5!qWB4G77*8%?jvc}x=nhHeCOm8E)g0|fmQ}hcexc@ zd4Nc+Tk|a4{U_8`+xq>U&+YQ0a(5^yarAz(;^E(;c*4ZNg}MNBL7qZPK!GzWg6T7V zdYIU*Hf~un&hG$U(2-8^mU8m75B1F(xT;l1f={3fw;FEF6(-@6D=OdeF%8t&)vFGF zrW7705FT$;9?hSvOR<6IyY8Aev-e>V1bAkeuLfSd{F$A^9AHlhTIWWA<%T}xu{rz5 z=aSIApT|D=FnN*pGNo!0ppk(=m!B;-Rv&_ePP{ruT^+-HLgOP_lP8g+d-JkEHs~r+ zoo~|5=%UZ6cTqb{Zk{CA4UmTe`PZOE;il+Bf$s+aMe8Y%l&$k)nhEq%*^R>s&KI>>TvHs>Yk6+pDmbO#l6` z$lVpZZ`BKRvLfeZkte!YDT^veMed-eH*2YQJ&8dDdC4dg<1$Thv*d;Ona2TfdB^po zUXv`ewYy}PcSkO4wswwFKS;*697I&Vn{QJo&U@5DN{aAuU3TucW}C4^i^J_GCY7?4 z{oe)0^dy&u3(f5BhZ%OisP*g*o?!5HEi<1|_mfRpTQz6=ct*GH;oZKML?icKTZ8(y zT}MoNT2J#+$@v>=)DmTEqDOyhn=o(8Jbl+@^tPD70^8M{nXwdkxESy78g zg=84J+R+7F^WvQ(Cb8G%$|uO>Pa-oOcIwc1E9<0+`kF<~xNXE(NJkF}!YW11OpO;CYnv5A)~g6^lE^DsxPp!V}^TM=aSTCA;6H3&$<znEeZUO8 zD_a0GS*ub=y;QZ?CUiFO(Ryf?XMUUWWu${{tLpD93=WdyacUaJ3ZxISxzy*6Xp1pV z4_BurnZlh*tc4BMP9=Y>D)742vi>};Bj{cu${aYhW`Op1^0J+St&37(v+7EA5NmP^ zIPKVz>}%r=2?m-5!IiRbzqolPiC;pHZ^6CNB-pGtLbcY`=kx`24&4c8_%rEF3ja!e zfRAUso_O(KpKuoRYH7Gh-Mr@nUd5i-{zKLt3@Mf zH@z!k>{QYP-YkUA|u=_Ywa4%PPAE zEv68hbP-za&Nr+ou}bglEZu-1S9m2TWR@kHA|R@}I7CCKV5)*nZJoZan=3Rp4&2SQ zYN5fm*5t%((~PP$ksHUa{M@sY&F?xtI;q2bh16Wj`MJ9!eb#;Rrr*=oW&oFBYcBw~ zUX%;TE4?DJ2A3NgNB`;;!MBdBFOs?=e(vzkoSjG?KajU}Y^CO;?Grv8y%^EuyMh>yr+Dpj`#@2<%nHEY$`%u~e@ zVYO?E?J9i>i6lF<89~yaS^i1C**Nq(|ABRj`rSyM{Xe@rJ%lCHV2xsLn>9Te93CC` zey!!;PJ%;H=p^XS6!zmBkrOs8xC*^DJ`i3Sw^5@04|uhDwVl&AzhaAWL39guLW_dP ztiiQX5vmbWV172G4Km5-gmGzFfg?f$a`xzOXI97@_Y#VsRmpSm$f$Wt_}dKg8zz18 zP6y*NVfM=x@^Xg82RfUElVvA0l-Ba*9UiNJxjR+;PVZgUEocXB!#lD~OQUnsY8A@I zbSUsgsQV(Fv_?*E>3^Q7zu{*uq0h6X-+3$H2BUY!j+LVcVc0Ow3^%yX6yI30mdLhN zlzP{jIc7dPn*@EM^Zk4G!DBbiym6^HU46daMD78aevTDqq5{}6-IKjaP@rA>6lucX4@+JIrsst2HeYs+# z^;s{w%b^PI-)c0bTUdaOh>=&}U zkb#XGE$u?lq?Y5V{)c?D@whZLkc|p}=dE6Ee{#0292>b5y>xhFM&WyIeFf>vo(Str z!tHbUP};UTD(8!_j;vG6hPPLkJJCYX;FP=Ru3yO7n>n2=g)P;^`E?TmQKb;3oTB=H z$J&CvgN(J>2Vb7QuOQ2O@7+y)YosCC4Ck2f&XV{!~6EKS`QupW2`ll&cBG*)>2*diT7SyRfs=%mVH_} zjLe7R+SXsNoq(mg^7oXnFWSb z^Kp+GjCi6x;~0%&XfZX0*t|58>2=dla~0Sz=7vp{$L74yfZmpt(s1J`VYHhAmNk~` z-b3`cTe_R?2aeGW&ePWYTZie%4XNToLipf@(*9eR=l?)N5ScJw1fpMXR`ioKF?NgB zo!Z)U7PwnuB+FFB97{iK0t8#EJ^&|?hZp=n)9TR##21vEP5Cb^GjLbdyyi;@Y?AYF z4WGjr7&EsfbYLb?{;n=CI=n^(R=Nq)AD{R5&BP)bZ{HC;WJ59Wn6goZByCmuj=le7 zm!j^*TFbn+vu*BDR9yeypY7_CdAYf3SZu4)Pn)wY!ivSah+VdZiE?_%()JfX&N8OAWuHT7ycav0RrCP~I9Dc_VAzcBVUCcpygleH z&92b?uKxPeu2d7jR&!rlVqmBQsgnz6p#>LMbJemJH@7gpleRtmoy3&I&-=yuArK{G zu1x6_a$v^hQ$QEDpYy~S^^YM z?+0wsQb%rHIBk@^K-i3qO$|i)qE*M>K%7y4UgWONcA1xQc=a!^P30tl5{usrAyi+Y z*E6wAB*pvTgBxRS#`fZi5H?SP3w0^!qDTsQHkZV`i;PZz_rB@F=E>L`7ss`Z)Y2<@ zV@GySy$*E5&Lw;Ig3q7^I4mW@@QuY$Oi1F$=qSYz;CsHyk)X;2NMphnudJ6qaa;Um zf$z2e&3FXtBeVDhk2xK4XmaG+Efo1jpYWn; z$b_f7x_mo?$XNT9_UeRTj*e*RBQsMa-5yRtF5p0Pv9=8}Qu-EMVmg&1u=(Gy0Z>1t zvz4Db)CWP*LfE!53z^FM4#rn_u$O^wq~tVJSp80owQZrA>=tcLRC+;6ely?yqf{D0 zu(p$RXW&zjGn!`6UkyH%QcZ$?b|+wg_YMd=D&B^HF_XTP^8F8GGJsIkgljF{s*ZxE zeQ^+n_L`n@@Jx`EDc!9F8%oBOy93m3Z|G}AAGA^bXA&J@0jE4X@ymsa>9#%4NQ#P@=avwlUy+ADA{Y!TNL<_OJ@k|)r|2O2 z4niKii|b|YEagt>7fbSkXHBMy`l*X^Ed|ve7hn8i6mELlhI-0sxV^l-<>WujgSY|Nim1uEioUlDrfu`B+~RqI3oM zZs|)l{@iSndG@rRIz5kWtpgkpX&kTmcl?2o;ZL65X@~brFcPD5U${)$9ZkqvcnA{m zwnR8yxm{0kFT5EetKas0QR;tzA$CHJ+FlCCMA-i32$2E6_XNEfl}-|lWPB#k_K?M7oqHdc zSArAhI7$-XzLoaIuYS;{G5sj3pG&iN`yV`nlf>xqpcs*V6z&3zFgZ@O0F{J{PS91z zo5Z_>i{gzdR9A(71nQDTt(l6LEWSnBQvCOrwJnavvJdS#ow|;S7wvX0tV1>$n#(~T zim0^2C67yX&wqmQE12=nN#$cFad|P%Dm6vg+pOTe#{}?)6&u@=o(+RZ^BX+zK-d%P z>96^kri5YCGH^r12Jj_auwF-n|3I$%h+Eqq#Fz9whq$@j=Xqz*N zw@j0Xh*nWokaBWQYV*6}dBpaWpV$M;v?n6>A!)I*_U6zHksn{MzBSt9H68jqe2!qS z6cEWuVpOS`dm*Dkg^KJE2=gyi7SDGv|EW?)lj)*t(< zyeya4B&h&%H)LRx6!hXGPL4x*ijIqFvKGd&M&}oEB1rmRfq*?JRO|w4xexnDZP(94 z`M=&R)zL2xi0OXQU(D1XzsdQx?zV=^vIo{Y$g_UnZhRmZibY1{`N9-{V$86JL?OFFR%2v_rAXzmu6WX*_ncWIYuJZaIgX4LMnyLEgZm? z3XW%^tTc}+7viR;37Se$72jJ-&P$xBKmRe4Ph%dK9;8JVN?VT>NK^t4l-y zvUYBI$ly|IaKX*92I?~x2h6i%oigyNUmo@RjFpxswvsoU#?5>n3N+|2)R8SbRTPnx zrsE?G0fo*cYnFi?;m>VfG@0giALp(XFU#%ou0GldDfS0p0^kqFfW8=N=Q(vb+y^(| z*TFtD6nyjR)FWG0L0v}Auw6V?RdG|lAQxYNgT(e;B14+VQOyFI95_ZFWNMbBlaA3W z??v|*P*GKeu|vIa_=Oj4zJ$jRrht++*f7=EN+Fb#R=+mLPT$y{@>7{-G2GLZ4=8m> zcU1&VeJFOQPO;luXCFm_cVa>N#*jsP-;)mumSRrcVWB>OwYq}LH7`MD0jD-_aU0emxeQdI<98d)QzTdFU;}wPQC9(E!+NC8}_f$ zxix6(F{oXwUUV)oX)MhOa?542ni8tKBwjvwxzYu-G@ak`QP}tv8z2l) zNc>*sXtsq)2(r=H8nmt!G}(0v!aj0&yVP_t#;pyuQU6zZv>bEdTah(@N$ zOU;W%Lanz44+ldw06ylIfHL9An6R1mr5i&K+VSpEiCDp&l2;?e60TWbCd&>zvGrs_ zI=UKu!qsBl2xWqKH2*q%Ni6XbLW?C!EH$;mAd%K1=!JRlMkT9VPy6Mu`a1V71B)Sd zJ#amh9^>l8&d*!f0=MQwBI~}y`Up6VF$)HT#FCr zm8Y1vtGr5G_^8;1>zn3~1O^X*nI<7nr#+bTf8OD~G>#bR32eC5ybK*`Vl@t%<2}u# z0;BswB(8c^BRu$qX~(o;Lj-0S97rekmx_hR_6D$t zJ5D#Ao9s73f8Yy4J&Rs$9=NMyxfX&E@76Rw{g-38ANoDrF!T^}li$wrjz6RW?c&}L zbffU7#0~(gj(^5zpN*-MyRO#L8y2T$4Vt2py*n>3tbBl!oJ}uWt=eYXx0F>jhCemS z?26l7r*_^2M#%it=LsQ;CQ~u{7b8u2?IJWpI>C}CE`p;wTLWsPoF7llMLB2ruw}G3MQy}CYsLG)TVdDH*l>r zbL$=oWe|)4S#leKksy^+IY?A_y4RKKmT-z_Yu@Aejc*l0^A?ORW$oVhM4L&6`gRU3 z!PO^KcCzGPb4q>|{PdjcgCX%ona1ohX+xMu@j}-l2^TTuAD?x(fJh3LcBg%X=gG%! z$H)El?^=gxBZiO_hl}Tlq6Au2+wSqk#i>iDk`v{3xsQj@#(x^;Y)g(6-x882rjM9s z7nE2W%bO#k`htiNY^e=+tcYRI18jN1r7`hvZL6@W^fo&oh#I}a=gH}f29Ut;r%uY; zB5iJVSUXk;G9tp_r1C}PtdAX*(;b*xyKuZy4-Z@|1~1|5P<6lLxDD&!u@cHi=wK-nYv*+G9VDe?|Pb2lw2_dJ;!=cr)gD zNiwNsVWyO@cM=9=ccFzYGdaKL*p=#Nr<`xNp>!A9t+59ZmCP;bFg4x87o2JZGiu2l=e9x9H<4+|aiYiuZbLDC!>P`OkPP z#x)an2ezVFun{n_Q(U?e7oGg|L1?4e5~XK<8S`>7G%|nH*#bVM$1?3kmok`Qu463gHnTGA#|%gEn8hIThIhYc&zA4Yk=9ewB~7k52;wO)RvCjL121R?$) z$;jcFwBIOXl*+aEYuS9MQnCi`jeV*kE)uqo?kZE<>zjn zO9%^X>z9mqnbl+%EKF6~@z@w7S^nkV6r!cHu&-h=x7s!hdACQ4yaJG}4DDFBV*79P zUwxsfQzx=RZ!R@~4s4kF{1$WuZ5`*&J;$JoO%FA|XS8 zg`uCmOuhidpL}muU(_%}jLEf;i((&jf$_tY^tvV{>o2MZtOQU)8KS;PT;` z!=lCNuj`8L)5Zud^byYCBbLGS$ka!}G(X7TBL zI=oww9xhC9!U%iOgBD`{z`o=E(xfa4R_V%$w#lQ^||a%`ppwav>=J@d&6z(-|gYqpO`5nWBB1 zDj4~v*tE?r`7ejP`}HM)^;D;zOZem9a6N+To7#iNZj|=$PZB$SAle}tFC!wU((U(H z=vnB=^TmBBaj^?saBVazT{-*pV9L3wn8QW~;%=0VP~JhR;BU0Kg3qHn+0xVtiMjq3 z)5l+8NH2@Uze~!Lk)(S1nKG$znfnSmy}gDO@JTk~rG1~&hwEbu4;T?R`bS-r(92NyYfu1C-$H{PpE(QI;=ueuLpSc zl9Qd0ZgrRnoH&_a;gCIo! zN`J5j@N;|lY67<3K&^AGPb$`{05|QzQMwfJC4Is15qlLRtvee855CsE*uCl)@JC(D z(r4%OIVE(%Uk;g?$yuE98QjK~;QN43*jHmPK-Rew%>QH01FW!kHYXbgd=^7aMJ~UIig|d zyzIxRkS?Z5_&l%XT3Yarlug?oIe$6m%QoeO-Kv9(rTjHj+5Fqe&r+=_>&7XURy#m| zYnR>Ou2!}d^|79s^~;ao73~e^)Ub>JZPEqsw31S z>(W6zb1QGmDCspUIb)GD!B-x4esFrS2FoD*i z7)ty-eDA0zYYj1nBf1=YEA^}nzgevN`?^PNRU}+AfW3V+7}WQsvV>DAA1fAui>lI_ zU^~trux;yK1ZVKDZ@C2>SY$ug@Yx*2QXmu)xF|9_IZD#O4e1+qTB~r&y&%Tz!f$Tj z_;iTRr5K{WVsP(nT4whqka7YnBIte&zQf6_OXn7|W}9HM*4mrpw)iCE42bYlMUW9B zsq~r+ytxyq_2Hr&hUe1Hl0{RdEFgctXTi}b`2tW3*do!P`l^*)Rh~Fd@6GiZ(!tr# zH~OhYFV_@u#SHf^+2nC4BnTw8>B&s6xqci<7yW=r`_hJH)jFrysR z<04gA4S@v2|B(ldaSn}Qemwb>-yQI3*%D2Tgdtu{l-AJ zzJy%u_j~zwVWaQ$JX>5)u7Ht~#WUa$wmkf4pi8ItGZ7mTT$LfkzFPIL0GWM|ZUeGfcpOA4PA4+5+%;>)z~xUwlgThU$Qw!vbXoJt?J8|Ak^obmyI_Nwz{fKnFjwoEgAs_HT{apJ$B&CTdL zO~+wxo~wwM(vjW(s7ve{Fl@V&{;Knl`5R`>2uCN2qB~hNAqZ!fbvnLxmnk-=yM2jR zo%|;2^p4b)_9lt$+%G*)3ur4F%uxx__acPtNaAS=6P)6Y6NVmuw}eVfPE}nYJOU9k z`S^EwJ*+k1cU`*(3otB{{ZmXva}oL&xxJElw>txG$=>^1!2H%kl1~tJl2IHtc7$P3 zspbfm(ld*QoyC0fidqX;Ldy5ch3FKYeLW>Ndi+8rg~Pm=a;&vfOYlH+ZL32VC1D=k zPiy)Q;n`{C0novn(=WilS9&*Vn!jgc^kG91pl7WeJ(FscF3FsWvsM9x56#7glIG?~ zcl*l$+;nOiKMp=In8LLeZka{<*68gzYwyf5%?iHMyszSjnPA|Zi*Q%0@>PS|k=1wm zG@B6C97gq@kVKUeWRi(Icq9^4tjxoJmbRPrCQB4me9;LoweIyPmaTJ*NJE^%53 z5J*Y9n<$E$+1j|Bjvt7KeYq8FLH3y?+og9)64hb<*(&Qc}>ON!}i;$r8dFQI3`7T2)} z(k1HZlS)n%$|Qkl^m-5l@|eV^T76TnFl?9T?KS~^-MDP!m&}49bEM*#aO50BGPy7qgmKdobfK-qcSU#K z{R7B`1O5^~Y^wf;KI97q?ZC6_ZsC@F38^t3kC8TfV zjlV5ccDbSlJLVdIcsgwGT{3LI6J{PRY8H!6XCHdt0Fh_Ff>v!zi?4evg;i=Re!JH1 z)o%;Q6oD{Br5W0*m`hTVlnyzA+Xoh=)^=QCIG@{9=`Q~YgIObbkY#?Y$X{&+nZ((_ zuve_ZLD`!W`H9S>J(4%pb?~e+7kT;V*_$he0x8ogfIXo3Q=|r@5N#`{6v#d>%)0I$ z_|We^^Y(NKu!oy_{Q15ud&!-AF3#2YN0*e>Mf-UD78Cx1$29OUzBl1<)rP1GCnrbp;xi*;^IcayZrN_ zjY)f%ub<5p!jCxb?1dD^T(>Q*KO8YB1YSE%?M)sB$5r>X1Dw7=NB@prjQY3{!qDxw`Qg@t#$Kpv`%i#Owr3(472baLv+RM&oCKQT!GuE2R|?QMpQCxf51MrnPij}u`& zEbFgoqLn;47YNp4m-s&~O!mgSGfY%d&lR4hvJekimQ0NEr!|W{iDa9Y!o+`PT4#UIQ09OjTGjS_R~{* zhXcJIJ*Zy+UfI#serN;%EhnCFG=X`HD)d;bUCy(q2@Za_Xrk$ee`x+7sybpX z3K%aOWPXA7$4Q0!|6lFF+TJmK0-UjkYppyVDIFd{Y-{NZ+zXL?TThcO={)k61^(ZX(79>EL@SUW_lsU++fD7*!cQyWU4Azl$kIs&Ek%Z@t zv+&0hRy!I4uiV0|Kb8(u8s_xn=jXJ-BgKZPyY9F9|vssBPP| z)TKH4boQd|1DF2BxAXU(h#rs2*)SK-FL;SkG?ebi_!F3=dr48p=5_PA@-GbsH%5KA zi!jrr269FT*2TPee2YvMLXnHngY8t;mmCbBAkFa4m3%7`d3i@XJb>6Ngq)iVzSX%T zo9EFiEWMk^unggCjU4#B)AgiC!)G;fdwB~nnD&}_I3H;@x88r*CB@{i;%zr-VzQgp zd0|FpZTW|#Md4u^h;!?s81A;YjYn$*=&BeK#MY$cgygTR*Cvki6s`yS1nJBfz?Ure z!&7T9h1>lB!eppec<8j0Jslyr{%#Pij3l|#*=-zX@AE}RS#P3@z;TkgMqC$4DfmW< z7efKb_sa)MRvUT^^{QOqgGtf)A!Gf6k(DprrQ#L}Xo+kZc$g%}cr%n}Ri(@%qZ3G?5?En6(4yzp ze<1ylPZyAXlu+z_Q1+dj_~#feceyQJF=Xs*>nv5KCQz}T<)LF))83fJJ{Q2JgWCZp%cJ0Lo$oc& zp1?_EJlCkA_j)l9klYA!s@rQdQ^T{E_N1&zVA z!UYh65MGfzqo`@A(KPetWt_l=lO z+omh}#&N%POIM&f4~Fe3Xbz{|`nFxja4d-FT99?if?OS(yS9Y;WOT?GbCotJs-?OX zpuA%KEP3%I)~h%3fUMZljcSGuLmSaOtw@Ep;zfTU6lrNgmoCc@o}1O0b3H%kxf8#> zXR_BRnK^)ZFsqqzJ|<+U=YMVr{fu4G@tm$}X{$-z%3gQV1Ah7P(V4ExjR;rnkp0wZ zi%MI$ulDt7-|ie%6?)2OvdtDd=C59Y1zSa>TCAp|4=;r&M?CpN1(1^XKZXDIRC^!8 zcpW3o|6?4*9@>k12bmF!8rtogmc&&uj-QyEn!dk!b?Vwv`!lFKmAScs0pkbR0d5)f zQ+rp$XB!FyVza_>Q8A50vw}_!)>FUbVqMqAdh0g3x}Y?*ru@?NOnK_Jj89)?hvjpk zx%JM3MFnT`&Bxtv;JkKbd_}Pg*2t9GB_1V>d$3xa= zC{qF~Q8yar42p!DgT(Cd4q)KL{_l*~z3%6&3CiggeVc0|q@rwZoTi4Vz1Myg^OXOK zAmyn%*T_3as>r;nhdVLwLtdOF9qmW4FwMV&?VcLC8e{%d6+UeM42%4K@{*53s2;ZX z0$awn?|G?>+OV|GU+j#l?8r4Xo7t06C=i)3M6GTunJnhp=E_m^v7lSwB0|rL+Q&)) zQcrX(dh&??YDO)phFa6d4iK2S>|j4YV5HT;Chu3F4``a*dsPYTGf8P?@#oA8(jha* z^=*096={Q+0ZoB#vuemM;34!`&MAOcM*tYgFEjN0G$kNBmkL=f{^js=*;4&w2`4;P z^I$^)OWsm}09k+r^T}O>?u*umy~n;YV3goK+;a7G6?`ibpFiaX%cw0>H>B{;rsvxx zMXe^Q^b;K3$%F^T6C#x@wJ>iYX?aC`g9QS&$Pn7L*1tdU!u?LIMmd|L^$26sQ~TUc z-&@z$&Ue!My?B=&!B~Id2|t(&wJrMphaVQp}AILS^5#Suiq{En8&Gj4^hF*@&5GmVQ^?=l2}Xe;tmFSwC}quIqfC z=j;4RhzTNNuB6d4sgU1NjFH^M{qbDNbXnmYTt+F)P_Tlzp6mQ*iP&yf9!2VA#u1b2 z3;?IjQq~N@-}wS-_%pq2LQfi z@k!O^57rJzgYY1QP2K+zh#2%~B$7KyKc^uZju9SpEA-#s>2!V}hL2>RvhpwxwRAo) zdk>}Tr|iSz9Jlsb{>Dw3{KQhZ6gfiq?}>3w?*n6Ro#f0_)=yZ{1~zv&$iJ-ehy4}B zU(o2(B2`KRT)|u)851V^q{h@oO=pMf4LYr6x7jT!}09*|E8<#Lgo=$f>b%`gRFNUXgmA0ZN3xAD-Ao&Nz->NJ z57i3g%Is8oqNm(MvRo|qfM-XKUhe|iNBX)D z53t7)yw|sC`_V~-5fWN*SIq#BmFmUqvm#b}=i(8;TYy$!pWN*0-A)<1eh(IH*s z)C>qc77aqE_EXxP4{(gp>+hTzNDgHO%U6(zP&LgWc|R9J`=raCvM;Rw=hglbrV0^i zEvb(A#%^PZuc;eBW!X7}O%lLU2HI=``4nDw!Q$+#KSErc22FSsVtwdZ z@;526Yv$BwRKR^%r09KnEx{E;tE{X>UjB#6C2|zNEzPD;~bsIK#mq8!eh0blU;cFud$~G0j&ooSs`SSNc8!MUSlnS`(^&DwO5x zZP>U0r(fJb@^nq$PUO`Ga=N$?}7|z6?%zL+tQ9 zH6b%48b~NjI%lJOglV)kfs4DVV6SL^NilZVCloTfl>ad*iVUD-sE5ECCd>cUlG{A?3S7-}RvG8j zIwkrI=yAellx;VT?MG!MSIf+Um-N_98igbPHL|9<_ph$>Xpf$m*ns(@*H>x}Pp83T zL!B5JTQ?KicTrsZJkajbLxUU~iG)rw<^zhF`f$b7B{z(XvVtOU#4~(pF87r51A>Yj zmNUQ-tc=|K1#RDe9Wi*Vnxt=A-8J^Pw$I9ezhpLmO-T3GV8(UTQME7Fj;SD5camdVgR<-~qBUbJF=l$o4 zNIKWd_?tJeV?Xeq7$DwN3~x0H!)Z~A#jn_2PxlG#rL^CG*Ml~pV3uDiI?4(U)K?1y zz3_r;+%7kaY3be14S&PY&ac07BH|WHK6e&EKy`eSK};fY#ZFd)O6+;H>0ILCpB`?`!~R zqORdnC@g=2qv%M8f(F?cbeVzc&?_gwy?Y7xc*&o~WqLuYaiu$qd%MP1>L)?DhWelz z$Wm^m(K)l>H7n~BlBmEUAwTAiP|$bek8d`1vpy3cV!T(88oxP^{!R1m`Vie{!WvmA z8(#6b535LA>1MxXqJ|tZl%{K)`T60WW|JMPs)nQ5ADy33R~hbeq_>%UTnc7EwJAaH zAn2?xD(Fk8ue7BmahHi_LEuAH?Xv#X(AYvSQM(J}vlSDGnEsey*l<<r$Ff)6n- zyvZ;gN1d{Cko9<E<;SPN7ei(XtmW3WZXbwQbOue<4Rse1irK1YeEE{xm-EE&udz;I8l< zmDE+V=XSz*@47K{T`x@HS1dLg=H*^}RQ2P$ag(s|7~O*b;8o8fC_A75wYyh`EsyB6 z1l8_Dy<;-F0Dj6B&*1=eCYaJxFpK#*SBA^3b#GDaIQ8z40%MoAXLS?0nViy zU-hu(-OlCOeFPt@`qd1a*lAv|%aSYdqj~L{V4j8`je@5SCC$8X)O;WK(fTl_PGv3q zfd0Ns3Awi8`&tX5y|D$Khs}*|;eXqQMjrTWN|tZb+ZFmFK-!dY#n?ME;+TR{gz}Ti zj2njIVO_X?_H$b&oQPZkki6~PdP8m|K|(AcR`+$T$3stvE}bIUQ--QZS5Xz)7F65$;Dw*i?)YV?ON#JbCghpaE@(F=~_VP6N2uy z&EB~J@c+x!)oj+uANWJimCjo)99r!J)zK59iCab^L~Bm;x%tO8fVKGC2n*RavFNzw zFHTcCYz#+_1wH#)wG}Pzum;%-@Gv*y9-AzRy7Z9x^QB!OKb1N!ub#`0i*e|Ev!)T+ zyg_a&5AQdItsF4UD1?{0pNNOSj!ik@3np!MKjGmF2BTvT{We{)0oR*0CGIb~9GaI> z4=R05TEV^G{evnAFu6Vv{EGLbEcD}`|0Wyi{joy!VWL3TPGgNx-*k6?orK`H1V+6v zR&1RvyO~Cot*c}P=zl@1P~{GZIsb|Ye!L&@PY;CL?TiUyggtY3xtmwtOFie0IpcC0 zZ$zUwHGK^iVBW#2ZVdFE`90wn#lWuE$%?5PYsR}%lK)}fzb~3x)kN=fquh0gFkoYx z5_ydtAMI;vTu;wYBHC2Kt#?jcHvYk@&{z{KD>!z`YqQ!uFTTImU2ZH$5kK{f+Kq`> z{)|Uq*wH3=rAG59pIaT|b!TEz*Y3O5GxDjbI=Gi#K#EX#&(<=>A$7_id!v9SX{D1} z@QC%z-*#>N;a0xf_RgY1Z-q&^9N}W#4cu6eQAW%6TYHMTYz^-1JNw4dPd?5-;xBf%Sd&jFVv1_Ob)T-d5XJnI|6m&&iAtmlu6%i}T6P zU@h%Zsh0bWT{KFce(x75S+o{ymS`mHS+1Kro)>pwQ2u+)EzeM_)KrMrIi(Z~Ul`FR zb0q@0;}%-$`@8j<{2o8@-l*&!~ zisGI$uVv_4wjpYl2ftwd*^1VZ)2oV$VI*Hc0*Vq^XPliTw0{ z2u7&*EdF1sJFn~Yi?_WMe zP}6>?2q)dQIKIvS;~T3hfpv|C2pWuu1oq*r+zBHW@QnyDmp?aGKg?iI;(6Mo0g_qb zoyS}KYUDGlcRK8-fm=;Z`k9jfn-_YpI2Z}X9g|hcR)BL7r)$OeU~A-; z7c&p~(vqj;#;SF4V;~8FQ>ZH=$A-@wa+>ws5nrOZCcPeAW|Kl*CA|td_deu)_#Npp zD(_^p7iZw4CTb~-bnF{A2a)+JK|>WCHB`c~P8A;JT=Wk1Lb(z!hiv-uUHi}UB^2x> zK&MMBHm-vx#EZvrB!mrq$zu+1ce2+>`$+yVolb>!t8v^a%#Lfl0Fz22;dFJyi|>nv zX9TxW#+$5(jskO^B%tbNneaLz?5-k)3b|`gpXr#PU^LWui%_i)E!oZCtk>Jo4>S6IGt{1KuWdV93+>Q38&&h zdG@&x@FFk4$s$)?v;UdL3PFH^Q^ua6II5(AFI5IfOmv; z3dZd3eLrNlGd-Ll=*r8VUn1F59(Y$iaEkKz8SUePik`k$bT=1x7iAuNDZURHDQtsC zJ@B!Mx{X6NO+!@%e=~_jgD@_o(}MC&OMX)z1yAfYTIbF8$?;#p<0BNW`}u2Ga1Kql#%>F`m6=LTFrHHiwr zV(BWpN)Q4cbCTZJHySL2iXi{M=loAk&P5Qzp^cPweBbV1HJWbnHQ^lxO+)n0JVd^E zJb3hXY_Cf2))2o9tueXUu0O;t92hemRG1_c?%x1|WtHZmkQf1{HVNtFF{$54VcbNa ztmdIdNv_UpcMGeI>&%3d^&_#Wx8>$9d_BjjY)LrQM;!aUT<%P~@~f7uP`h@gEFfRq zBk7nHwkakn=^pM-`y$Opd581q|Xf{zOCfA!>>)v64z`%`s!oOYK1hzbdt5zPo+YAF$y&WtUI<#ix6aOO$`t_6f!$n?~xI_BD%|_n|}A zX+_@R4K;MUwF7?+OyGmTLpyht7XIVaJG?-%v%oC}#;r(+uJcz!wuJM(L(dlFir$!t zzWaI@e$}weSw#L{GVba6f_+SOA$S*Q79wf=2yf@R*bQ`}1{0iqN#!OUwTo8VcBLdI z1rkISJK~1zPG|YKsXb@4q+%r+abU7i7^2doPGObz6ZBb`xiSf^?-N7#U zQFp^;acYWC`~r{UN9A_GIAEoq+i92S_eg)G3r@XWU8q2{jIO@J`JTC1xic5K7{AMt z98OaJnsWI2RD{EQmg%t&r`PaeZ)3aDoQT-svhAlQCG}(@bfH1xHhBNxD1ZDj4?I{n zY%RE;#w)CByFrn+w+K6CWZnaOH*@6$*119cL3-s5Z+9>7=TAd^?>}pTH3hc=!_@o# zRkvjMf@b2SCxwlYKV_`&;Bxy|q32dr7%_mhPdiI&XZ!DRYtWNgoO@#G;N>WS>qS@Q zXBT;|3+$}CgqGQ5Lvg$MZdN_8SZHARu3q+@t5C4Gkg^^ zg|9H}{qj+RCkj8=HI{A8fg$miamZPL@(vR{r+R$A$rDrnl0*2XU2!si=xQ&KSrIBX zw+Fcmtkb66XBsI393NN;NOuRPNkAcp<_(pr@SqDr!ie<+9%ulTH0`t1NemV0tp>9( z+p|PR?&z-fJsV)Q+g4t^zJV_lT(DHwHNzj{5Y7jYE4vnf%k6-J9_5%P0?JT!I+}e} z7L?yELewm*UIOyJo`l`v+g&|^J|zAswPMmEyUp3uBfCeSfoIzXRgo;X)qJ8**4odd zSQ0E31Tb{v{9^~V%D;7gc!Q?X9#Z_+Xhn z1Q>dgx#8hFd{f195Gsv?PILUKND)C?bOUq%)lx;!)og=({3B#gp`2G+CUDS!#P|O&|$`5*tu9 ztv6OSi3p}E|Mg_qD4)3eE<$WJIHzdQi9qbUS{0#5tRO@zZkBe52B{KGSDcQG`|Ek5 zM5lRgNF#z?nXRiMlM<#B2N^@cdKK?eH|(Sgo8hBd;Pi{2YWEv9>>`f}g>LAx%A1ub zRDdGK9MaZ@vNHdSyg@T8GQ`sLk0?&eIB@AEy4}&{v&iX>1*ld!G;+z z&S{3n<~lTcb=xC%ghTCZeu0ALjA$44+l%>hU`M;gBq4J{p!!y0s}$kQ*K0<5$CFQV z>k3MK;6D^To2brQby+|}<@lK_p(2^_eWY09*QB1sM(1k>^9L3+A({J;h6NZw!$air z=@Xdj>sj?veX60#cg%YfP<92wgtx&dIbf`IupwFAGsRpz^fWX?)ZhmF;{=$}9G;Eb z9F+5y5`>bqC671CJ*oMqzep;M(`i%5KY|cmHjE1kiZv;!%Gy0~@X6Y$&Oz0|ssmm-8v0PLuYIZM`3TX%&bm9!L-x2wdUPNjIv#j3H*-DPurToD z1G5|VJHtHo87XK7OpI8SUy_T^G{U9!z75JPKg;|i`&>ZVJ=by|luno|73@vEUlXg( zn9i-S+BcEo)`ZSD;9yy1qBp69Og3|6T$JDNu;pp8pUzT}##Q2qR}WI!Pu;Iacy-_G z8-)lk2*Z^&*=9!Gx|@k0)pKW?BrH8<+oMZgJ_f~wruZA8p0}xuEC*0U+(&irWmJ>; zx~!hlQi_?~wpR^|$50KdnveYN-&(ax`i^qQO+B1Opru?2n61`*CwySKD5annaguj{ zPiRwcjodEL#7-_l2JUgCHD?-VAM6?>UW9kh7MSd%GIqOQFOKPAHR_Fi+AUMv#t?TU z{sa3b;p){(Gn-&7e2Df{9VCk)_k-3|Pi|`{=21oB?wF_n9W0 zdbUn0kRy^^zvoUD)%o3dxvS@&SIhhKEixbHzdcmvObvC1Jwm3iT2oXR9 z71?QH;A}6)MgFd2It&W-b~0m}zXhGbFt3N?$tY&>7aC<17hWpKvsqPqZNc6i=962K zp3H|6j_KFl1~w-DgR}dp<(T=2ojlIXnTg+J8 z`k?#SEiM20w<^TPM^Xmzac4F@Jv`umSjeX4vK2g#9>WNV!gUJJ9mAX^k}rQ5cIv9cmv_sb4|N?=Ac#Y>f)j__>Y2|IB6Y3@~;?3b7M}D@sMoKtz|%gy4Zpl?60T( z5i%ZQr-p(PA%x8>cXN|h>PT}l6@4UWu3)x&oQcCioe981v{RVP3@e@-2%8Jw%H}R) zjDL47ynRMUj!KKLp&s{8fcoas$SFt6*1+a_@4?SgTBf*KB%`*&%~7xy#vJZ8&z>FM zw0vG@Ykunp{C001$IuEV90qpofgHD_^Rvd+cy+)?i@?iWR#h%LjY|9p?F;-^f|(fFg% z*)z!@liqhLpfhIM+k*L}(4YaxtXZP2CG>#1+7@Q-!IC5Db#3P}MM`x!1!B|}Op&>l zBQE3s=Z^QLF;T|fjM7gl7>3~6ml{rUYt>3Jgi zXt(gW?%5mxig3?hzF_MCgP5QoI9b1Gp!WFD7;lLUL+8ml4S9b%-rO2udU)zRc<(0m?I| z*NP2dg)*F0uc~J3DA#>wm_z8l4-bWIp{sKJJo22Wr-s|8NWx%xs)q6hfSR z!_No(eCl<9VbXT%X}U9n@e?}PPDg%z$H)|8aKQ4`>0ogaOQ(4(J@Cv!R*f!Q;|*5Q zcqr#!RQ^uC!^YcRG>yg=$97sm&2yj_*zHx5KRur&R)<$k%);Pm9x-)-c<>g=R9$~<(N z5B;bX@R$sED1cyjtFbcJ1*ccBF)1BH(3-1Lz@X8Sa!CTM+PU%h3BKeAm^)O(Wk8ob zz+$Xm?FU^%0{5==YFQR5@Kc+Y06lA{>4H78%$qn~ zo=<0q_XR5a{BJ(d7kn_0v9{9PR2Sy$+8b~i+%7UO- zofj_4#@rnYxPU23xu5#!^HNFi`Pf>@|K9VDbJpSx($fcSmMn}p!xiUpV^=M)nc(0{ zi_4xVhA!C57h#U%G?yAIY$Uzg0i+ zj&9z(&ZxezpM`P`qV|Dfw6KjL2lO=f*U-d3$5nH7cmuWYHmOrcslFIaLbjqqM#pax z=pZj9A?_mU$gO7iNvDj1z!bY2h6T<&!KO~H%j0!w(foa-JJkiR^#^#mvSzpnT%WC8 zgeM(|v1z1vi}G~3`&CY(3R-}nRDB+N4zE4ogy~XVH9AS;;km2Q%_Zo74PX%R<6a%_ z?jIcs{!lRIEK)Y8%CQoFmh4U0C$$i5TOR=P0cU&g)(U0?XzAqC%j%};vi_NWgtq*K zDlJY_(548{sWm%dQuM(yH(uN)6ya=vF<-mm$qG=hWp<{dL$VdWsh*y7qb$PIMwH$T z#L~I8$WK>W#Tb$Xh0SAXVWOMMYYyvsN=So)-NHwIn4iKX8(0xfD=B6SzSSLkCV76} zeznfU7UW@-FA_*+FzVU@!?7o2z6fELf_-df({W5+{NDdAe&S)3gcaowA_ZM-woD)D zC1!wN?|!DVj&)-6jbcw9t=PfO-7@8$B0QVTV64H5DnARpI|}wd0MpXl<4~+=J!V|j z-XrbIt^SJc9dcMGaUqnXJ1KLvm~I~tm*RBIZdfTE(GOq&)-RB7jbmo>glBf{Er#`q;~Dk7*&>U*;p6 zKa~8e``Hqx$M{^|zL$E%bZ>?6lhS0Td%;-}gU*e)>uY{Da*~F^KUQ1$WxJqS(A67Z z00Eu~YrymdD!vS-LG`&F?Kb-4K}NNCAM5cHfm{~OiG_2JlW+Z8VZYp!%>_RJuxd5V zU%nXoc)i-Nhtzbysr=WGjMoIcH6*x_-u=CjtX&)CX~WkGYnd>!yC<8E6zG8^=+Mvr zKA8eq5v#hqL4<}~-fD?oB4b~@D3NtEs#)~+jBN-hPy%r!Yt`CoR)z1}&{u|@Z^&iu zS#KDLKy1J*@SzU|z+K878P!~I%H_b6@g1HeY@umiRY4SiNld${OwlKM%$AXYUlU^Z zIs2x+Se0*hE|vt51{tHn<`tD0TuM8PcxgzvVmN#Srb#{iQviOHTIOaVpolE5FBC@` z?pd#dY=P{WM2jSS=x$>KoaCGyJODy*MW`k62As5Ei>x%@qCa_*pCUhdpPJhTQxNoJid(JMiC20whxWU!yuBxr-ivpRL)8cC?>$rjIUc^4s2f^5``w6)H z({};M-(%4R4^Pi1rHWS?D$@XCsrus&z%V+~^>x0<>&su4$bH{Q{WyyAKmEPtkiXDA z@DmWdS3@2>sF=1Bc9Woc0()Ma_@8-$Sni^L>IkpI_-=P-GIk&L=8g^;7U0)0W~cu4 z?p3c>fI)#`@15rCGQla1pG~g@D;KW&3a7w!3@6@us^?gcliLdSWMN12=2uuRWY9tz?5H$5xzwg?;eNAe3xR7Sbv_u2iEWxdi3nZR| zJOy|#AVIJl3ij91^>Jhs&=g)7CWEt;=nsTtJ)rUZrHlA;sFq3xI#yNn9hQR(2OE{B zu#KHlc;E0J2gst574UoBiZ+he=u&wb+>XV_uKo7}vGV8h9fMAd@eDHhdk{-fK zpnMj(QvhM=ORPNL$S0O%h`%xKzvsXyOSaDH?!zsTty5bu9&_*Y)kNh< zFo&`r@w zdtKOV)bj?S7J$i4=rrv-`JiKX=Pbfu(<8c8d#87w-3!U|lLU4}!iH-9r;H3j!Ye1u z2Dxe+zkoJ!>V&~zs6I1p<>8s;tVNi^-}j{cjQj|r7XQ8WI2iGrDbRVk6Ppx1ocmlL zXMdgK^qNn+sCb`qtvD-!<+oONx)jjCEYV*c7~c^LXk@imwe+Ia!khk{+v8?uuXO+?6tLj+<5hN^Hn?Vj<9IlZF}$wU_;AC0(C9$pmoG zO9*NEH)_*B9@Z2O(dK8LCPo}I2Dioe(H}1Kpef+B9I!ia@4UoGZ~=yA>Uxt4=8Ax^ zr^RK7<2QZVi&OUO%DvPoP&~oUDNHv6os8ACL0WJx(BA>bZl>NuW7c%V=~Ds)7O;;| z1sh1r4KKAOREx2{{})A92wtGGZJB`a;pI|ZKoj{p+dS9@Ybrmg{1H0ho)mqy{wWS#xeg-<8)6FrXJI24@K`dUO1DzFfow4RT>R1?uyx3cX!G zlZTNnX)3x(a2$g%Q6AKUkG!)ZU_XAT@2_Myb}x`Bu?WR5>=f@6?}M4*%En-F!BHa^!=wu#0ay^!@%7&RDa>M3Wy_go_M~4% z`Bx1c-{am@ySZE$Le4r8SE3h4YO`ba9!bp^-+lRC_egPc6r7LELp|!RUW=nGXZ(aR z+-egD($YpM^DklscltYOx_&24Jvxat%alx9zKih4dv*KehKCelSP~nK6vyn$eHa{| zi8X(J``fk3b=nsJv*-6+f{78Br|!7H7Uf=?yv1%{U2@PQT_9B_3r@6TB+PWzUe-=A zbZntM9t0 zhetUPU5zXG;;lGrYs=`{Tx(CcOaJlnVSxv$wuuNU{Rfp>!jm0(r%6_~W>cWlJ*uzJ zjOKL@gQ=pkB0FyTkgB5#UH~HS?sza2SU4bS3?lp&MBzF(=MxNq#l_lTW<;5dBr#TAnxyL{0hLz z_d@Oc`mb8?yJ~YL+hil^bfz z@@&`m1N37wBx5JZ<&Gs_lyJ zMFqM0Z+^+Ed}}=kiT^c7jOlXU&n$VjC0o0fVvZ%g(fa|X88w(R-V>iQt!f&u?K@nD<=X-*WIdd?LzopS8iKqg`jAd$}QkFCM!#ef9M_%!_cxGn7|k z-yk1V5);?BjQ0VNnXBDf4T?x*!s~o*A)y1iF3w|o)gQ(d&QPRR&axBcKd)_tV_W*I zkM{l%s>~AJC&myQts0b$Rcy8L{|dkCdna=&Uq=?F2`^ld6MvdN*A@>>%_=hxNyInc zWJMff2fID(kaE`=b^q!&9~c)e5pjDa=p;&7Bx#giMDT$~MHzT%*+VH4%`R! zrc>8nJze@ZXfie7RmR)N#7q}#?~#9X=(I`p(Z(-kj=@`~(h}u`g6**uezKx2VScjo zr|St9zHAket{9|tv%`I9cQ&Y0Dk~(lvg?v<^un&*w}-rxt$9 zcnWGJ*}vaR){oKpZS$lS48QRv`o2pzLYk?Rm{+^AEla z)-oVY$~xb?+B;Q0TmHRW^MMD^n?Qw>S!)fQlXc-=?pm3!PJ_AJmwMeV<-77glUE_H z-7fRwE6(DSL*Vm5-(E8u2}l(cE!NLH_JxVXBNP}%h`G9iL>}BT>LKfz1y|!gsl69P z=s_z{bB%dcHt)}+mY7vd;&QNhs|sndcNCW?#f}Y(>NhNLl111)wT%;6acjuL`r12* z0*S$`dwRHhRaCEg_LIw@99XU)G`=N@5-_)$H)P#Ee&gdpbpGZ$b@O#ArCF<#ccqz! z&0;QOpET-NFj%<=$n_~11<>{vPGf4zX>%89A7hfLkT)W0&Br#82{}6kPeeX-@X$v5 z5jr)NV14xCai+U2*Ouq@jVJZ~yXg!Yb0PZo>Y*tsh1c_@21jp)T;hawoln|+zF~{N zxbpMbhSN&K^;?NKdfB;OUq0B@v*4rK70|Xjt@o#{ib0Tsci;Yw+ALh!k%t$eeou_H zonxQTZzoKud=%)^`v&W3Nchfe&a`+#d>(X~yGMCs5gr75q&r zx+t`3MQhiCxae`MirU`5`+6P+9$G&iu~>FBkzWvN^GPsM(LC-+Sg#4~KtVNJXr#2b5rZOSHUoz~1r_9pJU7y4LZ|$Yjj9uv_;Yo`0c<3XeFS zvMaJD2%6zM)FwfWJmi7~=;IpaGY;l8M=~9hlxj^zQXP%X%(=ywK2eDYfAV#DOz7rE z#E-^9w+?CN$N4S`zrwP$!%9}RZvK<0snex!=5CcX&j{5T$yX`$m@IS{-@M>2i!#>5 zWWV)z9b~4o`vdgZHjblLSWV;$$5GWa7yJ6O@x#kz;UV9Z+V1C#Wx<(;JNC>QKC^RZ ziM@8Kx56y<_@awQjm4_%LT#lGj-SW#o3&CmTy@hkL}5-RD5Y;JRz4~>v(K|s{=SD3 zq6fmT`{1&5e0XgQaePV?wIAGclsn-^VQG3EXXgNxFG#`QOV@?fB_LuVm=7bw#GY3# z-P_32)$FOC>A4^ry$nr`yD$Tk#)JYcJTmtZv-^4LrI=!Ngyo}Km~!{1lm9+*d5Qg- zp}yP9lz3w--gSl$$r9U#m}YrkrJjwU2PEN;_QqRNZo=BT(n8?mEaNb z-CvVkA`0H^p-qd0TKKSa2+RLVTG`BiJ#CVb1@zbAUn|`=2jhE5$VAxyjnDfAW|Ac= zL&ig>e}o7D&Z`&%oe9iDj*8(1q5ppmWH%?t=~8gE!@HRT9eB@ODX=U3SUwP+2v*gA zh!5H?O}n!mZy=-FuCmYL2{R3pqs*~b5rA#@FbvC&qkB4=m+G^a0EM?1xr?mDlNU#^apDW+_GGyMs*9y>ZVZA>WCM9$=E1@X&~ z{`9TZm_2`ldUR_Vx3K)T0=-Dc+zx~k+kg>g1dnXFyecKLR9mi=kg?70lqvdhr_t)u z#d~F`;d>O+9!<)jc!zt!5o1V<&x5uLi7Cr`@qiWUBau%n8TyHs{h`inn30EMEi$c! zMpG1T4?eWLf35qG(2gZ^wF>M*?R#FT&K%iL3GT5p2ozUO4HByhDbZ%MTCf|T$%DR_ zrF8IBu3J42jWHZ;tsf2SF;z`TSve{tClYdX_P?7+^;`?VFch7f*ijv0!iF-mt(m*B zW($K7ohLS*t<8_So6m>4nCF<|RPTJzlGbdN^E@uxiTKolDCT-1NcnpF(vlH%^x$@E zijnNh75uYqPRjSamx0kC3h3v^{N+;-+VW+!E%u)B?-q#(eNT zHtus;v?!Kq>YiGc)Vd(<IXM`1&F_qogSn8M#uvxZ|Z(#p|90?K8?ZOO{XN zy@D^-+PB?}2ii)r{rr|c5A0|YpP+jHhzWvDq-s<|4$sdHehy9~W+n2J z=3*!ZWb;fsV*GL}ACzXC`)V_9AS|skj0It_S2CIPjFEYLstDr-JjP+7RiDx5jz)^L zl^WzP5s6Hn&~5*1!q#8?5)L)^NPav+VOY_V{|L#p$@n3Ut{Kb3?t3~Ho_L?Be=C39 z4kDX&SXpIAr6&7AnlFn{F@z^T|uG}+NJ{e-Z=0`!-gYBrqTx+Nx0r~46 zYqt2DwG^8)>z!WCUj1Ch*65V7()=*=ezb5j%ev!h{bM7fLgq7tybq$O#P|H-lOi+F zB)tB2uxpzC+`2-tT&~}8l?bM;iSZG|e}sxVe#Rc*w*FI;*0(+h4j|h(l4w@!igfrg zZ5;Y^Tk!6mPV-@}pbSWAfb&?UX<#g=jkaP@=^M#;3KoLO;H9jk&(^bsfb=u%0*6Lt zTJ??j#Um4g#s!<_s&BaL7^1DRTtI~Bea7ors75cP`iSKNR9PU;#3xQ+N6s|NBR9J4 z9#8h&vH7GXmiSdXs}c!-r!}B_4ob~p6xia7k1{)#ihTkT;?h4MLt(0g<{5Drfbz^zf`RUcc3~tzxqKSY1?7aytN~fD$6I6$|bI$a$03S5g0Iy$A5&x(R?BjWn_%o zmpd+6Sq9wM2byf#S0_sSR}}bYW4Qov7k*+Vao?ccP^HAe0~N_15!)|9Ts;ZZKB^aB zh1V~%8s@)K*ck|igB)utCHnIa=rVJ0t#`VLDQPi=xv3WhnaL;nn#^0BSkX(9{ZSO} z7?EQfV>f1P?(I;!4sV129RGVsWn#4Rc$f9o7qUV#feSBi3 zVcD^N|NkvCVEl=Sho*#I(P7s(5$ z!C&EsbQCad(Vr6cFZMzXHkiS)rs^}jyU!hKrlN|Y#FC*iE$)X~+gb$eb>m?{`HmUh zRGe{h*B+kfLz8XpBx$27h6RP+y3%gctJH9e>HWt3Uzm_&9qIwU6KR645G8&<>tma^ z=bN>?5P3i@MX2!1nI}*pk?KFi9ebbGD5O7FJ{P_sRa*l+--ThjaBm7mr;l6q6|l{X z^l)n2NvGsDs`vjR*{2xOG}9^7{)}+PSMhSDTV_94ohVW|7-H_Cj>nmGgiE%$=6bN6 z(Yj^pcE#xd51gfkA`i^?o=is~sZva~iPZ!~Wgz*8Dt5W=ZqFn3)eD0rn-vAS!5SSe zla-=djuCr?I5%3GoqXx)n02z5i>d<5t2{?^XNzf08*9^c6BIwnm@TcpUAjCxCog zQ*}FWE9aKleDVTOXlIi0lgK|pN;x#8rVZ&!@cv2e)I;EV8HGkX0v_%za_JJs((!O> z9!dXSv)KMVOx9viwm!eBh}8R-1;j_Wm?*)?Qnkds+hjaF_Ir_oD2wnFlx%22K6XPOb&`1NqD;2jlqpLGCE{Cm|EO)Om#NUKZaldDxX0;Y0*FJDn!qC z!}ex_P^@wUVEG5k(^< zi3zaaToS(`U1lgPW!f@T*f6;z>96_ zfT#0Y-W!KUdPjS&cC#G{VTWt?Y}il2n@XbMv*^ezd)Hl6{?!}$1AJnPxhDr3M_ILk zd8O6?^d10g@rmj_H z0Wc&-LiV8XZBo6pgX}9UDoj9CeIXlCjme^Gu*&4#PtRw1!MX)cZ#GJL%i=VG>2_=z zmLCClyDw=aKe5hwx?vw0TS4jEuw(7-x3sq^&_+-)z^gc|=+oZ{CtEb}M_4X`-=*j~ z+0Q((=&|Td{_@w;XG}lbteAFDv(yWxiDDet6%waR2N@t6Y^BLPpG?Ymv>da$537;8 zRZ%?jTMR&^JpOg977-dla&h z8d6#11HnsY|ArJqxl3G%)`)shYTHk5(naxpe2Etc#95pb+ClEOQy>!xd4&{X1{Dz> zB(kA+;3D=6Ob(CtB3XN6An1Q*C3ZCmhfUH5Mq!c+MR*_UhtLKVJInJ>CpzTzxuUX@ zHQyP&Lhc<#Wj#U*O&a^*l=?Q}h^dajF!FV`K11yXcz@Hope+7(uh6S{Zy0$)`H#?> z5tpR}aA{YIcJ?w`N@feE5LSH~xivPcE-;}YiaE@1MmsJW2$IXL?@ zq-9L>szk#%Ir}$S>tG_7Q{>x`c3We>wAVSKMq%D}s}ws<;<-33!AHAnh0ky@ka+8T zdQ=!Ei(?zq6?A-9B}h0ETrIJ6%o>D)#|LXuPACh^03?)EEVS~#s8Lt_($Ot(gd13T z57C_Ot~oWkksLXr6A=9TqBl$scI38(2#q?Ra%5!XkoF#FT#$gy)jg7QFE}%Q&8b0l zv7|@ZJ)(iS2;S3)YxPyiuN%lys^~4*Wv}DGDlMtfr=YxERwtOZy3Am_SC_sStGHs5X&Mt(4Ex zqYYPObi1cXz>e_3RqesS%e4?a;;mZ^SQomD4Aom8SxiKD3uM%8W8wiI64D89wg%T@ z3DYG(hOleAep0zUcu9|jc9epY0e9(Ly5TF}XkIZIs7_~v=OD;rV+XIdyYyhU#IjxJ zc1D9_Cd)6j)9IW5^1)`ELe~`vfnZGF{Cp!f!Ps*!N{bIWwo62C(Cr9IPZI=`YaF*q z+zJ}IUx)rV;vQdV?k8Z%!rk$AY>FImLpg|M4EsYl_n*L zs1Q)#u>lHV1f)hmq&HDogaAe49v6n#J39;{#eH1+u11v$bZ8o3`00yt(kDNIQX03W zZ2HZ7`K}k+(A$-mnca>>1dY10w?JpO0V;S)nyo)77LMb7Ud%60bd1%&4fTJuja*G_ zf|LvuJ5&D*d=R7F@Zyi)4Ye^H{DAAo@2i^(Z@s=cU94ZjoaCcZ``p=EIj?f#ho3p{H`o?%jo}4@NA~O>z76{>J&Q{!o%@r&cRs zb36G&J(8)V9$#;e_RzmeIRP|Qv2Bb4!1ezyI$nG^DD%?5MR~=t)D9~{won- z%T$*=p-6+@A@#HszXS#g0F3%Wl5+ui5N&Hf^auY`Y856b9uh3$7Ix?Mx;*(rv&K&) z=+ee1zRKnIo?F*Ow1?aV2GxLZQ-XuG80pE?y0-@dm0K$Z&TBrTrJpNRc3Htr)}piPV>Slcq{aN7%E0d z+S@S3Ll)EFkc+$p6oW%a17aIFUYf2q%9%K(KMxwa8`*8#4F7X&vZLuP4TeSVHeuYGT5;GmR zL6JT?PZ1QXZ#f06TDtj*^6Ry1I5!*f0IuQR|L#32;A-8_2aL?QE9tM(b9rI|_7hhn~;3ORJ8b4a{-2v*CnjBh^> z=Im=c$gD`PXMEU!Tyzxt^|4_XDWZ;gMY)DGIV6#fwU0qxR1V=CCMhNAGWu?3vpRE7 z8I;tdOZ_Fm$t4%#tcqXh4dZLOQj=Sv!DKZ;dyt;rAN;i^zoH)@hWXb~*#lW0wX1%T zxG~?QO23lOJyAn7P>`Sh{!@t8UgN?+!Sb_rCpR4>5|`Agp3MAEPdTSllACIsgh2w7 zw4a zKLsL~3XRbExwITEV?cZWUo ztU2ij18==M%(FLyJx-L^JKellIo5M_|j|N zvIl$L4@Te9(|n^kt@}#zhyIWDItpvJSsYk~KnvOZ0%-6d)mnTh6oa|Uef^m?yC=cb zid$bCyAnrbjVggHtjhN}Q{#I?*Bxs@uw8PmiH?C|65}s#yT#7CPptdREP36Lm!B4j z3~yWx{)o>$1?THLRVI1)K|LSIaKeANks)V5fz+^YLfo|BxWzUfS**1~e zXr|L$gUhabQXuJ(8to$v@eGeovu@m+$0K`KKbmuA$-XkY2J*%sY-QLdOu0p4$x;cv z9xmPyVeXrK*!P_QwR=A{8ar?9+gk1DDcjxND(hawTHBLH_PBeFwG;_?N6-Aw#zc3s zImUtAorNtcN7&Mo&aB*xR<)|hI4}JN42+Tfh9Gi1x+fwv)lX;-ezLy) zyz3TTlYRW6ouS_Fk^1L5HTEqCQOMloI~18_1}HnQdOCaJ1TG4*NInnyWPqf)?f!0_ zR@3w!TD&^ClT(_*{5nndlRGmL`nD)Gl4>#mp>;4nHsz2Op9E2g!^6hQ)@i$3TuP*U ze<~SlIh1Pp+!}0Md*fo+ZaG;pAT(+I;(%FUHm_l#`B20g{%>9CO@Yqu)B2CDE81wO zWWYC%rKSCn^q@#P4h}E@{TQ}WqA_Sq!EV&~oYk%=OnO^vd-n6!-a}ZHPR=T)^| zBz6RHll(NQ?FD+z9MrvK$tr|(2tKw3^Vvl zJzOnRe@n1E+i|kD!GD^%CzE!1xb?&v@+wloi-z?#WAV0Hd^QbTAm2TFq3x#J{?yxJ zM{~P55qFyIU+8evm)!SI3_jst`#hdwrW4PEED#!!jorhZ(LG|$2WkqiOvNZD+di~@ zO<0(H&uar<%#ShmKB`!0*o4eVez)Q9=c| z)2hOi=2!!MPfbYY`ppJgd0%^;zj_wa@WI0bkWfC`wUcLF5>v1{tXh~NTcp-?1|4dgh3$8@d<= z^r|+cy&)#;@+JrSC+-REr`RHTaWLmDqyG+0Y0B3nCiO&7oFzTX_I_IRVc zCpYV2S0=>$5}%=%;?mgo%w>7<0ijr~L7K?53%7_2IXt*e5AaCL&U=>&Oho0FT+OjF zfsm(O_@#igZCd@U!_k$p=`Gl6!wC$X?c%nu++Z)CnDT`?D;IdL54c+49_mcRY04o5 zx^ODw^aNe=k90MizO~Pk%Xp5lrD@3?OD^quGxS{h2_UuAWT%2o{22O-ZhCK6pRL=? zIa?L8%5D9vs{R18v?-ZZ>0;_0X&uj;Iou|mMfIwSed_4Atp^(#{lb3lK_LX9;cpJa zDTiL399@E|G9!e7<$`#3z8 z)~{DB4r`EpU{+>2T$E^05q9QSNvY~NdU}j{+IB_F)hCsuE~KcQWeR*S7mQjA!New_4R9lC`8V* z1=sh;5b!>484#4GNIqYexrX&P_)WI;%OnF9q%?h1`nF#m43Va!-g-EqYR{m?{cn;B zQ=S1!qh@seC+jNMH~3aJr&YTmovHCkzT>!t z6{wC)g<`#i5*WM;*;${qMYM_GhGHgV$CeIxh2O2;dk=gFUW>~ZCe`gkd(h1t=!YH^ zU{+|W3iQ5!C7tma9((igM`Ku%h40Gu++d&QHSoS+?8TQB5>#ei`qwhYVk=`0P3s2W zFuU;!P?p)Im~|N5akcpGj<4c=p`-O2Py2?SwzsFjFDSE^zEgd8@%f}HlMn*--$&Nh zSov@6VZ7D8%dLj;nQ&)pSEal#cJlV*1652n9f8@usX=C5eK|Ip_X@qR^p?s0qH zr-iP%fAxF1v*Py{i^T6G%*Ml;`0?6+!1u-RwAw#At!q}DAF^uzk^IW3Pgmhs_y>fR z_|T3Ghh%j@A$*Q=5$&(#DY;-=xQJ?^wScFlLV(|AKw7zKBB-x#e6(a)ryWx`w-i)=V^wa zJ?3sz2V_N^Q@}&wHH>O`KWaUS`vM4F3k6!!$Y-_Pm=FmLuQ@54hiD6^N zwS*ikf5;T+Dkt!c(^~x!q22`8;`zhpFu^ATwer08B>Iuh{59+oiXmci8``$@`4Y!9 zX6IDJ`E*P|exB*U*g#mqLX?WN<5W9Hvk|#QKln$wf=HCQ@LpzTtkyPGi zK4~>pa8hG4dwXp*r+bWT1TCwO&N-`CnXFV_%fNxul+9^@gJeB!7S2BsFuyi5>u_mM z4!`&9x+6no_(k*-Ms!b>gYNsM6(>n-)}atkzK+fG^rNJB2NUUz7$eK5Q?EECf#adW zpxbgM(EIKZRi_3iplewa;*>_6KwPj7dZ4&Tq~t2L zxa@#I^o66pS^$;gy{wg12%OqxO`3DUu2y$h--UidguXxAgAGmdK8wU8ZQ8I;qA3q94!X#8?fuJF zM7m15sLbA9X8T7>jzX(Ewr|Xw$D%;m&Ztfd0>d>HTX`IPw!P2MRRu3va)E$ie#~R- zy^1dO$>FS+(sCt1&E+r;68*UR*y5bB3;XEgQ^EJC{&Ks8Sz|lzdj)pm2lM1y9oF^Y zrK~!esw73hg?AwztLe@+R-AH5;w#udwxR!IxL^b_Nr5TG>fe>C!o(vsB}~0`==M<3 zeVYQr5daan7!zJ!Ko6bC88RW;sbOvmLFcfS%>uifCnJ&f-LOmsm!@RN1=z2%!EktaTL4G50- zggn0$FTSZcyE3aPe`3{s4q<{rOS87@um zZY7%y(G(@cSI#;`4;mi#n;f4sE+tCsW(KLT+J^#?#^q|Vw#jy5H&PP6Lg%eCooBQ8 zdO{hmGJ@&n^_VG6x(pz8r@5sgT!*~xc>UYJUAVl2ISeIcM)%{p_q-C%;-aBxZK`7} z62$5AQO9ZVq>kvk6Q`4Of!5;a*Ya^A_ntA4;f`#IR(c=nI9+_-5jb@27Mq~th~L-V8Q7wS4tl#g+aIKIq`Zn zNt`aGA<)~7^(iC%!C_}DkD-_<3e=LO$-=XIlIFua|>2~4~6Y*&WF@AFbiAJQ=$~G!8h#+CmTDsIZtjj4dJ>fk=uk| z3tj|n@QZit^jIL~ddbY^vn99LzAZREgW?IM^*M%UJw%D0pCwoX8IGCaVqV3A&z*&5 z7vu)^XlRfZ%F4Sh(2oGgX1+1c4_*TYCRbkI2NKOl)Sfg=X&9f^wQj)v2F#@32s#Zd z6YCan*D&_J#6Zf1a*|=_4nk4yjg7vD<1cy6bQZO=pU3I}qtj{Y>cRw4l8kXJwaDFT z8~1Q-@XatmTXjkmeJdAzwCHNA9GG!s<$O136kw~uJ*6+@R!1*!^i;OKj`wGaD@!|` zNh1Q~jFHsm3~hISO4+>};mV5W`8SHUYETlqAJ1i^x1C_ix;FbC`|7=x(zd^AMkQXk zO+(pOkYW!~>l>iZQUR?H-cgP2=xXOBj-x8OAmTv`iDSHj&ws$h*bJh2fsI-(NMeVa z!*ACRiD9ngjL8m6aM+ZgKf7EHmfz1m2}U+s4;oM&r6)=1oJ~J+w(E+Fej`<@iVvMKNZ++y!BH&COW)b!e%A3j zTNI|IX;6U`9AUBqrw-AE>v;~c&R>$*+0;v<1fQlMF-0T)WuAR=3yTpEPPy{JgGHY? zIcMuIib+Ajy<_DqtS|gZ0hH(tGV3e3vI)CESH8w4Amo5AiIcT!#f*?()nZ-gR_@hCO&Kx>A&zciuF zl};n(JU$3ITZ+^eV5ZllDL7RB-1l@MuBP+7watU(%Zd0}tC)i{c8`ok%-0z1(Gb{K z_?oHA+2qRdxJ)(*7V}J5b@PG>O_7ZCZi)fd$>%(X58i}z1Y?wHZ0YGgAv=+=BsE>x zEc!O`9RZUm>16zT^~Bv;smg*&r7gvGwD zH$2Y)U71*D`=FVUjMUmgqXfhF;7k4wAX1&|azdg5gY(^6eF0e{Uy`zk5OZWC!0`T| zjolxaR&iDwV;hs&0Oo)-1AZ>&Tl`Xv-A67EE>Ll`RoH#x4YMNaIq*8SPwN3JxW!}Y;KV6yT zY!1J($#{+|!pFFYua*}}g{B}UIEp(K z4Qc7DVs!=P%gVbRYM)&GusED(=6rF8GSH~sM@o$67sw$befs=dFZmoXQxNb2BB(jC z&KP|r+72JK-ARM2LAE=k#j~XmjwFNg?D2X3eZuhya$VN7e`!V%4!Z5ww^4udA*cp3 z*x9J6IB%unLTS=(klwr&d%CoQ338B?5uR>}QP2L;otR)B5AC^RHFvEmG+#tb>m9^9 z;HcsC?QC89#wUYvhVL9(i`;XF$)IdBe`W9#j<( zKMOd)ny0c)H(U`rU3}Ht%F+8oXG915b8Xg-NnS2Q$T!-NiUWE(V&V=m<=U00F;&6& zn`y4B$TpN`AA78f;M%!@w_$OYeU_|iX-f!dEH74!`UMjj_?^Cs)~DAB0QYcj-M$Wz ztkZZHc%8`;?S%_1iR_co+pQ-#+8FwQUkg})>4T`2=?imJ4l17bRLDIl3grkh>@ysG z;o75uY^CKTiH-ppQ4<_pGkAU8bINa_Qz`Q6?KiY5HHLAs$!B$yDn`HdsosN3<9^OH z>Z`2-@FJOKBdhXL49m*n&gIM_pt{92ILn!eJxFkQXg5A7KuM$FV6!B@4=)2Yz5NWm z9iyD93x+SwHL@L+cedp+Q6Wj9V)?Q>>b0V4mWK_y?FqC2&T`SOFxpkp$^nAjKc*9V zK{7SRQ0v`SFBaNi2S=tx23%!NLl^Qzn&<}R!KQWsvrO0c_j+Orh*jYx^aRxXp+<;=rm%Om$r6XehVIx6Y|ACcZQ&3++a=G6$?y z5B3cnXO-XE8qck-5PcP-_f&X9`IUB8|rnB3TgXL9)}dV&1w;f z2pR|QR7L77^F={_e9P*(({(rNB+GiDLbtl?%r4d|TdCa;1l51+js`NbVZo6@Nf3@o z6Y@Wo#C=nt*P6FFSQ2_GbRK9Z5`R90pw8hN1~QT@as@{a>K$)sr{IXaWA=DRlekak z9(L%*%9kV;nLZ{;sgiu^ZM}n~6^0*lUMbT_;yPy~*SeZ~srPxB?2XHCu9wdXHa)<^ zgd9Q_g9zlkd4}d+mC?xx!@%xKvyRmy{E6s;Kwx`NtU@EVvV5YpRm8gW=JG4dzY<m7qQKJom5u%o8!-4E{r}J~oED*R??F;R^dvy|su#KLZ@_6K#}%4C)nk z+U#}O9edYlr@8=9bDEqt@If%0Bv8xnr;++{np)Ly>}N)&tM&VUuIL*QQ6rm!5!AwG*@y8|?LDupJ>li3*VNwp z>F9^YkK(T7dTGG!5uSrc;h9k?WmdSFxiYR{;rNG#2E>dRZq)L>5M%>nB$74XnB zxu*^7!d{98{K-Xyz$eX-ohF|7908$PAckKExo2x_(rWp+^H3M2gj)!acQ%ar6!qvj zeO`;iqP_-DboVl^%s3Y5;Pt@T=wZA~FG4x>#iCQgBG1c%_rZOp5dS@pR(vC44fe_a zW=V;nQA55RiU19Ra-BI7N#S9nnJAjXu>fST$17A5{ScM)b$;nng(}db(Tig{0_`*Y8+9bFa?!(>C2`;WR7%c7!mkx>cV+0Y z8P{Uol*vtesxX0eL4TV^V%n)b9Z5~D%7DJI7v|?GNY(2{q53+RX3HlEF9q$*B%t=A z$1PEdLyEKflXNy(|>{zZa(xy21oUwq-0Qx5gwJChKlNe*&(M8 zozm~2UGTW3%IMycX5;@mf=f`@ApaNnDYMnK=`%}=uSjie8`IV2^wce%C~5ms$>y&i z_H3SH0af)5kvdMoTTh{@P8F)cNge;|q$Z|aOw*Mx!1nGOuP>J4C*h3bP}JpT9>&6I zP{PCTGf}WRxnp(+~k z9qAK^Aucf~$N)@eAETT#tkCXq(E+j8m<*RNK~liKrZa0e|Cx>*swF8GJ`B+uaAi!d zgvm4xmP8-Qy(8EE_nJE8NKY@2ItuKr-!`6GS_0nua$U^qM8=ZNqoWLY`Q#TNx$#*u zx&x=oKbtADDw7u&4l<%wVC7L^YuGGwD+yH_H8@mh`JC%O;9Tc_ddicrQp44|UL>gv zB!2sk1JJ{(g*bmzm2XN@Z&uu4$+vIZDJf-$c0l98=!q=Oz}d%~?bZX*I=&z^;j&Ym zYq=B?cxHU|yv=v3)`vH5t^HGp>)@w1bVi+L{8ch%@M$mhD+Rry zwN1Tc%Inia(#rFrUO{_(^)ocOa-Ju+6t?-4*cU!evI<@=2$$Ok9aL4k3soabv0E75 zE-W`3wZ!VZxn;h0utYz~Oh-Erw%Ha^oDxIQ#B)}FMNv_m1-szB zE6pqR!QkV)Z#(hdzLEuI3D+4j*MiRp9UE`|>&N?%uU0SR`OS^^)qxmEmRz4ATMX-w z!xR1X24CHocBQE(%z-_r;8f2V4mi@k`9LY~ujU>b2iS%&C zuRa7+?T7EZWnqAX+*BG;C1cS}4zT~%ISFhM>&$d+1lB_%vx|^}y_De!&lF(0D+UKi| zs!#k;Rz_)inDeyt_0@j2w2D7C%cj`J@e?PgNTD;U2k)v+)!B8FYkv3Wj$5IQ-e%vU zMu67h>T>yf;r@ByWsr2L3%}Z@3McQ5zPSghYCOXM^G|0RkiaH;t+~HdJ2KyG$H0!y zd1EJZ8`4iV{loiuM_eC)ad;$jPnLl0i!AFIzzMLvZGvdGvaEnN*^ z?TxnmxO+(?PIYE6>u=35d<7({c7K~z!ua%3z4jG+M zJLZHcht@4=_ZRN5wy@i#1ZZmd(fa#ZAR>G8FSMGpX^whYI!b)o@n zyArjg?QLbx3A=NlJ!IY2uH}8#X@GhK;uo_s#GW>bK1xJiC+{g=W40u%vde62DS@Tv zS=#6z4I^~MK=y=wqW5wpsV{>%JPc8zc>_`rk&Ukz1y3nBr3VSAo3<{Jmo}XXTiGa~ zLc=&1F09a#?IAUV1tk;h!BqQFPNTzI#Xyu_OvQv5Z;!i-bDNkIzqA0(p5mI4C!1C0 zvsuR3<{`~DR{J=?&-UomfX9y@b;(`ot>>zWsS|Lk&dEac)?Oq%g4rB6xNFhZ-5p}; zk7F$ifYr-=wzdfO&rc@Ch)$Ie&mtfvhVHW>$+)=}*1Z@IY0eQlP&onuWYWFO&LBgb zQLIQ=r@7<$a5k9lcsVDD3{2$tmJftkGy zJ#Y8=Qf!Ktj9kkSVT}(T8cvWgCe~f`VKZv?pSj{rB(R|1Xv&~M0{(0mfk{`4s?kFV zA50w$e=D+1?EFGWpXJmF2DG`%PQSHPLq7PxZBJwE-Q@KmIVb|O7H*SiLw{gLRui{g z-ewu6PnESPMmN5(bbCKSkk+|&@;LQ4MZx`iW#B7P>}b;@ymO^{U)9=Q7SdbN+BqdF zPNi^J^jgeLvzQZG{lYlFk*#J8m1?MNM(n{{E<`x^z#JEZYC`40n=fW%=jR8~8U}r` zbDQ?27)D^0?0pQ&A>w2a9Ty2~F$aBS*1q!+?gV<6ZQ@7{USP}OvL|^Sd0&P{y7M$w zPiu(9D|t5WDboe`DZ)o~4q@pxRGC>0}&7cYcCtZA%}Jl^@+yIznbYeGVc82}o@eMSxR2_1L(BP8KuP z#XK@EC}5@JX=$!I$P9mGj?+q~5={8dXY*3xHe-uk4*2=NTX(bW5}VkZSz0G^%GDI$ zWa>!ujK8QE*mJq^cbu-0v9at89P!ur?pB=fQ%9F|GiiOO8fs@b&lp#`fBE;OZz_{m zXVb>mWFn#b{!l*HVc99-z72ueq1{iLj@6gm_{uuEjcElb_a`l#-!z8n4dmr&mI+yS z{dtnQsr{^j{h?jE|3E!t93!LB!g{_(c4tof^7AG%)#_r)^x5BeXLlk`n5`o8M?Zx{ZwqO!UNP z6+G{jrrucFY*klIwN65(Hpf(xYUq{n&e(UK-_y9#yg5RC%SsT}to;!`hmH$y+08w_ z?uE&$(=zn>D0U>wvvk_k8Omm88y(*KTY?4KUYgIFENNwEpL$<$enfz%*s9(68VHp? z&=GsNbtte~))#FZdz-MTL2Rht$VRi2Lg?^1D?7Ta^_$i>wB6ZLNape%g_^`+d$1wz zGu~&M9u@hu(CY{lOIbA^)T3UGtd<_*<7+Jwj%!s4z|R|<^J%<@dW{UT4^~dgSX4Nd zW!A6m7#fst(DKR`$&NDCx`#z3KF~mNTwJi_W9l%}d1GJFC1IpNmJRW3tC?74Z=Y|z@*l;Po;@wI z^@AjF+z#C;T-1%ev%`=JVLzSUvo=X(vO>2sA-1$7kI^UVj253k)cfQYdxCW6_TVHp z2Fo01a<`As3vt75MJxeOx6gSc(YH7+M#}nUs}^7MWsa3NFT9%S%w-Z+yI?|-FtIGU z3HRxoj4}1EE{0xfd0hFwIhuSzdyxu@Ht^zP61wl0o#Bq20?7TReq+Tjbe$$Q9H25C zaDB2us|TJA%#flkJ?zmNBN!z)LMGTG9^eYXk?gnFR!y=j6>c<>}|fzau&F1O%-@a5V~a# zR-Y*fMAsz|BVyw(=*X&+<#q-&ZDkT*NS^!n#YWU6-N0PLPR3|1n ziCXk9Taj&649yUT`T`Sh?8cKSF_2vt$jF>S#pwwKd>mVTLSM)0e076ME?hj^(<%T8 zRZNpZn8%7m=SpzbCv#{_O{K1_?9VW>>Klu(QUv5lL^j-K1w#O3Vas3Ov?`XPKY|HN za1`-wAIYoEt(T!jzX=YNhY7Ad)@E+ouEvxm!5!Q zKU=W`zRR6;o|DDL+KIUFPpe-vA^OicFNg6i?}Zjn6Q2`Xb!IJd181hTfU!+{aqA&7 zduUFRs1KYlM5U3 zTf<-j_*kNH30E$ADN!DzBp^fYM$j3xK7$-POf{$Rj6QEK3snlr9UdCD$d%R47OsF; z=)Z+4oBoA1{cV7YuY_oHbw%!QOi=?FWjbyAc|B5B@0G4$qxmi)}XYfJ)+EQOSH! zzd}=D{q48e-(0avmUNKi67c(Yko4am^9!5PE>!M;cCl|cJmswxZIc~e#K?C1BV&O$ zztp%}Mkm|;{%+{Lp+^!?ARF0zlAhFxX^`8U{G|(dBeA7nbT2VP<)SkomgtsmT6?840r13(jCMfe9Mk z&c3Qt(3H({SPB}q$1aHIJ=7L|fGeaY95)sWWUuLY3MH(sC7RmCj{Lz)Z)M`9C%av$ zFxN8dwYRpHudpm70EnbeF=}o@$6OEC+Qqu9;L-DBtzV^;o$nTwBlKn=5YMibzSxuR z!vBt)fY_>F3w~D+s>T-C-SF$_1#{a*1{z7B4W_j~Rm^yzy~9(M4i*_uxPPsfx+Tmx zHfh)~M+XUxY;9|Xvc`_H^9asM?$#Ws!d!>$pDeeuXmQw-IkSqkn|a{-wT`3LiRor(ZKx(^hNn0@}~r?pFz&kBRfo82%%Sr(xdR zfMtr2bx3PE&o+9Y#x0)DD!=*gs3Zqy$&2Myl@U$j39|C<_k$mYcA--{*9&>>jau&( zj;b94=Fj7=N=4|8r@H=Xj9NK9FpEu#fw1$C*hP_gt)#EHwfKPX5pqiP2_#aIn);F- z65iWcRPed~Iai*qX3m+uxQ=#!DNb<;-9ZmUqM;R5=UnrR&g=YwyG=*vWH&Bee(hOM z3j{?*I>{_c57xF-M;4)id0c>s(R8EYi2{kTjpk~g=d70;GjP^t(l}F`8Zs$ES_sBV7{I-ge zde4JZ9yLFiCEthJ`?L(dc;z;?$x`r-Mypz`5gh(<5xwO_2jyKF1^gxsRdCWMEDJGc z``DTunD{#q(vC^-9&PE}xMOTlFNY12z8QlV=ll4@mJu=Rd=0HI2Y4u-D_}9AaL1_+(ql zS9D!WlFv|J&*DzEvns7-&?6mXDxl)76QImiwr=)(u9iB*Ed0EI-rE1X$HK30p2*1j z-8xguKyFhex0yK`@ss~J*>$1dU6^ad$|H%B=N%C-bFmkA%5Sk{UiZ~$bTqz?j7u(l)KGh^vRhNpe5I5POhLGn26~>rgzgrDoF#*es>x++RSp89ud)WMMSiG#j%#sfU)Y-S15lu zqkng_e0O_B5@z<*rKG9fmM(z$I;ObWmvPU9rc zCt^d(E3FoKm}^~vwpO#|`7j66&X|)B0dSkSMkjmKq>P?t)_sH}jKF(q^v30#63LnL zgvw8Ik7P1WvB-oxrrO23t}UFm6*{qeS31Ie=0`X{Beu*P4xlh&Z`1mi+M(Vrxw~$Q z0$9~g4CGZPZ^e0gi$1peNA5ZQjSK@hvpUoBmxpu)y)r2xQjz`idDj_4O{G`&e46uv zLJ@Mk4=}pLlmW12Xz<0hM2nphFE%H$Gy(;+M;2O47QAGMLPw(p4{dBu@B86kOpz>s z5XNG6i`pY%-zyfBwC5~gTX3~PSWpRS&X;UJda`7=$L|844@(oX{C=WZKpCqsJS4E$ z1`*<{1=?9*JzU!?12oX$@441lSyMBRsDfKq6wP+$K(vfS7%niPf%9 z=XZvLeqsg6JLhO(`*z2^F9+%Z!<(-Oh45}BwHCLO5od3P`MmAKwHJF#6hL;Pb18x) zcg5|!+${1JBT+Zj(puB!Ngxglu!BZ;+iHVY5ppf=FyLT$9#7|*i;Qn@w7Ab?+dVG? zmN2bErsV_hSOJ!R8^ky8V4xo`NQkKXy2UJbNWA>v0Hma3~?WH?jD3EgmwtAb{ zhL|M9=#q7-uA&>BB?V8SUcJQ@2G4O3iG%y-=3QA`Z@WHdPv4rT7>O}cmP8-z_*LeR z8S3M9OLvsY(!BptDQxR2w(1+qn%%s)EprAb%B-TDn=fqbP~IJM(l~C};td9Szq|-0 z65(D8n_A)Fex5e$eBufFV?HyeWaUjr<9XF5>}YuMk(0ZYUa^LL#dXWY;uHI16R{BY>XcBmv-YvC8k&$7dX|Goy}J8|N< zf2TL0Lsa5$ug-xb$2TZ?_Sl~ZX({hA>V}sC1GrQzjWJNw`+-budxX?$2tywr19}s= z=n|IP8v&h(HyC+a->N1PZvtvG+I~Ju%80o8$PjQV1=GHC+4~T$dt(v*_cdj+Uvn%P zZWeNQ81c4Dm(i5mw?gu|*vc7yp?rMdkOgF`P!RckzQ_8l;k%FHRq)%Ni7y z-a<6=-^tMK)b0Eg#0cp1=@KoH@Tug`(CYoOrI>mKR&kIe_w7RY9Ee*2Q~f8OumV4~ z0NoMpi_S49A^zXOY={4Ud{AbL8`wEf0^a##C2WfQ1gU9Zyk=wHY!UX{U)$tl;J7)Y z{HVy{VG*m2hx4pKAs9I$#Qao=gfhi7y!_tx$sohQpI-j3#>j*N2RmkEwn|cMhm~*X zTm9i0;z5&qDb)K;qE|RPsnIsH8UK>rhZ#%LL~lZRU1EJ4zQgoM$QEJn<8;aK8tpW= zuC++zU>{TGvoBQyOLFBc^4}Fngi@vOdMiwNu~#@5 zYpZzFJkw!ur%s>LEZ>r*HrDxr0K(V~v8ees@hgB(#z1uqMCi-TBEh(^oNa%fN)a%C zPRo&c*8!U`;7_RJNji{$6_T3oBd{tU)sSl)LONl$!zU<>(?nC30g_y;68Gd<&cN2*5J0GSdy?qTi7-2vAmn*a z$=@s>34UaF2x=Y5Slmx#k`Nr^9qYkKnmndX4SG#nkeF+k*u=|-P*7{>r^u86U@Y@n z39d$c?clY6|4yYS==fkil%@107^t#_+uqWZzNM=P%WeUBa;AHYRZFZbz8Fz_=AX!sAweaj`~t@DCP>Kh~fb!xd%`(w`) zoM4~rs5ezxw5{#mi;@gSZRb}+zAYOhJ<`saZV~#)854;?F2n1+Ea9wBmdIyiQZz~7 zwII6T0CStK#Jb;8a4`Q%;%bBU9b0Vy#?bevYlVXD{b+`*>P43Sz0LO z!5U7aB>|Qq_~rzyF=q`Nx3YQ&Y%b0I)CIuBbr!=a;~@%YfTigqhrkU>C+KjrMo7X? zPVwx)>6dgY|5IuIe>W>_mE=VOYW`7q2z?WS8oiT~KbdWImjCvJ>Hx&s{PNCu8~xVa*0?pnJ7IGF<#MQIIyT6y(eppZ z2pcdB`a*!AtPVOy_}3V}2iXpGCSxWNg3d+!>tC+%TRO5QsaN^bU`K7ix}8$wejn>Xb`JGwPsyj)2oh^ ze_vSuoGi+13|7a$H@S<_XSce8TF+R$1}nEeyGDwPt^qqpYjHv6GWef91P;k7|2i@1 zGe7SA&jksa>^1oE7qcA`A7{OT??zo@P%lPEIXJ=3czzLklJoXU*>2-4S62C9pN{-? z_k*g>bZGrylKfgtL!$>WP!OVZkjH+;7DB_f+KQM;lECbCSi{L^$`HMQxN916l5*8VuN9*0$wIS(_uJ)O+v1U-FV{q?~WbmDpXn-y9?hb-nK z8#;kmJ?sAe=PQ2TzPN`l#j}z&xZGR7SXbV0>P6k_`5Q|_JA~r5<$BorvB&zQ!vcG^ zp=etNH~S(J(DRppX2z%8A70SFpH*^Tc}WW}St@#58OFFs0r8o2!b=)A3!jiQ3?cN~ zg5i}hZ|Ybk%zB-J)3PzXz=-&SH-i{ z3dc_ecAB~g_9=BmU|VW*w=F5Sm_libk>mtF$y=`Xi6gL~rJ3=}O9^Lqy^I-^jbuJ+ zl~V8l_Yp4e6**NxEWh^V2)QrEc)rhKNJiQPD@k6nX(U~=%ivfoOp z!GO=TcsR4vdy$`lT^@&RW$1O~ylZ7NLPHXcT{Nn;;ih|U>ypwA(c}cn$vaxU2g04K zUhE}CfREd&_XZki^t^cf3mCkul8R}21BEM+K1HDa!)3v9qa-eYNy|18b|_M>hqT?6 zLd*S zNgMjSP(eR%t}VFib-n`B&l$BgN7}d{boZlh_H}wKM)@I!hvFm9@o0!4QDe^Vk zh0_ilHGNZY3Fy|PicV#mRZAxupi&?ulznAaz`~9x#dR+gWM`w2P`Mf``*YlQ9V0%6|E8kEL z=btmEYR!2}Vz7k%^U@EcQBor#1u+%=?vFmf**c0@oR%J0&HrOvLb?alioSP&W{#Sy zbE8VFReK114B52SdZyyB^IGS(AhUG;@N-Kj>|GV&tQ7KBY?)1tcrb}X_iTSwe~sk_ zkC^>vn_G{KWRD*%RfMxpsQp!Z@a0s51dmu`#S~{KB2p?DZqfW3o2xtBa62t!3~M7Z zqnHX77+3KVh8g3VKJp2`$vTsE-hmJiUfy}YZd0x^0MUzf1)K_S zyrUUV)h*P@Q`K>mf&R3%+XABYN4c79utykCmlpae0SjaAx?Vv~D-cJwS)@G>7doLyRuZdpz zJE;=5O~Z?^Mv6|yH$m`10CysraNblNLiu4SZ{xE{%MuaZa(-x z<#Ovu4Ms2Q+@u-V&-hnN`pyF}!Ey8c4A+_#qf!VXvB9~ywCCK)vr{oE@73blpMtrHFe8J8>YefKFQBgyCvjzNX zIz4XB0t~kUYO=XJjKGs)^}K#t`9?bI}3*kG_(c5`*HZTGNZn5+?raKnJrQVsQTU%Ew3aiI*-Zv!@MYo zx3{BDvtMZsEj>|NX%eAu#nx7ix*|W|$K8esqhu2Ns3_4JF4?*aIIT)H9j4+2+9s)`>(@W$<#^ z_if2LjV@#7xkNz`HKkd@)jNPY%_9fT>e-$fD#8n3`MT0kIi_9Mbj37P6R<++Z9r&) zm13+<=*ixJWs#?MP%m}}UhG|nNN-PZZD%T|>To}jh(qeb%6PZgU@4wwI?6UvL8y`* z>rY!jXqb0IriWo5o)?VjRhJR>=&6>Xj5)4@)C0SvoqGXaWCvpHN zCl)jx8)Nb@1)E$5h}lO>#|nlTiRko@?`}cFOVtEw9Th)?yI;sq)MvONI)6cO=h)76 zYQPpas8$SQ7<>`~(;mFCdKv3naj1M3NIH5XNC%{p<_xNdx_R3QzWyrVGTeeQb3n2L zv+upy+jIkXzV5FV1BTop{;7?CAjVyA{(k$=7z;xY2hluVl}PH`kELaN^n@8SQ!9Cqq7xSpN462}7g~b}V)Hf#_Jl ztAiBQ@CrC(%KCOi-pF1CHE1>?ZW)xzrCf)sk0j19)HIsklxt(mMe(B5z#)FoE7ty2 zSg3>0iM(QlmwK+uOnj5|fgHrqz8@~<*^q$A8LTK(X8a1OO|PhBXYr_FexmS`Jvm%o z1R4`Zy+ZcQIL*YNj0@lJ)RfxBgpOS}r$b5yrYiVt!MM?uEfH9)*kyfaL*bakS|SCa zBg@EF4Xhs67VKET*IL#-YTe!00l%korsBlnGv|4Ps(~Q>mlRWC>L|}OxZJhsO1m*! zAU-o#UaERAwbq=zwp4=VH^S6M#M-#lYYKC+loZx+cKZ``$Mm}K3)_{HE==BTE9nuP z8>`KfJ`ixN7&%;S99aO`g$zTghA*&mFbLn>0v!nSG_{4?Hhv-~>EZdx zq(1j8x!^otq~4+EZgT{yvf9Ua#PW3xF5O-kuqH+B_F+21mCahXYApx0!va;uun*~u?-9K6 zy9fT3HPihVK=dg zHWxzbaWo>=gaXCLZAQli6{S&G#hM|?w|5>gx4SD?Ea*qm+x;}&@v255AY`BC4wfBe z4A)st$*v2!nPDk>Or$tBLx z?8UdK4@Lg^hOt`n(~UU)bma71&A|QDjkX8|VpguUD~O5Ga6Pu;LbcYT_fOZ0#p~K3|cUZ#=zR&W+^(>g&y2G`9 zpzvAgp%Q&jDV@|{p|<_7APC85060NfW38J2a{XHqd5 zL1uXRU-DbSacxm` zm%HPY^s|_8Q7P%2jBO)U_06P$5?Su!w$>py`xB5k;a8Gdh#m^eTC{|hRhFShdI9aK zN8MMh3ACK&%j2m4g-jU?<=4Y!CQMxO$Zg;^o}16hEaj4e`mQ_9YS-P!!Kql;KYE{x zcBSU}YPjwnmek;aO4uI*!l?(%X@*3o<8);cb?e}39)mD4IJXIZN!&^x4zD#7P)>g7 z;SygVOkE4g9*ZaFP+X#@ptB-UAakG4yY)2vaHkv_S_ldENX@j@^Cvr&v#lq4iybpv zK%liUWUQb-SSI!>dZYBiAa`VDTgol%TpLdmWS(1{@+On$($zZ5D1E?7hM zqN_>LZEeswFX4O9k4Q6RzXPFn- z@$J{eT5F+uvLtNDEavc-Z14&m_8Ucb_OEC!ec;nHl5_LB3o^R~ZpLg3S*u+~U zf|mG$h;N%1MBlqyhnK_bVE@qDQ(t36k!F@)pHYnn>CQf|C{kzHKfccks2WCoH_r(7 z%U&j%a!aAottNIxK#yyJmxh`mjR>?Vc3I`OoL3?EN?#2v z(ak~RpYFWOilA;L^dO{&4OHJ48`4XgwPRST(Ybum_zUhiTXVBPj=47jyr)wn$b0s2 z-6+x;<=ww-VZ1#oc(TIjoyekoAXIv|-Om@_LEpRb&A*dDgfgiKpAzO0nEdkM=TmB9 zk$*f>qOgI1Yx@3D6VQ(dLH;M}v-Qt!XECuV4*HrTv<^b$G``c0jI0$X8%{~f9D;M2sJDLIg&l2_sxW)4(}02y~> z5lT+TXE5!O3D%12*$RLAL>EV=X$Mz?waRYZ%|x`4iI`;U6WQF;7oxSMWrs-*OTf2Y zx3-)2w{~6l2g@ij>d<`HPg*eOpvQka7UQYHqD#E1vR)5>@?lg?l&pO?fFD)X*BQkf zYMZPxe^ZA_<-jCPzF5g4$0);JmfsrVL_)Q4T+z9%g!Y@gt?L9|+QuJEm>c)UP~)&cL^Sz?@$uyUl{o z@U1g7lMXeMwNjzCP0o7>h>b12Z$^A}JkOIQn+kGi_IK8T@j}<62a)~4y3_N;W@VBe z855UT;plwklbZdlclVTtGR7)T59MXT8dJBfLar|a?v*~hvDp=wLKbgJk%tCo3bKWz zH+C0LahgWRH8as&r)D9bl=hY0DTb;(uxjFvXJNoBSa^YEk-e+k{LxC>ccM^^Sk58` zOMNgOaSKHtL7S~OGgQgR=eT_oBVV#JVM^YWn|+&Y>rE0}dOu5e*8t15RMOohd^@Ly zkDq@dE8Q8F#8z}#b$``LJGFL$)jy}~uM!fJ6|9Giq1;M=<>ng(2h7WZVCO0HE(*3L z=!;YwcfSRau1S!Yw}?%m<2)DUxmU~T`L%BdwR6X+`J-G&h=DHM!}Re@<_sqC)$pxC z(Vi3WBOod&9?~OA`O5lULPf?FAqGKWi|tpOm#_bzyc^F=T)SL+C$x+y85@g0tSO65 zW%;ixc@dQspwnkXC^rM_o%xU=uX5oWuk5iArjha4!ZPg-H?!WMhI$qY3X(*7=Xz>hxv=3K6RT4d44ZuV|%b?3zf&(NA) zS8}p=?}debxllOvr^Iq^L@cL9h=rXo>26~fAA&hVrEhEy9duNKE4{~z zo{s&%mUUia13|$ zf^PcAlmuH=)F1`iF}Sac=*A4 zE34;+pAkaI=(5<$pM<%TAN{M{-c^wmDtq*vQ>9O2FDb7MRqk@k4zM)*7i^;5CZT)- zB;2Q07;X=9URaP|tXcN+@kQZ z^7bQ=`Z6B62A-)*qd9@Zg5{oeLZ&bER(G~R1Az7L2Qc#LPj>S=xR3M|L{ha!`d&t+ z*4#O$_oJy)LtRs2)juv_Y(D%cgYc0YoCj$hah~J_vxP3m&j%qybI_pp&_bb-eoa%F z=(OMx-J-E~>5b9_AM(Hq0wfUwC3GOWzViqrRKP)2* zw~X0D!3_Pt*jxRX+}q5j!K+8e!H?$n3ippb{1M&XuB(;6M%>pCA;TTOJiBo8RQ`)^ zE^{vJf@etUKkZVQo#p~Y>k4>Eqf-G|SAXQpO5k+d-`Sf4brfb}s)u#JL!pt*LH4^xO0L0U1y9AU8R+3{`&@ z^3Ih0hX66Pu&~Qfwby2lct;WKb!}VoU)+rho6qJKcHx_~od{JC+$M?Ib@x0sFh9Mr zImGSQukI6HrEX4@>KxhZ)wr%vdbA5Xzem+>W=Ultu-xA7?oZqpVv8#wEPD&mB3_f4 zeOXwHK22#pyeN#<#(~vnD1Qj50gA)ICK?ObQ=reZ)jMH(R%+o5!(VuEA#($e++;LY zAB3D47KSUD>nKv%^$Rv~5FyRX_mxIsQZ6Wt;wt{w{)m5o@-Jj8JKr&y9?fd;hQ5zH z!44Heev!5y<i#Kx9w(n|zk^Ael6ww+Rh;8Wi!!c(2jj&4zprtt26niRsJ65V}{re(ohtNyac!s@lNV|m_)wrwDhrGllYP& z8xwMCvC^aqTThxjO3l4m+~2zDY=q8fx`lTu;)0uKPluC4I_e*Ie_0~;0BO#TBZ({k zFb6~5ma|Nad~v{)d48}d13h0btb{=z;keqTAKNAo^N&O^u{*D{o?^|0ACnZ#k}>$7 z8L}Sns*8|KL9<$DkgbtUmb!M_Rnz({c6=7Zw1^K~(D}{>?_DUZ!Dca*#>&<%I&iAx zD;6pB&OAzDG}iY9%-&JA3kVtP{l<>BU$>k^#ucT@@0Pd?xvko1zetTPn;ITk!G6qX^Y5>@z*B!c?8 zZ^u9LD%<$MBid=i1q;NKNirAF9A?uUJOaqVBELb5+B zqJ9LxHm>@-d!Ez|=gL#ShEQ`2iUP~Mx~Q#{Wg@<|f5$1q9FU@DxWSfL9y9(02FteC z8T74t1PMDD?zJg9BA_bt*q``|WJU-mD4C-g$`Gv{poeWKrZ41zUK@2&;wJz((oay@&&d;6M#F%|in|ZH4fIRSWjQ?|*ri+E*IRzsfDRqjhl54Bo=PI4T{I8ap z4{G)9?`w#mNF=2$%MN!CNd;oBwcUGY3&ajBE2f96h6jJzav$m?hur0rd6~}_OCf`5rTQE;EA#B4|zzFumu&|*EgjR zEt8w~^1Yn9_@P*V7zDms$k)szT=(B)9v&mAzI$I}v|fMY4!>(m`1VNM)qVQ8y6nzI zc2WVW>tvi}pgcpAp<;Mhg+S;`$Og~@&}Ds=1_{|lab=-g9zpEytQjML#$?_`|8YxJ z!Au2>(eF!WCkvVm(5h8Pd;4shm~90oS^bq&k+C~foeG*GeMi)Kimin)PKj|B5NEUQ z@(85}bzfdXUPEhYbbUXU?kw2$$r{wPipCPH;$rbFcpNuo{Z+a2#32tWCw*e4+{YVC zbbDIFekZ0_LLM*;&#QAc?!*efNbqg@+Yj#{R{;?f214u@w+_0oIgp14eyK}ln08u! z-nnkE3YH6-2$EXBuh==kR&Xp$-X*4nP{wLkZx~!+{v@&p{|5^${$Oj6hDJy!ml?Z! zMO{;#o|O+arYN#Isr!G`tlqN^2zaau&Q?qM1I(TveO)ueNr53}VVF z_A2mdyklWXza$zw&LRJ3>FPyf%p-r^FY?7hi{KR>23by7I_bqmXcJ9i3^2(4&c^YnbF+N;hQGl4j zDa(JkW^0$C(E8tu8v3a2JQlXhbdQ-J_K~7|UC0^D=*P?0GJpRz{P~W~M%v-`;je@0 zwzyZ4{TKYW8uX~fDA%t%)K5Q?%jq;ey;Cb8;<6&5SVA=Rt1M6NN1o$FW4X@b$AEWC_5?`M@{d%_Veh+}`T7`1 zg~dpH~Z<}jHh|0SDllhGdH-6FW8JaUcKozU!l&x?e!UmC&}Fg*BteRYu`Z~>X?4qXq_GoF<*PH! zTp&G3VN;(wJb4U=LvW& z)-m*qJ6id?ygP*d9#?yJguX>kV#67k+=BQ3mB5ONGN)gaRe^D|Z+5b?Z5XW9tuD3B zPQh8(nc%*kHiSjkS|Tp_6iuE0qU}!aL)}oFCz=^m-KtiC81Uz--ohYWfQaXAi#~`GogstFeZzHicne zdq4|Ys*^`0y_;FDua$%7>LJNRo0s;bz&1)9EG3k>F8!mO?4Mh7D00g%=qwylvjJsj z0^;JTrsO?mcE#u)0gSY#)1P3WAXt2aAQ!4;)m%zKfu{7C(R|Wz8J$vCFuS5-mtOZJ zi-=1I;2gsK6Qh7+%A7bW|Cwh}XQcX>{?EM9&v`>{8g$=D@G_^&=h~ik-+;ZirLWzc z>e&2>=&owCA;TT4cOF6xd+DSlQ!f0W$S%kZp^>(Y{7-+J`^UduKxe{|*~&ry=-1X3 zwu(Sw$ZC45UcJd_`8zO(|7RCm<{w2r^>!c#n8*L&+X@+E;tT<%Q&zMy9{uec=8ymJ z3Vud*$sV7739LkX&BX6_|DgHrDakxnh7FtG`Oaoz^{mf3Wj;MwOWh9{uaQZ{X=H!0 zAZ|Rlil7_0*+E~Zo!$&7S^(#HnHS{cv`Odt@UIZWEU+h*_K2rdebe8UdG%kpTk6($@UPeGORZ7Zu1gDj=NgmeoViVb3wn_1jKFYnAOMjIB0RDJKU&1A5<39|9+eR>fqR2&7-%hhy%SO53h z-_?DH8dBf9n-ItNtyUPEy%57x`P|IR&@S|{`qx>U(Er}vm1I9Bg?e#L4;Bye2Y*NU z!B#2QqZ3Y4=31~+b)@{7iQ}W2DL*DboKDl zpnjv_IcI7>#F?HWA6;1yXDoLVn|jPpu48pySUCmt@p*nNn1in`>}W+M=89r3Uy#wg zsqmrMUc^IT+l5mg62sgHwrs01KIu!~ z8Z;vlb1HrFyR>5a92}Rd7=Cc*(1}=Vj};v72JPdJeVp39j8r>l*s-1oPGqlDdUxyW zamb#e$6`1wH52a7opjW-8C%msu`DWNbKc*)>qGS#dI7+%hG)~sp`|tF%Vr_|SGwO21eQ-q(X$a6V`dQ$&~5kNnf+}fJ$JeaOE{b;~Sicct*bNrMqGEIBr?|8i>6eRW6e!i<2WGu6S=nB5iW%i;3#9a5p%tKOF} zS_d5<9P{-W>QL6i{!TUyw$^RK!5-Sy0+SaNN?LQrRYEEY+&P<9eW+=0eRLguW|yo9 z8n5DZ)jJqqn~$Xt=sWOPl0G)9vY-QP}qD zBAzDv712iB*+}+xlIC1K4n|G-q9GQh(*1QIkftxpVy;ASueM zBOqp;NdiQXwkR}mx6mCDBruUtHc@JO1cxP3rR?o*y6s#7W&)J<;%uKCg($?2ls#5n ze$0Z4Y=^M%73!ONhK2hw7nu#L^#j+5Z`2lwaG9&fHVvXAT@)9f@U`@2SwnQoU&pJ& zf|qoSVEkz9wp=5mdT|~{e#W}JmUTUg6(B0wTXP`Gd*dkGJ>4ZELk6tgD=dc-Fa2^X z;hF{IGm>8{?$-N}62@<^Jg~XIY~Nh;xL3z>BPlr7+%h!&T55dw@u5cL=6* z!bPTQM8Ibfab>6PxVF4g-6KQ3v>{n_PQ{Brp6s)-qx$4o;Om@o<*0y&u@A(`qeeHb z`_u>)Qz^@k>gnq^L5O$9`Zn}CEJ)S-{eC^5?HTaBPTH%uU3tOf5r_yC^h0M>SyU^` z%A(4molgnV$-$6QBh5U|%1cbPZyF&=N*a!@yKi(ER8F@0^`QDS9HRFiBnceaa;hc^ zRib)SZYg8(?=R%=o+)XT51dbSdW0$g1HIjWpg=+6z8(C(8@Y6uynyAZb}K5I@=Usq zI|Sk$W2=Fma6y7^??evO_fryvz|VOweI?`#v(BXf93l5MIb}yBhlN5|PpXZ*yQwjv z<0(n-t+z$$NDeC=T2p~n6H?klN&*b!aewa1HUxPvamsT*ds@w?W3!H>A80%;h`Xg9 zuB>Owb1^jzjGypPH5l2zqlNMJASEF$LsCQf&rY|nC=5FS40lm+1R&HPUfHz}yD1#; z1DbccO%q*Ybi9(O?h~ekAc?}U7-vS4GkDvYy<8M`fWWLU*s~}t5#}tn6IxWe1Y?@U zw9=13jIXkWKG0%gT+x~NxsZcDT3EE~7pEZhi>6H9i@BC{?7@Jj8@o=(q?Wwjxh zN_JCiYjVrz-1nas#86O%i_W3n4nb}u^TVI1J6wS&&GNKJ;5Sx$V_(wn`@a0@{HPSp zaYFac_#D#RE$!`s5=7LwA#jzL2VUXG09nLB2s=vwn$};?#j=R0YwOncAaaV4?VW;w>!_2<5b7n8 z{*{HlKc+(nN&_|w=`e9xoaT!p=J!c0QOw0*;F-}|^{X7hSW<_JBRe>tI08NDWR=pW zgDc>}fyKCL$P3lt$anxOUljqk^jqJ6g&%- znTG!spbb35yOk>&sH@Kuwn(d+LoQjNJ%0MEA_srp8pYB!G9qd}r1;_#+TUnNO>--U z9kSl)%P0+UX=FBXR zL6E1{&MF_ts#U0;(h;4nmEjrArdam#T882THniAp*#S@q)ApLg;wabE79G2NkYn4_ z*3t*VArNEnC07hm#cHdmfNceJ#Dwhu_!)Zva5H{BJW=YSkF5BR)s!DgUQ)hPY%H`Z zu<{jR&Ll67fS>n9g`r64G3)T?N$q0aGrQr@h^__m#~S311wFpwy^p4+*`G3tAgNW4 z@}0lhBa=+|Za#_(|HI=cevKN=g^g$Hk$+#T`kMG_D8QeZQeXU2${MTwUu(7)wuCAZ zelJ+IYp0{uW!C72=IB53j^60GgiKw0PK^cK)b&&;>8AhrR%ixM5}69R@|RD!#iF9~1K>87HCJHh3!0@KsnQ)r7GCju!HdKCnrfBkT0&%Oj_z^RPeYV0 zyDw`H9hkMM4@moYzqAnqv%gHN^lMO({XI+fz~bB%ZsG;eI#<>;NXQt2Ysp~1-h?ZN z#UO4|o{G92+Cm)*w1-n>zXn$uLQk_*^!&ej2A<=d!)EayT@&W z2oY2z=hp>X2+fAK|4Es>peQCR63_EM^J|%tz4IrEh!)4@f-kzm^_MkJE-QPg=bY|a z_~_F50Gv~(_O}Nf+4+LYKfK9`Jr3OqT-7GtXb)Qm8>=(rbFzYSe9lTO&n=)_78P}H zKa|mcR65T)GeUTz8qVCYn!Rr%ndD{JD$x-Guav%@F=sLBu6P%a&#Ko<6qyK)uXR4F zEYK<|P)8vrW;5>|>}O^0Ac<6Fo~vtrID|zj+5B=Ckct%RL?h^!40(Ua^S< zRAML40Q-ya8M7^zz|6oz;4{i^?dfRmKeDOghpr#O*@J&-e~q=SOI9V%fFK6d<;V=| zbyxY*t7EZj;J+wSTbC&)Qxi9QqlE-<@JNOFCCXcEr{7^`H83XWi{9$>(u!ZVI~}$! zIjp6{OrD{L@BQ!Os^3F5P@@?L>4q{%o%>AuT)8an&bG+TD|F};PiuB2abDnfU))BR zRsyYgajrVc^P52OZqLgIRaf>W+6}7%{`-Iw@eB+C)#^xv|G_+m4*+D8zEgI5dOU^V zL|wQQAl*@K-m89L5?LlhmutJ2H~|%}2>18MOzoi6u8g?3o?~c+l&JfEdja_(edx#< zqh`4kdD?X|H8vnxUD?v7-~QuYIN)ADo@7tO`EH^us|&XNZ3Zy@EZNT?evn3^>eJD1 zDoew<04gNV5A!bBeX-vpRD;glnQp%K_`$akqBychHy(6bgF7FrffD&`Dd~;*@mgo^*_{dXY z*%a%7^>CTx%jL-n|5J-X6&>s-G$Ke<6WNy6yc$S72%{L7qin4`vhvs83rt!u$v~xl zIhC6z?t&@v$Wjv-=e%LTNLg*C+|2E9|K)hk*rbz4>MVgdT!Ef4Ny(||zyDJTE0V_& z@uWu@huF_M)fJo=!!tz|j~P2oxXL$F()as@1pT$6$@!ZhK>&;8#*agiAdaG<0QdLv zLHrEipLsvN1Q^7G2fXz;UuFkqJoF5efiQDUBU+A&Omq9k5j<*>WW2R2GY zg85u+@rj;~WDLi!v6F1<8x-8Nv6z5D3 zq;|5L!aDL8!D$4?)7sGGK-VdtXe9`!=6F)jyoRILmN=#=V<8H2UF}W8!T`Jkex&}p2 z#m*^--@b8347d6wUEE$}HV}fV8U~884S}jJlQ;#df`91l`|S-HJ(!?f7t`PR+2^X_ z^SOQzz;qb;+ z@G*?__d>P~v86r*vMv=1nUv?dnqV}(Eh2@X?R2$&$}J((SWot&E&9}O>K;x?!KcYa z@4XOC{BE20T1ku-jF#Ej)NBQO0~2YR6_g+R!?VMn5wFR+va4Xb-9+o}2HtZg(Qwh&8Co6)nYAZ8)ElE5T3LmWR$iI4AR!^lj%aH3@E^vEz#RN-rwk7g?@7^)|r(6#}?*reD_m zM-8soDzUcTjpal#XDi5Cxn9?rc6&Qo6Wm_Pr5Mn!v_{Lk6M4fGC%>n}`*#vShCC>GBEw$yVC-Z046)bz~ z*pLZ#VRffQw5F#qaNux6TmnodUdn{b4{BDpX^!cn0U5gK>QfrIDu9>kT(&kB+6kTt zVkjk>GNd8E*}Ce!JQ+Y)9nF^Xx!WA5%O(4Q{Xyx{@#7aiWGsuw(Z==mGi}n@F|@~x zvcc;eh5-7}aXv!=>&f0nyI)R~4+);LD*Tbu2nQja8gr1TYwW;v?gRfPnIh?4-*tZ` zs54D*$k^GCrlxDSCnO84W`dIX{UcJHA{Qy=U}3@)(HRw?Uaw^udBadet3w-QZSMe> zZ$`@aJ>vDqPJx^P|0Ld(kf8jNqUT~7c2>#s!4lH3K>`~^Fl+Xm$yp9E2HAY5VBfBD zu1roaxVtA#d|EyPBAN#@B_NBBonT+3m|vu@hT5rQ{|$~fH`frT{y~DlBkNuXVJ>P~ z&nMzF_8l}p4nE+gyo`L-BAu*TUwvP(?SQQQ2%WN)Yl6?7PmsKwsH(BWn#r-4%u@d5 zdgbn%dW1fl~Zk%kw0afT3`e=Fd+?PrgTs8vG_BA+l^%lAH4VZ7^^XS*Ee2mKRkHil8WJ;c1)^(Pj_@}&iyt^@_XD;TXT-|9)a^Cvk^ItV zvlH&ZfGtpzaCD>D%@o0N@D~^4J_L^;w4NBfJeGq)-qchdxfLqwCs>1#}XQr2x7@en92=WObhsa)1`mUFjV02}mKc6>~uiOOw0@P>x3e$q%Er2)kN zv72k3?KUVH7x6>qq+J|s@4SMm8@KL+z(Hlwm)&}+jh3Dhvv9nv6zgqh3jS04txZ5D z{r|aorkTR-WISHm+F-=BnX)1;oGnc35u9q%?zUj`Reov+^Fhbxy(V}69uNSo6`xd= z@R4~@ujv06O&(1eKb$<4PK<{?1YFwR4v!ndxPn+V%kSRLXF!~1eR#gFcK3ggIE0k; z0|2Q}^yavl40x>kr{J3Kjs-gVR~l{xWb5ccCPR1ly^|x*>Y;tV#-*_dK(@OFvNZu# z(u~=>r09p+SS=DrxC%V(clCSC#Wh#!VWP(*c5x1~9X_H49%YRmvfz1+uZO#3+?DAF zfy>ia28)j1xZ|NVF}M6i;l_!G!weYs^g(DT#+^N%aZXOS;!=iRNJs%ycZlEH?7Ib5g% z@q(`opQt`E@0Q2triwo!q8Ut0DF%I#!u1acxg2)Y)FF~NspcGi7^+;1hlf8@ zd+l6zHfJivn$YE6qbUl@8{tOat^UO}FQ)#8H@BV*H`bjIUjKw|UhSqoWl+5-;)3B~ zv$eu;)dYL;w{nhQDYu0H!J)I?mGr|O!>9L7Wv)2Yhdj5#gnY)+rY2qpI8aXK4tBU< zVvS7OX(ecG{MG3lFK?=};hgDPe*W*F0kYjbUoWOx4|5?M-dvC~N}sr>S_Ln29M4_t zDSO}XP_B;?UChC$bCP>aHAPn9Gb!&-nE|33veZ;u|M<$+zJ$Sbrxf)yOZ6xl8)(Ca zGtL`X#KYxIS$Ob#t!njj#rHj@*ylJY`+`qfwosmw2^FtP->41@?`Lh)YY1Z7z7#mP zFiT=Xq4lbR!^U&^k=c4qqmONEZ7D6RZ28G^KNwEWrYrLKZ1JMidsStb7eyyrI$}c3I>kfFP3nJ^=WmZI+dLjP3-3RFO>2wY~H(q~ZERytYhwqP5^v=@MGlC~dGCr3o z)SwxyuOEr*I0eVfAd9);#!mEoFV(R)rF;pOw;x6?#?w`T3A{a0<6XRNS*+ z=3%w^G0Eog_fJ~;7n-7r$vi&_a58TnL{x&0K5D z3pWl;2*3~DU~W4*w2@*S_DJP|aje{TM}qQiIY(;`PDnNzNWty4Y6}X zB{r^`#mjjC5;cHk1@=f(X_MY`)6KBBH54QJqc{J`GrUxo!oJ#9Ei)~7GCNfnczAgK ztBw7tYSpW*>R)$O{la%1_$_Y_o3D&jUvNtwp;mKbVl*#N{VKS>VrI)%`^))HC>!cx zTU^Pl?R3Tcw`$F=-^;Pu-!bQhw&U~JH~f+umKoE zXn#|tp&yD}STynd$IDxJ-{5oY-6%|#8fU+7lXg7rOa{cNbg9SmTq&SyNV?4fHAD|H( z9aC?us~q^|^=n~6B#9xfe*fw8C&w{*f=UJbd-F9~JS{z0C*QNDc=ka(v0f4j_K{8hjYDn*RFzq|6d zfP@+N#NTEcnJP7htmfl^(cl>`thZ5Da^&Pc`jQ^FuCc&|syJE(`)N|dGLHvazM?MY z$EUV7pB%+Em1_nceg(xO-9oh&Blmlq?t+&+Jd^3$ijF2I>i24 z>=hKa`*vjlsgEZo6>19-khI>3Kfj_J^M@!K>muUs$KN|AkXo3b)jxc&Q)B+OrY5IM zBGlH3OA4d64F;vlD@=lIizpD7UykdW#Vu%UIW49VIWm}AzMjtRub^y=$CO>@Hl3ZK zO`sz~P86O|GOgdzr)QA)d)Y>H2KAMbybijos&!ELXQ1)^v`j1Z*CoR-yw~E)2cs)( znC$`q&7c!O11) z&5v~>A)4XdWhB6{TJmS@0(h^MOGe$R1hLeu{J3>a^rK3+aDT69xju8d&#HDhDI&P$ z%|`uB=jDvA&vxmpQ(x@Q8yWDGTT(^tY~!J)@3D zWAaDdPf1bJnBew}!)0>YrXKAs%zIxi<2_APvUbMCf#aV8cG|BkoT8)iTpYx!EVirO zNqJX0&#&wpXG(HWKoO9o@``?UT9uw}v_^CqvHJU(_>%>)>&yyu+u1Fxj8m0i3o#uZ z4rQ70ht3M^@h?CswDu7eZ{l@e&Fkt${TzOLSDYlfKCjEl3Q)E<&% zNxEP14Gy~35O@AN(J9kQFg9F)W9qCjOLrb(LA2Jr%;)YUwJG%nhn|S}H}q4>?DexI zvp5!572S{|*str+|Ak`avGVw|W7h0owF@G5#UTGTO73q#ESG+dHDgnyxb_~?~duc{H8+PxkCFENt1XA+@OJ) z#u`Ztr|i&czC3{t;)~9(hl^<$2A@=_fJXv1T(TAkWEMf^LgU^}krKzFJc0 zWuH=%d%hEzBHGHzf4u)!dz|S2mhB)KY?zjMDox)*m5nWP%1ThSnfko z-G=r5xm0&U^Ya=Uzr88>`#85GW2}^kdrKRL-Y>9=*mjwa>i#rIey4AvAi7HE+|K-e z*n01%CbPKvml;PLMP<}MMcRy@CczM}>sr{msjPVC~Z^7EbQT3*zOInKNMs^3O z>o>*b>8Wa zKowRl7&t>Ee7Sa2NEzXh=7{R`nyeXaWuMg3@Y_OC70IZD2jxgjg0nEu-SAo=UgI5i zN9{SU2CdVNqfgOT9Rxlwq+Z<1Y>M#?W2l@PCd)e1Iev2HM)OgFhufd)_2GnjD2A|2 z7D}{qZ89!yl*279I4h)^z{e*ay$Eay(^ZG5S#=h|!PtA~MdZMjrbff$$$>D~f`Ww( zr#iX#kD!ez6ZzG|{Qf?$JB7Y1f4tB5fTN)C<`^ROxx?mb0~@G8nn56fplQgevF6w4 zOn+6+PlR6zjc3zPh?4Vb$n-n&kzIvG%w5F1RO^uwNboHPP2w$PGAoQEe9XNA;!Y3M zeD{=@glfUfw@DBpBm?zbDN3Om7cy{19F-huO$hix&zkc#i=;Xzudz~#d@w)#O*KIq z`Q{z2mHBQ92U#jQ#SJ#TDSq@PJjkOOMr7*JHFrtyi1}x>E&H4iaQ#3%*ZvyY+Ilv} zFP>6Wf&8F+$%St?O>OHbKJsD2he54W5$Q9`><`!@gnxgy$sr}r zkl&k~$KBraF1)331T63Y>m3!^4eCivxsFkCyq z*uR2sIJaqknx34@VY>m^7HG5RZ<}hxa7G_Ncn?r)ArVmiMMR*&E|Okh7IIV+-yZ3F z6wfmikp%Bsaxo?t!Cu&5^_O@d%>OL-l)Z}Wo9Cr4MwD#vE3<-#S zDY-kE8N_TWwSqEUl+AS?n))8;#E3(UAgbbU36sWevLeq(`ueu3)hdk@dNS3+I}Xcf z%+ol1IBT=@l2q$naaTZUG~Ay~R?16d?6i~npEsvTexpSrvL!HveYCm_!-UX5R1SJN z{r71JVoLSh2}dN9cCU-v0cC4rEOKlc^X)VFd?eSO z+45@7Ih7yMT6@l3@CzfO0SA-NBunN0gF(*E1~A_*aC)n%FV4)B=~b$qR!=2Sma=Hu zuUT2gvZJ=)nvy1>tu<5)r<1xhl5?tpW^NY;WEj~1CKMT;X}oCiWuxufCm&bLM8V?{ z)S&xpM2w4UpgQ_qguhqAz{U4xIoCbokRzziYY&dRJpy;m()zJBU@(tYtmce-(dMWr zv%1F~@N$c8$Hc@;KYtwUv%J>vwlunCa63hj7z;5qGw(=>%^$d$zV>LesF5-0w9KIU zdG)-Hmvb+4SYN633cdF{?q%UfsY8~njd#|@JZ`T!mc zJFqh*HaSL_U}|ZH*QhsT;pL#xm@CTs$K+QzrC~6uXtddjOLYtIco z@VeL&?JE6;4ncA?=1hN-{!@MUh+bSRC@mr)%8V;rgF{{u@s6uzs?vjNWg&4NZG4*_ zXPyzw=)C{9JL}=Ia`@ z)UDK-`59qd9QmVP+IA9R4cmVZ);?2AfD}uWOBBVQHUd%u1b=sEV!=#aax}#=d7WeZ zbHicbRtSxiCvkSi1nMK2JYL1cPwd2N;NmNWP=i7zUCdg*CCJGhP7@|gh8ok8PRR;| z&B4j_-^KTKMN`cWO+%xQ9XwW@$DCLG_sJhb?Dn;bOHSO_{or5Q$)({mYY6$6!dJhH zsZAC?nTcA8FQoctkVPeT$Mt%bK&EV*Ur0@&np(d5UA0h9~0F`?+i;WLXOft zXL8S*XPCsrHK%4|vV?HLxZZN;yo}#i>KPqj&LvoRH-b6`4zRz^SGzyqal{wTb#=B? z(=*K;4Q}N6KuR}cm(mvp9MjjH#AH47PfAC!5jlR{S5&KI#n!)HMi((d9Wt$efns?8 zo*&Yee3K>%17PRLb9wXC)@Pn8YQo6J}xhU1p23tj7BcDhxgpN77UJ+c)o*M;vdxYP_T1GFM=Z;6;h7wcLTG zUKLSQi`T~Ua54+YEmY^QJEOCk5w(#+q_3r~`AW9F;k$s@-tEzy1(4c#Zb7@SV}#n7 z-`V&~I?A33Ow;OB=Sw>8CqNnUSzNqQLHk0H5XMem5)?hctwbrN$*WEuzARtvgg8Ww zxU8kzZrV-{(WJu^4ZpUi&22ASa0yr!`G)J+?$XwOn?x3Rgqw!vt}MA_ya6wr8K*v~ zAf9_J`G*au&56`T&!poc%9Z5eW@n-3>t&x6O}(s(0&5tk!OYRc`ue_PmR=G1z@F0s zv1zKbThxp+I}a?p0}938 zPsQqaYnDYaOifn4ApW?UMw_I4T!Bq|grCI3`W5V0@Gepo($tuE_@b!rtJ&}xQLiaA zS^~ao{X1mzxeaKy#m&bU9!G@j>AvPXA5>6qpdruTm_WfL0T>Ua%LBYV3xpUD{@JY( zASide=|XT9vIGo8HVG-@gpG4QE&RYxJ|L> zofmoScx{mfj1c=RmY<{rGph|^`fHXv$~t}`vG-&J!R8C4cHL)W2i0|R&q8t=w-irU#QPl zChu~UyHdgPpZSa{NqTGyoRtyouBsA7YMfX7)zq=sck}lbDbqhQFj)f+&!lYd|CNxq z+7YD2Pc5M1>9L43Gx(p(X)mLPtiXpq9xL7IQ+42K2d+u2$H50p17x0m!SQzJjy>WO zmw~NsM$>NAec#`?MLVTVbs(%}(sFOtY~0Tpz8b}~v;g#d^Wy|73hB&Iz0#74!Apik_@%1tN;K!vpD4!7YiL)u$5nE5j>zwbPrM|v6w6lOW=ILYSxkm zP>t7Ty!zR{ADNmS5Q#oY`eCoL@_VKiD^=L-cC1&ulpT!o^bLo*AG|H*7OAu-G5*&k@2+^Y@P zsbwwzIj}MDU8-uVmnMqS1lrN%UZhB^Db)sYN_@C zCqLl<@kw7b8&(QfFa%%}yh)H%LdzfHWvMdD8qWqukGfkqq~{YV|0%1wW#aOI&d+CM z#Es0fU+i76q(rSME}U&0YWLk=hyB+#3nA(UNP z=f5Kc1>O{-X-rV}nUFcSGv5cvYjs3_eDyBXnJWf<7BF%l=lVrzU73K9xVTBQ%84%l zFbY`pEbh$$1W(QpgN}|SC;MI@4%9EEmVyx!v$8>Y8o%_RBm^mf5EsE~Po1-9TzcVy zO9=QYA4yX|zxuy8p%Mx*D!CRJ4mHqBtI6snWUY8I&|&oLKxWkd{+@(FensCrfpQ`+ zqjh+#i^?7h`J!vXxlBkiAVzOiW6;}*Lu++an55;5P3u30or6ZKDHs%wdQXJMP{&W?dmJ0f1PO!*SN9qIsP9HFF^6qrEW5cbWsv#Y;e6zH9mwSY&XYt9(@xugE)%gO670R ziHWQ)8R4)a`wBb@KelyIH#ISXmkp1GMAX$MF!Ag79flh-?U%-39~@l}E4r)Op3bGo zQ=aqde|odRxsBC_P2#XEzcKA) zg~RuezVCOXp*ud`tcWKnK89Lr*S#t;+e{95bdke z^m4T&=e4|tmO!3CeJmyoJM{*ybaYhKuIRGp>nh<6P1luPTn+{0F9EEMHxkWG{?jqa zoeYz5OtFu(~d_rkY9UXs?B>Ze8eOtv%UU;>QQON>CmQ9cw z;0TYH0MjE3+#avj$_8`b37(an7YcPoQ@A+RVtYlknmwX_!fm87^99Cy4|vh%}T^R9%dU$rqeb8f=0dH&I;qNejl z8b6oIY60aOD_GqSK;gw6ce6A6a_DgG^(xiV(AUq2MAMZ8c=w908)AeNkdmx@5}bXddA$CZoxwZu(` ztPnVJ-6&X_c0w&^!reFvjK$P+=eu^xnA>>6?c%V)R+~a;<+EZa^XXbQ0c@9twl~?| z`K&YXI}^|4`e0Nc2rKwc^7aD8RXKvu|c^Z@NmuC3|v5v)Es zoOGeAN&i|v(=#KZ9;$ExougclNHtv8VnG&0K7nosU(0@G=yf-jj``E^(V62a?UmS* zFojPi(~N|}sFK)3MBdn5(ZyN+k1&A|T(aA6^3d``7d1_zk6zy>Lyso~`>Y#MM2tauhd&9)(p!ZL%-Hk&8`Hy?1|%l%7Fb;UlpMa`qLv-J zr^M)pt|hbOF6WWW>tw^6tXmOSiI0YZ)7etb3qrf*Wl!GrXnn%)9;H`1ItfQi)UCtWu9wl%~q9j0ifX4&GwRoh0V|E6N8&r$J(Lzpe-HkatS zUB^d^dS$ty&tPkFH^s@g^58z(ooufh)RLZrX?DJ>_S%`KZL&M-bwL{4V-{{~tY&bS z+t%zdF=zczDwwAiqMF=IilH_%D`XA|My<;(^jv|aZP2J~^%%ez3h;W-jaN%P@u~mK zk&pHI$Hg2W3dYK=9Q%WlnlUuz1CV0l8}ssk{cc%`(dafpYk0qwA>ZzK{7qL|oWaLR zE~7rY|NMMn(P{Ok?s!a{8(uXhiz`$+QktgPq)7z!o)))v$%SDuaGT3N7Hr!uKl3(8NMmNlQIa-!^SOl%DV!@MSs@%zbX-z* zwR38;p)Z2L6;oQ6DL!4b-E5H-K7hC8F$bUjYqTP0-@d8(`ZG_f5=ox`RhN;NtURz2 z?ga|K+M6Q>%og~DF4~8=&C+9iMiwO(K4W6)-P{cqNWDAXL{&@PC>;5G^}e1n2UT>AXb z>j#$QPzhLl^_MZhbmeTY1`^t1M;zXqQpdmO{q0lSXX3#*FFK(hZz%hWp%%`pvO`Q? zn@^Vfs2u#LmJ%GldUK4;aHx>iUhU8(>bSWZcu^SohG&(HH=I8W`d3zE24DRl$i`DM z;AfQ%C(5T8Yp?`Iz7qZE&2paihDRf0L#}kT2scLp7*#Sq%yyqdu2}oF5wzL;3V8qc zp1;1IAP@GN+2kr1HjtY@&f-as|LXkY+a_D}^c_m}s$!O*?GN)2bgx~7f+`zE`niNV zH1n=C)zY-XQ2r1ECc)=CFSmI4SdhmBUG34oo4gKzdGeO<_w#S6c>DhHs7SPK@q+|F zJvTpdcvprXoFYqTfb&N@Rd|0n(tcR`6UHrrh{zy4LZF&#T{9^QcxzS7F~w`TeG|0E z^gKasuJS*Vq2p=T8Y8&qocM4QLszL!`KVWKi`!WAlFM8N3_3pHn|yw4!9grf z8LhXG$HlL*o=oLMJ}SuHY5<$bJrGa90DU5U(s+B`u-&bhmdgf^RL86k9W5XjTs2jM5ZhYuk2mJQ5V~4rmt@I*1t4Ju$i-Dcql5rGV^^asIvN-(SsV-t$_i56a9BJE9Dim zP#s{Z6TTgKmER5VJuF@Af{7oMqqyl#XWV?WSK@%gGC4MRy?S3ACi=*j&hE~xQF|&r zVj0Fr??2Cj(7wJd{2R&jqGL`hpIyjp(ZuwOtZ}T+8F%9+rtZueC=Zj@MqWyKvLO@F zo*!m{D;M{sa9NS)_hUR6GwZk!lDfTW=2Pt4ISE;CXI3y~;NI!zhh!1p;0a0EoGF-C z!z$*$W}sfZ(r=>Yd8^**0Jv3hvmvn8*@{6wF9J=|DaPB0CQkJU5PFj*TZ%|8+fpVk ztAP64elUU?;4|&{Lp4e7-s2|EXY!EKE$O_tM+I_mU)ZXr#LV-#OCcNxRJ!2*QO*$< zGQ!A+Ll*jktpSYRJ^8T$=ju7Z!8;@!5HLdO2NsqF+jm?`woadeT=4XPwnhZa@b| z^^V-N$P4cThqMgG!w3+9t~WS2nbgVU6#2tA4fk}ukSDBcdxT}~J%@VXpLqfPUW*?# zB;96wO@$n|j+#$~VGXNrHb7%eW9Uo+ygB7=()EZ;QP$io#;?Dxt(NuSe?{iR3ICuH z5CeE5*CW|kyz`g{t}^3i!}rI%UG_fp=Srtb%1(k>K!CsAGEG^JbbP)hzTv9)!kNj- zMer1!9-hokZZ-`(Q}bI=;Gba)ze}S;$-J+0uGxYq^>ZDfFdBLDNV#cY*lqQ+vv%78 zy!!TwlLpjhqu(z$HW-W$eMNC>6R#}9}&>H8{pGQ6e>QDDieLvdYa&YF)z-2NP3 zdvG@CPmcYhN0?!9Y-H|$_)8c)Jsd`UW;k_2b)d;k>AB$2kQO)$u|=q<-m{47wB(XI z$5In3i}bbNOo0yf&!|37n;U*NqEg<=_ai|^oo3rBlzdAINP3kiI!kZ4td|xMPugi$ zE*&}Chizh=WPR#$oiX+a9?0w&%<;Q7H%U_C_do4sPlo5Im~+g(61&wlN3MDVuQbYK zfLAijX2xH(g&uiYYB2Ml;74!M{-d8hxIO$xcVRE*r9a|1J$hp{##Q{6zJ_imaKFa% zy9^IO9GC&3)JJ;tPZpz9Vu4}C1)^uzEALCQcz&G0&fZWlHqh#UeZ5Z9#mqtdPm-Ib zBFx%DY(pOpy3VHESVrHaM_>sk=6tDKlWu-<&({ojw_ZI~B{$s)d6<_! zSbP>D0>j$?1$jHN2Q>MQBt@MOZc@6y@cazF3`c*4(Q5Ho&$&#ZF1jRVl<2)ZeN$}N z<*kJur5*JRo(F`LJ|C z!H5H84o`*Mo6e>TQu+>tL@ZVdqGlAXk7l^Jk5K{y3a%2&Bi$`SHIbKad%wh~@_B8y zZ}jvk7MEZuHz#G(O5!gDl+z-<;t6q7JUC?Y$2#tn;a8&mJq5E){dn3Z>p`!`K_LGF zm!g^;T<*cs;bA7*PSV$(uGO>d;|B95CYmzP?kSwDZue8>R67XVFI2;cQonoKxR#TnElaR{i0E~2+U~%pA2xgS9SkNy8VeRwpcG| zO=z^BIA503%zp_({J+KFMc>r}rGGHhb(tY&J^qvVyZW~1tNiz~I3Bp6t#`5}nZSR$gl_ofi52-FXv(;bhtcXlD#21( z*8(diO_pFZ0UK+%TINIw&);IoVzdq4SwUE<{$2(H=5p2Ve|x{B(~;(g&7HuFew_7v zM7rNonKh0_`?Q^~L;QcJqXt=h|Edz2h`iNOn2Lu5AdoLP@Fz;Z4&FyROwLd>H{9gq zgj}ChYXPdWf(6h?lU9IhQN1q>2N>CjqPKXi5t_w0qd zcyJgyCJK47S(+929xWd}+Ox7bY59{q>IqC`Y7)6kRLOrbC7%}J_8wzxyRC>nE&kIY zdL3n14I_Fl>wrF(#oq5%F0C6`-xRv{DYJwhM~n6oEWo_A`hQ0P*g4QMzo1~9B!WZY z1&>04lzOSp@MjEUd3ZelhE0)bR(5M1YenRMC~;7^pZ5H5@K#dIOiXriC2%gSbCWioI&R>>Ln907K$5WOwoxp8vV=yV19*q6=Wh^IBeG+CezR%^ z$Wp;bF(~e0O08sP;qhIfEQzGi5E4#^GJd7|i=l+z5oLf{+W`W6q6&i>dtYe+#WQN3 zCa4Auah!M{B2AR~<@cS~QGaY{a}f$Uves`;`g|{Jr-IzaWAv2sPIc`<@e=oot-_*t zaJr1jiL^K@b?aUua`$&I8NBKVlWJ3Q51$t77hG#zv<8jV8q~pG-kL;fp?B-^K(hf5 z@tsraCi*y3tzYJD#F08KkggrBZoHWR0rBgUpRFl2fGu%*`y?AV^y{&{hJ6I&bY7KW z;bpgjVv-?m!5+fwo(z_;r@LsZSD>HO3E*#Bf*pnSXKH@M$)nfY|6viX0mo*%lRnH- zl^4Hg-|0q#fk5N32I>($66mpCU}p9f2?1V>>^{!GWU%qG@X+3|V)34=aFDb&_rZ)3 zU00&U=%$V_dfiPbP6W3^{B~uz?IrQorz>8Z3+-S}yaOixra1g`5Y0Y#$u}mou}tc| z4QN5=ja80+E-uD(#?b!rK(mzdGkmngSLN-Sw2P-i894lk9+zhRwovI&hyU%UCVX>AT%BneP)ambc5~KQ_1rL0X@=h>>mP?<3BjP}lvVp@fz3yK z$s&juAV_!veLWaW0SUI1>df`2p&mBrDu3J z%ROw}mIU*FK2*D=gSwYh{Xqy&1IdKK@}g^+RuqB@8w!!`ko$S@oS*;hHKCaEf!T67 z-uTb|Wd5=_1oM|3^B1j2m9Ebwo<+VC<7&m#qQf$e!kz@}q#xwLMI^^du@6mRB6LAK zhYbUI;VXRV+xk;`+^g)Hf>!{cz%mJD@=ub|aF+w}V7Dc4O#C8kJVD52wc zz#TaRTF2$JS|E{4jzr#6unF}gR<#u?u@}HM=&>RZmHhXcBMLj? z0`}?51&Gjqa8>K%QESZPgU8t-_HB@)MS(THTL8N&)b;*!2WwYU+4aRrxKI6s1^ac* z!G*4`qM@eu2^$Qp6ZVxPCe4?={-b;*)gsXl;_%gWBHBua6mHx+>&GE-WE9# z1Oc4|EkP}ujyZQ3ePBR}(=^18@y@K1iPb_3kiXBqU7S`ZqVMNK0gIdneXQ(;TH4LS zSR)|!;?Z)`?G=-eo*s4liM35;rRw+9&P%RVJ^ubl$b34+H;`UeW>YjPOYn`Oc5~GVg&Wr9 z3)>^AyN>^=RZjae*^-};&W4c*e634H+pMn?oim#B|AcWE%$vr9EAVH{?X+sC_*YU- zCtF3jb(Z~Sj+D!35xN`0HMI5_d~~PQTVyD%$M}4%JfXH*-#5aLNjmq+f1tVNNKuj> ztY|*RW&Lh^(aQXvtB9j+S+hQ0WedsM(vlJ`1}es!rQ<^+gfaB=WkKQ>kM5id$7pbl zkN5{XiQ#TTOoP0FKn80Qpg@~DJ+;=J8)T#hj97HEkPPPKZO5+~{heBzuoMQyFJA46 zAbFC00fLEL4iusMr9k{$D;6J{jR$o#9KydZz!WWt;QX?O@QUM)igytxpT4@l)qxWC z;&-7SNuUbC13dsl^efa(6T3pY{v9@I?Ea_L(1-|Qcdphee)V$!r4;0|l9dNpR}=jCN}$WNjW ztpo^$jd*heqcZB>*GC^)&x)uJuD#xYKqL_hANvT2uq3Ix`{d#YZAUjq08%{ZJ@n&b z6WqrB!$d>GaTDSVM(iIkl`FK5U&@m*+)z;Oq-Epj(tjMz$c7P0eAf3&&1kHab2!og zMa>#EIt#4Wd$w=cmRI#xD5X#{4%?2DDyWvId7eo-m1I;aL`erN+{69)j1J+Jb|pKa z0^ZXoj-;!a+86d&jMQ{V49vu0!Lkl?_Or4ALKWE7V@t9!~pD20aHdUsC>G2m2ycm$l+AIuo#MZ^18I$eyaKJ(DnRI1^m?Va^^ z3O><&)Mj&DIcI%DVIbmnq5a)NMPCge(QC3>-t=ycYwPk2mX=-uw0Bi$$XzeD(GO;Y zo@U}}%gXV&S*SmF@UqoQ-0cgyrTi|O^7(@UVe1N-28@1Oe&BqN?!aK95_%qQF4 zv_61mn4@z5)FXqL@}>CULe0rkQ~;k2Oq2LuhRgr}8S;2G^#zIy0)7Lg38gg#@FI?{ z7k19JQI{;JrHrp0!Fs~H_ackX(R1{4Mih2`DC{Y+NM8=ag{uoWklHifznF+H=^3K- zSmdT=#s~VF$mJ!aq{Bwp6hJ^>zW=T#hrV2Wlr%mvz;krr!MzCgg-T8fYbCW$FlPw+ z*P{_WukHy(t35prY*H>K4Mn2L{t{NvnrF2BuzuUbCNAKQp!cxpyu3u4P=8t;oFzm* zk1oBJm}|I~adVc|PtxOKQut-|>Y4n%bz6LnLdJN=*<|UfqqkaW`oe2@irP)|dBF3) zqgKx(ei(1Nhq~F6bD7)SJe@z=pkHse3f(P;W9+f{OFT4%m+tGKP>dvWGtu^?&f^(> zzdaolY!3CwV#5d{gqQJ}+XM>fI|-^hE{sv|NhQOqwe#2;J_pcZTfEEiW|FsFj6XtE zi?MG{P3a?(#sgJLTnwJEo7ZQb`Q=z|bb67Sa9j@6vaClfJsh+qjlJccSDQ?`Kv#^^ z0~?5-IC{M0$x$rg*RF#hrxf!s0n;(Y$|vrp^&S}~%0rD{R7spl3=g8RTpaq2ds|Vp zvjug_L}dzsYja(e;Ap@xIw^`V+h!eir(C`b6Jw6(2!b_F1-83ox0Vc1jex#wxLKP4 z-)787zqVQLX0TPD=7JYN@aO~Q@={`--4ttlhfn^B8x=RN?zWz|VpzUK43czp|Sr!94t~pKP9Sbqe!z_PrnMgHHsP zv0Wq8J*!$dB`pyHK}x6@V$!|8R*%)w77db!FhCXepAfdpf3HY&Jd&C`PE+nnN)l%q zsn3%Z?453=zVPz8l4m$sw&kyt!pr++fd5&XS6@^fHC$nz2F&u@~X2`FqK2bou- zbM-SP_u0Q+E(o`*JAXwccozJ!I#6=aSB)B0iOI;ZMPwsq-tckTrf2pVR!h-ULusS7ZZLpFK>-%am~%V|Gg%*H6;V& z_#Dc4i83~R`A|y+p;#n^u9|+2uMlVWS}J1ZbcIMGq1CSzxytW0qU|oKM)z;(zwA zI4z_an%wohjjyUE$hOpD943v;&N(W7NImQycxmd`e=<1{-CN4yu5C4L`Xw-IZ85D^ zEe@a&DtV@XX78~VM$e*A1Scz)*n>S4b}n2rG)H_skVD>Nwd3ce!uw;W=Yv^+wu%vj z7(`T@hQ?njd4s=I2iNt8rGTR>s2LH(ES?}2m z<1$H+b1>~JQHyDmw{%!$e*9gjxs)lsu0`JW`o>D$HJq3pq1R2A_aZlNSALXF8kgqe znb=@Zi_0kI8&UJdrL-QmVk>lx#S`x4q%HWm_5nl6nQ&48Nrwkyr>Tgm*6rr~BbmmE z0h{Ac2uy4h;b8is1m7wSG}5H6J$}xfXe@A0dl+`2-Wngy)NIU={;?zoAC8b~l2LzA z4_CzX;*pb(S9qD1cl$N%FP{%F>JcC0!RQV5Pn`>Qv?43@J;qtJh*{>0U0Vj?hFww% z^+O}z<3*bVc?Io@e$I9W3}Jx;ssJ)U^dcD!78&=fp22N+W-f&(XU+RVnPN_f)VE+$ z(=yfVroM^Rlos5nHoeza=}u83!&W~bAaEe^Pj*}t(?vj(^)kVX{uk^KS>u?-c z6`@&a@1suh88VPNTtawI=!v2G@w?qxeHy(&EupR>c*Cj1*Sq$}wL4{oAepdsVb=`z zl+Vdu(!wTxL@;Deb^Q4NQsnin8LcKsX_kEwVt^Z7m&phNGV{=@gpUDwlrM4giK|`WK0>qViM2AFo0fN? zTtq}+Z=>#(rGnuF?GF8|scp^U9Jo3i|A5!~h6w#wOYY)f<~(=J?_P{Q(R6cn(gjgv zw9c}YzU~eE;joC?^;Y%P0;^6B*%o3{O3Q5IRm~;EUkg0*bSVJKWvrpR+x}$1)lU<3 zbR>uM(c?j%*y&foaY4>UNln=tl!*`j0j%V`VX1ucOFrwev3nY;=s7u#C{O%PqIbR7 z;;~}}IbP9~GoT59U~Q@tEi8JyJzK5CHenR_`=7u^KPI0G&l|eg>UO#6Wj*#LBnK3e zsaVIR*e63DyV1$C4;~0|_w}(C)3p}^ILE%w6|#8eIEd^YJu@Xo-yI+-FAlk{_jN(& zbNb5=a9#Stm-1Xj4)71Sjv>g6z?j(TLP5zkonEi}h!hniJ5l*hX1K}u;;}Ee@iW#T zN;jj!EC%Ff0_X)ekMCK)64r_0k*^}!ACk139eWfX3AE4o%N~*YS}PwK+kueeHHqjJS_rwQ=&nAi8(Gq< z{pH`!JZMuc{*{1PzBaRteh}h_@&RDR5Umd<@E=;uw=vhkB&_dS4N9^2`z(Xw%Q41T zVye%Ioxs-(*V6$Y)OTV;PXU0}0+|_f8LLe9h_YToGJqzPn=_ZTq7*78tf<#nFigR~ zbT0R_c+owAhcLUf{vh2GH~ykjcrppBY)p4o&&@d(dqC)^$9bp%FqTt;`SJl4;XfJW z*E`e@q|AQa^a3!bR+y4#9Usf!to1bJ|8&Y~T4`dXBQb@~x>z*Q#~4s0^wYcg|EIiO z!nt{@k69R8lz602TPlJ6^%MqZP!P@?A$?q<< zQwYq5Ry*B3^AB2p82J~TN|KDQS|78AG zvuu$nS%``!8HB4gGQ54>r-07dWxH^R#i^PVQ~+QSEpO7MfYkC<4p3M?csKq<66^cl z5R1ood58a#`HKF3462CVW~6__E5Ss$eX6w^b?&4npi;+;T0BYze0Dst9;|=7)e!fU zcVC}?D--;5IY!};k2@AU2atjFY1ot;z){Vt+a3x~^r9e>42&$FTav7M4AfHtHk-z1 z`84v|K71xilP5g@+{uYhaSI@km%p|iQo>t^4K&82TdlWj7Ovga%4!)e31>+w6_XlS z;w4p%Q_mZsCq(82;~h}apC|v|oz%5NWVP$Rq@Y%Sq4d6@2K9aE5zaRNwjlX?mb7a!|1pMKUBp@ga2E)ogSwzvCd7**LuXySJrE&Cy;c{H%u+$^W{oy}~nNrR# zbG!fY`c%s-1!t}4R}JwDIm}P8bGD?pYD(o6T!ay`K9P`bQ&DS1nk!CWkgKBrmzdMf zR>Y0ow`rzXYU#(l2F0%|AX6i!nP6rGifArG4_b+0CBx(gY|eHbI_kD0<^}V_F@7-v z$w7R5!zvGM{Cm#+{U+;ciN6;K_(K}mH-LJg%LF_iYXUj={2k#wv(L6KSvss%;xMx# zVqW^&3BMcE#{m#Pkn#W-uV1jy-*(hI#2HR)GFhEg9Bd!B*j~2{GXpx{?zdr8jZK=L z$Va%LH6wrx%~c7w0QW`(*VO+(P7x$Jzic>e(E(9hJ$T)sE15N3A4+eJbs?W?&?&6) z{Giv+2=|E2n$wA$SIgaq?7D*LR)63T0fObxXKQmzFR@mxd7c)7O>k6Jhz=@aiEW}{ zcyq9%G3H(otOvyJNR-3DH$B*{Bk1Sw>$P=dA`12~0+Y|uk#1kg4L$X|`hx=SOtd!t z_+h~5_NCrS;k!l883LaH*qT4KBIL3HI85}v=By=Kwsx!NG13#gUp>L_Ca-@;biK40 zGSLn=Cwd@RzF>>}W8|?oI=w~S2q@|3i&yY3E-2u1#$YTRN77}tuZknj<4E_SSC|B&g)#*0~?OR??EAS_)8?mV0uFo~O)hN7; zXHC-o@|UC-9F#o*=i`lp5lJcCk1odEU+Oh-e-q?J7cT7mZ*rurlhEG*|o*(401HMTRGV(65+E zDm+`N$xW4EvO+W#K5%TK_CC3tidVZy{D$bweEQWqFuR&)AjRi`;8edc|* zU&r{SgIl(?Bw->$fy|DC0rBi;XKP2hTeKBfm=g`ON`qkA49wOHuLzg92?E}#QvZr6 zo24@5Gfl@M&@K#BMmv#TysAfDSFWHFj|Bb7IB2`8dEc2t7E|Pr5>VEC#}qd} z#k0koZVp3ldLFJC;0DTE>J<|x9a za&2Sq?>{Ic^B-W>dFhRVpi|vQ_Q2q*;t?f=eTaJQV_$!tukoFVV2mM-uUGTWCZG?ppwidZDJcTYdI{-cHNRH! z+gi~Lb zg^A7_fI+;ahT5H=Q&tjA_F=Nvke6V4PQy-mAHW2FMveAYo7RW0S(*IavUgt9`1P!P znw$3$`|sVTd)u=F1}aDg4BsG}bS>4O3W%SoTyO~1;gnfSddJ3&WYShZ03ccw82U&L z=H4{5CG?LPObFuHBAn6sb(()``kd7`D{3NIcj!naTi&oy|CC8ve)pUhD^eLbvs;)j z2bC&MSatI|O~?mdKD~zPyeWXoZKwo$)iLZFHtn!5CIRv7Zs*na(B>xX#&c&*VkM4G z<~P}MDW^N9AIFnbS9GZxDkHb1EgFjUjv;yZmvPq3GutY=g9Wy2r9hC5j-InVThV+# zM_r&8X2}GnS;U;2{GV%cCI=YRU?aF+r+@S5qS>O&&HXTEkS6D2;hsRvEMMIQ!CwMR zKJiS-^@R^pg9jBtN=2u*PuMhKKT)zO?^m(60>W%UR@PG5HXikBro9h!bB!ZLNGOXg ze9ds^O@t2Xw*MWUcGCRJkXr7@nN1V)$^u0V9jQgEDeZ(7S8V zT+53H#mx$VMvf|zR;BDR4u0l6*Zz4;EY9NV&-PHyu@i1Vt_dT_-z9OUW~8 zgnXamDpcx(I-X%r_+t_ zUT>EBY_f_DoVtTsVNMM9 zkBKOO(Im|UX`&Q<&2}FZG@~;Lqa&nws0{5PdH-Z%1()>%4&lk0ZEuq;Z|84;`8knE zCqAs29sh;s$+`7np+#{WkCveCbuNB{&d0@f>e)~_FSO!?t=RZI@f89ingx=x-Ok2 zQUS21(0M6HRy!$qVtcCde%LJK2-NGjP*JN{w{E)Do2veDsR{ZOHLNxH;E+9e$Dcu3mdMB+Lkgz=-=MR=JwLPm2S1`ohq4 zF~u=EUF3{K99|*Z0-0bRO5(PXTS26|^?&)NdT=>jRV2^h(+d?LYNvC6>|7;^QE7fV z{S|s8At2?k=-uM@Lcywk%|3(kKpG&@iNeU2L5k`A^63<)%B`YsfhqbK7(X}!C$S>I z*fhv|c_X(=|Hq%tK7&M_8jKepDQstAm2#3kpFhKrS}!vo~lJQErLcEt%^- z6m}2E@88}an)l+#iA@yl&lgOT+TIbq0O0(ZgONtrhxQPsG3rT5&*A0*JcZs~AFvlO%7L*tEoi5UDTsC0MR?CjzE*c7{O#^5RnEB1ODHq`upM?@xD%R4O^ z7dQWtial8^fc-FkL)g^(L^-^21f7u+tp%gCGX};wrQ%FmT6k7+$$X`*IaS8&8;%i1ar$u#asYaaD|r9CQVIE z&84hdGH^*vQBf()7144{0Vx&C1yD#4LFT>Z_s{!0$MO7IM;#dS<-R}H=Q>Z)Xo`fX zsk42Dl16pbT34XDipDz;TGD@bB>8hwooA_cdcCJYZm8&K)Z$eB=L+L0JjpKvNDmZ7 z<{CmZE^2C7g{03R{XlX5;o_j_T&ew#?u3UCPJ0v!1($k@n-8EfEt!j9es`Gb@uQ-G z&~9g@>|ZSY*H7SnFGnV^5i&R9*!g~De)|^o%<2E_cO4v9$5C6;oUXKLETI>pNhQ+V z`gK(-QOs<$(TxF{Cvfxh?58@LwAiSgpcKaz?NEwZ9MPAjcLmT$*6~+nFB%&*^oGIl zO#SAhDW)-9&||TzsU9fjv3O{K6bc4r?vG4BnyYD3=J~e^wH|U9m5Ze>n<|1nWL2da zq7n2bQv?VvvxXh_xQwo#*V`=5!dsf1B~Ix;8+&cw z>>8ePd)!Ug!=XOoQguJH?z3NHrTL=wcps-Jwzftz`skZq+KW*of_|OvETS9Wgxj2% z7IQ{tU^Myeqxz8EBm||t?QFN|V|GfamQEKuE-~XAC*G`jMR8{PD>?#IlB%rklkMF$ zJ$n+KL zQ$I;PUW1?mDwvt(pSRWPJ&m4WG&>cskem3+U>eFe?tLD{HfE*nn4$?A1fy~6l&B1$W*g^+0*c8> zixU*On7x0}qcA&J%*H*L-B=@>F3%ZNlq?h(&w0~{Th%Z>U;c(H)p=XTM&Di{V*;&D zeiL>YPdk}MR;4KZLtEoa2yJ&|ikm_7n=C(RSN z6yKf1%a?hCnPlpTN^ZzvP9o3riXO%$8H)jX zyDb|BG;E0m#KL~@tP6+4Ui>h7^;hhzv~T(eoYEqsTXo+bdt-gHj|ad-xoGZ>uUohN z8g|8N0^TwpK#LFg}2bUaz$*NrQajlpyS?b z{qDba>fkIxpKv?`PT{cJ!_oJ*ECivO<2;k#j32fLw*US4GV zo1W0glzO3IdJ1lbSOVLX4TzbrZ!7sS50)YjH>u*raTQ~w0u{YkOc_m67C;bZljWL? z8Il)!jkF2z6?_OYYrR-w!nZITgF|vMLcgiQ<5)a-c zdicbq009Q<;)VJ`OPwO$?zEvXzd!|;`gNn!rVd(F^561H!`Mk_-e&Sf$ zjdqJr-A3<2S8bo^6OXzdacsI_JlQAP=3@|OQH0G#suu_m8W-B&a(P&%mhd1sV*Rj5 zdIVBe5Kp=kU!1-6)@|Vr#;-NrR8~x!FRiJ72gWWBIM;fQ!QfD+{~+V`y))m>?&-ol zr9GQX%mZj`V(*vHGe;Do7M=Y0p1gRvZr{fy=d6!H!VeQeH(+C1Togr4dVMEmaLPwWXt&gPPynW?fYZ$I z+RM>z0usk03a&c?WMhdK+`_br)!G86&!!iAQ%SDt6(5r-wRQ$v`)-x>05^-f2YOc{ z#v?7qH|wA6DvQkCaV6ZqgIgD5vz z^iVwdzbIGk@#9}4VluB{IG5!Qa0sylN0b9Jr5p(Qdnyy1*QNCg-o0YrVql=dTtCdZ z!XKp8V}-)NA(rnhVg%sk+yCb0!d#Ltg`->Ux2<|JJL+3c3bw{SWFsLi2%0hkCu{#( zKjsz?J1)kJ=SM$xk{F>9&(28Ia^rCy5@RE?exuzH<+pTy0zD`>@9$m`(tA%bI1b-& z{m+5(?i*QH=(PD@+WO~6x?>jmCX*o^v8CmzvVbp3E7_Nko+~DA#s=G?YcxSBS{Zy` zX5jEz?iunH2{ea}{p7TuS-yPXh0lXXtkvpM^9bqmxUSf74|7Yrqm-H{2^(}xW zt2zMp?!w7(SBNM%~Hax%GY1)wxL8c?lqEBo@Xi{9n!47TJGgj-%7;tbbeuDO%g1`ddDx zMJzbYed@O?>B-h(?%@Rgy#V(RGFE@9z2UpW8bbL$tFs)EZ?6cr+k`pKj|_aN&%-5W z;1Z0XVAv*WWk~=&?)4lCm&w70|dJTf;z~c zQ>xQ>B5G6MHFvX-Hk#M)vv_OmkN|+9)n~xJ-e;K!I0{%agN(VQFs)SJ!W`QDyuuU6 z2DdzoWL!2C-Sug`Ql=_rI`8sJt)!wm$_PxhK9OSq*4{cM@WoK+ISA3_*SR88^+QKw6eCqMktOi<1~={|&}8=lRaokCCL<__VGmo_)l{G| zRfgD{v*wPZ64|1LI@fUf!(0hPh?7@pK3MrVcn`>Ib%9Ov@he#e@knx)Eh;xCJ$Lz) z@lO@u=&>|D#e9o>MQkDsq`hzAr{F`(4*pP#e}jZ99Ch^#HL!3$?X7N;#nqR-sOLAl zij3M56#RGUE%a?te0xF72UDcxg0;dW^2MkO%n4vTX!9N`gN{}04%XmA)VF*jJ{aGV z-q%VmGc)Muf1U@MHWu5?(bLFK#(Hu(B@2m(ujFqCB=c)a@aJ`W@=DYd@{K(nd@G;t z{$5J~>A~3DCe^o36sX&v+U&6ct6_;Y`KQH@gE}SAC&!wqVBJ@8-&mj+gVWSy>{j!s zuKa7dI=@I~&Zo78{A&7X9^_DPanvDiHx_Ezo0dKrWW?AV<0=A!sE3U8s8a9{d4z?E zE3A0d4`nsaEs#3E{ZVidzyYq^thr&K_4p$c+9u=~L#*z-6(0IAgj69hK$SIjRqhxU&{nREAmdk8b^XZRp?vQh3uyG%tV3=oQeoi&O zmtQ>v7Ft!D9fNW8=h^L)*Xu2s6?NG|#ndSM&f<~?1uO4bTad$_hS>hoUvWB;XkIY2xw zSWF`9J6R8hrZ&_{rfze6#PbGMH(%&JEpA}8+epl(Gu^gKg{B$x;qjZ?axgFq%CzC% zf{Dx5Z&C$OLXW?D`YU#E7|&_g8`z{A6@3%5C>d|X1{p>>SRvQ{M+y@aDyjh%S|ojXYJHwf5?Z!uh?%4ZJBP!^q| zwjX#6S^oYX)cE`o$=z8YGF9l-f0CIoUBy76UEFCXv3Y}d7F}NX)u_D(NC1VokF3vA zWlUd*TzgU#Q#XI~LD(j5MAiYbs`2Db0G`naf}!-n!MgT3kPHg&{M(kK=U)HH>@xI6 z1KMzI`oLXT_}6}Do)q={=EsC(`sc~}+}lJ`pS;OKw((WWpC`7w; z=rX)%Ytrp^HE12O6%*N5Z(4S~KAyaMtV{FUw6&3k4V@xvL+{tMdN#Y0VB9PBQX$i6 zEkXe@*LA8cP`9)@H{k~p(oe#zuwMSonPs#WncNb^qF;q?bJdQRIex3yy;ydq@T(PNs*5KG;;9DyGS{wed*KH zALuZ8(0)&vTIN4QCw@Hj^DnKjP)qBsL-MQS{1>R)_mXP)ORU0-#lpBTR2K&#zV@N{ zE-`Q>e{6dkEM*q`H1ddrA_%4Lg}IZraXfss(2UpxVZQMqcaP|`x<6xQo$)zk>6xyQ zf&2>s^-a3gTO#sDfrxLB!K8{Pm9Oe`}(K~_+aCJ50_Sbo7V^9&e zQCCxb{uOxXwl7KNyz$r1U}=?4&_wurf&?8YiM#BhRTLw2DFg_Tt~(_euDv>=-gtt5 zbKzN4Bh`%vyvh+p!s?OH_;7gK`n?_ z?J2itoPk0`YEC3F3x0wg8VLW}F|fh-C)9glbFax8JH(n1qd{AezylYlq#4=29tFPX z4Lgyi7N_cJF837jJp&dgmXn8wCWvnt#6OxW_4k5w!9jbR;_v1|B8Ay@fA6%~u*u7i z%R82?VxYrK&~KTp(rFKCf{i=M%MN#{fkL((6hVvm`SER4rHk>^TYj0=yi>LzYieOs z16O#n|32LI1f`fYi=S_AHS>L;I#pokPf8{dcchnI!~9xty}r&}_0u~^Z33syT1SIq z_gA%^ftdj=+H7Wcdk%VEcg?7G8=u=}%{D3bYu-t^UuRn>2_`WMUF5X%wYr5k9D0nw zk6=FNyg>Yu#)SK1fY|U$wnYC_2Kx{k23Q(NJ~N9We~v1#K0D~u8p2U|Lc}6%N3u*V zN99gqpsZ&vuBG~s_3qU-US8Y8HQaRcsECO8aO79zpq8L9ab5Vv! zV-FN2-z(z>T%QqOkmlrvm~W#-Z5W4Bs3-AY84#{Yj~k*xXf3T|2HQ{t!2#rYuSQB;9RY#Mb{`L~vE-Y%{z>cJ9rxO?x)CW=F<3UT_*`Io zbCHboHtV9M$(YQ{J90wPX7&4X!jCe@81XS6C;Lfses320zX>pgyKMevV5C&8G{;Ef zs>^d5rbm{HlpxMR^E}a?E1QT~&qdqcl=h9kaquNFkU zlg?H#21uh3!*48{)#)7E47lJa&VBw|`&+b5MNtR;ssBbs=ay=hXryufXAV7GDCddW zdhg@UvW1;ccV9Yy1)>`1dlwyc_kHfEK0%e3kMnLusYP7%K5sZikhdRLdI{leMJmPY zcya2@ZI8=XrjBukE+sv?nAW&DoBYB->D6sFjXtw-q*EjNWqn-^Bh=fS1|T>%Js9l! zVU`}iXyo=wkDJVACzX4wf?&9LJs5^X-;?k&EGuwN4SPx;N?sc zZ_IlHAkQEgf0!sLuNJ6vM6hJ@tWbF^t+dz&G)WL$xHrI{wqcn<%ARW6YJIO9;W?0U zGu318DXbn7=qWmYyXIeyz+7JvCUxL+T zMfNs-**>jWPpR+;j>v8<3>pPG!`@iQ!TcE{1VYKKa}sb{Y#Oa zf1<@Ff$TUiZ*A~n6i3{~+m+OB7vwc0(Ik$IGq2|F!NBrRdJ;q6FgVq>`c2t<8qaV% zu@=|o?tT7WnL|oo9oY0uu)g2V<8`?M|H{~Z?P12TMJ9>~r-V;R#unMAiAG(<&)M1P zR;}>k?ZvnrJm^+M%KeCAX9f?R@Wb91gR7WH3YD8U`7U(T8r?NN>GopsAW=%{~C5uQ_nDq?ti*7adgH zO9Yow1h@pO*H1Z3=Fkf=`V4`D>Z4t^W-M||UuL|UsGhW#Fs@ZsKu)LfBYWoyN6mX! z%>|J)wZN&PS-B6qz((#OQ87z9`@ydO%yJAROGHdnjVX3BYKPq!#) zaM=FwT_N#g98bB#NGq4Ro0ctW(WS-Ivz7jsc{5ZZ);gTS)0)>rAZVU!`i{QeyG;i# zCQZ{jL%$FZU|Gri!SeG6(uw&qd-9E%8sX7UUphpy3wJjnvsGX}Ccw8>(2D(kYgO{J zD11?`7Jiy2QoBC>i@K=6*rE4CLl_LHJ!C%yiNejmaM@VjyZRs>zWnT9zJp&w-g)j+ zXM-j#`rB@mAoN$Y#PO-Otq(4 z9g`9x5ME34QY=rYaUcl(#B-vyyD7&hui0v<10W|x%Q2qwCu=mi<=>sd)3Ce~M}_Kl zHSi@7`j=}txB@O`UJ#`;Pdvn)Hd1hx4CWDUHARr#R60fCTX?XH8X}7(1O-&t-6=Yw zPZ1cXcGGy%H@|A!MVSXK&($7;XjF+W8FvXk^jJDNm9`W2B)QtsB<`sVFOT#p1{hMJ z__G+FTsVi>)p%olvG7Z9^t<*inutJo!>LN4z33UoP)1z(rv&)Op>C*_miTTH9<(j^ zAEjI9&FP1r?iIhG9P2uCUQ3JFzC>z6W#w3k0}iH=D8csx`qfkZ1Kf^mPP!r2}^$gWUw0VY|*c|(fYxnjIgbK+4i;?sWaLy;K&Q
    zKA=Ltz;2>c;A8 zjkC%>WgH9$HVW!2pVlUft}tD-aLDm=i|d8-I0t|s#Y|Z}Y&=*|$wr{^MlU4{kuWb# z+sRE@?~DZAju}T9urV=vMRuxB?#Lt=2Iklg2Z3i&G$DYSwpZ>gSN6~$_+&bl=NJVu^XsxD}wO-UDO+j4zpzDr*Do>H?YA^NoX(HYEHuuW3tk*QtC{+$! z1p&&7xp+wYhAX<_F-?I5Yv=mpqE-~Qj@|vM5gPTC+5|mA|B^ImwPNbw*v;A3DX)j| z9v}$txuyeq>kp5i{-W3`+&1OP^>y~owHI4q6yir*I#sIaG>(iHZbD)=LYaM(q=C0H?#ZTP6QLAv4=Bb+O} z=6<1JiI%PG$c&o}X_}o4y>dz(E|5Rd=Bx4FOwBdn^A?Xhxjtj1?Q;8Ysn0mj+ieaf zf*wOE&qhJMvRzMpsqF)V`YQ*0tFJg(J7qeVJ}?Fj%$i$*-;MuPN{G!rmgo_gX#@A` zW}vd2u02TzQh1lybbQ)m)<<_P^*$H0jasm`c+Pn__G?e+c;oPoqn8Scuulm&Nsg3* zaWtMW%$`!zvvS_9Vaiss<{Eo9)0@!uCGPb^@%KxKJ_kI?cm{ridPu_1l^xsLN|vSb zhK-XK{ARes<#Ec3ZRyJT?*b1;0jeYGrubZ%rF1pH;U!(6ASwU>*a<{NwSuu_NcDHW zx{G}zC`R+z#qA*~K#!`G!W1)&)WVWze9$gNRx5jc{mE+DT>$$_A-tcttO1qMhSuYA))jM}c3;+9N`J&%{{@;n=Ld)+*t^W8T)M0^L`wi`2 zTL&v!sjSyn!2N$^W-or}Vz&D3m8N)n&fibzd+}GuJSgrHSV%NB{S}AfZZf9W zIksZZ_hT~3MUxW5srD6>gF;-To$9tMbF8hH>@n*3YGn=x-*LS=R@^pYiojnE{q~W)e!$M> zyIAqWf0T&uqW3&5@aetWDy&FX2Ey|1bO|4n=)!K~UD z7KqjfKwf?x*M4v17K6W;k(LlXO=4dyu%`(mqaUQhL2m&~*8Mwh%>O+0|02ew|9ZD= z=TJBe_xaV}rr2Yw!QZ{slZE1Is(uLa{FrZ+Egri%1Cr!nT78o!JFwfgyWe^W|F2B4 zPl5WRl|NJzI2QKL3}bU?_!_u>_>ecp-s%`Antqv^N=bP{(Sv1 z(E1(*;nOO>yiW7{n`o5^C>EM8$VTSK2?%c2we0iZhgnq#X3zcfPtw{O7Gz0?H)dQU zcGb4B!Pcb$PvCC``GzV8(^a%pb$tc6nfH}~y=#Ff%|?@MQTx@+-(|S_&v36n+u+oT zdc?#8st~X41=;0twQ^uaV%Rl!jue=A*_WN)1n&{u`NbANP2b#}#T5V;$mXb+iOzH^ z_^}@*PbIAfk-D24#6|0?m#K@F{S}@8j4uzr-R=))u9!LX)=$Axj&b=~J$Wq%CIa2E z?(!{8Q(_YM*#cv>ibv?r{*{?nl&;DcPuoCy0MZjDf3F}M^qd0_mqMp*&q%jzPCnY~ z8hyDfHNHXQ$^D{kklt!Pv@JwJcd0|pth@au>HBR~)JOy07BizNxvdc-B=h?lqW1G= zuUs_~m_FI%TMD4i6y3g&r8@l$?GuIA#cJ>ZV2PX4-zsIygG70|`1M*@d&ou?$Rz)E zNo7&NRHm)cI4h`}3tu~Jf!O76dmR*tFm6<=Ry{xJZSn6-kV8w0(xc-;MSmVgEn)QH zD+na^M(j8>mi4i1q%827uPTQ@WT9@@nO4VX#wuIgu0QI&BUfAoY{wAf<{p*fJq7>D z{M06I1|?SZ`?LT#%UhNgwfG2!t5Fv-nX$`QA7O4pK$X76-!|_xY7wG>bqwf$ zmURS+`?p=+fKapPxSXKz!s9S&2z8VB+--T$*+F^!V6iCVnSVD>9Lc2l)7~QxOm5N* z%Wk8CSq{k4w376k$ws)(hmnfTEHtshz#k^I3o7w=p(tce`N+O2_zPZRJ7)JuK!(6m6Z=qpCw0DY2Go0 z|7P=7IaFjZ=EO6IDFCR?ONyzpoZktTo z4(zMCjI0<0@r$wb)?}IbU$tsPsHR*LlzvYl4t@5-k2}Ap=bz*r*&LjP-RZXgUxp?|7S0Ly!)ON#UQ*%KKhJF? zm{xWHy=>w*OLV;$Yxls3*jRMQJV2B|W)=I(MMytS-_@>Mu~*uSy}hBM@YCqf=*~pw ztyHNuDOuSvRlBbxwBm~v@%K%(_oArUR?UEkrkB69eLj|#F@s>n zaXFLLQ;Pepd25JH_CL2yxsxl304=&Ek)LPGJ}lIIrvY|Hau$1XQ1#S=Af6e6+c$D` zYy3yGI1K87sLf$3WRp+7=T_W!V7|?#uZA=Ec*5?QYHB^ z^eVe0eKkWre-53V9^&hVbxx?oXa0+A|gsPaX<+L4@z zs8ldls~};$nJp^M=48)N$516w%#tc3dBPMi&+36mk;_WpVeAw-7u*YuF%s6MUpeQR&v4M%F3NJoOe zu8#xTGrXBIJAxK&4eC$~R-y7aeGt}AK`7Pm+1E-iO_~BK!so%H0dM@&?RXmWfo|J* zXzH)d~FRp@o^ ztmS5HzVRmEWI68l6zpa@I%>J%zSNCd zggJ!1hDXxsJ>S?#HJCzGtW_ZS2p?QXaxVLCZak?YzO%j zT`m<}PT3{ENX`&tO#ai?{uJram5~QcLb@g2TNRIfW5d5JtLH2QT-# z*OA~#p2{zO7Q6gC*;8Am!@5zK4ev&pl$|SEur{U5en&SyWUO`z@LM?S^Za67hC*=s z)Q#`ly+>Z#?$<|ogN$jKWWA>&IoO_fSi!x4b)Vx@gsGuAf-)sv7W0}&9gUGh8*cx* zAk*P6Mv)Y7yg?r92tZkc}MEj&|B&5qvJN7h;IBOLfzyD}WLn<^~E zb*2~<<{vB1(_@g<& z=~)rvX9aCARMDLu26WdjhVc?uZ>w=?Wh7u+_iJIi0K>=BhgromP+q*&)#ep5)lX{k zM->Tpo$6Iy{UJ!c-6yx`i?&;=O#=i@e-DnO$@VsgDIL-jrpdPPccje$I1ttpY$vm=uQFa z&ohJ5KlJx#bR4k%2+g+>NGKnXEosb;EWi#n_mg5n z&9K?}`ITttcwG`2T!dhxAtiUj5h>MdGs2H((7fhj!ekedwrjOJ)m!=j$X=WgM-nN z;_e5$^MT6=MUg2#XnE+Las4`Nzk5djkpaLP2rUD`o?NE zu~C&i`0Qj0sBle-5-VA7naPjis)c0o)r=avNYrLK^rU&Qx zY%0{aD6dU;mM)))Qud5b0A&NO;)ve0H~Zmd4^wuL49hEu+23hua~b1r4%T$ZTP~Mj z;=!pGb>iNW1bkreUSt}T6oG{LuYU7OPT-54^w)5qmvwKGb^n#Q@%~ZXHhjTv-VNc^ zO+P&53vFBYSm|d(n^q)@!AvC343LP@kB8`WG^dx+$amEDy zOGz?ExrdQa;=|h^?rw{jzuFP`F6ox=>Y>Rd80x#+j>j9WM4$PK1D^0M@CSJTGJe%Y zzvk|&HM~dyQBrVxAI&ySNR@GnDpw!%rYPuG!ChKT&Z&hJj-c_wSboA#OtLKI*4kXA z{^^JfSJ)cDD5cy!JFlS*$)}l861WBqY=f9v!@vnsOUN}*td=_hM%xG)vPWtQ76gb$ zM)%Q;ovlXYnKsd2)_AV3@+srqz46C$rTb{?k5%gFvHU(V?%s#_!J(3tCkUcw4SBT! zpmV>?9o@*!lRaSSD^PQByUp88)!6)8eB!S-b_vn7(XAgLm|=g<#)L;OP2SKUykZ-F zsVq5sh$s0mDaz3n_qVyFoect68oFJ=JpLBjq-rspOUXZS z)c`WsG#ZU)GTF-Fo!NH-euqYJBt_J_C51>{#?u3ar|`Yfhx)%19dE#f6ibR9uk{+m zI;3{32Ed`WesrSK2PYc!vlR{eAS>vX+k4t>VzMI6x3~Qe#ue5I z%Q-V*n*!@)Gp_g7C{g-cp-U~kC#4nY$wG*1DatKjh0v5A((avy{r$zgd>-BG54%_y zMB7M4o==38ceW==ta@}LlsJJg*C*IYkRrF8W`$v6Wks8Zj58EMtfQp2h^#dWHlemW zAn~xZMj4MpG=cY6{?Jg1FmTk@0!xoOE51BrNG?Nkk8Vze7i*{3W8oo^mj6yuR~aA5 zy2@)c9TbpWwN;G5nyrOlg|6d=Y8`@xHT54Hn{2V(dN0$I>bPWFb@s0hbnyW;s)!we zo;0z5=j_);<#~GoNhl4y{J`QJFF)s!FS743*zbGD=t%f7a8^i2fvXasspI{k+l)S> z+U)9#;c#P9>{Ge?`6p)0Rh=+;TfkB73DqaKQr!vaNXV8+x`ZIm$el3(?P&MrW*BjR zIt++^;{m!KSkVKgK8wPQ*Pu4^@XCi?Tj~KG_kQKbTeWsa&L3ZyVQAV@xav+5Q@L`U zj{E?`Af8^78_3|RWBDtEqxa;sQV;Gan%agSe>xaYjG@{Dk#FVS?q3?@3$L^kb={Tw z<^9c{LX zM*Sab;GyIF3xK3T7H)S^uD^lOrDVu8)SXU8(Z$_iA1vTidQHx%**9zzWWBTY5btDF zYlWMZ%`eHXmhA=T-4JmPY5hmcyh{Zk2>+#uu>eTZl{w%3w3F+!36(n>iU7E4q*7>0 zl;Uju`%HCBnBARsmYrQc@~xjy_E-0QMkp#b8QuPVvFH8;{-pI9n&T?R>GnXhgxf`@ zvQYMG1pV7KSBt}Ds=@Q{_1_N2fhCf>t#swao3L+Rj+SeBJW>NpA1D}kV_ORMJ#e9Y zhh{(!HdrkmosB3NkOda{}_XQ;ccshj~+pbZQQ!S zYD%^nYvv_bX1|EZsp0OX$rc(M>I*GCBAgwb?3`&vaGGUN+0I0SOssP32nG51!z(um zqh1cXc*@#fw~==J$(mPPRJ^CnPF;#d*_<~+sJIX0uQuNsT`c7-AJYoh%+00ozI?BA zRNOAx$HNxIK^mO+x}P&?*{i6;nN#1zq34l)Dw?s$d;{cMWlmpDUC%e2@4~l`1H#;3 zT&v3;)j1-(X#tq%^0?#a+T7U7wmv%WKCYMBR`Hc5WSJJ1S2$J=KphvLCSQ=R_aK<@rmCSz@vl^cU&))EmS5jBqQV7#e00blI~i0 zLTWZLE~fu0)9UhT{QH#jRuH;g@fUv;-T7P6zvDmb=(%1oYsdQA?$G0coxL}Lr~L)i z!79I}lSsBCF_X7*Rl9H41eMc5?mSP~tcX8px48ugqNroe*H-PmhWdyHPDnqlsB8q; zl{+SeB+?}2xJ{^nZvTYTnsjkECS5$3iw^Yo(~oY&35k#SC>>5ozkB24oYZUZ207Zz z=38jTM-Qj++K2zjoRJ;G4%2Yo&qf2SIe^((Z~R%6{?R#m8Tn*Fgzelby<1;I6RF(t zlsb4=uk8alp5qsze5Y)C@A`J>aL6E_SM1?`ulO$|Z$jlg+nc*i{^P&jF?af~_W*#% zCNXs-zd>Es-Mc@M`PLu)l^I{~+3>nj{PB$S{r5$AxreUee$-bQB_29w%M)T?xchxY z+wQcjodyVr`brz;6Mb^H_584}D}ud3JQ;}B+AX$g5$bVCZ!+A1?$U%3=F+f5EkOb{ z_?F^)&&jIJ^95sh-LITo?Ha*SGRfw8e*b$dXY4HiOu!1y{}=^Z>^#yH`l%W{M_O*s zCg;5_b(lrlT$nNI6v#D|&t^sVfq?S8L($W{U3pp^T$S9-Nf{(4-*T=pF`&WxO9^xj zh)0=*l}C_w_NV^suK>svv9I8$XAp*T^~&$4&HUHd_6uZPvEfctz(7*va>}~M0K$7k zT$W1_m)%c7XiPBp^?JVi0rck5=0b*BFoen<_S-zUrGnIUYjZN?FWEDqXpu)5jadEP z$EskqicSFQ7dM#Co>L^6mn1%#@fBorD$O%d1bYDv%FvfvDV9#cpi^ePEY$b63heo- zy~^xs#9*APjE$=7ya0T<+wi7G5Z~K^GIEi;H5)s9+#zP}#?@as#El|Rxi+BJ7IMF1 zG+pW&5zN@TvL#@*m%<;0VlO95nnJ~lKqjRAmx~{)eAf3;E~C6@9wj#VdVd*%$h`it zKSN5vB^p*)enK@|dKO*n z$}e#U7UvzTV)?Yt)TBwz`IQ~|k{1EX*{23;egqxya1nb$v)y=_JG?ec3}Zg}O%Q{1 z8UDA)>+>%&FLm=riy5TNGEw73TF_sOlPy)NHqt|TNy`=^wTL9RR)zyXn##wp<*Q z(&9Pg>R`T|$8HfAZwE}u7GGbxxX|QHJ(>|FS#a#SgG1w| zJmV>(-Q)*RC5^+gHR;srl22f}Fb5ANgG`5kQ^FhGeFV)Ar{-Q#>|04pr(xB$OaI(3 zJ-Fm*E9F0hZzw-2Rw%w|%uU5?$7Oq3bN-U2E7CMb!GP=*lfs4N&tIkbC310+Z-Kt(YL&($z-6WPqB{5*3 z#pNsgH{>D9q1q}e{OY18Ehs8uCdA+ZuyrA!WSytAwyG$D+jZ7c@bmzw1$peQVn5Qj z*1(F+`TCK3n(=nItJZ@^t(}c0ko0PcSXYr?N!kD@)h3PqoRc-w%eAu#=m&3y1AjAg zWQ)?L%$`aGL(fq(50|w>`p0VPaAj9oG4$!=}Qwv!B{(6wvXd}hk{X9Q^ z&@0ANKPv*MZ_t!)jKc2?Z=JrUvwd#WH{nnHt{8Z{=Cp*vmw=1`>s#;Al#%mYwXwlZ zgk59mxhB||5KdMGggq5ua50ZjB4s_B(P5*GR0Zj|E8amtUlq6ezGLy?_`&l?)x5h5F!uU@md0PxQMHA`1nyRA z>~yYFleTy@`-3)8-hM?fsFH;0XMVvmvOfiPaMA*R%9xQh^;B%)`%G0OM~Tc3KInRlZEfG78EH)2NYr2{OrQ*>n2~h*D8luhtAt(gYb5A) zP-KfkGjHz=+Ied8tzUt!@#q|KU5M-!Um9L1^S*-c4RDh)na)CYr4Zsgv(wSzS!^-QbNChK%mJ@+Bv@#{c#=P=;A`Yt zIrn1PE@P&U$d&BTb4LseExfobA=S28cB?%1PGd%#+PAr+sYNy;jwAYDg3ZzPlcy}^=oR>D z$hbeFUlC;Gyc~*SR0V&`YfHIYB{!l8I~(DY*;n9++BBp`FS!aXWbLt9&^w+$*ECEa zhANkYIT$7_!1cNYdT5^Oqxa^@*8sxr^;E~91IN{`&Cw4BHGuQ*&iwISzGr+KR0@NO z6jqLB`1%)6L=Su;kUl=X)W6zjG4g*d3|aRR8jDYFKvc37Kk@Z1l|wU>4!PM4Fmq#L z!{c1dQ!A2T#;B*7h?|t|a*GkrvXvr#(j*qeVNhLpf9COGeMQ{?QtpastKx_0FS66z z)Lmv3|1kAAdT|+PPk*f05jENIr0hKOs!%!maQ^t8wH!JiEL)!4UNTZSHrRU=|Mmm} ziYU0dW&z!QnN;E+ZxdMTuSIH0_^KE=XZYkFu9~aQG)UZdGUg8))Y|RcRnvnt6WF3? zzykLiuSegc>h*F zoMH++Ep}%NUdfg%gnw^&BbE?_vCAe_PrbYnQtMRX7X>;j&Bi}=SegxA{!3w7haDe} zMEex6fbX~^e2*Cebcf~QI}z2AU3|en+^A_K9O`~J{C&}sH?5|3)}=#^&!nX0%>otc zgDQvKK4Pqkl0K(<`O!WPOOh3jI;h41U&0ha7dt^+hO zu@J7&A2$QHNrTyTtpSAo;a}(4B8CWH|Jgr6DnNX9F zk>R-obJ~CI1%WC1$Ezr{pfc_LQ~_i~_k@y&YNq)quq2~FLdcn#^0~3y>GH_<{=G|U zc~*X2n=E?E?mz6}hk`m>nsU|r;m&(|Xhi+G5IS%;wB8WwuwdEHwHa+;Ya&x0%Cg+!{Vtbn)J-ZC;*G|4si}VyvXq zbd?$?=S?4YY5DW4>uX|8(e(-R#@av-$#E@}e{tz?h4lpEUL#*)>P6)m21-xvx8kwS z?r4QJ7K9)lDLSgY^QMX$fE|ld7>PIdEAhq!pXcrq7=)Mg9^Oxa%EAmzmrdVw3-^z& zViNDleFKGKhI`<8d%Qfl>L;8?PThSN!?a9N($!u^k$CU=BnCx>{#s-tm$z z2Y)VII}mojLE%ypIgZ%Rcwh73n>g0BzosLUv|ruTo2laq$|^EzCoD$rm467G@>FxV zE62ad?6`84sxOHAT;Wu2g=+c#sCx5oDBJM=U-h&rPm8SageXGUWtmF05MoBQrm`s2m?G;~vP5Q#vCRlEjF=g-^u3?Y=lK1O@Aq$qgX6xh`?~Mz zJkR&*Rj5U7dwY|9XVwj$A`wZ7q_Uj>7cd70_`K*j)>p6S93!;fTA$y`V=imdqbrl- z*dKyVY@4`w%pe~Yyj&=l1cpX^GPKB|DuWK;HFpID#^4LS-MT6z$!?~MwiZt?g8oEJ zC_H1~r;$8^bl$$cp+@KCc#@jcbrS~t8a@DGnA~_t^6#)=ANO&jt4ReX1C%}$GCK_y zVw9db^{_~3^D z5C-hS3Q0>7NIQurQcAw??gm7tGigz`U-Q4Lj1foQvaGTJJ+!St&u)gZ%5QjGY_n54 zj-NH^86w~^s4bE}Voz7X|Es#%%w?OZFH=FAM-S&cAIskjlA`1i$Sr(CW`@pTpt@b< zdaK@4@*`8`ng>}lxNq*XsqSyh8%A;`BuVK_S70~x-2Kqidtu|jtsCY6xfgPPu+iSSXm=9 zLYg>^PS#mUFn03+g=jihTQpRnXgk}%&qLx0Qc7sc4eNB{I2;S{O*82+?%dFUJE!$6 z>wI)PpMywuTpF1nL@hR+uck=7dtkNHnHo&Wm;uJZbtIEmrT3|BUMVS*Fxb#5u#L{j zaL|pv2jktIjKO%sPo(b>RMGRH<=i;|Vm`1n`8u-s`@9}>qjrGQxk%HO+R-QJFKufT0|$W6 z;%jaNuU-V0{`>TZzY{}pIM)$B=O=YH@Yr@9*zAY71ef$3C>K>!w`2woub!|7c$)F6 zL3?A#zkY))QTQ&f%`?NS3mBV&fQKhJgwLOsf+j2E%o2+&Ldm&-aJL3O7%=xGDRq6P zGSwtwTQwge4q|%`ICvkB+v-sVt5i*zi`}9#NCTdbnaZU5&%)Lq`b$aYhjURjRjb`% z$iPteb=Z)D`Yp)nmB}yfI_T=9L)Z}VOsdd>^z$?oEk*1A+l!4=%$R!;rXO6cdHjQ4 z=oe3RJur0ZU-$XT1NFFC!9s7f;@TOYq(mVlzx&(RTHQY!dduo!?5lF)ko9)A=9BSf zgcbJ*2<6tG756H;>doboC2MlQnJ=N)pZuse=b(!_6%93$z&q`eM}o@Ho+xXly?E0! z!uUKu@36)CMRs5oX|TY8Cg|3=>37S^%g8meL9IF<8XlS!_M=hhicjY{8z0ZA>~2|m zDqh8Tf(qtK@A|#umDwnKmKH`&W&aPFq52>A!6(p0ZW!RwYEsUdmgXIS1RI|D*{sbs zWl8VxEdB^sycuT+@ox{EZ(XkgDxt>JJ}#{~Z=Zny&{Q2xQF2feb;@(jjS5 zNE5ctC>}s6ae8uQ2~7Ofs?|)k$rqV2>a7NJgC)Yc6{8ecnTn^|$tMp#5D}ydyj}Pu zzbIa=1k{ml)v9jUH5OvfF+xE_WPpgbUwHLMkrpwu_UhKd)2PV@!XpFtA6PG7wDRmn z?2xqEm--IbGk*jgvXXh4vg2*-gjBqyT%5Rm)H*(5&3YU3%JVyPp{&E_5NczR#3O$% z-x?<0mEO(0De~F+>_chRHXKhsw$gU`WvG&w8`G)tKULV29>>}kJ9juv2b$5xuL4wN z`hI@|jzE&9J9>}1A$jUfBkSDcny*4b5YVkz$&{HgAC>$tOncQ z?$pq#3J>);e9qBk#=HaV?VrSEX;J@kmW1R1rTZ@4>i@{*R%b2qfchwF$1&9hF7Lvv zz-tj-nmGx(VH|j?sk&P0pGi27x}8q%@L!4fGdwDkZflupq%~7RZsRuE93H*bL@TLC z`~h(ij@Q;`gHusE0r|FPqMOwKO$YZ-ZX=hXLT8q*q%ZRiw5Aex+!tzqMZ{VSzhTx(@2bB45#VVB=uck;ht8L2unByg;1hWFi9>zw7f=SLe6 z4gps!dzs9{q8l&mlaL4$#uLkkHzl+{bM^oSw-e{%a2h`F?SSA5Q2Vx>eX_cA_#1#V z>y$%ks-fi4_=*DhO%M)6DT)Y$n@2br)e0HYK(g4$+%Wi_p$7nNcy>;wlSedpSvO2A z(vtXuU$V!&EWFIAH2yje=oACjhVd0WS~p@z(80|hu-}T;p2^*O$zjsPzN%JbHqUJ8`fp2k( ziWNMt@XYyI4ZRpJxD$xE5!epHNWbO2CB5slo9icbn6*WGdG*@ZjmX-LxDampaKKRH z7r)Ta84bJZ*g=%n1NQR9R7*xFOi1?XA%RiXWiLGqnkZ|{sbttA9tD`S_J+2w?6`9wD{*5zI9z$qi$=A8VBTD zXhrJd1!E!c3^Jo>Objhter1XYuNpLjQIrsX>CLw-3kq~GIsy~-z8%b#JtHsX$cK^A zZ|9+}Su$+h$P!KT1y_pd(su}B#qFt&v~MXHm{4KW`aW*@>3Gk_73jnM2-w;A_qe*E z@jz(?`VH6;U26p1D0Y7HF5SbkcLzuiD+B9t=<8TY@GSnh zQ)Gghi(V9EL+d;DfOup=<#BT?0gPzLPg@~U|}af4c*jVsJP!G_W1Vn ze{@G%y!>3;E34*g4`37z0vi~sS;xoimU9$~OW4P0VW6(|iJlpr&cBC9 zgW^}CgJiH|2nD;Tso5cX|4ObfzO`GT(5>4BAvDt^Q=Uy@W8ogNKz}2^t_l`wt&SR* z-_|}El?;jzu>6!8@{r`1jfH#fHW?PjJsmrB{6Ld2FwqxPyh+RD0C0^^cl!|6L4te_ z_oj|a-uUr|kl8}LsC59YQ?^$tT9W>`-0z=O@KK4PQl|6ZjNz+1dwST}Z*AAiI=na_ zg`eLYtP>%Ys)N;lQU1R*U1RE>0zZk9U^RV0k5}tyei9=&Gf{zTe@a+(9D1=!rs{Zd zLw!|Qw=M!lLlqbHRGA+KDnS_ZE5EaduTqLH8Bq;>zq1WpNp}DoMz<#FU)PRoqRylU zY$UOq7M2(OsHF^{+A(q!%p(E9%0nY1LZTnQ`Pt$y22iX7Mwcqak>+La;}SK4FxZzr z0w&96Kc_s>+IFv5r_8!mrfsyBF{a)1as#o9Y-7=DmGsJ9K%(*bz*^4G5T0ZBB zg@(Bp8Zv$XxCEy;Q$gAF)1n0s=mIzmsq^z@S%+U(h6V)U!8GNeT)^~9KVfJqsbdpm zSe$1wb<1D~zXaU}`P>YH>zhVB`bcUkI+(HGhG=#^qFDX47@%0;bE(uB>QqbtFUE@HI=F;}i;7+$|3S z_TIi)@m>Pwwk2L)ub*gfSynQ**0{s_H_JWac7_FdewLIuA-MCUwim&Y|0B>tNS?q3}*2X~ePr5{e< zi!N)DUUzXWJNgHWR*#e~8w&H9^bar8O1iL|ttP8BG@X5xFcG08XTm%|>0b^v!w*7P zEgZ{G?YReaZl!B{*-v8|wcnjo8?~p||J0o*ICMRtKxtch_p-;q{2#CDr5b;Og;Onh3t7u7m)dL@_1hrsK+QqQ?HF#b9#REx)wC(mj zet4Virz|vXaM-1OOW~Ej<`L(0rQrR;wN&2RqSC-tLZCs@B&a(%K1bxs$Y1^CtazJv z>#^@4n6Ip-33bF4gYcZMyeua@^mD$beX4`QnE$l)a-{DCV|!3%=y}uMwGw{>UVMh$ zL~#D0yazj~l!8qoxumOReWFY0J=V;+9NMlSvq3Z6B=g!j`Z!7>6uD>;tx1W&__;nF zlDm2o2LG$@iD0bVx9x7|7V;}hd!CkfvFH88_6B)z(+um2Pom8A{Fb0BS(P__+Mn~C zOj3%sH485Yzn2hm(t!QyqVX9VnA0Yn6u(%~!m&V&W}t=i4I-INu9#mT>!-DTz*P#2 zPHo@+orrSrdcT(EiP&oPwmXczX)#%(pt9r!!w+p{PoYBEd7ql-n@z5FdW*wZ4S{})+g*czzh zWSa--$~|(BYJ2XC-!y5l1cH^4|6FhXs-0=Bv`Na2+t(}&FWlIJsCDw!N6Kxh$QIHr zGrBP;9z@{K5RS|I;qD-^6|s0IaWlCy&^KpjZ2E`uy!br-DMW$#S1`5dx$B2fcBW-Q zofdVby0LUF!hwL^gsk70?cFunI+$DZA?MZGxB4xN?i_>>gSxfiK4q1k?KZ(-6bSib(vV{9V#mq}80zup%K*01oT zoV{Zt{*m!{=fs=Y!LcnsI!aCdk+v#XRuGs$`%9{F7UygC{-{p-;3LI))9+|OzP`7# zSex2jPc)iW4Z{r}t!KmFI>fmdMKU^utCcT$P7~4C%t+%2{ z>PddoKG0k$N}zdD+-E$hPP6tBmc)V$&It=9s0pkO2hB_k0ILJp4L!y0L}Q#oq4sSZ zuF_5|NyDq1K=mqPj8D@mZWa_iAtrjkF=Scat$209x4XjH-b;MEqjXI&CB1b9hffu8Dg3V&1ji8uTmX&1QHs zjf#xe5vFbHP3OCmubLx*C88!tGTiF#5(X^&fCr`v$;9zaY~kM$oeh3Du%t@gQBvc* zx)^TnKV@FhDvRlhy0tdV?^c?A4dCAUHwk0m%rCY5g~SJYLc-`THXkx(y$wgSH2BR_n5AV#1c11!<|0fv-@aOj&SU8 zW!#lFjX+hZVW9jmeErIeb2zJ9Wp zdi!qCix#FxCp2+Zm^E}_nJb&qUGQPow`vHX=2BFd_m3P}L@>aqKxJz;Z7w(d{zk2= zxyn0i`m&7va~%c22q~rQT>g<9$N~M=!LVA|+Y7IK1Y6ht?BNgsmT>KLVYPl!y4$XTl&) z%oY2wVJ0E60s%Owj`Z)6%3=m`UhDGdBU93cS$n-b84T-^84|@vh@5dW)qR94_RnU} z@Cnle#2KI26K|w#TjQiNgHSBlhsdsot?tN?KLUR(v%)I42Y4wo+@$+`krswD#5WrU3;?RH0L$obJL+TLjU(O|@ioYHdD?e(|}C30k>o@`h!NGhKJO z#lA+p@p0Y#;E~Gu%im$H#lOR)iQ}KK1^-}1(O8XX)i#Q(SDviLV{NIMU02Ts6ojt1 z4pmKd{4+YaG3%Ln?h%G0)W0&o>_!EkMhiFZu=s*prM4}pv|1M^#iv}7?svsQ{^9UG z**v)I@L^DOxCr+&fY-oo9XFoT*RD1j3ZAFMJ#Eb~^-(E8{&@acfp)8T54IRLRw8vw ze}depDL4IFyE~aA@&$S{@}_)B*&1Y*$;pg-@Fdmp^ez6+`Ies0pGt)Y()N6H-Y6TT z_-#^j%8MH%fim^KI=8&ZRhpx-F2@$0Yv2U?W=z>xAYcgP^gO%unN`7nRCD@2Dqr^{ zaEm$$N6~X{9|(Wfc$Z`41XQ%xcQ~@igRs8y497sxGtZNIKiWU}ZGW~RSb=CC=p%hI zQl0m)?c&yp`A1`#1igO87uxhg+?4j`is8>^0_YE7g5juM$uV?!3Q~4+tzY2jlGF~6 zc;#3{o|wWvq9ja;$0k=ifRT0y&R=J16RBdN(wTz?>O>6!5*$|WUnt3hEsI^`SQ|97 z!wS=rDPKki5KZns@`_;c^e=c{&kepx^uNPRC*(d_{q#9Tmh+4BXRXX9zi74UrZrSL z{UClUZ=PZ92kH6zcr83^p^+!})F8B0^cDZuo6XkAZY=AC@@To2wY>ed*3Pjms@fSW zNg~NO^8V-=uv$h)r!CAkRH}cw8qn_N7RvVwX!jAXwSP!SmfUZdt@EX}QQrz!g7qw* zzIG%Llc1%YGVA!+mM%Vr=^nqT8wT#MjK+!{ptOT64MZI+0;4{f)@?wKb*OqvpKEl6 z8Cl_DSBa|^Q?%;MvB--@Z<#$xaPZk3!8qYFX{Cb>)Q4QDLpOi=F^=ydw$8P1H26Oz z!)16ydN3nfao27<@x0r;5zJlF0XY|UDYO$0S>NWorn4O4nV1{cP_s_jpLB=WSG9H4 z-gU~(%pPH4C6o0%66@&+5E^@2JILy`v(9Yo!B>9j4}lhJ5-rXn^|FNRnvvkn`gViiW4hp#)RBQ-8*&gWWrQxPh64L#UXSJ3(kS(7XOfL#ZN zNgWXK$jvYGyB)--)B1%WARx7Z?fBmRfRrnNNU zah$@4qzErz+nH>C)7@gZ(A&su(e;`4Qwq=NV^vlf@iaMAMu}qwEHNqiLfx?Mk;rD| z;2CB-qoRJD({|GM?xd&L^sKpD@&P((D^yIEo;P9oxPTg=`##qE5D#$F&6I#z)dItV zOQH&#WBSl-&&3J_@z?sr4%b|k%QAx3oi$GK*Y2ZeSu0$?EqrXwQem=fMFbND>@w!O zB)xI5O5S(Mfj&0PxH`&95P!>YPJNy!e8}k!^y}JwbPyzcSOt5O?bIR}0X*Iz?xS>vRf8({pif7PNEKInH1 zVzBm#vo5(7kyS|aQ$Zit?<4l2%;hn)m!%R9zV{!9nTOf zxE`I8{42l>ku_RB??B^p^W7L&jAdMMAa;7*wZ|h}d!1N=!=BUC_1OLB?M{}hY`8K& zQPR$;#6M4&(kXGZQh6_LTSz6SP#GkJ=LO`;o;G#0xy<6nq-><>0fAJ-JEzH^k1H89 zjz9wBhQQnott2~j*c+T5veoWPC7$&Hf*KQApVZCj;6EypcUcD%bjA8hoGWTNZS961 zF;OOumlf#9ZhOnslP^}yOUN=B1MAoz?kX!UX1v8u0Mh=%gU0+k?;Dc(hT*b%0yq?;#K{ zl|akBSkX&U;;trC3~m7&Bgu3+M5UNxF!fHKOh_DTCeFAoiANvyHNnebhk0)PbtAfq zIz`5}Qx^x4rjNqPWniupE%NLlV0K4HSe>zwz~(o0P}Bnf6B!CZkJG#?ZUF`RUFWRfRy2nz$sCKmAcL?7d6-$u}t((x_`^cO5QO6<;4(;F=ILt zIWPmd60|dX89NC)`K%lWIa^Cb%%O-kKKmgBVwHBjqOFOHSCte@nN5L0*ZIP5Uk)wOjIYoCs z)AP0G%$=Y5cBh}YwDu`tYqE-bsX0~C!*e|aA!&{67%@>zZF?qOZ%XHwPi5Po!~ z_i)}~T(Vyk%9o3q+F%rhZuMF&Jd?u??cmdu8ZB2*C^_)SaBA4__3;`xp9?8zG&9B! zc6l`<>4ZZPlMo%$THMf}K)|3|@mJ}PlD8H0v25X2#kB*v`ax5Z&qTjfH%$g%-8{em zq$^rrZmYjs+!&I0=j&@ALDaM!EFC(Rq}a~fOTP_EXoe8Kv~qi+%}Y8z5hF>C6cCc? zaRq&4A$>nxJre&d^zm@ z;MbEx2Eimo?Uq9(>q9ihG1TEeO=4JKChxtSL5KGq{}@n$1)xGd3}t~}hS`oXEj?z-zitg_}YDsKly;v$s2BcmZYs>F!GXNH%ge=j)$T`A%5PzBm1Jg#yZ z&}0JF^jr&+=)b`_ypXmX;Atw|y?tyAB@KM#cb_UQZ2iB|Adb)&Z{V*QLwVY_zvT`( zo?Y+6ve#Td>o<_x{aZ$Ee3$?3POA%d2-Adv0XL`+wDqvfrloi96!7wo?5rs595y@& z8QBE=ujsUN((VM*;MI77|CCydKp~v6pkogP0tF3BARh)ok zpa1{Y?5n6C;8_2GChFA|0n28(ujs@TwDy)3eb+YxHXg7Iv$b42ZA=~o5K0S0>Gzdj zB<9bm&wJ-{l{(jb5!sBT+Sy{n1_QODUVs^?wW~Huw{Kc7q%*z2yk(BFkG3#CwK`#d z)RqqOEz%S8uK+%ovk2ST7z=8Q3sA83EJ9=k{1H&TUGPjZ^Kc=~%HvAQaU4tu&c2Dr z$T>spce>d8S12d~K&TgGA268)RIC=(0BHLIr%Lfg;(H>nwC-s{{dCFy!Rg5xgS%F9 z?FD*ZiG}T4jcK_7E`C$dJ+VN9MzTb7;P4zpVDFm|S}2>k*7uoP%|E*ng}ceAw$Ala zWtQz1>+o2nl5Hv@DSIb$ljxZ&r|iKy_-_7p0o5&ZM6ezryd}5a})p zCOB!;s+yUL03s_Amw`6j2?4!fVs&yZ{Bnoqc0LJ=j!pSAl05GV=d~*qx14ED3R*B; zaQ=zhm*(4AxUkHq&DlAze`Zza8jqxRj=#V&P+GBm{jKEvd-5Sp#mDSyBuv14YqldW z&B-Ktcrry>I@_5BJXp>jBeId7N0cNyWOOr+;eYboRDo>FnsCLsq(i|Y?+xMIgVI;i zfNC|w@Y}_-K*PyJmL-f2)KsRo!PNeOJtZ$z=G zMn%8;((y((r*a$CTSt4Jh#Kg-rC50t{xjfLI5>OPMQCA$GHXLAqdk*Nv@raF4WZNh z$t>}ka(;~#5(?1yOVhiLj7;QQ{C$K`h&GAeaGzAG<#QJd0l?Y-+^|{SMxdgau|8Ar z5pX*J)<%ug8wC$ou{7(B3W|C}3>?*{j#|DDqRnx9fGWz+%JC+h!11UjoA-A9J+i;2 z`bCNocC+EEry;p4=k%AXuB9e=X88KvdBVLb$pKQ7b}S1B1?(Ld(##5r5aUPTI<`!> ztu_Zim(~LTV@t=zyuwoW_uL~8uR$Lgdg`*!YAx@weggtN{H>{*uK*>`oT54~(y3)m z^UfTS(fS^(H%@NJ|Rt+1!9LQRhSY*+EkDvK7lVNb0$q z+YneWE%*eB>Qinw7h?$Y0o_dil9h9UoijC=piJfBK?82ULb|svF(db>1x;bgaQ@t#7XD+sZ{{roxwJAn0Fc^)&ijb>-o*!m4ki_{`ZKAiYzw! z4L}LN21%gu#Dkorlid0@vjf@6VlRZ=`x zxehPeqX@mWQ4r>fZ5)@VjVf$%>lAW+}u1nOtxD3WUR}S)SY4@2_ycv$`Iw2 zPPGJSPG9&q*(}CkGicZRV z;$soe`$#rBN4|%x#jV0&Yofl;a(-pn)~4d*p>36nCJ@;-xa+uXwnZ2T--g568mS3U zk~INwG%~AgZ)5rFlC5ytkfdLWVel}SP?xzSX{#|H>mzP3#I;;?4cY+WGZ_ssJ@uy2 zL(C??UdhrvTP53^7T(nBNq#kek_@;NenxrJyn_&|5e6Gm7%Z!YLra8oD*vAD7A$Oz zN@iw5ZY55A%X^$1noLt~3@~rx(UK!B?%6=)QrL+?Gtkzm^Ugr0H_z5M7^}s9 ztXDSEot__3&zDUeF7~q-za%&=!=-3RBNueL%{9j`Q+pWG6WBJdLbsmF@C(kar98I| z&?_(N;Kj3_uR!F*qG7U@DLiAA67Je zJ6J(=(jtmbA38Afzsq>k9USXvT3rsT|Iea1%TrTY7-1=cyT4Kzl2V%(YD#`rtEzBf zAz3qux~n2cSstZ23I`L*4h#VpS!A5<-qYGx^jzcA>7V$9o(vrL!M1ZuNTY{q2;xzn zp4snVzv2^H#p0u_Eev?|=8LI&y!c4b2ix%bC*8ibcBv(NM&{H${Q;OW1<^qizS z@y_$!^7U?Rt?fFDdcD}PgEV4XuQQY>`hhi(3xNU2g|fU1XxA6eBk0TOtqA_nkp;3` zdwU~tJpi6;(EK#!B`P3w~t$*sPt(FVwHZ5AIT0TSMXCLJ;o9QuGotNpBbULNW&G_OGn=o9;ffvaoqB)sHhF*YT%sq!d8w9N(sz}huYmCTtKJ?Ba{t*t^ zz^90uvKDNBl19SzS6XUs+<3Gcb|Ctjm%*z?uBF^_PJKRwqWW^5X2Rk!4pAOc9pmo) zLb^@lB|wtzyb&{axP*Fv8f07nH85XhyEPMu#zpeK;Gdr#IAr(j)r`R(0jI4$0xTuD z5C`dcsdBZ7-XOu#5^UJEg$oj79z_!?yO83qr06VV3RH2%T74m1a>s9oHX-Q@ z3hgptmOJ=ER5E!CF9({dp?Ht~5%BYKHJ@j^&l#INk^vYBI^~Gw0!s(o*+G+dm)SF3 z$GUMm=P2OOiFmO+;>!iF4lhQ{{VGsnIR@pi_K082-$_gMp62JD_bufacxB>ef4X{e zN`Fp$IUfM;IL<-^XMeDWKOPb$LG_Wlb|LeLtN=TvxrShkOG2pWPG=a8%q9!hB8$)OW> zEc$XL>+ANu%%kOdt&_-YG2XThqpEC|lqNpudx7Si93YRXxj*H2v*f{=kJ?_PvT?NE zkko~qtFk#JPft42qc*}$3H8Y*2T6` z33IibWaqEqiDSfGKQE;lXb+;)*3niVdkPZe#>FjrO9q|l1q`N`r@f-g) zU!yQ6E^s+NITtjS5H22C*(;^gfP+;_Hbtb|@1-dsOPjW)0B$*{p#PjjtB*W>M)OZ5@#y6w-1^R zst3Se{Mo{$q24%6f{$}&t6eVT7pa6I_{1dlLiB+bLn@Q-uN(61e*EL-w^DwCUbP}# zHUdpn`sq6!VUWfC2%U#(`S{R*;Q`&B)$0%Pf$mBdOA#f^A8bM>ZZvNlKfVi|#uy2F zZaTD1y0!o4Lc@zEACb5pKC=*DFClWkt((@rY8PR5hp0_$*m0+e!EO>-e97gOf3SRm z92W5909~{e;wp?qMlB|WGlsjbNJ$7ax?YQ_ptsHKYzq;_b2t|KV;5@iz_ho!w79=n zjvnD61~$}U->>hJ=T#<={1JsfeMUD_qQ;=Ya^sr1H4ATllAD zyu(jKzCnK6FCUHU35I`s&lF~Ig_Y*D;}dCxRs8{eKIM8hI-;_3h~8N+)4v3xho6{A zVSZ8e|CZjb9pg5sF9s`ic3O4JaE_NhmMLX@Vv5z!bJ!3A%y+Ll0+)ok3Bhb4AZa(o zfS2!1wc*T+Ghu+FM(Sa7Y)5bZeO0JtW-1B&=40#o3Uxb)&|-4%@SPsw(Zul2N3gsk8IP{O3;eq>-+Y0J!Z0M_ra}N zZiCM~4X)f__`bcVkH8lGMTdXYsMyT8IwOOOHKuvDv3I%sZ1;G2Q3Sk> zqs`UX!hTI=nU#$GBH43prkDDaS`9|;+f5blXDAV;%%iQ6BtpO66a6Mrdb!tbJb{M4 zpnr2Keo>_Bk3gc6Lk!n$A*&f3I=Ng^Sf7Yyb^(_DQ@&WwN7~Z)}7NKDXXgjSh zZ@`Lf=Z_gRnTx{pwIju;Uq=I)u$o;143$RzNzSa6M~IGR*Sg$ZQaIQfjig-#ieT3e z?YJLL!bZlb`eq#yO$PuowSUP*7ob5t=k4wZL8L=zu=i8cwN%|{AxBAglSi-NqN+uflX)o1m)q6stA?)$);ID)qz=$eQ9ru1& zJ|A8(+xsv$)!4eN$}VFU&MM9!AIMmAw+#^Qqo@H+)Mi+B@_F51MIGpIb)#(PmW6PLrely}~)4_QZAQm5Zu^LX9`AMJ@4-8?dj6 ziDd>Z0+FPpq|miHbq!Ya-i~}*{s4ETz%(3@Ni(ezb_rm7$nDqyI(UHxz}+1^eyGYoP4xp>eaRA*)QX!=OUKRW(s!P>51!GrOYbz&ACglODzfiY>Qhj z&fumv(Ff9j+~5NH3b4JKd9t&Vo~AwTABm)u9dS%-OVEaK%C}W|Iun}iY~_uS%o1gQ zn3tyw{`xCY^Abb1@9bK&^3&ZkSeMe!4%=e;g@pb>{)sBT8EZNNi-@(iyN^dtu3SScJ!E zt+Pnk4(}AV*eUmjkiG?ZfDtJjx+DcGDYH`#0HX2`)|XqTw!YH86kyXc>bw$Aw++@M zG3BZ3FXw}j@1)thbZ(G?ZC{UpaB?lAQR>faSI-4-ft@WlzGjD0yivxEn9K>@FF$e4 zA|zEQs#b>AjmWK69U!k(CFR&X0vAV-99v9m3QK~V7*;1L-lx&-ioi$Z$T^kNz_Bk77+hPSn>&?w&+a zE=%P2=f9-XbKFO(6MN}kEc-pmV;U=2;Lz?0zFHxN0~j|T{5VbbaNf4<%p-7)!yBaA z1{DWQ$zE_W_nX#coUM-`4hBYNB)Ct*lG$O$C_!2CLNp z+vlSgb&2PW@ZDk6H~{**KCWA?#Y+-4;SgS;X@REU>5iV*WWAIu6&mD3+$m}sR%(k;GhAraTu0ZCY&R~Q=GA>S`dZ)yG-Rs)8hkD=22j&esfmMGnoYBvmpoJg zM*N?TrT4^*IrA#y5p5(RB`xXHfT@}Q@LZF#u}_f|(4+;zZs?~^BAAuLH09c1yAU9I zcY^5$DJsu|T@JYlt#{7JV2ZO2Bv>Rgk<6)p4 zEyE)NH1o^B{t=)7ql)S895!rJnd6)`M*J22EHVEP<3|l`KHd=MJ`O=jLhsHr&uL?w_98m#6@gx*Po1L?3_35osRc235%7F5*1 zK@qf)syBc6Z%nMnvomQN{Q9vEH30*VQ<*f^cr21&nUW69q-*mHth^ApS193WsVyWd zjnl|B-_1YVAWY7%nzhh0QN@`h4a(FVGfb|c~6`0pa)37w}9Hv2`bf9suZhb%^@2oNov@9%mCE*8OF%x+*4%alU)9wH1vEeF@(h~;&a0j@A);NK^6ZM1NHsL9gaZB-7w`$n%~jLU>& zSLqOcgkZfb1PqDTY7d6_3b;ikcQ(LED$MLuy25?@^v3TQ=uDQE)xKD(xaW0dwMHER?+UAJ&e)YX|}J#RdEcH0=`@ zr)(U8d#F&00`P)Fw(LZh{#|sN1DTT7_~H_Jfg*JD;zX`9{Gb6iWSgsD@T{s2oXf(K zOVA?KmJ}r~B!NFqBy`aX9QG#jTK65NmREcUDd$jrO~f6CD+6RYxq$RE>G0P*zp_o1 zb+^!iy)GnBtk5_B(kdS`xE;Chgp`5gBx(z4cfIdZW-(UA9H6Nm^GdF7c zahnDeM`t;tpY>x!)<>A>Yw;ZDUFkXM?w0@$to_tcg1vZXS2HnJ8m^;ytL9oL?FP z&gVvCZaXDg$C{UXA+AVosg7VNlQ|CZ_x=xE@BPr!_HKLQc5mHQEEE+4H=rn0ia}~@ zG?8wCNQqLVB%uhQM@1}15fG3r(z}!-K!6BHO9)6WAw;^A1V|7FDZXoe&w0;1_lNrz z%&e8UW_iXl#;5ueJFvXFUkCxL`XG7^=|DEo5~#fT!#RER)b$2`8-`*8)w2vwx{sVm z3Vpie8GXGs^{$3oDH=1+=qf@yK`gNBqrLnWKEpN^RyazA4x|z~g{UJ*@dCP|@q9UPIMg^?qGFbYNvLXHA z@*iUFsofIGV3lgyi3^K->3nZ73@HhiKgAswz9v4lFpN> zoMD#1k=>gXD|Sz}TOqOe0MJ&BW*>KX9|@6YRG#fwwSx+dCOn^y5L%=h|M7-M?wXz? z@16?_hFIcJoK41D6=dELS$0;ehbEt=Of~w34_C{+v1jpD5CjOoWNHCa*f8w&yl=GK z>NloeU=2tQj^B>oNyQjnO681<(=jc~N^2DM+^6)v6-PdVWjhPD6rOLH5O;c}T#o+v z^LFri7E9szSWeY710cpI&HeeTLj%;5A_l(QDQ8<5+vIg79WgmBYIHGBvY}s|$GH2}n9{mF@a^xfRs;uf?y5&eqbYk~?V0ygC>8A*6JvYF0MXexWBr`-DiNvao{^TtKb%otK8pLLc3Y4?j215(I*E*C$)JD-}IDe;kav) z*>mh1@Z)CE0=FzGs+HUK4(mgWf+`dMV&gI;{`a8UTEq z@IV%WG?^Re{k|C9M`GfL=dbUauQqSYSfeip!*aj@SU6Wu*wVY#v)!{4M@8e=33sB- zKB%3q>+3=A?W(Ah*WAOHFd%y2uTPCNueVWHyLtdOwbxu)bl+eK7C5hKpcP_6$#(XJ zirKmE@Zt6Jgg*HN*sh$$SK6tF@8CmEDW-?p=B(z#jv4RJz)Y z684)dIs_P|09M;1Dc&MLHGb^8==Bi1=WSKz?mh77;;d712t#6}1w%Fa3_&zzLau09 zf8RCdAKE#*o3~A`9r-6T7RRE(xV!M0M=f`^E@<4_(l(m^kE1XXmtnYznNbFlUHD|y zjz*7oQks3eE}zjSXomT>X3FHHg?Y_LPKLHOW*2;#w)0qC{Kl$Ti#stOo~lR1FTukb zIOvE@5OCbmXj@fr7B`-S|C1gnA2m*Uavb!rfXW3weW4}Xf35l69oiNVxuEAiCK2k9G82Zm20_Fm9XAags+^pJFFpMt*?(VL(>bq8#;Q?d= z?Y}s8BAiWevacP5UT7TM2%M`DX7;z!&PIICsg`SrbT62)e-OMBkVP*~{kswz@alrI zN1wIFD(>v^!-r$7>#;QKQfwVz_wLgY@29`s1Pkda6Ya@k5EalovYIPgZ=(PBe$>Hv6R9VQmGzaCsm;|e*6 z>DpE*`~wexYwXlqEcH&jRkrx55Bw~4%H5;;$JmO-TK|R!_&MR&)8^w7Cv(4G;$#Eb zgA*klBwh{Hy}pcX0S-|w;(>Xv&ese|F+Ufi*MSIFje<76>(gdr@GQa_zD}M}*!Nw@ z^UAPU8GhhpNnLWIr1P@gh1b^A#uwdQc?fBhl|U_m_N4{&v#Q8~yK;t|;noj$1$E8R zH^(qfoCgQ5)jy~@jQiOCl2~M5A?BfZJ!$aEQ=rlo~EV?3p{xw&qoo>PZs&~xpZDkc=zekS_&gL)2M?eV6l)G<={$3bn6x}NJ z>lK#w0X~!H71-clH9I2OJI;B2)VTj(Y`rY*k2=DS6564#+ne$~yhA|mil$&a7w1ov zcChHy{TGg_L`lcbJlq|dL8NkSb7eQUdS^Elb1FTyYwjZSI`@LySTZvW0V_sx*;#VA zJ#soYBZ$b&bGX&$1RVvNzJ0o> zVo^Cog*Sb(|K1pJFEy6n+5ab7qqeKkjxydVnX$BtpKEhHQEzcmZz(Zwv01(YCKw?d z<^ueUKD&u%k%<)>z7k>d9&`a7(Jw{mlJP6K@@$Hy`BRPTF0S=5Psz2xzR$!N=z@H4 zW%4F+0|t$AxAqM$>#e*FqZ$gixJVqL?!G6%o|pA_DAnL;nLpR)V|BN z9=}F2ICMHJ4R9gRM9^&+yvi!|&J_ z^Q;7B1CUu&!fxOi9Udc5H#d3NB&J8{z$BBA(j^MY+}5{sSYNKpA9U zHB{PBRYchCWo&_H=Q_o2%;Y7 zW4CCgYWJYjU-ooe8wpI8G3PK>wK2^$Ot!F{upVqe=$*@)U!tu#ej}a#7Q2vlTU<`m zOR3W-FUQkdnVxu+%JSvv6%E@+)_FOb-S?#lqTOLfxEC=Eu%jN(b6zwVO9zt!kix%F zu92s^&x7T-Uw22OS0y*@FL=FGgeQcVxW%m%9I(3Kue6T85aS*v|EmuKo?t|CxEeg9iDU~w2XY$ zt6S;R@;{vU%!L;CIQk~pCF~*Zt)6<2*h~wi%(F%6$ri; zOOmMKj)+elS_-0*3Xex@vvkHLUa@nA#r+O0I0kTFL2iM(>@a)mp%#&$jHh=i$+CA2 zJ?{Z3j|Do`el{Ve<~A@}?y za40wzl*d6C57%+LUOrEvW2+9|d!(fL_nZ%HNRL;>h!^qjBhRo?&OBT`dW?H>BIBWY;LIOkSCA$RkuKL)-;Z^gtU9!LF%BPd4H za`lGbb%aBdTU84c6`7u;t1JVbt4EIiK*vUS@`=C&YduCspYzm%e`%BpE`3nYnWxL8 z2LO#64byQzbMlQ+*De7+-}-01u;N(6r6!kn?@$0b)ne!Swcp802l9Z~sj}wvx^T3d ziKb|ORpZ{_edM|pbR0!VdJg4>$4aKv7apd6Ra``zJ+s&X)cIfNc##UYk2bU8pW=@A z2W;D6U`fc-lL_X;E^VCfnXdDjutKX_V@G7}m9eUby@XJtW`Cs@OL~sB=C!$h+jy5P z8N)pU=anGU`U6heb?zJyM>xXdd@~dGIdbX!mJc7TbaYxE$O%>=$^GBW-<=zI^=@PR zVateZ-WMYoyH`-=1nM8zO#z$5G481<{l-lV`r8W6l(&i6O9KR zUEg0trd<0T=Ey5*QRNR#pEdt`eAmrEsq2Bu3%-2N^eR1O-f#Yu+}FKFbJ2U~?UTHi zMP6!zVAJGFpv~zJs2(`q4#QpBDjIG$8MQ0jl+!q!6oZo}Eb#R4z}G6-5tlk7aUXJk zSN$T&{^Oz>>zc`#q|orG;KPwmmUMixePN}05-+y*#8rC4@0M_?uGo29zUOyyJt3OA z%&P|jF2b`xlY*nWG&sy!fH zNB)p#*mVBNKa*-a#K0KVHZ{I@AcYCWzRlZbzpn?G6mwjA>=U|Gv#!|$P!ns-QfB~X z&$1uIGhGhTLMgL8TxXp8(tS4vSff`_6&J5_E=sg^4}IVLEx1ydH+lZ1n2dd z){sv9*g_-J#|iv8kfD<1oHAqM5=h7UD~%#&91Z^jlDrd*U0)5%C*$(weB|+r$i%F6Qr?RSsw{;>=f@@n$I{Ct&<93#hf zn}kkIb_ok31lLS$>28{)3n$+B=2=QKCl=~tGnGj%Dmwk1G`iF}Ffy>%ktuw=WtTinuWqy!`K59vIq}{d0O}?r znfCnPVt@UoLmGzesuUb!$g>ilcNWgL8Y>NR^uD@L6`KBO`RZ# zw-3WPc)~(9H8S_S<~4+yY2RSWFZ1M&+?CegR_V;eG-fFy-cKHGa0kAC^79i6sgDdv zARopImd9eSQByYZiK+%R&8knhB;gEnAFcfxfG`u->67dAbgpLy=4mY?*NQ1I1ON+R zDefrYabTk4w3=E?4TBP&Y_Kq=xqMF_zUoJO9^tT%3?Vdvn1a?1D{$uV&S51IdTzw< z;hwWUgUdM%7t^n$7yt@oAn(`LdCtMPk;hzm)TY+rIFz9>a{sfxNu+b4Kr;+sQf0kje!qD;hn=y}e$ey=lu1-s7%YAmb z6lj%UB=)wOVd^qjtNx~PkXW%$2Aa7v6x*N48jG&JHa4lat;`tNtPdZxTGEN6312Yl zrFkPY{E?lbGb1Lf9trBo6)~Q~EoXQxPPObHCFjFY$%jt3q`FT0L~;f|G>LBnX6{yz z!YiX;HM9slCYS%?mm_=me)QYFrhFa?1%LUB9i8|ms^w<9eL!g-2)j)eH_G@P7PE#A z?p$05T^hxf)5GxhUl~p@h=4~B-oSp-x^DVP=#W(BO2$~qq;tTu&%XXJ$e+UZ*Bc>w8AqLegYn?;zTkqk;I?NMbZ zF=B33u@s;&0#nNG$^env{21PBYv*D1;D_KXUn@wbZCiC)B4Uyj9AZ>z7hin6?467k zXutBbGUmaSWu1#g*dE00mAT5L2^8@^1d!Q6%D5x40s#3*&g;NZa)&-v+x*loyUOd!LN zsB74K^L$kr^QG%+ABVEHdh5NxI+3}c{FDb&%T@1||%Vft-DfSw7_x3?O{xE{sX zTR(wNck0h9!>)SZjE}zcBjKI71m#{zkibdW zrIxIXquwoIxJ0*9R04cKN^+H9Vyd?&Rg&ty=|W^A6sQvx(ly_8f2cjVG~ z<3d@h?$aa5QyS>6H~{cv@dE5l6GETk#l$c;P0?Edw15^SZqw!n$Lb1LK<7UC^_n3N zG%0*dPb6IVz;6M-;<^8~0IUSP?5idC=dtWVgAuNj?K5a#bSUQYKuzyUyfTReQQjW| zq`X{2$&I)E7Wh0`H_vXYBAIDR=so8Dvf)~BCj^iBh@!|Wx0Gv~F64A!nP4iax57$; zNJA}{X{D>(`(TC$v=CQ*p!9&K{TRE&LLbU= zKqH%*cc6vTVdCS>x(;$IvT_7;EO!WV-SHW`83)-Hd4Q0qX4nJ7U7i8BXJg773u(b; z(^sah+e!Zx$UVHGb24SaEe`0Y{L~Iy8JJ`*FpjC$ezNHB0MJ7nP1r-ctt>s8y2vhz z;uRC-pYIljf5#dkIk2mhoA*Hrl}EO-tbYp}<;{K~y}%k)asK1wR5}Kb*Z2qjo4ghv z@fSNxG@tSB-vY?`G)x6dK|MOR#SJ;jKi9o+@1BlmUKk0t29#<6$k&@ZIXpW0e?_>~ zn1nvv7q{T{@XPlcwabLiyYKe;@>;atH-N6X3v#`Y__K zXFE*L!`o9Gp&_aO{W&vc12!53% z?qu+|@tG8bxfqLYkhcQX^`Zr~Cx{(lv0r9C^2oge6ezHgiub%h=(v{vpo>lAqq=QP z5R%kF97moRKT{G`%Mx)I5l@IhfPZKgd$vBVXII}Nen75YGis0o#{V8sS8<6>M8EoM z^+mYPHkhxRo*@lSh$GXcOD@4u_hB*mveb6aNa?;i8G&?m;E-)o2hi8g9qw%FiJvW) zda$&c{_HeSfznT`%XSpw(58!`CdZM@w|)TC^c%+>@R75C4K-B~OfBF`0^)O4-M&+} z>AzZ->E381ATstd5c+Tu_SZmu~%ZC&K%G@oJ3Fd+)>3a)H-@wRN<|+7!G*C+tj^^iwmVwx0{7q zU`_q6pK}}Cq zup$hy#Ix<-(9Q)aRg|@C*&eWDR9(5O#qG`A>qa=kd8^*Hw4JtDwiTCbW9F3Yp{EpXE{V3HF7 zuZZGiL<>}ii`B!|a@xpzsdvSLn!+amARQH0wQiGD+1Q#h6Uh;*%E9uY^KWL0X$q;L zhYOAEc)RUYW76pY4M$I2V-~{`HK>yv8vE9Q%5okV!ELwcK+p>{Py=RZ3$5JV$=I&~ z2=3+6^?Ky)3LtAn7ypcgUYv@tBsgBKKMA`vmf;dRvc0qjTSzSK)p<>I`HhDwET41zKQK>H+Psy@Q(QK)!vQT z3l2m&%jpKiuyV9)jLfXnmSeC{s%x%Xn;3|COfNCILM9Y<009XH@?e7x;SwC>qvG`W zBE6w+e+zVZD&BRE=lR2r@D?a|y_igE+lO;+C=vY`p51!LQmpEgv$ihX`W!+VMeID9 zx-|Ig6wNfz4VgS2i*9}kcC0T^fX@xhO-RtoDXCrv%9ahCZe()D22shU4!<=Z$51d?yPx z^-*m6FaM<2t?c(TMFq`wjye+5lu7I=&sR)iWq26I&GjCR^j7rO;xj3{{~{b-%H{SJ zf?)TulM4y}XYA*?3gi-;olHf+>8;l3?X{Rhq~>c9>j1!a2=y5W?6=Gw(J2Uji{liW z4G&(vA%gKz{a!RdAsaZ5F_Cnx)@-e}ZMs`bWv44Uuo@7#T1@ThQ+wmCy$8y=4tYSw zf)s8Ydyqr;R<;P|*XNt7$rNwxi4_S@Q1_+=Yu>`$jYmROmB|rHRD|J0$XAuHutFZK4 zyF%yJ00ko1jncYu7l+V>*j@q%XA+CB8Sf%V%MQzr_sA7$MmC5J$p9R%SajTmmxzU8 z-@XD)J#Uk-zw}Exp+W$F`fVmUzkO^ZkqHV}K8 z$c`p_EXmp45xga+V|BT%bfX7j=j=yr2t;&MUN5`bW&#yesF9no3wu2BY;`CBaw#os zxcr^8_Mh+u$1HH1+zE}fXyL8R^a=&H2uvMSykd0@TTz-t5mr{F|)y>&w z<-Huyh~EMk{z`pCxsPv%x?mjcUc*s7PP|%RX_RNNq3c$LMTI#${5|+s7)L7df{lrIW2B;hR)_>vP_~dM6qTLKse?3e)sQ?N$646a|JAi4g@Xw zRCxENqa3s*rs|6H{nt;%mu0Ev%@%YyhwEt?S>iFo8f6j&tMRGGp2EIbUUo!P3*j)1 z=GW($)F(VnfLxpgKogHvzJ^MC@PDFYEpN3!&Ti%>Tx-U6SJtqr{ zVU(^NNSst@$V$5d(|Qg4+Arg$GFhki_|>#z2GJ(qSf^#i*oDpe82K|>yxOZ%IVgWa z%*X7Ixa*}>-|b6hjz%I=cWn7?Q?yXsAid#IBJSkp&eC-j%KTCIbz$4Wlw}JUxGJHy zst$bcS4jo3i4?#b3yY)4l^r9;Z$FHC>?i*=T&#QAsj&_KP&J`L#U<0im&bhADR4wJ zo7ku4_ARqWC$d`_*K8zxf>Q3JgFrq-Xll|;0gr|1t<{||o^w^$FXB!~Qutv@qax%? zmS$6v9V6|d8i$hwSq5Zt_lj0HXc; zo>gy|RQHQn#Wg&ZL0N?V@OfghqN>~Ky{*bH)`QqMP<*rif=GU%dLzawSS$o|&_m0A zXf)6DXhNB>2%QiDOJXpC#jS!9$%u?JAZWv3BNk}ls%ySXyCG-$^U~Qg!&J;hq?NyH9y$eQcZ?nDk3GjlEA+GO)6Xw9p&^8^x2I2a`-R~N}>t%M-udJ;+~*a_ryy#eH%-HCw6rH*HVjI z?66n3STDKZ{N1v;P|56l#2ulZbeH&EC%%(B0$$N*|(%v6^QptpX>|58aj(=rb;`6yT&&fuBkg%PqOoJ0z#B0C)^( z4DPpi>$%44C)VC@Oh$6R@dllokk6V%&XjN;vXm;ffj_5$h)A0)YOD{|FvSNhDiBwh z+^#2@=a=D+V{_f(3=9%X=upbov#ZpVzuh?JhogHIYS4mv&0j;d`#eC`PK`~9XbKrh z{F<^0{IQzQX%Kv%ba@*z=`DBCrq@jji`4+|GR?YSq_^0bno9#adGwg1bfZZK=1~vp z0EhG%s<;;1ciC+AgSUp&3(dSVYJ>|r^{K0^Nobr}G|5y4)|RyH_GIU7vkWCC^@ZjE zOv}hZdF(lcp%op21xowhH+L;4-V+akJ^0MEpStyARU`PKSCF%jLxOWSQN)zQ6lCB+ zl3h63vLAu!j4&aRMmSqohlijFe?i4i#c2QT#m`N#h3Pt#>(@}F`5Cy=D}tIGcaq6h zQUd-=T5IuACK5pmSjM6rfJyu7t6g_kk1!rLeai2;1Uo+#YSIO`8DdZYvGqUPG5Wq& z6LNt2<2I1a|49%sr}?>~@L>}1Rfn{pt0^T7OGl>iQsy*EYc5k3Ql{v!aho40IUhOh zLI&mE*-{1%c8;yl7nOA~Q3nd*G}6bsO&j=3I=pvcE-%#TtXen8ZO{mBvkOV}51R@& zziDsyZT%D|s_co)p=)iE7}6oDgKnzNuI^X1@*f|weoAXf*ani=r>WH&2M(I4*^hk_ zbC!G?c9p!O4u)%M#B7{MBC;~aKx!Eiq0M89@z@Q9`o-*72L|B7P%M3 z_4V8R)zwiUo(!v5u_czsyR3el-&}<(?q=m1Rg%3*)Kuw5y{UFGdsSyU0>7p z@Ikx@eda0QW0zMcyzgeHD!ZQ)^Q%v@sADtI^cH#m6O<}_Skb=n;Qk9c>4{A~9oTD1ge&pLjpxfb_XgHhfx|TbVnF|Ry^RB&<9lNfUr3p6;eTv1 z-mEb;`O%1!y$a-n&T}(Rm9GDE+QAM}Ws|FH&|b|OBT0o*egX`^urU}GJZ-G*o$)}5 zVL`cdyuopvMb>*VpV;4{51jkY0%A(U<_}i7ZWek8Kw5K86DB8HwXAEuLX*p{3f<)Y9t@4Chw-CE&>ID4W@Ki=ZfoI> zauqLuKYU({q#0-d1=0~?z01qk>W_I2_q5h5+D7Icaxw z^VmJyl~j!HPKK|hBg)rGxr3}Dqc3VbRZiwmq~&5_Klzj45zJZem6MP$RXXdaH@?Mk z%}j18^<+DOWmK);gCjQwR-O=0wP|^h{6F&oxETNMiJ<}RAWNAUv_LDgrL_eydb`cr!*|Uw_D|&9Ni-V0k51c1=uCl>N3$&cj#6GSMT8iAY%z2R}o_ zJz7d$N;3RE16^_BD*YB%bO4T-hedx2T-Gc@N2fa^#6oHJ_Of$~EYMnH`> zoRfau0(>OtQMWm{ehC@!GtX_R(D>|J0_1!`Bwg{ZOi=X?%+TDI}8q zzec*gIHe4fI9GCZEePzJB=V-eS;PD8?<*M@*Qrl>n>G$s-SybT6j3^={~6|6*DFsr zyg2&EXS%TQim=E`egJbG3Rb%UnY`|3c(!ll+;X0)U#u_d7-iU~^n}ZnCSWeMEP}De z_(0k8&x`+=>cIE=pQ$dFBm8vt?E#8KciXxMqvCl__fJ1hv8s0>f!`4)V0vrvXBBOY z|D2zXpX~}+g^%!8F6k_YwZJJROarl&WBz&<(rv3M;R8@0DhrbDESX{^(5>S>nEHR- zA()Oh15_Qu&AFFh+)uYR&CMH<3s0^*Z-M8o^+s!i<;hn1nqhbG9-d72J1YqPd|ka#&(Q|)I#aaSKKo&EJkBUrO3 z#k9QQ5}+Yal?*MYo0g^;3@Vm8P!izK3D&pY*0KD*)}*88?=AneBs~ImiXF*{T-z(` zxY$su*nhL%el|_AqeAb1*gqqpUQ2(BbWduZ2w%-joXMp~cj6&9U^=BTI3=s;>C<=W zqw=(qAvWum1MI`PbeSRluTlJpW+RfsPbrW8`kVClNJUxM39(>6u|&6xRD)LTh2$pO z|3vd##rytp++B9i&1|Ei%C6dqE?Q8MaoJIJEpo<{`{i{GVa}RSX|mv_?*FfM79T(B zm~}-vcZ9_f=cQ%3f1+m&$8O#>ej)te(};$e(i)`!_8~-qU0FtVGy!cnkfR(nc|RgY z0I4cNy|!I2k<<*6RJ)vDv-|c}KQnLQfA%H8|7!-!744=vnJA}5W2H^*i(o0h)e-&Uo_6@wIx#O9$iQ^E64ZjMtOqvNS!6Z;>PI+XzSMXlpMy`YY!Ax(3xZY8vOH*|IAgZV84h_{@EM#LtHD+HorTy*$*s%_J}>$ zDS7Z34>aBX&2q}oPRJm~H1T?CH>Wp9c4Dt@;#2I(qYM^#?o$x2xz|jdRP_tW}m)HG&z`xtkmGK0P1X|bigO{&yR8X+JtvrR+SpA84Ja8nBaUX8(tN$0BS+-hl^fZ zGprAO7fY#s$N~!`g1umeH;43_*7@J7tj6^o=@~$&jyAI+0B}!2Sg{^4pbXyn$I=@4 z-*S!b|Hw7^E-bAIaSW3RPgwmWJQ^f?D@fV^PB~)>NEe?+ zi|E|=>I&umWqcd+(81W#sgB_sbKn5~%<*!+r3?CF<-c7nyCU*0ctxH4&-CQh`7aFt zHR1{6{;q9DYajc6q?)JGN2kJ0=R5CuKmIK+;Pr5H6}O1o6@;bKa8J$eDjW4vIY%Y; z6ulmvag}xb>KU!D_NS@IZ+P8J@UEQNH#gkPVT-r6=)WwBl55jam_dtV7;PI20{yQas zua;0Gp2s_8GMJj@yT0RjBOxPjt-^rqS^x-XpN3@GEv|SU{a04Hc63ME=FGx4i+NA@&<=syvb_^Wc8X*D$Y#vGHOUN5 z-U30UzP}U0)$WzmO_6euGNF1bkygy%LQv@aTX; z#SWTUY?~IhUxO%TEA*64H^g~j!O_po4MwczB$vc=6FTr-Xe~dWQfr$GiEu4NiLBwX z#Qc#w`6sU@+|@R7?`0qR$e3VC;^~7ePcc!-72Cv?M?he#7T-C2PkI(JysdYvKFO&E zV>SX6D_crV*DfHbNh_0ChC3}UZE91vvhO}JZf;+nOGv+RX|ll~1E-`HYoRTzI_HT; zhhC-u?L^Qg<7@5^;0N5Unu9pkYZ(17WXW#i9pD`cDM~zLc#7^9jsGaG7FMx)(s;hJ z#@S0%qZc26<~OV41<18HE^$bs;3`Ks+g!a{OrrwrnNbsi7ghBU^cqm9qD^mPckxN=GfO|Wn0Ql@FWI3VGB^0jA~H$bin z{3EuFm*C-A+Qu6d9+0w?oU0 zv&?X`W1Y_bN-orC8*scZYG1#TG_!wFqZSb4!^rhK&j8B?C=gzelk7ucU$be7GZy{` zH{bc7Jj`&!xRJw14vFw2k^^N-aM;IBGyhLNjrDWNY>%Dl`oi`8IFIsd7%kojN8T|) zWT6yq^FCE~&I7g45-}7KviGX>b0@oECnx&xKTJ$;UVi9&^OgG)|+FSjHbrrtDT&v4nBC>@33D4@OO#Xr({k9CbLoX+NiCKRxL^r6yQgiq&(NwhR3Qq-M$} z2FPAj7$}6e0r(eEo{H>D(@-$UvZTG2Z#W>d*pm7y_%s zt9~4@lsv|3XFvUPfcN>qQk)7aICf|IEhM5D0JKU`BlvAJ)lv{`pn19HpVuCV=lgO3 zvQY4TAJRRyREt;}Zc^n2o&w?Es{e@%5}`>#F5wmjv9T-r@ps)|FGVQgpp! zi_;3)g8g7)dAb=GNJ~o=;v*2`0TM-}IC~%GfAD+mbe%j(kB-AfxcwHe#SLfg7WT9l zabH3ma+HSQ6vBFGLSDixBE-s+5YXZPr1E%#S^+>jm8o7bS344@*?Ybh&czwc{A-uv z5W>%+w;vXNf2Wy@tBWZYTXLjXJ`7~3$CAQFIVC(uX~e5r^p+n4PQ)W zD`^N*nSfdLtti*?!=NI6F@6W0MUXyU0o=_z)7e(j9VSW>!YyvDl-8Z|rAGpSHNpT< z;n=uOJA348T;du218NwSL!2r@zq(RQ>4N)wQ*Fdi-5kj5D(~Ux$4q;J3IZbq_%9|* z4H0d_AnQfgETx)YrgG!&!9!_~v{WRqtnOaL+RgdHaUv4#U_5MFwF0meUfgEq-AceN zu+y?o2!NG$E(EjCl$gcI-Fhsy=X@~pe)r&cqx@Psu~!X8%eaaScQtgie4&rAcEwia z44~V)a$(OUu+aQ8%yz*6cZE`|=P>^3AjYKdVLrG~QXw|0m6=0|ft-D}fEh-#1_Bx> zN^noY_kNnyX$;K2CyQb`k|FzjGkT!8#Z+$~KWMyY3hH{Se&KR0T&Qa}}Fy zCFT`Y&!2tOGK#F45ADjj;~W6#x<7E@3NWLAi8qV|0sTyo=8iZyBniw)ff zDtPUD?+qn66};vb>f#&yhd#VS{fbnry;e2(BsL zGERw3c*DCqIf_eo8Jj;z3lQ^C>A!U@ZBaKGJ37_R0}{-Ax2|uMXq^>q>=I`DLE;k` z#~bz}JbRN2)%&WBFHC_-jcbd${;4ljeSj_SNdz+{d}yi+=vI%TuQgdLg8n%$L2SVd zdWzoVRFtsy-RS2GXizJPtx3UOrrnE^Yf5NhUU8p#7oV2ux4BgoUx;aLYciw2#0XJ@ z^`tJL)FYykf!GnKbp!U}jzqIfeCIQT2NT$$BQql-dhvL@uJpp*AyD_?TVV?Ll4ax8 zKT-A=f8oKf@=aA?2NEGLXhl;p_DEs-QSX6>O^37yk3Tb?sl5-LEqHF_k%d$2H}<29rhAG*Wpxgm80VI$ z&e-^U+;Q2F`+Iq?_{h-`zaBaHmNn!Q1{H%}*yf>H~H$JMvaMW=hDUlHw%jd+Z)O?3uEWLo;D zbAPVqQbhMU;gpDNIyFcq1`6rGPdgZj$DWc}XmL|X={o>a5``9m(u7KD)xyZlsJuY& zID;z&x$+3Hho%j#ZtSrOzD%6XIi>xhqnekl5;;1Aw6l5RWZZM&re%0$*M%w0&Shwz zrR-St=L}>eJj!g8hF@GotZ60Q+$mE$OcqR&4u(qsxh9YrvyiGkp2>Adbv^x_8cybo zPE{lgzuGSB@s*-FY20Ujo@zHdv#_m-e0+I z9g|G(n-EV}wo&>351P-itR|5)_)LM)U0tf*3|;c&OW|w(C3xhIUdweW`NyHRtO3Y}3!IKj=nN`R$d8+` z@1&%Cs44y8o71Q&c5nmukuC}1#}*>s1b@cnK>g<*E=K(U2nLaZT6aUHMOco-g^XaR z;zrN6i%2^z$6NA$uyQ=pLA<#`BThg}SK3`fmu`K@Vl29LyXSD4#sN4DJiY#5n+_4W z_r@8cQuCRcsEUMTkf`;nv6wl`wa2H_@X9GdIq5)%v(9mwn1PF%=`&ViVeQSv+xe~^zO682$+aj%WaRx^ zrt|&GOQTRKMl}P=&+;gGlsqBTrbr*L+>uwI4U8>p>-;LFPr&EGqf41^Do(yWA<>7r zO!nkkrKPw+`O>jXOf#Fz*)0511-$Ddfyy4sah@*J*H?NeuSRYj1p)1dN)ozR;az7t zjFGa$LDd>yCsbO`$$sX7%5`(~c%ejp2H-J3+kY-Ks|s@zBwT7#YXRU!1f$PCVfq6~ z9IJ37SP{|Gyt>dmB?k%-G+0ls3PxaSjYN=&yEZGC|B*U4Wu5gYnr?2$4{~rzDJJT4 zLSMLNQJUhg-x)iS4R6)Sl-uxi2G6lnY||E*sb-zDExhjr0}|zx9_+>K7DPFA>a=Bh zhsG_sohS}<>kpj4Q7l-x-cb8G`@Hhr4(zvp0mjUJUnUPQC=f%(=9(;{}p=zs#x3} zxUklek0Prwg@(@p9hoU;xmw^j1rFjYzWWTn@M_AA!ZwkrTsmCNHUKi;d&J$|y2zEN zsr9ZEd1!A-c{uZ*PvTNzQC7t=KV(o)39a4Ha7^6gaf z=5*GvcJeu$7>XTOy0jZ0FLf_nu=w7&+0wmTQ~lJT6J$lZd<^QAVO~aB* z+^}z(YMQCcX)!Z3r!*@`&0TY=F}KQG!4!?keF0JvG*N0Mtz1*X4a>?Mw_H(CD9a5* z%Uu!41zdsD6cJ>ed;ZV+et5omcpTioy>Ok^dH&AjPJ7n@ce#g05s`xmIl%qX*jVLF z!~LZbm0WLyvu+rz9yJLp{WoM#j#U1*1tP;jzs{Bd>H~%fGq_TCIDvs6uH!`E5_e59P6JTUX>%(VgX|sFC_=|=;b;0{j>%JMCb1f zs-jQ(Oiu|3wV>|G{f#WV-@G&44)FbbGT(Ug`C-;6?_#zm2y{LziXDG>_{8{B$H0YS zy6h2+u19=~lqDK)ds(?FI9yeU>Q_*1C5db2rG6m~>y0`b>~#@f{ax00Q>~$Y%NUoE zheEi5r>>EVV9^5&z;+ua2E!+p8?w;naI;3mHj&@PNnGFcOC)z-57F~|J$Cz}@=r~QyHZ;M z>q1&4ax5Y>M55!l<0hLzo zY=roEjfq=%2L*-1+rzEZ8z$OoJVtxcPlWJi;lv0z+!Vg{VX_wpFXgwkt=nzBKxAoA zUjqw1wW;uY&zYA8(`7WLpTyLv#|gvU%xwd!bm~Yn!kuWb3Y51PDVAVdv8X`ja}alh z@DOj(#mEzgtumx$x;*jn%ES8%W9yGXn_IfMgQW#ci-tA+FLKBzc%E&m6k*@$ZrF8< zcIpcGK-~+8yX?NT>KtGdZ}=QahgZmji)m{~8+XEUw{50VC-h|wxYN#c5Bv$Qd`;Ev z(&um}yB65Bb(aI60)G(&%`UNd19a|O3~m5hY6;3tdbQ>w+hCWYos>V@bx~Vg$eXkL zb?3hpY7OKf&QxbZ0nUx=-h&|qGZuV;XG_u!2gcjs1)kJa-W3}p-`a*pW9w;G{^+c1 zu3Oh!!X(g$fX0VOa(6WVNIWlMmtEw-ZQaSf4uE#M?6_M#7EZ#slQ$I1`E(NeAlY9> zr&7IS`>)h#&luKBS(=lwz%7|&xEej6^X5OO(|m5Uimo@WL;(1}4~-3B^M+noa(+#F z4sm#;5%nyg8#Xc8j{PEMMVgoF0S&42!WYH*Y>74y4siH=Uh+5#yZuM$e~2}&Pt>g> zhn;_BEPf89I!>Yi)DtVJOa+%~j!nRU(HNE{f3u8!f`OBq969&p4OZl6qWqW)0yJOq z|Ai-pBG2Zu9xg~O2cC-m3CYd*6IhKO2Rfk57WYj7O)@Ux)New};Q~Nn%|D_0uT<>+ zq~;I6Sg%^CEc&hdU#a4S+||w{V=q$qp^&yBD|=^?bg|Z_FNH;O$LO?@(UpN0|6g6F=tG$Kw1JmPdy2%8(KA z`X1af8$r!2QER4Xs6RV~HC+;wZ+NksSZPq9U3)=zUCazDwg7SlTN}ogC|nKclvj^m zxKZfqE7*)(dZk!h3Y*_|3u0ggjW z7%xK;Lj#S$A(d)|5fFwg#n6j;MP}X5kiM?#8hejxJuTsjT=9u;A#m=KH$2}OXTwDl zeQSC{9f{3YcfsA7Jn7J)EjId35SIeUw1JD$8f%0>C~q<0cXJ3E?RYcAa;9hqC6OTq zqAyqM#mS;|4|8D#U7_=qBpyPTMbOFEcKZf9S$QKsYfVg&neq@0OfA3z29%b8<|Up) z`VP-stlL31*E1`$>|^0Yy`)Fz?wL%JNCrof#T0&6+?dTpaPy-8ewE#3{zz9+q(oe3->{Mo=&>Uv}U2FY@jQWU>S zFDCCiL&1NYMt18t)cgdC=?5DH-NJJZ1G?!5SVXymi)~tVT3p^dd)Eaiy4WF) zExPX3>q#Zap{I~7WTA&tL1>HJ36M@LcK?TE$+F8_n*Ezm`*b*y6nKj~%Ps?&n%$Tp zdZmCeqP0xdb}#S+7B*dg-586rf1Dh0$0P!G51#xJIUJ};cF+p2o}h3MU<*sSy(*CP z;xoAtr6QTd4y!1Ym}DSb!N))Phqx;1w%d4eoEcRLR3?2lsauIGOndDX=~u3i?;U;{AyF5J7wc%OdOr@b}`uaNKk>Fuv{j5pDV_-KdAKy$mAI2E_+<(x4I zgK)_lzIo$wc!DkWGd%qo1h9E?&$F`m&N1=&$qDVf46=ZQ>_OG zskGQC#a!Nr81tQ^oFDq>n4n`FB$pL}flD{LZgUZV$D(e;MfgEPtp(Ac1Aq>%Q&Xo) z-7)uv=~g$Dj!TeQ(Yi7%tSGl1`a!eNA!l)3K!Fcb`3}w(e(fbM4cu7G3b`x^rb{_O z>kh&dYy@lN0TxdCkVxxq7v;|$-V@szJMt^dDBK;umUct7v?!zrOwO)oyA|P zRj&w^5R5InD!auOTAnKVCpLMbf3(Kl8J82KD`)5Xaj$oioUU`nSW&P1B@lLHLmD+)+AcAc@D@C}r=c6vx-9twU4#z(`)=)mP`eqr>Fo|B!|2?ZEZYa6r8 zCWt(!nNJJ}0pe+gI;FSGt{TASTof(>DXwRM)`HCraD|<<-y|&_I4EfVomXN>>UBSE z9Tz!C0G@PL5ks~1M{T!!rz&E_{zy(+S*8>5wQ73L{Ari9m<{LX?U@Xex^{ChgOf^& z8&(AgC`07SGC?KY^NZ|1b26`m?68%!hBJ$w!OL9s!@)>CVs=p4QQ?X7py_$i>(nWj z2F3iTD>1A&q^GzkRpTUZqepXONbB>m2fWM@-nqhAD~9x+r%5j0`$PEX#*v$ii@<(l z;l?d|ujnrmwFL$r{^i9J?nvHWZ#~bit?I&4komzEtapqEjg2Dc)2x+caWp!7<4!1~ zsxa6Db*ZP#g$-sBQw1LQ;IgAZPc{Jx`LeIP-Ev-NLct|s%56anl1UU@-Q0;Dtf)@6 zQ#)Ln>A5qaPIVwONCzwS$`cWju_&*9rQ+R+uF+48AAm;!$pUvYkDKao%TQCN=Hz5s zD;0Q9%p)d?`Q8%^bGOCaOa(Ru?gm4IxtWQEL6G=$tDJk*f#6L-Ikx=N5^JD<2np_n zk2q)rNmij3NEFqBF6`Q4z9{?9hm@dur#69BYEN4Lgapa89`PTC(u#9s zEh5Ogj=Lgq^PDqu(q^t(j>@E}SApA%Wp>n!&4bZ8RU5#nfwD+l-x_in!!@`iIOv#l zk`}VGWV#-QWXJex#Gch_Rh{9Wf8PU8dPf`kNPE2|~}M*ff9)vrfjr z%g=BpYGoNIQIO)E2zEuly%)uj<7>UqZN_)@$zE}7ZPl?n0jI0+{UBl)Gj%UD2Q~Ka zUwnzy)Uio3!2`3lAhjmwVh!jz*+q#oJJrNDjS!U9VxaQCjIlKdj6vz>3h z()GH*SzAxb**_Plt0V7*OlhwfE`7;aTjUt#c1mDsQ019FZI~nu7@p8oeY&ZrDIM^; zX=$ptn|t+DD;Q#1^ZXtwCN^a`j?(EQa9OO{5!gQS6`Uf`SfEgbggc`&ZzQRaCrab;5ve;Z9Un{Je zk%fsSqWZ3OmqC=(lo|(+_Zckj-wmZKTEr>Qj;DOg?*|IP%-X-KGQ>0x244rbTYLBr zH-mK>6%##EU;Lrgut#AR)YeeyW^Jwb)fO`{EZcQH_K?kq61&X0hv^I|#GXq3-K(Sd zJCGi@zvLvc9&arLwDhTJ1#INT=^Zomp9zf2YZKID5{LCWg2fxWIGy3xa7FH3NaLu} znbnVd#N>huT|PJUnDni<8}*3Z7zey6E@D1-I|W=+C%kD9#(rX ze4DydN#uuj-y1rF^XS0ge5HY(nw8)PZK9E*-ER5KatrUMN|xWEY-~(vJLIK5B5FRR z34mOfM8`b=#))-Q0o<$nBQ3rCdAUq;HqASudseSI);CZ!O`yYNXid>hHQx!_tG9AaA%6BO>G4Xk zpb-RT0!sgENzjW-v!2sJRqtj?tt`?9)oS^&0%CC7T}rEsUxe?Mgo3x<*JK*N8Fuk& zwwMF1Y#KhzTKsUAa`h;r& z`WV6;)_O0}449P9ZP%mcRZ>3=E2+t)3>Rh^phFrtsn{v=g0|CHTE#j&o8G$WKvOan zO;e^Bl~%Qm-LvOatgzJBjKRlYZHvIDq^tKsf3R2Rdq>`EAN8~GCf$B65$qrN?UVs9 zS(!2$H;fkZhOgzwYHB$7b&gE2zBI)iL-R)x4H)~cu+RZs1jc3Ymub?FVB{UnC)bQO z=G8CwV0;b))LYkhH^^e6;^AXJI;^?l$Zu(Ochl&> z2vvi8jpnWxD=paycFMftr@e4DRwiR%)5;+9wk!Q4W2(T8_z)W{ac`7k6^A=J?fs&q zF~cbAU6yRJ+f!r1b1M&?g?iWDB#>gQ&(kxSU$}JghTkck>w`q%IqiJkshXtBxs)A( zLJXnr{$zy^w(++Wyi5Lbcy6JZ%^AXb)1Dd}QQd;dGHhAR14k96wa%wFsN`fO#hP#DFobu@p&ah_$9Erbqi98@rYf$erf}2-FcFc0_b9)A&0$@r0OGjEfEM zG9>V%N1v>{v5{3dGpy-h5*I^Qt;3KCOlrFVKHd55roAeQ3Z9a6JZUz{`#5Kpq_%6L z=Tjx4`mmM$EVU6B4{o3*+q``lAB`5%gZIt&jU|c1PQFxr(@xb2??_ETDs`U|3q`PLqa$2K2^tKss-|7&ozz>w-vT z!r#Lg&dH8?Bm4?EnK%dv5)ZNFk+i87Yjc4^XmNc~9Ip27eU0Dv=~LG1x(!D^ha&=nn^k8m^+70Rf3LKN`JOjsfgbEi?Lab z{BP|Ro*qy;j_6IAf+BX|Q6rA6Z(98-J!6-{bamSaa`Q=-Yj&#wdpu);1Ul&--Fso9o6hT=b&v1^P12T&}Pu9l_RL1!56Nxn)QdSk#La*E^_{ zyNnx(QkK!qZVS8lC;BmS#cZ%fbC$)j42>%2x?caasDorbuS4(;O0vzn=XzLB_a>Wg z^y1;(8D(Zmqd>GuR6c*|*+k)+DGTG8=HXCLS8CY#tDM8lF`}>hp{A6l9msQ2;I&E6 z`IqIG)|Zy6d4t?B;mz8X0?=L|*;<$qrIIvLI5<{G7N%7x;e*vbG)<@6x;hu?s)5`) z=xG013 z4nDCEJzr!Qto&NP{ftJrmdR_B7Hu#Mpp~TSH~1y^`?*e3u03M_#G8PWLfX}l)wszj zi>NlRm(PXzU733xp3}cGBd_YaZm8B90)e&kFS%9AzVrQ^JZDR-6u9GKne#2g1}9sF zbxSy$G=G03$~x8J{H8Je0!a3_xvaEKOV!x$4N&Nrsz~`Ry&3{zQrpev8WMMO3zhQJ zuuYvuJ?#sz*_rlbwx_I^+22rsPo~7Fm@tMPR$37RG zw5u*kanP1Su_qX{t<7Cifalr;j;!laL;$1LiXn6A(Y>~~o8Kxfirjosn;UmV9F63; z`Pbju!r>E~DStPl#xa1#cYn40pOo<2iz^J;7yk1>UUd#JPJYg?%`P}tsWOr6>$Cos zMQ#x^D7oumKKId3dV9J~MLEc(?zi5ub5q8Drcl@czgVc9ZjrrRU_DVm?NEy9*^n>w zBZ9#P6LrI=17cR>D)r5w3#TVM?W#^kK6uQ9i2ju_aEiV4YqZbc z_3uPAXnd>lTAfY-+)1$I^n`C`Kr;Z__zJVaRN&vk!W39VHahqd9&W+{o8Q-~sqdoZ zs*MH3mJbl`Cwf{8x(e|(6!Qd&4zJw4W_v{?6@-JTEEe(MJ^dj=cc7ED6$@YaG`O#_ z!7VAOphF+I@0!olxP^++&L$&gJLha^c8! zqK&A_sLONaId3ntT)RO;)$kk>p_!I zfAkihhG_)eM6-AO1Li91x){_T(uxb26*2Bw!KP=Gmiy@Dy9Yjs{coInJ=CiCmDcjQ zo+qlOMBIimC3K8%S=w)B{(zuN&ioG0vyeUgU`$BCosqEdyV=;*A=xALpWNo*^_@xe zSf;RaqRH9(-p<6!3w|QXIZ2$0iY=q;sOE@7AV5{B{*&KY+1xA<91|*phYBDC7P^M3 z>J4_<*Jss)Ij^uXbO$hXXA(Hw>giQe zZ4l%T)H2WzfDn@D&_ZA5F|QPXLQHa0LrG}*+Gyrh?HNi#{?kzt%8XrgzS_V<5=>u-Dl_AL9If#JCFdynCZFO=v=a zuT;>lAd$sZ<$uxrYi8If*}+Jq_AQWI=P*6VB6^hO(GU2YtG_^Zzy-+d|4)SWS9p~_ zZN^bL=@@ndo`tCTz_(RF?C1XqK)ylX^jAVO22X};52kdbW@FpH z|4JRB7~E2m`ES5$Frj-dgU5t!#w(E+v4>aBOxP*V{?Imns! zkIivNK`dAQ758o|*BDBi5(Wa^yvUSxAldMuEBuXp|-An-c5ICsG7r61b#d_z$#0-M(2W}{e2iq)zC{dz;zjlqj z7B!clj|&45zG~bzNX`VGDG13($OeJL^_{c_LsqvfjkWrwh6V*$ydgYM%fhh8nsq_g z2xLrM_juNYk)T^;<+zM|LEuUWYQ4EM#85OOMQ1&Pi-z!4pFRS_ffv|HL;gdFa@+Na zPo=vUv3vogQpJEXkECB8kS@>1;n~H87N46TWtV<^wncQgb67w#7?vC_pzUXAa_cK5 zXGOzKX*#%6vP;s8TZ z#=4Qdp9wB71H~2t;#}p;w13o}`8jOjWr%BlW4$XgS%D9h%rnKwQVwQSZM6wi}V5hL>1 z?P&mbA=iopSRcz&8rD@j5$=GVTA^g2LRY=i6Wrp!R6z*I&iOk*Ih?};VAi2bc~RT8 zK=gn;(AKi!27Wfod|U!{!7J!?fyjK6c`-VCJ)bEtiF3m{pG;JT`@0Isu>7Bhpvc(G zA#4^O&bF|w_=tO-5HKt#2LN2GpC)mxDO1+M`%zFN&^NICBdSbOF63ed3d3-{%$;3o zb(Z=0d>o?hD_JkYc7eJ}f*+Ub3PT*IpSPSECGj{P9Ky9VSTG9{NtES9~oUY z_Z8;kplW9)Bg!xf;@5AyI@uCg_;Tty4nEWm&cLWM@El=S(%7b{GQfN&-=jsNnOW_XC*?@9itXuCiy!by_~J0XREs>Jhlu#^~)Y zGrqa2x6f4dPeZhcGcvNO+C^0}@&ypsjPMbfx>2S96$B9|>cBwP$ff)f?wA-)#7BZ1 zHqpnBv8|4KOQ$6Ro`v`vb9nE2tL^zxSr=O7l(mM6&JM8EB1TV_wzNW;rXfuHmizS| z*oiwAJ}_FN3*m!jcBax}Vpgvle;0??Z_dP%kvv0-A{%{5mU`n@V*vsJwCwyiJy8T* z;KV`pGR}xeVDbXb7BMU{aTZ8wdP9j9D;Trb&&JN@cloe%Lo9gZF&ka$9V(Wpd387O z7A=h7ItdL`EW@nL0w!hbi&fJ49qn83{vvB`@1h{b%Tn~f`ZvP!V+{cwqxS&WQ2BDr ztv3b5(jJWgv(L^(F~!&2kO1GMSmcz#3gRIsYFySkuIu-t3f>efi^2hWmMlbec%amr znqz~X!GWb&PuG-_+Si!vgpy`XR*nIoOz1?^nH>X!*~9JpGj%$RY=39U){j|PUF(`^ zyc(axJtOhX1D^|v3Zd3|2!oqqMkQJs@U8g-hY#7qUPr_J^FyxWj#-HHV~RRvSyk$VH_?8*k1(0xx~e21HtM?J z7C8GaVZy@t{6;m%^a{X4W@(v=frw{#`gX6->qks z4DW<@s|ZI$g!fkSLlGVRU1Wo>nlBVCNLD;d=#AD?%}Ib;d9Uk;=>U+;BdNAaxwp2q z4lBbqiC(wFwQGM^HkK}R8%H+Bf@6ve=WDu@f}n9J@QMWjJ-Kh0w0@7Ve6t~A<-;t; z4>CytR-=yL6YruD%B#1VUz5Qh#Vh%+7OOLfsOAg~4ClgLSz@JnI(y#n^!WTBjq9!| zB86|4qhzm7`NsP~Q}qqR^yXWW*jC)TlEO!?w9aLZ9;dBUZ5{=AkG>w-^;h2vy9%cX zv|2heakCjIU5YX48*^bE6@J!2_rI&QB&&+~Ingef1u$*ZL_tsmr9;q`(BRryBZv1z z!*oL-U~h%+ucsy*_YB+|P51Yk`B&=mm&C3UW{VXB_F1qOSCDC1H3j(JufH8Qo{XkU z_HhFG>5G{j4JAts4=N89y*^CTWTqoJ56P_Vy0ZV9&=6|C{r;$nbZT}A=nV_|#T7wWK9R??g;$?NzHp1(I&qsuW4~4r}KFD&3 zGMO-hFeG)}{!PA!VTdhi63G<9B3^a&I#d~%I@)$5^Pu~}tN8gG)+e)1iyij+woekr zC2%p^{UH2Yv1RB_!dlQ9pZtsY=a{~cpFya(>N6Gibe1~kG6)WDN`vke{U?FD1o%OV z;N&|a((BckEG_5jt1ex70%_G+0v8jrV2SAIp=s%9v@`FV{|Ci!tQH@fqJSQ#+iA=t zzq(1j#m{-v$<6pL(Sb-S96uP=V)3I&32NRfjK5HOv$7cnER)9}V_e3|$ryE&174cf zqY_roNG}HI0c}vJjB;+A3Fav|5e+!&a%`nfoX4syE=W}!IB_!D*Uv?vao=Ayim1}c z;fC{mxmQ@xw4IfEf?e_V_pf&arJLN29eQ(v|Ili({Ir$#P=-S2KuL1uOh`dRm|do@ zKwFqITRM9t@tHXt>=0LmH7c_x-1l%I*e_HS|r22`Gk(Z*9Ey)#sGOelKU^ zrvZ$U95Yc)j%D?g%PCjipAd5b-o;GaF<80V`!U+^Pfp6+3q6D$|A$|yM*Sv8S;6;W zuCF@x`VLWMXHg?vy-jJMLm4U9{SRv@Tj`2U1lw*|MyNGH_^ID~s1kXy0#1xpB=(Y_ z+K6x*Z?EE8w}G)Px!jY}!(?P@be>Q7LnE#;kOVy2S;VObYoFZN>b=A@1^YG!7vwJ6{s4iZ9fB<5i0h0sdl!jo=w(vjn68 z$R_=gQNTY9)IHx2k)m3GpG?b#qhQQBv^PM6tt7i1o%|TScz|ERE@359vh^TWaNg~%94~fvjMEm9gRs1P9bIIn~gNueZ5+H63qufLxdFgwuBk= zsTU3RZ$1s_z_eA8f;Bfi9~j@^0L4s+2XDR`-(+tVK11%_%|=LuUq|Q#N1R!41?FRr zfwv!{AEA3?--MD|_aWLk0+Cw(XHT~&r|RrFJYGe$yumH{TBq5#vC6*WF}@@7cHzk4 zvBfr4P`S=CcC%@<@h`=HGds#JA}BiIib{^*IVBn6xBHj%>O4LB5|*4&slaD5`=oo; zXeO_`&rALr9yOo(s8rEgMJ=S&>2+&cr%+h;M4sHV{An3~xgqx3&cY?qx&d7J{Oj<*6@1a+fW zT6|YK!GA~A5e_?ArIHBy@qVJ6-XdgP7q47(ehW99-~Fx%tnq(+)HlJG zq4}D@*m@mdvcVmTETl^uJ9-#YY$yj)F(0}|;vCUD78^zPf+X0Ez*+u3CyS5Y1^oN+ zbln~u>;8x2JA9mb0fW@cHrWZTvfYZTCBD8$gn1tgxpTPDV0fjAADWxR9vI(Ly@O)1 zbY8*xLWe?0vWLcfAbW94GH=C}Vk}-y8CJ1Txb?;}`t>Vf&uMGk+Yrpbp_6-vzs{J} z@*G-8L*^?Fq*U?-s|o|A*DQ&dDdmmEhCd2a{{Xs9n+9DRCf44US5q0UiodpQ&Kehg z_T#WH5~Q!NMvckRHddUMwRO1Ps(bNA>3D+#Eb5nW$!PK^)3YN_dq>HF@fQhHD8QWu ztjYy`B1H`qy9YHb7{-aqjgrUDKJD4BQFSIohgY@4H0&(2b}!W>>w@JB(?0Tr2sX&^@PwWpFOk5qYU<$N}d87G`VpM%@v< zx6-*7O-V$s)s>(qnb@lxPO46e)0y^c^eT~k{$DAJ{{Z?o^am}^lH^1LhWlvmT#}~k zyuR*rHFDIS;F~-+fq_cmDjF)O2UgC=9VRs%x5zQPkoxpyn9ZJyD}Q)-BzDKT`a|wA zGJFyn_Wh-hm*HA58vwBtV2`{fbh}jdj_>s}}DOiHmnUhAL>gmCVXZ{rca z4)0T(H#@&pAb0Zvc@)B|>pf4EYX2Lk48NXf^~4*^Dz;ZR5Y^aogv{{)XM|rk7xZ`X&}iw=(fZS1%PU8qd*-vD=oL$w|}%RPFT0 zC3B}Y;vs|8o(HW=ofSAqPFd4o+67I6(XO}x)&1n@>Dx&(E6 z`@vy+$U)MG0ayq{hUCSUH#RQbuX;8YFv^LF^$SV(+c9X5$hLlnodK`QqEG!R z)iL<45JzoR`WbGIoD(MC$25njhJ8`}_d~%LiW&;p(oM>uCn4t9@;*y3>Jv=a|}SVWWy3}@i6QSQ~IL(+W4RFa+(g2M%=Oncd?ydHcEKJ z?O~;C5T-Bh{HD;sd}y|5?_6R8DKn;W@EPo7=x82?oUoj_cC`Qn3BE_o%9nwJHcz&}|=ob7rVatiF@XHQ=!_#iI-M@J&R;0u(~3~@pAyvZR- zbSA9LPQ@31Q3H9wdVG{~EI4Ge@6AVBmgZMHeyc2rG@6Tv^qYiAwnalb~K0%05_e*>O{B!dn|Tc|KdgOoH_w?Cv76bZ7=9BoY9J7Na(6QI;GNU<%oB9 z4iXSJ_Xo|R&<34eq`+4ucUQ=ObZzbD$BqPgRDV!3mmr_5@pyjBgvNt2x349WkiGT7 zY`sLWdZkz|!+OA$L52xDUKkKcl{F`a8t%Wpp?ELHR)_}Z>y(bCz~to>X(Rba%=^#a z{3zH~9@{n;5tW)~F~@5?M=aSqI}bqFjm^vhwt2v|H|h&^%v|MPDSO)uwIrUm7$g~` zTOL8ZZf1y~WeObsyCmG|4K~rCwZY3FmD6IRJdqYEvWP5uOl?RLo8R-2`}?l)kEe?Y zc=qv2*oB6w@XdU%aveX>Tp*58#IkO9X+7}<(Ci>v6^^(6K0s0o8A%1m>$OC2dOddK zOtl36J}4?!aE0lq%)MeL0U#mgB$)rzW5*aWC(Zd16VH8IbBkGJF?fexbEIpOBMUY^ z9`+y@0KSQ3c4CWw%j(M#=J!*qy^DJc#Z8|jg6)P%$j)r_s&WfO-#1c0<9nrYSSiR` zh9a)>7)4LE>hMHE|M{$MZ4oFlS)2}JRwyzvM~&^OS5tJXw8C$aK3I`OGsj~CvJoCGOB(kqMOJ6!!Jow5R=px^hZtdfF+?P3! zJ$6Ti?$Xocko!KQb{$X+-u`Oc0aa#7xR(u>Vv|P$80xsP*0Cg(!9Hr`mEU|1PC6gg zu2XJnNvl~CQv`IiK@w0=T`$$iRMCv}8p^A-Mu-AM2ke|0!5?CM-~PG|n4A;OO)+p*eR%BDCQHf-+(?U zUy1tHJ+5G|GCJa55mW`ps_$C9Wl3sveeQh@O*Cz8f}P= zei#=YB$*D2-ZfV97;jo1RzKVt_Zz(oRnEE(DDXKq45T)z^NVwG@TVZd_Zfh%*9d{# zFZh7nHO*0$SItQc=R#ncv0kj_CHjPV^>01R?&Rgt2=Vq1s^T=TJX9zAE47cd{jh|X zNuvP36?iWRnfi;b9 zKU{XXbGu6~h<<2vn(WIUnXT3DP5AJkDef`Ki}IPYt-N?kZjVhnfw-S?!CGMcYGZK5 z53Fn?Y8BHYdRfv+34}ci;uadU@!4_r+|!1-<0fbfwYPxX-!kI18D%3p<;99318Voq zBT8TcEYzMb4liHBZV*5t(D(>jz)#ypse&Z${>vhhfl@$mr~vVyY+|UJ_w2Qx5kVyo zyC-*yiecAoo_~iMj$M1Ov%NhGlwCFK(H2+M|Aga1R|1CgH9etS$GX?lTXr~;q`_4X z{f|bDb7}w1u=OEI8VAoVWMoFH!FGx+kd!_tx;p=*5o`Ud7dGt&(~fPv6YvW-yPC=Z zG~;kk|JT)9slKgY7EBXtqBdnT<-&*3l%tIX5wIC%o16K&=5hn-y-AxX#X2jhz}KJ zTFgX#e&9gZeEZw!));D>yN5+=+A@Q6YtK0DgOuCw>GN{(dNRD6A@hZahxZKL0Hw^BQ)>SBA(^*(d94 zf}LzU>9r^T1HHc);2;0=utY^nfyZrXtW~6Vk?7b)P{kkj0-RhqZY-5Nr(-wkhg84; zgS~5M*mU<8^usB+ff;g?im{~=rpn`7<>K0w{j@kWgdo) z)|%SJaj%mQay~R2uCi|End(8snRmxjK^zlP1ho}t>0qVJyoIF8zfR;LH%AftFQINK zIN)|wVDVac6~2w$w@=m@rUU05U5P2mk!>voAl2Hgdq&o2x;4IT5TH+d^btIcE`I zP4s;@#%h<`ODzdG^;_6oSfeC}&Y*x6KJgGdjfGkgy}$+yPFJf4Jp- zL;Y83ZFSG5O;fP3eCOE!_|5c~5dq_c+)qwH8#I3S-R-nYrXylpjni|^0u-JEFJIOR zHaHkmK@*Ilh~~2iU?#gqSG<%cHcIn0yPOj0bm7={s=$#1T}ccgPEGWB`$=92-`y~h z_*@~yiZrM4xmrQ#H#N!)v&TH)uE>7%9m1u~8PS>J;qr$v5%LnMpGhb=V(4STyAR3tW&mp}-l zh+S@eWhAU_-?-X3u_7iW`hJ!^RrzF(4&gG-M+nXryx2;q??`(G|AfO)o}Ab;`;3wW z-BfW+N4_x-f{T(?T*i*%&3?^I;AkuHz9u)+2=INLkNo*}zwQleY-s2CCRbTB0V&0K zV$h(M*`K}uvZuk>`RhQ*i|>~6YFO)r6t41$LiEJ zMGP;C?J41V{@dHbL#NYk7~ZWsQ|zLE=~JjCtLIMI1bS~qSo=gsWahvG_S8sD*vbnP ztfK#h4|k)uyBeu$a=A57Kn!Ve=u(_XfyiCB*|-Eu4>9jhv}}R*K4qpj=tRh0J)4DI zE9J!CuC=O1bJfV}BLhCxIaYPo`sfWA&zLLTn4y#4>Ezko;MnHw;7}nL-}4lGLZLYAW#ecn z;5v3&C*08gGE&X9n2aog$p`AbCklM9WYFDt~RUFdc>PY^h_8H@o5dXiA zi~3J(+>ey%e*K%7ItUf0ie_#mMvk(XA}+(`-CXz;>7)bDWRCv&;aJoJeEjh|QNFZF z)!i)|q{E${U5qB8Rcl>FeY8J35$I)4mK#ikXW+0`Ctf3JR15@@wOZ6kM%|I{Axz2Y z+r7arj?=xb?3i5;kp14B%T|SH zh3nk7{LEeZqe;P>a{D_!5Ti(RJ<@)aa>r&}!OZq;UU?1>Z>Off>BcRKv z>kjVh#<#Tfi$UE>79*XiH#byqbB8C=e?O&`@=XQaM~77Aq-6F zwu>a+fKoA#x!U?~LK~*=Nx6Lk{MZY_s2753cnKiCAg*o}+<6SLHf>BBcDc`k;I1PM zd}YTh8TqN{9T8R~C(|0#tof23r6-vovsTH&r;s>_SR$ z)-FW+hBo0_d9ic~6Iks!HpV4hfv9cV>T|^S$(W9e+Eg9|^R3zuvH%_!F@BdDs0!1i zU&I$olARy!%%JJ^L1a|s3$+o{T~bqy@%)=4X_uP1KRjbHVK3G93gvo24%r!<=pU%0 zmrTT@$ff&%nay5x!)=32$A(*8^i)1q1K7nOj2bA%2Z>kRn3x(y1lTvsq173vG9>Q0 zZfO0{v5|+-RVtCQ@TFcl>4oeo>9_Nx=EKN6O6F0JWg6CQwbk z&>J7dxaUBopW?J9&B-o=TO~$)t%qWUeTC2mX(vwIei_wWejIcJkhbnk{1a{9J!w06 zE0!13#%;gdv&O?}8}cJqv^Vdv$QKU&9sL5Xwgxc*F!&Jb36^2liHNSCc$v#4LQURj z-_%Td8oO~H)mYJ=^0Soj#nICXT5&4mjUSZ#C2_&rr7x0h_HGUFMuTzOP&j;|gsJ!= zOgC4mAtETY{il|A|2YlW%S!jmZ zx1<&0adl|ROrh$d?ba@>dVhNrYRc~x{@kmZ3Oh4;S^7UMI5(WZI7@}1lRxd$J# zz7UXkThTQ=f0kg|>+iW2uFc(M`2YBs=1Nq$%z5nRTy7wo_q@se$NL?jWD~lOuR0V$jg6&QvKpNtnv6Omi?I1gc$rvTjmfR%u!-nwDbxocdne>mSUU2Me0flEW0Dm(L; zvbVV7aXEQE=l>onZ>bNpLoD>P_&F^aYW44p+Vg*idiQvy7YF`dr%s)8@u`kVZiOh< z+!JxSxFyMD?w5*@%jUj?*}72)J7}0|a^GBX9p+NRFeCTNHX}x1lP$D%>H9vv-{brE z{>=k>+xxQD<@q|Qnp$W$r(v()40G1}Ep|yw{{Ca32s44OmZW_4fd8vXR15VY15X#0 ziXEm?b_A>H6sFapX$Sbw`7MyRY5;E?i zVmP65)hj~oW24oxpsAcg#-+y~mS7D|bKes4uWOsO#(NIDQchg?V!<`g{6cj%(?)uW z@nR@9f=h8E8J`$CGUq*{D8|Ilh~m*wmjaSnbe`kGA$_c36(xCh$Pb-?qrLt!Nv3PB zPH9GjSsMM3-}Xd5*E~@1CWZO#g2h~~6hWpi+XUy^Y(mD;OGnv$a{cdsp1#-+& zo;GM@6LW*1%L3qy{UvSLb=Efps5bYYt{L|$JR-n@8!P1<|?ab6KW@$(lAb4?smwnQEb?Pl&<_MG# zV3D;vR|Gs`wX!9Q{>Xs;fnx1*Q_>ayJUt&`NY}SKCvCcF-|!HQx~sfB-!60Ee9Zb- zmHVQvU&;e7at8tRKY7(;!`L%Z^J^5vS0H~&abkn~p#hn&2wNkuk@HJ|VkuZ`H^h2h zVPwX~RildbP0W3>_1qv+;a0OJJLDPQ5j6jrzDtdUj(Zp!%YDHi%aYzK^ZnDg4sYCt zl34uSd7=lBwYv8|>ia+O6FSre?ez1`zRIf(L^z^Yy>)dgXWrxXm<2@#k092mWWE1W zo)reOVSYhm#LEX^3v3 zuF`k?crNm)&rbZB-1GNPXV8FdJufDT>jGmedOKc?b5Lze9v)G{T>??LH76$I?%2Ay ze&O7G`NcM+$*V#7l6^+Tc=bsf{!CTUU}cjjn46`+)mHE9xbVlJ*T78PMSioVQbkJL zL}B(aV3Pz_8@MSauI}3Rw}xV2EG^RcM=G)xo4;erTGI_Ng!oB+uH=pIeq^iza%DE} z=DeF{^Cw?9dhuSSiA;`|(!?p7x)>-DMjOK6SHmt#kxU9O4;bVLtQ5AGGaVcfn)M`e z5TJ~th|l{2(I}hx#$4mdqk|$8*@48eg1k1S)S55Jq(&1FTWb3X8hCH*^7t?Bff+1 z-y3SHPAc?&r^TeJ+ZSJQ_J0w4FQ25|5p*yL0B0xMtIdQk+I{kNH^&}Jhu!F-G!?t> zDMRYL!$u>r7e{M3= z(r$q3Z<;5RP_9v3?thq&DM=?~er#@528kPu+!**8B+;zj$>8}@pQGa7Mzjd&sj7K( zpDVyg@;K{l72ulvx43qJ0<02w( z$5%41(g-RmcYb{PJ3iAOt(gs3Z)&F$rGEa)bwQ53g_!TFDg!6 z;?|akq#9A*Ur~>7%06_(!SCpfR3qq7HOWlrm4w$i#fYEss!Wfm&eWfl!OWkgq*%nj zaX~fUYj}Hu1-fHok#5OHMoO2~JoQe38|pQTk&`duyTWsR8Bw*)0YtV#E+bYu2f~}~ zFt8V;Qt7?O-Q7UflQdKIoRw3^Y6Sb;`E!!D27njxxe^|elD6BqGZ$3hJTeb(8)EIn z(d{0v%`fgnG~189p0!(!w|4mW7HIj^R{EPzKoh#YTQPN=no1vJj6I>H6@h4{f(>$gF*k}Xj z7>w%;c~QLLjYrx5-t9r?Z?S)VqJ{d3lSOD51Tb_7Ov2qjQ0&w(#?|JCp}El1{SBzB6f$!`e1)aF*F0S7+8%Pt`=Pdbz(IMTJc zttHe{v0r#NA~<)&>^roM@E=n@i|AaB_#dKc-`D#t%;3`m6tIbEc%Q4yr(ZRq zT;6yzo8GKi`?Hi+m!g7IgwS_!z#;(wE;uxwSBGr|$TRbmXY^+VPYIF&j_qR*(d^B4 zuR1}!08KlpP*+atJrM_(s)GGk0-q5F zpRf90?n2M>!ZBEmxk4X+WOCCtQvM57P$5N606ey>yL(y*;L1Gfk38pu5JQ>YVkwH6 zE6yS7q&CXvKvJe@tM_G{h7&S)@ouX|)ze<($rJkJI5Q!@UIN z+kI)NQ-C5-7XK)8Cy<&-1ElNDAms-zfZ@_8#vp1KSYunvV0l#JE~U)?_*!N4?zFt> zm_y5vv>WWb00|&4P%;jPs~=vRt+QZ}N%Li5gSxwc=O2yilP=a?J_P#C zkx4^j5k>kAEu*Q6X!+0SA?kaBvEO2N2r+Q5UN7moa4lF@w=gHCsp^B}U7B$1GSmQg z4MEu)fa72IT@_r_YqQ@XG&f>0@bgiLrRNc-ZsRb^+@?-j@@^KVc5h1p{330*D~>-{ zyk=BeguH6I<8zn>q1Eb{+hd-xuHsiKHkJs(zVqZ=w`_dCMA}rxMyJb@g%zJqGPqMr zUM?KSFZ=Y5>4mep^}-3er!LHHuO``!@j_CGk{&;^P-{k|4;hEAgI)Ml(mbwr+6t|l zJ4@5W3A$K_u2l1f9<+l+JVHI7G#5>CWhOlwoFVw5eSC(lWN81E^;IH?Yb~v2xMko{ zJN8&}pu8sxH_+5vOSgUjcvE|zDAiZ~KFuZ%lam>JtzIp^wm|n&CL2_30EzRE4lk*E z%?J-$xIql6M@16=+_#u{^rfcURWO8M2)F_EPBlsyPS9hREVZUBh1$;8spnIlbrK`0 z4aT}O?Yp}16sSUmF-%K7)@%acb}R+H^SNL!84Aq3bUmp&_vYoS8>Yl(=N2HoOD2?v zFTx?i%rADL4lCRl^FtgK511x}tqL=N>|V02F|My#$cC-bW6J2Ry@!W_xfS472n zgx5#%yC1(MZl!d67|*%PmOc=nHBTcGL%%fc5%=5=Nd`K@p=n9AW*bcggL+LF=W~Gq zE9_0^P`Ir}LVElQcy^bX;ZdAve$a$=?VJHgV8(&~uTx{9FCLfccFHUUj(k`2)PHWP zbJdAN_t6bqh{5aBW+|i(CKvV+f{}Tkxa9t!5rNt+CUUyd`SEe<=adX(5fL`9zJbEH z5E5;o?`v(v+XG9HdcpE!ekS0HH@%X4^kePf>oeW0Phh%rp_pctK)OjxDKq5rd*@l= zijV&7Tx4lbbPN9~PNN4Xad95_{aWBU)ij;+eN<`smEH;VcgRK8$zQ~O-{@?h0bntW z);ESry<(Q3X8}TongS5!Pr4#H(rZ*=o-iv_3?3Aa>v9>2Ng6dbbwjb>bbUU#(Ufuh z+N$K8B?s%80zDrMIMl1v=kw=%Tf8wu0w$L~TtwxbzPwYpl-*aAj9Vk`0uwhXtXiquSw#T!2 zTS_5hrD0%5Dzq>Z*%5@^T=cioWrBDxfgt{fPY&4QQTMxgeEhCM0!s37uRhi#5HfB_ zgt3YyEv{N#F54SroYjWKc=>+gurD>{x5*uOD9l%fDjlWzq@MSx-ag#^prTP*H}oka z7YV8On3a|aYV8G#$FS1s*((t6AjIz~@0d{2$N>^1>D_d$u_A3jm@U*fBZw z&qVY;|2^94tVmt?jj`h$Uby83(J)f;h>!LoOIp^HmyO7vYS5Io8T zjz@#E+J>7VYEvt_MQ(lg!XLqpK#1-noFRg4-xe#UeLKxIf6T}(E0MNNsIBy#$gJYr z{s@QoWHBL(V*B$SQrCSI)wH%WeWA$q2W9^lhrp}378^K5R0W`tZ#!{(kXsMHoF!-8 z8D;r9AflrNb8bv46R%Li8t-#~#UjXQNg+wn;h56+Li(qH5BO}5N~qa%OVP8Ww;JBo=RYNZOwE1TXRTN@6I6lI!aN5;>zr!`k3Fhs}ggVh^; z=9oz!iQx}q^EtnMjVq*TWm?U-p!q4U6FzLO!Y=GF!EWp(n!m~t79SE7Ufeg1Js<1> z_oD0qvjDZ@5j(}9*;Q$}imR~64CbmZi{+??@q|kZe`282`B-yU(EWf{zyKC%wERvZpD1H99i;G<_VE`D4ZJN%emMa!!Hb5n_B6T)^?apl~$&q_>65PlWb$^i+ z`4Z?{LYUq4+VSu2=C1|#BPYeN^1B`e*#ziDWbeM2y0^2h@doz_d_5&HO2{K36VoQg zYk_Cx!3S5=;wSlJ60XBzqRQF8x)>euQet?`g>ZfJ$BrKLk#8y`f8I^X18AG{Gkm`M z@mN-$2z4EGJ7bqdxR}uCO)^2##c;4>xUk0N1Uc`J`qICv?u=LLfs|Kxs9gH9N2%nyz7EodKNqgOi#m1IBS^|6V zz^=K%`!W$V2kuO)Cvu`MthP71X=Fp3A9gqRKFRVyV$0|7L7CM|m3(o-El3MZY?Joj z@!4m$Bbgr+c)E%R>KiI?&&btQmR%bG?lW(>0&vgtd?O{`-hm8oj2=))dxe#==$nxa zMJ!@ERHcr`YieoC<^-C8L)EE7`3O@-mU+#ead9r3*^#Z)%|2y|flXrClW{Le;IA=Hx=zs}U_E z*^B-Ums+AStuV7lmym8&LE*-#>;!Cz*BJ{Shw~jK8tg^nsoMAqD+A{Ma*2L zjx-eB7~%1r2X+jhq(*WC9VqdJHfw20JkduK+tcA%V67p47M&~UY+&~Ch!NYZ7yVxcY7Ny74Q|@dk{Y;?0~~JLici z|G6sa8>oxD!3N^fjvnKEukV9VMPA4-tPKDMwB*Uugp+Q)n@#nDr91PG&gnYD*YZxM z4@jOrF4}=?p4>EYiP-qJ<_oFP&3LIvsoq*8{g|_qk-y!xCjE&Ddv&hK-TWjak{EF% zA2-wD!$$8ssgj!T3M%lz-5z|^y3pc;B9slR5aaQt5 zZhZ7kT#QC@V{%Q^5Pk*K_$kViG4{3rJrKYxo+CH81jlH$E*Cr+HU7FD*RbmYWSAVe-;e7m*b zF~sY71!rrJ{*39Dv{&|cclCPUVtZI+=!)tA9ty@VVoL*ba}5qDd|&RUy@wW`L1$h5 zaJCk8E7=p8Y4Mr@VY{_AA6GuGH*wYMmeS0)$#HqD$V3YZZNq+D!40Vq_w=NllN|Rs zQpmSfP;+tp3y`?(L?lsPVXi78B=dI3Bd8hm%@@Fe_8ck8#G(`R;C&_68P_lzD1@(b$;ZvJc5F<>iFI($G;=0r{fc0zVv zirfsCdkoX{`nckrfxZ|@KzF^R;wMAvR)Vf#$ei8KBdBiDSa9{{o|Sr{kTO=YLXNOf zV@P5vy{rg_Ka)hQM^|XdcDYQMFd*8D4J^q#>5-B&W|=j&&TKfjaIcn}2iKS1Df!%U z{kwl-+~+cyDva3o}0nQx-Tyv>puQf=@*d9S^| za^Gt8?UZv9HkH`M877$Cb~ow4eJxq*bFHE#($66&gx4Z0MB)cWTC7&dFHcT4*(E^9 z|68#x)a!K-Ln{`V85z${_en@8ziSKCVGP1R)aSONZ&r=b!};qKKhrZyl~|XOtO<}XTm=K( zx=5US8NpCgEoSkD%9P3BKUDs3^oR3h~uhPpyIm2>_ozukW8;8SE>WG(o(r-v3NReQ> zKkKZNbS!=XgY9l_%EoBGGsu_1n97@s3xNnq!mRysGFSGkZ%sJGd?o%}uk(?*`Z`EO zpXsT`f0+d6W9#&nZsK>D$SPvC_3k5*%(I-NVI$MeuZf4`CZe5r?@j#&36X-zDOh;Z z3KVWiuY*3?(R6|uUF@?i*BJ;uoNcF_k0|q2o|Df*#a#v-A3y&Y_mrbs>6*sik7oO< zZo~pi5&|&nrb(~DLN*VAR}-YXfApmwR*z}+&)O(d6~h003xO_kF6yg22?#xW-Qbm? zpBF#b_PMN%j*dG{Ir@-p&vATJmtNpRxK8u%%zECqi<7*Pw|h4g1F~;!c4gmhYN1$$ z2X!dZz9yZB!f&<+*3r3w98_k`M0Vm58T7LGa*JoH_?`oKOI<<5I*hsJ)LD>k^n;Dz zG6S;g+vBbKmZlmul|B05R#o4mPgy+r^s;Eb*n{@f&l8_XkTL@1z#w(r5|mwx=u%Co z?E@~fMF9|*ka63(w9NehDdSL6-%OvZ!ok;`71%?SS8LfA_>FGef94-ltbM>cC+9T6 zV6Xmc`;=uU?Pjqg4IYj;ko={(C-ks$y`>Hm1gxaK13L(o)P{k8!DW}|_H@n3hxO!o zTmH4hYe$BW82iuX)iCT@m3DA;j5b+X%7ubvqR*a{&S=HK|7|2IB@aT&fDpLE-5sSsVTNA3Phut)TL@tdiyTj3Y)c z=N(S%P_m)+)`hnsIiPL+a^rjCrUn&Us3OgTaa|Mpu(zgeBaLt+TfQ2N$@y+RG!Zm7LL z^>J+flmYvd0x9gPB+^%!Iczt-bh(s3U)}_J2?(1mLO0(h>FqK}=rF8j&9Vhq6(5uQ zHXq*;IsUz}dhrRgy(M>}E5Hj!0ZyvJ_nwhdzP~*b5o-H^kX=XEx)6Q0qr*;LroM6P z^dG;)aNQf+{gWyyMvlXQ85Ztfu4FOiJF(PJw8e~FDM`CIxEidZ=@BQ|a_U+iFTI`g z$~{JIGKV4b`t*u(g?UDY^!fXv$`opKH`C3eNu$kmhx<9Avq{?f+CH6=t@E$5Y^%G- zq{02;BYJox8)o+M3_gV#DJ>{gFv`h0%1^S1Mgp4VH-{o z3855}pA}&WreBAKy{g0Jic{3%JknhS1EgC8^Sm;;((5*T2QuNf0{gPms$x<_hC;_O zxb`%n6>?V--5ZGL6oY@z5A-Vy&Bf?^W~OKxlT@iUyR2Ium}HMQNER1}pS1NeTiSBPN`LDvgOL|88faDLMy?a80k! zty8*UVB^iAt;DrRHFcCKo9<(*IEU`;gJ^IQzF>#)kt}s;iC5R|q`t3OBkIVpiwFfl zU40s-$>QI{Vm6@SwfReh= zByHIQvH_3^L4PP>;Fm~S2t3!JAtnN%K}hmNvKK)v%yO%}I%q(+jD7s?bLc9J-Z&3O zHQ3MhkMbD z(w3FaPXG&ZA6C1g!2pu;SJ1Y`#p^${gsUfhi{1PGrF#f9*iYCiQuXOj-dq%&EUO)2 zz=M8^bvVfIg5U^hC(FIdaoNbuOjv z{tdc~p5^yG;+OUFQU86*ZTtd6_QhadpM34FrV2hvaYM~gr0s6DbIb(@?T_kBy7}>P zBMs+8O&^gHP_xB0KMQa&g4|Fptf-1rx~E4I5*)HUV@~uVDpn13+K5A$zq%k_$&Wos5h5bfPg7J zMn`j=_X{-k{}N)1>J)0f18AUZJ_9)F9|8}l1CWEClFF0EHu#h~B#CQEUW`jVMDydi zy4q^Q&|Oqg(!Ti9Gu|oIfb7b1N8bk~DL!|hsw49sN>2k+of5fnb}jIi1ffyvF{{$7 zJ)NOns`?CJvDLZ{{i#A`(VK>Q2qFp)M-_nzMv$IZhzdOv$Oxm)SU@U8(?3e6Km^~h z)$19I1z1$yM=OrW0!!|(M*&m$(+TjDoWxdAN<5EVBufmo@(BKk{{E}Ln+b-Apk;=NRC7{3g#4Sp zv!jS8hR{iWvmT0-qWlNGS7#{kjz}wu8OmLEI#3`80p(tY`Om)>P+_Y-YX68ItzhPxB36L^5!L59+2r?t@HxA+DFs=I!gj<+o!$LAAoV|vzSe%&SSs$ZnDI8 zT_g_Y&KZa^40m0)->fJ*WY~V=l=gTgW4y4vNxzfa6eV7f+qs64SO~0_tP3$vz5at~L|_ZCqQWvO4EC?zX-D|R8S9_fa zK8+UF-vKil|4}XQ(ocVjRiS->@CUAwCu2YKRJ#RttLMqC%TH&!uYt-`V6zO+qmBKj z1T$~d9@mmlz$~EwgU-8vFq;~bJbn^V2gEu-SPvNE!|0Hyg~69zMaV~k#^7CS*ABSM z@(djyI{_5Nunf-CK$CvfETR!;bo&agIOvbjqV2HKD|ERjzzKTcj(^o#L^yRAem!|` z@M9hEm%f5v9E^1g-Hk{o?0M!maPC1X4}*H;WKAlscD|hPD4}^Fo}*qm)iRhy%vzxm|GRK_@SHwxSb0Q-M3J>zd4kLO zCoCm<6nfk2a^dq_GkJGHfOxdo$HEpW>Jsh2Q!6FzV*E!9M&y5!BS<{O)kELk*@;S6 z0XrYpnm&-{xRk0tUoAHv+38&;Dt>kY!k0F3wzT^aEx|iBe6`}xUqmF=nyW=OA7rtB zAwzI?Q#)EwP)&fY452E%6hRz}iU!rpL^nb5cRB(!Rt(r5b02gK;i?>em>~a-bk*xD zna

    +G9UE3-kkdlU)lp@<72A?o)P}X4q3qAWNiWO3DLOO1g(oV>$R=P2-%UW-e$v1yV+XLj5r=B%H9y}u z=}#L2DmL#RYaMNdW*8@+=r}|^oScf9z4%M+B7XZ&&T-e$URz|JsQLi5UI=(Wu#d{5m`%o^O zeR0=KWB#8tH)-gkkSc@`PQNqzkusc$S21UBWTMwD_bOVrTWEV~QW();>%YYi1?Hwx zYp(v(Q(3|(D#sL=@=r4hVb%PpQl-~i2sjjg_pbt^n4HBZ ze!`yyM8pvFHe_Hat=BH5yradTx>b6Gw%&o#|JW;L9z+Bkx^Y~KfB3&6?$pe&ng+7b zbWTF_>^3vb@r<^T`sbIERR+3oMV>+rT zB@61YdUvfWiJRoQtfPkJ1;`Il{pPzKL&I%ztQFHh-WqGvuGmtywkKSz)4#@nk>=cC z@3leME3v8J{~T@#*?hQsGsQ*JN{}NRN_sW|A@eE2L&yMh@FkgTZ&iO+Kj*^~Vi-SJ z7C_GX?cm1#Of?7FrdtY(lhx<3`&fM!_Ar7n{T&Q-0K<#Vbo?2alp|faZwA6pEo@=L z$-acnPoA)r?HFq)HkhJ!6wkG9O`7E!I;Dgf$S=|f&{2g|hRl=AfBx*~`Nl5^QXiGoem;QL`A z&k{(bu9M23M>`~De^>X6^J+nbl_2P%zfIXWSwFw-wvt?+;Z{9-QA2>q`P&Aic_VYK zdb#=PUr_B^iwc1?;5Okx>e8}^Q!+R!`omIj-8QhigsYootta%;=j zh(O?*lGIdOn$|9MI;a^n=N@;b9>S?nNb_LMW$kIp<4SX%%)M=MNisKg z6>PRsu`GJSnl$s<*wf6!H{|oowhJl#=$~#&so%JtL&WS=9SQkce<-R8)>Bf{A$o8r$Y@2&`iGJ5l*VRwhDX(_zjLt-#E`<6 zSTVAS-P?-d95W5XbO0|`h%i&nPjtH~5qTT?9Hyh&SARp`({7CkyF%EC{`Sw!r^X)$ z;zT!pV8EIIn~xQa3M!{_-V{V!9Sd~^SfnrD3*KgTW=jdJ)(VycJL9;RkO38qVJmP( z>Q&>3$Usqa&)Za`T<9u2TYly1QJq%Vii5|!b%d3!HeTP!Z7VV(9M4Kj)CW^4CT zyP}oZ&t!^I&BWDzU^PO*qxGsjGk0zkUlz#@=SzeaSXH=#+nT^`Qj;QQ+B>VAS{0Se zyH@LumNHy@&wT2~a~iC6hClAVvJ_}!ax^hFS|&rUz)y>5APFksVcVA5oZ8g;^k*T; zlL!Qkp?f?cBK@cYuh-S)qe^z^7mq}dflE_{O2UZr!M&wo0X6(M{T!)MY|V*?;*b{4 z42ELZQfXiyS7L+q4}Migx9;h6;$xnL!yVD&{w5QbYyKI7X^K69&xN@%hub1~lSH@W zoYNly-5J8NQ>q{L45MDk?7V$*H_h3&=}ndGcxXYr$L+xm4q&_3PSm_>Y4J~|LyKFw z1zT+YwNEc@|1aJc)ZspV=yjB8u3xBzr1OK^7fMV&83UB|Pte5;K?`|^yrKh!S2iQ> z9H1|xQLjF{P^^O0Pfi>&LJa)fR-gJM1D&>;q4l zIYPKq6ZNAradD+3)582HZfnzrT}dl6i2VGZiW*7)gWTNbC0AEYs6VlEsO}Hh0WKbQ z=oWO1ru>h4g|f3~in{;F4>IZGzKtIh?U+mfyj<^wC)wdfa+EVa)m8;D<8WG``yj5_mh#P%MHBN%tzV5Zr4H0=^RrcbmbA(*&cf}AhHSHAY`*qAnlVz}yg9R7Qdr8H@YqRshS}u;XRGtaF zV)Jm(mMpy=mSnr0F!H@+*j6F2N4zJDLsy;z5`c0H;xJrA>em>}>uT?(e|2tcSruVs zZzjD>`LuH{zLM){Eq7F9ZyDFpF`jU8*wapnx0ahZc%!n=iIjd?p1V}}&B#&JhJ zpyENm$2Bbnjl3gSwoNVVgo4xOQc6H~*Z*kVhIH(7A$D*tkK-i8{UJkDQiL0=VZ}zY z4xkgfhF3e$PXr-9Clf(AdM$GYX(ZWe6(J4c1A9OoZ+Nnf1{cIg2MsF410V0BM75BAddH#XSo?)}vA&dEf5=L#JJXGze&+ z{3yJdQr5|8W7~!m<6G}rob5jVxxq7MD9)VA4(1Q3E0AQDhxP+=Lay7J^An%dtmRgs zou%E18N^T{TKlRVuW?5-;sgrJaX!Q$kutoKBPzjZq8Ozn_X8~C6orTm{5S`gK2 z(7dy&@%PIOSmvzZ;4?GNm5KqS3=iHho=pT!N>Ii_Mz+4M1?mS?`YYw(hm_<^f{uCl zQu}NS)o2pkwHDZ zyhsPi*~06Jiin-f*87V{&{5opjAU-1dr94f>yQ<-mCl9oNf}MVFHP>0k`x<@p=yqR zOw3$;dPOE0=aM#DH4v&J7=lAmltCkV8F~>}0TU-VbAZm3z+?c=tF=eJAnix42V;L` zBYvs1&YtcQ1uiLeb zqqhzDE~EN(JAny0*m z0X7Y=GA`|r$9K5}H`UD?O0|{_9&Da>$8FL^G5#OsOu2jyX<@~M zh?Od8(0-$wa|(TVhU9Z8?+dW~1A5yJ=Qf4sJrGHM>yl{97Vu^gMosbpT{4Q8GR01- z*?gl`!>S%pVIsGEnb>r5ujFdts-qm8ap7BE_&Vs6ovx;DAn>6B*ecCyU5H(ktf*?< zSsNTm<4{4(KNgNuGxUUSFMPe*-VXHk@+AeCYg?PnpxZ|s^H!(Q=f7C30Bp`1-Gc0l zWIsXqzk$&f9IufN!7I}$6Nb1SQVb{PNBXrQ;)D4usC8Xr>0)^mXr#Ci;C^-bf$~?fg>io z$nn^V4vB^)5R~D`fcXKSH-lqWbU8qgfg8n zBHr(PcpCb`v@qX+&_WGc8#&${%7j9;x(3JrKkeL0*f!4k*wWdfBpRk~OI)F7|2a_@lJP&P`56vHtum!pk!g>)tnzpD17b-)jF<2I4zRt>g=_tT zd7QX0^=CF z*%JO&tW&Ho(4m8T@E6ohcI_nU$D_epc;!uu=_BguRW9jPoiJzKCT85zupgkg^RJWI z7yO~y{}W>qZEV5aUB#C zGy9fTjlSii+uCPZ8p9Rp%ZIzo?-r{lW(?>%+BKz4tzDWAYJ@alF^hA5`~4QHk9bsh zF4cv5sIMLnR~sx_i!~!6$kSVRbWz?5XuL&laq4Me{H#G^2rUmEcIWEF!dbgu|D;pF z96+udf;=|8V4PSM=V)c3b`HSHqCn&=t;J{QyPDgOZ8dmD;Q~GA9dO9(Id<+;^Rny$8mA#lXrlyLChSA)d z?J~*-b;ut@>i&%e6dBWd7U0|et+wih-tURL>ls)z^!(j*9J$qHSAzpaA7C1p{gTx5 zz2kVX`qQ}e2`WD1-q7$n^W;6lR;wAkJ|3>3;b#xtm7QA7K+#jD9kr_7-DRoNhm zw5N^fBqm^y0VA(FmCA(B95=H^{k_fK`8UFhWR_$v&MzyxW87-@5V1|&+#=;QVaci2 zmP##g*Q-}An_B}*H>1A}OJHNUR8w2IM^?;`klGM3YlhN{7(J$aNLgWt* z^%;ENrCQ#wdmF7*pIZUD4g6Y`3$0T3f_+B1(XvP(-De4XF>LaZ-;P+&?rG#PApeqL)j1Cg&eC3v%Y4p)I8I1viJ8#G^ z(Fhm>0v&0E3+J!i;!k|;_D$=yZuK4Rb<=H8seoSjWqLT6v+0(jhJXC}U*-s}u5%R(}$=K%Iltdx4hOAkj@)=%GFEr^j5CFh5k&u)%P+9J(#y zjo7osDtQq;c1o(_CSlAT-Gh>-gt*mj){M6iU#&wCqXf3%D>t`7rmutwQ%Y9X$6O%q zSJn+wE_HB>}BaV+oL^0w5q+RdJld}rSlDyL9-X~`j*TDe`86vN`q&FO*IXK0PTsS zkEBp6Sj6|loa~{KhO@V&9&))r+Sc~0)hHfF@x{Irc@4pJYIiHlc@3>yza~~5j9s*# z0(o{h+)JjPc0DI+2-PMW z=`UnC>fUhcdW7rJi1A4V&+^@Vf?nDG7CRn1BK*q*&!T_uY(T-<8+y&OSka4SS#W_h z^yhzae^M@DbjMRlv<0Xh?-7=woU}EcXcsfh&BgLaA|E$VpH9i|QgpDG0UoG7<3^HU zU&ByM@`BvWq_}5(fM)ST{F}*NDZj=3G6m+wS$Sr^G=g)46*0m>gd2e^dYq*Idosoia~^*j4}?(i~9u^MAO??+s|+XDy?i{1&U7==#x;Z~0gO{2hvJ z?c7dQZ~4KQYRyrQo_Kk{%8vg{*g^Zj$mEtHSa!{ptD@Pg8aLTvDgRClvIpye9^_Z=cCxO%VFTIz zq%K`VS8U1K(2iY#qm&sugTn&;oq>F~VmLvV z22+bJ(H8SWWKdKJf7pz8o931UjF(E@Vx8|~saekmCJJD`#TNM!$sb$Y#X<_<3UBFL zL-H=p`e2&2K#x9%n+X#0U%+)|JmlH!2Ex!<#z=P%zgje@cEtD~Ghw;O1&apQlnssz zk}0THIq$H~B0=|pdQ94(BU|xnAwlnJ{tz&FIl{Gw-(vq0ZEiWfm#X~hRk-+Xv6G8A zcmA{1j3R-+brzq|d#i`MK$z!uX^2^nxfew8n~qawiMGb~@6C8k5DAhzSlj2l#a=X^ z6VYMQh?rpLl9$yCHXN7xhA$j4>POB7^4j zOC|j_B5&mdY{{Ab7CTH03_iLZQ*(}*UhxwdPErb}Rn86OUo9&NZ4O2^SQA$K?hX_d zt$Ww$nc|7U{7H#SP}i(zGj{%R+bgK$}UKrmlt7KLwVNdm9cU=x0e-BB$U=m=m} z-k^_gXcmLgA?q!*pV4C-;Sh3^50Nvv6M0Ctnd!6p@Ykf}glVl^9rFm^sQ28wW{n0F z#wvYwUcW2A1Kf0P`gkLn!v?M$rjM6haP_YMR=hCfhWdOPA;GVISg|-Mr!7)9Za(j;!=}Q$4ILnKVcrEy`yFbtuj=5V354| z>?0+1jxb1tHKL}9JtFH;H!~Z4O?orqy|bKRY-=~Da)r85TB6y#@sk`xtD?Y?X;IDB z|FG8J%J7Uy5uB)D3bt~#t#t_pLIwL1lN%q+0WB7?LmdddB0u>p$}(MIws{Wh5=?#x zMWLZmr{o_08rJ}>e?NWGd|TTBF_BH9FrC%TD=s)sPs^Q`zCM^jriiO=H8tFDNn;lY zqPuLbbqtjzl+SRaM`kga%7=DXz_=UloV0A4{Hn9Q#O&r!x_(2O{n62m^JpaPC`oFW zKV9*cPoxC4B6V_c7O?&Bu4^6Lm)+yhDgcPCI`%YB~bO^@X0#mRGh z>`L82XZ!Z2+%$9`DWb?1xAa1gE&ama2|=r*TeH6DdG%HRziPLRiNgw=4QDtoVZm~` zxkX#jY%{t*YtiUOs5i#jZ1xSQ!pgsmE?qa*KkxAiwjk1HiC2s^Kwd`(S(LVhIcsXSV2uJHhE+P6p?eHTey) zpAe!p8@GNsPVc}oDY>Uka@CCH)}<0}!@iLwT;7`p6JaZYi&?i$0baJ`g(ZBnpYT@3 z=kJ^H0x47Z(Rq$xK&qblmPs7-$xLc6C1)!~&qs?a-lfAnii`hPThR^*KayFfUC5kC zz!pkB`ZYZi`&^mx<%?r$x}}a_y~9PNmOR(dF6(jy9*~h#R^-rMsWf&Ys#+Ri*U=La z`bkdPB}eL{USM;va1#qd;^**Q9@)OLC+Z3Fz_vmdY8LrVnS1}4^Ex_JWFf6)>F1VL zfRV;_=j3_nkZ4_J6C`j7kaRa0!e>(tQ!@tty&|&Zf)etsQ*U=*lTj)}o9k_+#t{bZ3jnMKmF0(Ct zKp}3dVGqc!iJY}H|mSr!*ld?@-{ z(V)tHfU6jhMp`D@13jbwc3?3b2x0IM&7S<)eNG}buBj`wyLR4Lg76(c>>Je>>Z)mF z_7^j0_Spr?a@zm=)j-G=Mcmo~{8ZH!pdbA9i80-3U?ZWj1sDdSACOmzFgM<)tJ3Ol zHsn*8j%R8G2k&TaS85qw+w5+Mdy^>oOdI2Wad1REc1gXvNa;2u;EKp0oZZ^Zt3Wl!G-`g2u>Yv~H zbyxZ;%=_3+o2o}dyHsn1U{~OkIZvwr8xgDfqN>%*W@~=gV2fK?`FdKrZhkt-@dkv; zwGY1wiJlL4SSJ}8qsSG5A8XnU)s?9cRlq&7!}|y#9&Fz$*DG`0)TV#S7(F`;YNFX! zF;o5)d^?vStS^672;8=_d>XuqW%E!E`06PD37M(vUBbS1$s(BAIcPR@ipGGIrAqnw z4MKt_zUy$kU)B1bzuTZ^NA4C-!jokfZtn>M6&6wFn! zbovhLd6UvIQmTlg!12L{isxw7XHqJ|vwg0*o=m>S9Z%Y|uBX;<*gOI#ntrecG1%2> zIlV5irZ->p9l#L!(}V9O8n${E!$Gt)zOwCnZq`cQ)r%ph0JHyj-CmDsUPEKtfTd)) z1OM13hO>T6w~+rUl2zLsz5VDgF|(Y19jCY!g+74Z37=5kRyinh+)`S$_U}G=&egpA z$%2wq0Qct;TPMH4#nB+GslTQcci4U{&-*CrT$R1lC!5~1EgtYxsi7XcETl8cd~(n% zar%MnTh1oukbkbt3HhFMt=W>Bhn8P7hdN;VV=w?}m+Y)Mvcf4Y^XqmyY{<#sw% z?A!~P$lkcQJ~&jI_+qyrV};sE(07Uy|G2GcU~<6o=bu%xRS~YFfUqHk-YZ3F|J$R_ z#jXu3@g`r_&UT7c`sU)|UdLhlQc9DyV5YI}=bshC{$X0y(NSb(irf@EyT#C{k&c9v zam6=G%dNh9pk_%9IbiE04_BoB4Cnk%WT=tRQkde~ReAVW$+%g7&;J5rdxsuO&0k)o zt!;UQx*1dIM=$FlmWVlNe(=zxVk(9>4G3z}Vik`+i;5^}NX1s}O^qrd5al;cpka z_cMs`A*X&UUBnd&kqwXe=Rz=Ja=|2*gn>q zv+bgrp>)(+;4)<0EDhWvCy$K$Fn!JM=B;#9E=M)|(Yay7Z8mi*eh)8cUqcJe^bK2p zgOAfWd#k!lGTH{aXAHNhkkkKi+1F#^cKGQ~VIf`AaU|5{kC8aF%XwW$oV6=EA8lgm zZl+BD`>=_taB z%=Xo+P`K!bi1p}dj>yk^9z<%d<+bH~!NkXB6RX3VTWLU-628e#`{gsA5H0zspQh;W zKTD_yR(_HK&Ha1-xIWQ1_s36b-R-lp)iWpBd_(|DH)K%u5-*&(^9syyq=mh>pksHa zX55qN0fx@W)PBiUC{UqF2*8Zli7N>8>Y)Q5wT$oH$-T-_Zm_1=6Q8f5OEcRuNt z?8a4Nl!uk4SK<%$oFU@F=N@&ULAaNM@p%eET9dOMRsV51vwch)E;D0S^expVq0z@v z*}#9aEdiu;YQ}T!$jk5N!i90WDhiR6OCG`80h~{82>zBj^t32S$w)GFw}jfEmTKfi z=1=qfrQ8G^UbC=Aq2u^xvqN)=7MybhVHRl4vuXO;(}_fViryao0)yAgtcTL+rhm3y zGucgpZce5-m^?4_V3Tgac3ndpjtF|^)B;GEdsdB@9krUaF(Xfcmzf&Z-*@5v$=zGfIZ(*Huo`&*dYi~~$qx~YSc8WYb;i5|Yc<2yM zADc0LVb_R~UajWmeA59$sQn6_5wQn)0y0{(gP7*wBkbIww4esJ+dGf(AcE1b#$MTv zLR)ex_8n9r#Bs2LTF+4aOXEH*pI3iroIsSQlAm$~if!E%DFORw9k&ewWH;hA{nHcb z8iQ-a2GsU{Mm4x)C3$BSyEc=}K4OR++FzdEv3?cw#7Cg$n_RPQTP04yRL6`n8Dv4G z7)d~&0xn<}$~C!nKU~W1xvB3XX(K=3x{pY~j-InPSXMRH!eaPPv=1HX-m)WZn+w+8 zefheM$Pf|aR$qJSpkK43`Of^ovzq;R54rxX3#WH0=CLW+K{#n8Wwl@5sHP{+98LG? zK2rIS=`%kTZ7~L!su>p3RzR9>YImC{yuk)^28ySS@o-YL*P-bkZ(UWn)Yb6*EN^V zJJ;s1mb7Evb~XZdirBO@rqSiDD9K3IWp#SEACuxPmpB}?IXXKzOG<-0@Q3WkgDTU; z>Aw4t9+2W%S~jamDPI#XcOJx`mw`0|So`MdLgdBqj+1K<+I5*{ZE5{WFn5!!{?t?a z^Fqg->ajG}%2mL)&7 z)|{vJEmC!FPq>-PZ@PMXVZJ-3zhQJ#_3B`FE8lFSE&S(4e5fdSS6K*lCD-V_(I2e= z&ejgfO3Tnm4sV?lyWkV|9HJ8qX@LX)+FDGao4qi&b0$AaXZXeQrpf17|8nI6bD`he zdLWyFv*q?(tO~IXAJHJG!@PhOfp?T-?wpEv4bT$O*cqpW9ivdH`trQ8?Ou5gO>7y$74*Z6j{0 z5!QDkZe#P>ME>ZGd{3|h*tS-H2eR1qTp}=_<=d}}X}4O8ew6RlEqTCQK3!`yH$m<2 z)VIKu@}0vjgsSYab3@Kngr-vb^%W@e1qv(IMBmg6U^KL@Cq_W>UnfsXdxjW%R zlTyym;hSOJi3PK+ok}`k=Gm$NvF~@CBO^=S|34@KJ{lg!#JAGAOw|vmwn|^eeue$c zZ>+62mEwv;yZd7{loA;MIYO_y&9Ur{yD~P@^KFeSS-QEGY~alSFF?1BAuXJi(e!!8 ziF4o6t!Apbvjc(2XxL$i!HFjo^XFNbGYt*H0hjI?2}&z5D+k(AQeK_b25N4Kzau=` z?-jQs!7Y+q9s}BCXt)i^q0R$ZMm45-u9ip$VbEA>>q>X%`k9ZdZi(LF7B)Pa;7qLsPrtfE3 zZ>lPOXwo>3TjGeej&tyq$cnM`Fg6fngcD{w82a^}z~Jt0F~xt)Ye*GT2F4I0dh?&Z zkA^L_ZdmJ+$nTg9HD8$#qIP@TnfIF)VS8CAZk|vOXd96OM)-h#=#&}P&)dCOCr86T zxhE#7N2MqboA*58jA~sO!eF@4J8>lJsl9+iUXW9lxNJftlho^XaQLRu3sPm%~%)bU}Tb4)mX#q1J>@5liz2 zE^yh=o(^M$XNuo*tg)4`o`G2BO;zQ=B&Z&g$|m^tnyk-`Bm!K3 zyK(-vR$BC*XeEqKIycZKOMFwPzM>wERXY&AQ&^2>N}3$h`q+Jep)Mt$jA`COHwpoHib-m5r9^Y&O~MhCtAL2-0#CBnd${TnRm+HGjDeUBjVEB^S=VK zpheSJAvw_Z?JC6d(xFD?HSbhahMMtZUfAF8oYzN{e#q&b4ecet!B9^ZOhl{ZGq>YO zJgRFcO(_6LCJ2Ex$&OSO&0d@&MS#*%^K}4rkE8(^{?%`W6`DuY7Y5 zjVANH#;vOoo=@8FO1Gtw!L8e4S$p-ZRuo$3CTQD2jqd3^6$GtJQYu_ksIpiOt1VzD z`^qRIo9z0b8$$^RX7lsMwC~Nm1$GYE|1?@9t+=3q-kI)O);PK?3%nX@0-H_5 z+J|J?!%&j!66EuU1nc@nr7jc;S1DZGu)(6q-I|x~DA)}PHb?^Q6sOWr8G9$2@PK9b zUW$ZUViDJQd}dWLhY0Z!%{;MS%_9i{nrbp&EMpGuD$VPXQ94JV=Im)Cp?7Pd+7VpS zyBlUl6frJ6`lGd#c5{93jM6`rBuV{Yi5+F9H$Q1Spt#>3URgWVw~!k(1M;-j0QV#9 zI)ujdO({}5ss?7UQ05&Rr(}JHve+9Af6phFk0mh`b&~0{ez`YqS z86Xz;vNC%#KXhY$v}|V@(8AE>(fI_DUNp(aVRBKeC(Ie;o!q>he{hEWAHwFPW0m0- z8MmyoZOPexVAi!*ODE%T%}52p z8g7x(#N>~fE^S^65scZVR-$8FvXSXOm~eD>#(N1W%kkg|d_%<;5GiQ)+l}08<<(hL zPWE%($iPobjMfUBqG|iF4^29}Sr^VC=<4|_?*H}O7LRZ?1v~6KzYo4Xa)y`mllK8S zx+-W8oTk~aYrDgJf@Ri=oL=jGq~qB90C-q}&a7%(DC7J^W^&~&Mp#~`!ICX*-r*gX|M{Uce?W;ZPqkM%6}{(Fu)>m5C%ex{}*RiYvUrf zT`Zh!uKV!}uoJND_G=J#ZV%MWaOiGF+CbFclnyeslO6Y;ico(gQA!Z8SsCzSJBVi= zXaqoHU&DgkZ)29IjOYz-Kw{pcmQY*usYmK1JFKdZ(m>~XAfD_+>O<8=oR5{KF17H* zlFqv%?W%O>ZTo|u?sH`a*-%=0YY~|N0{Vu<4IX#|%($%MfeS)VG@muTmvDsj)h9r5 ztC~|DIN8y^!f<-gG}vB+O=8W?2Gu0t>auU_r<2<`?9D|J$onHryBt11fhxd&W*n>7 zr0=JuQSg)$X|2m4a)~uB{UY0?h4PmHW=Hk}YdoJN$0fOBtEfL(lXm2Mu&a(!Yss@iXuX&d|DUD{q& zJBQdkU=SclPpo$o%y)D0xH+O}tT4zKJ)(Uqb+`{Lf++wtd0G^}Dm={9`LaDBYVm!R zU4S-@j0+c;c}V5dj92uQ2AN{n1$7F|Di_&V9z*|feR!0hgI=u=|NXuLU<=EF=ip%sXwj_tjgu%o7Lt~2!U zod6G3Gun@^VC89U2FHx-A2tB*OsEy4~I9ZJ@mcoTD|B>{k1xlF7py%43V)zBUN&8Y^DPCE~n?AUJcRm17Xk z@LRJ`ac*bw>TDXYBgQ(u3kJI_I~Hx+Apxi3=)aeGW;5{iw}!5d40F-`Z6P{Q0D+Xl zU}o%42ye)fr^xfLOO^j}37Ln#Y-fkp$@{4$X~|D8G1681zzw5kt=5zNO8{*9d|;3P zV*hT72{Gn2W*Y1cB>ZNHlEe^B1b7)?j z((gJGO5%ft#%zX;EjinXT*&L^o?QLyRjNS084eSfrdzG5a?}ChxH1KFC4Xy@?|D@? zyfS$Qi%4N7MOf#rsQH9@7NlD1vxrSPv^C55MsLroTZk|q<@5D!q>l1|W$zybl~QXH zc^TUBjJ>MykW(X&;N9jF4zLfJ;$KVlolIjHn;d^H%*pz%AiM^htTS^LC8b^`+t#S0 zq}qbA)T~elxr@IV1sy*!Ds68lsZKFL z`M^<``e8q}=?>O=uWjkJ_WcI1jHpQUJ@Eu^cG$H2sfPY~&STFT1TRk=~2vDtr*i3+dJ&}hf z1*H}9XRc~*I^lk0YcNgV4Qx#4qLF9i$WbFs#%*KH1pks*|EQVX{Lr=;hxoG}jo(aP zJumh)ov)Q*Ck(umOtYz}O$GJJ?-x|$*s!? zsp`6kAoFDXBe6yZwIu^_j9ozFQfzAx3Kyi ztRw?<9FX{*YC}YJZI`sg>D8NU2xQ0)Vh!VYfNn&@nc=Ovmm$KU<}{TUI}Cx$5FJ}` zNU+um@M>NQsy3I7rmspkX~sDP7~FEGI^Sv2H}G~~c;~2rf4Y6E7kXQSr?GF$|D7b~ z{91kZ8be-RI4A{uR2U4mL^thcco!$iV&u5aG)^{9i z2Lss49+#zGkDZ9|j{x^=;?XK$o;Dl8;`axtu7~zK+Nm4Tu58LMe<-fM)j;QfkZ$gX zrksoSSI>;9n9FsQF9()qDjr1rIJ&+1E`@v`H6PdblNA|xrTO*x2&S*0-snn%OOnQJ z?Wib8dh~F%ZB4U$A;ol9^}bZI&80ihemyG8PZJW@cnyJhd>RKFG-Xb+1wg2lCa-?knp(}`t9~dIY zi_fQmZd14?%T|LUuSG}H1^oaV4kf`8ej%7R`-}_%!|aEi#Lc_sG`N=6Ovdp(bXB)5 zvXgDo`+vFQ+|Huks1Ky-3eB~_8OCvkyx!AAK6mQSZ43T+F}6C-bkO-~8GG6V_Avyd z2F2J9kyTOHBH;gUPxdIw{|84KUh9Aj)f5S ze^Qe)EKp*|@{x65^F#|G7qLI_1xb(~UG^L2m%sFj8KjMT4mz0U&6lFz;3lQ@eNLYh zl>?Bsz4di+e*NzCJMJcZqfnacP2taqgFVl~SF*}NmY5JR=#HBiI^ScoSyR!XEz)bv zcF-;sNXBkLOl%48>-=pvbp zu>Hd1ObvGlp1=LRH8HJBlJz92hYB3ce;Q4(Mh1s;ujSjtR!{I#>^t3oaE^uV(N7nQ zM?~;$q0KezzdBmXMCy6ypg$Xof{JF!v#!$@m5de_=JSGj$F6|rx67t`1@D#3IO?yp zpx`j4fPs3^H#K3@r4so9$-dOv*QOs=?x!$)yEa~Uyw_>-DqqU3v^N2fPBalF>l@g+ zNzf}^OTShPe4Wipe(1EAy9i)mNnQ?c zLzGd7JC%bMeoed`I(u83oVBAVY$r1q8FtMN(bPQYW!s1ixiOcPlSdn9h%#DMtAVKi zOymm3%3&z6y;oM_e)I)pa*3#U$prV5w0s$w#2FcYBC|^e1N>LvgV3+jhV!VQ0Nc@+ zk@N-wp~=rwNAd3VG~eRnqk}G)zk-}hf-&cXKquGeB99X>#No}m(i>r0N}BGL#xNC9 z6!G{JpD1IZBuTRy(w2i__F@87z`NIEb#T^2+Dp15@q2MslWc2s#*_PXKTOikMtx)| zefjeVH2l!~$5G5E>?$8ibwQC(g6Ti)KCAqy>w54i;>=d0;5&D~W!N!-z7MrcqT~^U zJ_#W?l4Z6x>#+}fcm*;v`3TKQUa_*Lrc=n1B_6*YalTiL?`|IWK(yTv2N@J22-ZJc zR%g!i?y)@01u)Tm@9n6Z-49Zglla5-G`2&05Ju3RU)OH?VG6y*Y01Wa0%&kR%-4ep!8?ZV;EGY{AZdpwkWx(asv)`!HtZ7t%bYYJ31S2QhwH zdLR)`2Ta$?*Lp`wfoIZrNlkNrq3%%Z)1Ef?SO1jYpMBO@+kFhsX76SZ!&rKlKjw}1 z%_5G1>2F$|@yZ{WrOp1*fKockZGm+c8WHM1xMIl!}Oo9XHTibuG5%%9Ck7d{Bjz0H#h{9aYMvTtCL ztSsACg>%1rIwS3ctOH0hNuriZIlTp&-t^Gbi<#Ismhvfii!B^3L zm*1#Q)tJ@Hgyx3I=x$6KA1ZCx@UXdSER9lBK}X9$Mo;hdNHgz==x zdg?=%c)vSKIL605pcx>O-Kkbfqi0FPX4qh}=3qCW^4CHrcyA=D=z{@6>8iGU)3)!n{*dl&Q3I$r+QqsFW1 z{OPZDYYUKX&4NMq5GOG0Im!FZI)oOYB z<`U`a!!7TlD&;RHojk>S9g#GCFl#e?9g`9&QQ{<#wgh=CbrHYq^|^45PnuuOX;OW# zb5z+kYb?XQ>pOYFs`lmfDy9t)gMxM=Ou#`dp@JH5|j!zKC=YoJP%tNG)mY zv~7@g#{vQ~wIMbkb6H0OQ-MM>9o>v@eaeGDlaNtt1`kD25-?{w~(+rqC z(02XFF=lZB0*7M)9V5Oyp!5e;OfdiB`dEJc^F!-nvi@_89vEw~m@y{U0Oo$*-aB z9l~n92RF*8R4iP_Sgwy$(~Cxyeoa$ zYu{#D6Q~A|EAco7oS30Nj9JpLg;zW!dXfdtt4H4P!tYq!?x229kP@~`a~K)?1#v5w zmkIW20z~hovfSwFEu(c;A-~41m0c`bOt~?(AxTc8{>51T7R)<~3C$36 z@!Tn*=I739cEtQFd#-yXOCQTE&NHsJX za4Xw?Vz)y#g4caqLud1QIuaRq8ct=r=Q27cX*WV)6qZ@4^M|Oa7te!!*S>SPt@Eav z9atAM>B+8CA=}$_jFi#3BnfqS1y=Vjs7sqFMf(8tb>nwPy-R9o!Jq5;TO|#^;&o9| zNj3wxl&%JusO->i|H^j#sbP&m<6=(_C0I0>H=Pf;8PyA{=jVZ`gGxkU3=RzVbXW!_ zT2pVyd1P7-vaq&Flw`}4@8IlV(nSdUsIP_terw!38`Vy57F1q~-!9)2QKd-`+mjn= zN7R0X0T8Ne{y|r(=f8+HUSOH22W5qp4(}b*a22 z;PZ<&u;;paboL~`vJp_d6^mVI8FygFG3?mPF2oqL%V`k@MF)0H(d5Y7LNCpIots>p z?Qy^u$~8O23d?Fa&ZX3{=A;|`9Os#?25CD=0p(y>MO^z;>FX&QuT-pUGGPDZpx%x7 z3Av|DzIj~|{dx_2w{Zfh>tm3T9fSIh&(mNi?B4tRU#`1lFqWx9SM+nJ%Cyt)zBf+d ztc1V5>Alqx;cdneO7|N%iv^t>o2bATSCEuIHQWAM%Gq#XJKJmef)OVBZ-tX0EDjST znx)oIB81&1mtsa}zc`TeykSuk&V7fU7NE}0HCOWsfj*h^-n5Y zxI2}M@YWuOH7vR(>VT2Y(_(-A`KEwq>{mi=iZ7Xff7W*=_+tg%c159`&59?g4W^{a zTGqy5Mv;EvDkL`u{4@tCMdJOOseK`0JHhfIXY}pV#Sde44?-OKmyf5o!+v%}TBpbC ztyls(G%I}gJZTX7TlOP!d!~wd2a7Rs^Ymc#i_a~?w#p@NJr!p^{XMJ>EP!#4av26oxN9e`%8dS~nu_wpri>>uhxBBPveRq6H z?STZ{KM5Pva9r)K`Lefw(-JC^>ImT=6f{vbcWb}CP{U|t`5k*wdE3p4vTM9aG7C9H zQu&Oc#MtQD7YB~P8%A@@lnDJLX%X^5i2Rgr1F9rseI-TfaB z2wM&F%TU1u9RU6wALfZ}wON$Lr7hD$sq$fi1z-Ds?Uwc5hl~0VT`?o1*N!(>C)!qa z8Y}z6Q$q9d6_1sPPbOOIeP~IYb$Qj}2a}gfcWyFT#5jKPQfIaYIk_`bw-}EI{enS@Eb$W0j1T=PnHsdhEk;it(z7)h}SHupV)>fMx1r*WW-hiT7~MOt(GLVbnQ) zI7*8dKT%`mKDGhSM)(-+XR7&1`MoMuvKW4Yh=!)&R?8$_+47ntSr>h7?zA+c(+r4{ z-1hyE%0i{61pK#Yt3D03^!%$rbiD$vwcBXZzg#4IrZuxW}ETwyFKYJ-G0Ryl~plXjC00 z*kv!jRcSD(z0&CdYSXnSz5+cA#<43d)Ejyx)0R(DyUb>Yfx=Q1Z9DCZ^nC1A5Sqwf7Ix{no$}sX9@V z^@LCDi+bhNVe>|IfrwGEgAYT>gm~rUlzRVWRve7vIw$xR?qedRyDggyPYvT&Kb*?x z89wLzbziwhf5lSfwi|M`Z^cX*l46Spd!O#Mq_HN z(@-(rIF|2W^6OWp#pS8w1W5YA?#~fmu>CekI(pa=n0-bfWgS;c&eVdmE}aBR<>?2F zW(Kf~jH8twWkoQ3_Tj|(7WJJeQ=q8gWEt|so~&P31`f;9w$_Ua6_@|vOyipevC_kt98 zdKCkrYsV}ca*uV)osMc2m9TOA8fdB)k+tvq3QGKWU@Rj88fF|-<67uWaODdHf<-uP zJ9Bu-bTwX$2hnbj#v;-xZOmH)Me;>giJ=qHNLPyGP>(cykL_U#ROHBM`J6Z&Mf2ulCqX{Ygqf3@Ee zrkDXEVm2)w<1i4Ww=GB+0+br;Ph48Wo^MVIRYAvkoT~&Zc9xR>um1~>#X(#IWQdLq zJNNp;0WzYm?2>!m1V%=5j%v!p{FI>=d?tUUDUDhEt$vPdSDu{)A&YYj5Om*!5&_*2 zOXgf#>(pDK1RMXCX{v~-Q3J%KMa~_>!C>9#Kt=YO@cjt(tnK*9DqeX#Oo2Ur`TwKV z#$O5J9${w6PJmPH!7^am7ExX34@bQXfb6997;1)DtdWlj)qBaVIEnD0T?Og01ct}N zT8EG6Y##sh1M;#OkON=F(EU*C@-)##+IyYV*RDW1$2n3)0S5xi>e1@p%iT_l|+r8_|xo%Uwb%Rj$Z!`_c#9U=sVV{uFwK&5f zvS~uumxt>Jw@^$+g1Qckd?1JzUUfcnFfIEcbReV85pMpkDZM7vV*fn?XT#wJ*4L-3 z;t?x7=V^4{y}8)B|C#{QNaYhz;Qta$ZZTjI&)|_Wpp%sWE4KNj#9T@gO^p-*2-85C zWw$ht)M-d|_Yze`{Iaxg9}L1QT2UEhwppSNWM5*U@SEm9bR0IQ7rnV@ew*Z{R3v!p znB*)jkWEVRm#!Ni`>f-)gvTcxtGc4_bn{iStJF3&ZMFnB4)e4KR6U!9Bc=6gegr5C z2jC97Oz58wa*L0kApU(MA|kII1ti?M&7oHFf}viU=6{|R*GBo^>Xgm z&1f~%{i$nrTuon|w#+D9*0hO2D`;})N)KeG$$y{cVW`o`*6b`RGxj3WXU16RU#<&) zatIx5`@k&c@(>KvjSaO349ed`&{S5qsRJ8VvSa*Z=vJI->6ZGA?aIfZM3V{)r}e6MvX@Gd?x>4~`&=~{;3m*Oj1tFzBPexv>-(`5aL*)cuGo8s zLWgB6vBq(2!x@~z@}maA7o`p7&B*VX4g#+ry5E`-I1c{gj(zHGv3HjYw{zAfKR3aa zvkXY(yUXtuXidDG{pa4{7DHILX2!Z-Pa#>7ma!+DxcM!1ecmvku;&G1qGeV-o3~$y;%L~p8WyUN(H+ivZQV!z;fgZN9Ql?6nD~N{ zofz0m^dc-X6TWd|z?(T|JX^MM`LVPA^9o26qXAjx5V=>|SM}@pZ~4`%?xfV}Q3q1b z&{tmDwsg|SQgOp{qTDo~N!~f%% zXf2;1;hXzG(*AH1P)W+vi9pH$`bK7L~QdqIX{5y z+cxRq22??NlJ`S7MOmpce~x?_B02eHAA4^kEoKJZ75#-E_EU@%f_ZIp2{7 z3A7C&9vZO)z#?OnZhD7Gq=ajBtTu)thLe21xJaF;j>kvBC64Y1jV%O)!y5M+q@!us zh>YLdOf$lXXtfEqR3k?Yq5g=RYedox{J`@2H65f)u&^(sr_wLfU}{e-Ov!D(o;!i> z#J@SLty7&!V`unInGU|4Haj`L-(fNA{OCa8XI&>P0fCV$03{&5`3)ccmAhB zk0t()!ATuc?L87^x3+oA>XIYPM?>(uzEgQT=&9Ojk+1WNnrb(Vq}yT^sfL;c+`17> zhdDLDA`?=cG5J&n15fgTrWQVXzY2rg&xn6xHPJp@6gCLiZaz;@#| z#MvXhLSH+cx3wzvZ}4%$(K(Tb;6R%rrbDxJirG;N`!gC5hi~M>rSo`&%xg!QzJxfs z?JOjD{_W8ss1`>8c?3+fpFexSp!xCPvPm0fRR52dO=7)-s9Gc)_>Q-dolT-P2p3 zw;%x3$ImXDB_pP%?H7OauJrkWv02oZ5H=aXr$|3C5FM>T|MpY(AW+Ov*nRcTjDBQ8 zH0I7kAGHYNvnt7m?a8^6`}YgnJv}^E$=S=K=ukObx;eT!?^(LH#R0f&ak+y>O z;<#O_LLgx2>xc`|#ucCkHRwzo1`HX<@%uXm)?(G;bB&=Hg$;+`;z8`4NJ~;_zZxn8 zYb{S`6^nXk(v3buzCOs$$OT9aL(rC9V^ryX<#Y`pv~{s4721?4kr}#Z~I%Y zEaUMViSFcd20Q}@6sKXBsy-nPv9V|LwBmu3oQoKzZLYv?Q&Ow(LG=%g=*{-KbthBY zLnvpPvO6}j`5|qHaLouyo5G$64=?f_U@1pQ0LE44gvc}fSafVH=Bh{V{IYc{S!h{& zQLK4=+`(Y6kH|tZTOU_Zc9(hcnssqej|bQt5L^(Y>iI)QTrxTGv{wL6@)k}>8E`pN zVZG{RoC2(`9g)d})rmn@oI|eOQ~MsBonxgvX6(hYc}XI~6@WQknEkO35Z~^1PC06r z)#Jf5))$59lAHoeZ0vSbYeIT3DVN9trYzUwQVODBT6DCiwZpbftwGud3#DemVF#DC zo3p(xSbG9lUe3u&(rln+=~DkW&=Xu}&c9qCDG44Ol}B!)*@<0QUAx9gjZhC1*d9Lh z?d_K>o#18OW4Cm1i9r8PzAHhJ{M(9I&m2>zD;x`T7!)Iw4SutfqS=l#CoOf0Dh?D9&%ceSYU>WB~o|OAe04 z0hl2V9|3sn(c}8GUfG;^Ro+^1$is(>v~&;Smr_#;fu}@1mbAs*a1Vv5K|R9;p6inJ z5~3d(g$Tj702)Cj;7ap#5X*NQWSrnwmV7>MA7;m=NM>hdY}_Smb!aZyFLrC+U@07S zd+(JqXLRL0hqHdcQ-*>}Fs+eGBmq?RCM5apGS)rnl47?hesy}@GqK1KXV#Y27Fc`# z;sf~Yznt|Y$Us?E-+0uN@sjk*FN0DDNu|N9W3!c(9VXSa6?L~AqvZ)Ob&X^cm3LehIoO= zLY)s6mB{H&vSIw9n_y$j^17ldH4mdA&K0lN)@@YUqWGqpP^9IzNpV$~wJKa>fLvSS z{XW;QHtfd5*XQwTPdE8@Pkus=Uv+HeJZ@%ncsxvYfShG7WGo2)LS8<*fSsm9?!U0; zAl?2=*Xx&Nn-_oo&pfo76Z*YlO4K*V=Q0AL(m{p`^p|bmmkX4bD~1x9CX6E5LS35V z_sV)$v**T_IA*~5c>_fQjC;yBu}LD0qPM`9I+2DPW|Xaj5G|h&Q1DX ze&Dv9v+NZ)sKiW+p0t`9H;SL1)h_)a(vDp?BLIRKxJcK0^9fGG#r8iH5)x78SgxRD z{9@z$9%7R`d?ZlMur%QwuCpIY1dhYG;^VfRZ1JNVL-}5;xK(9AwV{)CvM++hILEq; zqP?{I8A=Wgv-8sre5S;f=_zBRlp1aYM zEWB^;I&7)ydHJs^TAzUy*TC&0!?Lch=7MKvgXw)ci4+MB*+63hg{VlDW#}1VaAR}@ zWJ3dy>oie(A%LN98+###ed5^Z40!(1=}dAu$<4SJ(tAu>=r534evNT}a@DQ+Yyeb0 z&;X$(opeo(-Z)q>LWoY=3FvKlM$@z_Jd)jS4eI3uhV_+hv|uOp36l&va`UoxrhLby zROoiqF#wqXkSJ11-hAL~%dloTFW0k* z^F;C3Wq7xyq+W$7euNp8Dpvj3-D0FpeT`%-<+Vn=boe-_UG3pm-`;q%oTP6-0Kjs) zo&conT>pIAKUGz*nUdz}6o;N_ikDAUT(55%={3!{GP^Z_|66xsicrq&a%}%DIy=Vl0Wdt`L3;+Y(~BePisYxpmbtyV17P4Y?pZHjO(h^ z9{rlpLW4t<|IGJnFUS0_&BwPTI9KdQy3-5cS8Y-F_z>g7PdkS0Ow6;VgY5Vjz5Yd_ zIFvn(Jlm{4&#F)Yxz*UDUO~E-G#e?sp{#B-1AXWHI~%<vSg0k&^vZ3SSm_?;mH{JO;YXZ`vn+`F`x03YL7c_d|vn+14YBAcs1hTAg!w z*z^N4byZW{DO{|z*j~?;aFadw*Fg=ycXQi6 zA}Dd(L60v(@~UKbZl>dWB-|>f3HTFS{aRM2RC1#m^za|$a3}wFjX|;|d$G*ci&t_s zdVR}6D!ZN##>8>;jV&F_ogy{_}c%XPjD*s=MP`EX$gSE53?B$5lleVcJCYbbT@ zVWtit&-MO{#o2JJ1;@6u#lAm=qLm-^px)TiF)0!m^uH?W20QNLC`g^lanGt}?bXk- zZwTn`fsIkjBvYPqf+7>=5}>Ll@27}Cz)Y<{FN*0>XMToc4b`r_lWZj6$LgUn?*FRa zR6pT(5;VVEtkjW?xeB@@2=-!m+BV>6a9!+Boze;ZFFB?-&gykh*D4x&eY0O%K#gRs8M2` z!tnxyyeuuk@?x+XCOF3aj`MwN|8R}kJl)#<+yz1<%hoK_gLzWjYC$bxf4>ajiLR0^ z`DWINrBo;;)Qc)V6G~XF5qp1e#ZO$B!mMDN2jt9b@g?;FMRb z->5$pwvHCgw1i~CW+?R3Irr0oZ5{%ldG{Nho2UttrBV&a3Ra%vrEo+i*H>y5m&e2? znNk$DL((4JsYv{okJ9HEFtMGGe^*Z=Hnhq>X^S7opS@n?GQgbPz4x(Xv`gaq%3|_9 zM99UtBVsOxT(egsP4^d9GTd$yZTm5NeBwdod6rK~D%HZ@w|--$aF#ET`1(a)Q2av7 z^?}rbqRzsr9+#XIrBknhZyL_pJP&Y;{x)jTtZ<M`(DY?fbk73#&gi9YVhumm>JW zAnv&(89yh`+&Hy92H80Y<$=GzsinCicSv6c$$BV&S~ z2SW0iUOH`HnLZaRWdC$KP#!x_(D7@n1@T^ILM6TCdDR)Z_r$+kiyykx&GL}r3ydV` zihszRqfzx33bUd5+fGD4)~`{LsGuOt+?xW(*;kbP8G_4X{><=&7lO$FMprzbnGlOX zs(>fhO=QmWyBcONE746!nkdLjGsKHYZ!R{RJj1eVh187uEon_z$j`06yPk68kC!ic zHKax>B?etu;|i1-2jvo5E0>pcj+#kDqTxJJ+C<3`rEJT~`ePz|ehRrwe_&bhHg@{0 zj~jZjznQ-6x$4^Dwu2D>613GO^-vI@p$I?NGEdTp`T8Lx$4tyH!<<5n!YcxGu#J6! zn{X0k%6fg`RLp;DKQHk|Zl(V?J*F!u6|yJ1_m$R#mEP2Dux~ZKEQke@{hF_u zV6hG&rg}ht^#?nR2#&Fpd=Es2KC%&l<&hujdD;Ax7_=dI2_2-44 zm*B_JysBp_+>rzf7NylAx8n&ik9m3qBhYQ$hDk(~!frch9Ss%Ak@a?$16+ zLoxSTAXQQyD?dTb+|%e+6~?2WgM#Gh$d59rxVvh6>HPi)lW`uNW6ms9N3fHM8E)Uz zG@zx!L-XZujrXr+m)|+AvyRCMgV!@dHGuW4MsNH5s%uq!yck^c5&^~#%0bP;r3s;D z17J%T*c~uNT+3ymG1mEGQ2rz03if;l<2U+Q%>u51LFvBHMO zDZ)02RfIF3~g|Cfti!g^}UA?lu@IsTZ+LVd%#jnz!QCpY!Ag%{m;(cj^lJU`bWLGUiC^=`ZCU7R!e_0%^oX2hHgAq(#wb$F6Xym&p zC;MK3@KV_B0oHI(_#0fKcg5UiKZQ^!maXtP{Xv?ajN+FQ_DQI1P#2yo-c7rt>q_JI z3tBbiNoc!yd|*Gtj;SEDGrWVmA61n2qi?sb9RD-(U#{lRw;eKmGZMf!`kkuexPr=V z(&|unz+I-hSoj04G+e+5%ltN*35(7lvp^v~ndyA*k_qGP7i!|m+*mZcHy0@a|Vl)myzv^(m(Z^37-7C$0o4%5W3m@9hISRZr zoc{6nqkKC}!=Q-1H3hKs3>>+Lv*HE#NMS|(jl!f z&C}vIx7d{%Z6+lSYpvFABt}FS16cU<^GQWT(jB+#aQ>BK({PQt&rQ=3q<#fzEWA7( zrs{S|gHjumN>$7nDABQQDfS@L-mJmK&HMG#H+;5A`A~Q2w0NMKuBwggaUJ)|&{UO9 zrPlYcj)0U4lu)Hu9`)Tw)Y|+VU5(qTPekR*-V;6zP$VlHq<&Bf8cEiec3KL028Qyv^%gY!E3p3nR9zAot;@KnE- zLc&yZWoR*UhJ4N94KK+WSsb^(ar;(^tJKG`gB`h>;N|CO`>Av;Plxo&T++_NCnB!B>aIg6yKX`k{;|E+5+ohoozMcX z>n^L7ysp-)ervHhrep&}K{TPCO9@4%k6qm*9-x^|0+YHNs^wz*hwJU2fu$V`YXrQ! z{p+Gcd-*4>w&lbRNFhg_i9aFgqWos-pW zTDYCoP}M@fA9;Ll?^4*)-pV-0Y&N=H_dTHK35@Azy)|A@ceZHqED@RNl=EP@$qDws+cI;gU!tqXf&{3_1{G5!6?Rc4zrp_c^Hbo}0`gn6A<;q;^lbe3dRgzz| z%Bx%BEzAN5n)DjqqC`h_4D!~X$GtO*Smb#nNsglpc}t|>at0%FA(c*^b9luP94~W1 z*99i^B|fV*2;!M^6IB;pI&srvJG*hW1hQ!iB0xH+LRwd-b_Wq#m6Mc%YAKsYriT6% zlT_v+#&;-?;5%7h=Iqf^rxa?8+H`|$SLa?&ftCF_5I)1c)D`S&#u_gd$cl|F$1W#0 zqVQmSApu6=-jAb#W|P^R_X3dDsQ*&tyNUxN9lq~$2sz*h2K3BtV$$QL#0nn%Tqmcl z34cOgE=FH_&=v!!F4ft2C_+L2Lor=bJ@+!XuP=S;zJz9~sP)399Y4`mMhia*rA;GA zcc;S(!mH!9qmm8&?srL1Sf?q12`9U^86jHc=B!_{{n4*%5zDQ<_5n`idb|25VNQu2X3Oz zX}5s_W3eOf&YD~#o4sI9Hcv|-8z#2ehy5`EPnbJ2_X8FqGxvgftPOHWlqt!le$upr z7(}9m#E-)mP&mzw8l1vQ2I?z(`!5sgYfyC$^j?b+rlsmy_xr}b7%0Ty6`!U@Oti1F zgsH(v2y}8PlAJfu%@ycK7|ce`R7!67-a4w(xPkR`eb6j|{~a z{==vh*7j6r?fR2biw-S2mN{YLE7-k|Eqhgms`@ZEgU4Kp*LxFjn6L@?^EZ{1dbw)z zwCkos)Dg7`2m!xN)~1JTBAV+`XL--g#(|a=)^4Nu&@vvDzNl{I_(Ih@?ZQz>FA;a-C5GQM`1hG)N41+lcSVE^SOZ-w&V^U1hpp3UCr$1(eSnuQS<>Co|B5uWv4V z!IyKx|JVVc>beDljt*|jE;RJJl&oC=i3qnFnBiVxNh_-$DE*;J#qOP#dWcR7>py2K z2GO5XDxOT+5btU&RNH{5#%i z!$^1e-+kKVEbU zwa852j5kEsOe-R-5`icWJi_UFi|A%uKO&Fb4#iKlCjEyG2)r^pZ{^s%SP!mbHkZmR zcmD72cCme@ZNFXo((4h~wMnZ+k1C^N*u5Qr_MU zU(yFH*~Kl@>+R1@y5<@-P%!xoKZ$WUcJ){EdD%v8Knx5 z^^H9_D>UVqs(8mnBX_T8Q}EF6s6l$y$tXtn8}>d%!+Y*$gZc$S)aN}$V3&u%obiv+ z1WwkFmfEIlUP}FTpq+Lr6Q@tdZ`kw^#|OVR3}(zqc+Q?B!ja`+F6t+biE8O-B_Hx=MT$Ky+F z6-}Yn9W@h*fomlnBje5i<5|tVou^-8;y~#Z`tRG11HwRXM|o!B5UivudlzK43de(Q0j(N-0-6AA)<7A1e((`Oz?p3 z;ZNy(>0nq%C#!Icj&mLGI>Ub>3G>*)ovNEmd$C4*%KVK>D9Wp8dJWIe2{KPzdKmS; ze2FAbgAgUMm;sYOJhB8m!Sp_oim=~l92tC}5@BW82T~|SQM>;NMBnYBHZ#&8xNR6j zyVI^A9h#oGATHnx_Zz=1PHblwE#$tcjsX^|D4K*)t(b%~GEk zcEHK(rq(z_$;fyvwKifVGRV9j^^jxNtHGtgm7z=Nh4_AoMGeMIWrh7r zVM!c-=IJ4GsGlT>h^ExNf+X&;(#1|1SH$%^S4l7L@9GIQfAB=X_S_EoCbDbHh|5Yj zE5CfL%G%K{$Jc#lc~XtumO=Y6yFESl3U@WoVb_T2NX z-+@m#K!J&^p5S{|W3i$A8N4j&X(*imy)k$Iikf}3wwW|?UQ#P z^v12ib|k1eYcXJ-7nws$`8MNL>Y)Hj82U~r3cTv5;e!tkVL!Z_a}RfbWP%Rh!%rii zLG^;+`i_K>>O20|B8yfpXxm!75Bb#n5L{cehWF&vh=)YFV_AI@VLEyX`lo)o5^>F* zpZ9mm#)^gASM}zt%>&gB5&-~$3x9DrIo*b&2NY40p-an0DJ=8lEZ&>_Ux{|^XT4?V zJvgk|Vau>NtL}@dAFR8FxB%SG4`POWE~w@;5rv|O6TubhFW{j~0s^39{=Ir?rteL- zJYbSs<2xfEKiGO6uQFKW#6j}Tsyr;YbqzDMzZ06Rj7Ue3fV9r`i1c(r`awz~$EYZ( zf9DL3?hbc~cU}tYv|Th__6H*KM(b2h_qP(vxU76#k(l|p-^-!ovM=pN*1C_1MuP^1 zC?3EI5C=A`L@V-BsFVn^LngN-4YuTOK^n!b+v&5UIZu~1g^ur7Z}=sn@GZ11VYE_j zzQ@VI(*&8usN{*X=O%!DLfbshMZXd(C4;M^?3lIpC!lc#%BA}7FF8vA%zoyQ{Sl|& zPEpFFetO0&9#lQESVF~@>`;DHIeR5H@|0#@?|vrD_VVyROUcPrgo=B`ue~F3yVLXE z2`%Qe*q108MziuzW_gYIW__y;L;zrHj+8Vj46H64PW|Ye5~@Ybmn+5g)3obG(l(|6 z8H1(?%Tu7(6@l|@qQh{hVUCCb%UH7yGp#gz6}{3d=10R8g)_H?2y9j7$HALTL||<8 zt*>kgd$diJr5c*vLx2bud(X;lBny}a5_9%))x9@NNdeuhPHxPF$&o`Mf?^guf zaqc+zmu05=Of-T)hl`vD{F1a@F)7~~+JTXO47Gq(O3W))S##GIYskUNbTz7-^%kNf zc9hF|2BqJ};61s-+baSAazq)Q$ZjGzKl_V7$s-ks$(IrsiG|m#{G5Xg%ki4UuWVO5 zXgWLEGVNbeEd2RS&&;}*F}|rI3kQWRyLrD48xhAX`^vQCz*U!=7*!eZTN#wOJgb>6 z4wSB>J^nA9$4wRv#?#b@^^pcPr`NmuZ{ZR=E>J*{BZic zC&l@X3o9NiDgA=YM_M)c3ge8tx>iQ;Ba0nbeFAq>7o=)~1B(9}_}M&owimINHUTcx zY-lhCHo-1mrLY$|lxyjq`aDp)BeAgEd4q6SYUXRw`Pkk6Fjokg_wv+5x5olj9Jd39 z*r*`(?DWH;405V2#!aj#@!7K;s`#*^f=_?MU)Sx=9I?6dv;0O=5byLWM1`HC_yk?{d6D)teF1~=?*WYW0T^_Y*rJnn_mUaD z{#1_G@bL#2y+R*&h+A5A=EtQAMZ-&Xxi#*=|1OoH%ackUN;75aciv{@++OekZHl;0 z<_L5Ykb~s>>s5A4Fthp%Y(wk^v3yI+^0ie8pa&y1h+>9KR{ipWR5ABy{N=wtOSyh9hLMJ2PW3 z->VzhM+-9!7_tuTvOV*z9=@FO4nZIKFLlkTvqIgaVEUD1^treSVY>&=OPIMURYNwn zUTbx*C#3!tB>{yN^Z7lgmYpr?n#glm*nf2x{;iR};3Uk~Ec3@D2FJjPS9r33d|(3r@gq| zMmUxs^kzoG^(bRJ;h{(WKzIr?z#-LF*B{iU!u8{Mhm+%P!dtcQpmMrj^8G2^t?F+~ z;u`eTl|3R(vs$v{Plik-p~A$;Epsu5-qouj^r=~B{dl2pkTQJI95eY+z{7%}v-oDV zsS1%65$!$BndSaw_3 z&~OG{cz>7A<6zf}l=Dimy|O3D5rVvA?nJUI+mMyYPKKz8mNkG8`;Aup%(ki9JJbw>X- zv1-M{nyfRWSHCS;hl3xD2?m(rZwfjr4Tbm>%gJW1PKfBCI^(cmtSbffrzU<>acR3w z<>Wse7#SF`m6EuEE@?3M=xo+20zLd*Grptu^&OD{LVh|&HhVE!heDUgO zLg%!KBUF}=13pUedUp9f`EL>)vAr>{%J4`_0ly>*`ihEA{`|)#$3c3d`$RI&N4IeG zVuw?X5EiO zeZ)E7A|HFb`YyVvdV&-+y))Q8_i-U8I+Hta8GJvOzI_hhZ7ODuPs7DCMm>VWT-|uW z5Y>78B0g){$MCAN84*KwW~T%$sq~Ao{s7h9YN~uYzR&4+@D7&h@Gm>;S_>2$TP6cD~4+AoO=HQoJD$TV1mbOi5Y;Uh%7s zXYlZuMfB-3z7|iHU<7ok^x+!VbPnOfA;=@Y7*?WCU#9)SxzeRHs5^k8T^b4=LqR@M zSL}J}UfIHfglak)Wknfbwy%QD|Bes+ZAo`{p24Go4GCmfzLdCK>wHfPmh?tnX#SO8 zK!LFA{4M&-%(RsH%|uJYfLCwNoidNW^}5pw0Szh6q|44Yz}zbmX7T+5XPx5{<^z>S zJXph3t$>7nlI`L)Ue@jq>LuITovuhuTo84I^x*+4yv1<5w1Ya(62c`aeCS9^H74C z-T;zLTiz{2Mo$Kmi*{82^EnxNP$q5md2ZKZ^$Fg7#W@ij5>m1#{mQZM*_}^QCR^rb zZ9IY~SKVxci?65$(5L~Y*iN7tdw-iUGvpKYAu5|ups;e6V2@lSrlX3&Rq z7g$fTDEm^QsN1r#&fMp^CPKNCVV@%4$4gm!rF()o&i7QXH)~OcVOGuB2pbK1qR_mY zQDGVsRXDCcKLCys)tvCH^J7(wgjO~%R@ zdVvf6%b$`g#KtC^FgF*Yr|9RZlC96(D3}koq7RQ|Sa4^JY^ogca-7$G(z>aY zBr|xZCh1V~sIRAI41D%K-2teZXTa{V@*d(HK6G>6VDx#s7&P;CMM}*n!VSZBKeDXN zw}u~Ql`d`^NbAHDLk}R|o66)Vw$m>&K4M4;(72pdCN6)aVXbZbWay2}<@v7UdAT=I z^O?&jg6dF-aXY^LhV2)6$E+fTGY1wld!;9)DkZVL{3y?D2qAYC5y9eQ^=Uy69B#j# zdk1ER&a<|N?s`#g^6N1^R2BGV%bpx|zj}a;%i=>B%a>S@Y>o0Mc{Q5VhZx)?X4Q^! zz+tzT2wCc<C>D5Pb4w&)8svKosiuix$8~bpPr4aJIV~;V+b*UL>9-L zO}dRsWN1ra#)^PpiFmX=2RkaIXO`=fikE6{!om+NmHMOBf(Z?|Ipm~reO>fWpY^rd z#A!z2J8daE2-$GeGVbu~RzdE(98q+xWR;K02ta=QV{=p(suWe~rHOg3KhakYGuPCu z3})gw&~*igrL3P*tYes=?MbF?$I(}`&GN>*1)BYt&Y%gfZ1$d7h@I)Yx@ICaRdCruGAiAA=#)A0#aE`b z^#^)Q`PdUsMvow5cb(wy6NVr(%nHn9Y6`A`|;3ykh*lTdhVupi0xMt>c4tMTJWjAO}*Bk$>Ej9L^j>C^v;@ z%Kq92t?J$j9p#c&I0UwzCl_uAevF<>`0-#*>+_~oCIT_5Zk{Y2!7sD#sn3B;{dWId zoWDENLb7m>u^#sqS{jmDXb!W3%W($pj&Q%P>uOK!BHRS8bbVVBjAa zP9p4{2~BmBL#wTm%kLqG%2N)yI~w0zu`%vO0^K+L#Xj8o5EK%BW?{u9=S&!P$Cfth zOg{|aD`dFGd)c9FFm1+#`5^Yy;z{&fG{&!>x64nYFGWVm-xg5*N_f9?@ps8g`!vfJkVYXoohmzn& zbjGlW%wzCN4%%KKpIVX2++c%Rb_5>DK4=3{n?d)%1ah}4a275J5M z5n6kjIMaEm^F{Y(7Z*$QM)d^jPm5igDZi)=Hm*LEG2K2e6sQWnAY7UP%?#qN$8xRm znF3+euJdWWqZdVv)bSU!te^EfE>Z8K<+Y~ex~B~$=f@)S10IaE%LR`CN|HGLh)h z!-XwDGpU>Lhq!~n+y`$D@KJb5Ucyo)^9UVTCk>JO#@c78n;uO#VnOY7JCUvOsp^1& zE+FIE8-PikdQfcnkL^C|4_NQ8t9u{4wNdV3)ZGnAnPCne-AoL?lFf%%>iUam3>lzL zvQS&T1BXbKOw{>&{UdNip`I^}Dx-qjZ*@4}(aa1O*>~sX+y4Y}w&D7wzpA&%AVn}* z_viG!t&^GFQVsOyoTD=yC7Yt_n~&pG_O1ZkS)9!h+Ff6f zsTEi=Qid+7sA+T97X3y2v%t=Zu^FZxCe)VyV-u?bF;AENV=MTTfopYW8ay=rU%mO} z3{&%THaiGvh*{ST}?tml)RgaNr;Es9HMbCX?9eQg~B6l4&+1pZVBF5XPfLQ&|BbFfV;SIgg!=%ztwQvS&kD7nI zVm|i(5ElH;7y0J(H{xp+=(k~p($l1UDDdN)S}EBj7`~%E$%~GoF#>)b5A<(i@#Haa zzV)B_aYqDWDdZN++?~w>)qF&V=?mM~t}_<9L1RBCE-B!h3%j7BNC9ujmo<~dWeAg_O07Vb>$uS|^L}Wkq??^+=$0J(7LN8+94Jz5ceb~CoMio0O z|KFc5e%$DKfwsg1>(8U|CY|B_ro`N{`zfykmr@cWiN$#LqyX??>GlypVwYU^GU5_Q zFumr`+(hykv(v5<>VC8uu$bgcZpu`^lgW)4MfbcWePAG!&BJjWvc3j>FQsXFw*?pG z^6Pv3rqmA@KX>Uz2ELgp751WKY%jv`C}pjWn1#yU9#=W>H`p?!%)2b?i8%!yQiA>6 z87lD~rPpfH_d;x8(A8GEvbCNZWPl(*D;-zR+tyvGga^wD@Y+tO_+HExTZ#Nuoj3FAn`Dh^-N!BfZ=4P&T8qOPtV%$I z^y#RJ6Q4*cll^U-D4=ZN89KR51ZjUSPk#KqQyZG?5yTWfP&YfM%~r`YXkt+;7_QLn zK=i~~n{7N1FVMJEv-f-xK|eF6y6eETQcbbxR(srP-qjuVVeu01`1)HqQgLk?sT6~C z-T!zL99qQhPltdew9>)TIfr&;C5M{{MfN#tZo#f?f5;lyl2KFYDDarHhg^6+}n&2ZnVCarIp^Zk1Di;f9BuC~9B*sUt^gzU2Jgw8KZ1o@8dR`_} z3xFBB(zd<5MV461n=akxboVp4;pLQ<5<8*~Swi|_LKlOIn(lcdG^M*bTf{j!vGz<_ zyyT5CG=FNuA*7^X`UgA5 zc~#hI{U3*dphEu3H%XbMSZs56^3)A@OevY=KUv75y;lm-uX>*cjbFt!eov6BzEuRi`Q%81e~mDf5`_@ z_62yBRM}SH8h#EDO+625zEQCPlgM%Az74G|F@&MM@i(`nH5a;v^v0KRE8?o*EhX)1n0!3|XBDdK(jlFuk6}e^3 zc^uJp8oRNoM{bTTiDoy3sN^WDESl^IlrzkoA@8|Or@sh|Dh*1O>EkvOyRpA_WNd1x zXH3Ni`ZC``8zc3oA9o zGX{THCc$^|vE=>KG&^I~TN9G4F2Y+-CHcA>WoNwl$e{3gg>08U`?{i1EI%*;e=dj+ zR*WdYeu#mF6Z+4>&+ptyK+bDDwUAv9@rAhrLOF0w`pLdS-rtWClk~k6y81E!k&I+s zrn%L=3kNek%4WH=Qq+ENamE$EM{?f1!JC2A zSSr$2FyQ&v9ibOlu6gA8EwB1*7>txstfZK&quZT5fP==oPQm21z8a)0~+l14)w06_y*vR!pHC;)GgRsx$Il zl}U5m_l0EOKDcTLec=4$x9qrG-%zX14%IKn)3oM{mT7fU<(BA~3_*>8IB zx?tSkcB!H!u8Vw%1Jy8WL`~KWqIKcY;rxM&tOqe0DfZqQcTc-Sx9_|-9F^;@bGnVi z_fcUf?sa&>XM^x6{oCIX(X)@1RZG=8<9~-I&IltF z9(p-0WBa<{nnnK&&)EEZ;H%IiYmF>Q55q+QTM`0;w79RZN`ZQFE~iBASf|p%>Az<6 z-^ycdZO>!vi0RG)=!3sPphClu@}QK>+^Dyy4e}?@xFnYjScTy&>FiMN0Dg>R4Cm*B%JJj?FL7@f#Vxg#Rxp^i*!HBV8&hOq~w-opN- z6b%ZMx^MNQa_PhA%&9n8$7gpa_KI1B_3qA6C%fCL-H_4mCs#*hhb1L2X!mWIMXZCoBnjrtD#rS4RH-!bM#du6tD4O$*WtaNw|%( zE8nANy`n*X9z5sx*)=xVGiw^M z{^@CMLp*axF*Mg*p}KA~f7a7?N5MCC`;5?&6Id>7kVPu1Dq}*AW@6q50tDxyHG_5^~PtLReE=qMaF$d0gdWLJm0Be$TwQn7^~4GpF`P4haE)5nCF5D zZ}mfjN-1o7Em70YstjGo4T}-_L3=_u?w`vD!kq(E zFI8bbpYP|epW*|Y(6Jtpr z*5A8rH@(s*{zsDy5~r`+WT$&B)w9*5o#=|aRj1nr3BAOYy=u(Vcv_pIAZXSAAV3~k zT#~jl5Z^U^5Z<5OFulk#MnfuSjN70J#eDSlB?2XFGZABW_~JICR-Vnhdn0*glT z5>lKjLR=k*UWin!^pYxtb9rmPSF;K|0t1OW}t_BSe zcNCFs(n+B`&C?DZ=QbQ^ogc&(;@?ufG^MZ0W=LSS=NbqlBerK$5KGvHV9t%ZXIPhQ zOr?IQT#%MQ2xY1q66sDZzOO&gG^hV)nm2ro(xHX^X%4$OHfj-Xp5#s3mz|=`at`O@ zo5w4RN#668hL>;WS)K?TiGPtAyXYrm-tsJ_OGZiIXnSS3%iQW_8)JU>&M)+%O7RAm zrZc(@P{G&hq#D#+zEJ@R3oG0y^xjU9@CbBC>T8%$>F1N&t86?4y|KQ216f5j-w-_m z-`npSY|$Osii|T5?p}^vCwHlFx`*;)2;R}iD#4x;^@BzN2P}DcgYNWr)nV?Kg6<{K z5Rd7?OJ}!=sxeLGxe18}Q_uI1iBz{z#M!#hYHa^y@uAT`A$d+tO?7j< z*|(la_XL5nw@+CYxEu&9*pf{4(W*h5 zmT^^Cs)thCx0^_-^+4aGl-P~)(eaax9)-;ycee^SKM&WfY|X}g@b!<$!(&P_8|*XI zix{)S)T0n+3s!9Qg0j|AiCZ?bPm|(q85F)~!OZZW%ZqvvOhfb?;wuc>_g7_raXH#e zYk=-q8nK-!U*ovMZ^1Bd9g7~p%-anY^LUiMx4Ds`)I_*DeY;0niYu&v+<8_kNxK%> zsX$g^tvK=BEERB?6Yn^q5FAU3vAR=XF}B-KJF^%9)K={Jh(C^p zdtz;s&Y0wnva>p}0jYOh@Ou%frbg5A37v={F{3>{=V#TOuA*J5-850pbi3)_7Kpt6 zbem2W1EmSGp@K8qjl_-{f>m@qj)P35*4!6T$p|lz`;9Z~@SN0aM7LIQsz(VJQ}y+0 z`?fq9Fi25vO5QGf6PBDS6hY2*#aN4mQl+|NdAvAc6%J>HHCH9D0zce1dZol`_#u8h z%r|k}OJTk_+qdcs9bdG>{Rkku9lnt+pjc8<>vFqOVTLnn+r670H~@{QtVK~J=_X#$ zXH#Z3+h!|_6d%@PsM|#t1kxTC?$v|d>_Db9 zebMd8PAsaiZCN>k;MUZvs6ya1P9H-KH9FQl&(-uk7?EjLzf5sZ%6R9-QNrlQ`3yLE zV$81UE@+sg>{Sy6Bj`vRMLqhC`9*iosj*@crjdq*npgPC@?pG`yj}er-9oX4^ zo86b~-uawz-yE)3q}I*Nz7oAw*bb(u5zhbkc6qFjf5n^aSwbzmYzYf<(9(>gsUE-8 z8kHHO;ClRAc(}b0wlW*jwFuDRK=LbZq*D3wAsL4w`y#;3ch3s?e~avYUlfmr zmdwDf#nKtv8?Y`g0WTTrCzDaqONq1 z4g*M(d}DBdTVi&D5%%9&p_o&git%+VGh04Chqm@RA?FVHH={kYN2)bgwnc zjkG!Hvmrrs-8+AGD`f$CEbG9s)K-@>Y5{VA9GZ`meCW5?3jIvHdi<*YGS4!4)5=IA zFloo)GrN=&`ys!+Xt>g5JvXxOW(Be_{1L|V=ilG$EXk@Zi-?StvPlGdu;m(C=n>vrKhexC;+H1f#nx9GDy^>Xi;g!BS1m0<@1VFoQ{8>L*dA5*kmRkwY zwK()e_f|zxrB?BoM5oJIG`;k+#H*)&^uIzXqB=gf2Ukc`^%L*Qj-nw~7b;h*sh1$`a>ouux30Sp)*EwQVy_>Un^~6)uN}M4 z)S#V>SGjR~sWMsX9BZIe>?j%V=gRSW5L|Nh&=D)o{U-6P%#d4Wx7mvBSu5h$--ZKe z%^l`R*091$J|HTioJ`pCc?QCE?yIFHTBM#X)hY~3AGmnvzxCa zG&X}4hB;A&RS8c7z%4W)+1k11=KR>3mrV({(yPVlBeX3q4)`(Yh_zWU=d+^@w#le>- znG3{zuTxJOc)}lPG?mARN`1k*TOUFk6 zkaSte`12CnqDsHFi&n#&mmwxk^fMz6@-~RnCF0dYv&OC~DubWQc64OL?p>}9!mPQz z9FS>j{J!>>-6p*jYkgvQ5EdU0R26kO;Uj7!X(-sVY1OhS=YcnxSL@2J96k-vpwGY6 zf=N~bo$039XQf|r+~OB=a<1w`4SN4$JCQsp7VZfsZe9fTXWpZlQDJ3&4x zT{Ert_-N~ohSB*kPl^LDm~K}nd$X`E^3(%0L#AfCB@%KaU;DcQBPWlVp=}3g}c0Lf(>a44la zo6yE|n4!+e=FG(j(4dR;ZiV{RSjdLcf)93TC1V#lsC7pocA#%)#?LLxF2D83S&1Oc zrm=FEBVja31&UD5Tx>Gb(OPD|icwuZf8io!_M5*tNG%Y_Ix{vWclHofe-P(Z>~2tM zv#PKvpOUpxQUS+cR-dtS3;PW>W7FEQkQI~Tl z;CalYHuXr&-=u;Fxte~qbdw}^NwFM7^re$di`gM&YO>kzf@gNmcXE6bOWRqFBFDZH z0yk_V={9rHO7&GcuHVrIH$>t#ffV9$VCoNnh~foJ-{(;En5fpDDIqM|4) ziIIwEz=jSDM1R+^;N!rZ(vu8Y9PhIwr1xdU$DNq;)(vb-@Jy_jMB0_tp6`}!t$X}i zB)~#FuAHxD0RQr#tnUuba-p!=Q-T|8KhOI|{OaX^1wq~Bod)nd)nb`Hr@v&tR=89? z4mMf!!G`q{RL&TIi3N=<+}yv zzZ=B%HB&(tvr9B5At#Yf(Uh?@3+pUwztYQ&rBuF)T^IdHcNST9iq>SpobUHn-Ntbl z^@=>+V>tZXxeG@{m7u?iqofcOwlk!_$gU?VJGXD4vk)*LYohDoC)OjVUI-JZZgOJv(Lsvtq1qw!%(6y0k zgKO6d#R!X_Y79?Yn90uZH)sA7ZOF=0$SPQv%_O9ct992pVa%3K6=*l+?1eKQF+$20 z5(ERP;y&K&?a{bs>|S?%+nA#aaN`}~)z*kOj8EZ}PBjDNasFm(OrNJ*FYsv1NyC)W zAC+<&vK~**Y!8%vbf)MDfps5Uw1w?PS1Udm*!sF|*N_+%rtTYS*%US$9Jv?yW?|bg znxd5WmDmsFUT6u7O>yZ&>SbDMg^m{4XL0I!PPL#;G9?crc%ra+(I|2`-uE)b_m48L zB>vqs3@SLO`?4eqNPK`UcA-wV`8HK5l$Muxp%2H}XDTVsZQ+E{ZF*&f=2HK-gS5OU znquSU&N*-CYx)4Mu)LnHKIEW|*l%?o@WI}D6xR(=sMA#;4?7%X++j_n3Qfi>LJ2UTWQ9p=^Lh#zNhhWmE2({}-;LJt4yz&bw z4A&^4Ms;wca+|!V9E1U_8)kxYMd~gtx_-UN4!~ps6l_9_Jf0f<9|ha#9me7CMJx>W zf62Im)G2%Bc}(wD=@eV|3iy6?+Yb$(g}+qXvE2UitBWQ z0Ir+1rs#BUY?s3lSwrpy>u?CAk6p_O8C<~gq!b05Hk+Oo|FT90Zj$R6LZinL2U2dh ze8dkJuM-US2Z1KOPP0Ql0d_2~YBb0l14It(?-!EVnLGabJR}r5B^HX#08wdmD`=v= zeitL8|1H`u)-CZ|%%#w0PL#6?Y{|ZJiw>w6B9s*wjATzy+OoV(KTirJx^D##VBlaH z&C%t17U%r)o#!#!-`KxE=b+#5NoANwleIR_Dx`&N}2B!B9zM%1$Ga?MGk*6)5-}iJU-)TqWd(hX?%zJU|{U zC0tF{ch=d?)KrVJ7%vDgU~``M_6Hvyo*Fb1mMiUhjd2Z08l61TnNZ>?PO@7-_GSX^ z6hb6GDz0NR?{Zi8k}1`oRh2Xw?vr@QYX&JPizbSu$F%E{F79$HWKT~9Mk`oJiV-<{ z>z}V)x3^vQwQH$Q*>g?(PndHt?nt|zIo$b($ATDz(M#ZV)uYrneh2e>KqS1G=MsOx zne;yV{C>aPXIw9%%d;UoU3@D+&>z;Nwe4Acs8gLRx#2*n6s?-6;)_ix7~yprK~T!c zo51?xMqRX4IrQie;0*-#u>;gt<`){bm+m7 z{M@-N|NV!r#$fs|2vmS5b`(IRe^dr6;e>xQH`=vVLRpsA93~|G?hY)dz%H#DegwVk zSIr6V9gs^Er&DgcCzphmLyC!qIKUS1ALTR`R#XJfQR8WA#XZZ%6x<;>0NpourL5;w*;IM_Em|Iu)g zAzmxs$kv%6JGWVm#D!nKD;Y_>x32tp%(PGUPzIa<*c!Vaox(bk;yL_>XM4_uO2$PI zI;g}#8vn!xDTzMdd~~Dr_XTh_#a%DpEo`WGQAPdtPRWp0xH9Hz%JwpnUb5D&%u2Vz zP^rYxs@%U+GBl{BWbjY7b4x|8M(pQRR{`(>a13X4;U|KHRQ|*D-}UZM;ISp103RPe5+jsO!2S)fkNz(->)lXbL1q5HxH4y5$W`w9L-B*B0wHC^2r~QRnsIh_wn`6Gpz*cw(haxg1-jan3a6SD%6y4Xk-=#99u6B#O-T=0?I;TW71=HP}Y7Kj?e;o#>VFVKJOS*k!W_ z1t*%MS+;fgdKuA5v=@-XfST5B3M@4>XI&6mf9?9(V2w1^(Rm3tka>H^5$l>`R?*_0 z9Ip7$9aD^-hx%%j4(wU>P{ts zRirpq-9ETHoCP!X$Ofr@@G+L7bq$YyoE`J} zJgbx}a7cwBjOoqN;Yj1n4E}Fvd$o~^L*eLlv5kbhmFbu`S(%{0!PsGS+-FCTMK68x zg_Iika0z4v_j^H|td0zhLqXZzx)|)U3qf$H!O}jN{@S&wMbp#4-lhVP5qxQAM{A9o z*5-2 zRgL;L z?-w|-+Z_LKwnrrEe(A?UsJJMOS@lMd1)*k3g)Ht0Xs2ZcAn!OA{7NSKL-TSSyl|mZ z>*2DiV&733CmnBD zzd8BG;aDUTPBMng3tVf6lUj@KSXCse!Tr?QG`&PoeJl@S8d<%R&~pN7qhk4S{5~Q= z2o1w;$!ztnJVd_KlJ{aBc!)c3-CepALJ!%RuLO_e?1(u!oC0z?6>@vBw5L}lnSda6 z97R&E92{YKX80A4{Azw0T-pU0S`^mzIcCaTpg7{9ZvUzbGUT-J+P0FyrXFGXVX8z5 z@T|P2GPhXC8K%WAW`a5RI6^Dvi(VFxf zVUpO{P%UP7_tV`R=|WH!vNj!CgkeTqIBA~x)`@IJ99C5)iJzQV?rtf6ra7(b$?jLY z;3W_ceU^>^^}909BUTr4gpR~B3zZ=aM;2?NtX}flmhV)Hsl1nj{$BX{dMZ!!MX%42 z<*|gBm0J${_Nu*ATbj=E82ncDHtL)w^NWUQr_76v$*XAqsU8qjyzjqBMyJc29v#wA z=^59g;?Rf&lQW6FDyNm~#|$4K@~ip@Uzb=m68F0nKrZXCqJ)}phL|r0f{A-ec<96k zr-uyRkce8_-@lbRH;L z?>}FEkF8o3)Hubz77~FAaGw{yt!bHi06ZKNmyuX6O8Jwk-mUfQR>@Zc|4Z^_jDBx! z)KX+~TbHsKi_-lan_S{7U@Zz^Qj)x7d(<$5ptv1HrKVRu$)gk4x^aWSb|NUOnwxzo z^>t$RP)-o&)Ij}njKhgpfpmqKGWbb&Y;Ggm(gS)Fx9{SgHARnf3(vZr3j=na0g()!rP z69Nq=M0$j=nfgSz*XXNLhMae>)E7FvU!U=>-LWTO0Y`qb+7-W3uN+!~pbO}SwfiPI zR6FtJj2rwxzAE84=)wB)v(jeY8d{@K!zK9=K-Q_gV3n@#Mqwjng<@@z(;*&(Gwep+S?A~yP3LeLKFJDxK zajZn#`d$0Pm6{?NA!X>{qUDfuUfgZ*(j7_TI#1rA>*5^z?UZF8(;>mK)-}c=3N{*+ zZaXZQhY9;qczX7?*TH4vP8{h8)2>C7z$V@po9*v~m$lC`ij6%Y7!;`=6=m*dXX?7M z3#3WObMDK>p0~;oM7jrE#B4vj{_FSL4*MS-W`c2mT3gc#&%smhH{Qw3xBdg3yEmlz zW?N&s=j|weaF;Rh)JAu-VcOY96+x_T{?z!xA5?-LKuow0EwNwJ_;zBtYBh891d-|q z$v~+8=CU7547nN~{E{|AO}CLDs1UAf4{`!Ezw*qmy>b5KeqSK37Y+}~Yqc0sVpqx! z0Mb&Q3tQ72JrNPi`BI))oKBlP^{E!ytZhfPASjPbrQ`Bd(Ge*QB(*zM$+f4ORLBB- ztoUWnfr-k`gm*vFpS00!UeHLT(e@CT_ZPa`RPS+jcZeWHFW zoP`wLqcJP&-DSJ)B)F&xv=Q?)?NkdNi&_W$vQYZ1j{}ChAt3>I5W6Y)5f9($ zaV7K(L-!Y#V&@bmS^Gtaf9e4u!momCABij75MG@jp<+OovGe zh;eIHNIn(-nfNVO{-YUt`$Ag#x!rOD*0-M5r8J9s)&Em|tK=8=7k{dm_An(ya^`C4 z+xgLomHTV~b^G#FDL)vSKaZ8*O0NI(>x&;LIjvh9f==9=6X{)lu+MpJka{RT*|(gP z_N}?qHArJzQj)C+I^f}T@-gl;geNb3b3h}2cT#Ss*x(ZD-rn&e;R^(#Z zIv368#@Q>mN^eX35Rrvql3`!mR%z=CC3g@LGq1ozsnE;zaP}0Z1!KpiHf%oBSPJ`UDB{+{Z8vo{QP*x!;{_V ziR7&dNs)AX4^SPhmf*e--|r*JPxxQmwy4@o!i8-BB5#Q+N}N=z!;;J7ssH90Tcau3 zAN6b41$AjW1M-U}YMn(Ry08<^p!RdTDbEclQ#{qa0rS@Vm8g)X^tabsIP|<8o0YlZ z2e@OLSI0?5WlWWhus%28Zi)_G0Y7HV`u3`%QEr|ruS{YrOeGgQa+ zC~HcN^$?V?{|bt+>ojdLF2pyZ#bZ0HoLO=IQ18s8?(?Tv_8dpNIv30IG{jSEvoq%k>tZ}*+N!z!p>dcU#76r(?elj)vh<9U5CeM92R$k=gKt|F$Q z$T3cOhrn)Ye+qjTee^X-$yQN>C(g`btiE2fy*gR?uR)WLl!tskcBaYTu9!&2^P7FW_7XkA;?!*~eC2Er}=VU~lh# zG<6GjC0hEZ!6tvpOD$gCK;cVyQjZXVfj7@A`Dw=Mb7`FLF96Cs|EBue)p!Htjr@;- z-3JSh<%b0#i~?L5shXa{qebha*9s5BEwb&}jA@6iae4k&1zP0+auPWxMQbkhWsa89 zl)+@3r5IkskTA$!O{VwZpiQ%Dc#_z2)GUR!e+c@GE+Kqw$K{=7bNCLMJVZ=N0;j(z zBJy@2;eFEU&fn?L6NN5=!&dCV@>L&rJlQ%8b$S0@DsIOMn`BHEHW_4C43QqM2Gfd- z`V8zipGXUNp`O|~3obQgF1@cARNxi*x~1Y14?Cujx^6Kn6o2o_H+@{s#^Jl#o)TzI zh;g7$Gj80`F(fDvT3+Uv^<`_rqg`=j=3{jZPHU3W%*@K@fX9pzG5qji>MtH2^k#n* zXu1mi=@*J^xU>^IjO;$&?lgJy?UKGP;`yhtS~ES^jvaMp6?|r7hlp4CvuI$F@= z!rSWWB@s((RFl*xlrBEUKlP4ouh>(neR5$)imSB8D-okc|5k4%<>}k@BJ+kAm+q4z zY*Huqe)pWxg>{e5nePoF7)1|0q(KfEtuPOYr^e1DCe6+YJd;?J0Y6A}=U;4^HvRHE z_T?KJi_Ou{Z5~LQxc6!0@Tz|`$gMQ3(gulpkspQ`_Q)FP z)Loo!c`>cq5y%-eCi1ruRb{^S0>_{>(q0!-o4V2YD*USxn`>}mmTJ@9pLh%Zsb=u! zYuCMgDOE3o8bszk*+?LY&18w^)>Te2i{70yi5vmp1^pAY9(|{I1;KB6r>wm`~=9F2?KoxU!1-Q0E)?Qgr%M|sg(7X@nKvGY?YLTN5Nr+d6MCPei zz0b`O?%?)Qat4>hOwXORVGw&h#nb^H0Neo0`p0v4AtKNFw}EKO{1^iPU63R3CzV>P{^)DJHnrESH|0;Fj$Hp7PmkQ+@76@Df#2WE1~E*a|N zzm+gtQ@Z^Khl=a<97KJ(iQ~!4b;jDb7xT8)sdpbC`oh;I!1A{EEc)g}-Nu9a+AlVI+#28u%;&`+nW9JCu7lXVUYWj@%1e++x6 zcQsc+2P0Pxc#{NYsmjpcBadFJ!PE9bY{DmQi%>Z$*zg2hPjc8)+PTM4Ulbi3yKb`F z3v@cEB!-b>$U3uo)LYKM#kF=qm_3$x^R^&|fphE*3m-7eqXxkf4>ky$+u9D!+7BPR+ViHY~ayRD7%m@cStU4!8-cxw`nD^`rK>_4rLxXO@8pN3dtD+KEB z{W)c<>KRZQs}qQTf=H&+xlD9lD7=SY&3D+B{$?ilIY(kdNccBRmb;_649yKg=yyI~ zuWiKjz5z$pp^u(fH{X;NY3cOjv=A!2USOXt#QHW5M9yJe+dG)f+oHv7($y?Bjb=LC zDM)p>z=GBI$Rdlt07K-Y`6&-J{kpUz#NC0@v>%8 zLT#VdaV4A`DmO_L-hQyKGb2xsFW*RYzlBd%qZ|I3Fxry;IY9k=B%W8Df$yr;ZQdg* zS&G4EEy)i0GUP&{6;{vknRqPvRo7ZtM0&8<5J-Q3ER-AzlY`9vsk983+4- zeXL-8a7G*Fi#eS2PUsdZ`=F%9B@Yt8f+EFAgi?*wm`)(EPBG!5FMyeZdu#Lf;IA3a z#U>GFA7?B4rc_XGgP3Ygff~(#EmW?IIwQa$_2$|LM#6CC2B~s{M>*O1#YzidecX#= zLVnSTFoE;9`rIxfO^6)^u3um7{8LMbh4EySF$8MpCUN+dA%{PvOMT=?{T{fj-%9z^ z$v=0{(sVfTLFG$puQ<%RyKGK6dtPExS7bjvJU-YNdg~v}b(u($T%-Rzfd_UZQ}PRh zqYl}x=5bAICFnd`H;`L(?)j943p`4JwLl@}cr$QHlJJHvXo>KS@3f{30>BF35dp*1 zRL=T%4_Rqx86=HEM86P_cSPH(Uk)1-V8GySCUggzYtWbH*n4o<{dRYA;_EeNh*|jW z;0lpVrW)NMT?m23lApVOX1LnD))-;}PoFk7vsMP}Xg%s8@J^30Qy0)T+C@rHi)O^h z*EXzP9pU*@hlnUj5Tlj0j~@Z&Ar>jzBJ#oiV2B;MT>zA7pOZmM zxr}LuRW!3pd2GcNs^LW8YQ-qe)nCDg!{Zaq8fRh%-~tyvl>go|)4G@0^eN?TR8e~^ z$YO zdm|Qu>DAu5Y6X2cp!b|kZy4GwZc~vXR2fWFJu$FS#|$R3$5l;(LdrB>&L_ohtWf3f z2iP%^JM%n$KX9@@j`@-~=C$rdsz_&on;2d+ZGpjO>gpRp&5c7i`39;F#y4rbd|)u% zD3mhnn6~U1qcs2J2p9f4mMK>XV=eWc)t*vxi}DS*D$qIE&{hGO_?F51w<2&x=b_R- zhAvB3THnK7=ZGGJ@x47*&`;hAnGRoqKwpi*cUt+Qk%yKHZM*XQ?@B(V!Z*^sImSQu z{eb1_^_(9GRoq}QJ7K{2cH5!fba{St-}hD?jHtI>X?LQ}?@+bf6(DjUQ$t!V>J<#v z#CCGl2<-YcZ0xeK%)1hMjvntPDZR?atohm|5 zfVDL5x*h*#xYO@HpH7ZdazoAFUG96&Wn_q~Cib}LCX1bCN8KPLA*C+9UTF=YBwvGc zkTh9iDox>>VW6BQB3s*JbohPFa?bIgI(Fi5kylMyK+Es5 zfto_S3`pvcubp|HPE6;9?r0pE&y6E20tHR@?KPXMm!DRSE^)S!f7mt2JO>jc9I_y; z8s~QhNddA(Xz|}=f?Pshv15}nonpj*!$fI64Sd^s!=i<|vXz z2RpATmOw~LUt{h}ftEvPO7sY#e1_V!A3_ym6Wvz#=uQ!zDKQ;PiELh0Cz5$5O#Q zY1y{)RiAOkPF#E*ZJ~x}UBAEx;hDzZ144w>mE(#9@R==gaBwJYL^-O7pd_jp*y)sK z6GPhFX3HA#1-G^&c<@BsJk$(H0DSc&UHL@Gd4o*;)xtEeygs&NF=z2ye0aP28f0dN zZ{8RbFo4HOhLmCBr+1MwW;LoZo62e-|^3^Ds#Ul3|N)CYnE3)edt3_Lj1BEkr{vs zF9u41sQoRiIp7Ap^?vE^FVDYkm!}a?Y`P!!?}th;j9Pd(IOvsUtWeRO%2+ zr4LijC2{RoOH8k(;eT?A>bgLj5`_${4x>*saKrTn3+irO{pLqw%saV_3D~gJwlTgy zk3N%NzN#Vj`iT`&?97{7NqFGLS1&l z-aRLOC`B4BkSCT$9O1}XSp%lIMLkzn56`^xAx_o&2*)JtJCRDqmB1L3+%uEI3CyZ3 z8BF>wwdkn;9XDpuYyDeT$_{ahdZnM_?1~m>mkKQj%rPLA%38#w)6bu#CZH|fdF8(9 zTI=jNb!-GNwgjRq*~*lC)}4%%%C!EZEnXf>bJ*y#YTTeo^poYbKIj7amzyf1@Ri3M zk2x00B;+$BG5&Aosizf!)*i09!{ zKcM(ni=|LXb>Q>(-b#(FpEUvp5`H=7`^mSI6|GP1!~Zl^&i3Qf2a)9DDfr&)8fsQP zL^}r^Kx%UxgS#a6oCF`4uXeh!^s7B+2?l+0UqqQS3oLw-rjGH8TT)Q}uOR~TDS~8X z3ascKP0`PtcKR=e@-dWgJ363YUF~XKkvK@VR5?adLVme$k9r)-fQQe@RT;+xNFKBS zG9;t;{)8{^4nW6r11T>Q%|SfrJjhIHAr0Yx3~=XwRI8a~*Fm9d$9 zp+TodqD4K+xpHLFZof!}*#^D2MD#EIN5j6>a3D@D3|-K8pG#zE#858 z_Rit%ec`{{}4UO9sozE_17c30;K%8vc31Thl(Koc+ zcySL0Hj(o1m0I)9AOTL8z`~Ojvzj%(g6VW{+)u2SUtqYY_$<8{uSV#-<$4hgoGRzmng5g-L%po$LHx#4?H zcn`7m$vazcO%o9mnS{44A=w2Az6N%Z61&0f+1%|5Y01BDLl%%bbZ=xvRX}~fR$L!U zyh|4jW2X))*Sv><$`}5eEl2tJu{=`!6z9o2e3_T`LNosxAcvNYIJs-PjC4$U7z_^?5bdzZ7@%NsnfCVEatjAp^5gxDrvE z{EU(hgi>hcEal8l&DfX0LY3lo(t|{QhVIc~lz8gFg_eM@6K0O-Z`w>*?$_ebS&Wxc z`65c5#z$iDq`*fccA~I^Nhm+Yq}loBb&HB1XPN7h@WZ1~PuD-csCc-4yTQp6CE6E^ zVqGOK$QOC}*$5w~Gkm%~aO0eSm*^0(s4=1<&(Fkz&rp>~W9ptR<(s{xdgZtE++wjH zV5)mW}}fb1uzwPa#2leB=94o5B1kq+g>b zFj5@r%JFCMSKkk)LCeUXF6|hze0fn`NhmqwwxvWZgKxIDF41<_Z{$NsH3U$ z*Z^00u|SzoE$?NQ<%>{(m5b-;fW4d6(LWmUwKb{p+PvPxv+ZR!WyDEfR>~Cb%F*su z|30w~?ZBni8u9RIV&5tAYOMar@M2EO?Pcx~FKhzC$uJ^yFzGsRD zvAKtann#2W?!K56QjAHfVH^6Te#Pe>r=PuL2%nD^r%#c021mT^q1p%~sSt|gUu-mm zjgk-K#hKRtTZPDgvyUZFl~UCb`N{s_7DgVMZm}tNr?;F-Q?pwyl0KWAukMYTXUh&h zRHNB*{Ue=vBljK=`Dxnw-s>VtbQO=v0djZ`#sGcZOa!g{oLc+-eTwTw&HMp|q>0p6 z))Z7!J>JE3oiS7CuOG1hWebBOrK{dvZpiNHuVhqYrrI^u~f_v>d&W}+dBZFC6R zFrIx`vZFE%7uc@PB4Kmv@S~W2Gzsw6>`1g2E6*2zl?Ps|MtQs1z zRqP30tJqYxUbdwWtw287i{~v)qus(3JeTcCmQQ08R-@JT6eU;ziF8Q7WVHK+gB>%l z)^;H2k&mLWif8c|;r*LBmC?D~6STM=*sw9RP}gy!BRXzY-~!n)v$s0^gi;~;RN=CJ zI_J((@a$Ku;-!rD&j!(wGgcL2d4%Jd*OXK$^AgmSSY%U>kfWsTY%cz5yiZ9aho+zF z*rQ0_AgpeitlbX#K?j~ymvpt3oiWGh-&tvfXoZv&W-4~Yz6)E#{t!{SfBuB+Xe*}X z=9FsC+LaZ*<|fE9_^lTEx3M+hH_pA&F0Cm9P$0~oz}HltHo=*oVk;D*ZW!Ho%3zv` zibbx9`Df2QLv>uTBA=QM_`!hVnc8AvV?$E_JGOQum!Qw}x8HoFt6wk6xZX9(u8JtL z_LeM$iBov#+nl^S#69v4iPa$H7QLKAu6zzot=H%4|74pm3dGr_-AR2Cz@!qN zL1P489S`{E*(uqWEO%;f#xu}%_)GA(Mk*~v<9VD1^Fm`XkarZr0`Icw9P<;3>>}t& zKfq;3eURYXlZh}n!;(b-^>lcH8QR5jQExR{H|-8;L*^;$r4s+!uHD7xp(%}(6y=Ui zbbVm?%%&PDQx5T53$3$SjDTJ9SRh->KUW;QgIW z2;+RyXFCP^_#><0D)Bt&L97hkezG&Or&gUmAf^E$a~&Eg81`dR+3?4XNuoE0*_5DWY5s>#{s z_OhGcl=l~BaFT2N?=D~T#bheIP1vCd9E3pE{iT8bv-IVu&~KtL&k8P)^}T4js|_^n zz0vu*Zm2+Jo774n=&u4V0&Jb&+i#OX>Gs#5K2!KG>i|DsK1Lj=_DtYCvWqlF9_yNVvzA{Ad}Kuo!|roqOcAw7zhNh)4#uZ#8;>r+oMz&m zojZmzpXnVrg#sc++P8;$@o~%_p}LOf9u|EMFYc`{T-!cb)Jg<6uT_+lF5^}N^p%_a zXXvlmzVdH&x1fC&&;GLgU?vKsM@vE0Thf1;(6Z*r2_`#WiapyRToi#dJY8M5K7-qU z<*oE%Uh(J(F)aAa5B^|7uL8)`T^k}@I*?gHa$P;>RTIQ;gjf1i$xjzFwScomVuhlE zzkdFOQC(SU;C>(*TiZ}4Ug<9eBf0z?<6Udco!?s3A&MNHptLQrk5F9=h%u&lvmq9` zrJGw9RA;^Jtf%d!kiqDem7S#7vsu-GIkJGXuV8d$50u0I?;p+T#}%ujPndR`yTqEa zu`Q|XGmtKf{z^|SCxS@&&cL3^06Tpo12B8eni@+6d}q9yBClxGC(&O}WUOUc<9Tp+ z&Mhn+SG;1kj@|+;C|STLD1*ZsQ_~C9?G;J!5(hceoMxYEwb|3^L8NO0!4vO-- zywIa}9e)#yQiTXu3UWjQ80UlhwGP0eZ1?z zK-GQ`WjjL1!K!?O6R20dF+!B!s>E0g?C>Pbaoa}VHs}`$hNaq+%r9&U?}%A2ysSli zZn(FZ>V4yD>_<*6hkeFSY|%o~d)rb1<4M{>)JE(NRD!n_2v_p~{vGt+13qVZn-Z6z zJ82$dT&VEpo7sTuhkcEE(w-b~B_4bg2V$WQgF@^{k3A^V-exs$-d(aC>TjhN*y(pG zw`H<`@-l}4JE>oCcz09&$||AH=kHn(!cr=gcjUG@Y|q)dA}OI2Ex#PhlN@A!b-k5l?nG|T!#4bjZ=lIFs^zC%{{mUJ zIiLc7dthR6v>J8U8S?f1qJxq9YyS5B)a_TrrG#{*IIoi$f|+Ep4E47+40FJ3cO-sU7f;dBPf+ z$4b1NB&l#-X;3G?PIbi?g>|`X_Tf;X{_xLejobK&o%m69EVJ7Y_I1sA=&K}iwZUfN zAdGHO$X2k;_fSCVN~33CY*7>kokMw2rZ`wEWcUl~bW;VtUqA*YuV(f+#M`_2X8`o& zGZmkm@eKn20AOdW+<%)bHG{*S{gD?T{*vKyd1e=fj^Si&SqI|`j*v?5pZ&J_*aC7P zukXn7cgWDf#>~8Cy@)u_h)McThUxV_YvEC5_rKG?-%R7z<6s{53OSrV?xw=C=t>V> zQ^#CAnk9E#i?mQ%{da0o!j=;E1l1J#8!asQn&Zs%-WCS_kd~Va&AWd|FYVL*g=Xq& z9r_BsR>!-!151bvtw8%@m9*#8(t-UXU|;pR<^JsT>l3T1a{AIqBm$N4j{hE0AKiEI z1H+31ek1u=tyaw#e*$iwMK$(nyEaS-gIp^8OA4&H<-_wVe+dCG1Ju5Q5AZ@?JUlNM zbjYtcOm4nzK}2zJxW$imv^6d7ZR1vQ=pGTAXRWmw#s@qRm%o=T;`=1i8SpH_AMS&n zT}th1T$jf}Ahg3T+aA0&c0?pSqKyYi>{1dxx&-%=os+tM?>?J#JuzcDFJr)*Hq@45 z{~=YQ_x)*R(?Wv@g5mApfXhD`KjV*s(6L`h!l&PZX_&RF8I2NNC-XgC<1wq+Gur^F zzow9-C%ktTHWIgp+SSW-ji_5 z8GXC_I(nOfe%U3a*H}R1(p^-iTPfG}_QS|W`6!D;!7ge%S!6^gZMdB2#k#H0oE^Tz z()qBbq!QO)QVq5p6Ng!^VML^^^c#SGMkn*A{Vuqz$E}lRa#vFIXDm`fdNjaO`6`80 z3&H4A*RA54?% z;v?R^(Av|IRbDda9P}G{?I;&Zuxy`4fE5P|Jy}{(T&OY8B@uc@xYda3Sg8G zU(Ihc_TfRtOo5|5#}(!c34A??vmCk%mou^pS~Y(x{={!y zQ9K~h)8w~`S}bZw@ryx5SvTUaIWH7gb6Z~+@GtE!z$JHI)<*SojO{$q{pZ7*24Y?XQy@;@R!UN;* zWz61$jaDzuom&CHZ^BY{jdoJxQ+a0*7Vha|i(ISANXhGV=X7`Qv>DYH65$RlGA#hymf6&Ob?;MysXs0nZN0pfR3oVZ!gbc53ed-xtM5Z zkm8T7QZfNldhYTKs3w^wCyt3NqGc`K#m||L`@g5drCX8{`$IX>f%=ql%c502N&9O> z$KiX|#MjuZ(klJnosc4j$*jGd(ZQjM;Y*paJdbI!HXO&SAD#x5gBVnOR5#@_j61a* z^gi3>-sQn4;bqV{qTT&MY0fy0Ih2XSkTkTtmVR-6Y--}}s9*e;k*R%PdqZdz8PVjp zpupM!d+dV_GqSwV8V8%pb=G`?ydBk)20c82qP}-HXEvqCIO7;)2IHN%OpL=1yLa^V z?Quma3U;NusHj4QP?eWx_s9k$P8cr_ zZD#3@7zOkqG0A99Vn zYR@J%inAQ$YH$4M&n(dSYbGVW4)m=@K#^BkR&fEeT#A0D2D1sllGRP!s%dH4N#{2T zIj)Qe+1rHmt-wd2$Zljq|9e&Az+2yEBw*uypXWs~N=Aed@b_Qcy{yCM=?&*T;Fj@l zq7*5Mhsf`tx$r`gp6_IXxGq$&^h`(o%(S_xe~&C7>+vVJZkO8yvB1XtG|0dAmV;x! zLY^Ujsu!;7oM)Sq);ehdtjeh=`vXqG*RI{aGXIrwuG*p(+@KHvm024CGg0!_^ldlh zlUNqP`}F?8Xemh{2`pJ+#8+MNh$-n1tw(Y!f{riD*Sbc8+oSHsy4xG4rwuId@RFkW zlqy6x0%~(-ZthQ|rfq)gln@Tw1ZT?^6Jn+1S$!Z$N@LXzOSf91UEhw!SPrA{``xQI zlvM3hBIv*q?I!{YK(erpt(t}2$3n{F3+$aNhZZ|LZ0|n!AB~ltHOEmz+}e=ujBnNf zVt(X$;GGcPx9f|~7*n41ryk56R^5rHy1eZ5_Vv+?at(joOosc(y0rCfi@ohd%{T&_ z{#`;?&ateQR{fF?PGNp_(@|4?4|VCWSiJi26TWWC&@ZRSx*O!-fw~RPs92j$n=wnD zOq2FENT;yrr7vRr7jvC}U3Sk`r`gPI$t?q^3{{xL6U3$?s-9w+^!h@}_o2~HgDPzg z-t>t)7CqtP(tN($rMjkAJP zlcG}LA80^H`vzcho?7V`K0k#N-vb^^?zXhKSeulMQ>`0EulUr}9-nA7J7~o{son^* z3cs3IiInu&?bUa67n&-(vO&q=P?@=RG3w^ifpY>9Uypm)-Aq(IB)E8l=C<1L?~zB| zExI4~O4_zu!|EFCc}7HPh$NzFMV3z!hShB*b5eg0k5vz@6Kzc7CGOw_76lrLzl8 zHg-KXO?XSaiNBpqhfFLRZlW=gv2&z}RA2`6IoQqi%t;ASjEw!=Q}|O!O(a-Q`dfVs-)9 z;x}ftQqpz`vN@J|5}JOG3;bELRoYZ{hxz7yHS?MWcKmSm1b*Z&6ISJFZ8aUc#_*|< zONxw4@zSzFi(TltxPRRH+(w}&rY?kkw92(;|4w_OriHPyomk6DC!Unpgm3(**0d>m z2R?VY7w`1!nLO7Y!iSNcTtF6ip)XO@0d-&a;a)(_|4{Ya;cT{V*gCZ+ueSDjTUxDI zyJotqDq6K?6{R9#&yX&(W>FMHTYJ|^5PQW|n?&qQ5Frv7@Av$U@1O6>ANenNj^lpr z`?{~|I?wAo1txa)rPsq^r*=s|(z+Zc;3dWqyknQrCDMXh-KE6HYyz#j>Rg{dba;JH zpwS>elnk+gj6XOW60KM_%iK#o{4|5x4mx&IY!IbB))q+tXzNtZbWbdbif$g5MXl zTu&Y9Fe;7Z-o@v~x8L#TPl(nu^_-a5(r1+s*PR4x&Z!<1`B(lUlf~vea4W02;+kLS zDuPF5uChP8pe$G+IK3X(uXEleJ?Tl?>Ot_uCSB4nFz-f&gKsqrxr)U@rffn#3cN9q zkB#-3ja3;#bdHkhOx3@?E~WAtUua%&X5wRdGpSl8c}^tz>z6>YD|@vi`jhw!{z0cch}upYlVo zu$|5I)`muSH6CePtMa3i-{*O?&>Zsd>GT-9baZw?%ZC0YdFo#4Fna!KP>f-9ef))% zKS&hPn|nHQ7yqx3r4X9A(mnGz!7MJLC)x07X?3o85#?EwH|1|Oj({$QT@h1@%;!kk zu-6D!=|4<8c=jia@?FtK@aSk*B0rY6DPJ2fI^ZZSg>nvZeokWw#`vh2RtOlRsP&$yd`ITh9qN07rXI3iRN#<4eO0EYrZOIQ*KZr1B^`eP5W+W}; zj;AAfD|QEWEBPYQpy$M3g&D*-l!*4nA;OH6uj6*z=15`_z*0PqHV}xaAEiAQ5J?eh zb@k^_H}kIbGhaP*6+S*x!FN;DcHrlZB?UB}8mJe{ij_UdWrcs;41Rn2W*Q6g#q zdVd_)NR|#!ka~Ylyl7Bt@*gkUa@xtpN-hN%sL_5(NY35g5JRV z|N3!=xG^}P5vRhx$_*8#^_Nw7^Vc%I_sNv`zCSE_5wGGMP4PFAUVXt*6Aaf{w}t$R z9~tU9Z&3xbC7oi!XBeE28U;$)rOmh#i(YtEO}i~OEnxa@{gx9kUtKxgm=rsiH_4C! zPsa(*f@%w0UBBW~uBNDluZ-2d1qFIVL=Bx}1`gF$K7K!QYVj+4{ADie4MC-kBoM3w zF0jNn-u^q5oP%5Q-aJ#Ol`s^CxPU2X0eg0o?5$|kA93aRncphc@zgda=C}_rD%UR8 zX6qQ|-(0se)kV6>lvUCC3*+_i_(!E-X@d!VNjLZGVo;vLt4I&i*zOj8EGj3ZdbgP( z63C}{x4i9CUz|x9h(@tGT_Q9w5_AX}p%Rbi{QG*quA9 zOnp2s0$sb^K(8GDym`IZ0=VD$HzeBW`|K9-sq&8CtSRwIW)TQU{hKhLD>Aqs`)^XH zMI8gZa8W~-@SAFe{99g*TgsNL)7R+qxbZ&R*b&VY)LZy)jzo6g_*9ubo}Z8=trCjD z7Q$cdXF8DY%63xktmunQrw0ivSKVt08-6Uuto4yt2!KHsB*{T+*-se%n)%-k81L6w z*Pu`R8*A}J7dR#hjX&52V+#i*map06K|5LF85&C58BrLYHhk z;GuCFEERtALxC0Y$r*%S)P1fJNUXp3##gz%`)wn*zRIubz%d98IvvVgfV%PpVAH-s z>~f_7WpqF+yS4u@k;OQ=@D9dS9t)jmNs!^0IyanraL=A<` z*gvg}?gbiJt@D)v^aQx8K;$~`uHMNW9zU~T{WOhvwD}A!nMmPpwoao z35PZlm0)Z3X5zda;g91ApK@)mupb!CQbbq*1j#EyQ+8<~%Gr-73VG5(f~IOFHniI> z#?8fNhII!ybS01_3OlKApxyrbAp3LnzY}%%mqs>{4mXEw;4+VSFAV(I%Ib_wooiM_ z17xRmNM0=L?m>U+U~#wu^uU$9=>#ni;xyIlO0uA5!g$0#`Gr|&s4N{#-mdvz1r;!O zpX2@H-w&qQnW59I5nbbjk+%ICQP!DRHljq)o*Y&fWXWMhSzu@2@{vJUs0EMV_5YX@ z%A8$bla48?vM+v2Z>8;CE5KSZhQc|%WHKDNOOe@xv%1@pz(hY zN$TC9k(LIRCYb5#*I%(6=rfMZfGq=~d5kJSXQw-d{DTW-=iZtxDP1Qj2j5hDFm~@q z)8{_=p~YRQrSFrC=c_5{TP-)~2@IjF5O{P&?Fh$=rMvL$50(`h!D6P64Y5QNFX?Qn zTDSmX9E03-a9rWIv?a`!)?-*OKOkitpC#J-BUs>Z4g1-wbmrC}yRGVY6205HnEYoGevm5$F51PKv=WmTHpR-6 z9Idl*zOhoS?}E6g!^_E`YQ{;YrD;)zSw{b{6WG(7Pwgm8hW@_~s)N$61+$^KSK&^s-lgiV_14{z@;h zY~4LxZi-J82b{dDcbeD&gG96eY^aBW&Rv&-rHDA#F!bG(0aL8#)>F?fe^99a0!J!% z@gEc0@$y1bIq52V7Mc!jHJ`&q4It_{FjD5V7veiI)>mjJ^Kc?wz zhf`alnl=}UHjK>rmJ9O$z+;#$2N&Wz0QxAGGntFHXej++m{uL^~qJZp-u(vg$mpq&%z&l3_$E$&P#3Ev_+;Q`-=vQuvMsCc1}rq5W0&^VW$ z=YSO`P&xRJBTJn)p#9ic4X!17o*8&pq15^o$~3c+GYin- z57sJv)qB>Yp5Dq_-%7z{hk9FUn>t)!=mc0y?9h~!G{xKOIcxsbstbh4>W}};Z!T~A zr1x+abb7qe$_sM-kLesOfN(LPBq-qt<8Ra7In7eV;TS%4k^AS_RxJv{s;7v?@#|yT z^V@tpK8^QW9FMtxO!o4H1kwi^fudA>ONqkoDsq}kLPTxM{OVTNMLV|u6@GV2bFJZ7 z@zkP$2Cs{96pN9007?Jwl6HxlxI9oEXhwz?w3LT|Fyaj#-a;_?m;1z>&h!C>S3=&< z>(X^OZ{S}_MV^!6mgwxznh;qLbJjC&aA^gh4}vE;>68Nw=c-tJI;{yl=quD3Wk7N z9@T-2cTvWkAeG{hs>MD@>h=SEU=AzKplS5-g#&&aEXtd@usbHdXRozCPbs;mp{IsC zDb})U0CgIAAcu&M_2hjSm9WWzh`W{qIOc8k<@2AT2TlSI0dyZ#uH{r8K2gkIJI^{L zZ$9RTIpahYqcyLuh2}F(%=GpAT4?m+h_=(`54n0*is6EZAqH%#I|rOp77naY^MWk9 zL((*^ktQZ?IegH%nKZxR@x@i5Bo`i{!hECVt1dIZ8GI5gC;Tf+G<*-Ymi)SaE98Jl zb-5J^obgZrJq8E)!@2;tFn-!FE2i{foKeTafL=-AM;~y=z%7R;ZYfW(27e6JH5n{B zSU<1FrxC7nJgYTGnG5|}BdVq!VQ#!vU9r%a4dVYht>Irv&V4xU7lSunKJC=)pT$1y z9-G$qrzItI(8BjA*2+|7l7ig=0#1QcXP?6zh#54~7ec=fnrJQT5fvPoJV*pBvb6`S z%mftWL92HmSkBf)6jyUYaV`ed&eA`oG7mwS`Gjz5FqCX%Gq}X;s9Fwb>oj@y3cXS> z_ZI8cAv!)k-4`opF?1WJeF&sg7PqzS=HVBHnqH%5 zg=?xV7pB-eVc+*1gS)&$K*pKpb5whawc07S1ckq(t$wBYho6xwO#wpPpBC_UpXhKY!k;mrLCifxe#Cu zRVX^%NqBnTn?U9^KYT zjBOPhjlVqD#cbMFd4Ji3+8RARrc=MHngW>MHNd)Qp?|MlGe&02gM_L zB)VrpQX}!%v>bBYu0wBHL-5?lk~x0W+1zs76nnU9#R6X`N3T7t=7~}_gU6i2prEwN zZjdzAPT2vPhJI~A(T=WCzks(3TTJzX{{B`4`EP(@T4p~|? zwTPL`?;zJ+m-ild-n}2;eY2!AtoyKEp1SG<&*!=QkTfE%-Dzvc@8n(@oE4U!*i#=p z9c21y=fq4w;Lgs8%}1le^c6?>fwf9pK&;jR`6}_btvmal@7N(MW8gBEuBSkTZC8x^ z!?nB`#@aa9E*whTlD}K&DI;^eVk6EbaPYUb11vr`FMfKk-aJ}w#f5^%i{!CAY6BoW zlQM-)KP+PpkIf3ei!#@zKS=GR5}i&iEnz4`7q(TX-1;f**-Gf9SqYPu>aTH zBuP(g9ri5s+>hPC7Wi9KNx*Ti5PQ2a|s`Gkp5-DJ+oZ&EC;(mX!o@gErq zl^4XDMU>m!aBTGdYJU@;*NlsAt9@)QBf}h}(O+)Y1X_v4!9%YoZneJ|8o3YTRge42vFF> zL!=$!hh!j-!?B}!%MSi%*uXqqoj# zY>N4%29cy(e0b!0j2=SjNqDon2+={B3RRG--qtEosU=Ddz^oWf?f-Vmo);JzCGwgl zCOtPY{;46{(af*6*MUAKj}3NLmM`s?JBIIN{2f0&KLIh73cP%KA;)u|E8(2jTCgAq z|J*XYe6KZRw>SNbY3AC-q!^mF%tcjmNc7wQ5ZIkHS)dpe^fFIYsqQi>SnlE$aCtxO zyw>>0(YA&wfLCl~O?;~Pg>yvN3OA}CPHS(gr8E7P=dj^%gKE~%J)1uwCwyW~GT^!P`tal_! zo&oG(eu%*P|L3(Le}7DfAQk5^kbu*ci_4rO_1^Od zis1DfW)__=4a{(VOQ2*T4C}s?m5_#b&oS*kuKf_=`hLsIpY;nOH#qIub!RkyJGGs9_oLWSsvOf7c_n9ZBPMla-nHk15Z#FtOR%%pfneiV5KM2m?7@E?B6NWE=k` zRW}a#yYzC3m+zpwZ>JyH*t(@^U|lNdG1rfPZL92UPz~bxN$OS8NKhcCzqC_+s8-*z zT+mIq2_=)_OZ-tS^dHj$ILp}=RRSs)X<8yeD>k}XAaEzw@84X>?uo$b-l z{omue>&f_R1Dju2CU?&dW92@%<*Uxwc=2k4OkS=f6uDc*58DJw3AK*N-jF=eGNT_o z`Ir=L5-Lw7?t!Xd0b?d7;UioxY4HgW`=Ici~Po@y**V>^XJ2v&5&~w6Cq)l_SQPi zah^zJw01pav<6VL=JPUo*oHRxo(H*&HAKa&MdF;PIqC*)4w5_2$lI#CBr!qZi+9e_ z#srEOqs;+W*ydmd;hxULr&%l5%BhmaeoCy`RIve{L)X>1uXAvw0j2LX z+tkK|ces!5X{w4lHgSKj9cippLl6Z69zLq*b|JgVY|NOI>qWeUFP3Vo#Jxnr1~7r%6~8X$`6 z2Do6-1ZaP9Jv*;|r>_UTN+1Q}b(-3pUyAe&-MJ#Q&50;HqcLN7X#5C%!`vStTu{A1Rcd_^!mO#OkRlrw^?*6vS-Z*_> zFnxwbL^p&xC8xjM2pFZDT^$k>-_jJB$ zF4$_tt9nlI-_NL`dNVekwx^$zcR8LGzpj+tNaNXCucribD|8aCC9ynxy4N$GRnmin zsy+Hj2{e&Z$>=AQ<*hxS=$o|pi9Nr7n7A=1jl0=U-w-jGZa)9eD|+bgJ>r@2gN z`p6#00df|X=A_irgG+y*{Jw4&H@n|9G1^bXgq|}H&83s+uGX!9l~l;;3ib@xJ4eWU9tT;9 z8uT}ol^N`J48XNL=sQdmrhufGbPKjemR$}{5Y!)~CB12v>khx0!8qSf7jhMX#R3Ah zffk2<-CXAHuUN|ai+{6Ce+cW^pE=gtR!J7l=uRG70A(jN0i(dXkTcezUmts_YS3_! zkL^PXqWbF_h?#y~;Y$%+5dPbi=abim!wKzuKiMEwjx}{T!*<(;5f)Tcg#RVhd*%tO zeUkOdEpk&$3NFh~%m+J=Nu0j{U_=zp`Z=qqdoXWq@MgM@y{frF-wvi_02rS7IlvF0 zz`kVjKvt8Uwhq*D7=c%s*}?vFBy7@>-|(e*a$mH6(!8!I znLnK_wg+b`k+TkL9yT1r=TrOmO|yR2GX}t)f5+hyuj@ViP|cRaq2&->Hyn<;BDC?L zHaM=XD}ZR<=grkAVR&n*ckqRnjX(%udC;ngd{k*pPdftbI=oBe=1x;St@{CLd|YVQ z;K_Z@uIl=XKlEO`2m4ckT}p{kX_KNF;u)3zFFQcB+(}CHn4Ray z3GFhZunk2)zMtc*@79!lR-twLfIGs&sU8aAkp0}MhzEDQENiWbg*9zTjn`6m? zt9W=;-k7dTZ}pJ0oO)Y!VvmOUk-#$9tqT|PDCjo z=V~4kRwib z5(-WCMyzvy2`=rq)R2NK($1IK(zlL!zmZ?_;5UP7Za!3z@Yxn%a^CAUauGNGRFFA( zENqUGdgfMNZg!+ef^dVw9$fZRCLf zn{s@eX7}i1y7m1P#C+@B!+DI3jPWC_=iZbPrL%nsD*f0brMITlfPBnh5qp#>+M1$y ztkwBKYVVWE_jn!Wu!Zfsdo^bcOSr-n7XD87+H|`X8{X=d0(+r&LcTkAIQ^~`u|JlQ zSDGBVWA5ezmo~ph6n*t&MrBZSxftMNb^BL9k^_6&VMX7uHE_-|miUp%awZ3=TJXJU z1xe9MNY86P?JeNLzJxY$?>?Rg8Jk43y_~7mz=cvn@AE!2 zeMC?H!`bxVi+n!v%;nZ~M5mfyCj|KO8wfV*afR+V_NdBcKztKS9g%7*c{GT6(UkJ4 ziS2INF!&q!Qz{_{-9ZiC4S8=K;2@P%nxrBtl5i0v5Hvm_f~_xF`Tp3o-!pNhH%?;L z7TNz(!mG1r7lchmWHGP$*h3~JQU(ML-;ask`x>EFNn;l}9 z>8uX)YZVn+H4z(}M&owUZ2{ys#5?bL9QIx5rUjrNZ!j^E=Tvl8^-*rUidZ5yT;o(u5g(VV#OeCIy`@71s9sj|myrrYX9ZK)Y7T;2gSAr!QTLqQ0HC`TY7# z<3+>ovg~sMBjzs?>#zN=xOR}nxV*yAJu*9PFi}DCUmmCba%`FJ^W@w${p}(;bMLw9 zny5y|n?{#gcW{~)z;0l8yTt9*Dl(YBnWQTEhYAj6pZB;c7b(T-bVsg9s8FkXy6z>= z{S6?Cx7$lKlD`xOQT%WgT_@IG>fTJ0F~(we2kz6C=6JKP1>(OqfL_6jF6nbCS$8Q% zkbHKlX~>}6O97K#_F;;TM{IzT{h~9jHvOK>l~{spRNKO=E<=E^()AzHKQ#SPL{wN< zkalx+re`A7>z?mdouFNLWASoreQOIn*px0HW^}%@E_#GiLe6qoipns){MeTidaDL1 zKkYjQdCrz|SE5-@6^pFoI_a227o-w7UrhGXQ22$*ZM@=qeLD_k86B;h6^wI?aqE$G z6h#q*0$<8+LNrEqYi#8|Q2yYAP5zkbX|wiR&0@as&95sfQZ~0Jh>G3Kah)Ogx+g7GImA!)_1N2H!9!YaJ(0qTvp zL(0n`qx5YKU*r##F47@e)_Tz9tBG&HjWt_vgpGn?K$;{%KH&Et*Fml)i=K}SC{FBN zr_-UKH_+?wjT^u{U& z(llAcVS$zZ(5o}?IqbWu5l!oe`Xp1g4E66TVje(Z{Msn!Uw*QuLtOT~`oK4Yz-Vse z*Lc8d=x(kZ?o6A<8>E&Hxz(J&^Z9m+=|tr*t4+|<3(awTwP**aTjaB#7_$O^rD#fB~$8^Y9bR4~fFxD6-uI)qYB{c6c&=YeH74_;y#ke*f9n^24Nu z+iDhLW(l`%ZXx$-C`fjC{uPtz0JZ%Xk!!o*Oyn5-14LBrR%Jf6opoCtXBo34Q;>f6 zD{H1f;Avtq+Vg&;3ca+27ZY@D`DS0fTIUs-14d5!diLu_MasK(Z-)RzgI6HovoElf zJyw-d8y?fj1f!e=KZAfLm)=`?>5In8Wkiu$##_+KvOxdLt#^AX58JgPb#v*40KfU% z_5C@o=6c0fYr)#h$4Y3Oqr5c3XE`%NpWxgwBJ9gzN=!8+%DexEV2VgY z$O14uN0!iu=U!gu3g^jr8sH>hYtu{ge)o&zBX)h2gngfJK>i@TT)P{d(=I5K?sS+_ zzI07o{w(r70`bjq z_HPdsNL@gLI;%G(%e{q=tMQmEeoPAHdF`n|U+<&VZN1o@YV1_QI?$`6Nx8KqwSUwA#(U6?t1vE=;pH&w9Gly~fU3@mZXyLNIDYE^R~Ao`dTkipGr@n^K2g znwRdOeo0yxf~uC5av~C5afz@;F~$3SJfcf3wvwgI z64FE>J*Sjh%~CnYCzzc-8)6?!;}>7?@3nyzMBBQxOFTC=va+{CBlW^f6E@yp9NaXn zc9Fz?RwOLJyCs1ru)tZnaMi8lNk(>RSufHm>Hh53Uje57E*5VkMsHZXbf;vdty5AM zP+5(r8$qI&6jMsJflM#%BT9=)D_q{#)?!jvU=F#g>Aqq+DJxUiR8-+P4~%*73~0-& z)qG4wW;5rz;^~+c9I6FMYH^&X!W%8DOY)`-2Km-k4s{TcjNRpUoqYzHGu=z&0uluG zMGNLgKZj3Vb4Vk;Cn9h2%@RdJx_t+Q*?zM&uyBh3rv z$cFkXSutxRXkpwS!+yT$s{U#;7$@sA8~#r?E?kX#`CxduBgC%qlgts=BGv78>uA^D zkSO2fF!Xs(4K_28xEzFTOt@B1_&nNl48~J{?V`^5#jyi29`}4K*09+|OzTZ0cahJ! zoruB>zv?e zm7z)1eMl5n67)z`NSJT(-dGPl-~K4}$kRI`UpPlAbs(;2=#Vz(B*F7z)%%0{k#f0G zsi@2b3^t5P2^36vN{ptcJ|HzT?{G?p$>+&nwVp3XUSDf@?KS5l6cGyD-6{NYfE&!T zaZXOd*23BjE}<(V(Rp=mMcMYoB=3eL0({PFX67FjwTxlBLXepbuBxo;3$?jbf`8wY4vmF>SEi8DsXaRI&rJ%2L9O~ta#C-()vcMv{YKB;W5#<^OtAQm#A11Ik1{fWv_ zaR7JdQF+l+>4m*(67B{sHx_0AOVE|Yk=g0CKrJBzqJBcO-UL}akHiQQa`w5!KghM& zzGDBVF`Ys)1-8(wO)as>eenZymoX>#X$KuS;CMdVS)T1xE^HAI?$BAJL`umz@}AQ$ zklA3|Vn}2xHAM_)P2vDUmKVn*{T9Y1X7}|yf-H7F0vQeQz<4)mX|nF`QtI}pzH|06 z%>#s%X6t8rR22Mla!pIZHhg-X zQyl=Kx{?6@tw&t3DQQC@F75FB`#DtRF8EflZ~=BU{RA>MgPE9miHd|KA|)nTU7uju zGra&v-oHSeHb?6y(e3Xd{>Ow#G^Qym#0W^I0xXt)DoWerDB+jJtXg*79ssIX6*i>8 z6;d$4!jW`sdRwyWfNx)IMFlNTTrAiys~5>~?^MFH9jh{S2}ACuvzl3BPJg9|X& z0_3rBMS)+sf)1AfV?X-{{ymR`X8Ta88N9EF{6_+qSNj4`uii`B0oHpO0{@?E7VXk6 z80YVJU?Lb;WbN{|CHT2>u)5?$Hh2efZrCKW3Ru72QwUMVh8iPvVJ%0-u?5Y9Hd9Eq z#$yrtvt6XO@s!*}3*CJ;(Bh%lKu_{Ks29<%@QK3X17=m-wSUw_{kNMFYiA-~^g z(itQW%Ahv&IcU*zp2tg(d@zT1UrYQeGf&QS!^JIxd>l*Gs48YkY-%}Y3W;3H$a6m9 zWB$Eg1ztnnW->$t#MS<#S|ywmTgC5%yQ@fgQd-P@Uc#yeIiRL81`R@A&OW74!;h7G zi7;Ha9m?(OZOFjM+sw!QO0psV&|9GB7y>9{#nnuPA5N%n?~8d__#nnlnj@?*@c9Cq zULv+3kYdKZUm)S!MvDTrFg6HeL@4a$IKw)CDh*Aqyj2I6*co_Z#r{`EKHR<#abF|R z7LGRr_UFJD$eH6KLWC1`VYyOZcK+=av{-(il-t7#)^*?9e4uzSmVL4cAXGL@)`_sw z{0@{$UGnN^=F^5(fA{dMCW>996{6mo>RhR#6-#?tJl=eF*_A@(*q)5sTF z5N~4d$(d{C_jc-woN~;Mwz@aC z`^0mvB@9`Tjl%O-JMeH7K7sF?`%7*MH+*Grgx`1 zss3Y(>zh8$c38C1pk9Hr=wHh^G_{G>C69inZecC{mdHW%MY2H$#-M~8ZjEbHg&>px z>LBN{QXI5Xj?d#}bEM_`mi~F2f>)PWv+srY@$pvvfVoiZVa{Yc^<|KO0ReCz_s@wk zpK5F}yb#mpEie~;^klz2<%-CaShg!eK;2SXg=sH+>tn#$EvEjoCYKpUj;4(OFEI{y z7gR@>oSTz5u}-=<>-%NVNB3r#1o5gXtYh^><|f&teqeL0y(oZBi74#Z+5ZHuiEOBN zOB(C*cXiG-DZ|1LGiPJtgEZJ&Z?`IjvjAYM2F#f14HKVgxlKkbM|E*ei`6HwI@HGf3C7oYt2^Mof3N9_TyFARPez z+iS%^=pJE@aA|^KxonCgPiT-0vlKdMgeWL%>J>Z`_8rNgB1>Obs*v)HE%kk{-BIw9 zHJt}akd|M5$Yz5>l&fjq>lr%nW{eCuh{D^SwL)VOW;QyMt7o<#rC|O~C8=I&-w*@P zwV8k5@9T}==Q28e+%kcEKCYfaAVAjyr7r|4?0nu+M%P!;SpAikmmDL$%L7fFz`&sl znl~W6)7;9HV`%EYLVmH%YwkpPSN5Qp2av zXw#Ab_QfFVF<~{mScI`No$?;aacp=eK9Ma!*@M3sO zJ<)-6rUQm_!SeTaXM)c=crk5o9Z@v-bY#;-QoWVchmN z*!Gyh6i%n$Z4U9)$oA&f-oLQ3wU|#A7e*RmOECLwy`s$V4XRv6;t>oXatsMV&!oAQ zY?DaHQF3I5aZUNBsOJGP_X=M2m&8#hjTb%Bxi(EpR-`%7BJT97Xx&9NQlCg!44L_3 zn_Q1Z+*6zq-0zqtX0A~vw2SxA4MmVudCy?wiv1s5rwIvxqr-@?Mhl>e92?@!#5Na7@%Ql zvE~&2E*s8|*SbVzHV14&u@Ef`cW8nC7c(aX8D@_oCicR7Refz=t@r1#Ysx^q?F5wE zI}2xzp`Wcoto~zqwW+Y%_|_TZmi#Zgg!x0Rg#Hd4mObWDA7_cuo0A>HPH&zCWU3y~ z><9+Njr4EfcY@?Z$AK1ac(PEF;Z;hEzn2l~ho~R_%$=5yxG1>af4IFrBTD5XASImF zsq9V1TedSWi@ImK<=WbLp**{xp0~-=r6>ghj`R|n_BvkC$LUOqK0z9X?2;tLfI-@gE3%e)9Q!!Ahah1L$HxY~F!GSDZ5G5=Or~|7xyOxRd8&l;Gh*ftoE;c^F=V z#--Ao@dOX$h^+nIlp}LquTm_|DUO*%-ur`*F+Aju=+^I}@29o%@xIEv;o{)}_NkZ} zRMkmXb9p~9tvN-2TAv6va)(#-35_0R`XvH83FR4<(ZXC0oSL$rmK{HzAm~G+3qv_c zdqY#@+%UYas2mQ+04l~Cjt2$mG-y*&?BDW*XEwgK2TiV@inul17)dP#W)jZoE^t08 z8Dt9ujQZr`7$R{z0-}ej$$>*zsOi1awQm;fX$}Xb`#i`Yo+!UevqWUI^vYmU0A}O; z&cb{l5_o(O7!2mXXvn(P=;q90w>hp>to)GpYC#+lF)yAOA{zppWb1I zfc?g?*Gm?M?L8og$ipege2a+RhGjM$CZ43t`IgCpZZwTc-K4>S*d*fW)l|LL5@cmD z?!)FffzOX(ur!oecM2*qIR03U#(3nIs7U^cHk>hku@LWe+BCIUN&ZCHIFzMbhNqK` zY&d)W_+L7C;NV1?ly5#gm4+i9x0^OgIf$& z+yGx=#)GdlG*tTibPG+jMdFLcp5+1(H99*dT)d@D^r>E2=~5qju~LottXk#c(d=3M zW*aN$dm^`%%!vp<`FObC8YTY9Lw~SFXu>O|HuoM*(RMFZvEY~W1`3DX>Cc9+_ zzGy%jX)HS&MND|!EBW$8nM5s9pMd0lUiJ4&5o2suMO01yTAc2>2i&_hN~L^P!Eoj+ zfOc}xrM^)fvLYyd=JcbrF%VQETAH;ZMb2R`nO`h?3yM4u6~Wq8JR0$r#i;(*!|V%I z4LW`t-==3^DTySd?&hWemJ$BFI7G$q%pCC~IU4C-kSpa;G{Rq4n+fM6zHV^%0KZzh zA1lJXOVf7ZNWRsNum2!TsFlBVa*yVR&0#eAojk9YoI`R`>$N;?@p;cZ{Zvc?t0KV) z#AiBJ3xvyxrp&+jxeX9>3Wd{t&D(ZNvylEONMQaXBAr+Q?)6a+2a-fqk^w#I7@+E} zoFqhy#47DyY5%#cFx>asJ*neQMAl!5 zc3~f#^-U!D;~jwJT-82ax+HuUkd<$_iT+J?G9d(#dh+Z*)iM{R(|B^45<5A5;F+1e z3h-5w-5kaG#@Ed3OT8ha(XLICrvB3I1~1EA17}|&D4J-WZ;V@MOA=8N|1I->9rExYKsP1gvajLXf-S9p5V zRJtJs-7UNj?H7v^>HAmbxhRhZYg)pCRqk*eQ391h((rXuNB2hYUF>gn25+mKq$RiWSf9xuK6eNUb@Z?SI;kM`d^Q>Hn4%fxPo zBP(1ke6W?jg$edA^z%5)p75M-E2|Z|e{`JThlo_Yc*62mC{_=24|82;M#ExOkpMeKAqZ5&^ zF-mWzM{Jbk`U;}d&wJ#37z5&Us?%Pi33v-S6SWAUDTwS&FYU9~+F&XgJd zt@;clsB-M9t$^Mwr``z1H)bvv8%2IQ(ezyQr@jsj%|#}x9hR?(+(Dm+^#t#NQcP@o z1>`azDA_^26ug7j3A%6St;1WSIVn`k3@RPDZYA0nr{m-MvEJExWbIk}_JV1K_Lmby zrvR)K%kiR%*tYs|6VB*E9zw3CT&B<2xVgn4(=%vUj|$wxl`r)LL&_5SuFfkuBIWZE z=XEdHpZRx*u&Z!VJpC1mDH%ZR5+R^a?s-jFmsqh)T$A z^6h3)e)C~@%D|!?tcbMxkEuTWWYu@jIOX3{c6#?4EWRqiZ%9fOxf*PWsSRdmpi{K! zN^kubcav8fSMWd&qGY)qYV18GItfJ4i7#f*lKRb8aVt+ivOjLXgwGu2F>&G_u-`VW zK}%0$PHD96RJR=9lc`WsSZB`kN9X?Y2030s42JQ zn#6E7BsA)srYRnnxLCg9(oz+vmt=0^YT=qH=T(}JIXKspxTzUx+RKXYYQMGeq-<&j zxo6XR(D*@K-<+a1!Yia%-0BF?;98ZFl%K%=Lq(+V#;B}r2d%eWdaBJm8)mHX5tccvLbFR_HSAr%F` zZwr?&|MS^-e9*l;XBR2(ryt1y#){wBcq@(oHBY5`yH7Pn3cv3sMRy?l1bd|Nki^n-!;EJoKHev=^Di&0Ul^3KN5x0R-%Qm4-@o4Glx z>lMr=mY_ednfL^6#6R4hDsi`9Hi%bBF#1yA=tG>d)j6nje89y08UISZS4?DSW%Ne8 zRqM*~)Lm($sDc5%gOoF@Yt3jWJ6BX|Lis{b)AMYb@??6Xj*Cu^Skh$8WMayfNBY>< zfPDk60SQR+o0-p`(4c$~8Pk=acdJRD(~WY|alAAJ_epBBl6Uq-SYG{NH%Kh8o-O;F zmzpWYpd!aRNG$HfY>SyrDC_4=tzM)v#rX$e-_*^hYR;V-FR$6zRxQ*|mAxw5f0;RG zBC*0{|{4V;nvh2{(Te`1q4M9keCvp zv>+W*5fBj(=@u!;(H#~bEki&?sdSDWIV1;+kcN$r&H)1%n+t#E`+KhId7i(3>wLz! z&pG$~y5FySzKYpRH8qB(E@r999N~7A8!(s50Qp`=&UpUcFV5~BfA}yN;U7R7kub22 z8`rNFiflPbU-c<@2&6}4XDWn%N=slzi@H(JP`Si3`G(#eCwa49-kGm&I@GKNM5GD- zfw~$BKCfNEV#Qrr(Yn2u3me?$z+d$>o-q^sxc)3W-B^6H@?>oKP8tP$>9&CM1oO4( znW2_BnDt+A@Ed>#wRnuVw0fN4bS_t9!Sv!jf<9+oaNn$2RQkp^5&So;VElff z9AYTTJRg~)FS~X%ZRBuv-iK~AP)(}tbM9bHu&osSW${BMp-io+1TBz+WZsKdD zgS=zC1UMI(9Wfu6xYK2P=C<@tOLv{co)xVZHa9vljwECllnMqgW=ks`jNU(^?SX`i zSyrMg`kS;e(DD&p&!Cw=1XM(xMKd8-Qhct;#BA=z#l`oGY4MT<#@h?Bbw*TPxi1-+59km>RrLJBu#c2`Z#ElaM}ESO zFZ?y;{#=`gzC76Lxh;xwS(P8@^y!u5#^|Ww<5E1HV%jISCAwM~T2yNad&~mQM-va{ zZraOnROoFg>j)~>T`s@wF$dHCS~S2SbLND0BCmAQB@k3EKq_o}3J2KnFP8_>M%$ky z-i?#6cDL{kMSt3Gf(QWAU(G>y`9~kFSH7r+i#dENm<5?yU6v{AQN#vdv!pX6=}7cx z^PdEoO%_2N100()$wT zZY}ruQpjhv=|$^6z0aCnHN(pNRp~y$L#{mQR@!$>82G%$k>bRt<;ZI;k@eGsrCYhz zo0_auOmlTZ<4wZV;2eTvxhCU`ORd9LK|h(WZbc<{<2n>`{GuhvKOK_i`*i2FxjZwS zP{O`pZnztmtUR)^@VyD@pEb+_mB?Va`M|7bPU#$5Ym)ELNfm`f-poZw2o_?Vt+>bR zZScaQTxFj4hoVMI#AEx?-B#2@x0f5UA5=<|P8ht77vE;Dh6;9H7bYa+K7?1OiY+e@ zwJ0L?KOplR_DO?&$86*gp@Yu{hOJ6F&(G|OJs-cgJZUFyst1u9dgy3rF5D0tpVRY- z(u{KT|0Av8H&_3s)~=P$Nt;S15?nh0faa&QqhlW;*D1YIR znkz22p0OqEjMRXuzR25*R}^mMeLe0CX`7bOF1hO#Dd9lMvzP0TeEtBJ&EiU^ba5-! z-k3*ia`X7gYH@sBeSJpU>?U=r72d&)&n(#0NKL!7?9=}uuU-#1b7$CZ!j)wVpmGna z2dkfL5kYs(-UVBf3b$QZR7G49wscz4lAf-aeD!u8=cOZ- zInq0Zs^@wRnC|;N!|u18UoDH6-M+K;a8YZH<;<`-7A6DkMh4;p$ zn`w};A@0h&34ub4BbFOYO~F%H{@os!#7)n6FFI|tnDKhm9=Bxa$R9&{#>Q#5g4d+| zV$TP=FLhWk`SxBlPpbB?bAkKVqa@SpO?b$#?e~I8k0-b6-288u#QQdrUK=t!DU;53 zTYgBr8!>Wgs$ewjMuBBuqX%U;-bVYMv%@Y#6+s+ zQo&@H-tuFklxMJyAGtPMCil2FR! znX>d@`9(Yln-d?5zfah;G@Cdb%~dBH^%(}J`_LD2^ZhmMUv;@pimzHyJ6PVTEXcvjomitS}Q0Wr1h!P*ZFT~VCrrXVJ z!>Y1v1e-M+^au>T!#I}9liTigL7(;O!4-W$E6Y0PfMu^C&TRjMnQ1_Y5f_^}qp=xD z6rGMK3CbckyQ$si+kG)v)u8(X#-!+=bNjv8`h@G|P5E)uTlo_>57Clr8)oyLr|U5Q z0w0Q*PZiZom_FAzxQ~tZci|*P4Cwh!c3^l)~NYOc#T!o$; zSj>@6y`0!RA{eK`_xwOz8{uew^lq}s8)vC;Wu@6YuQabt{T4MD=$$TcZMSeHwdt&4 z3jtm*4~20vmrC*Hp!PO>StEU~Bk$pq1~42CMGC!b=_7#234wmHVf5Ut4Lx4I8A2^^ ztZkXF7p_vElzr`d$%PZ7KM0xGa`(pU_w4jno?7Q0bHp9eIc)iaOyKr2G>&uaMP+My zmfF~)K=@#`+FuX~eN;8Ale*5Wn&f*@x_@EU z&p6fB;qhPv&jIgeb z=CkrE|1!3SK``s8V>&D2_FWKcwB|eKy(+Ko($B-GMuurShkkc9Cw$5ND63#vO7&bnK%!VVaF+vLcMMEyDyiU zt?0|I2YrI{40iMY*%f&fhhVJFawUZmBIG%Jq|>sXS_+=Z82p{TDFoMl`bVabR(Gv` zRMy@48OIaja*^wet!^7(GryOv>L322>w}rJ8CMmJSDo+Ck!VUW&OYRxTx(p6fpy?D zR*X@-a6X%$BvZEwZXf&!MsM~7V;n;1{5%WtT2ZH=GitIL?j_T;qSjp%ZJ^EYJiB>?4K7R;k@j2?GplS}I8Ufqub|Al z7XItX<8#n0FP+y-z#_MeXOdg=OK85wYzeXXxzBJDkg+Ul%a^Cq&EYspZSBsLAF9nh zTNndfZw+u>hbJR11!etIV8)=L{d45Gd0h4VorT`?4&1yz@8o?zkubjjP72fiy*>5^ zXK7QNH1$Dq&H717=@tunn%v*kpj1~Aw;1a5wusq}EFZ1sMxNS)HB;f0^JTxfhVLr{IFZX9?xtcf?fDwiQi}76{@cHt0EcvD>u*}aewH}G z^m6`yw;J_NrpSwC-ReWX;f^xJ0c-~O9&NB1KvWQCqCT9){bA4!4l3gre+?~awMUp0!0 zujPsis1o+5m`61SNiUOZR@z_6H_|M zg>uyq(#o{Xtd%|TB=;Oc^AXbxb?)zu2G-1jKchClgSghs2o|p8(7;|lei@?eihhhd zq1NrM1T7ttz#k5?hC|1-g3aYYU$wNKt*WPOb=2f_W!YX2dltzalqgVl82H`;Xl@@^ z1YC`ejm4fj=ll7{<5tM$h8^2O0|>VcUPR-Nzt#hHx&w1*3qX7nT`q`tR-to~#XDCl z*DMOB22&tJ9NarH@*WoQ04=7blhm!h{ZaCqBG^){_Q^HjXJWryoqyI(@Tv3AJ{r8l zBb4o(+BXj)R`vWCZRX3t9XE7LhfjQd9%?$aRLy|Ok@_9ozQR#F`GMfO{?k%ar=76^rdwR7A;Oz#`9(jn!Nqay+)Y@gC+8?e;cE2B>oRft-} zq|-q78v@H6{_Bk^7u0tk{GR&&A!=u6syj8%kaWpTFvfs+{_I8!ciIG0Loe|y|?Fi1dvRhA& zzR^x-&Rc(8WFpvF1F9{2E#R2zKyEeo)S?4i53sh9ebLp;Er(K{_Jy1m8gIv%NGtpM zJdbeygL2IU6Qx9=Rwvm^4neVP>94V2{d|8TXC5xLxi~hZ5%hJuw7lKO^5K8x5<6Nc zazMPF2pCBIKsIzo04Pa4BBsMdKgJ^R(;trkNaPhiQ|m%Aul{gGw1-vW^aSw242zPi>tDnF--j#Ft}_FbHlTC*}iMBr3hM76@It1-Vv?zca{;fGZ^U` z72q6m;J;qVT3shEgshnzpbpKOGy4+$}LD@-}^fw=@RGt9;#ioC8v z*uo_>72i0@3N?c!7UqCB3?GRB)_9el*LW0+4125X#K2s#H($T+S7dn0qGx=+p#6vL z1_zwmM?M^23(l=m%hm4?QN0#3AH%#$G)rBP{AQFn<2ce-f}|O1s+X{qDLp7B{FpJb z!Y+dra(QWS*YTM3tYI?8^92AG$SlCH`4Pva5q2ZF@%KPv{r}4aE0?`L95vsny-?tCwvI0^ zAesbhyg252F3e)eDbE^S&XN@CMmt|GN zxzZ=HK_65%6GsXdj&(=0GVZFf6A!iGzJ*oVoo!rNredaT-PXd>ASB@}U`a;Pma6c0 za`QX6Jh76x^E=YjyACjfI)_jH7cIuIC0P#4xB|&jKq#3a_;7?KNvHu-HBs08O9)%~ z{}RITf9`Pp{HrJ;LEw_srutgUSowh!$i^wZHL<@FxlYN}v_IBFU0QLii~lATfvceyy=XQ&RFJaMJgffEk>?Z1 zBJJxwz<)>njKC>HIBhgL_+3t3-#vbbShQU!_GF~U-OKV^rD8r`wcK#0Oio*O>{kk9 zdK8nF6c!6j<|7xrrE3jZdaAo}q(vBLFFLBsMJ^QNw1OxB@1tyAE`@wWH#CtepEK}T zddP;w_Ig6kFjWcW)C8MC$t2(zs6w5cWPpjzzx&qLTBZ}J0DM_d9Z zA9j!Rl(kZR>5YZSCFsQP@eb|&U}vS)bJzEMtVS^GXNDAL4NYv!n*wC;QVnE z?;qa0Q@0Z~KKUix2^>!1d)y)hBOG_<$BWV%B|qs{elnX%tVn%`;KT>CyOr#~grlgq zR0twBNTa=Z#HS$XvOeOJ`ePREv=^*^!{OhAU8QE90A7G8aGg74+B6HT<(MpbW+YgU zE^r}^G6U32kBI4xv$Pw;ax45&&w?&4SF)qs#UlVaZ!7od=Dv6KhtI?{HhFv;HJbSS zFs3{2dYkfJ{ZD^%`Rw&Fy@lJ?Tl9FC?au)xl@6HhV}8zY8v#Iis(|Fr%Gc@!qx8Rg z7R21uMZa82n3x>Bs^#N?`u>ZC2AIjyZZM|RtZgFfDqOzC+s#$7c*#v%H2S0yPw_$;EDSNn=3ZGdnSaNTZPOET^5(A{b$OfBm zt?UE7BuwDC6*gra9FA)!2dcfh)NC^Fz-SbCKcO>|yK+5>g0(EkI-RZ!DZQCove7_XtWIVZkfOANTcFo#r zsK$0ATxE3+zl&R103CtvsNV)2$L#f^42!K6#E~OS`-9WN*rj6RmcHLTBEPiX8|a3n979tpHl zBn8R~3KsT*rYPE@`6^niSM~g5B4|e1rxz z;=cJ~N6Bia&7>>=y;hLaP{5vb>!sZ!FGP>gAr#^9;B(+Eq%cwYaI>$LxcPLdB20}x z$J^1HS}-p2EWn=eV- zU>?t3@$c6@{@mo9Fg#5>meoo=HCAhNpqUq2&OLOkWPgD(9+}==D$>6Xl}@qrIdFia zWo+0M7Y2HKN4f3jF`|T2RQoe$lCvbyxKtYyS(r9G-BAaQlVjRFxcrZ$?&Zj10s|u_ulm?0q&~16T|bCAX*y zhv44Ps0bNqR)nxChP7MAFUvC2Y#PA&GpsT^3#yjeny{(-mPN9}naz_Sd4$FKF~+hn zt$2R^eq;JppMG5rN0zR3*Z}czq z*`l>4^J7mNrwxFAP}Z9P3{&NV<1TsWZFx~AAlaiSYcn!yNOP2jUP|!*b|mYfIBZ7t z=ast-cMAu^Y{9cA1a*fS?0Y*e-$sxpuL(%0x$#hAMx<9v))OPNGf2RdzxUaVvx;6McT`9jQ_b_>w*jLm%0$Jjs(DY$##vrSaNJyvipK1xeuq zE(SqigArb$6=J_7X}QawJ?(z`zI~L7q!_pXSNXNA#Xb4z!4bZd%8Yvv+_!cvo2B?H zay7;S{`GN$y~wFUw`92SUmCkhNN3bnZuLN(=P+6Eqs>O*AsulP_U=x|1h`j&0ne?!WPOmCU!f!_>l~f zouV>e%&uEYyqr4PIl6%zWfDu>E3$(Vi7Bxpx zB$)5P>Sfz+h{ov-$DnjjU0vAT*ptH+D#tthkv6m@H7AVwFwYEn+!gZjO~&czWq&^$ z4+?#guKd=`bW$zr`eMtS$#p$m|GOtD=xrp*S$G`^pTqsC_r87G@h9pcNl@)ARqQym z^Y1~7Iy>-)G*s0qvvEya-es~32rYIysH5ik(urR|YKY}DCv2XtNjQ@{*3POAo;@;~ z2VyPkL+c}6myGBPQkL?b;^F*}ol3Op6jS26@Cw&l9=GygV+uCDL{4YUC>4!!=2}g# zPkuU{Bp~fENN_TYcikds(->XIMnS%W*oH$?ci!2ZMx-=y`gZh=WxTP(?Yw*0US0PZ zUv|6PJgYTL2?b-0SDebp*J!=SYlkDL5P!Q0EA#j}RX29-LPyN=y~WFZlioj!x!9x< zD5=kJ64+%sr@tK2b(h~-q3iGS*h*|$rL(s)gy2$1>AA}G`0ZM~{R~KfK2--_NANv_ z^x^oqRP~md8cO!6m>UoLdD9PA`%Q<;UkfUou5N5wXti;qHy(3}HRDJ3I9Y$f=azmF zLI^dhtc=5}MVgav2=>K$XT)OGkn8PR=<5<~cZAaR#P(S~0A4Xw75s;8C~zjz_3ifh zDML)5j`xz(`V|zBtmplyO=E6cRM?a?Bkx*dOC^So9|89d+UAdSAplS1Ako1 zwwT|8O;vnP9kG=#S7<@=uO|mCsJq)NS>zXWb0ELP&9K$}*e7=_`vftNX9>He0RZW< z-k0ZyJ@(WLeceI6HCp`Cc@|eCl@izHSpibGLTToO@~f`#&(UvNnLvCEwMIao)f%vL4To4e91Y}!CYc_w;`atRg7;=iQ6#mX|C@5mbS2l?qD!# zLwH;=SP0+5GEXypIeOiF7c@7g0AWn^aAdd%P7^s7*cZuYNta;}Y86KFZz*uKJSDVF z%b@5_e^KUFf8~XYWj!^Sz?hi;3o7Qq0Xl*(#VKiq!6mTJW>T7#ix47b=rc7h)YJB^ zUJLxYaD+`qOoKITG>H_}JXVnG<>+E8bVQBtQ|eSpUe}gpu4}O@@1L6Tn0TXk^c9}* zRwh8_v+verd5EljCeVnLUzD?J4E9(&|B|HAU1WqO87?>Ji=dx)3h4%5@PZQKkE|S2 z#FmqJBJ!j-cwryCP$`IriAJH%UFg=gVWsL?{c9`>Q7MzzwCi%UvUsrsT5vRW>G1%90g7G2>CI!*_ z?KP)9y64l>R2#%M?#9(QC$NXTFRtFk6fm}|%C&t?aSKXjagj# zq1iZ2F4`n3_ualg)G=|LLxM5Vr_@0fEF ztVC4LnqPFM?ge)H8fth$MFOB20zK{^3e#S&U!6SPE zc3H@!W`#Li!h4h$^dr=W`5MY15x3C*ReGh;#sKV2NYOJ=iETm;T)w2hi#q$--SH}GOnY-_V5;tyG=x2j` z9PFd}BeXz%y53O6U67(xwF(J0NuC7UMjo;S<3F^zPXj7IKpWyroV!EnR^*M*=A;>u zCMv~euGjN}$5d~rsoAgd7mvF?>!<=bk!jx{CEAd3;f75t2K(m2a0VKgbR}OkB{Nv% zfy8))5_CSp2tn(HKES-6MGPX{WM})EFIus&OwWfVNzV@3?_S^ax8n+Uf`y<}3575j z;^@KawKZnvlX60xF64fS)x4lkktyGkx2@{D%`%rGIsF@N5dX^RpWG z#)S1t2{k)1ug}8$j#U*}gT?z;)hbOkVlOCvmV*p?sd z=_V`LOZxPW&9iAOlP;_@+*k-xkQspZQenWdM{w=DT6TQvsSDSLy-?DH&_C?hYD|r# zNlVjA<#IHqV~Z)ZYgE7%b)$yynwLslGC-;?=ma{4GfR6K`+J}v-tCPgUB#)A^!Fed z$sy5BN%Fb{Pb$Y30)-ILX^>RLD`;*(Z~MtO=-_bH%rTxT;g>bT3xh+t7Z(aq{bXaz{nUYrO;<_PYq_Dhk>76& z_>~<9_YCd{kQ{UqXGw7!kgvRfyGG~g9^J|`&qF)fUE5E9g9`w;=`8E?HOU`~Zh!AAr4 zy)^_p{f~{X3a3{UB#jWf*B)GMfO6lT?V8sO+T$i@)^0|t7&G>3c&SWY7ndNwGdXHo zagIs$oi@L=OoW?vua-QO4IV;e0{LWYkjN0S%XkZQ+vVvyX#M%en@r)xKP*W zSD27d!OA#no#-HVtf)nT+;C=f)r*hi&e_`&Sc?Xe#C_OxYb@L2rjr+E5ksuLFXvs~ z!J(5lYcdj$gn2HB4ANLZe5D^w-ng9G41~g* zl)_bK1qz^3sBs+o@go)GtN@P>z8(&W zBEmjF9INW8)F!`CMj~uif6`s*K=M9mwK{$K7NP_3Rf(-dsJc45OJsAsA3G}0UZf_k z3s$5LDD<-yIXpp=IYlI&2^@x(V81UbA2+EceL)q^x8+g4?A$3%aNayi!vbRX09VJ zAIk6R$mp?tJtp0~k)P%sg}t>!=fr)xJ??q~%rOp_XUMzgmRCT{+Qz>1oo%K+@baO9 zX96?ve{?bOG;R+m>-wbS$|7@#@u14pmS{W3^?o)f5jKrzW?eSlhFafu)+X`4sgbMN zKf%mqv&2#pt_AlKo_L;RnVt6w3hZVDn3abjUszS6JcD}!On&~#7PR2s@f_`6|DFVA zOwBj&RV;_g*5E~OmwphPSA2qe{>sDLV&rYzfy$<{-e=>WvjQw$eYtnjw>LmOw z`&Qx1I>II9F9arLCnhW>u*0SNmTVh!2&O(dh|HNENYlgP24qM(kt0yav)7rn+KnUskd+I6`}iWo7) z4j=lEHd7OPtFbA-&Hrd|WECBAH>psj_QF7aKRl5p?}mZ*D#>+lSxNMj7g}5ExH)Yz zbL!j=Ncj?XFXmcb;057o1^=}a+o!bNT_G_2A6+rsa+Tenm7~lGIG<{tsmu_w?5kMz zoT>+#@aJy%JQ*+ZKN_3%`ighlue9V51v{ZicQ~OEZHa+GwK_*VNA=*~h-14Sn}W?N z`NpY64ae7)i(GghUlMLx-TS#*t;JcX%L@sl26I4KK~=oSr zdvPn3%N86IWvbZE7w+n*Vx?Q+2wQOQPuoa&FEt328ctXAznO4m^l8k{n=r(Z*AU4m zk?UF8VZKWzZ-`Ot0~37(Um>VtT94DBRtoY3y`<3R}gy#-cecWZ&k z(^2Ub&$?mK$#5JE^q=-q{mehQl*!25MZte`20J-gB{S>By}xhEFr? zZ@H(79h{(;xVo#xIZK3I%_IU&CG&%rmgw&anadqF%=-4w96cs3_kFbTFGgQasa`DL z4Qn`>iT*iy4N6< z;@GM-FyF@z;g;u#!nwmW56raRV^=3#(nSz(Z??d~RN6@+AT=3$t+Z27`iJ>Wsk zMs-tugx6V9HhnAC^(yc!jq=r_N?ZV)3}+_}1Lq`7wEG>&u2(o(=B8X!TGXtYT(`Zk zGc7-`z?H-8gFbryKyZEr2odR2hX@^Z0EGx&*NbroOurFMwld#>Vrxa6(c*pV8Se)f z@1`>3W+$nz5{30UZ7&7Y{a&nrFKiP+HV~!ORu8=;R%n=tC7(b^a-Ey@cJ%O139S=vyi#w}G*LQ05NqL( z*m%DZls;$)%>n?)hPe!rF%xsxiV`Bj_RF&-Rp34NK?$%kF_Ac^A!KqYb=7GoniI|U z%?@d`3X2WXar9cW@_h`oT&K*f9+C9Z>=zXW!rNe*(B>&1jxm=m@wSrL&HBlEV_>o#$Ha zRw{SWTG@tH*heT^&I`pAj&f_0PG2V(7Vr2+e)0GN)njbk_bAV)Y7NLxr1uNQF9IUc zrAFB5@=5(BRbUabg`6?)NulIgTrfEH(Px-$PiZKBbCCHuW}w-&4Y)~De2+?QCC#Uf zw+RwfqU;Xa>+6aLmi=R}puu|4Z;cA5q~h;Ydkw%CM`Q9xHcalxvPjS$^;gl5J+hL- z50geGEPDr1#n{Nx!6Ee~G$a&P@WvrJ)Qtl{z7Ms#5xfk=qMb>!fB`EU_5*EvD!!NB zGAmimz2HH4v*vi;_>~^%5lYH0f|}c61joG2VI;vIl6^ZpptQnmX5C}G=@rhkl~Pi} zJ~yC5pfW^ChPq|>-#B!M`Ea$fo{Eq8wB@)Q+nG{l7E6uF7-$!Rh zO*8>2*IS__Bfk(+^5K04b91V?!EVJae`lii_{w(&3Xb*#uRW>3@q3a??bnIi zj=$IZhQs2?Ji~zsJ>_dM!D9{Y98FUs`4-PfYeew|x23al0j8F9EDE;Gd7;NMI zy~atN2uJ$_=fW_^RqNNtC*%>}IpQc^Gk@kND6sop19E}KBl&#BF#Res_RT9PKY> zPem+{Qh!kQS(QjleQqtpIkIk0DDce?{;azG zkO9MygN;1gC$*CdDECVyzFf_5@g3aqeKxN76>&fGgZw|btl4ZSu0oIL+S;^P0A*>i z`kOM)$-b0^@T3mP>}x^h;lmTfu8FmQ;`b<78uew!Y*1!LjNC8yBx)}2B_R14I5gFy zW=?d{M5fvtf4G_|7~1T>3$|8%yRtc-3g>F%iQYRkERHCcF(>;3eONAP0LY?g3zLQw zrua%Jop`dmU{PY7Wevj+%r1)id@Q{prui&V3PH*YfaeHB%1{>V!?HIg_@{mawXQUl zuU4w)elUVgrRu)5nEN4>vEHZbAZ2h;Wo~CbI^u_7BL#EEXUmd2j>0z){B`}GF7adysqpR>LMFczqg{uCs!0Ui#q#c9CkP%~tp~u(` zxsyB!+x4Rr)Jjb3`3f|1gl6kVM{9}$qZM<^8Y-tF5V@%7m;^PlPNHP+88ReB-%iH| zs*sb3w~Kq?1GSoHeVSPtTDso_JZxkvRNukULB!ke9_t}{kMpaM8E!TgFv^>gtYM}L zNKjK~D3{^ElR-{jr=`3$6etihSf!CwgchaDd5o7@w{~Ej&%$AZaqZm~cv}?=enKz# z?JeL*1qpkI^r&78^2Q#>$SrGaPD*pp{AYtiXqV354N=pVeO+#UV3uxX9$(~|d%LC0 z`;Sf;kOHHlwIma2WcKHqGA*mso8b1;yo2~R3fHIcWmpVya;G&JQR%yKFYOjj&u%xd zFz306C)k^WSvu5=j63CdmO5j`p;3Vpiio5t|DHQrusPacoZB$W=L21X8K$>qGTy28O-jWjLn1Qy#(VZMIE1fUZ<_Ji zvAHvD=@k&`c`l_<#i7beo6jwu^;3+LgqH8~gfGoMf^Z$U^Q#~XdL^(I$KTx}vm3!` zDfX#CV*1HiViSpR^-MKKTmnFlm2Ol$+_H3=4F@+Gc=|l~w#gi;xx_+Q@GAz>~q^v^?O_X@m*()N~(j z7HsA=(DwS(japk~!1=%kk)n z1V9`%mHEh}M@>8K?FNK4u7lVffYMV3zI61SoXB}#Ed!Pa7J1zBbF}Lv(`rk-&5;Ym z#}h=;e{}q1>W@Uukd1h0qv~RpyCvd1{?Q@RTSnOm=bFxgyP+t zldJQn7fnrnORBQwhXF6#{L-O7lA&A$ZKi_kJ)*a#2%SXYkaFRmD zb(W4T;49|4L2p)S(s^0Q|01(@Fo9jA?AO&*$1rpls=OY^Az$pG$ z1TUv8Kpi_p7#F@e;ugr{5vXg^Ss51l+2XdN+%Q#{nA5VKZeDa%0A4EYb^c9ovocDzp%x6llzBnxIVPy@|ny`FvxQ{5m1D6`9$$%n#gB2Rx={?w=L6de9;b4k+`NSI?Ymu(E;#vBLL6{Eq-qo{SX+fBKhUoi zfBId$Z!l^$WfB^&IafYaoKdQqZk?=bh84>{(d}7k-0VEKxXW6+ldFDMl^4$A9wag? zF}13mpy0qyR4Xq(l(Jsl9BZ+y_8(t5oZ|&$d?(Oz^(-|g{8Z^63PW(0mu;^Qd5os*#{4g# zEA(ZD#`aP--hRGU-)H2TdhEda2V=&lKycZ8t&Wg~3xEH6fM;5b0gCuAh$6&)=a--2 zoO$CS@EVG%gVMcL0NI)6u|~SVqn55n!O%K*RP+f`pU00o@E^{fR~6~x^_O830GxYY zX}+BYtfOg{J{kY9lX10E`FU}LgyL)S0gt9#Ed33-K#_>CI#io({zin|kKPf3 zH>zmOB@0V?M~VA3@g}whtQkc*j~hIHIoVOE3)_AZQ7}8eQs`ONQ#Nqg@$|jsoCqz- zmMgLofKyy>wkwFAt)oo48RI*gi(D<~3#!w>1xH4|*-&acUc0u=R$=4!Kmlz#f2cXy z&knw;zq!k7f+=Gh6LK9tT#{oPEKkgn(_O2Rx`mJ z0v`c(NOOSGH`azMusw*ptoV8K1`+4R(Yq#g)PRyWvdiKY%qGCa+s%G!Ym)wB zy!QPGs;0r@hg&joe*#~7VDnsYG+u&`Z`^UFFK@6o){ux`SS{8V4%fOyd_$rbS(c3E z0x^w?ybV)8s$8sRu5QrG^E8-|0q7R%%Lpq6UzC~{UhrWKtk*be$Wa&+>gmagC8b0my68Te;Xng^EsX zXZva*TQUdXq@+q{TiS7x%1@W!H3N6o>L%+U|GxHsb+Spz!t&SPv0Hs6pA~y6uzx}g zj`}M>=g2VUbKjE>M1d^L7};`Z>Br|kHuY=p#Rk9Y>Hj6G)J?-pffpV`DqBQ$ond`o zOmM{s)=tJ+>5Z9cYh8}S;;X&VA)t{~^NDEr`yJc)%R_-qU7Xow33JSA_*UZ<@CBx5 z*<|^?zh=9lVw~n`Zw2rg!<;^^j8@CPm4O+ypCUx>z92hu@`Ilya|5ubQd=_!#L2o zH&cq9PqJlP2Z{rA8@_Tayne_TC-sZkvQSsUI#CKb&Gix5;?ItFafTX{=Pg>+v#381 zn5T$0>*9U!ms*!G$bCIt*1!Pm_O?H0gN1o!-MksuiK4=pP1_AtJCy_JWjZQ3siVzj zDm3Tq1j`+nhjV5~5=fA#xh8b7+J$%wCT*W-h;16OxK2tuomS+Oj zCR$!5;Y&He#5&veR5}5vi^9B=Fl;x7qfa+Q$OhdGYd!nbbjmdz=dU&DLf{QvO_r{t zP&bvDmR?xSUOkZ+P@#m{+GL9M*fu7pn27X+#ni{7gap}m?_pVQLRjh;34xUD=BSR=Rp&!dYpNR7f-SZ6_ zlzUVUnc8=isrl=S;kSltPruo2ms_)YQ-xf=xPxcm@mCjpy6Rt!lrPf6S~ZWDm)0h% zmdOv`ZchB-C8*()H_g+Qlj8g{`Fqz)n4teo*K&qd*~ZyJ-}>)l3P4;m84iV`E5HBM z)%jiaSS&jYPs$9C2qWmZrF-M9A1Fkca1YO)`1W%;E{rFr9LSz8gYNixos|~OO$t$Y zcgR@b(yeI`4ju<$;=t+2%y+hMXe@3BL8i0>8(q`UBQh*|MRx+|BdlM77F}G%t!s%*tQg(h!TXKW8mi7Y$M>EqDA;}; z0T;_8J0aoj?V>y2Y`VlUtm{;-n4dU7n_u{X{o2#@aR2tZ|BPgBs3<65wEgO>@i|${ z3=)dFdVr8pZgCDUZ zwKoMS7vo{+I&WV;PRv|t<~F_D{Ch2GLmrQ>M4m)7fYCYVRSQi@DxOZ3tac`S(cQ*& zUfk}fAJ0J-=RB5Q_s5U3>|^tvIx4KYCoZ{h%P;CUmVe>;>cUNggg!{0QG`GeCbe%4wVl01 z-0df8_B)W1xP3<_+KfnSz;!Eszw%dDtYuhCZHR|WQ#8mqmoUDIP{?z+Y%JpgIwT(6 z(qDXULrtVv3@tiy3F~;)Cg28GX4YfSyagoZA?3Ax!5Hzi2&ejv=&JC zmVvI=8Sz>dVGFDCdr7)=Sp;Q6;3e%yb!BQ>&Wf*yu&uIdlB4v!nhK}3ENz-R1SXz- zX4XQA%CKEw?Pq^N_b~8cH?-~mxqSvaV|xoppU5%TZ3)!j+$Q}X5GEkOgTW>F=;$@} zft(d8#wSjF%FP@L?F(O?u9fWbo@9|)_Xo}^a%biZ*i21{GQJ@9YOQds7hn9ZuswU$ zZ$MGNTJ8T_g;yFIyDJkgc#gESoJD-`+E^WfHH$Mq=*3Oh$Yp__UQVN)oto8R$C&=Y zy8iu_XDia&H|ja~V(TtC!S`TY`0(`^vn?$E6&c6|M~xrR<2aMtvbR2Q9?@aInk&B zdD`qvD7#RV&tm8>?&j*uys-HLLhed_)3Cl>Uw(sQT|(4W;GEg27|zp7RX?rOTc^1p zCGTJo>!hE(X53_c>Ziaf&p(0C$Y5B}97?G;F_*Yhy}K+ZxIUls%hYZ5JHnmGe2Sn) z#8;Q5*{U$lE~|K2P?VK5cp&afLG_zhh8J?BA~t;S&|$`*pdI|ow=vW*f*`|sFx~vq zZ>HL^eQ*}pI6WM+tlU^sfmD=!RNvU30Yxd5LR`(>QMlpQJxbP_)^ zndjugHh$fu+yJ|HpG2v9JQ!*hpQE_fSCb=r+7pZ(iIgS$lpfQ)XQlPNwRwt`K&_twsG`uw7I7$K>9c`XF0oR01EA zYl|>T*s;8o7cJ1Lp*4E2FlPYf-D4Tc47hh5=(Cn1*WvKjTqjgoE1anGilK}hHD2>We8Kip3 zozpSWla)6uKM-5mTddG^pZdK}B4L~#bSE{aMsU1$Nc3@WbD|Oje=3CSJNb3ArA5zw zFaZk6Io&yOt~1!%x6{#;P@Es;>0=mwN- zVeQihCGB;c`T>(4kfhoW((JU4#XUashr^?qId3_+16=s{)j1tWn~og32h2dmQr>!F$Xc zG}L00r~as85I{Z-mX+Q88#Ef~oszbzrYq)f>`8;y=+B66)P$1MW(pe`KFF%S86kWB z)U>c;!)vN@A=^_oePh2RtCwh;nA^L_S&M+^=7QyB6&&VnhS2Gb;dhuMCFZ=)`Ev=? zbDCQ#~Ahqsp656>@vcvdR0TbD=ke>_X%!#OeGoC&*3f_7R5g|9^#{y7JCM;U za1igb$%JNK|4XaisPx0To$b?%+J!hpT$l$VjKa{WUXg z9q88skga8`VjxUb%i2o?>swotwdwF5mATrzLFx_xNy53eepD}K99x28Lqayam{za8 zSQFjgBW%Y&t}0=pNBrxXsafzP4D9vAi!z$sVEWHh4@>IaKlkpl4-{$S78ZIfZtc#j z`!*wel2;_CxW!a)%U`_8R2qaG4VYWMF;UPo7KK_9b3043M+$VkRiwHkbtea`j8P{P zOCY(E(!CbbEagOS-aLD0%t?e!@BUrTqK^5Vq$GdJ3?!SS`$o-Rvqp!7PO#b`jekEE z&p3D%nv|#t?3p|ztUIyc^I6*VO8j~d4M{Hq$N__x)_4>eC@C%)AE^BPjm-AlonC*g zsmEENQp94vxCGfq*7f!ln6g-iwI4=F4ync3omR~iUP5xdVwFYicQ3oFOE8}dl>fWBcwU$tO z)4=wp4@j)>^RyNdLq5jTF6^$VDJ`#-)O}%3u6-(wYDEpTy~KQ+jXm+g`}D|PGE>-e zLx9CQF#<_`-W+m0LCauym{O9Qc)px!+@Z`_iQveDhavw z8PaP|afxFy0|#xeb*^&{#3EiXT`D|VaJkaEV+K7cE55}$0~BOV;nn-SQYFTCec@s9 zHtP?vPab&4zcsy&1TjE_|cL zX;`XWKch&=CAL-YsH#i}^*IFF1~GD;1{BMu_xVN7cfngdCdbrSW2&xIO$Y_nC2%!7 zE;va+;HLl86YVIf8<=>;RxJ3Wa(liS(j#NKCCaL`;NZDkd~Iijba!qeerHodp-y0e z-_Dm)>o2A+-Gq(DC0(x6E9pjf*Pf4iW){)F0SO%xE!RuY@^YAo4$?&|*5ocfC>VTo z#T9Ru7=$iN^ZzwUhIy=cs@PGdis-$|jb2+T_mVegYD`Jzj4#46evP+E4gYgXlg{Yh zX!&BQVbqd_cA#0HiFOb=?MprQGS|W_#nb#|=bAdi;^b*;es}d=&0&n9p=>72J^rzH zOenJZu`Nqwlta~dZN5g*u(@C6Z9d5N z*QfI?F-zu4%+kG_*!2(eGr#;1(Ujrjw?L8=QkfJ6x}<8@^NrwM(t9akfSVvn#*!{`z^w%-UZ` zY4_{;)rSv`Eyaf;PIj_&euwh>^$#%J5*+VYfL52MPcnh7DOC#?y?B#1giq&pQ@R;c zfjO~DsAHU72a9`)cUh~gRg>M`#2@PI_T|fw`V7A(v8yyy^4m_kV2~`b+IP_)Z}HZ; zLk4RN#6N9F%=PxRtVdsa1>z!_VaJl%gc8N(Y!A)kpQ9E#WDy8}suT0*pr;+8N zdmmJ!h_D@9-z9vE%AW%D;{K=Bq8e`y>M-`$yPYLW!hP#WzSt1zvcS;MUXJT>lfo=V z5evWVCSMO&ErjEMIN_q*DJgsJ*|+<+dl+C`*1cS)HnHGA*x-r z(=B`Du-Dopt2HllpK0ohUT*yORc`nC#}&%-mJRNVmExe!Mo~=ddW8w{E`dA?*qQdd z(b1F(qEh|0I@K=f82{vD{GQHzH6dW#hUv> zh~|CIV%1Bd8T_fTQJ47B-YQh@QKNn>pExFch_SCR*2QcYORJw%nXl=P zN*YoPxv+S$;8&SlmsEHlGB?W)UIVT59X^Z!oXllc$OCjb^1R_CvX|4Bbr0>)=}X`? zQw_&V0SW)`(s}6}UbR>+l!u#3;K+YeCBgAQkhGl{kQdd!s&Ay1dl#S#3rfAyn8`-U zz0KEm3rcOR@>*>x+1=haR$7}i!(}x)p<48@e2P@$3jHrm-o&=3GIHcX%6R%5cQ?ep zwMOTTm#6%kkZPpL*>H1>UzB2u_~}PyFzw)d+ssr4_^$}v(PfUF<`-qFHT9FR40$|D zl%LbW_~fSx<4h*m!-=bo&K9gr__{IOL7orB3JYQXwvfcFL7`Z*1Q9EP6+EnU7d%XR z^zlaVo4|9A1`qQ;Uqre~8mpnv{a!6phEJATy^+j9<`nP6`YiU?p3ql)tJYQ`KGf=8 z0pZQK)l~Z;WpXX4ZvX581h5&E0R3>(V^lu6n!BuTz^}moBm09_$g$xoRI@Hhyz54I zUB+n(lhvqIyoXXUIarPS=>|K$3dO`PB}1p7-t)Kx%-~k=Z)U_FnGah$JT_z*6FkH)C5)6Ee-Ta&2+dA z4RZC@KTLL56^KCl_A6AXnHl6G6hd_1i~-fo=C8>>r@V~8OL(;-Hhy&U^Z`CS(P zxbHNH^iU}LSU-WcX1L%R$+_1WV$s+fC0Wz)h+OsHgxaxpg40ak^%9!5vzyBy^bmJe&3-dg)4b+qE6KucpbRvv2K0e_$xgKswpXSS}wi zqf`0ag|%;2+pP~C)CMcWW@P94k%hR?TrcF(uL#G$r2E%bS6ekA>MBN zlIB$XQgXDhPZ-q&!)Dk`)rA7E(~|z}Dfe8Vx|&?T0g|D2D7G`>#wXp1*0}WbgV~L6 z)S;gZO2K*vZxx%^N={1=ulHfbcy2) zo`%e7q3o;s675xBoKcS+VKG#bQ>M4@8}*9(WD6%}$Hs(3*G@|5`;2?JWMz-UwsRE- zC(ACXJGq4+G7BGMs*w!t+`lrhUMUMOXp}n^e&>u`ZM+wKjp)%MFwcwTGfuGA!OQTr zUIxsmzAY*Q5|}#wnEZF-d2w-@SHB8S?PU|D;-*{9F%d0W+Yfu&K)Ai501fNimhOn&{XwV{{1KBsaMKcA7b5mQ@5y)9zpSdkYt- z!d91-hE^@Wc>QHQJ$Ym$k}iP!BC(iK>%VA<9y}=|Is72O7RT!gzHi9+OGBF6T zp@M&QfN`KDSLGbTvKvNo@faY4uZ13hiTY8pFlLf1s4?M3bDY!AyFlX(u*D~VbcI*% zyfAfvhMno#fAFYQbb7gorDm`jKm9a$3atEevXmlz{+;myoY5N~#oW9-csPT`DP{5M zCqZ{%_M@PjU%6)Yz8>$`x+QfEpcFxQ?G9uI$zII_58O_W)zKa=2@l}PQM%2e6v=P1 zfx-G&$4~>WpVf~9Ug8@N?2Uk|eQsNHb>}(j=;?D}>8#ww+SsN$n~iW(kZ_u|L;31NE%-=TO1c+Rej*@u6RQcml=)SV|7jjNTtvq^vv`*>flDH zwZL74O;rL)dRD1;6h7y-J9Ox2>@lv#DXtiLIe~5|3bmhM)i5dZX?s`TFccDe%yzZv z;S6<_awX0nF>PDre;SEAi+M{-At|+sEz9HiK)Wk2ojV5d27bw(nZiAx%{m0+7Id#k z*d-VVq%p9ucU`0Hk2hl~-$zcox8bXmuQd8Z9EG{ECrjdF1Xh0RGS%j;*I~&tzY~9g zw-rZfGP3OXgN~vG9opQ@}RNocFOvs!dWAXYnYzkEv|fIgC4XjNcY>0N~FB><{)l+~>Ixu2U` z>9~vYez!e&bB7)tb>lYIbtr!-g`e9ac0Xwcuo856PBMG=zbisS(L%PQnm!+s7q4PA z!Tl?f>}PL6$Fq`lE-&QpjGB%v)urmEgG2wYECd3&*lf+E<-lt+c51yANlFfIZZ?k6 z^)<_Syy=@(9CL599kfUQ2rYF)Ut>Dl2x35-PIUx4dFFRIciShFOG=gcv9?YYr@(5)&pSH(DaC35_c|J$}5*?Jo12 zaQ3=77^`bmM)ag1E`@s}U*+|>czAajt;1HMnUI%U8D9;bHT;WD8VCIUZyXxf=FIx!eBqK@$^BgIqfHaGzTuSz4g9Sthx9P z&$S1;SB6Fu=Y2uC*;PZcbO#S8dA_Q}n{V1X-7YK=qAW7Ug83YI7)$N~<-BGcwyYE% zBC{)j<@cVfc69gdpNAiwIKVQ32fC?wLde@Upzv4c85G}r34NjN=Iixgy{Ux{5})OL zeJS0z7r#DJFc$Iq&vRWH3~f7_ATTpffmu15vPWfxwJOdNJCJAE>MjkCO>XHIn~&$w73mf)HSWqK%KlFUiMCIQm&2CMK?0S`(}H zQkq%*=6i8PV0{1#CLH^ws!si=S=kleoxDwG(H8Bw?`OZ>+;;UYN?S29al9~Y^+IC5 zUghsr?_=|8^RBLIjB8>+PNv=28Q<9HzM&wBk+40bN6RZRza+9E~ZrQcw|}zm^nHfEhNs1zgcdN!l_@We06jfnIN|ZJ1vQP5qAi0u}tlE zQy`nT!K=%g+{x1~*IU^ozEveX-W|>648uF03p;+?1#)zP{T_@qPzS*0Wnb3#(}UmM zACtW*)8f*YGj3wGcEM5NQDLsjjqY5Nlvu6TIE2n>{S{pcBZ*E_RRn6ESYQ0vzi6#+ zm4CHqO4OFfzMlx@w+D0fUQ4`#xGGfmMoX2I6n4T&s`K7=#`L~p>jiu^v(0X0C2Drc zt3$CP)M&n&n!no#>%h$s!tmb24kv7WNW5F=qM~he9uPgym<0C`%LcSa=kAKVTH|T? zCQfJbk7n~K`Pv_=I);%RPR1y4pUINy54&f2B8OWS#zYbV^TiK=2+-{nt>M65R1|dL zaS!GGc}^%G_vv`Cvq$kRg&U98g6p(nOtDbsGzSyC$e)ZEY=mof-Y8P{*q%W23GeQn zd$&jX9=GTt@ULc}g)tMV=z)330_nxPTC`S{6DW08RGxsNVIc!rBieIP6_IYywg<-w zmnN!y@~Vscvx@9%Zf;HoC7SQY$Lezi_zpi(d_5^%Kw3VDJkLjmEKO6`i7&T6KmW+G z)=dY=@5$3&+h>y7eHZ_xENk#g)!M1Z7i@2tID|^wXJP4^-ozaF_qd zHC1ato$Wl__b6NgzPQa!6t34|1CqDEPs~Z#Q%o`Mj zQpi39ECt^Ud{<7MFwW$(FLP5Y5-{hNqp=qUlO_wS4htdd0X{M$)g#M)WE#~eoCh<8a@DA0|0@?qW%pg)f9Kl& zQEA7F2QobXfuI2xdC-Dz>5A>8zw>hQM|XiIoQQKMoIfq; zau^uOyBIeDdTlY%@^j8-0Ofo(20H5ti(cz8W|l!nSIoDygw2(lklnvSR&7LvMa^C2 z2sH5d;Pc&w1*;Jb^J_mM)c@)h!A=8=0)m3U7aab3ho^2VAL{4YPshEpn8Mh8j0XM< zi_K~I6MD@5_|Y%u;Ir$qaw`wUFL<-Ex_o_F(n?6|ePoML1r`5A%kV3U7wdzu3E4j9 zbNJ9>Rj-|K&euD<0RgA3)OXW2+uvn2-nW@2lw@j4&|N4S?7+U(NQ|GgxKgvNS|QP6 zl7LPG+TNp8&Ivnff0uJwzq~qUa*I7l(#tfZ?ZlrlNYU1_k~E!bPCe_c-z>8lcJ#TI z>D%HVIcSCHKEJ8#(dEkzI!XFmIR6+%7m>A*y}G_T&dUVJ6q|mveY0I|CZn)G1+%Q* z0qCSu%Z zck(6LVX1}*DM~vn4T$oqIGqO}s%e32+YM*XK+Y4v^KunF%o6JPg#ynx3Oaz#aE3iz z)3~Z|#O1KM*8`(y64(B>9M0!OXxT!NcGtTj748wBOtTeT7Z?CqJA5FO_DN#frNqK}WMBZl>_36JxJK$)MCImJL#C#*oXoTp91|S$GcNyo z!z}3g)hAGP@?sRZZ^?L_;ze>`jBMkw*vb_k-pupz94{DgY=}}|f4u1o$TBT=FrngF||SaZdnu&cFP|2%ceHg6PaaTf}WqnI4h zQJ92I^cw+fl8fv(Tn#3m!bfyqIQt}F_oy}ZSts<#y%i}1p1HD3i|^!YQfAw6p!tUI zB$OwYL*fzmbI^>1+4|hUZe?`)LgDtfjB#n`Bi*XU!9Ca~HRL62qN*g|vPA`i+k3bfR z3;=uSQs|vXv!-#l7V$qSZ)e@X#OdC!%GQu;y-s^JM#q`nLRV}qI>Hv{I#mRKwXFvd zpMP{V08<^_d9TUdZZ0>dqXTpHY@A(nA%C7(ytB6Q+a?3Yo^$R{JI#546F+apvaJaP z$btGGNfFx*%|DrV7acEfSZ(hHOMMGpcb20974aHb86)?>^RyOI=r@~L`v`sV)}y3j zstV<&W_g-{{uSxbw4|C3Mm68s_i0v<3G@4}Bst;Qq~H*@(uxQ_Sc&DJJ26NQUf0n_ zd;9%=RGXEb#1<1LR3(RuHG#_QYmG;PZ+X)GX`eyDI-bHM_lp)zT2c6|tQBc>JF#T# zcU8?nQx^wRQh24@mC3dGR6ZNfDZHO0mR#QEAjhcpi%~r>?a0C?E^YKWZ9c z3a17J8+cV`olj}`9i^G|J@ zKmu^sdAC6cQ@q1%-+-OrNBY32f7gRUxv+#aJ8Vh(!Lr^@m-9iH^2b$Lil2!cTnT71 z9tC-A^&$pQo$>wo?fMJm-+ntri)Ow0JNkDl@^Qr*6U1!SDMxbbgXAj*m?8T00G*{a z)lmSWSvyk~dE$dwl^p8ka#+K#089?->>(*)f%`NLt+wpp2ABWgW(l1*D~m}{+7JNg zW-3T)-Xwfw8XPn0IhB4;P-+W+X)>wS;JTcKUG`tUY^eBZI?Cj19tY=~ZUa6^ej}0# z@iA!ZXw7`rbC<@;btt~|=d&H0Q1Pbdb_*{_IH^bcreMRN3}?PoY59q&Ym(bhKW;7T z8rk7QnPgi;(IG7^&Pn_`*zBErg-#@xS={E3#uNtqqJzo)lPUwk-_XKWEa$r|kK(sl zpeNXP-_f_)$x^?Mah8iig1Y+is!sc(PZqa%So0spy8ATOjc=C+qQmx$V6k#L_t|oJ z6Kusw>s3V%Qm3{`#zGg@0*ET$`wt162`LeBgKP=;G$eY)-={3QK4BdX(SkA}4&$=e z(nombL@)2r-QC_GoRvv7Q2I^x{_Rn+-1iD=u)xb$roYd(?(<4@F}CDJR48U0wxVug zHV&5BXr_PLlBgH_fkKlj3hLiPfUnsV{V=2f>)F+6z ztfphv@VQTByWejE35=Y3fT#2$YFusncxAIiUcj?l^U7U*NuDBs(^7!U?GU2K%cA3D zakue0<^E)1UMGf|fp0za_eB~~`DSm}7BBUntv&D^(U*O34Mk+Hyu$#!VF2;(PSjYY z^;GcsdeU)P#yY=m${Um1kX|2pCu#7tLHdN&^s`NQ(SsZBRskzfKv#xo6SCX#@a4em znX3yaCan<6>Fc2yS;xtybG7>dBmO8V}5ZD_0lOaE>~KJVfN*#M_rD(KBd<@p!T zALeS8gmt{S;NLV9Mr!Y42Q<&do$4g``~R}D>mQf!1N*%Mt~0u8uHmtGYT_Tp7r2te zGJD6tqy8CpxN7(KX2ASDc|9@lI}J5A8U24;OvH>n8fH3_7cyq1wqX!qdmhE~s!o%1<;B{sPj|+)%T>`W0|Q zO#B>({pRb=~Yd-&b6L6^}7PLV*I@o{PM9b0P$VvE|5OJ^tk`=6eUyJm^`j@LoN z7!5{FtJo;DB3vTo@2V`d#u)<3r9rZvAC?M?GfmV#-fduAwvT^9(;eMj$y6!4 z_hwk|c~05BvU?odh1@q~{PZuh;BMn6Tr#YvhEjU6i-2QtDmkw+Z>lM8wI^NBTP(_@ z1^|lodrhXHj(m=zWX&y}$(b#$UfJc6Yu!l|BDk)0+Kn(qIGaP!Msu)uYwSn$r%@0;?ug?5 ziOMdHp+O1Wo@EWrtFvuJf_>H)1#-A-#5*L8RAP|M=kpE4&?5Bbtq5sk2%A52sHm>orJDN^X4H4|dT3_b15xh!E4!d}*9?wysV z(E{%y_ab7?T_z^S9wL_d0IseYEIP8%g{oA40AG!&2NvT zZ(>V!{1}Ctnh17X`E0d){~0aQKmzj7YaR{%*Odd?Nl)w7CwQwbqR(Ci2K1)yleW5T zc!_i$d4#9iFfgtR*6Pm>6TkoA4!0W>I;dp+9k!68%H+p5lZ0u`w~=Thg)Qb-9yp#k zC5#pvj|p&HP0LP(Aj$)o{1(hwfx!N2nfrN5X=~Z}e`k6|+$W{81I2{?xMXJDVI9yZ zZW0Szzq@4v*#~}4H+cW_B%BC)uOb_mMIdl0e#nwJHT6czRcT$kLsx$k>+asXva4cc zU!PRlvij(+Z#%VL80$qh5c~Lwn{83AWl2}NJC}>-_ruz9)`q}ayYXXVbm+6sfYT+_ zY&S2?23fjZK>$Jl_I0i6zo{hP7>`UStPVYSk?Bbp>bmo(zkhy(g5iDWOjqdffcKVF z==A))kvLs9feCTtH=JGcsqIEpL9GbubNE#JLX(HW}-K~BtPYzBUk?B75214&_-`(&>wonv<*=XlTn{# zi7u4en2sGGV65j1>|NGx&wfSpuO1X1t6$n+mAz!D*g??NnwO)eaX(#Zn;6}ueRxQh zng2p87D3M+ugWF%^=N0xzfzH{K+k4|d(8jtgp)~O#*S{y8eYuK(Nuwbp4S#rAnm%? z+~DHUe6VadfHz!qc+#t{N9~iP@@gEOaiY-$L>Hv9^rQ#)*ojuQnGlz@uiSuF0XX zkWf4#h2qUjrDjUDB-Smq=tofS1?V&qZ2n#K)H~t^}7MUPm_Gx6BP+ z3ILSusN|vNo1uZx_JN&ri}m=&j{lU@0}d%7CO{#UbeZUO4D$44Mr@1Py=_lF>IJzNmj|ea2!lormGIq%9iM08Wd1UO6KU$9{825wrS=w4uXd zuDq|;g+ZaP{NA7KseWsbu0K*14?5463}30?p5IyDJv0Qlr#n>?nxm%8d|LME1LuYx zr;#}mL1C7$tkK3P4hgWi`?~l5!2uBZu!}OkULY{ZW93@f?&1+Lv_XsGc<6-`$fHXr zV*f?1+ISW_$>!mQ0@FurFwM+bD;;#5#Q6yh&@!@upR5pn!5qvWhHSTfX!ulHCT03R zYHLXHy5j%yraaHL>m%pim6C^%E{!@3dr)kRX5M!~#C3XQFy%?HK*Dm0U?ZLv@g6>D zE9Lz)wN0vpigDQp`ZID@7Fawv$jhi9){#> zuOxz$;9aLsq!qHW!ku-$t`$8o61r*(b#y&utjXkJJ0p34c;+R!jGw;P^DdQYXqYN4 z?d2hFj#L=b!ff`!KV*K|s-GQIg09WCCc@^LAy(A6`UGIX-Z z>xY1HuHRxX6 zk+}-civc_%J!$rX8wkY|qpmlTS@0<35ixg`6ChnHI!vu@|NLf1DW}J$qgKNw_KmJy zX>vi3ctv%1%z^3vK1px-8$Fw8x!EO+Bv;%J;`+*&3s0T%!N8>coOiH`M^QhlUML-6TT@;7`uZT-z_bue(r&C* z2?MyO*MdV6-aUdAew)5^+LWRd`tBN)mZQ{%Ig5RT1LjmnL#S)}Q>4-&N3(`KJ8lI5bv~k+_?a~BWBVy^_fMN`PgMPZH`QD-- z<>BS9puSljMw*hHS93bh6=!SggH@OaK^M@1rmSjD3XQhEOEny^8xaFAZr{-p5U>T%D?=2IDteFwPhFfL) zCHlgSv$2j!-@#4%Jm;KLuZ{R4p_b1^&E2+#`Y%CK_5H3tFLx-t{b61u3`rZ_D%d() z5{No!iOI9VF`;Apt~)N8uzB(F1}3%#qr?xocvc`o)e0}72=-_7-m70$Y1R(qLuMB$ z30o!-vL11MjZO`tc2VR0b>qFqPBFJcin4ipEZSq5z5ZSMIl*sOlT6T@jE&7V2!a-hi(| z{>){LUv95_=dj^_@~B$#phj-YQ5&_zn>pN>>WikCR95shLG7&kru0NQ)@NxZN0|nj z&ghNnaOH6YsD_t*;*hs2!hbi7u^4AZ7r`VppOCIq9Ufk&qU<&;*z}0aHKkwD3G}Ls zDr=Z!fsri+8P5a}Z7%=v*EvOoZ93kkPAa@Su#yXQkAw|Q(LEfPE z!(7b2`+`cTt7ZoCYMm{_N4G2PS(l#R+Nq~#PPJ&t-k!})q@&99gY$bW=PFpf{Mu7) zyWm=(7JJf5XNo!XaZ5SRdsX)ZB#!Dvyr@4Y_=xe4`M7#rp7#jnwuNj>Ov_{(C=u4L zZh>dphP13u-qW)`pWbzoeMA2sgy4f+m+gi4%n2U3gGFx9L@ih9$veo(N3Yzf8)Qp= zR%-8S&Wvl`xoF0Bet6E~ zLj#FinIRplS1KrDC7igBsF+TWgnCKl^%@%-V zG?H+(N6w7{+vy78HeklSl2$dHaL!cZV$T(6ftu{$(SY4XbfOEij7D&hp!mXGh#bz2 zv)g+SVAK&faq{y8_IlAkEPdO+p=S8SwpjiH-?0yLt;S;#f*#QUsX%Rv@u35=ST^%V z>8`_@LH+$lsLL+ddIvwUccg~?P^YB z$PMB3&f~ZSYdUp-BxJFb-7=5+|Pk2Kxf z_|V+*7_St+va5@Lhlf9nz+rV7a`M_{nG~(t9HiTzD=BT8m;Ek3^%I|LaL;?b(~6m? zordo0)X@cHfsA7i8|Lfo-#{WDuCHNrI5mB=Tj*H*gqi4d@kk&RzFBV1`;PYx!%Cn3 z`R*WQ?zFV+9zuVcR|zt!bK&(jGml9$$b~nQ@2*{gPuNT)Eh*>BQK)PFj(aXgl6HoP zuF8R;P;;zn1*?nJ(BxIV`R7;OJtA4w;f>RVb)26@aVU+iI^qHnCzggc zBGh56&teD~a?tSW<+P>#lvZ3=Hp+a$b7lv%a=vq#8EKq;cl}V_r%zBlt@HF~Ws-4` z_tRvq1WBZMJRu5?Qr80$ItipHbgI@0I`Hcq!zyT(kNGZ!)*+HacV;Zv3%jf9jXy@%@J!F;Xu?BbdUZ>@wQM_f zfC2;dDq1hKYpb+;1S>M&{iYfO^TOY@k&|S93>}I`-kjrb00<$r@Uyui!w=KzT-tQ09XxBR7e4?{cpwzndIxqdRZS zZyXnc`X${czfmk*hPymERRb2t`~~^IM`rU{6Qd(2Z;iuEh&3;x7ZWBEYilniem2#4 z49cd3_D<4-eU8Az-G5H$mfET>weaW5O-*e34wC6KZTWa)%io09xZiB0E;eE<6IjI#XCkWND@w{CI_?hDR(4vd5s%# zmpiMsm}YIXX>T_CAqb?X^J>7-HSqUr3Ag*^YEygOMgMA_anK_Dsjzm#d3!jNfT}n; z2@CT0yF$o^<}O{~NWUZnk*VWSRGPgoC}|4FAwhJfSlyYw_ZD=Yq4Q6=Ap`f}!> zCR{B-U%&LyS!RQrn-jG^tu>B)M5H&E*IVUB_ES>{NEh2sXqt<+jPm7GT`k17EgkC8 z(1Rd1-g{IEI^j=GizQ_Rv%xM-_|+!I^uW-Qjyi8Kt9V`m8<;E(l-|?oVVX63==ca# zqZBzK3i*&AT`WSECfvF3@Aj#?qP3}Lu|TYI3=5}yP1y`OR(go#^K!)4J|oJRFeD3n z2(^Oa(p}6m4Pmu;w49$f6BqY#-L;?&X9`hI!j_k>_GR$A>@(lJM=woHGm4_}45>ox zsJS?Ut5~-Z5MtT5`!>>7f6dUV<`}fhR5c)w?opa9PBD2+8W$|o`a@DXCUv?h^o80n zIeCfBV#QTooM-3x!he14!xYJW7ewWYt|_A{YZQ63E}W;HP%kTN%>q)rD>WJIBY-np>@2yTRDN& zG>g5ytkixHa@U!Pxkb4wj<_j4ABz@oFu{9=`tT1hr}5{#eNtiNP$&7nzF-2cM-J$s zb@D%|Q5L-@z@d?=tcpcwH2TBR3gT6k^scZ!04i-u&P}UP3A6~?B|J-M1v(Bx&WrG=CNN#$xy}q0 z+esprs68bOk0KJLGgoF`$L(RAo8O=eVt&YwFKaO)X$1z z3lsKb&u@cHj(fR{mG{px+dcGYFGh2@5zA_+rkV|3XK<_q?)S4MUQlN;Xm&^7t_LcY zO<2kw%qR#nH-fB_n(dwz`+l`+vjgIsGN2IX6_$^A2@3bpmQ{|n zqVO^Sx67-F#G5|rl&kzDXB^3LLd_i!!h%V@$TWeO`8ldGBTM4_M3aPZ$Vc7Hzf)@G zt7KoKB_c9w+)tRR#!BWP-pqski5lWf(C|BxU`SZiOum6+X8p6$3m3$|-PQM|%QE%N zkv&}^bLC(joM>>TZRJpxj}JXJR*tjD(IhaW-(Fpt z->o@Pu^K&u6_$IBbTygWHeApuWgNnfsJ95!@z-{9&v~(Ne*`&bCtAhBoX9mv&HqQ!Tlh8Azw!Tg1EKZ!NF&^ebWCzIlA}RVHefUo14fL&#_r$w{J!7sAF#(xywCew=el06 z*VEWIt$Z_BgH*>O5;14fS2}T?xbXUcPH|`f{wB3MIsApZ_jtSBdc67S5lA{7QXM<_ zEofCp4xHjwBZv3nKjfl!S=f9R?wJaMB^y;97?kn$qEWj-M{WTaJEv zhV`4F8tg3vPMbGbNv+4E6e4jdU zyK{ca$rmPwlx*cyoy}v2LAQSs?2{MzGheP=+FsYRtTl1=k~`uN| zCoJi_*=ypAJY9OO%S1#aAsp(m4wnm`V+rOqBoN*6TOTd zpMmc#!{3E-kw4ij0HD904GC>v-0f$x;rd;^6GcUCTcSAUtDCl=Bb+CtZ$caAa2cV6 zftOJn7d_U|m{x%$RX)E&OR8_l9dv=$rcOt4nHv zk{f$(G%Yt&>^V5mo}Ig@Zq3}#~i}FQX}K# z{&!nPy{PlI+injEo4vS)r1303l;cCSy;r!_Uy`JCBsV6dow(+>MN-H?qeTUQR9C4? zCkqw<&ndXv&!B!j^`^6~<)}F251_@b_^Y*HZ$_3ig5aVpKVy&M_eB0(c$$GNczrtg zJsAI%wNd&aw@uAkC(EZk)gvBA7V?*5&=Q_32LI%#uEn}4w}tH;7L|<0N$lRO zez%x$z?DOvmt7Z>6c>*R8`bakaS6>6&NcLEwt%+H38GXs&#@;6ve-s%zve~qpF2Lr4UQU<+&i7nc)$A==Y#bD5<7Ej3?DG5!yy7Ys{6_&Wc&&N zVmu*Q7r8^2wpv&@i9@fiUfsI%!h0B&fUbt+MzaoHJ}=U@Pv1rD!O?@JJKF%6SL&ew zq-0;hrf>>8A5=wN%|Y>=%Nga-uH=1MJqYEhQiws@&tK;B_dSW?Vsq<&11W1UPIZG?~&4$uk|aRA||1z!Ec`H+IGIuX!BR;)#F-OFhuUgOnYvs#Zs;@1$3q=+R zh|?5>45hW*AA4C&doof}t>>FVz$IaL^Tr#!Z|zgtXc+C=q0B?6YS3xjLOh})Gyr*o zh_0!r*VIR)zDQiX#n+QHiN!`5`h9(Q=^ zZurOWK}20NpgD4rjjCS|99wNNv;w{D_ZCPOmX}>fcqjbNl?K=7WxbD4iRyQO^L#Y56Hd3Od2LLS zgN!zr0#yrE#|G3StB9JYr}1BM76rUKvZARLs?(9^)FJ2CbBRZV)` z_Ph}_SqtY8vwp@OG`Vv94htJ5UTgc&L|n#Fj{25crr26nxW60$I_%lw2TGIjs?6N29c*Fc@e_QRvMPoLyfm$?58i&@5h z3^s2|uh=GGpJ(%5uo|Hjs?{3GYU>5G}BjXfd;LbL_x|XK8iS@R(RhgEr z|LN4aH+R#kZ*+dICj`6$10kraU%`so=Xx_fB;t8U!+w z9_>NDW2H|g%k48z3(%!w)DQqkyFUSFK#a-a(Q)efOS5fL`PeQY#c`tzk*+r?I$VfB z`The$l;n|NXRy(FR!^FHbOH@liAxPn-B?LBzgm7PJF3V4MBHnp5rSmng)RT1bI-d3 z9MIK6B>5W3JkbKSb8(%vyLB+i{S{w#5-}+LAKhoZB@CiPa;U8OSa)F`O6e7&br1#4 z+;mF`p4%tIP6O0$;nr~k#@Y84F9GsxsSaE<(01?{c`KTpVqs6?-sp+olZp#>0Glsb z_U|jj0ZNs@F9K)M?kVS`pw)#It5Ir04gzmz8}JUeHkWi_mBY6Gr_P)#2%;iU#sAT* zu;>3jd8pCP@>zIV3x!k|hOe24L!PVTonLkz6SmFsb=#%j(tT!fX_LDf03g`qRXcG7 zSG2%x5)h}VqJik7G11zA(f9bWU+$&s0W#wIN^AW8j>6V=Z5KP(RIPp~wvF+3xCN~K zz7mL#H9c^?5Fn2pssIB4>-P}^b5M`$aLii5EDO%nER+yMnZ+3l1S6X!8bg&eb8<`0&C;P7MwmQvfPCF2+nGQ7R!v}@(Q9QtZ4w2VqbS3AgKIU;H2UXQ zZa_8lZd^a1UGk-uAO(;`UBKxJ)~fkZp=5&4z0>Od=;Wtmk!?aQ_^Y9^LFMk8M5{lW z`wEB68$P}HBKxX$URLb9uT3i)8rwCWZT5S*@TOkr9D5qYMwW`++3*_MAs75xjy$Lh zada|yuG&f5%Od4{Y_CoKs0j*$`3YQc$J({J&CW}I!I4&wna{a>abE1L&ounX5|ZNG zO5eg>h~Q7ZOWgm6n6P3u?3a-r+SrM! zKqe>5<>B+PwGFrVS&Ua%O3KOmipVjK@}n<5(KU7G8nm&*y*nRudEHblmHtb|^e;Q; zle+D9vaWtetKo~9s`>=OmXx8-Kiu*~W;5Q=@g^GuDgo#WM%(jTKM=eAcMMVTaYK_; zPgB!_^E_{r|LCkAnT~pS9~@V>j+f3fWy*U)YW@B3)zB^;ft&heNP4o9k--{Tqx&q> zR}V8;`yT1IM^#)1gm(n%MiHpZteVp!e7PnC<>FUhBi_!%x$)p|hG%m5$3Ezn06kT8;VqPj>}wE^ zK5Fk+*x`x$MIUbdc;ugxO7|rwVQL?_67_FdE;n%|`dG5wb`Z{p*~@P1Ov;)h?h(BA z_m)P!ku>1FcHHB;d|Faq>yIy+oxjoLtSl7GPGg5cC-*86DFNyHO4MN^3qS!I3CYhC`v+qdX5v*HDJ=h~IF zjPD=)M<@LV*5Q5VN&BL_K&iEo9t>tRXPsF4kM4cgR@ByE|LH%wPTLmT;WoRJIuj!L z?I|M0E&r9lMjY+;@9qifgz`gAwf2BUGydKd&*e!&A)VO4W-|Enbs4rz<55Kj%Lvh9 z{=^#4oD`$(H#I~OsGCVY5$C{Tqg763{;VqBZ3MB3l| z%?VG~H`{C;uK~h_d8xi6vR7p`Ce!Ho29GWOL*v!8% zUUrJ#G_bm@&m%EBh~{ghL%B&Es#f-|@;gY_hVKEcA6yk~JhKsf&j<%uJ8iQ#rvE3^ zfu(c^FB#g*BhdHqpvIAXMfVg!v)aXQant<34VLihz1^M`i1cd7;H#=dxKWLkey|p+aE$?l&Fm?icl}&>uYDwFbfm0qOT5_) zy)I=RZ3obPtrs}{qcaaFG4^WVU2&JQ2`Gn+lox_B!&fAg7W6jXQ#bE6SgsuAx$1V- z!rry5(C3(q)%r>z2H9~`$(sF*(@76kp4QPIpco3=tlomw>PEp}w+s?~SC zxutZgGlaH+f4JF(0N849?*Nnih#WKqwEx_=)+T(yjvr~90$aAd^c_)?ooM55k)9m5 z_D%(b9kg_8ny~s|T(h!zDH(2aVS+6=OvC-x2>Ut``VTgu%F4mQ5$Uu}<8V9;KANjj z@Cj?I9yhE5yOsX*vs0mO)#a7b5|nRG8*1;$z)kRfNtdfw5fXx#!Lx%&oAIba6vxY| zxl+v^K6(KU*qyPsa0@K{nKHXN&feTxbWO#=$t2+jXaVUQcrp!}KRr0{ydicld`;m% zW=h*1+Ek@H&mRdnoy-z@z0(7u_On}YuD>FlF9dtqY3o%#kjREBJw>V|W!MOwvG99q zmmBl%&DHvNf`a1J&zuXS(n?5?K`RYLW#|pt?Ic_<;(@MWgbo-I4T*BTu0w_C2}>R? zHBd{2y|AHwV13nyo0Yvb6cjr!UmTaybl1t7?;glUA+j=ue+>*DO0weyxFOgi6ow zWKLol{7=&p>!fiuO1Yipcq%0G=|JOla?6-(NSSEblKnKlSyE{4;~VuGkzX$Kb)0&+ zCcJr_sN3jxstH@LTQK%ORk{gC|FE!JIfYOv)+ILL89iNUphCfnPaOp$PNTS0j+i76 zxBVMVv$nKJ&^p0Eh5%L`<)Q44eT^&iJX8sN8P=BgZ&u+ivfsc{y)pCQ;uEfK)DW3z z3qbEW$ZYrJ3{MJ5QKb8c%V)juzHBWu7^k?v1o_?BZ+9leUR_%B+jSkw*)L(#&h6X= zAqn6k`FNtxr49I?POE6NnhBqv9hg}VZaY3j3d$2KVq(hyV?xcHjabW-XhU-|_<}NU z6?8RR?-Ndea_&p)hB zKieHpH{ev^qj(mF-wPkIV<&Ga$dhY2n>>HiSJWD6<|enOCDK_fc7GIjmgBcv+jcX2 z5`VQ#+DMB31`!?QM*y(x*iGzb!@RtA91AeiUEGWt@zi1?zD+(5vc#AcYFaT%Hm@{q z8^NY-kX$p0=m(rT(dv1R`?)Ga9)22;N1945<^9TIp~~;KV4>0KpnO*)$siI^qW8Lj zyWl%{i^t907!5t?jP8MrH)e?LsDszDqdZ?+KZ{a;Vj>&slOapZ8f;qQKth5{#}(@y#>SdNyl=8W?W2-8 zNX`e}=_U@R$<+8!i625f3RQ7^D@UqG>6FuR$svV2EM>{Db!svnW5%PCx9|B+!jy4Sg~(9wuZmz8hM%P@c?)&5xk`)why=u47D;koW54@g}oekW-9aC_=WsJs`ZSu;c!7=onf~pr!N3gWD*u1 z$Q3UO^7i^2lWO(yLyh{IZO@e%pQT2D^kBcXWI||lTp(IrAnP*vd&$bVS%jEc6XM}$ z!LZ=W6KR86`?TEjn|jj=0VBC#nT{4d{>v`(|3E6Aho1b$P02wU$j6WLvJMt-M%elVSiYqA!M_djb-K`Gj}6V7sjs4riPLLOAej4p z4o={@EG6%jB(y|#!mne@@Jn3Zj79nSf>r(%Wl5cMaX{i*$+hqLw)yREKUWzk$jQj~ z0|`B=*YlXO5+4onucKR+)mR#;AfKjw=wRFBYar1!?F09T|M;GMR$VUNY%)~L`UILF zytbt|KxBoGE|@E`zN1B|a}otT69zU>cDS#t^fy2D-IsyXU?Ni667fO6a89&P?)v{IR3YsFemYx5`>e0=-@GpA8N=EuS z_Q`juLPu}Q3y<<>QJ%CE6#S9n_gz&04N`!gnu5BztfZ zr>|$du<#Tr_dU(hWT_$mDGbZH*^p*Bll-muc77pl=)_{z(HvlAd;qcwd#{DIOXaHy zJ2x_Y8`i7AYWXqmLKN#>loKx3Q63i4g%YU=jjdi6cbRVWzi+EbUb4^9TX~gT6mKhx z=pAjmdN{#NXe#Jt6-^{Ki7FmA{b5fNRoY7#3`M1iRP{deTurRYR&XT^Mt;>Cs48}H zM*sQUFZ$rHTdC^U)BDiZ+IvoSwItFi;1Tz~02x$G>xkbh!ydD$nHm8v*AAi|bo3>; za)d<6+@~#Mj<9mTopELnM)x%=2B#Srd++KQ(aQPwNIMxFB?+6I2fIE)o&AuQP!4{QzCv% z+XgC_5@|My=N^Sl7gsb(ce^v@pl?|2&XcT^VSnxmDV@+Wc}pj^URlg_)4vOOy>7&7 zG0fwMmu@tcQFz4gCa|XAfp5x~5*=6B0^gWJ)$h4x{Jai;nqKFOf!|0NitP@{0Lkc& zs=0kp!P4PsN-g&3ytnPnb0>FDS;SM% zZ+(4-OIrqsP*lmbS-HY2j5bON3{6d8*6fcHcGB(VH=9dJd_bEBF;l)tht{4qF&eK9 zGSPoEaN$o<=&x^myFL%b>~D?#yj|@sfaPd=(?yDo68EpsWj|7Cfmu$qPqQTYs1mY9 zCyrezne!!OCKLQcemj~yK4CD)l{dC0Po_Y%M9SqgaxA>_FNvjvgblCtX1rX-%&cDt zxIS87g^q%lH<;Ja#_P4OYfdGuK@!$f2jh>vHD9=;^m8*fI&BP#3&IN$@E-X43;pMv z`dfH{v!XS|u(_$GiDD)VmoGku2b45>$+;f9pE=1*&aT3-$vsv_wdi*?mMvp^B+>x~ zT;BQgeQYSTVJ~m_)qM%c?GR~EVi7;=>twEjO>I3~$mhFEn-$5PY_k4O*p(5;T0`E@ zskwoC8S_U+&^3#%ubZ zkop5%jor1lbYIYQc_T`dA%4YQ&ZvzdHN)&VVd!)BgPI7Oe5&VV_~p*K4b`=n(E^2C zM!t*7Iy1s`Uq$N8y*d7TOY0(B&^a;MKDZB(ffOxlDEig9&niIPL40dVe`-wL+bSIo z?GuSc4gLy61PC8mZHu(F#`eGz+8i-`1L-$(;#wBJ#o9I6J;*Dtq409}6MQ|ZAk7=+ zA^I>O7J?;t;N~vk%Bu&4=#aR$vPMtT9zT9)mcg>YMv3#4Y1E?&Bab&5d`)cvW9&1( zf7Yg~;XYOJbGoc>nazp`1VNJC@49JNPwO}}Po6$1Fmj(tL< zG`0JDz$@47^*iAzCT>NM1k_h|*bN)SahRouxxM_Zz=Oh>)2N5$+DHFLYrTjwtjPlV zy9d5H1h0jtR>tdjid^b@a{Xh6I{l%;A(YYew$Vn9BQZTT7i;@u*;wfyfFj;-_@lAG z_osTG+?Ti#jP~Ymm?OnH@B=I7BH^rayrQ?9=z3k-*^4wPWYd3Gh`Gyoa_>~^14kQ_ z>`Qc8={OTbvnIy87D2~+Z!n*POYKVWA85iX<{i=JgRs*+`(E=?;LF|q-tW}sJLF1H zudjio2uB+d;*aw(pugz`eFOwUetsg8X?y+y+hL^jNC(k-cf{px$fjM-xc2M%*eY?Y z{Sv&gjfFOD{HhYglFpgsf8^@HalrG|&+NcqU~#ZEieXoBy8b^pdjQa)6i1YVRJ8y) z?w>7am-Mg}u%!HEpS|9=rI$TUs50&(ABQH>TR|TVY`C-aa!N7H1x@Nd?$Bef4s@ zq$pkrbE!Xt=`I9|qVC>O6V119$^*AmqW9x}+O1@b zo}*^xBe;^T^5zqVq3|=-C?MV|W<8&Q^#Irr*3B_FY_utZG4Xg7trUML=?NfOj#)E}f$1#)EL;DU0D)d0{1nj-74EBZ#yq{WZw1HEI%> zi#NQPgW0o#?}H7Mq1DJ(1#;n(;yu61_8$VJj-`qCOI7NXF#&7kB9_(F5fNzeVan)b zL=6JhH;tzB<_(_Rpmm0`))N&T?qKVhTC>$HlIJzr)6!Wo8*)JpH8&6VjYWbg;nolo zefZ2xBe(jKaW`<4q@kKFg0FMFFB3bUrSnwx0&+;{XXOluo5)x<;hrW5d+m}tecyD;^MpFDgr4P{DuWd$=vfqj61g`_bHz#q$ZW|8h7cG*Z#W#Ad)mT5^ z%D1|nxXdZyW2{odtv^#TjF$ZilMK1y4~+avjtjq4*towq^%CjM^>?(q@uuSb%gBr3 zUKa%3l{Q_Kri}^Lqs^TzBXj3*o`!GLf@$pe{K-Gdxb0h$T7J7X7A6ucpQ>WiIv9M6 z#XQ|4ZKZU!J)K-d{joGHz~m^`f9fEHwkB8bW9DsVZ6J|ZTPowA1x=;Bz%JqJ#OM4{ zK1@s7Pk%wJ%RpIsLWn9~9{PjgOL}+SAC;v~*Pn%<^5DWRTL!`p`rXF$plYr;w`YyLeA40PYU%vxNyTInn=r^{y$f5AHc6tt%(b*6yLxuOxv~n2Z3j6 zGQtz#gY4z#Ycd$FM+Z)h_Pj94h>BD1LyLqHj4Tf%eBO?Yh=^6cP!_7(K2v!yC8Syv zN*KI%fOtD|=UxXcM{X(b2vz*@dqe0Sv&0Lh^Q(v@d*>+~^b{hCBZz zQ3J{lvid?Nd@y^Gs@Z+kMX^;($BdH2;SuW6?mx=kbn zqgFozm9#H@=fq+<5IEnZA|NiZ0Uc(_A!pd6Vxea*%587Ov=B1<^9hZ~@+|yIC& zQ7K&i(U}o7FNW~?u^(*2sLRTv0Ad2)@k-$+%hk4A<TbLSYi7)KJe*j-l8W^bkxA9w^jge-q`BF z5&qUAPkxc%EL?A2%IRaX&km29`KQiA-k`jlNihKu^5>hc7pnc~nt0dSRoj@!-w&75 zsq8g9O@$fL0oSqEQ3s^6SWYaj@Ey-DD-v4HykU#-a(QEe`WMqZ*F*B8GwTVd32kHf z^_nL7yWTb#Www?RY(HykbiH}>;!!Lx^lJCu0h`u{uQ_gq6cV8C&ZBebEpSiDK^+tP~tuQnb-dAyXd~+otU! z=PuLsc#r07h%;J$t9jeFc3|q#`o-cJc&)#H>RDWoOID9+3QID%Az{+3cpN>h+}H}=076-FLb68GgNAp!whw#yQThxAz*dlyq)P9*q zG7v^JFNKyH1|hg~&EgjNPS`QSVON^-L7`EB1+~45jlATi z90zjbyJ-Sxv}D5Y_0#jLi}4Fqjf_HDS38f z^*emy^{Dyka$71nX_*;?%&Y!76RU2xCR6f#P||uQL0|+g_N92q3xQ1h$nOnRn8kRz zyY*sSUh7%a=RXrZm}1iOF!2}LrTk6-%@1h8&z_9bm1jXvTN~xH{x)q?Pl123sG%jZ zK>ZW${Oj+d5A#(!)GtJQo;u!w@>yByz}h9c`x-J;S5xp@sF66fPu8eT%Ez|xb%=&J zhe~}doMqO&70nOk^|p&y1XgE#<5I>-M0YM{%`^a+SAO|yQwYB3%y5w|9MTaK<^JW|naQbg3RM}6lXv5{ZAp4Mcv!h3yKp-4`}2H5>4YA=YLdUav%7o- zX@`p&!<(DBtjP`RD+!?wiDq$dr2@ov%vJx&0=JVZzu3%~=yGR=gZH9B{gy^Qas2FG zLR@nRE_W$_>@+1msO)I$*HOI_!V)qw8lr^OP!C{UZ&0;v<(5@*@!Yz}ScMl-$h9t2 z&T0cJaQb%Mo6u{B4o7u!KFkN|U3>QNex5;ZzlWz?9BU~q{#^65s5SD;>@1fa@5giBqDZQv!^ zxqw=1(LGZ)1I&hvTm6WT?YM`9Ls;wNzJ7SIcChX*Joa!Iw6phP-j&8avlwmIk$rD>w8l z;Tj$&c8LvC(5k-3N+!&~z6I!&9W>SNc+CHyApA3MRsoVVeev{g*ziHF7ZZ=0DL14* z(`k6c6W=_Olt^*aukHVO@(}qE#6vZufVNL=7k%_|tqo{hd?f{yIc+mCNOIIQ;>;eLBBSQLmA1`*Tvdmf{{1 zH#(rAzFZ5$ll)#!8JsIYubaK8Naf;H_Ly?#39!|CpfPB)T1gl^Ed9t!9gJt0tg1~T z?(g(9*hmJ&B^J>g#-3VvguIke2=^&*#O_5pInM3|@xE!TA%&r1`J`8`7P{uGpGJ7& zxCn` zVc>KS5Za8cQ+#Qk8mCjy6!)n+0ofEsg&OdzOCp=_lo=bGh*PJ!Fs!2OCju}`>oi|t>51b;A?*_l~AzFqdD>HxW4_-B~$ z$W`iUwNzZARk-8puw*>fu@hw7hEgg5>nGM+`0)fK0np3J>GF&XN$|**TqK& zaH<>m6&n|BWl7B-*GJF47T?klentIw?Sguaeb!kN1zdw}Ik>$nniPHniI6{kw4SDj zZk+4ercFqOVZBrJ)BrQYU4xw4HR^dJ#Q7&0U-*zFdjmjZFHo#iHf~$m_&hAq(W~j? zku3L%`xn(HXtWne7G~=}C15|EoLFm2rx)AIg?+d3KnWZD%E{=IbD1)xNXX&Xk8gk1 zbzbNGZaYgEXPjd)9hQ>hn-p|ezoFH~!n4NUS7u(?b7+en8lH%=saKCCIiE*U87bnM zaOWi>X^)jGQ}v35=3%i%wm7LCU3&EkW8f-XF0?r`8|Kq?m%OxyXRMz$>^_saAtoy4 zj|7sf--%0~fh9qNh^2XRYWvmA@Owmi=POvd6rsDCYox`H<%VsG_0-j4%^K;&mTh)p z?9zU!Dk!t3ICP!Be&}3M4r`o6tQ8%iq=>#iC@C~hO9QOc@*mw;q+**S^*ND$>Nicm z`Y%!LR7SDF2w|Cj+5=3=KT+=znY!C+1EOJmsGF|AN+sR}HZ9=WikV5UWd_g3>x;=4 zGV+hg3yCuoAv$S0B)G~cXnBnF7cY|YK+eIe)Vge5c zsG^;J0iLB9#p1P4Y+LlysOrEyuX*vM`&V9)j&GQkK8Jyv4GzxnRnNBuh7~Gm8aHGY z^Wxg>*|^!s1GRdzeac>8QXx+S(rDt^;}doyk%weG32$L4*B6MPLY6Cn4RvFu7Y<*T z)j7Sceb3#QczNs3h$Jq*&uK8UeZEB4!pTF1P%6=y6_N*vCNcx|xJVmeSJRiS2c2I8 zzkVf%>qx*fzHWs0J)nx%%cL&xJzQAwH-@|3GLdaaHSa$m4W-P2$o7rc*uHkt5j+C6b&md zpEvl!+!Z=?M@v`^eb#LOB;vHW31Q1V+LjqR;hr6wyoEKFsfG;ECq}x2RxhDQ`I0bkB5V3%g@tA@<~mh1Sbzx-=RQQd#(xyJ-tNSwWj+(iSxAmBN#3%643>!K zSdJ~3+~tv(VpvIhzH6ind={-uRccK|6MYCnZm50)ooprFE$lg6>_(k_CKaKY=um;lXdbl1n8`FL5{_LCEV!lVd2L_T%@PC{! z{MU&mUH8D9XzTEb8-t8FiD?HC@jJ5cmjwu~xZ`(RnTHYB*UO6vzi^&n zel&b>8sB3PY}L>(wUG>oOUw9Y!$pcynEJ0h7b;g%Q43I%{znHWJG;EuGF!{{!1jE@ z+;3InlM>sZ*5@zJ^QB-87n+vZya$uFaNObdTxJ9p>p z8{(te*v|o@AM|=ChrU^yQB7>tQkr(cR3_mkEfFqQ~J@!1BjoS$;VU!C1xem@*ap|JdK4Tnlo zj6#`+Y~9G1E-Qc7a7gGac;9Pm`$zB$1M@Xk~LZw28* zjgd3U_vwT9K?a7EnNvTM9B_w2sL$J)&m(u<#xbRj%&YU@c)qBNbn|`MOd0dtwA87c z5|foHeQB<#g;-1gaU+&2sc(oyo!P?%TN}m`j_H(#k}*uXkJ7oG9geNWBRF)uq4^+5 zrN#I%DpWDt5YZt*1+f4Lg=`$m+fX@z9b5u}%*^*#354$nWarZA&Sn82{sUdKPldOW zeu%bA1>Ya>@Vzeuw2Bh~rCph#Qu1w5dc(pg$rQd{r?mWlq=chN1kOWqfrKIRJsf43 zbEgiVP$@?sYK|xs#zSe4k|nG5w~_CSPzT5*;duV8R_~?10~Okrup7S}g0wwGIeA5R zZ1DkwS$W@CrKH_{C_GCr%VN{WAz<6Ppi!oXj#q7<(-7Ub^6OJN^I0CQgehISDOL=X z<0k1N`lD@q~ii1sBNKMgU&1EevbJGNf@| z2O&FB0&L8T+~m4f(1EG9?MtV*L!p@Z3o4qOt?`-{y%Uf!?GZt>8{xr-|NZHfELno1 z)C1uNq`E%&iR*9c!=bVdQE8`QB6>o?_g0a;?d(U{VbecLPBXJi*CX`DVfmHn-b*y|L*vL$P1>EQ z6{P#zu44i?U_p54h2Xh2^l3QmrZsH@aYbEnzZc_IUr~-tfLNuUcn#%)gxT^I*qU?R zo`Op%8!6BI`gTHdgxH+@LwoqzQyxf#WCpNXBt13g4i3PyYH~ocWgFWg&9x+hedbk5 zfA)!H4@TA#Xc|Q)(PJr8$^=&N)Mp`J5WQwQG#73@Kj>I8jJSIM7-`Y+_4stwLr>BX z7wXY@4zQ7HgplHiJ#7(7^3Ko=jiIxwe#BP}mv;n& z(~q|S;Q}9=$w{@q-o~i}=0FR~2KRia2ZO7W(@1gyk)gkn<$mU@5+mIPY74lOZ(1u% z7FNCrHT&PQI!gvERic+=8AG4#w94TX8I zapS?R{b*9_%VeD`p|={kT$@l^H^3XX7n}R0uJ_xI{ObC3BMs?!w0FN9+nSw|<8zY| zm%IWmXmkVhkX3^0sx3??t2#6Iq2(F9w>v12?+Gwss^?2Ki*UP8@=0Wnxoz)!Ti*OO zG~1#bK+(jWb#}S?mbi>moZPmRQFfxQ-$5jpH3OG4Ce*B^$sJDClbR1;o7aek-(IQb z0;e7uWDCIlqq_!G#{Hki`e<-xZAnY!?-HeX%@*f7x?sFv=vRbUE9h+dOEx0DaWo0O zfXpT;o+gMiW+H-{ zf)XZ6m%<&@DH|p0MO$?o@h1Bal}(kfJt}g%*z;+2XjvvCU~o+;Px8Xd8p6~Va;pv* zlro4Qp)tqwb>Uu!uHiN@If|sMi?86lm!x5-XT!CKAg@0H(9UcDD!ah)wB|75$cLDp zn7Z<(Im%+uV*3Tht{+1=NBq~Lfl*N3xga`)V1yn518LS8L$fhFT1oh4#W8cH;1q|M$eirWMo@7999JyH8Vmh2zNb$=+rypbdn} z{kh+@5|AsM+L+(HzA4yt)&J<0*6_F1;R-h7Fb5i^k;0Sh_lew=SMwqtZqTl{6Sc7_ z)KTX0`^C)d`Zq#y>I3{XMALyk``-dlrMdk7H*2$&Y#>#>l?=zW%b`P$)$e27MC$x) zX>WGnsn(V!@~gzC`0%>Z3T5i8?d75AO|B^g4gl_3pPN$2Q_0>hq}iJQqFo6h8a|u+ z=Fl<*dtLAEbf9nuZ&1O8Bu)H#Cy`tl==!I(C?cpE-1C2~rMAddOy;4QUIJCbWK9TD z#PbvJFqY%Sv+bMZ66NgQW8X9f_MZy0k2k_Uw6hDWFm;7Vb_eX&3 z$uh{Xj&5R`{y5Oa5^`160?j|{+1PyFXb@r@9dE?C>x4sMyNuba&D>DI(nVYGNOr@3 zZ{-2sl_EI>?47icpSCE?m3O0m%T53sm z=n;IR|0aL!6vKY(0nBcF zM3)>vKdjUy90S^a36t%%s37sNEvJ6y@MBCZuCK4kB2s_cOJV0Fni+oo z*}9dcTKHJ{sA5HqI6?%I=Q(->BMiQA_x`|(N6Jde0k3@q9{s8iF|sz@)z;t???H5^ zAl?Aqz=*n3RJYbLjANOgP~ilvvU5f2o_Hl&J*nCCzrktRuvXP@gB46XiFN{x-I6w+ zdke_;2Sa9r_BC5bhxpCw`a+)XSD!XKsiv)=U+Z}!w=X<%YBi)?swwO#{EN6rC`^=n zK=BdI^*{6s$K1}$2>lC6_^?Yz9gzfz%>}x1>Tt?N zud=ym+KrrllenftJ?MokT%U=GhpiGv*;kD973$Sq?Z%~{!8iWQS!4X*g0oHe+U{P$ zAuk%&l0BarGsx@}7jB+O{8`ZG$O4iM8O>ZpYLYdmRm>5*(LBMlH~(fEW&J$`>!CdU zI9a_mJa5hu`_lEncLrTxJ-!-?CtQE5P*u?s`q_H!GKV~wnGzGN%H)0F9euphhgdK+ zayUMLRGWrXf^Cgs4s{@_S8JYn=?mDHXDk6$m>&Y0_rK?5oPx(n=;D?q%+M*$vz?;rk}Qi+Qn<%-N1iR_Uk7jRrdlW`nFmO;mX9R|VNLJp^8~6R zv$G)oA4O*!*3{dFaZHpDe<&rTq_i|hi8P2H-6&lf9h1RO1SBUQUD6E_V>Bw=U86fk zGd4Hod)~iyU1vMjIeX4??(cnnZconc&YoFn4G=ir74rG~5Qs+I#YM1&R5Y|&%AdIg z25cb{RL+;s+x$OMI3FKo`ab3P^$VAJLs2E84<(@zJ-WaKY^2)WdDNr~+~kbj9(25Y z+3CBU=307R!W<{EU~X1|>gPt~$Na$gb*(521p>@Aal-;_%4}z7iJ5G}Hd3OjOgJa) zZfD}b^?o`o0mQJ3zjALCY3t$<^C-dfYuMm^EkZ7D&?|fjQRzrp1~Q3(<-6_#yuu(a^X+s!FlLTLngARSj7s z1a{>_w|MV!ru^6f+tB`E=Y)Qnv3`C&d!O;3J%diL@WQp2%9 zH7)Ma!h-+9-;jh@LY!QLON_O}{0grMCeUQV=z2mdzMlbK9_FDNy0~-er`XjkTNR(_ z$_>A`=V04&)}SfjWr(y4oojc0-)4Lt<$z^WM=kT z5${DK(D2kp{KdY99(4~s6;p!`&6 zpt5kJg9&|^K-+{gPU?Q`yKD4{&*_1gadN|7XrjfiySqDQi(B#@=rtrN^`@|x(l=|T z3xbMLseAewH>*=RbGd8Hv>^4O(2(aZu-81d817YktH|=BaQY*MpYb2ErDR(ImPb@J zhCNRpQ^4ll}-L__^4R2Kb?S2sUz2RT5C0r z14Yd-y5ZgY>rFsC?KWt^zs>da7FBY0>uX8oPSCnvtFH3KcF?|OU1NkwaYS+8cH$5! zJ7v3PprbKm0H<=({rN5}6yZO94Q>A}xPzF&~}QI!RsFx@_~}l_*R9tIeOk z7qSDVGy04e!~DaS#Srd1TfhdQ@#TG+gXE({+aJ5U$))$hyM#5s3F7x!FjgFaanRaV zREhg4VimWwY?5c>Uxo7-EY%nZVA@S>8+&eWJ_w9gM!Ekr{%eUmesrZF!~bvQ z3cvl8wA^$Cv7l<^i5AI0nzr6S2Jb7`(m-415ml`gsR`Y&`r^9_;;iXeC^$^9XMGmiUC}? zW{5b4c6BT^363Z1bC74_WY2i*Zqr%2P8u2yA;Tq9B29Ax{rhoQ4;1{dM2EaH?LSLW z_Rjf#w%3&SG`OGL>K!E~SXZjKVwyOd>hW0#FCkR!k28#3jSkQ|^hq(_V`c~`IlPD$ zT^!`#b2+S-XzTKt?`LXS!*B zHJB7=YwJppq-Yp9Tu94Lp5ElX5>{)Ie@!BrJfc}eDoz=qx&o>*2ObU@4(BY-6O=PN zr4?CbJK+{Fp37zXM#v{th4*7;hkOC|xiAt!`@;Bx>5E+NmN~S3`b5Bos2=C4HPRoKV$|NixlsrY(&!5g^Mi{hN-t~VIeI%6JeoK+oH85p$1UQc;y-O@D7 zGHTm~_QUWT*aU@`#DEN~X#o%@8MAU7C>J|Z&_wsB2z&RBB=}Bd$O44l%D9h5&-Q8`g&iBs{Iy4syR&9?}zS(Q=3n7Vl{TT}T%mhxcT_D#i*-<}D=rV90rhf9?NQ*4cQ znRE3A_d86N=e;=M z#5V2a-#@;R9rq|f*>d=27%9^t|Kt3XIK;n(5=n?X_=HSU!zB5dF9?109{72dd+E?N zxy@HSx6_T(wt;G`JG4$z%*-qYmd*s&wW@NhZ;Ls}Tc>QtXmgSKqOEe);bAYZiK~K@ zYjXc(=mGe}P_oGz0pZvoKK!oYt@!xFgqDC}*`78n@3wYj{Q-}u zM1z?aoPyGI9Pw#@g27bo1VTqZNWea6b+S5CeEVVdV{>kc5_lkVNoP1T{X%E{9|=aT z7OP)T)Ka=~-J*v~GJFE4Mrk&YqMnjo3vch{-!_4I?E_#GnI=<}+&3`1E6Y6Y? z3q?%ci|092ygfPIEagGI6r!TX);vEV;}bx=-Zv9(T&ZpBnHde&(B!Rd73U@~rI4$- zxCqpoXTsXyVfi~!U z(8x+`&IJ!%bq1v!)#A-1s)gN?UJ*%NF$YeeeJ0H76ZtgU*}pHz2BvF=lDJ1_Gd3Mq zxeL_Gfn8%F)^CaBIMVvnsSX$detsR9!GY&zMN*^+OTYfk2o_cfw9RleAT^$SxC?Ns z=IRGpvO*TZR*yJVZ|%GK9q4?@O;F!(jZFGNQSxWYj!g3BZ`>!+4n3FfTz~gc^P!&$ z)hJ5}z3vuU;ou&gfK}Mxvw;y~ z2e*zBi+m97^^I?x%)rysHNBj2laI4Lq1TsOBgLuVI%_T_5B)UhU{cP7nCtLF1uvV^ zV*DKK$ub+SFa7EiFuoT9lZ_|rj9&`IIonI6Cqb2#$r8pg$tWFxg4i3J66!j^jpEy^ z_1n=wWmwIgStV!osp{l)KFM&{A!hL`Mqk=BU#`k4{5A|I(%<;Jy)B@20|R) zSzjD=5L3$nRtS$$FbXpOb*kg`!K@W;$t z`N$hz*C^QMJSL8_)+vPffFx$M;5{fNqvX6%G#o@$@-=PT%mV&`b=`~)rQmcQPC%D_lt z2f5L0Wdw69j4r}Xt(MYWu+SG%C+5Z?kJSz@(u<)me|PV@uc3 z5-WfFyu%wO>)X_Qq7~SF(ZD|HFh&CuTl~!4%s#qxPZk-btk+WBb9N7JFK^ZM*RaqI zB<_&Zx=S=^x2NOn%KSc%^=qSv$*`A3oJB7vUEblkTEVeRzqg}~LZ0-*9?>dlV*cCF z-M!HyujdQ(i8cV%9YbF;(W7zS$5^V=GK%0nb(9i0E! ze-xYQo+5obQH(;AYNpHbVHmDMGcY3`1=Nh@2O zRR5-eiiGJ*zFt$!ah8v>AZFn>;;(j8uBC#O^M8X~qYlYv;I;0`m~?@y)fF>!5|>j< zke=L0kP_I8yMR;+H2Qpbx~S+Bew=zG_h6+mFc0XD{?k{z)lE*7LkoM!38Zj+Zm5JVEqf{swEkbltA~41Am*X9%AMZOe2m2!Qmi7Bmc)q*| zzBJF)z`0(0taqM%D^44+>2qLEDEQG`zZqMJS1OKem2v&y+{~4cyPFO@(_(JHMJp1I zh`(fd^>0kkGOd<`GicVkoJzt3iqwC$G3>K1JSkQ>UaTowKOIlAKUId?m(xD}(sBRd zI98q?#An#lXzqYW*pnahVGr2ypKIxwAK36CwffTxOxA!o+cA2>^n!{8fV`jcnJsr> zXu~;4>A!F3$UaEY#~8<%5Cv7d__wBV5uZ&BL<%Q5>)niP9<1JCk%_|VqjhLA!mR;{ zFUxd>*Ouz`fPxfe80!Aez_V*NxOZ)o&H=jrT~!9@r+*5i)ihEDiPs#tzMS0madWk=`lsw!>cQ%K4Z#cYG6H_}gtHH+81 zw>G#qJ5v}{w8jxww_vw`N0@GG*2yrmg_X|r(LxIU4DyVz&-|7HS%2mODUwe~Ric== z>k{#txOSRxI_pUvrz1DnQQrLl2AWL@ky}SLE&fa=cjc3=dSet;vxy|9-U{<#EyGMl zhJJO8lK-u#32kY#d=Bbev!({L?pGc5o_J}ekGjzYK^oOeErs13iCgI3{fg7-OJjHz zNL2;@WJ!hBsWq*~k#mZnZsDLADzGi+-C1Tp0*!66xbGr#1`wA{6vEqV*Wibgr{?P& zVf9(&o$d5^hm6XSl?bNnFi3x%sf(k<_ZT#Qv6@S5Hm<6+;8OwfxF+HjyCK zLPm%gs=3~>gS(R!3lO9)ij_Qf)V>(5d>cMX2~K_L*IVgk%jx6OaWD85whkyLVxEaz zW2V)%IU8W-Kdj~OT#;#ZkoXs<6(;aP`t_lRka$A^kb zRm0LW<2IzL!PikBbUR1zNbpN+P+sdh>;!S0Z_3o+Kg8y{)i1_Y@$l65SMian2{P{R zl?RvA^P?Evap<%4JwZnEDRB*V8n$?@@R7Sz4Nrf4Q&sh#GIIN51)DJ|?HlP^n57kga0-Z`^;QDhI_}f`gH_gO@zPlp1h6Hle;R(@aFcN(mXqRj z&Jj`xzGr4rwI{>O@RquWkB&l|2BI;~TGenGE#sq?ZMDb;9^zjb)k&doVCE4j7}_6* zJ?9%}N!gaWVdWWx1-9&~#VIBW?rR2QjK$9ObdT$BUf2GArAT&tI` zWP`3Rq_y9nSBiu~DvA%fp&d0P4Ql%xr{w25|40N=h<8}e`1_%7(W};I(1rp^N0n}wasn#x;lWAU^z~t_avaIh*>mGnpT14+ z;g4c4aw1niMy&0+*poM)bMc1QqP+NvB%-I4Pr*zwEM=Qt?M^HIb+%({u1e*sOsP(3$x6M2+ zr^Pl*k1XyL(=Dr9JS~<{V@m$s?#qI|Mj3*+kPqa8J~O+Mq)wgG^f5b$RD zt?Kk{J6<#%@mn@NLFcIvRcP=N=&S28g8#aJ(rYYYy*!ZKJxaYnvKrj*C7az;{{1T^ z=190%4n{wG9eA(&j%{j~9ZA^Z49K@ouaivswS(_Edui_~x~6j|ihr~0EZP49n{cp( zE??5(HOGD8XmkvIYfHMtzEVwMn|`sOnzvloMs1xnB6OL^olD$ER>94b>gD5q?EWUK z&c+`%yC14-z;6#y_kyy-pU}CTLObFwzmGa- z@{=Q6s|E%i=@W<(crq-w9XH*#fS3X=U3q3^Ch$GNC}8_f-}bK4eGPs>cstA4F;kCm zh_rUtduF#6#w@MJn9WF$sf9VuM8{)>@|3ZfIyHCSagRrccf|3Dap? z=*WNDF&Gv&jl_L{s*LP)V5EB=bnFek^vNOKxmVg@%th!Pzf>mxk+M59#DVb*JXh#i zg2DWP*dWC*JsCM)&|!lH2gT}N<9)hNn=>doxEy)386p}*SOSJ=?@{|X)beZrgFXH_ z;?pCArS#0%%FA6LXPI$7=-%~^{-_@RNAh4Ui(5mT3lvv= z2zGpmu-DV6DA*)o76bv%|0I5){cJV~i;y7BErigu ze5Dr*@roVecj^ecpjJ3tv$XznvP?ey7+QvcGRr{`g{<(+AYXSJrxQTdRI$F6RGwKv zWbid-u;}jitsG7CRYM5Z;L}sWr=I0V;tjTO9c|~jB0O|{e+*M$G>>tNTe#r;YjlUe;~N)} zZH!3D-mQf<4vbAiUdC-%V}>#DoSfwN6esIrSlipBmdqfOEzeRsP$e#LW%ubLqqiwjsJm(m%<%OICF6sXt#?5 zd~0MSt(0V`+t>>rK>`e7LrV13A$o(VM#UWw)2pb;?Ywna_NB?L!0~x0_oGvH3;?$M4B)kfI_g@pAH&x=;t(Li;sk4X zzDJzRNBDw}mk&}$uVVdSHOGfn8~;d9b(r)SdEo;hk_)l~FGU+J=>z=h^-C}&-h7)5WnR4h5w`?2<$9hdLAJkzQ zSoX_vSY&0^;5T-gG39w?ivrX5L7NZSB_6%}eqX0(cS>ccG_QS5sX8s`y2tv`li@}C zav%DqB6OaGs) z#J(QwTxN%TH496@Xm@wacUQKxh|oXL#Uq(m3_yLdoxqm_eh@eU_74fl(TVVMg>}-^2BJ* zv^T#r-Im$ml{1#L_Xzq&@-F>X?^!JoopKEO2t*WmQnV#X8eVGla$b(;2dbU@q4Mr^ z`MREwB3)hcRf0TWqW1_RXNMcD4_6N0Jx(*1q5QW zu#VLMRK4jsUk?dNZWDr;b$i8bUQ9{w&^80)Da~)nZ|dTBa=`x;Q4`=bT-Q`(2O7Z# zpB61aX-Q-v*U%64Pl@_+Jvp}%d=7^Si1oW0kJ$&seUwX z5mfh-C90u%gOty1R`+{?x`yicV_6Y<@(ubhEH5FA-aU{{T6?i|FLmAaiZfVkO}E< zwUj(0icHE+Gl7{|xP{Ued_34}$Yk1oeF~YnE(ak{j=sLiuBTS7S9r;HRZGEEN z@gnF>;|1J2(_3Dn*6c~kj#f+9Yv%|>NqWtDGXS%GnMZ!|jYDb36d3ZIJ5~zo2)S^w4eyppO$9X<7`f zkr9#z22w4*6+1pC+$Atz$*Wz`l|Lq~%%L*A(xKlD{8oE5-gqmnx0(i*0WNa-;6(hu zO}J5Wl%HEY56AL3)JR0*U$~~I4P?((qVC%)?C?h^TD<5vr1R;Kx!e%PPC7nV@MUdN zhP5E?)lz)ShW(wsG-U^8xHp|xsHEG}OeejuSS$q1U$7qDT5W87cY2_R@Li5yM0E1? zNDOb0tiIp8B!_=IKVBg3RodW2t87sHm%1A7E)>uxiU)6CTV;6-$tTzLdyN-*EX zHhrCz$Q2nS7UIXv9#uBf;e;o;<8{tOSv#XJ`8vznvJ8f`>dC4i5~fHP)fMWEUpHe` z+B-udE}Xxp+uqcBze3apTowVSF)j{K3QXf6seeCRA+=<8wBR zC<$-M>--yFl|lNzRmaE5YUg9?I*t4#{MtEAX|p)P(`O$+TqYj>y0b#|;`RGSBS#{x zTj7R@H_W%KlQNtae+6b=a>f;khfVamdwYzmbZ@gPcNX#Se!nh&Xgh1Gp|dv$@VSJYy{H{-1k7LhLX!Pxj4MbJd8HW6#W-3>L)6Qfvz(QJ@wb=O|;^ z;T2Qi9U?93cn~!;E2~`|5C!_%gRF9i?s7t=OsGedNqixxdHS55Wsz(+HpBboiZH%K z-Vh9IqwLiv592G%28{gn10@fwPYUJvpdJ(TuHhi$TRNY2;lZTr+zm3T@2}9-#VicK z;^07#N}pz^td<|=9x6-!QZ^tQde-g*(3&vU#GA*v9Wt6sjJg zd)9T!%qB--DZIlX<=?G&T8HN@N#g;d&UVt1?1&jVX^j1+g0-;9=S6=-x5I(sm=h!s zt%<`8(<~_MvS@*+Z|%mVRIH_#ZVh0mzKz6!#31HD_Wo4y=DLvo;$UCl8E4`b1-xd; z%GPPdt{``T=8H~GJtZ=M4gUDDm)AQ1goXoVXJHs6AnwLRg^*fC6aMM6#I;#y<&mv6^x5#S6Qy5Q4>gKC{ zBKqJfo0Oyfkpw;PG!U$GG%|{u&ov}Rcye=JCyqP^ya~O;mYw+715sq@xhPPs5X`LR zn`CL)a5CuW^TDWp=c?vGP-!+BaI$&?spd4thQzM%TAsz|QqJMl1ji;6EB!|3aW)WT zpHW_7V+W_n8>!lod;eN%?AE9SW(*K-3ZtLJry@Alz1YECD=+7BK(P%tkoj2gru}?d z28QKa>Escxi$P&O`EuDJ5C0ZT^)kPkRfs1zy8$Z-u$#PSLXI@oDb*{NU4=^{gZw~* zSEGPTQljL~hHJM*wIX}! ztxi!+NEQ#glD|IKofqOiqA?>+j#FREkF6vZd_cHQ;-JT^YI_xsdK>Ki0oP<#KyEaQen72CW=g${nsEpWE94`z&q49{rj1vw~(Y%Chs?Zxpu61%sR$_7bR(YpGMMeJNdx(4ytK{ktl9uWnH^ za+9Xl0R-vWvslj`OXdS^mua*Tto%9ql2z=4>W~E#CFG3NueqIKdN57eI zD=5_Ru@aUJFUvh&l_32C*#?1rkCV}}{_x6RTa`D>=Eg?pCfT*>3A{6h0!ve+P)m@@ zHwh{%NH#a8l)n=T?M%cM>AujBQ5%pUYpTRjbqe=8dI$a3UAE8EqG=`S%%_jMxOcRxI-BU8omK5kNJ-r8eJ=m?twXz`AUwS(4SeoDG#Tn1v9)-=n}Oq zJadvT>yAcQnW%VvVB>$pfoVw`9MKGi*WC)u7Vbre5+BC0tZ0E`)F*7}fQazX`?}9t z�!}vnA`1-=ty{H}JG>*xl<(!HVHJ;R2W_Dz2yc>NL2d>9f+sn1-ga}`UV|i21zPVVu+SnzCbnQ5lQ~N3%QG(Pm)${lxF3b}c zp18>YT{f$;54qW)1ROM+NH;$3P&eiSQqT>XpY}NjKogQagwSxjRXqCf>0IKDl_j0d zNepcFWPZM<5tR%)7i7bEo zXwZ9a!=JlKMDe0{VIe3&@0@!5G33#p!JCDSREPp!Y=!4+^_rm|(n6#~bzr=BknfM6 z?9UzU9eC!Gj^Y*aaubkE+`641fB)l1ukyy#hjF+3`otX|&4lbwK#Afi1 z2W57$)v*ZkTRgh#zbs|c#rq^YGX)Vxy4U>-n#16)6mR)y9868mAi`&)*}}z`jv74vd1714pg*Fzi#ahIoFgile@^jfhSwxQqi*TF{)Fwo1cDOO!WL&bZa!Ugv zQ+??Y%Ke{uL1toTX!hlutY)(%_39=LA5=`OT;|xZuWejS=0;-7HK0{S==e=6tFDMg ziR6j>?1pUBoxQH5l6vrB{@0*mdif_$mze|Z#LZH7-ho%kZ;wciib&$)f_U@94z)as z2F1KJNBZFZ*=wvV;fL|YZYMY2>i(2{wDQz|#d<*iw4N|yqy-(QDrf%tTL078&*l5v zKRKYCYzcIsT1a1qD6X(}z&c|x%tAtP^H*Kxdi%0jcRVw&e+6=*1)bVwRq@bSd<&Q+HAx=04&?d))RL#_|j^5&CUj5`6J&B zG|Ca$cxp@>6-3z7-fgynla(Tbs9*Gs5#|)$8S~pAo1HlujI3+dFx^*E$N>d!5%hcS zzL7hx?cz;3`ETA%_+u2WA1F87=wwUE`$Om6=FiO?{#!hMRUr9;(78ZA<*D}U-|V;G)9NK=#GP)H(Epij9R_f!RDWa>T^gGceo_Jzecmw){m;% zIz1URWnST7KFEWF-z$F{>GAFGt?Dc;PA6Esu(cU4n7d=~daT~%5n!anzheE)EL`%HBcpr0T*5I5_A(hd{=HI4#!N#WIoZc2RPrZJISpk>aPmzk5r{uFSNjrze>uwuv$h zmhE~XmY@e7@ATd^3NE+CJosD*`Oleuq}@g13Ho{pPSq!M@4t2ij%V)cV=d zRcWxgY2KaSU5o4mh}aU+sNqaZ&%DLrS>z9Z;HZZ0ypnDD#bH}*K{Zk3|CUG}!S@j!zX+5d5) ze_j~QA-VCx-HP^PHR`$H2Zv?AcY}UL?`{Z0c)Yst83Syx>bmthblJo7wHgBoKhK~f zQIVT`^NT#}-XRLpFRqwhIz}0pfElUtMQYK;&0%YPLVz=-Yb>N-E%>DWlC6A@jWAX` zf5h%EH_n!#J`|R6m*IQxvGZ?fDax@aKzVLK3Gvnf@uGf0OxL z`j%0EKvelE24bDz-obtBP?^@65y?Kel)v;`hm9{}KbM65KTSD*M~1ED zY4h@Tz6imBWU&YrT-^dLP}x>SvirBi)l>bB+O0tUE@-nPl+Onl`z3Nt;eMx-J-c3w7oF8RYBJAl5je3 z6s+@7Fn$$OyhE>ZIG%$ zw1DA!!Rcc-+fhSo#(<8*636vs1f%S3yW0(dvWGNxx?M`bl7%d7f{Me@C)IuyaU*|) zmNQ32Ph@d*p%T;h!gZcA%X2$pp|+{{x`$-X7jL|=YoH`y8}_PIYEWrS*fyGftj9TV z>6FA^LVD}jPc^)f_(zb!VIew7*`i73A}}Im?d6Zi9^n>`zK!K*lLw^%DaRik^*Su; zX~}+=|6=iJySwl1+b@83xmWBm0i-Lq<(zXQxzwaOI@BMI3t=fLdc_52dLmnQzaUco z%9WVZK5ue+MbPx_B9)c=k?1>#4EZLpNd#b5=sT!g7ZwAx^__LqP%gaMUCwZ6eV$_7 z?ku^uIJzmq$LI?>9xDi?Cwn_~-5hl%XduPtqY^<7&&N5u>#{dK&~=6&U#!o0lu z9+|wS?~PWaBb&pKkUw35zg7S&;N3+o-{67=hr2|*>ue?W#;5pjI;oz2Bu5+a^~e-T zcQPGMj@sAJTYQ7}GDb`QX(I;w3)dufy|2a0j3{UHeiW1|sQGIgL}%r2!#}3?=|Bus z+qKh;3H4-<$g6lznysjGJ~^9xi%L z`+TgHxwuG@MINn}grMT`v}TbPvlv&4(FL zQN$`MtUmy!I@MpJNU!&B8sDF}*Wg{)<+UfGEdndBxSRdZfcJBOFpBDw1+y!QwC($WSf`%tL z8SBE9+tuGa+aMJI>jt$JW4^c7oJvN?vaZAGB+9P~KRE9!4q^faWwsDH5ToARa1sAmyN^|7+VoxJ{MQ(e3QTDC>akgDz&nP$+$UVr=zRyDTj(8s! zXiyBGta7&~C(V1>)&7do_}!CcWW6PQvHEukQ`1(F!`C%1RKq8dAsL^s?G}0#dO_H` znf1C`f2gq$G>{`Gm=D%^f%_Vq=~#_0;pd9Ki-CPdCf#0WlD$#;HsbN*BV#@b$fV_> zwD#_y`8M2d+qRx$Z}(;T&?#$3rR*EbnTwVuhu@i~O07>i!&es5*P$6_<{z9GMJJ}xXaGTnq|{e3emSu}psJ1SCD)S`Bp zc|Q0<^x1i1PK+pYF_y#p1-cV(~F;CRc}qIJTW$ z&>1qNK^mRPOEU0FM)c9h%bSu!O5)5idvtembp(-3sleRYRQ*>h*XGFBcP2%F`ZfE= zy8ibjnH2F>(ttb^i9}8ksRLTNo_wD`wQs48rvpQ%5t^Z=?+M{W81Y49ld+efN)K zp|jk!Sb-*O0C)_`5QrT8AVt+lPOsR zG0fO#<(wA(i{Zy%W-8CU>ED}FsgDlMw8vck2$q!mqwu-8H;#RhILlf2t<^++6m!2I zL9Z;b>Hez$X0OHTWyFaPT6CS2-UWuVLgr!}&8GO@xBhg^kkRHIZVK0E?GUE3`^B4V zWwLsQY1SWTKTA$IwZ-tBDz~#Y;T^w<-2)3CvZVT(mrs)-zSaK9kHv1rkaV&$s+VB` z!X7WOb8ezw-bREs*Ae$^F7l%)BZA8GW7P>eZ#`3%)Gt>kh(NeAvf~3V>xiBRuv$8< z1V&&IBbW{JL!8IxCcoAT)B%so+gH795Xo==mZLz|{tT)Bf+=A+eI>%LSnVOJtqEK7 z${AbAuNit2^(MRzUD?%UeJuTn_XkT{jEy9-8BQuE5n)GJh2I1p7vSt8R~WmJEnH;N(>9^Y!x{c$n^OoP&sGiihJ8$5BLCbEb>Uhu6;Lcawzx<8p1Xu^Y zSJ4+jb*2G2x}t?cTy~A=(^jGguFtAWxDc=VzvRMQk1B<_J_i5zDVL2Xwv<s{K$JaAO(#mSCj1YLnzOkc4W}@H;CC2Uzte%?pq{bKA1Uf zXLGV%ptfj7796EgR|<6LfdzV3BER+#u3h_JuE!6Z|E7dYxRMXb>B*R)HtdWaTIZF0 z4$%xr#zg}4XIsPmTV-=4f3y93Q`SpYT{L}AlVy(mn1{dJAFw4XFXh|pBgsIUplE`M z*O$aAode4|)tz`WSS;1tinBG?Oni7cEqz%uYq)Lg_SsufSek3j^^baN(k$ji`sqiX69jG?;>6$C*ec7vlqG4>ZVWsFUElC@p6OA z_c(!_;NA@rUj_}HqBudk)(i_{#$ekcqd3%K#;lZ~IB8B${;(;DZSN9OPK#-5fX~m- z+p$dXby@_^_Gz4A6601+Fgi#YuMT}XO`rmNq0;3-n5xpU+_tvBuM=xx*we4yzMdil z1`;p#tVK|k{9`}hUaBoNa}zsRP-BEDLf5m?nx)YW*3>i~#@yx~CPB%VTo8dK=m3(c9@r-YFbJLap?rP@dMy72c zR2%<%_(9I;X9i{)trUchNitApH}TMPK>BHk?vfO~sC~fvs}P+>TDyZ_yPE^;yDMXF zE`uoS5dd6)SVb&)WSakh&IgaEr7v~22FBO%EIhS;ccuCchYI4EeOLqs=kYYW!Q!Jp z3uGc*@<$U+>8Brzw9k6MIozX>?Ylc1-Z2-)T9~}?0>H#3Qes)QkmTLp2cAP)OU+-( zX%64^k1y+Q@?SG8hWlIT@GYEF$8@aL8S9%7#7|l!-_!-=?K@9@`MUhZB}{5`h}~_c z*a}x&m%YxFrlG^@Fq9+l!C}!aChm((`~Ro+<4(KFH^$t9@z+h2{t%~;ntOGFp+gXX z5H(W&Nx!svvw-sc(*0;Zb#{zWLBcj@w z_tJZE3S3cfIUm+<--m%7@p~@w=6q+m`T9MEoqf;RTrWq=Eg-%mxd28js~EIF^~5DT zX~Qj1w>1G`3iGO%kRH87G>w}MBjc`mqBcas7M6|?)5=w@G?LbQa zL#Xauodz4uB^qH8w7s}596A}>R32ks%q#l6DXR-V-e8WVBnPReibyg6_9n3k7L{|- z^r$&i)kIq;F$DJD<2cuWky`X|_40Bj*n5gM#%LN|~lrP#UbQ)+K2HF0< zoEZ@FKSQyf&pR z=g7pxrOs&5Ix4FEuf=cH>NuAS6+Ybl)m4^{-6W1>yCDA29|PZS?qgvDMhy zO)B>dPL@24$zDk-fvwHZ;YD57OTfl{J?a&h_AwD_x7av^dD+=H*!=b~y&fbl=xa;i zLY?1u;<=DZW2d^?LW8^U>ShF~)<I3a?q`$%iC8>#t(#OjKq%8mLg7B z>(P0@sc!T6k?Ih*@4!4-a{MM0T`Hh9 zTuuGom0*`@mUi=t&-?z-v0(8>*=OIzjD6HcU)S2`EqnPTwDM0BFjF4j z*rxR<=rFv{vFdsV8sa&f4(s|yhtTOXWH=u=1=FT=Z(NJ4-OU^%K8j^>KpqM8F$z5Y zdB4af5@(e!FdSE2NHTzk?=xb%|YIL@zD_zl&@FMr22fM9&i zXpVo5HUGqGG({ES#0WbKPa%vkYX9ZrIeK%d`gQZ>gA(dZntiLe z0K-`}R7T;bec()Q3gG&wQC6qjXxq2s(sETu@83{!jLRVI2?bGo0+0C#WyYhlNnx&F z=fbVyW0mkY{maNV&{7tUhc{R~&9wyQ9hGEQ>5zJHvUUSB|~Sop*!1ceLJOGV!c(Vm&d4 zfFq+?^_Bvn7YYNJW~6k#j`W?Ba=$0Km(68M4BZ_Lp-j*<&6hD9ogWF=n)Ujn+7I{}1eOO|O;NKYeXWD@oPOcB zB|V;J<+)A&=mOty4V+Ie6eR`ung=|7Km!5{v;9&hk_b0S5fZJD*5|RS^6diQ|;$p3Y?- zfsk`uSNB8jJZV%b>CVT$fkc@vaZ0xfZk-F86Vxj<26ppZ)8H^!mJoVwK}BDknyQrU ze0C@+MLsw@V1zF?W<*~<-KKVUNpVB@YSVx~&a(LmEPoYeyL8+~2#TrSl6m95;9Qk9 z=nNZvQNa6~9Q%XcC%=n{(t6HRL>Sj2#Z$ycq5tR%oWtVHh@+E=|LDreN{YU(7Q=`z zQ`(SwKHYj1>)N7Ll<;cnP*dB9gj@MSrDu)NtiPA|w5fsfJJE$`+$VH*c=v6%kDbOp zy3TD)*8qZZPli%LCH3#78;6CYYg7Ek$9z4NztyingD5`12gWUD(J&5@mRDNAWb)YJ zk%-O6oxcpW+I!7h9RxdF66BoG5?_lxep)l?iDWL^UcB2rX3)8v+!GtFFi}JPO8(_^ z|8v!7FLS-0u_Qmwn~k!i-s;L%UK1lVNFf6K3sTz39N4(?w6dzSc;P7@!5Y}hZ)r&{ z^UUXSr~t@Hfow8O+pos!pxz0x(FQ{K(dTzYp*~=#gskcJHi{2sRDUvDiyU4zx|sjv zy5+}VgYa*P!jLpmQ&g+1jVagAkKIuD`K(vKw6)j$zgSP)g%bO0<`7bP4gxMKy0=55 zy8~rT%2gM5e=N*Le$YjQ1rbb?;u^QBPlA*vlg^c^QS9NA)U~|@fR6)0Q1NIcwiyOV zi`X~iYOF9c-mFf*e76n$bm?VPOhM3#&AhLt<}787n-1su+j(bA)jDTiC0CP)j~%1^ zD<8O+#A&Qh3D&m*VNMX9I#r+MH|>yagK$L-nOR}zo>1n5Cz<)2=|Fxuzs{vOu$sMP z{t0+>@f(LWrBjx*#G=tS4n1)qvB@@mt8!|Y&q{OdYzALM_+B5MWL9#eg?xT&pC)LGc;srV zu4L9Bm>%UWfDEymyXGJo9~&8uwYx&XOrup;WWQ92=-+x<6Vc;yS84)V{f`bfW%2QW zZ{1KjM?s>T+EZ}<9?^ImLI#~EA8Sm^D%Nqr7j>5`l~~aU>K?p-0IX5AF??{aOkZhp z%V>{jup1#Ky)ZK#9FoGz-cDCHdSY`XWiVIL-_cA3yg+bpO`@ zI&>SxLFFK5c30m5Zng7|1{mI00OU3{zK(LI+xAwbpT{c9(Y!5c3_qfrvIQ9dtDsCr z6d?_n@yJsCQIC|KhFVE#js2ayLYA2ihIP*RZPxqo@tpyuhn+h&{MHSP z-A1z#A1%OtKeXDOKF-6pb-5!vYb9V5kka1BKz-n0^{ks`A>~>b0>h&_4jQ2Cc*W-s zN8eqbN)Tnv8Kakn7>v#ek*Ys1JJacb=kNjh5WX-`2`XLUmv@0!wdoyd&?wk7?{pC$ zOsPcd4&C+2E6=BSPt!ln*k^OC&d_RdGfr|zR`B%F0$0}Ek|}-|!VaRX0zNCmq|8QY z@@;4+yJt+y zk94LyZ=5v!Ts(hx8JLi^0dG*4h{Ypl9)4%vB#Xf)^}6~<7QjI%(^t9D;iqI!Im6YK zQIx+AHWeG4J?Sc%hC(qu>;?fG9KKodb&0T_o2ZE- zfPyF_{eC)gpH%zsZKrPtd&H%@Hi;;Z@{~)|s$!FVAdxL7QrL8MlD>O{%6wG)gv5xC zY?lLNOnL8Myi#gKOv5PufdVD+gc`CEnP;>tT~oXJ3)PFy4CDy(wV7*~}Q4e`EXv z+O`rD@qRv~+h4FTqXR6oydR?`K~v&4BsJ(?4zV3xeulVJmwNxlZs$NR8JM6tov?jl zWYeoT-eG3Z7-A@bED(b2KnSkno#^ByT)t)gt4RUub zgPd_r}PDT%3K{pOwEx}qW+-LqgK%?^V@uhpW*fO zxKKzU0;NYT-VOJ3AE>eJ7taZVAfDT6>2l4#friD46(~X`+BEzvtR-Q9O(I$qQVU_q+5>qZ6}g z$^M~u(rg`b)4Tn{hFx}6B}4`(m1wI2)`)*}jbfd47<$`q)@KBljPPnn_!bWkEpCnJb(*>5|NK&7YBJ*- z)#5kWl<OnBf(kl6DFFL@CJt6!^|(Z zhw`I7+V-DNGewG9%be~rCo3GY*;hcpDe?xg4fj&!8-5~Kua8U$`lw-IJ2W43`I zdvGjZ3@O2n#ZXq<_vFQsy3th&<;WxO`N3G`5{o$axJ!S&xt!Kz@>?OD?bP2VgHZ@!hgm z!kZYfS(6U5NYC*J9s1GHrXLK`S3_onn-HnrUyMF+Bo|uuB|mz{enG4;6G zrgtj%W(!4gy??L7^7AP{;;E8!|EGqM8sb3Hu%Eyb_UO3UyJ6~XJ1{JgnZNakbaG&H zKubBav@y6Yd6ueV-bWMDEoZ?lPH8%wJvYQJMO0|6h}Vp}Ways{BRPVkpxQG*0}tgM z%3d36(;&u~(=>CJy77Vu=hvy1AJO;~FOMqIN-(8YcN>SJ!DkNZU!8;f_pG zh3l&v)6%7lo0|w^*!FDOai7uRs_rvf(0m3!K>05Wx``6aT?wOE5DzEZhjv?V?w(wB zN|a_i8_eYP+N^rKTCtrj8=mIagg`c6K5VA*Qvl=y0Rh(OqBn^K!J5JC;NhiJfDlqk zn5KB7Cz}fwf?rD6H;wHJgEG}Jvo~V>T`;|zrQ3#ub_ z5TCfA)BVQBid3^WDgy3;jvr52zLBl^^RP+xm?f^T051IY`uFcCIJ3qbaR3DDBS_Ka zFCzb4E*&YMn9PE^(R+e^J-yzLk#rj`XmeBJV zm)kmaL$P>W{U?goO>-8l@)te61JF1f9__-svmPLJ!C%YcbmZd%CAReU{F0 z?$cdz<{dT^E9K2jvOKWScP&?$={#nwMfCoZo9W}Sm1X~BoPta2sFnnQYA(t4{ORU1 zP@im$UAyDuBWYor9MZ!uIPdT-iNCu%q(4bk_Iad#%-?yi{lU%kp%L|~mp&^V-nOjx zIY{IM0o~apjnZu{&rluAPYkxz;9xo6hE}JMWPt#4CarnNVDp?8)@(`hfOi z-F3t*eUF-oxMWK}ntjgw+54M9)opshc~}F=C66($2I7*xE}k4WyW&ka7}-#rFeue+ zwZ$0VF+XhvVpGjtHH|2XRU5x*8edjQ)XZhi8EpvxG~fzfm&UO;1JzGiTMZ}VGopkO z08$&t3sYinG2gO0i^4w%e#E#uhM}ylLZhC07(?+6-9i`V7#hkbtFaR8bn_*n=ZE*^ zno$y2lkFP8hMnj4Yy|eZP6aZ`OXs9))Hc#C0fW@eb^1VVD-q#t zFWwB)dfb@He8ns1(~naPqvJuTE9jH!1!FK%1;t2A_)){;Iu6NUepAJrsQmCn5^zB# zLp*IE$0^c9=+Xt-M)Qmc4+1~+@uK8t`X zYY}vaVi~+W(zQefjdh+3ZRo3oByVO#lNlrsh zGn@5u#YXVhdcROzx6*^j}0Bk}8^=vv@riT-Uf+7pU5qhF?J(F5) z?T$G|>rvZIO4FM66KG(jwS?9!k^atzVI#x*l&zF}J^!rkszirxSj2%;K8Re?R*tTD z{A4TDS*%pezN|ggqlH#U?+Hb(TRNv1k%g@H?b|g1Ki_84VP6?&RbRm`U7}^;c^+3S z3|xwu#X1Dlg6-?0wtadRhG@+o;!njltD!=0%wYBPDZf#X#1FqV$4Xidx?q=17_Fx} zl{wYxa8ggg&v}Pzy<3WWhDhh}N*I5cQD;CeUwSzwYFKOGzt z-@|{@N~508qxfK^kfB6F(|fb+<4x2du~|#Q`8Nm9FC%_E9#6_E-79}Qclg=ozguN~ zzh=I>L3=We55jbH`G^e6DlfI#el!FDU+d}4ghtQaneWfN)t{2XvHaFmefzli;*bYH zzk%OYYHR?~P{YP{YxtvYQG%}yK~dsbC2X|ZVM}B}Ej?k#GF^2iyb$8#`EK>mfo~Y@ z`0F)`L-_7ob)C)2A9Me`9NMq|Y=mzJ(ghDHG791`=M~8JE0UN~nVoGP$~IG$41Tat`@rz?ee@!h_HQlb z)p~Gr0HmF@DH@XiNB#VVy=$JgM6a`lC6Ok1BiOrSCHti6r(;dv_AHXGP0jmKO{uw7lF+R(^5gCB8oP205zl3LT5L4|-vvB>9o5Btl=RyVX9( zkVj?pQL76ngt_&be2eW_sNkIvOxo<56kqGk4;gnVKKTB)`c?2Gxb&v&zE+IeAAN}Z z2HDn(Y`QCK(RW}S^5ZI+dy`(ZHgvL0gO*$-`AM?-yVOM-o2WJJs%Y#by4GgukP)7W zFgHUy94wob&W08(frLV$|4S3;FC&L5Z-RU<4Z<}7F01h@vH6Q+h$rzjnO&($NG(Ar zfA9D!6MiPw(r))S$QT?5?vu4H5T}+!yyAYMP97QRlecjr8bGeKA4i(mR9>_WkuzAo zIG8Qc+hZsans8(b@?#kh>F@7@Xr|(%nw_%lBRF|i`{KOTG&GsO+2LgiTn0V?Uc_v> z2gRJ94g?hnFeLAbc_^GQ@z#NcGi?(h!fkU9j~g25?$UI31O-6WMoJncM5tRezVAA& zOlUcT;ncEbn(%v{2(8DiV@UmQpHkgZShjp4UZ1;(mYyBtZ!x=U_wZ_?v@_<4vhehG zYA{KGp-25%MT69{)lnyR9?{y&l_rS%E)n_Z&(|({*jsIwR|B?%b=N$EHLgl*3i^~* zCSRq>2>*QXxv$82$uoX6l1Ja+Zlb*^!u!>p%4b*!W8Al0A?{WSvZopSt)tBT9IwI( zKU6KOk19vtk&;%8H`~VQwmRvG>hGvOzX$>aUow7%xS2M9yIVVFF4o|BJ_NsR++)j2 ziug7!J+sg5c|LM^^VneWPs8N}o(EBX*syMr-i!-*@7oZ|BfAZn@7AUZnkHx$fCkn@ zbq1`rSby*I5>C~2{s6jvO-vHzh~P`fYQ-BK`(>}NgjU9EFU3)M^E2*10w!8cg!k6{bxP z$wP%nMF%d=)hu-AiK9slMvA+U_jFDqPs}y*;y9D4V!6qkcc+?|TMKv}%&>7%j-eSCE^eHj4qwyho<1#lPgdL( zsnf5z`LdeZS#>2=HELxVrDk3QRVM*UNDR-S4Ms7dvuW^}K_`ky61YxDWEG92-lsv8^0wp83a%iNeB#NBNGMNwiDbrs_rm9b)t z4`l8t`fdONlV^ebz)!eAm~Yn=oor4zufK+NdgPg{Z-++ly<;mYQ6TV+LTi)h`vjIH+9R=LIsUynJ4WF-^OAnCpz{C1Kg*RBO{gYV ztg+@e7VB;lM~O7qbZDDp-ygW09mMgNzCWY*vQ>~6joJ*h5lxzPKHCVa`*F4ceaB(4 z6|rZ!m7I-ca1(@12{)RtteO!}^!|M5RMi3`Mc0vgea&318%f*D36 z!&M0h-PH*mu*z2Y@RnA0!>G?ig%suj*kXxkzq(Mz=>IAuKI1^yYx z-KWgs^ZbG#Tr$e}TG+a{WVCqEGg>2-JG(0}*DePCtwasLpJ3A~S5Xn6$JyU4xBpzu z2edR%fP?#Dir7K3u3++i@x8oJp{{bav=;>eeL=8`LCRre*r?COj`le)OXz^mO8>tt z;f226fWZ5C@`ewgxYl*MXMn!L)HHInU&0%RLt<=o{Z2JW;y91+eO_kf($x%3JGW?G zOC(T^`O#*%>&d&lUiOWpdh`FJ;WWVHIg$CDLM5dz2W^u_QR9ln&VJa2>%O6Buh zlrFj5`oQkZ0<2SI=ma-ZM137?QfJ8gm!NZ{&q^PZ9R&=pep^)6}0YN1BTp!oorl*4?GO9n+jJg^6hhX>3B6&yf!GmYqSu^sx-yDXGte zR#xn*?W?&c9;l(;2xdKYp}Wser8v#~{k-d3Yz*}_o5pe6^hiIA`X*nuAY?Tt+-UAj zENy&U!OO=%=QnZ>N%@Vc(Zp#kYeoeL@QuPAxVLDeKs=@%S*ox77+_l?>lI&T9AJH< zcktWOrMN-2f9K0sF86nJ+Imi#jlXXNuvb=Ry07pC#ke~;Wg5;d&)g0P``Keowm4X- z46h8rk7!MMX5*}+ax2GgKe^{yVe`&qCE=hu_+(d=av2CipMuXT%RL%lcL}Z^-$uyD zSS{ev2NQFb-FeWciZRJ#-(KdNKtr^mIkjLK~l6*_=ngKSw|L}1fzO|xo|vw9f& zHU{zja0!>GFml5^y_Rjv-Rubf90!&a-we$||1a+{jQ1nfY$iJixM>2B8(@0$KEW?% zQVL+UNPvg0_YVH3XvNLKKYmE5&-bzR`Q0H+K!)?$MJ+`f&jx*Ju2g#g!ltR|NVFc; zZ}r1TkI)zy>Q!pmgqonY*FM|y%W3Id+}Z=ia1CvH0l#$Y`s0mKL?mRx+2YUuko$Aa zY*>2-{j9lqMua9q)o#%@Z#I>z9blzFILgZz&!ZlHUtOt|T63RuLPSgEdETQ{xLjly z4G#-Fy8F=`=(mGfl?ODQm$L_j*+G6$!!@qATk^k3g!4+d1TSSXRw6y?l)=~$!T^n;_vRGnlDL5Jt3=_k>7PI}>5%{%6w&u6lv z+LQ33%+M2ar4RjSF3FRXYdJ(4pV}uTZ(WN5-q3*N$6qXEJFtzp9u{eJ&{MK*yfEb)f))Mp;~#3 zha-P;siT(Frt>^*d~e)8`qMEa5nd*k&4tPHtjW2V-vVkO-6hPKk|e@@*t#p0`y&)r zhcssIwot@N2D@Q%cNGr0zCc_plvDBq`-%1x_ps&-MJYTcZ|`je2z!0wB>h0KIYG0a)ty_@p}8maR6b5+w`9t ze@iss)g`J3oK&`R1EUd_h*g<7Yw`HTlcd;>(?Nq>KgqxLWaVhH1wNGJNvqJQd54Q->+nm1<8?uB z+b@8nMH<^}=#A@-M-(>N#qh7nmltgHZJz6+YML7TqS6;u77+2<^G-e!eCE-+j#8PY z-FB=bKY8;3AHLc!%M$W7tj>z8^yaL%Z)(Nfs6R z9~??{L@fA8CTUTcIkY}&+axF(bBpLOB!=PzS)c&~bfi>aq5*-UhCl0FH6%a@1E&6b zI@@S4@8r*}bNubB0{VskSustFKH6w#M${mc@FTZ$51qVW|mO3%IKF3OfWpH#qQvFj^|_>&Uy z9CZItyH5Y_b(sZq^Yn9`L%Rr6tx^{&Moh15LQS;@)0pXW{@iZSMg(c3dfoBa?zeZE z!Eq7II##EpCICOd=pMC^Gy#YZoOM7x3E?cO)bH1$`QJ&At&OmY+j#2i?$SfL>wz1s z`SCPV+Ueb%vXh$kO1g`SD6_gM#aV{ zOzZ8s`|676=X_%`n0b&@VW6TJPGS6~#dj^amtBM!Q@_uKc3W2Npm{5V(~DXAhJ0ue zqQ4b^6U(E+?HF;$%H$~a&@%~pKW zk8={!lzAO${sxaamLWwGvO5Sn7|{%u7Mrf(t5q^G1vUB~rf+0=JK1(sg*K3t zw6oh1WkbFrA~S=)0pwgEObGUUSm^Ww91ocDYp{?!vy7-)YtBr1e-Us*WH?gK{uG>WkKa#BG(0t;R_r6!B&T;GecG34- zE!V%3;2CMUh~6)?DQeB|+-ta?fVO!l^(nq*UyTmNs?%52yT29J)@Y5E!JvekJ zhEPH%xI&8~&7iUa&6`GP_7P|9-;!6^Tk`HJz4#rj+t>TJ7dHe2(WXZ3XWy&TWUz)D zBtc_T6R5AqM*kJ%#Ta1Y$+L2F+ZTMv1|17@Wcusz{kQyj0y76?4wEYFL-}P7O05*D zkJ+0Mpz766PAuohga(%bliJbQ_=WY#3ZHLji}(LSpL8#C@0M>Uhj?9mN+mm9cnHWuv)>B&RiK-dO2VW>_72@a)w3~> zk3Fx+wN@ChwgL7OHZE9$L+>gPcstsaNPeq=9CLFE)}CPH*}c23Go=%-QAVxaT(?dV zLLCp6j==Zh-csAt3Z61oe5@=S%wd=2_heDo94V-}bq4olrv^#w@ey--*q98Tc{6~dg zdw-o&2qYFjD=L5C6DcbE%OfZ4_QuALERD|h|L7Kd{=a#o)l1nQlvY$Lph+BOM=L@F z3hrs{%PBBlb?3^@pn8lXefkBPd>*uWvf8n9uo?t(5@=4EV3jDp9|A+nwV!mBG zA6}F^C(h)bF@mb_x4iJ$2~5ACBXf+3Bgh<>xfbD8r7`KrqyRq5Tn zFd9YmxBBYYcc~O~7Obe`>{~L|GI*$U-E&ijM)K~R=+U+rX?ZWiX-)#e%30fVB!pV- zoTdLU+jkE$=rfa$igStBu7D}PMo_GW@Q-#4I^8?hWYtfhQwPGFuYoOPy?W9ny>j`v zEeUP1D&)mBf-1%FIA9XVSvoJ7cMp&Hcu@*TGtbR@o)h0hHVHi1eq{F+_6v1oUsBU^ zB*v_zF&pj>G)PcuBzk5k1y4ZNz>l{d8m`#UI?LxMXV%+P<+FyWfLtNHX$8USq%1p) zz?elHJB2HZ5^Rr{U`C8+sp-maGr^mBklDUN4Tma$!tnL^LqSXjzY#Ay!dG?|5f*%} z!QGF`9_N)Qr zqRByX)QzEDQ;PO4g(y_Bid15|?miHXso8sM{(IY8=q$ZjGx41Hauuxtya=W;a(2>I zm-*n+;XePSs`MU!RKb_zn7z27ME=_ez=$MEhX-YNJyw?h`+Y5p&UWH&I0pDjv;M_t zGD)H*sjWdS=j>9= zurzWxjc)d(b$U@$eG)5HLXerHZvtk_56b2iVJPJ48tjb3CAG4+$@`wgE)BdkH1N z%=eZfN4QQ+l3|PaTxN##nsIx%Sc9SVMKPC!aZPDo)leqN9F|sVLsnQLsoIM=Q5*55 z(6smfMhA7j?F+~1pbQ8}geK=}?S6eKwF*QhwuPwlC7y1Vkcptlf|##kKJf|Mq=*hZ zvtT=Fve>2|PJv<#eL*V4pS&J}YOOK`7)X;p=zHON29Ef=?0!YqDbCcGX~C0c36qUg zs#v~d^S>w5+u6sDNMU%vW$A{>zdSZ$*0`I%%BgQ6UA`~$=$8W5RdxH;j<7M*`SDJG z3)h|*Mg!amJlbfFeNbQ8Zo5f?u|HZC+a(T8LL2kzA{)%~f%{J3eH3Yu8uaa1%=taq zSobFStPRfAKk7wXZ!x8JvtEmX(jxW{n0hEZMR^Bax3sHDcy2=IiA3PC0tZwX_ZTpB z@%e6#Zk@1`8OYNg&IdGE0%Sg71PXjs5_vrGcnOj3BgZQ}tJLywq71_F75(OaF8rbnXG|xgG$M1ip(*S)C3i0`&bBD!soiCYAd_3jH z_r#2Nt-e60Qc1ZyXtP`n-ni(f)X4d>JkO!d)AS#mP7=Irz5MMlzt&Se=U^B2+aC^8 z!7iuRyh&j<(L@i_8L`#0byI3s0+X6My4qttu>-qCHKuvd(qf0b@QXF2ZaDwqMN7{O z#j1h7&b{E~xj#hEUz$%VJT`!ptLMm z`Do2q$vI=@GGt+1t?~ShV(TJyAaTG?xJ`pVPYS(>P?xBvBbk@N=JIO|qYm@0dGOel zt_spGMmCK@L=z1I8oYJGceNc^e14zrX@lOMwJ7Y9Of@f1x$)ozu;PKm_!7k!_ySd>nyyRbCH$wF~iDcWVWgRynSwa1pa!& zkP{Yj>MJ-GwmSG3d6U#=jz|#{oyiT}dbfjKu~nkgbp#TmnEHxDF8G_346F}L;mXWg zePNlJAmn15w&oL&bFyz&tdx&`iHc0ZAd-rf%IZ9|L7Povo$;itk$cT`+}aA^>wd?q z*MrN21|AxhWR7m8goc%F9caiy<_55rGu>7RmAJUx2<~qQ^3HFlm%tdE372x(Yp>L; zKk#4HKf3O*vw{m#D^l2mSFA64$`kwBCy=zykt0F48A0wO0$boIh>t*VX>cj{`U=sYepA@-Tnxa2}e1eJ0J=C78SVbUS zBq_eV%O?Ftt`9wE2unK(ucqD-TCpkDqyoGICUe00v3J2G;8I-n#H2Z~ixnh~ZQknJz_6fjq0CSJJt!G6_$}D!^CQ#_ zH3n#Ia&S+W47ztv|DlheGNh>TaLA)$RysFh&FO$`%aNfl%!#)(fWLJrBwX3Jvq$cL zI-Jvk^l;!SSTlj#_ON9bUqg+%G>soIE6hPuItaZLudcERUIH)l{VLu2M+ec2vm*XL z63j6{Ue0#A6v#qEk8BL3q6M!0NL?qyT8DYcx&-q8Z-KW}@ zt(T4RoON;!B;0cAr~R-X&ACo2TltfAnWmOV?a7FOPgCstsj~P7G^l1FpPkmTNUPfM z+F17VnS%8VL&*qbPkVvJAi5r(_nFtIYK5P>F1y4^1D z_jI7BDqry%h^L|X3tD#QX9%jr{+(Pa*T^*+A@_fDvw^!VfjZ9TBEiR-iAW^hL}TO6 zt(vl}{q?T$b#d{+&pnKPe>{2n2<>S?iO&YCwIK7u`ai{i6P6?heN>4Nh%uhUx^%d{ z1mIh|kl~n0Dq^xEagg)Z5RHiRm6E1J9J3cY>&V6(=_{ewoUrM2#BKpzPcUAv&aS7L z$?9HT`1L{r2ZSNR=UzRl@Tjo9*kH%=X8ns-=aEO%6Z;>h9_XBy}F{`oGSgO^IB`;;e5lE z{r3GzLzTuKYWX=$wc*@Dk&gsO+8*XfSkw@6(454O91!Qy8hgZJ=b zfl7*n`)S)WZVoS^Id-=pnVF&CQx>x$W8S8_Ztg?k8hC&Y#~Wt;4mPQIIRNq>yuqyU zJJ4$3`AX}Mu7}xiqjw9YLqs*nah|^KB$NB&C4b6Sp3{_brVn^dtEO?P2!XRB%jC^= z-c2-y?W!}7DYAc$-TM*y;SeZVpcUYaVpVMrcX0&$FQ&i=?$cg96+Nh7ep6v(` zSwp<~zJckvuPw`c!OMHlP;8&4125POxlYylvnP$@uC@rywi$r{MPJgnbw~Qq)hBBYje>&M zH>L{)LUi}y_5X&oA)~tO^DNVOqiiUaPK}wCq@IT+IbI_^I6%3!2D+`W1BnX(>jy5A zYYvuB@;l0z0gQz%O^apFq6nG=i1(Gghga1Jhb11LtMcK(GQxJAvj<8kw20|<7tr_{ zp-zs3D$bg(1ImSY-BPOyvKg_#C;JL<&dgK#PV(Xol83{GBBhPw zW}=>=swc+1czfd=5iX5xu0>DIUM3a{U9_*LUw=`i4<1_Ez1uDP3gbO0mIcAqDQzk)}V?p+g5v;iE4C`sHy zLz8g)<{spnl$76^a>g!58;+fmjQqC~cXR3iw-m}N9M|pAe#fohb$MYBJ@Btb2SJzH z+6HuZcw=LYH>AfzJPjF4#rC~9_nC6v1=In+0W9|S{O9k%Yld3;gxB)Lu?%_tT{Pgx zf?_}hHM=;MrnjiDUB3suvL<{5e7?SnMM<`xU~DAM$}{Q!EvFLH8j*+<;y3gSKCR4w3g5t1zqe!U(QE`T0^VF{#B-P{HuEEcDH_^@-_Q2Cj{6rdcwI>ao{hS{FgS zPZ#n^guRS=BvuWhHFy)d^ZAj_U8V%x>k#ix?|*M1HptYTW!-Cv_RVAjeMl$%qeISY zv@a)+>y-=H&b}{5EoA#W7+*_}|Mgmlo-d+s4`$rb{+h&#-#5jhaDdXbr6?~c|HF_w z`9^Iu2Ru_k?IGtQ0icg_(8MUoqMuDz#OPXD!7FwVY4qS`y_lIlmOb2Z{m(X!OXBiv zeE8Z}2S&PJjrKwCp$r74hKyeY?~R&0bHY?z{iRCY%*(*`WcWE!lt?^(DnH4!3!^LNgU0;PN=4( zImQ1w-49{RKtm#f*9P5b(77T>temQMmUY;?y9?AKTu=0vHsi6$8PjegYVO^<7qhR% zH8S}4_g_ETdD<9`v2WJKjn)z!2e@|>2{+XIMb!=Tu^Ie%&@e+B^ZRmoTrDP;-XXtjRw@M?|8vSx z{;*W#XXj{at?kjsSI4^X!&!}9*nn`t96xxECCnmzkmJD>E*2u(+GO-ExTN}2tJRA9 z=_Fmw0iPkX#@7AWS0#t1c&hOrM2X|ig1BxZv@ugUd0u~f&1VDr+g9biNAi*t=rJ_b z8985@8w*mJS^IV2=EawavMH^9LS5RyV85-F`Q{&wCcYt?{L^1V@_J1sY->c^xDw0y zAtz-5x^T^y=PPo|%!0!-VPWuP`U#_NMGf{&#n&3%Va7{2O}MUl#P&JS`o#?p$BH zwQsb;@jx--cJIDI*Az;UgQ(*Np$xv|a^;QrLK+bai+DXVI|m%h;H6EF`7=4Bj^VCn zi{0^0$y}kEiP^>XKVECdtP)K&OMbw@DH7ufy~NhRgh#rjq@4^YswT?vrntq$^IS?7 z&K|bz)unqX&FggqFrrrqy1w&6ukScSG0jO^Q6`dXa_KYsTVVT>k*UIKv1T?vEnsd2 zBW23e%mf)(L;PxHm_4BGHxVRH;eTeMX_Um~octK>!_(E_oZ>ccH^%JLn4o9vT%bC8SZ+c+gf;3I~KP;VfSd;G?_AyZr5$POC zDJcz7UxN|>rD240j?pk;vj8Qf8$`M#M~==hP?`-kV1&fz9^m`@-uL}?$Bykd?&sd_ z>%Ok@{G9J?{d@LQ*?2z+hS3sFnmJkwUfteioYHcfl-7i$`c@ADDwrg;6z}Qhl$GQe z1q1s(*JY@LF=e`HUI`JNiT1ICk0{R1P=tA-Wc@L9g+QMRZ?o9|t>#y*hJ9|ROrAYU zyOM?U{@AvM1~k7fZ+12@%BIB$y%qk_eyHT*1BvYK(X#xJ`{6v-o8m@_EzHCVQ)`AG znEEvt{=wKt>IL{(|LV4vO3Pk3k+%imi2W)2%^jTZ;>`;=Rf^d_pHmGf-g9YEFz+lr z0Gx-?uk>(}9$4mk0s9qsgWm~FL4(nv?Fr6pNq4KrX-oiD=c)mkRO%5H_Gi669t%fC zp(DpXm=x8FPF|r&I)7C%xoy8b1-QcZ4;sN z+GtL*jgvRy{~qfWzvS|bC@u&MMp>MM{zpYXqT_Yy;z@KcN3w|9+uRO1W~|ndKxp_o zAX#H|rwBfBBWs3p?q!V(paOT{qgz%VxaPzeiI`a|;eC}^ff}EZP@Q7B&9|LsB0`(! zSrTG)?L&Y~tCm|5_Kj%aa|zYW4bJg+H0;ZNHCO0A6r1-It>S;|Q(;lMf+1l`&^qw9 zmIY?fssf!9ku6VzKoxtO^ZhRRC!!fRYYU`i<0kUR!=GJ^$cG?3ABHZU0K$s86YW8#p4J4UsrEHT2;6i)jLgJF_J={M2T# zkHkhqTe6$|HB~-)<0540(^~efr%27mOE5JRG_2o1q3Yf+xNO8DdJReWIg3wQ>~DoT zvFdkckG9_g?&bOguYpZ4Hn_|$5~cgPej6geB%ey9w#R<&WZ-g_fz9#qO)`^Ewlnz! zN0xKm*PiJ1=G=!T)&5; zsUsRnRdHU(*a6Th+$2sg^(CJo4!X$LqraGv_Nl zH;~u?2_6r5Sm;EGD5eJO^((+OSiwI%;}PT}9! zo6OmNxXm4cNz`fArbc z{~A^M+B>19JXRgQsyqn+-N-cTGl|BA$vArhq2fmsb0eU5ehkh#$YX<0F0Da5QTkfO zT#e71L0Suh-h0g4bvNL$ZqM^_6ff5hN;Dcf0PEK`YAhmsOh~q|DW^}v9(=wn;QJlE zMzYx7(OHZ?f4j3eC2HkkKZyj{HIN}~v8%9K3curDCQz+xbpV0wg%#)g9!XiSHXQ!#9N8wwtyuw(!2H)*@uTyg4IYZLLl z(|P#FVe$)R`zxVL8PPPYunQf{979K|_yJfKx0|v;iGi(y{0nHrhyQ>k0Ic8?_~m;v ziijlI*&7-%QSlKH^(uBh6F^Z~l1_!|==#M;21KfnQ@#D|y$ZjeR{s$Owm0=nUt-_H z<_cui%)YD{y1oDOL9cQ)D4<+IhVr-XXNc#oQ-nu_9aYnl`sVAWsn>PAB6mE}y#JtK zB~M==Yf{Hn5-T_{OL$K`YH|y4SBf1QGMiLiDJXT|B06)-hfYABcVB(Fe)UiRK`q>~ z=>@L+jTRmsX+FMhM)hTN`Q1{#C#sQ|erRyB*n@p^fZoyxYr;Ylm|50`#j@K5>}#?+ z5(01}C9qW{y}96ZmiCU>djZFVrWnpt$)pY5rl4hx_~3LaN^a`Ci>>*^{4ky9-rc+; zt&$?zEMs2@hZVqqbo-cl_eW7=+}Z+y*C6#o)i_TccA7#T-@stHqMm1RSG&~x#2%3~ zvt%!OJ5=893cmKCi4;WIZoeXR;@*f1y3s@?<4WRb1L$>SVfoMU&itOv=Ag3reYd|) zub9YDN{LHGAMu6Q1j0nGsc>^M&H)&M5awGP_q?(W2J(=XXoB|?lakFBOF_HQqIZq) zE*$f#Cyf;#;&C_siNuayw`o?=(eCUtw)wxQvLh(BYWk3az2TcGizn?>X%iQWY5jejkHM}xR=sh_yH9RiFyx|DdA^8K^db%Z4ADt9 zkEUi-cZJL+?JfEy*~MnwriEE{)iMl=#pCPzUuVqb1v=*Y#vsr8C$j89Drl7sYI^z1 z9xp*(W~@%7X(_*T*AyhZ3(d7V!Vm)VYxKt)6OJctMLPD@b7;MR(cJOZ zSWoeCOfX+^1e6Wej%NRgzQ&(oEtcIfL({A6!lIV|5<*Jr>F7U$N;6|wP=UU0)8}4w zN=$?rQI9l~D7P3If7&)2Ij_a1dR=EqM_`W=(}DR^(iecpEz7fTS{+eRWoK zWePpr<&C6m5&SMAZL08jM0@-Ma^4%8n2$)|!*kHz1A8LnFfv2_HpVK$1L;(?>Na*F z0g3La9-{z{NCglop4lcD+u0h2Z`sj_j$ACZ9IRP9Cp%~?oj=h{&vTr89a+vM@Q(t` zdoONJO##Br=`zjxMG#hfxxYzjRX7mq*vobe-)qCY?p=L*B6pPI4CGMA(6)}( zbR890eY>BX?J#u3-Yk$*sRl6r{bPz(>@Bxy4wRmQKjzMAUDy8AikiU5vpJm7`I_sX z(ZE>C82{2ebl1cdSC_W_G+SbM_|%FN9a`$-hRzvyAfeuTovnqmv5#7`(|}v`y#YA` zT;@X>T9^B4SkZzyNd(b zZuH;D=T|LN(aMA-OKcM|DfYa1<->Oy{=#!gsYJI*k2|p|<+bwG5E92YLfV$MX8#uX z%Gn?AP^;G+Q{p9X9oZ!eVD@f3QZnU z3DzyeziFPx0@VtH$?BTi^d;t803qKqhK>a%tfJA4k|+ zNG>v=cpVAP>fS=P!>1^wkYQN?n%5`8kAOu#1?BD(l1mST>iW*LL=^HH_K051Ubg|? z0edkEE^8v$XQ5TlFt&W@SGXNC_Gi$~U+Y~i%N_^iprn<#B)>$EyZNZqu^+$Sc(97; zKJ`k{AKa{)(eR|1x;P#)e5*30HT7_OLp$r2FG8a4@*%uWnfl!7Ck06fPAQSxk^sk(=CWEm1Fsok95;AYuy?qykE zbiadhEmb)f4KcY3`5+znxr1Rh`6Ih7M?W6z}N~JZhDBAPk~=; zsEgb6ULA)TUOY;v+`iWQ*w*5WYZuo6Nc5$pkecV1+UoPY()aa8cV>6Goc~eKlm|1B z#n%zcaH{hMsNLi)$ZNLNn|q63b3M&$t>{Z;iw9z2(JD}3bvyHpkMh5~qLqFkyKI2w zC%zGD?idjEO?f`)j5DWFqL^O!u@)7>BM_MB2rHenb#itDIorJJa$4^eu4?W@%s~5F?=EIYA zvifpteyT;qt!CDA2Ac}EZ%B78>fpIC&%k47EML@od{_VHvaP)~oeg(&ZNwgF*1Tcq zz39#qf~t4XYWAJc*L@R+9evCsg886yCXNqG zx;IQZ|9aH49l2U*lRaS6s!4{c2hr>h77(Ea&BgEzn}vR36*^4`T>p>xqwAz~^|i5Z z05kO|%bDpoo8CL20n8f>qM3Px(qzfoYblEqQD53|aX4!EBV`%MdF>>y@&rB!-f$^@ zFv;g)0OOQXsODwU<7XlAlNGx5p-1!j1$_K%#w>5lq-udcmnAh*sB| z6o>chH>jFJS(Ih+_1orf4ux^SCie7r5&ZDk8OUr67)|MK(+QWDwuN|uL!wY>NooYv zkH5ulD8dFXrof~kcQI7CVF!R)IT}W7^P~c_2d@#tXsr#fQYN#;YxM;iy-9D)7^vjp zHN8(`FbN%8yS*BH3q8QlHw>)fUNl1FGq68Rm8^QSbkJcqtn}l(QS`Ek8{*YipZf#D zI7{#F4PX*suq*y>W`X10Tw6#^Q=DSsk=*rQ7nhE<9TOEq(!qiSs$t zw_$mqtW-yhJb&;l&wh@mQzsCUNFu4Br#UJ-VVl(6h z7nEI@FM2L(q1J#W+;8beL^0`XXML!Wy@1!PG^HYJimm;nrueC}wMn`^K1nA<0wD7RWjkp(XM186o2=K~c%YH52! zfFXkx+M_x6W*jv9ABAT?AcSF4s0~*(q*%!Ft?B;0=>Os`Eq6ZL{K{B zULBcZ!{jU$3F`7Jzork?{%aso9eA?!ena;l9pNbUF`13pw?8ALiR#*{>^e=3$Qjd zgzo!cg$fc`P^uS8&p&RdD~^!O!e@b14qP{4?IZON(XB7o)1L#89~j}^Bs!gYbT%Op^jv1z+uUn) zAFm@n5bhun-S=yF-XkOUrpxc*$1Ylmrm}y{o&TIAU=_l=;RaidVO7SZ`zW<5>I(A z@8QzD^4RusmEdJyXy#|C)5XCz3=WNjxGo?q@k}~#Pw&m{N0u55FBUgx@CBwg4+e6E zvLNdxW*^6@8}uHYmZ;2Dl`sN<-mlw4xq+#Bof*Fw@)l8`440UG;xc&tUh{J5lBNSo zn3l;tyI*N!D4&wH2W31b)cvFQ;xR?O1L&JxFl1^OVL$+Nbz3%@OxcZCE9R`^G*t2( zJ0W~W*XP*XNC+YX6dqfq)z-ztD3FiJly{@?LgcpHMZ^JbMQQsh(T}yt>D&LGPHBlP z{&110VA3}<$^X9(pY*?t^uP8B1T!4GNp3s9{9lo3Cm>R-{eL3WpUy$(dopfwFM~%Z zhkyrtB{vCi!a%#6orp8d_gb=+6%-8WM{CD$yg09&Ym-*PI~%+heG1%19i4k9pxMg4 zxed#yVdT2U|0sC?0#@oAsdNI)Uh( zVmb33(@-Dt{I;;usRxG7ZVG{oK)#>yoAf4tVBEQUtKlafZw;9JqhJC8=>yUTqLwXn zB7_C1cQrIA2qt`~-`{Hten6=2PxtI1`Uk2 zHr}}SZ{=X;#zo1s)%Gfuz-9<2an9nY-q}j_@bktQ&d3ClS`PAMATL!)IkCdk+fh~# zfPPlU3h`DT!e4t(zL@uE56UtzHTN#z&0-7pLd-eC%LScY`H6)9extgA0(4T446pGk*tZkUS<*Z<88*kNk*KF`>p<w96_r=#q*=RSgS1Y|HKey z`9zd=>~$C4>kk)xH%3Y>8N7E630+Ku?~leSOO-HRU>-z(;_OqT+GRT_)0G_#*t;?F zfy%W0Mh110wczEs8_R7&aqOOQ9XE8Y(|&g`bYk-)o|MX&J8?Va9ll($GY1rEmUBN& zod>n&>gYY1G_qTpR|=8TA4(e$5#+i|jI@pYckyCFaw!tRpQ4aC+~x;-q4PK809+~x zx~&J)oVvXw57Ay7a3yE0V*fujq0%#~ThJ5h8x znh8Uv8NK+a7jvj`kHXDI>uVrr{~C8`F-LFbt*fPGlE`?;WEmMFDn1sx$v2qT){N^N zKF&Ak2C2v(Oyj2#a^&0W=9p6GDzIT0Z_5q*RV*Fb$XV%^E(<3(XtlC{w_sVPipqC_ z&<`$8N@kVur=H{(Yns>4lp6R>{fgab{W5Ncqu4gtHJ!%Ua(29)Bg?&48{UipQpd~=FyU1K}>eiIZ1L&PsPjQGT+Q0tbp^ zZ42YB?!w*j6-*bsj@=Qb(JFf6SJfVDW#5j$Hg0p#IB=|yi15(;6$4u>g7mW3R-aCa zhyEme9HYl-5CN8bFDlz(|IY3(Ndz3%^J6q@u!-bwr7?ibFJF{a#*Na0JnX_g zetNd&WK-urW6= zhcvo$Wz%qS4@1*KEjHA4K27!vYCeicG;h7BhB-Mb2+pj{VlZKtJ}>5v zoAs!1vD1dv+NG)PGY!0NmU(sxiOz#+D|069J4`zL4vOIoUnckx06=3lc*0J6Duaxoq8z4@-Ov z_Z#igm~+q&>U~_zl>ruVp>iUCo+V8xlnT}(h>MB?@zat)M2-#FXz=y&i)^2zwlho) zT;q-mW*ia}$vTp*S(9#jDv2|;3DKSaTUNEa-;EI$`+T^PO@uO;`15x(g?$y}v8@_~ zEM*0!v>3m*+P&HFy-43$o!uxKKHOHj8iH`Dq{cgEF*doB21~D5H;_eB-69&VL_SV= z%oRUOWAW_pZzOnvSz=7Ndb7YVYjJpvRY5e(hKbVxpW<_)c_$#oIe0kV^>=v-q@`;$6mqOi)`SyX}f+o!Fo3>IaJCnRoE^XzfMIqA2S(RYa3KDp7mGW@IWfK^-JXy z4^RC{77WZBPM!x-%NW;<3%N?-s5KrXJ^)LRsk^OV3Nv(W?G0XNx`ERBGZBHL4bb$8 zq1S$|Rd8R-VO1piS=x@yH_IJ8z{iHTdHKl9AKLw_K0n{m1eY2#UKJQ|>zJJjO|j}3 z>RQBICAV044irY8z65cf3=jpu$}}fks_FWT8P9K&Xn9%hxlufNH1v_j!R;x{uY5}y}*l9Q zjJlhqzDlKQv2|}NoI!fy*=BM5^v}9kZ!`HDc8Rr9i2oX?yygSkbV5%a=3v;9Op&-r zDYl-ZbU%p9En|u|aLt=;x31fG`7*rgmb_e0(EO z49ReSE$pfv5WJk9@TZmz7RB>|pR9n_RNY)ozdv|ub-%|ti2o!f=Nypy{5(Md;g)~T zYVS+}n%x?lR3pC#!_U)Sx8Cc#sqhLPLyk?J&E-YUCFWSh5B3bI#YbQ1^4|D7*6KAV zA~ND-=k{rxcEEb*sN5~;&NgJye$vi9_=n(+>F(&frQ^l2H9sv$0k;Qy$a;iiZT+r= zq@7-7b+63b^O>dWR+V&cUlDJU#7l|Q#)xD#_WY$+B&O6D9pRcw}Ryx0SE4Lt^The44C%~I){;}H%Br&Vq=)A~#jZ$H5 zqgqhUdN0it)gE0zIfbQ|?>DFOuY6VXh&@g#nY`w*c~tN5k0P%!ne_)EYi=wwxb)j1 zr6O$mSnFkx2DC)&wj*RIbl7}X{&9=??s)g~y?g#VOED=1UO>r*W8-u&@E;c}=|3uG zclsdx3-@dd z7zg=w9+B6eG8byQXLo%+Bj92-&{l<^#^NQy4&vhA!^+^G64&bzyh_eM)PGgPc`&-hV4{lkl00jEe&X$Fm3A7vpkstaktB& zdcqxRHS~!gX0Ty;@7lh4r%;ITbR4XFZM0}CLC*E_Pi@bn6`2u;?BTLU9z>|B@;-enlh9FB^P!B>dMpuRZmMJ2aP z!EYz6ySbfhSKU}4){BBL+5+|1Brr?Gb*Ci8zeLv`NET+0%=M%09RkU3!FW4ab3$t+ z;?W348Img5(U(>I) zrgZdMyaBKk#cM{`@Bf!{%moWUSIKKr81jdIUGQKqlC<6wNDXDoXf&I+B+edw0~^nH zPnJ9XSvFKN-eP=ubK!Z{P-cNXQr3ICepg$G*f;1AI@tra0@zFs?#3R%WM^c>^ z$3Kd59@<>Vr;&X_uc0h4 zEqSV3vx%kH1#jc%YVYpWgICT zm$H^bPy0;S^V!VgLxfS{{}u=Q*w=Q4;+q(|BLk>E}c0iRc`5t6Ut?xvp6;V-O5f zj|mkNbNzA;)AJ244!gw%iZy&VN5p>YLsXjkRvNBKWzE_+>i5aXVKr7Na6(9#xB2nn z{R55lZ<22(2VLJ=Vf$jd%0*=Rz;2-L^e}DFIE@zu!uS{@OW1&i23?k?70x^=A*#0Ku0gka%PqpglRiyx@T2LQx?ddTuvk^ zPky_?Aigt*7+f1YhaaBonrAKf0#j9JN(j+kg}tA(Vzl>q_CwvdGdd*wtJ?r0mHOxlvZ+Pg#Th@aN1XGyEH^cpf!(Qz>Y*>9S^n5={iLrrTd5#;I1|Fr^9%o{ ze?LMQj}iV72|gZSptyYL>Wz=Nh`5IJ| zEhbjI>dSn1>aq6v@$d2?@qxQB^fF9_gP1BM&6A_bE3#LrvMz$xk25*Smpn|TOS>Z; zAb!q54fk@iyVrDi6nZYda!o}OBNB$Z;5+TIU5K|ywKsh-N_B;*-h z?vU5}@hJD>h?N-_Cwr1Wfb3gEcO|ddZzFFlP0R!pRkRkLK91<$)qLGuHZ~of!b!x`?LS;(J_H zP5nVqkEZ$a7;tK{7J3vEBp1C&7uwveKpE%TNkg7SDdcGp);nXGp52AC|0HVnW*%UC zpgh0(JUm?U69j%WM7;?5Nb#Oo1a|%I#g;SJfYG;C(g!lcrSi#!jT9}u6+@rPJlk+X zW5i2;p`jskOC1OqkDL3#30W?IlWpNnSB*o1T1XvMQ+|57B&XVB+Gev;!r$t`0q>H^ z{pzP44I+4nKD?=jt{;CxlV$|-n__yI2a>+!N7DqIxEHH|A&*03Bi%hd|ITu*ugZME zINy^?Dpe+mC;gQSGJpt;E5>b)O%}WRx`n!cC&Wn?TxAoGZr6&EjKXH=d4`Y9_ z>5Ipnbw9jj#vqKNo*I z=j4|b6wV;L#gM=)S#ngPK6J`0xM$<`o5rlvA^eoB=X*1JTGtr@b-BzetvxD5xU9VN zw)>7#VajyVRK2?O=w+`_F>_^w6tvFCy{R4VRZ{b_!#%b(z0I3jOzUF^ka9ygl^=vC zeo0+P%G);w8^3gG$}wnYh|`jCyOF2zKveSDO@b7C*%zx+kLI-FYSCzT*sup>ht9eB zVGQmPujR6^mBi%|^%~>jWN7fwrUhJ7E}Z!=vMi#JGIjir*N9TKTy$n?A-J%c=EIqC zn2%;sTV0)FS*6fKh2%x&>?sK%DSqQ())S%^&BF$(03WUF`c!^X02R#OTHC&|LSD;O z@RNnSq`KX6k{mC`DCSs0aSij=#zB@U7g08-^rPT0m5J8wDbsMbS4poLT|RpWHr``9 zj$l>QcZ-iJX?1aK+p22wJIy#T_hJ#{UbTGS7~mUEHdD-xQ_02QoS(irDs~Zx_X_46 z`bQy2CDnYLR*l6>j9ajeJME0PSQv7k9G<3?k(QNsbYf^yY5K%hi(}tv!EE4~?G3%y zVb9rY%LJ65g{fm(J<}kP$%yG0ki|Jn+?={=dCYjU!q#)U?p8l{D0N4BWiDJM$gt)j zTY>vtQIkTA+A5l%$xLuM6zuL#^PoD!{?7gSYi<@31$MrFi||L>PnNZtGt2$F22o-` z&Z8)r6AAE+Y7ECkPwQE5*rwC6CHB;b^B={NpAGUqV?26|s1tSXx#V4Z3lao{1<`qc zjw&)eyoz9s1MjD#Yt(9Q=Y9N<0<#)}v*cd$omj1Kalx*BQFa#n(6rJVoR7n8xVJyT zm6-H-j>4RdLSsmb1e8G^dPQ2S@j3ex4f&S;m_aDST2Wayu@?6=cC}73uPvHo<@*n< zYU)8l`i|Ai5)G-mvK_hzEy=^iC`E}|uZ3mn@?%PEMrF)|ehvL@9ZdX|#uSp8LF9Bb z3nsi93Ggywi|}g@_V8#Es1)Hdxf9gD2Dkc5C};Hh4qkIzS)VXD7WgkYbl8dI=EM!2 zQ;HFI7(VkNM!3v*ZvgsrS%2Sx4%#GnBLfzjS-5g3bj4DTZj)CqDtefp6SbM7Q(H60 zWfyMsXrN~G{i6g2isLQcF~~tG=cGD6`B`h{*Z6*d4Yvfx(9@a!{sWycJt~Nn17AE+ zU$%>FDR781%Vk2-i=_DPJY$U>Udx+X;?`P~c#VNRjb#QU>eRN&E%zoB ziwli*xwzpN3@m1jdb8I%vlHfz|2p67nMf;YFi2C?-#3-1hie~QATAueQ?H&T}leEu#*f~y_9!NsFFj^dAK~ z>c-4Qme>yADDmJ~)HukI>`R!qTR{xyJH6sVMDyI^h6oML7|>9 z^A#ElpA7q|@V;%Vr5wB;K?PSnF`5^y8~L)S#4+cOut1W5*f1CHAd-r=U%;BqO>c#S z8=13A&M=%kpNyMcPL|OF8lm$EfbT!KFS|N;C4yJzS@DBH=3JIQ#)!S03X zVVB!AcHhc$gqMKc3E$~gH5@TC~$W^kf2*hS!EM33jhse1<1&WxmglNB7Xv2=v@BA67Y zcSZVu7Lp_`_#Q?Cg$`sWZ}&62fnmAh0edzzdej{hh;v+rB^=xd`4dS-ipD!S;w${m9FmRGa%sZ z`q^Hy%)-VS{{^HFM(Kfy*Kzq%M*nPgd%-QEqBMyo=)KsZdEtWIXqc<&Q>P zSG9t+fqv0lfPEVCm2h|S(WrSvd70bw>b370JYH{x?{OqnMIu|8M z9I&r6QId@0p%{iGBaObnoGy02lf18~2Yj)X&;UK^?k>AMBX$&snjFr^qI~!|BP(SC z3nbfL3iy1l3<-K!uOJ8{p7^}=nA1O&U2Ws=uc$2TY9uG0znG2sM=_*FUWBJ3NgO-9 zi#m!y4h!RPDgpx+Mc->&-z>yV)1>S)Y;0Iqk#&NccM#p%p+`rioQ(_Qjg4>CK2C0t z(AzvU$&TqxW_LYr4dYKLLx?AGi?(+$3kX`7rUa(0up19a28xo(3A&5Q$43jjGH-pya4B}FMD@wZyq_vhe`w% zb)$598v3?&47&WQ@y~Wp>7-NELVX;^-utevU*TDqnBZtgIel~8Uj(1sGi$cZ%t)GO z6xS{x^zt_DM5h~|CtLXZwr|Ut@9~h~Gt@|5x$%6Kl3Q7nc@Y(ut`qY%luii4xh&kY zNU&eyIFqabgq2UF=d%Yh3soYuZ()1oj9E&!y4beS=l=#XVe~UN#xvc294CVvdJ#LunmM43HkwWg0FLw8 z-Z4TQWq;s%np`0Ju1`4tg=vU(!H8>qi;edRu}@MYr(On8S}tIXvJ&_B&lzytx7unh zDNnj=4=P&dP0M0pdh{}$)Jek4dt@@UhIYY%O42`11)3X( zm#I_cJJ6#KyHlHorRG}mZFK7voDe;bBiMkh3-)XNLG+!clqXf$0ZXKD7>2#10vBG; zvoE_Ymc3928|}wMz#wd{1`@u||73A#XJnOfo%9uVKN%(dAlqHFUJk26QF{L{-Cf2a zCY#pHUacH$_wa^yAmMfjBRNSI_n=;1^~6j`sST)$;8f6%aR0x9yS7LS+bMop1jY?VAewGxXq3jXoRLyRxx6odnNpBNybw(Gq z2#;iuKe00&y#n2n8~mB)Q{`YJH`hJ&-hffzE@r@}tjLmx@H=k$peT^er@9)Y z#CwvvXmB8-#4}YX6_M^}I4sljUB0AJAR=a=#|`M07AhcilzM*b0Ed;<&0Y;ZsTK=x zXMS_ZVEG3fGrtOYGuUGcyOMq+K|;{gpriMu&dYbTfBNKMv8AORjYjaX@%LHy+D4o4 zqJi=#D5L)|c(=FFt9bo*-yCnQfdUtxQ98P}iIk{kzKf`EpkjGFfINyug?cwMMI9`E z#NUt*uf)>!3n(wAPB)KOSw1cAi1)0Y%l304k)MM)QCW2dQ|Axfg z$2zj2d|#r-r*qHUsNQ89;m~Tz_I0H;X4MvkbXA;5?kkMSKgoXxUQROK9{hsl;58 zr1*elXkuH_cv(K|-cZ{aL(m$jCxXYNnSaILlGSg{=M)jKoa;=li`I?|o@?_d`6xePX#AJd8`|@rg*WsOjaZaie9YC2DisGmmt&LK`qji3L zRe?eukfIqlLSg5piW`Wx6XlW|!rP)-!X!wnpF&MPw+iR-*Q?dFgm65=M7;`RQHN$0 z!zayS`sLm!KgE5vPg?pmGF6fJpjvlUolU(RbeEC>l)(vp_fL7yD-!=%z{`5a<5hP` zS&HSbYx&@lMlvse6Px@D%|B`Gnq=*%tLWG&7x=wF*b4exJQ?`MPQCB*GKT{MIgWTA=utuOXZ6atwcEC-m=D%ew*% zK96OrSX0oMHP^JV=|Js8Oc1x1Z;eZw3tpf>FIJ?o7%evP=XFf`XY;90CDxO`4uM>a z-`<%rPUOkSVm46emH3miW=ys~(GChkEC$~vt3J&ICFHFSoUc{B?19T&{(c9*(4H>} za>#UE3YjZGl(fz==fY-4-0ibZjhCzc<9PO~((MG^cX>aGDH8OnZ6h!bb{S?->FYOmps=~vY?BN!5IYEErKqhIBN$|Mj zw(xoHyXLKlP{5yosN2^^_`X5VAsF0yrJr5Dzr`$EpD}p553@Ih^d!if9u)k~%#rH+ zA;!sZT_y&qj4$>K_*{p;=Tvj+20Q;`5|H+-zd7-b;&<_%bHbBTXTz|eRcBJ};B1-W zcVp}Q4#?o#V_K4Z?~45;<0Y%aB}VkD-f~;?u=q-xc=eLZT%P@D<0Y#Gb8lHQ+_L%d zP~v-O%)$@K3sO6RIB{>WtgWj)yLtI}9SYj^DjVirdO=A0@F+I$f>e6G)*L2>ZEoAe z2ELb(H(D;J4Mf^3pE~DVGYJE19di|;L>bI{^D2nj^+{b-UBk9{VRDm{)wyzynM|KO z<0ValfXqM@%5vM|wS1+n16xn-4rK>iq;W@-l)5;=_*cWj9R-@=ZQ1`}6q}G&$Wvp( z1$nQrIbDfF%vV@Eu01K=Vd}Ktt8EECn>;(3T<2F2s8(IuLs25Ka{!S*i_VeNMYdXx zC`*uQRfA zsamy>DuMFTGYYjUMvawq-b7uGxW6&UVN&u1!3<=W|4%4q5HE1Wyb%KLD0=Q9)Xe8^ z(B@4M^?{3+ID)KveYV{T+R*?mFJ0uveZYl}`oy9W@7jzh(}Jo?!!LCb*tIQJs!lKXN9al?m(`s9oa>;wKR z{6)iGBq(!wg!=;xrdL~VT{_0Aa;Ng*&&>NFJY7TD z8jL^W?X}(}Pv9gi%)$##;Lf`OuXWQsO|x2M^V!s_-XR6f38Hg_>LpdRkpPBk_Z{YG zC`XS00_%JZ43s{#!14bm=#-eweMZlf7cwo#olUwk1A+rCDfly0S%r+^JI%i28aiw# zRhZ9upllsNVolbIt2D!U@y{@^ zjCyBcvvk5O_@*Nj@)KiQYA$yuF6{xq!yWMM5Kht~NO#u||9*OuyWscD7j~Xvd;1wv z%awx=y`$5U=3=d;?M41@w4;Hbx?T@DJ!IYuEq<<79 z(1%Xa%T@b!YFsuT8U8xBCmi#SqM9ih;WTo;AZkJJ-aiTh^PFWL#|2IQ0gC?aU!9RV z&$8O5^5Nszb(B$XVSm0A4yZ-bgzz@2s1(0#*w8K2YmjyUB{PJc8Pg_lm%B%aY4=7Q zDq@k^K?7V&4EGs>^3?6;_AgZ@4pW#JjlG8z{q~(bw~TD?EqIq2tX&)LtMh^eTYBWA zGh?$DlKpue)rOjQFeo2!?Em6X|BU<<#Se?kpc&ld?J=TGw60QdV4<_APH0eQHd+5g zHSGUTbk<=_y=@#v1rryvW-wDu^FhPUV$1k*CCGYH-r?RTt!hM3rT`&Dvn~%SbJ$1-~hQDAqRSKY;yIsty=eS9R zYOTfJKR3uQICiWo71}PhU+DmfZ(_(s!ygUGaivrvTOr{DC|QT*n$=5I8jHC`>EsP3 zkif1G5?muULc2RlX>mSz!7p9yZM&`;885U6H?a9DpjfH2(Y&sS;v-JcyoY5YOj-!! zHkL9LeNTw-S)Ut&L;`-wL~LHDfHo3iY-rYxgcHlP;9B)sp1y%qFJzs}>_$l*_`ge@ zjq|nyV6^dUlX$7Vwb&a1QnpL*s5Y(|xi@nA$fo{RkK7`EEBfKR|A^)+Ldh{OLD-+G zsPGOFw~SnlnQMuswI#>_Cz1+e@6e97@KX%=<;~hAoROE7P#WoZr5KpMyZqotrWZrg zPsjFx;FN6|EDp7W?7UupbXrg<{elzx zOrY00IxIp8O^bY8cw!0mBaTP^(@zjvDTT5_Q_rR^vL0ipgL}*)2OLl{Y4>Dn zMZ^pCjDFt$KSN~(b^=7Ir^}z#x+C(hFf0QlW25c95=(OwWT(1D4#v0SRmI>b8;Z$Iw>B5-cRPd6Y%jEaxN27i zRQ9KPY8L!WrgLa<#vu3n6`n`eC!W5ilVg}z?gWkcw1-K$fm7BFc}5zUBgVYhdi3l2 z?j1`_U&|a(R301l#}}F-N9wI5Ab6qKbk~t@@xM$*kx?oAn|?dAS88InyGxC2e{NNJ zXLJgn6}qM62R2UtYos^%Fw*_(v+rwGynR$3%7p_Z|sC9(*%MbTmrr!3;wy~zT|}UO2h#n4#MTRZjH>& zNiSihZxX7I`o7dAZOcm&xK*}tir8aA^`x7Mx%q$sm-jf1)E(FdrLMpDUc}34UkzW5 z3~KRc`^&jp)=_p@qvb4un1Og=?;pPg(H`6CDY}l?M}$#JYxO+MrwQQ|BtpgAeL;L6*GQ1E5MGl6a?Cx%-JgvG0F}< zZG$Cb)Kv{Go2N)2Cz5YUlqntcb2~3pkVaw z!o%t7qxy(1!`k`p+=?&{{OFev(zj1t&rJ|V8a8Z74PX~3?oT6&?H&Bq_e62enZxZV z*A={ng8q4g_Q?u3AB5Z?JQPOXWGE6Q!^!dG0V^hTGrl%Y_7~txKHA>o-clW0MK#YO z^`_E7bHs^&+k<+WrWpYuT3t7Zp{td8NarA(;sWPf$=AarZ_11Nn3m;KnC@CxOC~dZ zBIG@~dumHUSJPyYFH+B59aZ^Z1gD*ktdI?zEy2!PftC!vh+7y0{XNgKyI?n^?u`Uq zG1=wOx$g9))mg!O@5X`WXxr?zF25A6x9l;F+HT}}kyox78|am(irkWGWG8{XCOj0 z8DfJ&FS=7iJ#^MzIZl3n%{JYn!5GYt#VgkWHh2FX?2Sz-e@@4`bFt}BX)%4-?PM;W7euzZ7*=@`zyPYM2BL__R$F6{Mrz28M%HD&7(1t_~T z;uWmq=G-t#Zkz9gxf5jFjlQ*O4CL^}iuG_WSY1yOkg=@8+|6!wUA4m3S&A3VC_}M7WkBltfm4wC;2fII(%kJmi zR2rIu3r%+mE*0wji%buI{@p-|-qoeF*5%sSwcP1OkmZHvk^TEl@d!WqrBNZYq3Wk4 zBb+!+SbB0&N$25?XLXAYt_U^6Gz0>ZyV0gGY02f^OL_X@`>4NZ&kvd15Jwb zj0|1TKnn%~$?vA4Z5qd;L{&0g^0`fHIgh)-B>kAc2rO6Z2!TqTZDy|3g==O!k;AT# z|LLwYO+PzldN*Bx77!2jOP_srj8%*X2<*9+KB%N^QfJPjD?W2hh^{r*sY7EP64?R? z8fLCIJAaE@{n#?d%qCvbw>kN_Sb?I~Vq3%a7{x!4(-dajxqho;{wWP1=}tf4X6x@! z#c@{ZCqDgOaK1aTyeP@-$n|+m2J1HsA)5)LY|65Ly&`6vke2g(W6q{1ttJikLNg26 zhpjlFG3aK5&!uPlBIZ28xQb+-^{ly)qymO9;!OkbW^L_|cXM6ZCHJtZ*Okd=k_&!T ztpkO>s05KV=XmFSVv%&>m)nD#sikd_{}C#PX3ud= z?C7fw`Li&Ogo=xE0=1dlZJzHRoTycVZ5rh~!ck2;WIH_y?en!Ey`3X<5sDQ@?X5Tj zx)+{c1^*;AY1d(LMw4|s@Nj6ylZWFW$}0XkRVHW3HqnBeUvn4!BO*W`VueE29AS$F z0kCx!$Lah|_!M`{JRU>wv&zNSBU#m}`1A1dwUG^y>}CYmCR~~Qh%K+s(z&u^*HEKm zBp4Xl=zI>?6&8Q~u{`3ddi$8$XN7s)aQhAja*uU>Do|`s+m#SxZwk|c<3#Mq4S3^7 zMQv|+6bk=}3QUKt{upT{a1)>kA@=i!>GXz*Y{vh*-_^^~9Sx>0+!JC8^fO+?oJsAf z)t6ewnanG)+hUwQaGkgA02*m$Z+UNWU~GHm8HCY`@Oa5HTo34ZqaDxuQ+nxQ~s5_qvMB|s~p77gyQl* z7;jy0B$)C*4^{sPy3blweVYtOgLvG{Ot`71Weo|G+Cenree|)RhrUli^}|it43}MI z6e}7ui-x(*Dad*ry}8?=O}FlGH+dk)=|F#j8A1=0pTAacDX0u}L=Fqh1lk#xM{FiW zC%xC)j6kvree(+3?wDEC{fHrClHPSSH-kbb_7*Vy2UjYJpii;E&O(^OSA>;5vCW&> zl*z(kf<~uSR$9=!!08v4N_U2eB%j(u!5&>GsLuf!8#{S=`>fyKR=-#GkCR(lSQP1N zK{Cud;T)USW1wvtirp*!7=o3_C#OF~m(qOC0H~;E71A}Y0F)foQ0&LQiqVQE%<*oO z$klpX0PtLk*QCd<1Jat>0~Vi1?W;nRzfMJeU`~E3mZ0VLzRE(U)V~Re|Br|)lAReg zWy;3rOZSfVfz?&-vjgZR9sViQ zaCOH&|2o7GHL{kKnTm=z-?uV&RMPgHXBjB2O553o(rJGf@gPl<%uoU`}UN{ zx{}npck@7D{qUDroR5UfO4f#1=0Ys+V;#CpNK|iKk>9=oau_W6g_=AfowHu!iyU{< zv5f5-=LOVMyUhMn^V27 z$8uQQI3JYl%-3FuTB&%;_s&abQfb!@oY3f9ee?G6_1k!Yagy`*}J1(0VKS0|?g&3g zKI9BGHTaLH?P0^KZ^AR@t+#Bd;*6zj4WT^RnCBTQPkXne0ls!rZ|{MJZX>ke@Xs4Y zZGI@%J(P?^U2{k>Q90w|aDLLE{L7#jqS3cD9`scvWtipRve6fMq|g#oEc9dG@B6Xa|}h zOO`-t6dX--K>)L~$-Q1cnL|aoQRL@3>sLXpmtZ zY5o{o__g4NUrgQ7`gK-dOY>=)GVj|de(`zruAuGj0IPlXE(2tbs5**a`S0&BvBtWg z2f2SFtt}$wo|&iftQhT^H{;f52dvPk`S@5mB;RZbA|GQn%&3EIw zh3MB-HH?$#<=Z{&pH5Cf<&ELNC4OHVQf{>eKE!N*H2zRMf0}dga?^+1;?J>rLKpMw z-666|@wYGs)4J5*FVg&CTV#i5f0j^67Oy)xgR8D|piK#DU{O`YaQ%t&$*Y%{kZ(jw zWG4iIqR1k)gaFldbX23OgxsS|uw}Ug+4`9Cf@fpL>L5$=w*pWHH?9ctvELz`|BhZnqeRrO@aUoxPKsS9*HNr6V< z{3!GoinaiEz?EFY9piLk{l@m^%WGBXeYf!t51^Yru=%E71(FFofBQKAcBmjtiZ9Cj zx7#FuiU#jAoaA7H1hlB%#iicMOb76L_r}>%C9dzQ&V6HIodE&`^-D*-oOFK6wV<%O z$7X%cpIv0BqHWI@Q-&(W8}ZwIZ+axhfGTKsG;lNh#4vfAGShb-nmqt zmsw3#xSEK&<{DAn&y)VM*(2TodEDD9j?yJ|LKuMl#*Ry(g%<^dc}}`N2@4C&Kx4!Y zOU&BJM&BPv7>Cv!`hF3wLu&`@!(G=;q+A~MipqN2{U>*iWplxVomO7w-%^6030(rW z*Ssk(mt+-j!RsCdDVIEFswrmHq|*H0C~uUp3`+W~pe8M83p;#>Z;_+LHv2VW0=?U{ zO=f^&&e?lZ`0=oj&)nJMqDJ?KPWr*a73b8JTJHOIB_3niNG_Sy3}4iR=P-MyGjPyc z?b*0sK<>smfyV8QXe#A6u@~X?Sa<$jbZq9I_3vzpSOyt0)=)C^1(Gw zgHSrHD$s(dfag6f5lR2~an_&9KR@U>8dCt-%!$7*a%CSXY9B4UJzfagoT@<@B^s#0 z+dj{)106E4I7sMU+0BP8?{(S?wGsfTf$f=3%_E zRd&fGI7K|*r&3S$YvNbyR^fuSA1~E{PixJO5_?d9hZoAX%z+|YY1hN=TRKk;+154e zNXfMYU%mYl!FW&B9n^-S$7@y#ZCg!#--UPxAysu#@A7$+KAyC6EKF5ztb_c^GNW*E?lf*c@$YHk`L9G3T;5H=o!y!H`{`gst0Dh z_%H1QbB&4s%ex%IfOsD!wmNX7%TLrFP1^p9$3F#WlEfP`x-T&Jb$6dLuLN zcGACOAdvIrb948qjaG1tmz{YkwXo7FwvKt--tQFHo~!M$-%2wsrU%vnKG_Oo*S(5K zwDvda5rh(Q?SkS7T%|zS$*#&qEjtJ;--aEjXzOer=D2+0I(6NOO}#-@E8P_LyT_jm z(*csx*0iEg@9{ZF*ooj-I*)i|mmfIV>s>#1vKZXYY)~2;nh~kgf^S@uY;1aiBal?H z>K;ro!UG#{KUdgCyAM6{EKBaPbd3YJ=u!S4(z#ycg>Gu=XSI7?jrjZB+wk2o}e zi_O8CqQhcdep~FE&jJV`sCl_#DT12!Tm6zew7s~m5+XbJ?^z4$V>flr`{j}|$m0HB zt3?xmqLxH5=`ym5_v&!i^(>BVZX`t=L{T=Q#Wu;EIB`4-Zuxp?TJ5s?w%?jGWv~RA#2z^Ie?UW6cAAB zVJtRuTeO>Cr63)UJk(;fi$xhH@IbQsFfq2`0svVt4KE5l`)r28qA&hj3GH1b(qk*V zPXw;pD<*PlJ-eJ#9pkf&R$?RK?3|f1wkMT>=7Nn|aJd?eCgCDqM`_f(Dk>xrg{@Vb z+D?>Q2|bswYlEZjh=eYdizrpHpPe@y%`otRc!4k{C;8D&x#86lrNp-5WT-0r2#8E|+Eos#FjVrTzP# zMorgT`K$I|>$|TD_*V->qVJOr zSgR!Hz7C`TA5p0U^EL~MZFSgk#l_Txle8>b-Dv*MyN}G zuk|k=$M;O;yQl+dCi|{TTHOrxCIU8+jarwsSgHs}^E7b9%ROB=d@kze>2FwdNYC4#+n(9(`{Dp2&3dSdx9seQsw$Vm^7&oroJh5L>hW29MsVT|^ z+7gB-YDVdNj7T2i%deI-L<$XwnJl-GDCVfvMw{Gaw%C*LCa>#nL(leib>>G;PlD)%gb$OEshvDhlZiVyt0*?8O1rho{r*;{>*G0>Q%CKEyuh}-v!!K6^xyL*UzoX8S$8LO z(zXE2lDv8s@-H1*TI$;9-?kgya(kbmKSTi@bW!ABZ*s?X7I^OtItOg z31WG@9foIroNK#S#^TA}{zj{J?u0kKdrHq^Znr6{2EcwZ^#k7GC=DmaD>PU4K))|g zW75)s%{aGK-vps}PPH4YpSg@`(}<;=qgs^+QVmzp^GRgCuRP z#M^qSmeUU(v2J(O8RBdDUv@hhglSv79l-6lwRZbd%F z|2>WOUDGX8`$t{tf2Uc#_ca;K4d1Kd-+WMY^zvdTL(@Z4^wqxdsi%{2`AjtKDZA`% z``8fQGXD*w?cxABw>7n4Tf)2s&UR)TO+J{VEu}fnsZd>+7F|@{l73mc(K()oUw>?< z>gecV*9oT=b4qFn7<@Sib!-(`OwPt{&_;|mdRn@<_+1*1(t6{IN!as5@&>z*CmS7gN$latYTM>;lN z*hqk18u85RG#1^H^+4w6tTERI6SiI~PD-MoWXA})07}avp-t(w?Zk4Idb`6(*CmY! z9kt~MUEox?`1xnj+H33hCkBE#!i9a3TeO6P~C*SVVPr)w0$6LvXyx9)g7 zx|2A>dTh-iMy<6xds8Svplg&mukV)E)H>a&Z(={eBm)Z9atm1(q7+rC{+^Q!q;a(P zCcKMB>?P^riC{Lf0@|**FG%dZk#OrPZ2z+cVD8pOM4b@(gwf#KZ;41?4e*-5wwt~$@qJ&Hu{eV}6>jdj>0Kn)N8!gnR zMEz(SXwl;NRF4ZHAxvqr6c*jR^<|Z!sqVORb-VNE!H|Ko^)r)ZM1xga*+@C=@qVN4 z$uDfo9>VcIA|!Bd1oWi?pqqXogjf?-`04kK=T9O#S~ulqHxvtw7R78 zadqdwY1@*>;wJueFFPl5=AAt3`){V|M>1!3F4B%?dZOxe0D!WMpIfx>?z8sPJ_o_41ST5TOfI3`R7j7yED3SJ$MURG^j^6zlEd z)s_~i@7g4xDLPesLXY&c-=6ou?p%ca*r!qTUXN#g6Z2SqY!H+a*nF3�|TYXnEZ_ z`SyhU&%*jy<&ntxz+hb=a2Gx!l$Yj7JA|bfUQYZdajhPA%37z-_twmRymj$Y_iX>h zv#7#j%_7+FvU7b83&0uj-9&16v^`1OV;H5h7r+RwG45#Yt;f&^&@7-$`w0Oi60KuN zY4Yd4B^ex(89iyV7^D1uxYekak4qBr4n`dY?p!X4d~28YVcOFgwd|0N2=CK<8#zHG z?a6uDHJzZPS3qdBXQ*e_$$v!r>CC<-7bZ*X zTdvo|Gl10=LNd$E%{FqQ4@TeSpqsUYOWvM5PHiEAWwOl$6Ka>AC$6oJOX{1iM8dBX zl=?$E`MOL<#2;{fBkD*9!dbJvt8e^(ni7$iD_u(uHhKG9-amDbw-yZt7%ck10ltXN z*F#&^eOs56+lWQ%E!mxFsQFP|MhL-f+q$rhOhN8S2n{rfgNd<8-+0V+AhrYkUI97l z=dtQnlu=NLH8b5~S5r)&DBF)W(mQ_^zHZl!wx7rzv$1VwnzuMom%c{f-zLTWN7OBX zVILvi0IXJ8yan0R%{OFqPa5>IdpD$m%$Unj!oCmH0&&k}UWNfG2SagTRONCNza78i!t8GI?fELij0{%V>!jrgvU-LNw3 zzWwrz(DPNU@C3gN;?#j)na>C(2t8~pv_3E9I%Gp2{`F*kE=QAd%JUU4kc1H2FqIvZ z5S`F8ChZwn$bkwSO-4chAFRC9=M|0D@FDJ3=BHdu!DZPXuOhd*tljDF|0l5hn`_*HEY%7g7Vxi?A9{|!2YZJ`^zj{ z(-uqBAF`3l6EvP70qhSdx9+{){4`UdU^*Du#E#)UZcsl~3!_X>RH$*jax4#I@n|mR zIsM@9!Xe(26z(4QXaOKC3fir`;0hgllt*<YMc+HW`du1Y_e@IV^00Z4YYXE|OIPuC`u7Pc5R_N}2Fvm5%o1&GQUY5CBFj_GeA z85IEp`MXZ}YjK-%s!~&I)(2)0Cq%d^Qe z&B`2>&pkx4n|HfZv=A2JZ)MK^h_p3MGym|fA!09FjBmjR2?4_*Jw)HRtCTJ7J{|?) z+SwRT(|3?4EA9eHk3)l!Vc?Yk15Lv8oyrKD*8dKWe>5=* z6m_vxxMUNceC#%7y(_eJlHs>B{&OQY?6~ItNXo$M94;~RU~vW(T2qWDXGMN?PZPajBE<#={j1z_@QLf_FuVLG+)(5q*5|}#o;aOfs0#XCV0~& zT*1*7kM_Zi`x}l`yoT=oUQ4Hzh)*2BqBhRtj!hH0NCLD5tXXH=Ynrg+-Fbf@?)$!6 zKp9b@gbIHTHO(bU%0$F!DLWNR8cOx^!qDL;YRFVsdainXT6@D{WQC6*Q2Kf5H?XWM zdq64@@u5jbdHEO-O!h1OTIdD@&^oG4$dI{`YU-@0U0P%?xgL_TK`M?ee*qXZbeOLa z0^Ep2I)c|v|0W9z_T6^@Lp7^)&adJqqw=;dyD*P< z7cUgbtA*_@5iu>?`Xi=FWI+OEpHKZozOMM+RNz8m5p^qlE66*xY?4Pyxo~npb86?o zIWFG`all=HS>|mBR#@34{fihccQYXotW*)0?XPZ3ZfrrbQ^-rdzV~ z@FAWB&VFr<)#S%F*#SiX=7r`Da$3X$er@`58#y%*l0E7sF#tvvQ(bQX{*ju4sdPu8 z(_1XtHsUQ{75)g!ez3xmf45$KS>UlU3lJ(;kSVA*u2yOlcm zC*5U@$?HpZLe-gFZQ?!|svyq88x%(nJ?UtP1>UA0{erJ@x@^YmG7^unz$gMzXXvDl zb+ht8TI=*r@~P&nSMvFXT2v?p!zxvI(b^E;NDFE`@4uM*?1vkLU4y zM4i_qRDSlhp}PIeUhm$Hm;URAENNP&B)#}_D)1js17^lId{)@r>ycy}&BsCpu2Us} zNuIeHUs8IEL?9t96FiMi;geU*?zf0ML-g2?dB<( zLM6#e6e;-I4>0VO}scIXZ<^GJ+u84v%c zg|Vlf!h#QAp=3u5E>gzk|C9^4C&ez_Qlzt071Y-IDT)E!heo9D4T?Nm{FP7@dls!# zNth)D2T`F|wqtEBc-i{|g3YW&NG;IvV(3XuG}rP_lA6*_5Sr1188ZV^b>C83c^2Qb z`k=(`HjQ`D-ps#HA(RZ8xKKVqvD~y3teHEq{%sKwO<1^u@$#c_tuv|%^P5r@$~7xt z0u4<<)qQ%9i?fC*hsaNMy90Zca+7#XdNk8h@5;tD1@;*&J1fvxph3Ai@s?Bm1Y0eA ztgR}VoEdB4 zJHh30jqSg$FetYMOI2@9#um_0bs{zY%O+s5JTk4N>Ulr*dJV5Yt@Gql>B{T)|*N^x8rFUh%)T z_jf;)Obr~B{sR%V*zwzndF9O({TAZo(aA0x5%Z; zRc#7ECyHXB??b~8cF1L_8G|?GG7`f|?VD#T2ftXw<#F2Zn@_hiixq?!lZS4G1zVxh zw2So3_wr8(g2K|4DltupS-(_&_O?{)oof=CD1~?o=IGEVztO|MSbjvsP zZ6x@VcaZ-PRR<2eBSf=~cyFB|6aTQUk&QVtABA)XV%gDIhqjmMd`*9nb2nLTr7DYV z2LNRMIt}KphI%b5<%>J=*V9GBS*!C7-LFHG6 z&jd^d<(<2lsDzd8zJ}$a6mRTalq)pg{LlOe2o(_FTNe|Jjwrvt81}Nan$yb010kV5 zkZ3FJ*@WmX)RuKrIbQk+fl2P}vI9X64z!O72l5)DFkykm3jr z^s?-~(9#iE9wOV3x(Y1f7zQQf)wUx{bNX&9$jn~N2*Q^;uR3HjgqGXQ{*4#(pFc`v zY5UNC1K-c&jUZ<^kI67!v~^bR_E7rz_sP_joQzIv_K;(cgd_|r-xQBZDdaUhT9%^ zPLzI|@ec(lBqxcUr)zqlYsyw#mElc1jp80u`-IO?rMe%ijjtMG&9^ex18a74*u*Picg2DI%9=ccEj&Z`B zIB+IG*B(W`fp5XbAZccXPO^!@fruFg?c-G=jEf~T>C~l=YC!T;AZ`qXHo5n3F zzfxnoT|G6LK%T@ig74rdf^HRfJNmbUay|SqlwK~)^5jVekyF>F$>9bCt`CPF$qnD< zQx|~O8b8#MHJ8Gf`~JZcFndtRlyy2CBp?Mq)c}%>}vQ5DY!cI>E>P5iNjcm7$q!O=ellAT6P? zkbHHQf&*PSxuGAW7dGp(3Du9M7d!jExQ!wH!XM(()SeP2k%y(p5eNAexhS^#^0Am4 zV~}_xA;Eho?w9=az3u~9hNW?y!@EMWsc$QW&vF9%ipo!{)gyZN>LNFi#PVjO=yHlD zdCHdGtSoAYN0?P@2m2)kqV)^X-eS5Z?(qIGjvWnTR&UBRb3k#rL8PF+P6E3FJUkN~ z`6=y+NDXwPNPb4HGqUlSPxEoMMW{Tkhz@rr>vP`E%PQ09cF^QV*o_~r*^g>*Pzwh9 zY->>dl?t`9We-kG#W~j0?sMdr!bJ5jX&Sq`U8qoFg3Vy+oX1E>^emL04Q@@iN1f0M45AD62We5z>7 z>mjTZ<{FC=uvGa9&wartGA#w@{Q5KrvgtYDc@lHczFOKB;-q;~(4?)4XS*>S(0lsKQcr`JzCDok%?HI0pZ!DEI2&WU8k}`&$Vu7H_bVZ0{)LnCXKQ zbyjcl>VkgXl2)zY#7k#X^>)JgqQ~9nH1_jMY}zi)+dA?Qvpku8BGN<=4ZAO!K>?}9 z+HC;{(hZkmnK0OMS2oe3Yqti4@A{=6bMT?yVaG49ZDS|G^vLhE;?wDjHr{|lksl7(Qz5w2952O z3~jves71+Nx?V7v=($-sv^8R{T| z7(y!>Tc2|BRQu(X;{ZLOY}XcT7iqSopdib-zYI6LHf51PFCE zChqWFmt0;rg4kCp6!~G_e6A62FqfiLt}+P;Ea38|PtEM8bo#>T5F?vbxBa+C#x5?z z8wRIO=X-+uS;O%uo8go@?w#NF%8$3!%IBQ-I<=g9;;U@5-0B;}YUY6E(jFh5b3_tY z<|gWTVu!l0P|O#B6IE3u!Fa^ab+nact5^G;e%*|SeH}r>eBJK6<+9q6GOH2Kw9Xyx z5SvE`Ke1Xh(J{%}Bs9(T9(xBItCLUB z{mFHxN*Z`5Y#4Nl9YtRsK7&Clv#TGEch1JV$;hCp80r+x$90`g^o@VK%h|n^cyGR= zl;>P&!l+3VWU0bEP!wJ6Q%TL)BY{%hesK`{^vBR=`Q+62B?ZeF_k5RzFMRsGh| z2n-@%=l#p$_$sj#-sLLwlIBiMW;56o*68!P!rz6!-b8+zywM>=@;iDV`GT9-8W!_U zQ^{g!lo06^(iLu*BuHHrPpk&XoX}=+2R_H#ekKqiwMI|Yt~Q4}hW3gF4iBF{t+&+l z?3x~AuEZ<&J#m8%tgF|_h!Wb~Av(HJJXL*K^HtN3dV(dUt)Mm?jI@11-YuyzDn_St zq~L9I$O-%l9k%NT@cT-D2ZhTwXn5&qxj)4W!IW@@9K3nw*%6JwVDO=PN32lYyQ5zX z2!ftkb`cKo(8Qx-goTRm@4!NhdN=u8I4H^x#GBdA&$G!a1}~SBLm_{(!3n7Dxq0Tq zteEG(v5eS^XQrE;9WO2u4vDPL#|D%<%ZE3#UE`kaW976}DJndiH`8I{BTt9gFEWU( zTX>>BE?G<*u4tJ6gUf~Nym3+;{x;qpbA9YQ68)hx=M^2vJs|hy*zNXVK~4T1k5rLg zGEWzIIcNrhZkE$NfCbfk!ELI|X3+M~MnD#bQ!U!TM|_Yh6RC3k^TG1|yZJ(g*`$y} zESH{yq}Z}L53VIq8bG)k%q^@pdmpueU7k5MeKJ|hb0ui!9r51|Iii>!KAKPq+@CI) z7j&3C;Ny4$;7$qcScgpe?)0| zD*T6L-HLug-WDeQ9~2ll;LQzi$g>=Ka&T6%h-qa7QCZx9#^nUaVg8e?)eUk8m0Z&0Pi>DFSYz3?o{38MzvA<&7ba4uZ&- zBk|&dDnM;ZxY`LZ8|eBdzJMdBu6M^T$nX^8EnZZXoi<*TYawvyxuP~b-tqPE6O$)p z3~0}5#cZNdPmpweX*=YL6ltdF$z?jVhUFn&*jHI=iHRT+&!g#G8U5k1J`tp_zoc&2 z;NBR*lhge91FFO|S%CFvIRPR%u=zVD&<3iS_9KfC+KZFN}Q&T=w9@kn#2%u&~M^VkCA$} zm}R7+RaFMr8I6G4j^L|zBs>1R3r}w>G!N5}hTyYcUl-P`Tn5ybExsj5mrjj{g(fAW zoHN1ve2BJsU~XmvRiGIrxp*@jsrjq_J$b^4fSnRwTqQ|Q9o-3vBm>0Xm=58HV_(AH z!=3UOexb&RwAcvX%xt=@HzDoTlC5fg!V|)R)>m9GH=IYmJnZ}a-Q`38)lC;KLHQSdXuzdD-0xmcUpwT*n5$i z>oFP|9eMU*cB2p`FhZDf7-D&I!qA3PM{H+|GHg*IA;H&!8SDt6J3S%ePb72y9 z+PLBdM1S4#jBFg9%GJhpc#;L^o*`4Uat`R0bsC7t7N|9gs%Je=*pr4t0hbIHY9GOt zNvT77vDk8+=^$VAs5}`aj|SJ1zX!b0%FTg=d!LUz4q)_)?W8 z+^$hlIwjKeWVVtdou29T(S1&9M6Fj;793+Lnla}6rF|8=gSW4Vl6n_7$@R;)rY)-o z0Vz8*h9*6~>ElCqG{A?-zNHjkwD|xBEcRLuqI7z=gI81{@?A@}P4 zJsHthpO!)!MT-jDE|{$3J5pP{ZCUae{RZb2h&Qn*S-}as6+hFF7+l>bEv-e&VOmVi z&vc0EcrS~?82_AJ@Tnzzm&f(pMt2Zugzah5)KCf_@jOLmc>PE5&j7=AdmZPVd=TEA z6-lGn#WTCN8GW;%0WLGN=mz3Y?W35N`GSsjN&SCx=E{E*p&_^SrPw7s z;u(2KZgg2vAeXOfZ;~Pg``>!~bPyywJRF2wP2*LEuu_@bZ|IE?33{+(321)8P}1w| zq4uNk9JNIk3quykF3lp|hVe0~=qff_$K&G=*`$;8wFH~8fV%wZif&2S%)(jipQWP6 zqcvKEiy82H8yH*?G507faH!5gjc4U%$ZQceRa2R3OChYjG22!v;=TZH-|UC%FDfLf zY~qM9yup!0OXesw_4VD!F0j?hw;O$8Me#tT32i#faulv;!M<9L^gGUi?EkP3(H-q5 zgLdFrjW03LT~bkQHbb@N2@pOI@vd&4?-{uilcK}b&*M>69&hZ`y#XEdT~@Tc-ybsj zJ09HPewHrC2Zb*uiQI2of9V>MTkQ6N(~Kgt@;-zU8e(q%ZYc=gTWI`n4GwJ$%xNvv z+VQX0=NvIgvQFeelx>J2kAY1G)qVjQbZBlGGPhwyxZ8{dwy*0;&2 zI~e?1BSt)IC~4$smSp^KQ$a#m8&|Yr#;j>9wCFNcY}&V>6%&c6=HjM~YZ>)uX#3zX zl@vW(W9zb22+PRSkadF{e^msCoe$x9SRgpORx60r0zzsEs_jY^fME^jySz@6oW}dP zEqH2GP>Sj2hJ5j>O2yeSDRA}~33iD9X4egSYPT$78^ID-Q1LTHi%Kt|p-W684Ds^s zgu>IXj}7B@k|QC5;%uKK=a{ft zphski%RlYTbSVBVKV|MiP*fX-)BE{Ry?=Rrpoh`7Uogk;J@!<3uA+G{MyN#q-VTS5 zhuV#Micv+DTK{*cIzk7pQ9{x@d8iTtE{ywf4|OEGiunbM_fdCQ z7kpbYvFaSxYizti^68-yqjyf&jQIht4A9_wN%HSsZtoSOqxRRRpVg5W8<}ozkecvX zAKLWSRq;%|t12EF^2oy~ki?5xyqZ`#d?$Jzsz2^ciacx$%^jLan>iuwC!~im+FsXi zACkTQxBM-wpzO*)_d>htK};?O!liuc(_6HQlk4uP<04*Yf9~wPT8_hz?GX-88CxEI z0_)N}QW!LeGN?Hl>s*RSCR-5cRze<`n4vKv6{f-f;|3Nbf!?RMg@1b2mc8QuPCIk# z7t;SS=ukWL0+zib#RU7_B5*bTurM-FAvpc-`*OeRoFN_Wmt9@1Se-+0(gnAwb@ue#eCY0kRj5Y{d$RgulG z7zB8=;@u*as~T1pf1mG&T_#OqvbDLU9M z<=KLzfl0}39m&q$95>gWMam9b84X)rib}(4HC{poAUulCCnV*%wd$+aHrL$w#_O z#eDBw_y>;i1O(FtMiL9BU22x=L2C}zlA?mS z*P+B;kB+TgEe8niR8XmL@`l_|OVNTy7c@_$N2z5l{XdFsS2Az(@g8H2*tnZ%-$APv zn9l&r+O1xnbIzupPM9W|O3!8R$3c|`${$>E$tPuTiX&e~o~{<9nezl{MR>V{w2T34 zR)%ye%uL2hSm1Q*Y6j|f*HLnZziAhwu2aL4{=6_zRX8F!c(tc3F*Iy(PMgT z89e?Ew5BN=4Zs{w{l_h|Zpw`y6 zJoooqMFevq7Il-Ps+}?#itlFHQWBCXO>`q0e%m`ykSKwb!*vU(sh0mu~T%ILv_@28uefv{lux8GYLXsSjg!)c&M2POrTQqLXDr7uVWgei-Q#RTr z2{*iQukNR5+Z!q!uBFmGg`{4A+fMNzyJJPY5PXcLhWYOP1pAl}1k4RVsysdV(Qz=f zKezBqBt5X$?0k&lwDH^zVLcJUcC9I3YizRZ6=3a%Z>4KpNxd4rH1%{zo#ytsDg*Neh!>~XCyNr}A`Djj5>BxWX~M!LBhLM>t5WI52K(@Al~xXFA{ zoEK*#eav8EcR4rICyPr7J@Wv`1#wD8Vl8Pjx8)vrp}C6fS8YM75UB46G!=Nvy3G*C zH>O_GJWQJc9r&8w`LT9ug(|H>X7X7Q5!XHga-fm0Mx@!Q1Zf^&g4UN~jgjq##<%k$ z3D$Ldqo%NJ%^2?-^Pu!=9XAq&8OAnT@~FrLI*ur+jmU0vaNSQhR{={K3;Lu-h6q>Y4f}=4h3_seHt9=-zaqP}T`pNgzI{$tL@* zn0oq--nH=bO})r*4qVdwOcjGa&I(WXbrDfhY6-HCypa>I#$iJRz#?s=Pm_vD9m1Hm zZ2pQ8`C@c9x?naUA&BzrS=E&umCTkH7e z%!7|F2zgyr!qa4`VvT@b&Sq)p(mgacx=qEy5wLSJ#au+iVzI?rGe?xJ^ad#1ZAt!n zyhqFL>qbdoEw-a(CMIh_^L8Ln-*q&pFILv#L7zZVrk0^@b1&1geVe1@wRj~}Es1)a zwH8;Cqq3$jiLg7Ep@I++9T{pw7JMl6jVZuyzCFCI@G?_L>i#tFo~i zYhZhMmB8^k=UP30&Fuy5>F->lX;JB?6|3>r1Lj-0>1j%%M|GJh^SVMB{Ca>?q6PF8 z%Atpj!D&{eWc|fI+jKm>+f>)o#HiStjb&@VrmSj}FdJoAr(i`81ExJes={ja3g0%q z1ddlre(5hF>#m{5@mA1_z(f?M>&=aQ#G;spE(Sw=d>SShI7H4xhuU-Shn9%WxWz8^l}D+KeI( zvc#clWM(Ky$T3h~MgJYmF;)#h(L2Zu$Pp=rHS^rq%+mD27OFnhyvm7bA2=6)5P3zi zTuGIRPNn8mG{;-N=jIOhUXVXC%#eXu#FuAID)*ke*;lkH>kL>wKl;J_#c^8pxx}xO zcrW6|wpdtVcXi%*h{)d0JTg{J(YPG?&wIDIM>H(uDPp>*FB=~faW#4PN0s`;D2N4f zd0gK%N4GbHBpr2!blxP(a@z%S`G@(+N=U~FWU$Loaz;46Xw|f zJ3?cFb{UEY=9yday<{cALUQU$L}vSzNE--do3j5X#CO#bBnMhZ4n*$$|0ryi79Ksn zOorack1fWuniZY%M_6pag%YhzJQ5-`TT(km(QJ)lUOeX6{`su7O2^ ztkht@GHFJ<_<0O^2YpU72fom;9PC#^c#bTW(yg7xslVW{&)lpcsVW89yZ@sIyAbW# zQ(l~UU0q#WUuT)fi+IBDLcW6|75g^Npfy>s`TO_MKs6{ZPQ6htmb0@Wdu>XpSE+UoHK7nyLKiX~p2P8n|#LuQfN?lmq!qZu~1!kM;3A;sMBt5u^`o3fo8&dF06bIo(t1AZ8tbmgZ#ez~#Y%FMn#v^MMwcnTS(yj|g3 zlM*h?Bq?ugEjv6m3^;q}fP&M0DV{^*Fb*-?3?4a8>txYE(xrDV!-n6EH(@U^cXj|L zc2(xF$qtC-gD)7V2%{0WB;t;_*&JXrIVurt*jZ%?qO1viEk_{zRUPQQ#lObwZ-6M* zj=R3Nq&^RAV))^s&LsxMdHHRLg1^E-1MaQfWjK%T*cY^K&ruk1SuG? zz~#`7;5DPD<$gvl5>;4Nlpf)m$d8;$Ko}qHfq*OZMu=-dq?v9%jZOa&1N4PQ(5g$+ zg8m*O#53*pPx9v*a!-8sxaHXH-nsOdX?yhltoMDXmOYWh?XFc(fk0mnW;p-Dm%P}I zh@l-IV*gNIuUW%^pa~yQmQ=~g*8`!fp>k&($ABlr3 zP1Guv`Mr{R>+dIC(sN-lNx_5q{P`x5$A_7Ew#>iAh!b_zxn0&^{1U+gItvf@QFL3O zi_omR6N>wHuIDM_6smrenY81KhK2Yzm3GuNsH|g0)cIIsAXz|i;aqeKZ_Uw1M%EuJ z3~iR}fkY?8-W23D-~GHRGjUFl*r(YH60BT>w4r<|&o3LV!*Oyl-jLyx93 zxY6!5d&>sS&3wH$-`TQVM$4^GyB+aIq54tINmis9q(zfrzdmx^?AHVLI5;FNwarey z#W#3Q(syQT5v^I#lHHPOU=X5#U%H2h`F>JkC3b1gAPeTza$rbz4-A%3gDmUo$a+(IZ6u(| zuI|hLz!wF4Lqyc7KlFv4%;w|x}mT~Q_ z4Np6i+{ConQbiP0?*gthvJ_Dwo$-@ZSpIgMc7=VlI-8{Sf*i`=ruA7A1+M9@ASN#~ zZ`Ycy!69A9(AcnSH)sdXO-Me>?NW*S6d8RAjN#|Bs$U4U43hbO_v;hy&OIP;0NVYl zHnuAiFkQL2+dN(A=6xc8B$P?I)`}cSL@&w6jSXMxm#Z4dMWx_;TPi|2CCS|R*Ih>R zdz3B1Mkg7vh89VF%%1)R?~{^!iz%-sXdUCl4D*R&*WsjTo#{$tf!&vjmz z(TR<_ukSmcns@&|M{d;+^?n<_( z#gq|~aN8K0OMv(M^G#=pNsqCN$8yx4)it-etep&EHe1QDH4LR{R{Q-sW&^O<#xt>J zBM^xQbx?E1i8Nh0X)L30E-SdlFZ26SEoZ2?abV#LPqnF?OG26&&6yVElwf`6-=R+_ zR#_6{(vUIfbE6$HU^8H_OxFkh z&-ScAvp+adGmeqRkgD<7pTz8=?SHP}#or&oj#7sv#s`$Ky8T00|WyG~YKLUpop;y(j?Aa$uVC zig`of)(6K$l3o-NcA@+?Z%n?Ab>oVSv^>`Vs@>cT#6eJDJvr(TP?dmUb?Q=#g(wo@ zoF7u2X7u<5Czc`wWSKl7q_pJKG5l0kZ&vY-;xIZ7RdyDK_%aNDjJl} zj3s=>6h9_wa2-Dg-eQ3uhS8?F&)wzvZutF2K^bCS#dI}}0`he^C(VwOnX!ecCf&*s z0Zi=p%*D(4cH1cuD{-fLku^&%T0|T$07!-#_ixi56ZzPSrz?fUP0Y0U#Y+P=1AwBp}d`US2;zV7eo%5}?lw)S@K^@prg^~i z7(mnV6dY8dbI?CmA1oHsXjHRp(8CF9{_mlk258ICMf#7w-Eb2=7@C3cNs_hvGgVHJJ%XGd*~5;?P2dH+(q ziqC5`hlf}4gr{)j zE*&@ru&CPZ6XOo~Hv5`yMnP7Zq%_pg!9!yoFTOj<2D~xZwajm%oirgG2K&R{rsaC8 z_Gu0wsR(q)X>1U0LcBtSAEB9=e4Kc77sBPq*BLMQEJ))NNh|H@n4R50#nuSJXx;$3te^!s?j?&4L~ zBrJL2yFbPiZM>7M6K5m0rJm)PpL@NmmU`dy&Cuxf9mOtXT0{7@crR4tp-WWEk&4<1 zi=lEEKSPiP!%tLoYUU~Hp1$! zIoZW_!*e`RnU)RBgEaCdP`CkjlhIh}naKUR4oc*CB*Ss?{KdD4(#0A9OVf(!9Qz&b z3=@HU2Uv)80vv!akJvY>!W+`w*n(TuW1A}#APGfEBRapg$G4}RWd*zk36-W$fzm^d zRNe+AjQ$43*nSHY`&=5S(XK}RR@yYfRIG26UXWe5T4QJbrmM#Z@5>C#>9UGrVYXN6 zGPzm!oxe|gSWV2vhOrI6PQcR~#%{KtIb3uNZB~oZBCwgN2m!^F z4N8+5>#e=33aNH6kKSK^QEF;RO=o2>^6RWWg5~D84|h{6B_u9$fIAF@aGhs*-z@&+ z_Lac7OAmmUs`^T3ZrI4Q#!G^nJZr7Y8ly#7#qBI9p8)!$Nzgv+v*o!NWeG%r&LOrJ z)twc?6eH2=eRv*vP1*Q+zmt$JfVcOR%p?+1F2XR`6q?cZv5GTB=!wljy{YtB^= z0)N;zWIB9iI%BXn#XMICZdi(pwZpr58G>DdUXT>8mU3x;a!IRU3M%X6b6FvIUCY#0 zz>U&tH{v6E9wmHKW|LuztOxx0pJZ{MT)MN_{b|boi;^bOAFOa%u5fdCvU?P1{N5Kt z#xrR7O@D@Cs=cR&o2o>hY`UR$=(|ge%j_oJu|jgFiTi)N{x7e%Jvp)Ghug9yh4N$XR0AhAmA09H6Q36#tEFkNF3XjjV;$M6!{i{P8vf+0^&+fS(F zdL|_DS^spRnE#`gO-NS>`aD=(G8L8ClL$irklW z`dAHfnTb|_C>w1>Y0T$?yV+tJm2Mw|I3J+%Iyq}9e;4FFbZS2F<9H(3nrUh>2I2bt z@3-*zTZBZ@A4eVFCjrbozy)Y+$xT2ILsoWLsF5Le7oBR)31$tcu`J((S$>(6clRF$ znBFn?;=4a^9S;%>=`>R0UnA=iAJCjMHkUJwTqX|XI%cc|Iticgr$4>jFnVf#o-h)@ z|7%vtsfm>5nJ!Y)v<*5m1HK89R_3J|t1*M%&r8>vnUc`1(7w9Y>NncIA8Ro zO+jBd*e+*(UGbr%?!PHbt6A#jmT+^NG1;f?la+lz=4u_Kqaw>?8EXli9J04gf~(Vb zV6Z7dTC9%Lz3-NB%xt#*6z$j1VrhRLZoW#eF$K!WtdEYrvQGj7(jNRf|DHEg_S>+! zli;Yrg^jbuQ9Y>Dr4X79>~Y;FB8$FliCMsWu1bJ$0);cV$kKTo16GrWm3l*F!eMlzD-V`;shN zJKgRi8pl}sx7o$q$vD}p6LOi$QJ7S_G@N7}=36^}T>6w449aMp`zsPt(0zEp{Hy*8 zK)avmEq`y;=c(h|s+0T8d%jf=fk`B5otEr=J6fgg$CmA*9 z6>gM^LU=$Nj+J@J z=^|w5+*Kss=DLoM=hptO>}ZJ>dXf{>>MKSf_2>2NydwE&_OOp_uGLZ8aqp~sNA8iD zFrEPf2BnI%DySK1%Z&vaeQtDS^|7zy^UGeb(aBGH?17uoxzG^^-)a1q?_OL(eofLh zisq-BPpksu`eeP-#np0BBnQ3!thiO~rA|X*(_NVPJ)S2-QpDe8?nL(r=b|!EOdE0F zN*-`*TE$v`rzSb&Zbv1yh`*$t!kZyAAhlr_xuHhb;3KKR9ZY$+pE$tQL>8ZMTFmBT z1@ID*lerHX>wLj6T%dkVa;?dnN*nb~0-V%WMA0{dO1td#j`YKc_`9jWYP&=L65<<5sp#H=31Rea8B8`g4h)R z=*4PYVl?(iQP1_usIGX%pHUl=A|R1ZEP(8?lDjb1&G-s;Ivci1Be<7iqXF@_-tIWL z?`mgE(#F%2j$`^0OBb#CRbAP{O@One)<>{oA z^F6_eoOIcRN*kvlaf%Z6f22N&r@7*f-Jcnca@H3`dXqrWD8tA|+!gX@IbL|nIVC85 zdw-cz*r5R=*2j(VTzKpTnA37$jqN_GI_6y>Tf#@EEic_QGYyUkFstGh)GaRB&|%&t zMfO%8ub_5FY^v)=jN0L3;A{sZIAMb+YQS zdY-cB_coacohHUwn#@@>@)>4>^^LS&aIn(cvOm(sFv|50 z-_o8-2IS@gAdjD{RIT-w%<5BOhVH&Gt>F#cz+QJ8aT^~Cx89Vb3`ge_NsnHk7nvKz zp`y!|d`O+@n(>UZp&N!dy*3Vs7Q@kmW%M`Gn@ouw)3jgJr^RYZcDK~DEEi{G;_YG$ z&UZ9Lb?D8qdsJXW;llHDyFsSjq=1jr@U)?Ag{%LdQouo+`hCzu%M!HnE0>g|8jmVrdf~nioT#TxODW3Bs@Tavh`nqL*}R zeAvq!kd2M?CRGnxRN1sh}|XD%^u*L@GJdON`N& z7T&1)L#heV691zzawTLhZbc<3M#&!q3{`hi%g#=?@Cm?e2RaP6a!w zfIJ1T?zOHqF|dki4SZ^^t&@`+*p-3RxM==lfflE_u9q7-ntZ)u($B z`L02OxuUnBM>ge&xn;7JjYrc@fx`961q-@WDl~JE^P>mO^wK9Z?&!qk%WSpZ)XZ!G zTzPcTAE`%;nb>t?jhoZ9M=x+{Z6u|mUM^JCPfNzvF&|!B@4f*YYlTq?&K5p@K4&C@ zE=-*eFMxAZ{VaelpUT2X&}TiyC7})@S=qBI$-XyLTDy#OpVo=N-bI9y+}?vrtt4Z%l04;vBJ8jec|R#Fbof z?=IzeFp(gZLjGXY+vM_7^XyHSxvV{RTV&z3iS%U$gMBEdOk*>c zFbj*GnG~%PRBEborLgn9o9B>5dyrMMC@+=kjF_ocs$%b%z`Pdrv+7FWW@bx{J-lJf zQpJoT1}Oc#Yst9oO*mS~1T_krb2dY2TBw2+P1RV%ymC_Wq*vNtPL+?4rn1nZz7Nn` z>~)F4hazt!V{^aH#8kYngTaGxos89j(st9u&I68;B_HMm#FG0JLmu&EiKKf-s=1nt z2y3gF(TVTc+OXMvBfKfNYZotZi_<&hIl~%EE5;}JHM}`u(a>`4U4Kx^(2I%lpx@21 zi=*4-QH*`Eb&-3I-nXbaPpFDDsdgM&vM@*Z61H`R8;tr!xBK205t#1hzl%S6cbPqJ z%n9ZLzgPUFNGhg1-jBtEmL19jltc#qi zauRY2!^~r)yK0dQkCWKV<6@Yj4HqANilu8E9Ff4Q#x7boIoHY#L_M5D4IpowCnbGO zKpxB86{ACrXn&5l=rTdAuLUktOa|pDIzgjr3ZZ|V)Bk%+`$8dVFFIzd9tJxyQVUG; zf%*Tk=Bk1G1Uz#clqJk^B_cxTcX1rHw)TDN&6cqX3O|`Yjtx<xWtVd2hxpgMVfb!oXZ~EE=fVDlXAABsz;&`}+r07o;D0d&@0SkFbpLhl&s?ranJ3V=BXrL;F z?ZkM}dY0e*qu|$&EN6#_P5z30*f+B=FUv$|N5XPE5-R8^jU0VD-770fOzK`|Z8pS{ z{1Vx#nVIqz`ESgAYn`}F)8{mLDhkgRo%`-O{``P(*5*G7YVu3`Y(*(X zCj`t_dMvU4Z5asmSpS#Rpc-}al|$vEt{Fk%r=5_JxZHVsuRE0-S%C>pR;)0#rpEWo)Dw1YwjAWSM=Ox|gpM4B*^GVe_L&R^p|l;Si0gjp1K0Ph z^~;S9gw$B8pdME3h37e}HKZGLy$<$K45{V!23+kO$K4#GWBIOa)q5}hG***kerbSH zi`xrq`5E8~GLp75Yiu!6)*%+p>0d1{PFlPw-$ogHYHiDUu*Z_p*NCT{gWa!md-zX4 ziW3vYk6s+~lI%!~QTZIqp`2$U1!MVAZ?r>@SJvQ%1HbQx;Ad{6dCCG?Kn<{)Bzxdo zROm6=#);cWe>!%7EljO}MeQG`)fvMm%Jmx&w^p(kitt*?Ju2+=>680;@TMByWSbI@#REZp+_1D`Yo+-!R>sA{GbvV!i zC*PuX@U&BUqaenecWI{3Z{QzzFq>m>(MUqr(U$<})5XX#M`K_I$1cdl2jW`sk3v5~ zM=~n}8{i~dLn`h5M{Vc$Bcc*eL`lmeg@OpJJ$onF0CQoV>q++U;t7HSKiMdjuu6fm zbDg3KpjSldN>IU1REiEXjj+4-q$U$bYw!KU{qyBSXD2mrb|FF{+{b^g%r)MkiZZGT zxfDI;o3UdS9LDP8qQKkpZLtsg0(4eV@j%_hgJ7O^ekRBz{?=ldCi&#C zU(w~Sk>b(usmqIWy&2`{T2%qbYR{oEE{i+?=&ujZj!pboRkrf4 zl42?M;goXE{$nuu*sOi<=ra?vH6*6so^b7=x}-Uh%l38M7-x2avB(Smb1J1VW{6qZ z;sf5*t`yA)bUUzQxHDe!sS$E%*L(O}HVtk9M_%cT_|4kWAI%@xWOtXZ2r>7_14~}K#uPcO(;f!X6|D<4o zD#~?^V5zQna>ZFi?i#xUZI{<#mQO)ez=IK8aRar|qy83melNbY&QXQ`D4x|g$F1+G zrQdBcn&%VbR1xPeXf?-pMMo^oTbd16Yx%q3MmI2ovE!cCLweozc^njUe(7 zey*i|ToG!t9(69(q5bRc7PjxJOAgY^ba9F6J{7qmau0mxWAN><0*wIw8ncSt9u-Be z1EW;Gpo!1aPj+%nmHreU?$%cH4oT#jzt>x5sDW?tyKllbC*wb?E1nU4Rg*Y7EkEfH z+`CZTNcX8SbWz%4Uw2Ip_{C})Fm?H&OQt?_=n?(;sj;cjUrTMaDoZcxt?_id-2M}j zixrFPEBm<*Jyn#6ULb$}sqVafj@z?Rw?%lX6U?hK2RG~Bx22Rl8F+5LxYn2(qHX-+ zYH+DGIEf@kR%rrswxEy-^kAS85Y{LaD6?eOF>u4p92^}^?NwoG=(42@i1`} zXWje29>TQ{ThIeKI&;*P*)#JIhyx^lfUlu06WUYr?Pqd+jZH^~Qosl_fkZ>5zWn9= zAH~<5GN=Nc|7*P^f3H69Hf@#Nd-P(w)Xnum5*;7dk|M}$BbPNQ_VU0aPc+=i-%Q61 zM2lAHfe;evVhU4+ZhRJg;BX*&9RP|39v-Y9IH`k~{|2*7DbCbQNTGv7sLa1MX~_Jt z$HYZk&&DJwpJ}4x`kBm2#sr|FyX3>mM1)es)mVE&dJN(Q?uYAML;Hg*Nz+1fLY?}? zvUZ#PlYd^?tkb%yYsU)$o~AF#Tg{4}&U$Rz(+*0VVE;@Y(C@i~AWu4vgU>R)LmA}y zmHexmh|macS_#$kxbL{}^G%D&#J! z`SU?&XVs0%cIBHy817Nm{Q4ob&N*=lrsE@AI?R{!Stlm+XAQIKwUp?yAZ1-XX?33f z?w4p;ChQk--edf1K0NEpiLGXD{VXJ1(I zC{uJHeO0w1$@&oVE&ph~S3nig3VV#a>mbh&mKpi(G8Y75_RCRL}h4kpoV`1eGkFV??P#?sO;L4RnVD($fa8i zB(Nrcqd43z;7E6%4yeVN)X$W$M|DTwB`2l0Eo@kB4kp+g7dD~D;H3?Ym&jxq07M+KR`&vm_x)%$MN zJd5IF8N6fpYTb;SE=-|j@I#_b9vh)?^JVB1=kBpp(lY05VyW)eXN^sNu%ZN;F)k}~ zezLhmKwKAO0QHgm8}5AW=U{+H!HwSG=n>X3Db|(v%>%~QYKau9V$U92jrelj3YK#O1sFIUyxqwg7>b~b;d-90K*x(HtIQF2)x z8d*(PsOp;_CbN<%==*|__$qSi%4^hO-zf$Ro##YiavF~FXKOFhv`nrhB>IqU>xwNu z=2Myy*WB*ofbi#&kZ()%o8N#K1xVf?fre8(!`LSxt?ENEo7;zh+eTLM{1pKe1ZhW` zv=t~!O}J@~@CH3PF8gak(OX(hNU`Lpyw7akLOfTtp(6ke@X^uK5$SE97EIVhlbBe% z{rQsR^MptSTx~Zo!3gn|#-9Nn=N zeZLQzM`*IdodG|NXVA9O?W^0DP0DO!&CEVIX<#LAb?cw<2P0>8ejN#}pYQ$h;lUqs z{E$BC|JJ^o8TeOpcsXq;sTBZ7Z0 z0bGu}xBFi8w)7Iw}gPx;0`4YTaCi>o8J6fd-to?_sa zm6sIVPRziEdPHWxbvw4#Rg@p8L)zF?!5kp|vx$zcZITtK+y#ZgLCAkaKp_d znT`L!8A{@a>0Rf`VqQIyr3Fl7J59&Aht&@>kIc!xGaAD;6MugyVRx1np0Qo@<3A*q zs`z2m$1i5n!=bDtM6`M16hb9`TXxPk<(A&!DE(Nvf_r{g5+~{IE$g9S=)gj{v-bxy0uk>{#g=L7 z96Y+yYB~+AXn~}uTPbWbA4G$$Ndu~Ypa z$*$(~9#ICTPb!gnXWN-yx30hEo1c{Ew?5C`nd2dp#HLn_bL%YjLF10yXlhmUn+$!+ zq4+U(m%j-_KGwS6>4_Ghadcs}q{_k?r@+B=+v>+9;3mqgBr6Sk-LhK|NriX;eqbDE z9)mOlDVtmF-39l(Og9{OeA;hznoH!f%S|G^bxqAMJXuKANsLJlhW0$Z_S3q}0>={~ zB>wiq7FRQ&Vdf-xn)0H-v`kKLfAqZ^3E zwe?rS8*6+udsC}Wc@&M7cT?UW8LgkLiEVQjr#ISLqJ7T;)n9~-ugwieV%GhpjUwz} z4snKQigiNToS}Ws-CQQx9Rg+G@OEs25q3sd)ehy6OzVGuLTos0#EVtNmLUZ9-yvCW zJU6XA%>^EUdJpmkJwB8igX4`slAnrgIw_7V;Khqs3e}$s)awQIP@(9PlHij_&P8gC zBJ^b`L!!vKD|E>$v9EEr+i!#nl7_YmCj{C`DDI)JyxwMUucI4^BVL2&AsKC_&m4ya zJeNcchzuOBCMvWqZ46+Ci@Cfrr#<(~`;WDRj;_axZx6qr2$mj!?Oj`rQK^f9nyw72 zH3b#NmA+`xKIz&YYoA24U)>3>uy6{g<%~*O+%`9Wzxk7$0_3Z`dAQG?*aolq3NRmt ze7d0_&U6b`Xw$Sgg9+)FzZvQ8Yp3(kY%x!|e`GygqkZ1rD4uy*?JqYSS)by#-1Cu* z*D<$3u-I(-U4El6BTNi7()N^6^smb!D`LY+5S@`F*QUkf%1l1GailWQLS{eGNuH}+ z0?;ROpUuUD*oVaC$P$BA=~%6Htk@4vdlJArXML-@mLx+X&;DeY8f|ic$NXG$@GRq^ zJaG&^^&TIbIrYlUp-i~6RY60lKjZb;L@VG=JtB5Da zv3?uu!-b9^L6YQ~mqk$Pa;QZ8RmWlYW|RmEWA8-L$NHoeiN@WwTm9D^sEQ!Kn#S@U zm3sa--ERn4x}LE+{xKR6OYh=wTF<~gB2e;LLUvy(1P3;SZoku@$f2lwQy>rTh5c<` zNjgxb?wd63H^_TM_9;0QHF+^wboC~Z&2Yz;Ui7t>Y8d@AC z)V6W0VA@e*)Zu0FZ?oTcy)D-}TgDx}yj^j6i8~T5jXhlYl;iH$G$; zd+rxx9!WQw$g~|?-qITg&9`n!eMDaU(p0IsaT9%cKyWOuM^*l_hdy)sMfZDYUs^mP z-;TA^^dWTSfy~SbEQG-$`;H7Ne6JsQtQWK&Y*)B{4SprS+~&&oi^{#?ID|n=HUln$ zZQs)?x2`!3snZ-{Xd|ruy4APWt{^O3_+jDPEKS=Dl$Mt)ew5VsnYn8p++tP`ciYOT zW<87gEuebqTBeZV+$n5h?Q$L9;!GjhMcsv8XC(NIG=FAPWi_CJoCWVW_{X?r zx-NCKXhAFVF*-caNZ7hjsciDOjHjE}W?~`9qG7g81Zp!2^`preRBFqj`q2`# z&tbXvj@#Gw_)P8jh__0^qg^C!i8-Y6xgvFye_-cD;qL;cvqYhbgcLU4!@kLz;K>@R zdpCK!b|qZ)feDMA)768_H{eC5yyxE#jjL)jfw?H!hj~mK7KdfoLk>9Iy>onecg};$ zY6R!Xd|`Xj6#2o87Oaymp%B9RZrP54`iX$#mrr%xOCxkBYQoiFZhsX@z4L+)3JCEJ z9aEhA-k(=Hr-j%V#qnTUH64^5!B|7?T-06N?j=1W=2~5rE9&9}SNXqIo#eZO5WnmC z+)CKHR&f6A+PJ`;a+48Nl`;&l0X)0Rwk0MV@|)Bj&W5!ZK}5`Xs~dE#KK-;^cDT+s zSov+kV8v1LQP}s?vAoj+dUc%cS6>+6STQE3un!=e`efvYY4p$eO%+)Qt{f0~Rp$ul zdwBdyy|Sa%<1)R1!)|4{SxHG4p9_G4Uh_5qN3Akn)!iHtC)KL2IVb!l?dF$LT@*8P z?q3tzq<&p6yowJv5^pFCey$sYmRvO|T2;C0e4(6P#*<(dBEzw`a|R!(R$}s$+v;^E zy(xGvT<+s3vpUvz^>{n!KMH${nMi?ygO_(4eSIxg&`SLtMoo7Fok@4z4y!|tqnjk%|1@pF(-*|k-_kSFnhd*2Y+s3u3sG_R&tWlfVv(i?rs;a$dYYSrUQEly2RBWnN z?VT7AYHzJAu}9Ph5yS}jKKVWWKu%ugb#n5#@9TPBSDnMqnm@aLooVaMrV~)OCJ1_v zj(@ssSx|t)K15NTvx0zrvR&BlI&4~ zBae>HcCQW>*yYFS&U0Y<8<_{wYk)+$W>rB9A#;N&0#*^^nkHPYNQAsOs){LNjVf1O z|GR=SjAItVWj{*#W@s%|nTK8d3#X+;s%>Pz$5$DyjYfVkn9B;Woq7;60#r|MeHVq_ zTQfIo6FK!dI$N~u{Fo0Z`@?7IuIWS8stZrv!o<<%&}Z@P*Xn%#>s0xyk8I6dFZ^1f zo>)8Epf#%jSR9C8J$Kn*_QTOmt;R0$&Y1yv1UA$M(SFAdH{E+fpU>BNn9DUi>usvM zV&n)s+ts%UpSPuZ97S?G(Bj33M)GI1*L{FalS1ocuY!(saJ(1Rpbe@7Wl#)(p~0LP zX7HObs+c@-I{6vJV2ih@Z39=Ymb?BDjH_r8=X-;~8>zebz_MmIGxn$Zr@n)RJdKV4 zF(6O{aF-qn#AROm-UKCZK603cnO3?&+D$mb4#gAeE69%y?4Sz%TR!JiOvIeAfg0Mr z@rQFGcmqf@uqy2MMUW^^=CjdnholS&E_v#CzcAvmjLiAs1Ll0au1Cw`TC8|Cm@ml_ z9KvIgS|U0q@tf~D5{@IG8kEHf9IS589@xer^fTa-_XG3+1qVzX929m-k-IbVosmhq z*1Q;1#R*Is*!kE@DSU!jOf+-5XeHvewrm1%ALWMDuX9}W1AcH!6&YgSwS7!6pnTi1 z;zGLiU=1bW?)U_s+nbK>y%1~P1Q=?ZX-JIs*r#KtWY6zb|)s(3-4*W zs9o$c-bh)9nq9$2lCLf?_59(4)u$y>_kWW*5EznDuQJpb^D7>; z`7X7YEn+3C5d5A-FK1A!dyB4nvnDXJ7a5DRfk?I=LNjc~K^aD$l^72s5uKBSdz8nF z2(AP;L(agC&P>Vlsg9{_(>N|gEbB-avaKml=9Ao62~h9Gu}u+y2sDm52dP8sMNti*+oV|9Bu+Dpc?MtB@liuhTzM2brs zY}IA#I z(TLxcUCwcEk?_A$flfN^j1l);yew^QeiCiQ_VD(nA4-A-$DWgukV3b2Z9<)m%#wpN zix$zv%;p7l_@@_}eE?e6t8-TW3i0m~r9YjEkWYNRK)K`qnYO_=5hC`pamV#oJ_)8# ziOk42%AZ#}CGI*Z0hrhSkwhyo_0=T>&|Q4)Sv9U_Gyp+clQm3ip00oY{DV_r-?o%h z;(!*@;yaTHqc4$ZdK>{>7B>_P#4o;=JhBSC*5=_6di@vCH9_7pjUpB=(6X5cq#2@S9iyla&kn1x6wUr4jja z3Fp$0EuXS7*z%i8kolRyZVoYy0pWvl!ASG~Zov>-(P;FUb!i6L%WH?}5)ha0srVZ? z$l_phUwwnS#$7LaQ{n;99-(WK#4ayd%9!5l>yK6Sgr}CJ3KYmDYfcbTDs7)~BjjXk z#g*v`fOcw8r-284mN!o}EvDx5l|=^Zqjz~!Qe^M7e+ryfPwUiEiz>S`ImitN1Iu5+ z;*vTb6P^#>N*2IdPUX9~;tR-TRoV6n=#NXpICFmqCxk52jMwyhdy{NDgJuiasql!A zy}B#sQ?A`wHg5z4Bzo3Iy-kJ-t@JC-V7GM3Rr1G3 zF@;s^bzfv+fs}eEF<=MxYaP67&Z^<09l)k2PRcGwdKlXFyFZNVSbozq@|p<`*tem^ zyeZ&5X84aJPVS~yf2K$yS!eMX~*Rly$3i^YbbObz0@kA8Gh ziURg9!3DIPAFab@Rv*-|d}uwMkC$L_oP9ORx$a5CuvN2piHn~IBJ)JGyCQxORqA|| zQEkfVHpYmh_>bgo=DWBD9i$!GzaPKYEtoxvy@?|*?t&XKFg7vXjog`jbKu;Wu2<$C z2X3cCRMcf{2w^u&rT#@|1}YDjI~rz;L`xCJ<%}cyD=}Gs(jifx?utc}CeAew<>i-1 ztL+u?*)mG7N>a6_-ZZ9C2md+{JLp5p7ML@q(Q~M?69v~#bO7FEooz1sHaxh`d%3L)OefmT0gx!l**JoVK0)5m5nl7R48!jbF^dYXap5uhyS0Sge zZEJ;y@{K1k8&yH;#{->SP`V)6&~rM-=9v4VPR*9EUD|_?wb(q z3G`rbZ5>aXlQg^5AHX4neVIz7GbT!Jp#jnnuIBw-EYXkCkmM54+z&KGBK!4@r*S@i z2`Ul4jamvRTv_{XS{f0*IcEEqa#7|V>uKiJ647kYEU}X-1GKXHwve6Q|B-O$;z6Ne z$A!@_k%)~DHo5rOuEup~U9QEF75y55KJzH_h$_fwdz7@_vx{Cu;Mj1D>-v!te&7nw zbMzpv=XVa9ua0uyX-7y|&Lk=&^u?FPCTR9!0e&;d)6>T?2gsQo{q1KlYZ2FUM5%}T z7?N2#zA?$_YRYPbQ8usX?;KC+6^+ax*GyDQ{Pk|>OLT2I?(>B_#uV3goPmlAx`~lb zwtLq!>EwIm(FV+`REIb$m;z6KbNQxNpswYKM-dVtgupjfU$|Ik1E1bny$v(*R<7`A z(L~7o!p=mDz76mbTWOU@il8O%hmUnZ&W`$tFM>caIJdJ!OJyGpqThK6UVpFkN~)Ze zX}rnpi-2U~;nq$zG$Lphdqc7rE_Y3SL8OxI)E=8;ZUD#w)B9NGzt;LOf5dYf%rl8l zzG!)$^@Lk8^uj#cu;2@~NyPP|F9y(y@nhvRw~4C~RnEDCS?-gwSLwqi_ECpvk13=- zb@jUy9b0rY$Mi=eaX|}WN-o6b*C9~Mk#;K#uUZ^bJ%o!3+m4j@{@9I#Atk%j z{<`Xf#&sTDN-Snu)q!0|lShVYghm`8GdZ=n4)Qm?S8zEfv{H3asm*R}%?un1r7YA%m0Zjf7T8YuMx^7p>3 zXxD~q1KP||7b@s(OQY)e4wdVHdxf7=xsSQ}Xk+Ap3zJj;648FPE2Z->8!)^Pq>Ss* zepG?`ke7ul^73tPWWQ-P+(jFp=IRdc6XBwb_{}7S>|5o8i#|J>!65msY;0-t5fmx5L2LMTfA0y@mkjSi?+@gqmIlI6fo|?mk*%j%7dG=&3ca(9IC+)`mH(% zBr$JS2-t5=z9Kb(2+xR2i zB*d>>tNX5D+T8zU=CkM(MLxDfpy;jd7{HtpDSoD%2w+)k&&R8WXQcl_`nNuLs-@3;SpMhBn~uFQ_mveQ=hWlCooBpg~eFQa4HBXVWTQ zaJ7HQ2J_>%?`&~A!jtVDa8&0(0nEkV7g8IkQ>dK3UTRUp@3Pj4|K8De52=peYvb4AdvvCPi znSK@$JK{}LAmRjlDKuv>5+@Ik$%i!5zVN3|3{Cbrhy3q$_z#5G&6MT`paW1Q$9nS0 zewX&J2>dL;gWOagYIX26wyop>EkJ|;08Oqr#_&vXoO);9m3v8?>-6^o#&fye31^eV zg-fi^hnAQ!xzHd?$^d`~##?ql)U&bwkr+*D{1|osZ2=|6tos<}_A+mo^`=M`sGWy9 z?vH!x`WU_SV}NBZvUqFERLJwS*TFX7O5wx%n1O+v{&woE`o({-PA*Oj;DOyww^syf zJj5Pji4ANz(htHN9o^`y0bk(!d#Xw|+1Fln8*KaIYPx?p6>5&eMF(ow6F`r=TiU=R z>`0k@%^Yony!{sIDB;gV%Z45aGEfZmtdXJpiw>7v)`FE->G$W&K!%C;cxf#onM)G% z2Si7WJkA7$;X0V#puVH+-h zp)~q#)z%DsWv54}l;&N^qQTxFJ9FH%2*CM4E`~V-MFZRs@XITz-vs&&%xd(3`*N+QBeW@g&aw5Yh)iahFum8NvaT(58;??3f-Q@7^gM4a<7vC?(2qBXdP$4SxJGPAc zJS4aP+1hWMHXu7!%YrF&$Lziwu(~$qTZorkB<4jM7^N&6`q*_hUcK zJfss8EEbm6WSm+`4DH;lUxBGwaXRH8*<2Armd-D*KjJ_9DSUf#Y(sgkpP3#*&23n!5DQNIx6RM~PVFF_k{kZQIB}0e@V0rD{ zBw;dBE!#j_3|*FH`#3-w$Mmg|(v~cGz>3qJ+#}$&2DJ$+nxKGNCI&yaGon>6tuCx~ z=`7$SJ7*gz-;tZW>|3RNyh|1>rR@@V9fm_K??+LJEmwg zp<@B^1yc*lBA`I9=mR_M&Ci1c%Z;N|6=zh6rJt2?pr)Z=k)QzFC3pX$ASx8a;F!<9 zW!IIM8ov7j6x(U;D~9U8KnBmabCtMg4YT@@JSUJWHxrhs)TOK`<6JOyRIK(C$pzRi zV#kJ`_%7=YM+AX~4(8QLA+EYP0M9uJId2mG#AwkA_m}~Kn)m%R8=bR4te z0)Udji`#%FR^oq_Ut_|pa(*zqi$-n8OIxaku?d&wdQoJ{^-xlx`lNd~%b(=i)w;(F zC5ek0Gn-E`5Oo!}{CE4%r#6fGCqfJ!lMZ?Qf2``#kY9Ch(IH&QEx4*=v!8+;ckF?O(0Q+8jf4aX)V1D$f-MN7J7()|l;Cin*60pqYkSKI+7@ zq}u1ae5FBb27hj&tw?zM2G-*KL}%Dvhdn&x)xKEW;<9DLw^Z_!t%1#6PA%lwFSKKr znnz!2_IZ=#O-6B>b{2KQ1I=5<-}>yh`qM2u_tFEM-h==hpkN(fP4(P~w%bY2`{+-D zJZMSq@{qFL=!D?yNfYOeR5iM7G;;QDoG{7YIya%$2%p8jacgwLW{YPA zKbcMJ7iS|&@CGRPb>@NhAdPAa9U^!18i#RCsrvFVjsgZHPKkB47CdC`rh2U@diKuz zX)E%{{NN2b-$owl1Jb^LT3QVS#a$zN{V*v$9WOt*W00r`HmoYhl-nxOiZE?zG^YKya^R?ftcNXGfm&uo8^L*|FN z7{mDjlK}``W4A!gErwya3sEx`=1t+{w<3SKw~v_Q z?@TpzuBP^8*%d{_sAOEH)Ob8@g+ZNwT+NlQc`|B6r>^8EGkuo|rO+G~gXJxs=R zu?}HrK0DO_c6lOqSs6Z)6E@frCNjtxof0^ww3B_ie>-72`AFj4bH~Kn#X_l1q@y>V zv{yNte6qlUuH@&|x!JIw-Ypy`crxiE&Ujr_P)5Y2X!ljIg|^{d&qE z6QAQSlf>KDINIdX!|RB}gA%5jIN=#sng+bFb>Q?SDz;q=2fJe3)88EimRtsBX7T9O zFfDq#97eI|iG9<;m*hF^7P1A#53bvOS%=SVnWrI+-MEHY2@@_QZXX3{r2aUmK$}tQtYMBh6 zut57o-&Nk4s-VOY_}|!ak{wX}W&i^gfab@W+Xim-=lBxn+PnT97&HFehPB{{dHb~j z3%?qBtTZ7{yI{|toWT96X9oKgQ`7I3ak17qO-=l#;TAuP-VFsf!GmuOgXaSC?*G$} zs=&3gu1m89=A=c*V$P1d56;10d2LY%hFrcHY%SiTl_J;pX}DGT(l502_!0F2pv;fEcWZUlL!xbxC>dH}RnbgKuX3;qB+`Jtpfa-H*@_2i9vQ1H3rn0?q z#$QLVX4>zM<0fsx$xLT?E#vYNg?P#=o`4k@%x?O1k9|RErY6p)RC|gk;rcH?xAvqA z`opv3{N<}ZWD(-el;3?7U9k|k9$SPs3Q8w;XbTkmbG5Xzbaa8wR5vP96iy}%tSYX& z2y8eBIo7^E2I+D#GD`CA8-4V<&8{=uzHKXnHFPSdp$E6$HG$u!XLDil>SlJUc(24t z?gbK88GpQ!x(y7H=czhqLolOBxsUG9+&r&@Tz!IOmsoCF27RmT%MDms3r&k)3=_5v zc^A)8c0ZNR8J~%!yA&Xu=J`1{q|eb-ef@Tp$_#62mfk4Bk8V<1|X-p0uIm zkRO!`)3*DCE(Gi0yf{g*EAhDAXVBF?6FhgKc^3suQ{ zBnA`QKe--D7cJqH&ukrpepc9z-vX?atwJMG2qf3eDZRF|#Iq<{NFdql)bFzIu%u|s zOeK!Ja;~Sm_tb<2U+-NdZX2d4U1qhXZmTZkTFgr1^jugj*5q|{g70KmT`Iq@PG%=x zVr|))$u?mNu|0KB(6p5vUArFdv|lTHja^-YZZZ}h<8fYpuPr7;maHuYT^sjII!v@v z0by9NPH*S<&cSm-UrKe85 zJ;Rt11D%iwoAcK)(Q#`WI=!4MO*7&iP*)sd5^ra<+P12{qw^-R&HvUpTtB@a{16Vc zmd)UFE(&a*hc)E-efzc4*LYnnP_&yfQ7TVf6T{@)7jnIw{0ym|!EgNS&C?%E4wk8C zz4ot`O=RuP7V66#UNK&Fc?=#j&DP&umXs{Wi-ynxFNrQT+V+mv%izqZ%WEeuJc@Cf#;lfU@|k@!7IEQ_f=T;IT!J%wh4Yr$r{prbp8&U?V}PWTBQ zWToTvVc@xV_}=Fssk_SaxA2BR5twoiGt$aR)T3rwgnvxx4#3-Nm0+G0;$z(wf$w|v zmVNLB5uSK4{9V&;YgzM=KQh%`#Orf9*bgk0=W@d-hH>ee6`NsHcyxgc7sH)%4C&9*~o($ z+m|%x-9qlyv}_JAC0nY@BlHpD{Ou}K?YfZxT0I+p+3Y;shE54KV&xN+d z*G^4~Wj%(1S!7EV8e5|Lo%TC*9dh@bTrSYbX=}+GN&FA)083NVu4W}BQ;b`*pYYk+ ziXjxt#E&GO=oY7uAKR%mgP|{V{H+fXT6u$XJ5b^MmJp?!%c{jfTb9@2$A3;4qtzM>Ey@lilxo&oA3*HwpJ%ROnWPhIcs?hCHk3=y;8UfMf6WTydQY zh;*N>3QzX2T0LweLf`c_i}Et>Ung~QXfqr}VDvi}V>bP^_OLhkVr#2Ou_LUKJq6km z3JTXEyB|AGwk|uTXi4k(xR6MjKc~t%NcnyqES^Uyf+y7spLAC~s66m+qK{Ey*`u|O-C@NWkfd+lq zY7~0Wq_4@*RSp%fG&wpNpzphE2$S+PRC!Y`=4u>O`cuY)@!aI< z7+N3oCfk(pI0@Nk*1(tE))^Hvk~gbrmVcbt*dhFUc=?!KRZ?b&r&P zzjoN~Z?skXN3vCoB`Qvze_YId=*t1bZ2Fv#e?dPOPM>_YaCLlI1GrC=Ppt@ifgU)N zPMAbbV|AAtzREP9d(FG1fEb>$(lP!2*UG5W8tmtM+?r%|h^-a-i=iPO`I8JEWS9yS zBYwI);n5p_ILz?0v-ZC(-d*14M#`VSo8DI_a z9|_}K)aUtLxuY)c5)+TT1?GhS!1AO3vuX?rgKWw*z(!&6%O{muqS_= zPD}wJ+$NiVWjE8R@`1@%PF`L-{d&!*@UpmU?!^Iab57ihaJQ+;Nn&C1#Z5kuR6JOw z(J5=ueudQ$t)89~R~q_{Wbi5WGjnXbPa!cU4Eh{@Cg^(L!Bp4n38L&Mi$+D-xxm2Hjy1BI^EocDKEj{$y=J}{Z zX(%tIX^@NatnjV{B2?u9=ntpMI)s?{8E#E5f8+AFxES8bOHH>eCKf0g0%hB8QbKhf zx5h6PYeAYS942$fv9hQxjCMYQ@9N^}3q5fYZP?DuX4t_aHdxy&)Fs*LLSrs z>c)t8!CmgzYaMyWwMSULv4F;eOb%zyH48rBRqK z_$>-?`}=Pf3Pl0Y7s%+dldfBu>tRkf^(&LR8w@oynYU;;FkIr%VBw3)`)Pl+p<7N`i|D%uAwG*<7tc0Q zXnSSPV?cmrvdY6&o&6-j2fds(T7B=+23;6-*IhrXbNZ&8YL4!(tbnqHtHYm^I^A53 z*ycJMUGNt64~Obva^_#9yGq13q|MGciZ9$@;7jxN+@E|ML!eTW0W5@5x}X+=p}9Zt z`0q}NRMY7LdU~aSrq}d!>V-Jln?@CTv{LnL;9d z+lv>?z_`|^vOWB@=I@ zwcz_r1Z8_6#(&~M6zNYj@G8|czYdq1-Fu2A^t#@dPDL~&jsr0}x?m&3B=F()e}BJy zG9B;2Sd4p*g>qm{=`F3a{cei!ar)L^S?AS2h0Qz(+n&~nky)DfKcVfMXgvQg2ejwr z!R6Q_PS70w5#PW(Jj{1u^QVc0;q?u%OXcSK>4_a?QjN`D6DODVgoFfm56qO4gxAf*%1BpR=Uc$);}k~TmiZ%|7@ zBgH7fe%RhiReKZnQNlQ1x88Eo4r;mMC`@SYce_$$Rp`uwceh8e=LxO*>QvT4QP=VF zu7nF0q{hLQ4%9D#^&agC0WH2N;E9A@zBAx+^H?%P;cIU8-r9jOw->b<@)svpern-{ z^H)XW$Dh9fivQaJtb)#S;{Df%v9UYBf`V6caL@&{WLJ!g$MWR43l%lYRHcJW!;~z= z`v%>$QYLk{JI$`)3oecon`biTzXRh51X5EH(c>$%yp?fBbuRLKUAQ?MWb zN{pYISFq7P@khJ*&pHk*w?!P~*r&;7b&0R8FF$`UET8#5kG$j06yLbQ_SK$oJr_AB zKoNOud_U)_+_&Zv$k1#={3nKQS{-Z`mCb*mtExXr=2F|aAQg+ddk*80%! zb}zf{CbvC=Ty~zF!<5sHgT^(ZDBNVS$wV$ZBIah#8(9^KQpmm8u9Lo4#G4W$xAb~) zCzepG?KGgTJ1A=x$8l8;?BYQDNZSGw{?&Cz_ zaDEMhu37t!B&CpEMSTrTkH+q;Fu6mq%`P}cj$3iP9Gj}ENxHeFv6t;yM1n=($$F7F z{gFFD?s%%m(yYiCAvnvRdN_+TSh3Qm9J6%&d5we{+g9w_kR1aF_dZ~n*6IeSXk*%I zi-RII++Ul0jGxy@LF-a}L)*%eZ;J-gbV=nDSfrUmZx4c%q*wVa&EKwe>W_0TpGT}2 zyJ<7@CrS%TRsSVNtOofk;N#22m_DsaoC5`$=c0@4LCr*Gw2KQE^7Gl)s^3n&?Yowg}Qsv4t?2HH=%B(wcED}(SDRBhqA5%JGj*z;C`>g9}t8sYl}Aa zB+rMsZ^P#WGcf-yt9{+y zHMDD_^2c=r7Akw(Z0;--NUCq8xxV>3a#1qXs40XZz5ZmZtgmKjqFlKzZ{!Z z+ZI)|hMwoY3U{(8uN9e#>*WD74c^_b^pRhtiZxX&M_$f!IRzs9mpj5i?W&+YqD3%$ z+c9Rx;r-YMyr8sguv9Uh*Bu`^=!mZ!(3pIIBzZUXVJ6#AjEAVyRE2h&NIPNHXs5Cs z^-2pvS4XAghlg<-#1NNVVJQy+<2PZ*v&=k$%1hTFrqQIBm34-u$btNzLWS6ol(0G~iqjkJl!(~7Rm-S%F3wl1$spmCbJP?$JZMnB)3-y*%bO?}D`R3cKA@);%#f=s$+c63DYXfTA z*7!uI2hS;aT9-D#Pc-`RBDy0eqW1vJn!QVMN0}&F>4NftABN$7QV-R$Q(G?|zF57< zM8A`2#s`$#t2hyXIoK9zkUwg4RG(P1#8;2-nOwKkaUVU0JDaA?@tL}Jv?aCfqHSdH zUY5h9q5L6>>F67KY{ByE(=4w2V(wpL7sIH|{1PV1k6cn-=X}b6`&g(e(Xxk3TdM0d zS0Pd>YOPqQCW@QB^Z8Na>u#%;sr{&)*t&Kq%bx{aYhLu83hbLTMh)-r4sCw;Hw(UC zvympyKNGV_s^pG_)2cT^kcM96Q6BGup`L9vl3OVoB%EEP;pM|^7k?k61&tBMxoWX< zeMqh&Q4}xr?y>;u6oJZX|9Oa~X;3tdx~2=%4UGhR8K5ke$nb*5wmCqI5g7CFt)XuA zJkd60@*19AT156wW9PpCB1)ajiF(#09IyaD>8ou2b3NS~uq8o!C4>F`JiytIp1*@H z7MZ-+_w~Ue0fqla&Tb~4QEvKn&c&}Lc2Yv6o*vu{RH%#jkHo=@^JLRF5^P&Ik~w0U zB>wQDMnB>&_J@-fpgb6#;np`N@&Ip0EL&-G@O@wWv+DhqrOlJN&l{FE4#8Yyp4Fza z`S|Q6Yq=kbso{>7<_(15 z;@az-aF21*wv1bVhx2#`Qdmtg)Sc$SFZ zlCZh^da_&H;Ud9piKQ5~+poKi(+7|Jevpgs$-gG8 z7DhK%LlGTz$u-!W)6$&z;S>6>>i99ao61$7b~AmXsMQ%k;?Iox{X&;$uIyRQj)!Yn ziI05g0Ngi1O?(NQ7RqMJxg!W7C@AkOx9RA$+DT&7(2@xh$Yg7*i1XLT)L)-?eOJL# z0k`cMHJ9%G z$JFXz>im5XPXFm^-SFuoXGT$2G1A(_WByyq;L?}#^Ll+VBe-E znn(eG>%Aq1-j201+x*H01o9Ae)5LIH0V(a*_5}0Nzo8BvHYD!uwr?>)_d%8B>V6hrc+3#V=CfY0-rK|Zdf*^68?G9zRu&t7d<0Ufd{sBD0b-uCoA%P3z zE)#spWAHVDQa=j#Q36%W8ddt98I3;Tt7a;BkR4swnK)Kmla^ zkT=`dxYR^vX!9&lyYf>*gR!$c#{`uY01k}u4vozhbYu~YNFWla#M zW6S06aY#Tq$CoFMDg-Ll{K~B~Rp!}>bP|3k7=K=l+DV79JpT$(R5=Co`RKc}`o9Ba#xH*^A_g*`a$L{V%VCt;^f~xHD_#!x0kebr#eZ^xUDCO z9?(07f7b+w_2>72N2au)2Lz*sVU;TY$-$uyt(Oq=GoMdNG?H(Pfh=GnJ+YDzcd(+^ zmWkb`+!+Rd;GSxRvPMq97Dbgi>*3AS>(H8pY$urlJaxNX_e`p$sbE<{G%4=H-KD~Cvy7C!!KlPMa19wB!;ls%incujpnFx zOMH)L)C`4N@N5McY#(=g?iF}8;M%^6+1&@-A$DwMB0Y$q+g==lV*y!X2DiU@FTU6A z_2a00;zzOBBCp>x8sy~#-07!(p(5$Zcw80Q2O`mWbUMsOipYLa=&@p(={u(sHNgF< zF>9EkD{Ipk>%qk4HCd+QU&S)40%X-#?u(i8wi>1 z4i-gpqQ~AXAj@zr2h;DMi9!#mnO~sZr_bE>>d2cN$Sb?FYb%5pZETB}{hh6eXu8(s z+t?6cp3TnqapJr9_&*Y`HVdeAB-s8qzm=h-A~4*{_pAeMi7#pL0^tUs+F;o@QpuAd z(sMVx6~M9wSt!0T;`d9K0Ej(x7s6C^Kj7|g_@LCA@%wa+@7z7=O`h;a2LXhyk&(59 z8$?9I0b|(1YEmTjwMnx&tl;x~y z&$PGtX@6aVuiM!o>?>~y(Tw=wCL}Na)ujgk__;2V&hE2z_fji|NTFq9g^u5LwMhdy ztcqUSZLijo2g`3om;5!EoVl`q?0D^>2s5a6%->%#kP8gDJ?VPYlDswEd->ww#)8V{ zr(J!IJ~4T@IdKBl3X!*0H=rpJGDux|tF(!JRGfq;g4$q?A>~}VMeAXZI8sYN>?8zJ zu@2N8wp{lQFY_7Hk59~l^ZN$B?uO(vXKH`=;L!zhaRATko=ZmE;z{wfvrp)_$mI&s zI-gD%ho}1%I_Dr{ljU5{1{)N{fZ%^D8t8Ji##QutN0{=UEd&}xpx>KkbwhM_X(U9G?;}=QQC_(?$$(DG37Zl9 z$DeU4k@+j4RYINMBbR8BN(pRoBc9za)Jm z^i-7R-cxP9PfN7gEp?|ga@&ihXdxkcB=7Et_-4z4>f#UYy841~3=TC~zz5;={&@-lwXv&7mJ>~Gwd0MqUEzKWw zL1a~Gvdf)yi2N@>jSGYK3#_#3X_feYTb&B1$iJ@hgfjW7TE0X?HEKV4*mv9?+Hi2Q z%R(AxgN$1{?bqZ;FzXp*S~PG!Ml`8RS-|h29y30FS0^l05|UFV+cEAtcV6Et#*<(g zvIZilrhEp$PQ=M;N2BH;J$vvx-4&bM#_ zO4jXZs|N?F;o9=jRKd?jG+KSAR7l>~~u*<7*LCkB;-Cq`j^tdl4ri_KVF*Dx^ z#(Gwz8*+2E*tcevB)d4anccTBV!Bm)xmv6)jI)WU|0k?)UDnc`Llxv+vJ^V!2=3W< z-jQmzLx<+bN+~smrRj_+2hBRTkBfE~+rgqtRSh)mQLk%ArxIJxew|UtBl%4JjPjIJ z7pP}+XWLUq84iE1lEl63d=+~lty zuThYf58KB0MxX(f{j>F-EfC2j%QM_@j;Q;S=oedq+gS^ijeIHP!{EzoN>I8pd0j-7 zV`;%Wnl-qoq_zuYY`%{8)07t!?)FTxIJ|lLhoOk3Oiqb1ow(T6o1dbF)Y(2gD)jf? zOQ;df83ORnU9O_~poW%+=A;fE4L26g(C>-$mrtd!>GRtgRf83J5xm))d;37*OqX!F zE?4Pv^Pc3SKyQVmGEJ_$tU25$zN<5dg{M`+oZ;@;efrOm`9IMAGY3Q;I(t}~Hxccb zQelnb4s;%^E%Y8nZ@#ZSn2`4Y?;OzxHB`@=c$KzHTlH*?ETc4it6IU%EVk$IB%1;F z)^aMp2H2~N8vTq67IT|^gefQR2jVsf`7sT?5vXi2-3JCZXQ+KN4bJ_a5E9t1qJ9Kb9c7 zmK=IFti~7DvMn-&XOw#^f#qs}j4RrYfpG?Ml6*Sc#4yCCylj#0Z|x-ebmV}Ui4{Ij zN{M`!M25rDD3qXlyYOoY?gGkFkCx}=?Zzg=DCjzfikFBE2p4N^cpk-R%wk;wy>pI! z)0BGThJN!b$fj37(Oj^whT?etDchQgffv?as?G*9fl?=*f%>#OpdAJ$N7lU zwbXz{GC9~XY#;m4Kwg0Nj^8t4B*jH)gck^J&TC=5xGX!q-I=$G(yT-@XG%vqf0h1x zTqx)zXoa6gFd;0gZNqA1uqZR?t|JReF6ps|wr`=ZPpUY|$>58+%_v-E31J=)UFx?T zdS2+Z{0nhYIp_R#G|-OT{Eb7(p`?@~vqN3TV}lIsevxG^>AtkY4{r_pn^X6=AdR_o zQF2qS5~xozV-6~SemLc9s$xXHN0p$+Nl?DgeTtLRx#kFmXHVu0F65m`_UD3uNSA;l z*Ay>D(L)w@jXNHg>m;7hRu<;O{6*sSI0A1S{#TXtIP>$VHLpfTE396JxRrgA^K+28 z`V~d|>(D>+{u>25|( zx`au?MvssfY#?K>G2i{(KVZj>=Q*DHzOVbb&hvBH@w&gW5Qum4NwqvkI&m7*mPTKe z!5g<=t*vz}`8rd&#nbOwofnIkB~evhTVU%qlc}o7MeM;07#3YX&fp`lM&) z1&U2Ij)FC?8^v5*^TIQZ?^py*nM4f-QY@tz!M^4ot1w=PXbx)k$pi8!2e7_N%xR!PM z)x!k(F)1ClEyt_F<~(cne&cH^75U3lKp@i)UvL!k#O@ zY`)RP#-Y1uyIgjif30Y=x=%?|1nS*nW;hXh#;;I6pw=LC8@M?2)G{+S%>>nuE=N_# z*ipaw_dD&l*sQSr*fQM3{+);+IQRQQ_8pFamyXlsX5{tag-q)w&#wInuo5#QyX{P6 zv;WHa{AtYGH}23lEu{M{)pg1RDlfDAP}r9E+S7MlUxls8eAT{?%EL2P+5P9m?CXhw zhlyMZi{XRyON#aVM-LL+_9~NCJA7dB=!E7c%j)jJeZPKHRd;dBqTM?FQ9*zi{7Ct7`M&oQC%7)j>w-6=HU-fxGLlhr* z^rxa?h|_t!cP5uW@>nD-$89IG)hEB|7nlA~-I>)WIY}4G59HuIhuz=Rs<32n)SQ#i z{uVuFLh8Qj#GA4;B84ER&27kSb}a2n#G^7OAnK6*hg@QEN1B3Z&rG(IB{VK{dXDbC zLq>GPj5|oZ>-Jet^y++P5xKifO-TvAN*MqvLERIn$q498zgQhs&{*jnUD>jhyFJo! zeCQj`4R9yUiScXIl_bQdkM(yh)*>!!1?i;&15!q_WJRL7b8>hwAdh$SEd)EEeyk*j z1`>FIJ=RwUC+mplA{;ZtzPiBy(w?u$H8;}bo$XZMj-_;ojTUSduDU{;H5L@XEWUdzl4c zhhf4fzJA>qMkS<$f1`A`U}XK(GSh0AuYGh)cNpH@)u{dYkIFWGu@Y?^*L_>NGC+MW9~-l){3y3p zSRMbCS=$RPfcQW(^8@mGpme+}4faJ!>8FD^DLjpJ^jLqB+bBF0qFXlrbK2nMzbyLaXZY3)qo@_`FuRQWfg)?T z@n0@W6d7<%>($#y-w8i@k9V_#ziQEq?n!o?DGGRhr?-bbCs0%`){IX8#y!tZ-c~8= z@ZZiWy1TG@yi-;k&#=xA-^~I_wgg!*%=uPI!^CvFf<5pp``ht_A|0tT(@IKSSt!~Y zYE5R~Sx&C|AGjEF#{>=gHqMJ#S~8^k8l;6z`P(B7DRU!@EKdp1B%^H^3FS%7MP(Zn zD|CKG%ppaF^+k-NN9ZbEdHNE&m)5rgIbLVQY$Pu; zyLR;lpWPT7P~lN|?6cBUiub{R!%31@m_g%Qv!$14Z3*$}ePo3zr)5R_5o09PxjF1k zCb4t=Pr$s~Z|?}AOB=~6EdH7816Nd`yjWc;dYq`*&7@Vm|9VL z^Xo+5BGRR3Sp0zlz;3;btLvqNBw2G^#2IEaUgdtm5u_iTXx+{n=>L^XSo}u!ceWOlZVhBkGJG3~b!zcp- zG2TcPww3BMu|vFUrQO{dqKU!D#bi?s#Cjra1c@PT0xRvsVk*oFQhLr+h<{!O@;5c! zLe;~DP6UCvZAu+8N#|9o?Up^M7~~HJ3v4%myDKCDdqTdIVOMJ27*N^+*76e4ZaH~9 z6E4X4F*}f%D}~H-kWUY#VCo{^_uLB-fcHcqeD$G8HK?wf`oY3f%?w|syiZVWFw==d z>C-=ml3yV}gqX2kSxbh=9-L;j(5MlnvDh;F&1mrqVzuD8Yb^}zF;F$N zxxtcKywYv8;mt%l>g~UYzZBfIoc9b~s{360^y51_4l zg1~%~L+54A+|?m`{Z zAHovd`{|V(JcX-=713=MF*7*kSZQk}%fR-Ug1~YMfvcJxJd&C$*6nn%LgGJ1HX6{a z@imzkxDP}2aRnuJiZ)zUmR7kLppj1eal-5iy4)a}as+(-2A_!&PAv8Z<6(L zSMxAmnRiWn%)6?z9*ox)PRu$iROYF3r{qs1WtJ$r3D(<8;H|Sq=*5$Dc!!93k(cx+o|nRUeQ3ik2RMV-9C}IY+Xxc zpp_cb^(3~Xg^a^R@V&k2k4RlUyRX9pvpEHDXVHodo}MmM`^;zQ{?9nNvX(7b*(P|o z1Rn7p?ht}*jZHg-vL-v{c29crOcK;Sf0{9HgNw{r#*~6bQHEgeJHekwyO5cNYw6O* zv&t8krO_KhkT$8`@@!;2+;$@+kGo|rD`LBt0yWQ8Oyr57`gxw8GQ{-;e?;J87p{QJ z8M(m!YmQmz4a`62V6Pw*U8ld{;E%j9sID6>xKrCS#L-I;j0rj^z~`hw8!7rPiky&_ zlvo6rO+G zKh%zn4oahcQ-qes-U}D3ZoC7Pq}{emU3lzSOzUN!^q+rJjjrRoTQhI#13xqzB8QH| z5U-R35k~wjExDsh9!tgkpGLLH|J&6WKke#vhBCbNW_>pXD6E-rpdtKgoW zrvp$`RbL{%=r!MeRm-{QN9Ls*wz*xXZO^pwPN$gjZ0F$7LARj(EYHIlp{*o%clB}e zb0s}cIkS8BfFr7-W^XE4IvLmwKQaJCocoh1)pg&@0sNdiD@?kox07w+U zH}z+j-oNCEa0t*@&-;WWj|=+>b0W0s6CVp>=Eo8gbJh($To1n0vEg~&#ftW~ho7+R z#k|h+!S6Apf&N~(b={eIIjUQ0P1Y!tbQ0E zRtpe%MFw5y;6bkIA@b-WMswGo!Pt`3WwWOy{CUe9>ph53jp3RvI+N~y6~GCzAS@81Q1V zv<6IlHK_ymRl3M!wz=w8+xlc~Xa4n&XI>j>b49;>n`gn2%^S$UMyUibMCRsIFm(rtOJU6SG&?U83z z%cL`4b!{@l%ai?icbZMPI-Q4VD@>C~b1g?qio!`6Ov2IWn2&RkSN}`&G7R9k6Q8hF z{)9qpipm2Jtex1&ytwP}1$~lS!beAiFjJY+9&gD+*Rf>x-L@(>ba2*loydbG4I>4R zUxL)RuJK_R$CvL+4hEGn%8s5Lm&kFfPX7@dNiE#*w;zVz>^1V&95`vb=jb?VDVd8; zO%B=7Z8oawg4EKRNih>c8hQhKzy(DPJK*J#3QUThyzwR(f3#6fT@3byMrNM{(&-4W z2I7fLngA%BFqJrj!o=c!<^c{Fe@EtM68%*HF{1)FBY{U*x&T=$g+^Lth+Gt?ZqI97 zZiO-st#hxvR$(K-m(9S*MsE)(WKhce=9z5hQlmRX0vj@&&p{&!B`{rST@~+sFGE_z zvORT?eMrWhmwgWz>c%fAW5nT~^SiXpz_(sZ*(pFUJ|h-L4pq)nhW6EiDTzZe7lBFC z6JII$vI8uz-qI|c-Le-fX1#Hqo_UrD4ncLhQY9YNp85ZyViLhDE1v<%#n0+Hw#mL# zJwYT?8TFe=4~1?s+cfJ`7|}rUL_*(uo6-^c$Z;qj>z=x$*9Z6pZG7v9tdhZ?UP=g# zXSNxl<`3sQWA9_~IFg|8AI6R^jIu+9(va|jSF$*X5Fr){wXRy#<5xLF7o4}9M@AOThwxZJZY5|HtFuZ?c(X^uAZw%3=dP;7FXIb8 zbyiTPgbfCzAA;1$H;s$-tn2?#Vf=~+GMcr4k`B5a6EXBGa7;}rL+w=oD+TgHBEvhbM!(pDRy*P_s0(YiQrKs;_<=`<(bFkdT!u#rq~_(+(w zD|zhY1DIauex&BD#^m4&>T_^y`;oLG?yMJJY3z;uZ~8|rlHPr3GJK&&>CPU3NWQ7h z(UpkN#Q6$d7BCt)XFa>OZX^Ll=Yj9s7zo%iDt-G^Pwm(0-rCXd3L3|hBv{4%?Qk<)3zTrR~4~HhrUCn=% zv~Z1uv%};#u(lAoM!9)5VM?RAWt|~c<`4a}nfqE`bb-Oo%M$=mshFo7FD0SD91kis z?YBD%H;ggW*xJE=Q~=1sd>Sk3+K3Qtr4Gc^7Eg~+#up}A4fbnw9GZK<#t_plx}TDl zGdK9o6PMkU_a`PXkiDZYOZbE9**pSE6e6kUdW{o4h)`Y-;!iLyCFJ+bGaIuhU0`5= z7^~$)M9R5>GLGk?!&|7dTUDS4Qu3y4BnWJgt~yn`N@phPU=|1*V^~#`kJ2XVF>^) zT3Q}3C5rm!Q(vd5j$@YkG!}73M{Xe0NK$v|%;{hVwINU;bLf8#qx6v3v?7}#S5z}+ zb5m>P+~J$^Ckd-f&^R_7`A)A5=~fhM9JH$sZrS3dISMua=QqI;vd=*1e5R|O>lF9e zYqwMGJV9h>lICUcG4Mskr&H*k$H0_-RFe2Uv{Fwq?h^{KEAv`*bWzn&`Ab0!(5N{J z@IbfS(f=Gw8f`tZCU-$(Q6vcNlSdR`+A1{PFIz9;`(GY%n(Znj-XJ}Bu?g4Gb!Qe? z152)~l}FQZ#Rot5pjfZFt=QguYbG^2-Vdr43@0%IUUtrs8Ij9P`OXOw#{f%&SQ`LZtI&l<~l@(dgjgxe|`6B4f`Cu(hRo;MrDyRaDwX7!lzoq+rpktTx=ul z+&O-(&?1`R(Rq>GpG5T{Xgzk;6)lrGOQi#DCF{8e>kg2oxEe3vJzPjZ1MItuGS{qd zmwm=gSki!7N6wXrD}HfKRDQKC(?A>Or=Cbx@;hv z{8#WwDc8WK(|r@JmYs!W22^GLe7)7{v0F%?BiNRnosL+tniySk5Uf9u1u_o2r)aaT zpk&j0#I=fa5qFt4HuLL4E$$Xm_ZU*Y{=%pDgpeg$m)ZXx{Kf&9dEQ_`@S(&A8nq@ob8;zcOklEA4s=Lii3_$*8C0?) zT0zD^L}`+*&h^E8x==rNm#eV1*p^ulV5izt;qCBFyH)9IEO0}nzG&abKg;rxB-8k= zaqIyj*S7*LNlsdhM6)vn!c%-Xa}3b^HoHaj=XlQ|Q?ql`=%jD)#HG;bu^QS^v(0L= zDpyoNmt3!|q#}^WOj5v#_H{8(;QDCy;Jz~}0oX}XJhxV}rl{ig4;~IHRac$1IldI| z$DHI-wlRIK25795f;q!o)eU!sfpit!=^7Z1WZ>(~z)6u0GMFJn(h$veq7MEq7T&7_ z?66ZkPrN-t}JJfOQG>VnU4Jpn8TYcu}48Yv#LW~AdL9&C4 z*C{k`+5G z<15u6s2}L5RmMk9^>aScSK*x=V82Nd_zP7;|8AZY`5@S9D2Q}4t*jK#yDZi%G5rZ~y@c%JD*_cyYm@=<+s(&wlrk9|2(xd0D{3Ja(i0j` zTLyIiUZG^Y0I!|u+zl|+Aun{#q)DYY*DyY4j?YnStQdWvr)+rXWgVPl%lj@il_M9i zdC(A3Zm6d5^Rh*mk#bAB6~eJDEU6BKSy)sGRz0l$HOE3T#(tJB+_P!4jE#(#NG87OFV)j{(4(@@-+ zlk*t$(27z3Q1ILf>Qq6O4*wG97{DY_@Qq${bnGO8gJ@(bl~YEXI5N*Q-Q=c!7c)A1 zD!O=!NET@>&mV2c+(-||wUarL`0?RE`Oh(Loqtqj-3P6m_ET=i4TaeBfEJ813B`SY>_Xlk{M8bxpcQ3##cMb3(i?^R|#$)#)67w$x;7d*75}h|BRIA4#7ms%RqaRxgmluo-=3i{$@s6%FCru884FC>EdW z7t6BkDGig^I<}YKSCaEkdnO{RcdTlZEa(V5RsDvPye7x8dYqFNsxXhfoFDXLw$`MB z#fH3y_ZXPX&`a|=Mnksb5pJhtN6NARB`!3H%!F_U2QHzkrelG83x)eb%>mYi89t|? zgm5M!LfZd6VH@B&mxL=zYx~M*M6#(n{tz`2{hwXJIT}}-q7AB6;$!CWj192-ZMzG| z`6@R|!=e-qQ8pvlp03N(>X zc)XWC6*gTlJh3jn@RQLeCex-U?a(F$YgH{EQGQysdpUg?VWKG^ps3s7kZJq1^c&UB zQO(uAe=FeKphN*30Y=PmM<3qbfuo_&q3ud10%2S3=Pf={NZw(*AMB|Xv0kVR~2S2Zt{BN1rW3GE|Gq+5C7p7Yhug=`*i<78)8)QuMLr7?VZSTcdPSWHlixz|Un;0v7Idmq1`u^{ z53B8JT{Gb>M>8X(D+=Uo7CU5BQpI3?kl2AveYGfo-*Zq9fmFcj%r^mTU1)M60XRUWSu}UwRR*?3#_AZfBiway7KZ ztnaM4?X}d0BsC^}O;s@FiA$iIr4(b})n$Uh1{6uRCOVkNSd;|{fNfYFw41wL#OEZT zR9LPD7mc@Xi+LAG#5qb|wTn4Uq$b&>tQ{TD;yTt3Oa01~%P(u%+3yO^cn$t?xGnVR z8H*giE)>If=#j}XOw7kKOosr8a*#n~CgDJvQmJ&^G2z((-1J5kXpz&7#pPY^D=ce+ zPR2aD!Ca!?_Mxxm{nX2RsD0v1azDJ$s+=M2P%1ln>xr-$dH%r1bXBlT@P74ZAx7iX z2_NmRq3fL|Mzv)98mG%_$7l~))qzT?T85|KJ$&S;G`1)P~9n| zQ3#sJy7PSwHtyV!#2OAyd(7z=RA4+jLUPsGZ%*ED3=Wnyv>iR^#Ur-Gf4&$wPFB+3 z-`W!#OBix^iBv9*y{=_ml8M%<_Vkp{Y*N77u*uFXtx=<;hek#4~qe@kc8Cm6wu1Tey_trkx=#Qw-)5c2XsNka{LBaOH9V|;VR+!{4B zmG>w5=sW)&&6PbvmES3L{4*InJrb#QthiV;#?Fx0D8wzN6#WxHBUQJ1GQzoU)S6-& zm6YN@^2)q%U83gd$9p|?VJE_}BjGad8&tR5P$ILzMkgkld{Z))%Uu$XQ)Y0|2)DWb za)@uLV+)3yVt2o}-G^uiR3d!;?U&=DLayF$DRcxA6%ii$t)ERg%jIkagVs1!W1IK& z3wo26mQX)5wg4E`=47#t?ANW+dK9|-f1YPlYXcM??mrp%5bZ&{XR3z-xP}f2(NX82 zg^`)1Vy&$%m^^+kv|ejV!@trVnEoXD5m(3X=EVi$?{A}9!umSF`{wEP&PK0IctNrE zxGPe+3QueSAC*yAgbBZ&a@l}9-zLvIK>8!(J8j&?9<|Euf8lZ9P9 z9VrdUf(2{55regac~_dxJ7OH+k+;v(n4jsw%u&$sB(Vna-!3MoYCk zJV0v4JrCXVS*+bf7eh~T1oFPb8Bbc@AxoH;kwktM;8eGBf9wY(hvvGG zCwV`wc+k(^Yr22CL!WY7Xr8MFoqCzvv=L|jTMas!-ws$%oMPz&Hdf^!yE2APbddLZ z+QEJKi#sa6*IMglYpaW!r#Lq1!!P;14tscn*QrR zLxJ7qm6i(cGI`=7HVah0hub?k&q=n5dykqw#)X+tx*Enm%~>Gq>Nr}Jb`!H>!`z+r z#^l8!*^?rhYrP-4DdYch8lPlPC&dW7t1J~ljk~gccdXLv57x@XpID`O+Wb?4lpP@Z zBBG9^j1e=zT+6hK$tq@D!Dw2n<+8kKDz9c1tRI6+P#S@cv9$+iG+nk!)q(VFL5%*0 z!voJ^i>J;5RpJ<$F#&tJJdN|VDz3%ab*qBViv6#u#es8kBM+0dSCC{(%hkZ|=9MpD zqY`%NIw2v1MUvuT-)JSOU^w5Z-YxAEUly~_3N$~E`6QZ}hA}WYf)3EB$O9B&oKHa~maZ9=s0xt~V%|*p)J*kL(=6o8$7M{z4N+*5~SHPldU( zf@7ie9+zL~kbQQ5lkbZHX zxG=Z|$H+pc%4@h2hV+vAG0=t{rjF3`S4s6WA@xzkw6{#w?rILMsJmg*9!$GoUK`Ul z4(A!{Kag0^6bJK^Y;u}Xx$o4j)FyBL2_4c(SL~`EuCIdK`XkHR8SS^3$*|Pl`o6$F zITR3vtoUNgb?dJ%Bj|*WF||&tDLQQ+ z=PmGY=8qV<(z?KKQu%%LM+@r0k*7#nCVw4Wnj;1jo*uxD6kGJB~QdI2; z#I{GWx-qo?nZ(j1mn2CF9ZDV+JDP&g{LCH)M0`~7hQ2AwoZ$-GcDa}l^i9%qx9#OS z!K^Hw++9~(n7`@)48Z9NJ;B|xH6MZn+Nt};i*gUjj%FA3)zSc>Sd{7lW9Btu261-g zM|@hJ&5ff)I2Y~ZB_#qSZg<`(vPXAmjMgt%P}4tz=@+{DeO??Fho(3Z2t@eM{7Tuc z$U*0A*teU-NhQQ?gX~E&^$p1fg&!N30Rq)E8DzGR{W#B%uhBG8(LXIX9}-7nwXi( zJ2r>5?2YgkPd17Rq1oSFms>Kh+d6c0{^kB*4&wXY(g-=Gj$5g+QEbJoFTRa#$w^6a zK*pWL_3pA@5yf9B!97v3q9dVFuj?2kQNvvLKBpq9ce{6_jIL5P{igD?RNRW2u4d!d zoi|kud_w>VNTDkx@(46#{6B`MaKlSlu>OAb-33cdT`C>ERdt( z(fek2Zj}ntf%j!DKP#xxIEl{yuob7xKsWngJaOaD%k0A{fYoLJ_BNZ0=-QL7mq6{w*R<139)8c&+rBa&n+wC|nhnrTaC7V*X~@uoZu%6n(nR(@2&d111h^d!PE zdlXdm8e$Pg)>Gq4EaN655|so#c7cQDneVvGmL#tiJEz}lX&N~G0Tgf(eRrvhzs8q0 zah9wq<)sdAyyi*3XMTnr|FS!?_c;6@@MD<{U|M4}Pt;>M6L5zykCr_C`E%?NJws2b zo+`q|L}5I?Us+L*3OMMDebzZ>`XCT-Uqy_Eo{3d&==R)4*3j=m3g=)@mwdDb|7XdN z^6mD(x{IJ3daO2EC}mveMG-c+ttxF=>78pmEU@i%gZp@K+J2^n1}61Ms}>IV*|Enn z_E++#Z^fwBwVv>JU%3iRP2!TD@R_RGo7ws?V|uW!m1-UK?Gh=n~-k>Ww;Z^+xd zuy8{bB5qG6IHP?}ST|sqXTz1pH%R5}cC}+4gN>639e88PHL26Vufoa&CsHg?A&FYH zaG^LQymm$}Q8#qPVcSETgj$PC%bLQ76|`PF(|fQVvqtfKIi8Tdyq#iw!{AVx!UX3M zW6x(lV4d+9+ki~Pa*fCJL#)!XYE8Su-|j)|e!Kc*ZLU0*IueursO+t;?p|y)pEv_u zePaY=ExnhPdMBAB6`?L4uP|IneRZnm@v_ROFdMm(%`R4@ueJv<4@^ErN_(c+vG#o| zht;8De374(?Nb&gZe+%CP<*v;?l14*Ej=0QQ^ywtYKNMFS>}~%^EX2Sog^h`PR8ym z{}6AY!ls(GR-wsm`AyIlz zl-dlZ%Gb|{7SI6W5@$(OzkvGZLjL$aUp>{tDUwu%lr*BccvKl7- zPNnEgnyS`;TC^~&s2s4?g7!Y{Y&HFLj5q12<Zzw%Qr< zZCB#`&>>{_;KwI??CA(P%#q%BwV8#Lif~R$$80h3052iPm1Jjor*~xs{-ii^1^8U^ z&^|^jqQ%osjrd6@QUk%SG_L(7P2Qc~?{}3Fo2&Z(&qa#Rz1{|>Q>SjBmjDj}K#I=I z<~i3CUh+Eg2FV>cn*mB-o>@{x>CBNDV`gQpq1U)D^ZQ=9d60IT=)*s0V!(`~U zLJ{zFnuN5}N~OU99{;)Hs(66MO<d!9ZMd@W3Z)XS!g9cOa*|NJ5K0Te_nx4BRVX z7@Pm}NvHku7WoOeJ#BTqhiafe&eyBW{&kuD-v@8W%8zS^Fe-c&6J1ya#-KwBNuNAq zX_}IQkDn=zjtBg3BpzQ|_2S9|*vK{n*5|R{`92E1V)DBlEsQ~Jo3JLkJcb@|Ez2X{ zK|6Bhs*-9K=AO<827i7()-LJsYl;)%b(|?CxoHMn{IPbP z5>gPdaE9IS8XH==^}DZJsUK<=Ul@DfifHy9cpSgbHs+yz?z0>2^WV}>-|nPcz$ z?ed6kFlssxwWD``{~RgLg1T6XR?}_zM_Botm-D}Iy{UJ7WT^cKba=iZ7#`C@doB5e zvfE$Gf0>o>lVLcTbpl0X=Le!2%yh5aNay++HMPt1*5QNyh4}C=KdzSlG68DeN?ETA z^n?_Rx_OaikdmE2!ny1Sdp6uRyYIEZT@(xr6bJZBb@g6oY-f+1$P67)0ZiaE}S8%8nB^qQIUYAPXkE-T><(wAk*%rz1GQ65sN zM0?qUI<TJ#NkX&s|?= zGQR5NA03ZR?8Y7q(o;tYzdh4BfuWp4$?zWNvW#E|0am3U-BN`HuDvmwy-|8t5|dH;!vh?7p#ic zwhr5QLWgPQTZPz@5uFUVUF`&gKyJ-jl4_d`RTVrIiD};Y+nlo&$IamavZCtjS%Ma? zev_tUv&w$CEjJ$5TGUPzJEKhtlC|990SBlL9p;;-4wyf|Gf=zWO6ZekyxE?^W#jmW zUV74qh&eT!EgZQas9+G+p(#HV#(ZDUzo-u7w8EZ-kC!}tdxiv|{g z_bJ)MVoW}o-JbmRpa=Ql?y--SPjDyP_`g*|jAqulJs>;yp(+KUwS4^XS5By;(WYl+ zCOjlM|65rm#47VBZq|e6K;i=JU*Ppr%cLl2Vv7O<1-$ug%LX^AFN%l5;uP3my*pMRXU z>faPT>Tb+iht10P4s8nUW(B<3LJlF8i^xU@eFn3(`@$Ptd^*yEyanV&fYysxV)t2&pH9SU6d_sA( z-HXS{FCPN79^s`gf`F{4<|(qCl-QT{(vR-G{+TsW+R~d2U&gdj<6y&O;M*u~Oe6-` z)&Ue5nuzNNIjHvtw~Z?+^hzA{5bx-AQOzDIlkyol7Ibq;S3((HH>Kl;2bl*)J2o3~ zb$)UEiAuHLQ8<4Jj3r-vuCE(IFpR+P%8m=i=SM2vZ^ZErGPr?G{28Zv z)nxj4l(o>u1>Je+1ITmA{nIr-bl}4|nJc4Tnaj}#*xkzfTafwOt49t$f?nx_t(j#f z#%J+NzAYOObaNKDXSEuz@SSJqYY@Br$0g%sHbvKVw?Jf`xjXdSaqq4#dJ8BE#aE&U zNv$&x9bDA`q5Z50mTFqGrbCt)md|TS`yir}KeZrCznQY{{C!$YYXvj*i{VSclsM?- zJa`|-|B+e|gRoL`8q9B;kMCyRlYChj;A9Y=*;ycAo*tj@d*`bChvyf@dkO1Xjg5^0 zEr?vORN!W~F;}jB>-1WCq=vm=602pJ>F41N!rw(&oMvd-OEp<$+y|HYAf!iTB0ICUDzS1bAw-C1v}3<32Xu)c$@KVm;L@MS08! z$YA$v0ub9kG^A8R%~I#pTj4jJw6+FE%_OCd>?pL;-@WEz@1=5Zv?#y1U(AYZYck^wjUcDb{=OwMhMK6bzuK4| zT`+Z80yB?n3_rAf1_!%NCDT=h7Hswh_zCXx`RmvdV@N?4(`^Hera@0oGu0g6JR8cL* z-Pap<8@iUedJn=IA~qdjUZ}ZlP(RDsSyn6UT(u%rL|>m%19pPZY>iA@`vBzvI)#Gq zez>9_ooJpZGu#h`mfn3#QZFEFtcH4d=1!|aZH1x@c3yLyOhe+Uo9_($P7qn)xU0k1 z)v>BcpYmbFwe;SgdErC!f{(TI|I`IF9YiTYv2U08f3aruot%*T(5uYc_-J4I)=J8ruc1svtF%>bUAA8`mwZkFL zuT1GOHx9QPuKE>@UM{&056dgPtf^c(!ccD@7FR7&tgxY5UAYtEDS?#aQy$PIu9K4# z-nrerby!(F5d=A@_uQC2Ky2iPJy-rx28zDwS#2u(2Nq$uGHYV*DMBR@bXPLbY?^S7 z_=J#wo=fDbQQGQ{OSTx*%6R=k z%L%IV@o%lNNv0axAy_TWA~6Z-%(eJsfby6g^_=+|f*_;DHpBEe{M?>=_2Co9)e2*I zdJyINTuYZw0THdt$J%Uy-TC%+Ty60`$)XU<0WEcczC-NxCq`DEXU@fnOZt10=C8>s2z<~Gn!FEJd(cp zxFKbM;+qIIJZaN~L@rpcS8f!1DaC0naj3p|(N>7~oio_AzE zYssp5f}^TuJEAmE+-H6}u2z|_(d}vyl&Ft?1G(!YY$*rNJln~{bBuQ-<-V!#5O3d^ z;e2i!N|dQ%&Pdj37U5_K!D0NUaGzGC&%^#vF-Q=SK%VRZNQ>BqGIW)`Z5PLZmjUIz zlx%YTemK2kbC&a5vdn|dhaF&_l&{1=$hRtx4gb@HgTi%AubV!~)^IX4QEe4WZF&a% z>8jH}KH~S5?SjZt7}nQv3A-Tw2B=E_M7vcVu9>*air^uFD|IQJEEkB3<`d?bCLm9} zFu=u2?ESkJ6S7{YtYe4dIoCgbGa^kJ7YE6u`*<3`YwoD0Tc+Od_>fA6JYOWf^uQlou}18K*DjChvb(?)>y~&@1e6X?`}DRFyA-nMKc(tcz%Rgm5~1to&3h zq-1y`nz>GK9&J;0ph!)ezEz+CH;m!FqOxtJP}IvO-PbNtp=%T!3q8=KHoSf>Xt|}@ zvtlK12$SBP8dDGZws%9P<8nGKRPZk?`PO5{_AdvY(AS`8g^erm9j@hfo}ku7XGeemnMvSg0-6Wiw2lSif*DJO?6VSr!l|)kVUZ5=o!|U=7M6qM|c7i)! zc?|)wehP2WVO)CYC7@Ao6G=tSTxt<>*a;wV5fazG^iuRri2iHlh==<@7H9XH0y|?? zpXCJBh6zPPzLVn;xg9Wc;Dbe=YvV(1hRXIOMj1gEu|!J^xSjJ5(lCX3*!NW**o~qy zpJi+>>0Mx5@m-O7_*56LuQj*rAqU&TpE&y5oyz0mv8 ziDB?&$NIHeE@#1iR5y*Py|`t5OoyBSUfuoZ1RsBN2==jtl2L4x&^{JI2lIXN%H66e zvW@n4n{fLeG}F!;aU$JU zceRD#>Dl(;0wWz^&uHXpeJ;!3E{V6uzu@#9e%ANKnP#VJ_HWDc7`AqP#a`JdRZLkB zG?ub)`Qxsy!F>{bv=*{j&wv?UM?t9xUyNY&bN4CP4M!hN9!71|?FG1@A7Rde%4tjY z;Jx_|v}yw+nA^&Pezz!vYgD&= zp!|6CNDsbJgdm!?kUBu=Z~w&AaNDQ@2Q*f}mk0W-R{B}ZpvSEN1Lfoq29{kmO)U%X@BlI2MF7p`0@&&&@Gi=5|_;DXSf-41U5(e5xu z!|km(_g1mG47UiQt9`P@R)BL_#~*bIpABz@|00 zB&x2T+$E)RK{#2-YD8lpc&!Q=-Oo92L2L zNRz9JSNpL%_l{aot5mq3r@I~d*1l$ohl?G)*~->gCCDVwAd?g2l~2JgW;G3VBn;Na zMkh~X4^VdKrxf)clmQix&`Tcb7h9CjqQ@0Uh_f!-Dx>!K?LRoZZ}pP0d1qW^D+Xg> zXxe^vt%2tpgVBX6@48jA?##@v7WrQT(hqPx#T6n3XzBX=b;~OWA+gz!ZEslQs0RfmWrl)X_@I`#aloEKd@K9=sbjW zJzbrM@+A!Y1+Ht)0M~MW*EfxPDC?(pUuHG6B%AFY)tj>cL&WMb8S}Ej@_NKiBNWWz zDCkdoQ2e1k)O{O3q#$_L-V(kHa@E88v}H}&>nZO?OGTz?z=&^pE$R8OnDL`f!LW9U zdIPY>oS^ghuhebLnX!MlyP(lq@;P49oVp)lhAHJ9q9^V|7nLe>Q z{0p7&iMbG9Ob!Ptva8>9d{d}ft8lKFpT3GUsr>|@C-AQ+F#_)pjJ2A(v#bdhF+dU3 z<*%~o{NC|7)DuDUj@^2fUpK?KV%T^Gw#KX5s}B^ij20@ce%w~G`*{8NUt%-fn#3%z z>nBRHd;GIrX}qO~$zLpG%#cNd=5lp|onfPPLPInMW!U{#`tJtKT6dw$4$wz9&dQNt;vlqUtYEd8L4M6K)aU)w0{NUQySP>~Y?0qNhz;T&YtX(E3 z<+xGIY!_{p7j|o_YS5H_1di%!Q@a)LBq+G#?DZwJ_GTXhb(2DOzQk4CJ5 zD2(TFY?4*0n%oOq<@LCWtW1=ls+l%RQ8>+(f5mbNyWZz`Pree^I(e$sj#ob7H|#Uw zx_9Hed0XmiZbu!`ybiDq@VRHV^wO@U>Y+&$0-Mpb=9=aNs&)XW#SzwqS2D0t<<2M@fSyoc_ z4gOPO>Iwih5kf}u)18Uf=cLZHSljdh5Ae(kZqwtmc-b^d-8ySjta&f0vbn^LcA5Xo zCnLbh`^LxBMAgEWpGzzhorkU#NFs3S@YZLQ8n%lXtxIR-D>dDXGyd8v?rM7d`M1^e zc;=A?L)$(gu%?sTh~=UPuToF8?pi}!dZa@uW-R{&?BCpY2Rfj4w&-|wc`zkg-oJc8 z55}2wzf`)XSK`5=nA6x$>yj^hXQiPCPPXml58kLMwe;dC2Y}lEsg7w+QXz*rku=`$ z46~AJETA4?;-4)OFXQi^DCMoF>AJ+t>0JgblOAaQvRnPaZhfu)N}%eXSU~XK9x1*bLxXoleQ@bm znv zY5Dm*u3xjg4EIiceg6A%O#;)J3o5e;pi}`3V5P+#fI%}-#j29e zQiC3F4QiSW1D{8Avz^Pkdd&T#awegIk^c;ob7P`kbYjq zt^6?7i2ifFa2+rB)!;_N*58_@M#lE(kx66!01RcAd!9^;Se;%(s zx{`krh%;*5HeOVEm=en(2xXQFJ z@-y;i<##8a&y6=5{u@8oAFc|a9dxGW<20QtR`2XJ5-<#1VZJ)6IVwF2usN)%#*BV* z;#L+&A^AUO~se38&G|jNXl|qSxiknKI!>+DXG|2Gv z=V%P0p~LNL@r$*5a+uKk!)b)M2s%j`{XH%4C_P=29L&}K<`Ky}U1Whw z3#gD8o3!~KT}84wcXUwsdOyfOpXM4PYjxqLe)jUp#G$%J=s+pz;L!GL*&fg(wa*a3w(h5N^ykx1<%bA< zp}9SHk^f1%7cx&cGU&H9>SG@c80~dTqJ{j@w88gXJd6s)fK$My17}9ocf3E!9)svF z#q<^SRRXFb6KLPTg*uF+4o6+ynhMxTFrQW2n~16q2MmKZ_Tk#DM)h)+wB>ym7YDie zCr~Xfk!YvLUjsPHA9(4i4f?G*#N%#&~t?lfr zH5Uosw{;WSf)lqDmcApnKpniBTZ2Kni!Tf?$F_o9@XUv#d(Z2~u-5l*(ZqURKsfC4 zyyj?F|M~5YBx6EJXO1?<+0@#dIF`ios36|cI>jbq%a=#;U5-NU?xhfI_&UU^Uoh5` z=9t8o);3$1K7!aOraq8nGsJ1s$_|f(Is2WOvP&k8`iv^4-<8X-j5k20#Qnb9H2*?X ztY+!*kH)~+59Y;bzh)*kK3Yt@)KktKPQREPE+t03ye6grs@Z!v(4`U;aK9Ytg1ZvS zX=$DqVs_Kl^cDHUa>M3)FU0kcxOiR?3=)KY4Ys(g?^AetslrH@sPh}?Xv8CHZBpi+ zcxjMZC^Djd)4oFY+efPf7$jp)-lkp_s5}@3locCAh9uIj;@gNp64bofpfw!pm<8oXkhJ=2<44a#|npwdPf8AH_FCotZ(&LHQQAR<-Jta8cXM$CR- zWix&-N6FG+?NJIctuL7WFW+X5Qiq%EcaIEZ@{)~S*TGY<;iVEE;oR*S$d@y)l~>SP zKtws#g@`H48Pne(dS{CH^gA~Etb%Qi`XeCIALarena;{;`uf{ay|qWU}kb_?c!Ml{r>n*PT-BH2}Jd->sV6|ITo#E4yd zKPD0T)UOp9=eR^aU@x46a64@e>vz7CU*H9+*NJc@J+MW+*fRKRXw1kWW&k zsdu*iM`t{_xh$lK$#Jr%|7y4=bUw-*A6~oOA;u@+DVMHVrt6o_`a<#Es#JE}`f?q# zyUo12gXyp#pA`q#F}}_eEG?sOmR`$%6^nyNwFjE%IvKt2Z4yp?807_BAf2w2y!(S& zW~LSBx4pELBy2KxB8(s$zYpB6kI)-%y-In|>ChH7SL(&gJKG-4=mqvo9O{r?7{Hxf z^P|-J$lYWd=i6P}s)Q&RN4Rm|f_Z3Ar&vo1(}y(NmC&Yo@)I#_<;j-zHf!9)8;DP3 z3w(xJJ)2QSbRofM{)A&NI(q79Y3m9-M4?y($?LOJ|dR>iW@h_?FX?vh zAom*S!Z*J03T_9AzKxCh;a~ziNrn*EMqu0J3lGfH#mF`(4 zxjg2*j6YNr+v(XL6i#ulNIhFeHJL5LMQDL?+ z!_VHmx`G$z7Cn*v7Cv;+5$r5>nq!k1T#Y0dTzvhT&v-`N?s1f@YmD7hiXIz^(4USd zdJYaZGY$kr!+~~pc{$Q07pKK zF%vCr@9O)Fn3Ue!XJ|HCJS1poaC6{BR8Zhe#=h0;=50k6lTMMcJdM~y@p5#icm9(( zD_oP z_L+~oWn-1uo=pJfEnIyc@xBIS)kTW(T_B(Co*VLYevy*;aFn#G4RrC|T`9E|ss5%z%ep!%nuP3mg(dlLpT`Tl|8IVJ0jg>gcrkD?}p9$=`O_l3xu{~AQe?GpX~2Dap+%1u;I zF2s%6CLG)C+H^8^c=z1fpfF3ryGGf%zWE-Ft;B=VWn3Kl%Y4Ok+c)aJUI(byPkB3| z8!m~IKl9tL-?D!%jS7rI`TDbmIc)d&65)*?5&f>m zNB9fB$4TlT!kG9~*HpIV3e?KIB%@STAy4a`&0v3A(J$>@HCJ;nI?^ZI;vHQ69DE zCgHj(D+1x>Rp2EePfrGRZI|XGQD0MRD@Xw~9)eLb{u z{K>EfQ|bYauGr9vMNDG;P;pa>ykQ@9tgCO0=&=2&kJQOz^0}{5j_|g>SpWROXeY($s4xsJ3DB@k!L{I; zj8ZpwAhv7RWo1qIxx=;M$FAfk;?VkjZ6AE|*<>9m(Bgv9H(A0DjP%huwTmZL7uLBy zRknVKe~>U5kbKB-a`PEmq005E%CA|{L&`8sTS+?gT_>{fmhX}h8d95GO+_8$ILlPa z{zf>_%hjSCM$;_=!W=tVp5DlMyz~)0JXv_-LZ;`|qEQRCv@~Kf$4}_0VW$X(X6nky zrTmk4bg3d_+(&(pc2yApemCpC@yI z_Z4@}Vd;F?Vd*ET+MzimWVOD0KlaV4o>cp&AN3)Fe*Cbu^@n2P`8x9XAj?~#sp?^z zXtl)DeKL5a1pNr<>*CDT#jpiC{c15$ZsM8N&tva>B4W0i`KWJF^VH=XtswmpVW7J1t~;h^JRy4ADih{-oIL{%_ZHJbvHjPiC8&R4)rnP=pQ{- z#pM#_!)6{HDs^vo$~JDuIf=L>+UwMP!wk3e12~N(ch1c`ph%>_2utwBoj&+PB<>zmGm*@^06&awGwCOusf~4 z3(MWgHo^YOSMN#cdhf!toaJpx_|V@IwNPvbvF^2=vO|W`sKe9AMIhPdKLCo2OV?cA zh=M?A)`)0|>2AW3Lq|1bRQNJ|WE88-+M|N5iJ zc%|4wIU!^vKSewmbLvncR^>lO3h*IR30LPOiz`;>-Z`G$zixXL*JckfcnGqAL5rF&yGW_Czm<2Xt8}f$5D0!3p8`Ny-p>` z$4EG6V6ut$E%A!r+?IIgpT#twROBzK+A}EWJrX?uk^EC8*p$4QJw`Lvj?^dk!v}m{ zr>;mJ6j>KI&!MPTBX)SFEgvLfX%QkAS6y8>qV0amfcVoDWp&vt4Kl0l>$$tSqc@Rg zm5Lu{NvydWK&FoMr~lT{I?E>j3}zL>_`)d4CQ}PVh_NB}*(JqT$p)ZnlW-On(OGN< z+a^Ym`9Dw#V^MY0kKKud{wj~X%SG#z*%7@zBZ$KSUraNF6Q*ll!qBxej90yM4yk5g z&dlUV$utcC?k#2nLU*8(g(%xPguIQsy)-fLD0)XIg?Ruw*PF2FMS|DkZHzT)Z5<8d zu}A5wFZKNHXMDaCt#8PLpv4b;DVr`b<8a)p1VvY=S-Q_8=C?OClYpOuqTT&*U#&+d z3TEMRN~Q1?9oZYd@-cKj2gZk*6)i3Qx^JYrddT8z0i4F~x%yZ}xDf9n1DFiJ-|)|+ z+821A?e8OzxRG+q6(M!w+k5??`FgP|(jkS`Ne&rOr?oj^u1SUa9f*hg z*DahX{0d_=3Py=6_}mWS`FiKe3IZR6d}Z$dPUTu7rZ~U+)ap3pr@noKh;UW2m;)Rs zXv?kf5k}tG+Jf4XY{z_p-qh2rtb|URJB)g{?i3hFCB zXM0r?BX%rZZJG48`uHqZQuNP|CvM;OOfadti-in+x|r8w5C4i<=M9!z-aki{2ltyi zP)oY(6@dDRLy#A36UEmjFhlHEVXu!(hgg1SoG9KvPB#5|s2bd-3@X`s8XvpPW{~X~ zmvfpXUNb1TI6mSFAM?>_)rpcpM61<%)nrMgxrBS6wzjR77|CheB z5$pIZy+B;EGLG!sI;QG>l$`fFVOoR-!Tf)`ptHC&=!cH_qfd(COrB^vt*T4{OlNCq2tUxjOrL3Nb_5pb@*ymGFi! z9aa6yhMsr=)TfPq zA6=5DB~GO+?6J|L6jle@`Cv*X0pg$^p}b!?Qg>*OwMJ)fFGaSQ(qDJA3BGXJ18jsI zC?4lwj0(>6e;p~1Wwgfc+%2kV$h>_=1t!5|JM)B_Zad%&btLM>xdF@m|L6$A{hU_H z|Cr9o`@$U5##UXB%}w?fMG0AS<^mZOmrd1eZmO1cyaD2}Sr(R8Ja<@*mwO@wDa^ea zWiY6dBTt+N&%3bi)XMS$2D;;lf$HCVN`ZFvW0TE?0=3#S#|7{cLW{uJ4UF@_mL&LF zWCT}#@9n^G^W6(``?Pu`?lco}={nwjM4N|(J&M=9t?iy>~-3UM*TO*ZPG(CqFlapq!-fDs+&IJm}_Grz^TGU)ZF=+{!H; z=9WEX@p`kaO8bL=K{)3{HC2Xomi|DWnG;g}StoNVE&Mn_m2Xbh2DKG<)1do;KJE{z;&r7akKS8Lmhh z&BdJiPH{;p%1GKaBz6b(2Q6-HDMBS<#rxg4#1u(ZRZx*XlM+UxoM7JpgkiwzTo!~@ zWLAwjD_5Dj{~r-_i$P*ew%1yDKi2BvRHe z6w+7pqjRnq9n@*MPQ zXZhcpBB7PkbQZNXe$_J@`aawN8d3@@5NWZiOfiyu4O)mR_{pV#U?~cGeOS@`qV(iM zntSxYs;6ZhV_{m``bKz3h399_%sF{)96!l4pA+zyY^AwEKXq1T)u4Iv$bR<6R6|44 z>{bxKB7XLb&(N(KJ(gtpz~!$iPUVB&6L@;9-Lsd2zTj3V^0iM!!V1WKh%?2daOSgb zT6b+ce--DKIeNByd9`4-DEVlVWaYNFahv<*6DkdV@AzM2o>^hR)wQ(9FoCyI#U++H z1zy0W9)fb0He2|kI#eocxZ50ahbl|7#qPO&)ZVi`JX{go zARPfs+@-36p(IO!KlOg>uBNdS#%1#0F9*drg%)mSSGXX42hw>kr+6Y#J?uajLfF~{ zR*&N`;&E^p5Aq8@E~(o7rg%W}^g+Sz09URDzg}&$SAfdTB%qwa=e`O$sUm5T%=tM*jvM*@VO^r z55|W}?N=@vXlk}tkHSm|_b~AK zRh|~JzZZJkAhFZbg&Z{MWA7m{>M|f z^H!XvFd~MI9n$eZVKD-s$JFR-x~PQjTPozAA-1tpw^t$+e(pd>^Ax5!_;a?g z`Lvc0wNGs}Zbh5P%aI*!MNs~T(F5^RR7$jug~UGhPPzP;CR2CtTKiFaJq}ivKQ7T7 zk0hWie}${M&pn%m*2n4;F$$;sIXIhpe|CG_Es4tI&UrWJJL$UfGW5zkTsU?; z5Z3hHrjM6cucOQ~23Bem76A)@DU5Gn>PK9|Yd4UmgMX>%T7xHkkH&s@_Bnm~kZnk+ zFgO=)C8hKkX+B}UT5?^aGM-TG!ZLh{sn>tPwVp<{%+fU9bm;~MF3wdy-j8?)C!VJk z&tkbFU$;B5n92GwdxRBaW?=KJA{R4hm;UvV)x3`xbvT(1`&l?&@d~x@9*`6qw4BoG zugzK&u1DA-37iE5tyD0Z+rYbLnY}`w&g~$Z@msf0`o?rWong6hbA#F2J+xKs>@h6U zh27e}r7l6Q%cdud7*DOI_yu)?H@~hou9zk|J~}gp!Tf0Ht+)5I_yOsQ0qj*%WH3Ux zKBnOxeX>M$uvgwhkIm^(@+3_~bXleg4ze&6>p{&Hhb1VdY-Eqfw_e&oBkugsPNG3! z6OOBw*GdkU+`caxmjP@|pc3l1diiRf1#d#bA3j5MuaAVFUMXn5U5vvXHodPXeCV$2 zA(tT@Hl_~x#%oQ>n$n!9qWuj4w#BK!uJzf%%RFFs$dfcQLVtzj$x`l4sac=|)2G}= ztQ96$qeX4qgGF^JEnoh8*5=(Vc`uO!5c?)Vy{^$!t3!z}8fIwjAQDwAl%JV)Ez z_Q1-jJJ5bpva5k;d-icV0-&eMGgQ~tI)QlN(`rG-!mU!}MGHRzNyfKow=4%WuU2e| z*g;(*b4+_A$r1*)#xtW zYVBv5W$fc`=EiST*%iKCeuOjVktCVD3RpP#(0_hwZgpf1&Z~8wP`phJY@9*O{9{3G z2vmFNXrBqXb$^{;ARWb5bKi#W6GfPpRc#D}h@=`cDDf%gz#2;OG?n+F@r_wdy*e{o zK0()i{ppx{zIo(;(4)vw`y=@-GQvf(_1}?-K8VP*8ViQdR7+um+FY$+!B+q9xx_2- z63FeahSD)GNdtk>#_-{DyoH+*$ZeQScKWW`3=jA)SnT}H4?eSTk}d%}n=jW-Qnz#q zc%4{2c?F7*^%W=z{vX{ro9n8gOtjkdLb<|>J%t-du`WH;Q7`>~p20CsY6*cUu#(-t zKs1T-A<9Ntkha9E8DD#kYDs(A-$x3Zg@J|dYNZ$NSWyy$tpazhONXdf(%nE{tS#@( z77c|oK0up)UHcy$SW0?wkK{#&!2@&yXtig*l{GxHk8U9RhVMNY06QjS}ZcmNPCS-#KuA6eJ906-MGn7tSyfZSbChT$ehXzI#a)vA~pRB~6 zw1G(aXV3~D0M9~y_Dns&1$SE-4kadTz?;wa3Rn_f#=M_71gS}z{W?E5(_Rz1Xwrrj zoxy*cMFOBVe^;F>D%LDy*?##pxIL2oZtTg5_;#_xfi_OUD0`WtO#rt*EC8bEc?E28 zA2xFNS$M6H!O+#%kE_=J``O^C`kF<<0@fevB|}ZTR*kcnUX`|kUSUx7naa4vwN%-G zpT|!aG(E*Zyj$5;`d@Y)^k+5`(C4>B9H9%_Pg%t>c8Nj(z%Pb|Vp`2LUpl;5u-(S> z7qv%!O$F>d9q%9a$4b*ej4Cs@4q1JCE+z1o3dX67FV@U1vaF7MSdGw9cTnn+U{Z

    |q1$C+BQsOIeezqWEh4`lyrpMB zE86EAGy-um&34p{)%v(r*g69dLcLoWQ(1?H^e^532s}1ui;O)BvO^O1KSBc_ls8%Q zwBDLiNO6$n@Inf7kMbJ_HXdihKt-|--c6at*|83GeQtg=>~l>(K5PyED#7hMBKwF= zyHYw9`DcdXtFEVF*po^-du=o7O_2r08Gt zl;cd9{ztd)N{F78Caymvle*kBObvaxOmh=8G?6pjhBB!?v=FZ>?>PG_>F1;;wyITz62^&Ny6)HtG9z2)gdRy zi`{X;dk@j*-y`LC)Iobp5&t)|md-`7_DTbl^&*ohFBSvA2(4+~TE<+qFjkq+7+pQS z6K4&poR1jSPnG+nM&0dUTF)PR|K& zAOlqq(Y`k0qilHVksz!!RVl-s9wD(@k~!i3V{*1XMN-dFY$Gx{@|OTgEJoY)C^l$G zo`%T4ihQWSqPv+!PMpI_%fF@Cq|>8EQy&lVy6tPz`f;w~<%5Z$-H!QetE!U0B3ba< zZo-yCVhtWd^9fy}9@(AaX+3jvaGEXQW zcFkSt?2kO5GL9DJFR+m2O)qzE4T7p{C106p@r;4kw1rs_23&lB8=<F!@DFGeN3- zjq@We_5YT6fBve3wz~5V(p)$&<zDWLh|@f}p#{hP zX#b$sMv-7d0Ow9e`DMX2&5E7h{dj{>s{)6iU9m0GbI$8CP>o057W?HzI&iaBffScSVu_dqor84djI7x*>h(ZES81O~~d&`VS7Hbt%$C8wb1o7SRBa#LMT+)qn zZ{(u1y!c+cXv{`xSb_|rg0%v@{m@6S-NkpM!c7iKpux7BP28|XOnVre#1vKKoN-c1 zfI1U8_wG-XmDPlQ&ZpO5xH7FN*!2eY5m$-#csV?sZ16p&wtRz&WSXjO;t~ESQu?fg zVnHhm;1Osl3Wd)VUgUrtq}F7jPvRghaqk-(30{rCz4o3hQBZl>tRxX@R{NkcD9J4nMN@< zWze*=3cFNQx2~M@a!NLkH5dj}aroe9>3tO4;dn!mgx41 z2RE54a7tDC=31ey^<_QK>5mwQuiF!1wX|i zL9W|3es}oP;b{)sJi~E@+(CP%32m8y(fX4kds8Y03Le(h0~TB6eG8-f(3icm4USA{ z{1fP*Ag43oD9@5U-8I^Zce{6;oI7>a-}Rk7=bV z;{;4v$!3=1U}vb*99(}T9t=;9@EosSedX6;@G(4OjP6EmE~z50g1xt4AT{JGFw5$R z=r6U@ngQ+_Rdv4V55P^i4Rowm_E#;SZJCGsh23e%a{8d-dM71;Gg=uwcvyPVv124Cq3PN zpVQDCp%qF+%#B@a2`9AW+oXzGdND8MVYGGKCMXXomZu*ac-U{oBhZZC;DJ?*soyXpuE?z8()y zOj^VH1;P$f@LR?0Cx?-9<(`LI*k53nz07^1sEyY@6a zl|Bw8Jx%_6-qB)gC5!xzx~nYU=$=X(+F2;JbjS}tXztzPb#auRQdAff#)dsjeMUeJ z4c}%$s2$$~>@8zsT}}iW+riR1&WL4yNRBN+p6B%maiBzCvcxvWA|Z5CGUZ}Z-y#PR zy!vrOdtA}7YF1^2<}o>1aY`Ck_Z(ctO_m0?+QsM|k9`jluN(z?j$gSsY1h{C%}LnS z>9;XEcjv!X{5=*Ecfl-q3So|x*!9i$r%hJs=)haEWvQG}?|w`dDmj4jjE{y7&?3T=9o8fBmp%sQkXQ23JJ zYg~{sn-_vsseJZII}0M25K2f9GhI?+sk45PoUA57k{A`euY?BhjYU{1UlQ20WM~AH zH0HQWW%}<}Elgz#c*`@BP4c@&1)K$M(C}yjnsAK=s4MPfd1*s{l{ra1=9b0AQ?3u-D?8)38H@9f>s} zQ+KIGMPF)@7QXz{Xbk5)`9w%uYm*>doOyi8s^R$O0Kq~fQapQ+BjI09qYJS!;3BD>;!8?yYgZ9bS#xrP= z3D>#61=@{ZzV<9%{Ut%a^q)6piX&rjDz^)#T%Xlrwa7g=H!;Yg_&yu|H1FS}xQ2*n zq){1woYMMy67tmbgS7RQ3fV!{SIxD$F{!Jcl;w=+h*kMoX?1#ehv)1u(SGvxn ze%~-swN`Aegk@M*(+qZL*^eEYg-qMz7V7 z&KeqW{}rpLGJ?7(XAB)kO&(X&zwt?GEyX>=U%Lpq=^>mXBa`yYGTF_nvdjnU{Pkk- zz4p+HtNMD+pYPsmO#Nr9l;hGnlJ+QIxqj!4+a(4aElh;x45qirIr?goi$~PvhrYhF z*D6UrGV4I|e{rK$)1pd9K;85Hyu``AS6^l57!p}?PZfsaG892V4vxC={kJRDh>8-! z_r$ixA$ivCEba^iVMDShoU_CO`=8YlZMmtk4!z3KoXPK+_%FPkIAs&ZII`7?lWg?b z*B;4*z|%Gvowhgm02f6YTNTew6x6Gh*4Uk~OL}v|qQpp3aeJa#+Vg0(%#`gRYvyK$ zAY3bm?y?^;Ff3)R@#=>?2bBv}~zXO& zin$a2CGX5##}#sZT3k>re{4iZiUXS1QPL#c+#ZSntu9Rf}|8wLu{c?`Yd2md+CqzsP={Jt6ea{-oQfv4qaK{NM{f?U1 zZV@=DLArfx^iHZxyWpo0!oHJ`6X0zyb8Fd(g#ePa&bbGVcf6frp@cSpU{l^Xu01N1 zYC=7B)Yg)`^&I{gzYV>Ni6Q-NZy|h)^*50nEPFnuywxQU#xo#o_4xPc?Y=inTEVcp zHAk>1_kn>LU50409{oJ?7@mZUu9oTKApsnHXCToQZz9^}#ymokIFR<9c94PD7or)L zG`Jm>faeWA`Ae#d*I2Nr%iUB)B;mc%-BD6bRS0U9YOYtR>pCjYQzt7~|DQNlG{Xz| z6h~0;x#yX|&9vej*p5|Agx?#|!@m;hAqqjZhxr3aYY(q|i0?iv*;o(cxiY6qdG689 zM^OIB69F)6Z-kp3pA1Un<f^j>JnWTto(}}8lh-`!msrr7A zs)><9pk_r^2dgCYL9o`g-9!T=AwuhEMi?NtCVKRK&vRq$SbOoU$ID7O8N2;u>ljXo zW9Qm<{G1kN+S3+`DK`$kCGCGVe)U7SJ=Vd^<|yD7+4UR!Vu{DvNH~1$7`h*|CW%AU zmHbZ9%HK5RwVTQQ^z8(Te}8>TZmc;a?xzb@e@s?;CGVe2J3*;-7*xNuduJ*gJm(GG zHX>#HV6_kbCL9J@Pu29|-mEQo(P#wbW1TTp%rlxO;@hl*S5=F)U?$Dh3=a`Y`nP1T zLbs)PQ$fo&X;Nb?!{T5?g5MV4o6Tm6EoM1OlvYj-&I`@YzagG{mZg^+wVp0Orev&w zsr|43R@c`xZc0Z@b=$N&%}cb^%Jx{5^;lEsT`V63cAi(f2AvKJjzO+tSa;uY;DU*9g{`j=f-xNta$$Lm+P-Tj0fhLSwE#E$Yb z<{z7>>}uZ)$nL-2Sjou=2NQn|(s)7M;RjsS_McX&r3y`@r&6tM!cb^g$Uneoy^N(CkN{t zCUq_Y*3Z>8I}&DK@y=OS!+$OY75&irNl?y-s7cfUO^h((yVApgWu zt(SEtoA7OyppzS6YwN}9tuxkQMKTM^CXGK+SKDV$IKbHBlZH^b^Rt#VdZyA`lQV>U`#; z^4B;l?Q%nuO5BflHy78e!3Rz`nw%X4=I!p5JyD*<32`pqiuO)2nN91(2UW94|D>@$;1M zvGUR#L04;YH?e`sR|Zt15b`GK?+lFF9dz7UtuQUY=i`e~{aAJ%r7Jf0LxG;)^&>y? z-)y=?{iHy2#*$KifpJK@M*O?^k}um3V^}k+f7`6vRWQpD5QQmn43P@o#Ktv!&(?Y} zxPrPGbUohPYIk`+z4(OP>CIL|N#J@KKhHJ;WHo>2D+{3T)0bM!5ykf1VTK+?wW z4Z(+7ppGq1^%)N-R}gP&&V_XjOV-^oGW(Uf+{6B;enrVNgHoMQ$SJ?`;MPH7(?cTi z;N_c4-h++XQ(L7n&qG6xP)*JjKCPRhNJ)3u+c6Dw5V>G->180wz`qg{R*Z^eo(M6c z!8==@Uuqm9h#p2&g}))hSk+H;c#EK$aZE+MNf=^h2#H1R+Dm)9V65x>r1J3CVfi;- zy@<4OT(AE`e~|E`aLP5lqK{!9p4^byTEVuxFNE#=;csUry^rt?HYl`T6y$XP;`i>W z+C1uO)+}3>>v!Vhu9HZA0iMvS@m%mEF-+h2#?38_KQ$f~X&TBRHJvI`FDd3gdtr3xTzn?; z4O6l78~QfKTd!^bmv~c^U#~b7{fcrKr*}VPEc0l2v6o<-YE$(ZgJA#gR`xqZv)fx9 zEOl}VhHDJ0sxl}tL=nYtRSir~Q~*Ui1XiQdy(y-MlHq<~F(YnlylkGpm^mFQxF(@# zR$oUnJx~m}8bdJ!e8;5w@5o4!igKQmX*>elSI(4bsOA|tG36E#%<<5aSd8+7Utii2 zKrU{jmni1rglzb2!CPSrSuYdf)`-P{A4mIN01)!nhHw}~^~`k5Exuqjph~e(qI4zt z8e#|2lUTXsyJqvOHYe8^!N7IDHH;?~d3-SPvJ3r6f%(oWC7FqIs!5KpdOfGlUN5^m zSL3s}(;#+@YGZ7lNfvZ8Iq@bijERC6f?6Juy`QG z8{XDjpKZ=V_D0rvTK#%|UnJ3lhaA0XI4FE0*#c4WOY;Bc zNBuXd+1(AQ@IYUU7>2r37<*m+l6Ze>N#|8DA3baKpPE=2ou@(OeV`Y#!~^Anf$6zz zVWQl!ALl{y$gCuV8ZW z3$qv0=t@AtC||eO&}gQG5i{nim^;2&Y2#AL_^RoYm4^^8b1b6pFu*toN44b1WKO{r z+sqU^ZNy}lbVQ0eH(6bKlv=4wkI-j+ngz2KoME*N!In*=SKq<4Ug70%zTzg7NVVjZ z9o&Xwy9P9MDg8f+&N{Bi?|tL&MMVWcP>@EYq@|mwNQsDmbg6V~NH;SG$q5KZPNgI# zIbtyB25H!U(MXJDY;5fFdw&0Juh*XK*?G>n&$+JqeVrOa^)8C|Cc=6zvfpl1Yx!5C zg~*Ca@QZUpAAV>;3WPVEbZhEOnK|WUsN}uaa*o16q~2*darE(u3z)cP+YEMjLUDpg zO^SW|?v9D+;Wr;`JwLKm477Zk=BJ0-xzVDyc;zw4NJGukG0IM-*Q-{SY3o0l$hNnA zx4{lsSC&U#oD7TXo-uG?>$?Vq*BiD_-C$IM8TGZF8OMCqvtHnQ_uv(CZ7=z5aEItx zGFw~x)%ym&43WA2R!p9c9j4T-%|8S~)bR3xy$tE~p90}flpzr1#6O_+Ai9kqr?Jt5fDqYC(sr+)09I7>h zrBzU#{(;gG82-m0Ce$Hz_mrW0$4*RCJ#HU7u2S5O`LO<(W~ktOms7Mcrlr(;y=1^w zVc!;Lx$_X;f!&}Ew<%`~vlYU0ngicU=iT@tx_sYyW?cP{*wd`3VT$Nt(loQ*L$mCl5?^)KT6niEPG+z6L>~ z#b0-Xxb?EXc)toUn~B}MMZMllV7}hDVL2~2h>%Drs*%Wl9G3e{2IE82Mz*#1h}ZlyUhyy033(VPh{9Vwd zPxpQ&n0kx1ox~@~G~37hnejUxX~gq{^G$N6p&o``%E|e|ddB2zYrApNXMi}CAN4wH zW*Ay)M7g!8MKoUNJ%oNnX;%=jJr+hhtlO%IK8D`%Ph>V|qJ!vCx(Z33JZ8oTitAvT zp=^sl$D`hRSmEO@*OhnGX4vl+Iu{1+`J385HGNVmH$YAcy)m?NhRk*JeSM&I9)ys* zsMh4&Mzd+&6v{~FotiqIr`KbN2C4?ymx&yEG<=UKJ5zi051bkUZ#_z43ev7$P5J$> zpm^TQGeLf`xaVR3-i!sTsQ#>x&iMS(sGug?hh8Ikd*ygf%R1`n(J647_diRQ+F2u_ z0-PI>jWQa|!(2aqlmA?K(~eJO_K*g-g5olOU_(H~lm09jbNIiN(YLj~MfUl>pk!OBBO`?UV(NMZT#Dz(FWC zlwPUb74k}5@!H*6Gs)s7~tZrHrk;}pgIG8BSeZ2lckxTCH4@7QmYy}GfYxq;8$(OnzyhuAh6xb{&r zD_@(P`pSe2i%#R4V*;^s2k_Any{m#hX*JKFK&28vT#PLx9~@Jsw`WAID@hLo|68Ds zOdke|L)8&}P=Bmud={sUEq6P7W{qlOC zNp;zE2cNYd#JFJDvl~xljzOscePyMio;#3OR5;7w<+CnWR3u=8h$@BD4{8W;f;T74 z1TEK-xT909x~Od9D#NkYb?c$yW~eOlsqoTE`7i#X$@-vk7yg`ZiqJX~!RxO`a|FLI zV%FzNZ3a*1?A@&<)9Kz-aT;=>`|>Vy=9@Nmt$ZaDajc;N`H(com>g`lGorV4%XTi3 z%fG2eP54|gIk%JZdUe#B%I4O7=_*joNlrq{0^w_1p5~|kR-X~p@sT@5J%E3)teF{~ zb9n1dGcN0*4ih^&TP8$N!A4?prr9}k@?OF9^4~nchD~M|YE&u8>fX04i@y9s zR)z5~xImz!D6HrIWhp!{Y$ZoGUwQu|EbgJwtR2VHvt-{IdVAiCBrIn(LDwJ2*;Y8xC;JhIl@A(jCpP)&(^;vM0Rz&99}VGR*JSZs1uD7%=g z7Yd%!|Hsf%Bn!QM#Lp8s@E^@h^~>rwkAt?N03I)Bm?KAP^jDuoj(*6+q{Yau@r>R* z&^GR}OUg#aq;VQvJd*K3`7g!!M{qU{&t+a(yv?}NdLP-G0V{NC@#RJx{3)|Lalafg(dW3yG=I7xR z4?`z`IYBdcu#2A_QP(ocYU{8ClN}hdmGQS2J!JmzRs+-U<8fKMg{IMGb+KSu-sd{( z&8hK_k(nBcf8ltAU&$+;AxbvIM?dn~{zXQj@r?5G>Q#JjT_g6I6Knxkv+p0#``QEmazRv+-U@w{0Vc+vbadDf3oKm5y zzX2D^e>9pj1K-te{o$(*4Y=CfptX4~s|dE?L<&R>9j5Omf0H+S$erqpZCNKZV&`uq zPXSXNk$wgCQBhTpdVj*k$j)~GlHyDzke1>eaq`2?%DtDFcl}mIllZPj_~U{-J5{-i z2$qO|VXa+p`S1VH3@SJaYqxJJkMim~NY|6JdX}40y}^y@qtx>C6_7H2*2GZd=Hr3j zQ(y4avw~Qg;NP0;1p^7ct-(yUpcQSviYdoN|gWarmrU}PdJ~#76 z2>nUj^+&xMpB?Uhju_ek2mE>i*Jqqq};mbWI{fAya7l*g=fvI*iIL^2t#bDw$O;sAI1zWJAw)+794Z)%Ac)jMG9W z&UJ53y}_N*k#EUNaoEj|rP4XvkL&>o9sW)z#+49W-*(89*dO6PQND@WTjt(0!t0$$m!1dqjV>Yvp`SGQQ5U%Z`-%B9;}qSC zmgVT$uh?>#CT+FxkSI|rgwhjur2L`HkdZ`Z` zzB+mjCZ1ekWwzd>4i;ysL3$;sk9T2{{4^AkgUzl=UVz+WK4XT2rrR$*^>_StRUxd4 zPijJ)xnO?Vx_-@EH6oi6B9z`x=%Kncvj*RFJ(w}O$bv#(>_q-2(+Y!d=8g&VhNI0v z^Q4~MH@QsQh)elC!(mGJkg{2 zgia|bHW+Mah~4b{p6^agB6Kv@i4)Xo%s#S_BbvO~E0`Ul#wIJP6?X=S*x`4~8or8D zwQ>>ab*qYSe+OpbfDJ>^mC-+{W>qIoQ>M?4L}+gRxs=K2b#z4>Hd|ydH;=`H<@RFW zH>e_RpgZ!?co4IP`FV8mnRbToWy{j`-oMi$3lqL*>1RZ4>eT{-y+iob2CK@wdv5!# zAyzYkfx;$@0{_&G&n*^f^aPVWLRW_^&Eum;#`P+GI?Ln3w2sdVj^6nUg0sU_&W2SadA8?uK}x z`&AQ7Ywc6)S){d}?uInK)bxKeZNJR9bN1i3U8%VLTN1uUsarQYRx!s+_PlOEw_I$i zFLSL?29fL3)BmyMY&aLLLV)%x+^dVZg>>NQ&*=rqc^LS+hZ1)qrHNc;+K^XKux>3D zlCY++;teeOw1642QeIK__PPnyCUAe>LOuhj2w**B7B03!8#a0u3l}K&bL!H)6mft- z-Qq!t4R`Drw33H@b%V;~`t2cFi3~~?M}o1xJpSAxIlx*BF*YU3295sw9k>H72k9Wn z^)EO3Ikq)DxE>B3@0pkM@7BS6EaYi#DP;mljdhMgTa;I%+e$CoTRxsr`B9aR7|E4& z^(Ke9gWrdbqz6hiJQ}fCX};603Bsuw!f&`jlIkew3B*sO#0j!nF?i=!S^EeT64~_}=G+Zsw*&_CeVd_K6Rs<5uVV^V*mvAOf!%!~P-P_-aM*E6Vze zo<)f7A`+*O)kJ=im~pj)gsdMaEU&%uzWt!P#ZHMHLd1&Uy&tQzsO;zAD$dg-%Y+M&N7$RN$(k0uBm)ciP8t2v7A3` zs%=E?6;RAp;ewXfU`0g^M1XZk@4DFgM+-eK0*|ie@>ijkfd3dc(n-){qF5fDC5DIm zw6)sKK9av_6!I=pN$J^m?4nPL+slXa^c(wjo0Qu*1Y>~o8!qbUeZ#79qsdjQwSxKc z)aTbm!zWv5@w*v{%nLR=zMTV<-oFla>fKO}52mW{f@HJSNj|SzhympF!*vJbB}LC= z1W~{+0nz0h|0PZxE_|fzbTmNevAva+stWyQe|jq2;lM~N(7O0?5+T>sY-&yXiD^#_ z^UuL^e{+&nxqEAt?!(cC{NqZf2_``LMr0{`=C+soB#|;clPW@6Gml}4M4NE z8-Seuqv66*>}!c>%U@Ab3O9Jo+PZ*K=%{KL?XwVCgWONBV$VT}RS|U@bnuFwGZ@+# z3h&H;(GnxumorT!y#++QWpo&Yz@&G|q_>}saRS-+4*byOk0iGRY^Lc+FHkjQ{8*Kq zvuF{XsQA?NoX~!U9+zAD47Jf2?P7=3R1#u6Q>}JJiEtdXgFrS}sI+4E)NMJG|tP zg+-dAhn(MnjUJR6Qzxj>$Rp<_0GQ)@c(HIc(X*59`|#1|55%HA$PpB)bQ7Jk1ZQa2 zKaa*XjGc&|Pem9Il!z|V5*gGh2ZQ$!`vzNwkhGom;t7RIN^x$y5x6Ei!u{zc>V(m=*MPI2b}32 zfFd84*iGLzzqXPTgg1Y|M7yWOYNSF~LD3NurX}j&iPjQlNMq}t_D>hVUG1#uJhkvg zSN7^pW)((bnkb~6tYP&*rP9O#Cd+|ohx@U3gu?nJ{?jVFepqS?L02~VE(bl8{G|6U zUzzIpv3&`dn`o$clOlKM-5sGbE$#_r#MErbIh1uEExg(9Kq!z-)ekdRVN@-lc&ZZR zPJSDVp-!KV98J{=8Ccq37f^3`OHLR);~l7t!HDOL)01F7WVl^{)gh z*|J!_%JJ2r4h5D86e-7NJ`>5=DG(W$*7~vrB)lY~bUrx28Z|AQ545_NPdR%g#93>} z=?n07Wq1K#l$=3u-v|}5G2b@_?MhB(^r+FP*5*6x*h@#MNBOV4yKKZ5BNGdiDIRFp zQY=9ZsBmoAjXjg8Q7#eQo7?8Ebx2SMBu4+(f_tN44H_rkntvKPa{QJy*~@QlL^A_a z_U%vW*bip#Q)M>2%z5iu)2wBMV!7%xcLKNPG>n!pC?vrX6~i2tZLnaAoyE7tO|5sm zqf{~Jdly^>+G;&VZ@XiV_@an%E063KwQm=n6?Mlr?Dc%R3>%P1{v@EVx#Bj6@q4;m zqSn(pPE|dCb}o486N7$HLYgz59zG3ZUl|zH8X7lrgTJ%ojU6;mRwx({hBhowxph zeRlIxWc9-^^u&Un-6iO<;tTVz8IKM+@%7uFFPaYl$N z@+qRgC8{Gg+?DvAq~HCJG&dX?fB@nvNRr>+?Av{V(attocZTfq{`7S{OZ{QM!TfkaP^jnGb|eJasTGV48eEkOVY?lkP;UEV zs4dp>^3F+7Gx2aGfj`@uo%ms+G0qf9D6Cqvj979~^vRDH*g!w4L(J(eFC>$8DI&{6 z0;Md$^_JKsqHk$cbJCD3M$tI7);aKw6;7#Lf7T!h8R$iG@B|8S9aF2>P)232_&IUh zmH%kyjM+=|<=zeRo<4s`jy z4`)v$`spIa$31_2cZ$EA_Kq{e;4rV`I&(>VXo#WP;H}%~^_u)$nwkTLBqkAts7~Jz zW1LodrMKqDuxd>O>#V?*B_W_tDnJ2 zRZ^!IV|4qLpo4dRybA$E2Uo!>4U6mGZ%~a$&##Jm4YgiYY%rO0Ab7`Tgjqw?rL|yr zzY9d`>A>jFsi}~<-Qm=zWNwjhfReuU$C%@;;~;tdq&uR`k)ttO${OBJ0^1m^7*7Pv z?@(nu2{=xWvki>T!KyOvB6@QU>^y#3LgG7E>p|MbitZMt@b5kjlAV%OX#y3jAtSpi z&UOd=B7U9WEnzOLNJ1QO><6$q^TjPmUQzLux4UI>yeCz4$3H0lrSCVHl%w_8wB*2< zWUX5cUIr0^3{p5T(Wrs0Q(BHa2H1=IRuA81rgZ5Lg&=?UQ_doT8S~l+Kk=UY2h9ih z@yFd|^Hz%@89CE(x2pXzj*6li&A3A^wpVjj9TL{2*#i$_S_7)Diw~A*^bY9E`*tOR zxXw)p+QgtA;ZKMuKH$<>OIykMQvWz~;Lu(mEcJ=;SE;>ED$a;po4{hOrJ!bijCa$m)NiX7VPP2K6m;xFV zflD@nTRQopPC&xoHjlw#to{8jenG?RP)v^E&j`K4+@q7;%mWOwFs zyKI1dg5#g^3Mw|iVIVR``i^Yi{wcs~Plac48Fe$W;H+w)9r~g9_Aj{3%~K!IpM6?` z{YPUL#9s^RWd@2T^YKjW>H1+)lcwgRw@ACkdnS)?qDI0xcR%H?CKo2UptTi1bLi#M z9l^9<-Hshu%~Pj|?t-32y#r&*(0vrl16@E70SFB-rZ&XumS| zpVLjgDW;m#8r>_7D-9N(J6}Yr^VJxI*&Ha@=<~5P1|;nM8ms9VzU>V`GW}8_J?r|Y z6zXHDf6w#PF_(0m9yTj~zH0tlKHO&#PVlI?$PbGGxuqk+(SkTPy}?lNyv{{90KY7C zhE&dt1xfYas9p2#sBRyPT%1aRwL8nNVdfHNs)TFn)50??#8TLwespTq=Xm$OQng0) zlpdu3L=sgH$kk~Rau4k$X8h~?;<;Pg zRPUUsF9}{tk!uML3+ACz$BhTkBtUaA zn&6ol^N`(e8>#cYb(}z;yJ%2Azo)Xy6ih_25@9{V2+yE9`(ZzAZ7Y0`=QBtXvjWT~ zAHVkz`b!q$`GP4R$mm>#!Dw8zW+}jleg*f{4xlD&Kq9KII+W5{Y%mt`kvPiv51zqe zFq`kGw}~~QT@B|M+2y6fVqIs~NAG?61Q)0lvk)oqag)eq*{KGQ1@;&~BYBgJ`p<^F9_aQhm+3b1;GZCk5Sd)qV*AeAc#gC`-I6V@6^ zFEcRO$W*4+^%8-fHrS;cjj2r^r2qP2nDI)7Go5H!)8%C%2x0Hh_T2h8*Kl6N@3~%2 zru!Fz2eN?R<8pL3I@kys=T>iRT{|r>B8# z_}h#FZx$Hc>y5cUnKd7cIPj*4WkrUjA6{*>&Z*YA6RJ`SB?7n5PUdIac^{pY-+tK) z;%zzm#lEN_NPc>_-!ywaD9#?EV@LkXv%4_pv`WkouCUeNVh4}U>&o_`edE$N`!StN z%G*Y#WlCI=K{Fj3iz`!FoS-om+~j*reIpJ6_3YVkGw;oLn*`8_Mc!1Q9r?cg8>V?m z0n@j3ensfQjscIX#!q>lLI3_tGyTgQzaRe<=h-`t^iNaDjF8QVN(*D3kN28;c|zwS z-Xe18fVs%t=1TUcSE@HOL-M#2{h=Q-meQv&{54)rQ6Z{|`UY1_!z_f@s6>sIPNUnqF1Ppw8)xkrfrDRj#VuqkQuu{F&E3 zIs{GH{7Qxw&Q`)tzE)6tT@2V=&8IX)LR6g&w_eeK5db7@?IImuZW)%TbqYnz(T9Kj zt~l-+@`gI2;ht&kx_fLOTl0MO0g@Ap9Z{4R^Evu3bF98mr#b5qBda8)CWcHA`8Hs= zdRb7VkFK;V<$0Y(XBDlJ1;%e zLW({z1Otz7-owPgM-NCJSe1m{`LyKMAA!21lNS{am7@0Qzz#-WX@e^2SUXd`&3|N}^QmA()3y@O-(%P4u&6K$JJ4-3E{h zD7s(nT;W0INyC%InDAQN@KpM=k>Ey6r{HV#aRNl2+?mRZ718ms+!+d8&(J|_C4-J( zh*Zfinw}~YJhOa}m!GsuzMQQV%f2seIp`>-H%f@B9PSE9)USKp@_P9<^WB-B;d(GF zV#_j=c^h|I;mUY`XeC5*1mWQldvV`FJHej@nVZ087T3>{8ba3$95@J+0y}I2|8o?` zaZYIX~X`;Fj?r;5VssPyUT_e=(FJoY9UDcx29T z2D!?iFC4_fs(k7CNtw%S=g(t8o9FpnzUS4Q$_6hj8u!%4Ms%!p623&cIoN zqB@HN#n~anX|J^OcU*>DHGA#mdo-nhFo3?c6)AX;9pKHpSie4}aBh3<^-?#zxd@bs&&vzfan3jngz7~2AdSZ%u+MFzED zK0L{7>8G)~4$cI`r)DsPpv0ihe0i$uL>FA-U&4 zr5TXBA+F2AQt?E=t^blYCu0}nMy~58m1)K3=dwwn_J%u0jIokkrroOPrnY4R8@oZQ zkMEPjuVV#nTS_{SrXRF3aOj7wCHEpixpsCdc?*P4qNqo|s#|mV0am@G^iz?1Jz!&( zUx#Smm6nr0zHE_fuJ5{kXbG+KNmrZURqrI30wr#SOl5s9#(X(E?(N5AL5!1hd%Vfj z4r;DN-_9iYb&T9En~EBnIzOG3x9+Q~V*Bb{!cnfut3gIB!-4=|6vG}8M;*_}2^_L5 z+a;Mj)L90i$%M)}Jq2Yyug7Q~-*-68kZQclc0KKPez1suhFG~xaSrcP7XfK_qv~x4 zuxS9^ih9luThsOq4ljxDllMMM{a(jWJ-N> zHzrE!woI|4amJn6ZG)OCFI2WI10?3tvP)cWZdU39RHKquwQM(+Z85imqxf0x!b>BM zEH4YPg7uyB4Hrzm_d8?DmgSd)y>xDy8X9UZFNv45q7-W?5`R_eH&_MQR`~YcGi4p* zU{r*y^iJk`EdD6fsLJyR;K{BZ7vFt~d=n18e~IODvYozKvPFxM!sT4&0`pXDq-%&~ zAW}6vzU=zdIC5eTW6ZxGQBF2bOP6XNwoW-!^>?HrZ2H3bItHYAS7lQ$H&UL~!2p@9 zX1V)4<;_vPU_kvhz%?xE==7DPPg%M5U@5*xF`p25H%8o?WW(a!n6zvCgBb?~NdP}S`>aeq3ct!o{B*?Abs|Fuwa&DZU*LSYDz%E!DXavpt|*Z;Pn+Du4o&Ix*V zIat{`e2SPt&n;M+SoZMYXdd!F=<`rW1>XEh z!IYuxq3WSFlM0iF9~@0RiVZwB3(|Ud#Ta&ec!pPtcU671%3z2^LNnL(D5Xpb3uiu~ zG%qi=41NeHYNisLp)xnjWGwOY@y~g#JHMi&f zS6FUJGP8Yg>dH1d>bPOoAaEADs)$$0$hs^0+BbMucGQ3?y@mVpdXlmE1Hneiy<5!3 z&EBTyA-+Od;+W^x!oQU*0bMNhE&Z+c)7!$XsdSCrtYz-U%k>U`HVz}>7?vJ zlsW?>KNhfEba!HFFB^WkmpneVN+p%9iyCIs^YS>@+1P z=Ik478Wzl`ELo6$sDsv=ZD@a|q=@_WT|ZfFC)sFl_*FeBMnlW_3{!QF$?Aw-5pZ2+@HC>kMcrn1 z!)|}$_v*St1a$G2v^48s1|fKkYfg()(_8N-MK!rU$hk&dEuP5E&~IDd{=iz7T(XAz z){OT~r;XS8(u?+P#S~V{Y&B0p631#vzWf#7c1dwGY~j?$gzPEro49Ez+f^)o>tF9k z9BFywAV1c7w7axtzA&N_xj+4LoFJcS^*H2~NOlAGHbCx2b7zCZUW6~cdJR3@PERf% z7(P*pFq5!-TK;udF0%A zE18<(Mw{TxJDRgjGDq4V!5A+W@Mhx(PKiIs4wWiy6Fn((9E4e4aZQxdiCjq*3=dj4Uy0^O-T+OR$YCW+(VLF39d|CNM}pcf-IWo z$X?%cf4iW!x?zlYFJX9Zs&c9@bt`|WqitX6NO?7m;Wd=2Ki{u^;BY$4s5cchb0D;96E51tE%*&Kztz&ViFKupw|x(w=Cwg3(5JB&WV;D_85J% z!1nA38La4D(fQL(Z$&$9IZWwd8S{zwwLhs*V|2Psx-fov*|h~c)|sK(7$y7bak9N; zs%r_fr%h}c#e68Tgo~N!QVojBFyK|XlS;C#t6VR?`}mfPo#W8g0V3(~X2Typ)cHU*_hkKZl}^jOvAYw>61*9-boWcUizU@NhtdeczBKK=FtK%2yYw)acKSQdY>F0rM9iFWc$LCVu>*)eU=~ZA@L?bFp zt*0@2@quHsRl~f?+-yYG<*)dK{3zB>DK?h2l;5X1CrI_;7z&m8l%PMmPLCceTh<3nDT;$q=3PhOvBuA=>$I&tuYuVdJbk!qfV+A*iTJQs=W# z&e-+G?SeO2gV|)2@=EmutM|ZVZC=0k7U17DUadKfXEkH?wj6IXFMky$ncfB@v>_`V zHj%${+PP}k?w5P|1^awwUi*0y??SyYT1?V#(TMb&dY_wvosjiTefU&=#D-%Q8)z#>{Gx3j}*2` z-I&&=AzgW)c((Gnr{imt5Xu*4gHjy8eA2Wtv(#^7&J?oQ;JBTgo>x|1Uo$U}c`fPh zqaLN#@I~`gM2Ynp)J=Q?2p<9l)nXjF79ub%RZ`#F=#Zfz@L_>DJN68`0lseYF}OQi zjjXT*tt-K69k{IaSVOxL;v@tobBsQYZ;zmDId#mn${R4>> z-M9lIeyl;)4B&E6H#|7&#d$OxvcYl*GlUwB)wZkuDsNXCMVVaLy1mQE^S0?f8n$pR zVl~+}@~^!FaJ1D4vH*!0Yp~zk4*BL3b;H?PEU}zQG1&bUmxl zBX`%$NpU-gO~|>reS9pu^oavQIW0ssC?3|_*xz`=tHd4jR?}VfDz+z#zo(7n0ESmM zbR?);l-3ztq8K0EK*Q8ER@{ChkPVDq1s-9!)199PcKKc5*;MnTSLTabtu!U{<@8t= z=HF;OurFVZcw!#LVCC2lQLU%Xg2cQJ=)kv&(7e0x{Pzf7>wA@qdPShVtyLve#IEal*+#5RyxZjXC2=Zbvw2ynN-!V|ntoqaCvv;E7YK%p z3>Yn{8VtId6^+7XgCw&O!guN|Pw2#Zd=|6I1=IdN!%7nFvT1x@sy)}qFZZmZ&R0v| zD>%NjJtBS2EojysGE>v{;oK6VLIbCm@DxK8fkS!BS8VKb-qNnhL)Tx!yl& zp)xCIV-tOQL!pgG-F+2n(S}#aDgrq-pYO=sC9xV-{4`p+cb>}q36m%9?tNe1Qx=Po zuyNdAPkex(V>wC4oO5-c+wvd{Gj{PQ z-M~aOojaR%>mpYd+qMoysyE#adP9c=WWg{OVY5ZQ<0~pXATgrna-vJ`iq6L*uG)y7 z3KsGDk{i)^q)W`{H5y?G5$h#ez~4XncU}WMGUw!Ou}7fuM?{m*pbc@tnTJXINDEt<^wZR7TB>Kx5`2dsf9qL zaNnMn(Z37>*k^)XyA22IW=R%~RruBy`kg-GZ7$D-$U>qv3x8Ju6Nc{NLqcYfjn??7 zD-vAYx=;~x!@Ff4>;>WEJ3SJ?e|Ia z9nf|1w6m&4M>_+hHhl2t>$cAzlV9ZatETZ-g8q~rAx2;NuC{aH^WRIk8O|e% zx{;KCszga$yz#oN?;BzZL?X%WmdJlCde*$3l_0nqH?`fWT`Mx4 zD;NSf!#^P%c-kba{~c6LHKY}nP6lv}8%e%FnlKMRF>0^Ekkd$@gTp&%hEM&l?u(_I za9WYlEFL`fyqr;#TyziiNLK)W!L%|EWMZjoqq`G_cX|wbygf_pT@B+Mq=y<~1dq-) zlPVk%VateYigB4?RdBpMER(BW96~}uMg!>*LrslQL+j$YCP|(5`;gc7_Rt|*hPy4n zTU&M_okmHEf<%T&+wFYbNy%Mrsrya~8Yo|}wU~d8X>uI}kZi+Mntw~{(}S4NNBF+> z5w%dWke{!T`jfJ?Ns(S&eM@V|gO&O)&K`4jxC?MQA8QJ2Ls{EyQB<1S44}w`;85{| zgs7+|NrJzwo&FhpoU9fGB7hIn(e)O)o^O6wFIW@blG`%@!MLl}2Ashab3_sa9Xdub z|F93PawVXeKRUce-%!sqYc^tf0#~#uz`UWHSXq&y+wU4L#X zrCua~UCrDI70E`lviRA(C4PcC_RMRyW3q_HSv9>rY3igc&*&EzaEYOB$ii;GuHXYNKCAXP}uogWnwfyC9ML&r|q7&x@J zYU_FV=GK;siQZa%Ny&@!ooo>0mT9|8;c!GixvhW{+gsE_lvgnQC6@OZVKZ+ITBz5I z4m!K7qX@^_Z4cZPVWQSsESWssg2Ff6sD6Emcrd>WV>vL5T)zY-8nGD>C15>qw;@yV z^^rm9*5QvWY5#Q6C1wvd18Pe{xcw9*O|jf5^~q3B(J#aAi9Yz`DS|QZmH_3!H~0yh zr5SmsS=59+VKK%*+gUW(C>x93H@#iBpJF})&m7S3Pd5t1|AF4CtKDPS(fyA`ND3If z@=%DRBLQ~6OUPS!iu>hu6y-Uav)*W-!u?+4lK&qXNAJ+{jiGA-FZqX_9YH?=krex% zfZiAlVK;dL1`Vl2{pU3(<0vcM-wZ80X@CCo|3TP|7k@M`3$}97C0C$jXQHhie#OT0 zu7@lbtv zpD%=qR8LUZN-N@o=u_m>FT>e&vpZo{Lo`VJsb4uMNb`oH2 zD~@z~jh)6Xw7tJ}!?+H;iGmyX&}G9d-)@h72KmaSOppG!c_*e-`YQ2>j+HzyK0Ly2 z{m>E;+IN)4OucqoMG?8kqlABpfiXbvL=#r26o zGwfN-JJ3bs6e;5We_*>lN}Mc3bUD_VIsx4RY{YA|sD^hjNxr^H@`*GYOYc>W?HX;h zt^Wp9_r@3W?E+x2SwxSf>_raRQ&f|e^62jh*}U`^fYl(s&De1>?nb)x%@2O~5_*bg zLwk#}p)QgrZ`j~pD>8fraxz1ITiwj1@{%pOaI||0Agm{01h(>uOS95-Swrf6hEebc zBK;AK;Ef8EkvkunLeyvGa1Fvge3s#}XWhy8OZm?4k+a)2?_B9V4o~r@D7Xm9k^#!;UlTC!28O(uS&x6 zEWTEHn0l&D?E?=!hn=}XFg_>P=B8oC#?wExa;E8R|HxBZ)eFba<~n@*;8~PGDgri=5f~2ZX5~+5$4*L&EzU;;#_gWv2%)OKr0q`UIZZ93tL!+!>lMJ9* zV<9*0(YASCT*=%kXT`cFPzf6zp%;r5fSH($g)Inz!KR0haSFG$?vcL1T9F$+OTHr9 z!a9C~OZX-A(09o#VhV{!vQ4Bl^t`o%2yL+?H2uB*#^xS$ap47d9?>fDE%NOhPm==_ zJ9)7#r}1i;lIsQ--EA-kxefRKI}c?DpL}md?|nd-{LCD&qk9;EJKon4o$p--+B&|{ zOp~%|DGnWV3H#3mBHx+uhpa8N?Mk`3b!|1&SsZ$C$UeL_|8f}5gc0VGYc`5$G8Z7{;r%OtvpA2UB zV*3b<$s~*%=xFNX?E#C`ziXAE-6PLr=0_@0 zEnG`4zD69NRWG)^Qt;R#>0yeE=P~>-Fd-5>Rcp0YxM3fg*U=wcUROI*cK)n;oi6L0 z#!@YkR~AfqFTx3WL`U07J`6--r$I$7O@}*f&u5SbuQ7y z-T1pxA+IanDX}Dp{NXO_kGVx6z(zf1`b4(0440}OI~CumG7G=Z7EXGDyu4uZ04H;| zgoEdN+N6CdVcpZD;B!>{^K(r@#l<6SIm9=MDJ`ff+S7ZTy7ypOp1S?OesSsmiU-!N z%L4~z?dT-T%zJP+b5(HKtFec*tua=#fL?6Hy{ou_4IRRAPHR9 zzUhzVShL!g?M1y}WaFd5XNkOm^j{wH>WG>th2sLu8@<7tbN&SGBMN$fikCGUo@&Dz z;1VbOlrjM|=kKrIc%K@b%6`DT&KdM%+ajqXaKA|7)hS5M%+STV7ONKt&4R`PrX< z7J1Lq9K-lq&ff0^_o4+UY#!JjN2?bY=q>Qo%2SQt3(tKRQF0OpJzFLU87aE79-EzU z5Hjdv=CAfB)9~+e5pP)ba|$cKJTK2Txqe}i)n8&fx0qcIeW^R@2>qE+gd9&VbgmErpkOxbFClk}V0 zx1S;zWyS2ZnthVY$uN}zS+^jy1sS48@}{5*i}+HSMogQ6ltxt`!c0$U=c z%&?8;sq^o}^wW!BVGZkKY^LOfPTiYRRU#od3Vd zJyJEbZxuFOjBU`K9r`z*6oQuh&D*$Ss{Wq z_%WO($-j|15W=0AdHg?u@|K=Y`sf&rct2ulGGFkJL2~>*nqD|Y)9O=;EN?v1vU5!lLUy@5GHhwzu2k%8o-gal}x?;5vFkx$N9PVX8$}dY=`vlCA~eHy#cNoZP)S z>Qv+kk=#=cX|M!VT*(uCK`A?;=Wg*myaQrDPk(QMHL`vx=_;lNMWW765UJb&A zjvdljouLQ%gh@bgdCljNDqq67NS@rhT;#Tqw%}zt>bNI!c=C32U(KFF= zeo4}>yoUk!DM>RxKmFqYjmDGBFCJj2r6;$g&$ZZ&at6L=u3ikodgv=%?QUmp>o_4( zEY{|?9U-dk`+MlC#PF3BnIEz;tSZNz)yjk1Y-u=SOgH}U9ujA^jRGTeITpMme2Q~g zopg_-Gzsfr?y^Sn)IChv?%}pXrRIh?xD3HDH%hBi%!KnZ^S=m{d~zq1JJ8%H-5j$7 zHch70SLx9JsX{TS>}LKBGBpXvh?c_<6_QVWaTIGD9_WUs2t1~kG~M7Mdpf0XzV)tC z>igdZfaUo8cz?QWD#pN5`L9h*zik{7l~Rx{rKP2Nic$h1NY|8xF-Az2 zqM)>ZbcujSj2;^;odfCEXc!VBhQP+go_D|Z@7+6&JHK&V=lMBnsgitN<~Ui&R1a44 znf(}+b^N}FcKr9NIC0b2p|#@;wD|>=dMT*p)`f1WMDL^=h)KWMH=6Iw3Vv@UAZP7> zMWTsVxJ5AA$Sr(!?xB}qZicRJX=1j3-Cl?`NWOI*)PlkGI~4YixIdug%>bhuvty z4a?CCl-gY~`j(oxVM(&s{5G2u7;N%1Mt$Zj9SIeQ4 zS{JCvci2}Ui>lVSFVY?UoPwMbX>&>-j`H0G z&$}?W{#+c%*j|;`nelsU{E%t-au<1QzGtK0cw;(MxBs2{TVnCod-i<600lp!IsU_O zyb&I96li&zh;3_dxAsb1jDPCPXE5~~e|t-yFOa*s$^y{++odf4fEVG7mMdI10K{d^ zvYKBAb~ikAeKQ0JmeXD5-eFSG=F=v;_uPP6XT8ofuaimb*haWz>Wljz`D|65o$ysT zY^8tW(Jb&~Fi|GXW2$TpAxc=yc37deN7owrhq~Tq+5uiZ zdRy=`jcsTJcV%ejw4ywwk{Ri+VM4dKU3?%rsM=A~b!-c|QeZMy;2~XT=;SD}&8-z4l%cz`Oj*DU}V=zqQyYv}FPJ zJXO_QC2quRnY75C1%xJPwSWRZ&L_odR&TzlY?KcVjeDVIfN;H^gjAigpv~M(aKcfm zm-26FeziyP>Zj1YeGQwMe9u9(rIBs0!1mU=P2ShWR_;gkw;#soe|io^nXl??rTu;g z%qeix?9q0?IR}`!jCf{nuk0ttxmHIG{yLDrq^iCZ+Ifg@S5${iTRg6Nc7F9^8?QYe zy7{NU#7ElOK}|RXh5c--Q`UoRH^{fVqfj%kSpF&bDs)y!j$xfw=qnBlU(FF#cI9pI z4U-#(3`qHo!e9_rnt-hSram)lAa(Tq0l(*`t2$wU>m_Y)j!+ps0+=tXe&lwN^9jR~ zq5ggPb`P7HM#DQ}lk(k)gCi^>C3ct80Hp`sM%VUCA9g6JMCshF=TvoUz=LZYU43}L%>q>@%RZVX`Lr5Pkr{a{0qwg074~f={JjgbeXYZfe zvI+DVZ`TUOp=C#Bedj%o_KRHmNtw9@yZ*?A!%rG6XA@u-#;S#PZUmt8Owz6 z%_R4d8#d;-o{0=Ya)qHz1ux1S^i*xOmUeZKE-QB7pUpwd``F2gow2zLS&w>F!d>yY zyR@IDH!m0A73%1(*hZ~v$#0}e89SX562fjpL6@ZAaaTCAb@B>v%*QnWIzi%KeD2@xh?T|GTBW?;^jE^=ZTpk8ANW2KQJ`ioUM z2e{pvk#b!8{vh#%^Ypflz}4P^?a2xxZJ~2*1A&7%>9(;KjUg{2Mc^See+X2^H@nzg)2^>;j@JDD4jxNKr!) zx5?tR$z3bK{OPa2Vnb>1iAUyx&I!`WRBuCbmVcVXmeIR%)4F5kt(M*+GfxkV<)>9j3sDXyUM^cdfD)2LX##xF8M1jNc}X2G zxj>T@_k+42*w3f{oZQ~HV2+{`t?pX{iuhZ3zd1Q!CR_t4haeA+)-@&!H?%=K=M!aK z$&j+g{XW?H>;yB}xz|7QKBGj9q)Vij-QzeYWQ{WZ8oF&A=n=)6(Oa<=# z@yVjd7bBgQj$)z%{$3RyJqEf~S^M}AOo=M1GG*K1w%$+Xg5z!a289RG?!|Uqn*o~LEZE2d?INwm8QiD4kkiNa!9h z;p8N<{Xt(|G~B}pgl-HDp6(?XJ_gS;W|!u}1XIdVoXso`-ntbVNG_EH2{x-Sq2iqL zz6!2edo5rz`YeT{+j0S)L2qQ8&epSjDmft#?dVj^P8WA)_~Xuu&W<;!{Q(E(O1z;3 zjj44e=|ghFFPQ(Rp1@O@7F&vgnQr*I^yo8*f6pVKKM>-a0@jz$oTJ=|-5-lJh-b(K zC)uv)UM_s4`d(=7am(NEnPo%vd2j|!1cnndYcm*KeIv8}1QmKjRr%V(d~RZZu5B2u zTRn24s=(n5@1rX*M(Z0p6hfpfs-J%-$2}L5K8Gy0dwFwOD?>)Z%W^a7C5FUajcT0z zTSWeoGF)?B+_A*?aPUgf(E{q@(D;2Kq+x!DZ>%ZcoKb0+QBPa|aZe~fM51;Gv5{De z!Tgw!ST>Z0NJ^lbCI?)vjkBXieYY8Z8$A#fSatT+6aISZ9k=ch=y=C`1j5;STm@ww zNS%n`@hj5fylDtU5$7vc-1OD$pT{x7UE;@=|Fl;vI~Kea?U#LU#W!R-NyUsaeqg5R zyd?3VCA%H#NLylj$3z$5L)RHwr35TZ;oOdO%TiK$9{7zemAAd{h2i^_(fCR|f3*?O z7K}|`2HKD-M&#^PZ(V*@?6z8AyB^5PacW+7&LD22MI>9&MC+QLwmC5Cv6_=FgU@VA z)g)(voxP)sa@dsqn2{>>-K*4IOcJr_Uj(X%`CO7l^98Itlv|V^nDUU zK(lsk7|`yOG_zFR_*P)u{n1zJG2CUDM5=ezXD}#SuWV9Sr{MZzo@cV&)AtdDHN#v4 z2qL-bN{nwF4GjSvZIsI3+)wE=+`$JdTK?eV`>_!Tojy-ApWS@0xlsnSiaDhl$mG<* zXm-n+W_6En&{M@dJ8#$_99!jISHVs(xhCGZ0_b)?x!Z8=^3yI`5UdwRBQP z+2SsMEB{mKJ$Zx)#8%?$K5x3$qOZNVIQ(^P;J55W(2s2KxF-=DH;G@Ff zNhm1d-7?up>+;f}k zrol{+q6o89Qdh$`*Q}|peBPgV9p5_CkEVW`vP6ac4=7*#f$X#oNu5%1S41fSIWKmv z5}o|lmwa*v1K~06y%XwjgDJ;6Lb8|5;dhe)*Svblh`=zWc{cvSPokwJQw`;n-d2w5R43nocb?u0wiF+l z1DpjKjCsyZYC<(VYWqumn)EE}_ck0FmO^v^+E|j_*4D?#M;a1=4=+Wlew z^eMr);p0@AJ?Bx(fbp@#e(O3)T|)9_vrVPdlHA@QOh@jujNA`5VYVcUQom-@ZJNT6 zT@95mk3X5Kb{&}%@2khO)M^xU6nWW3xp?{Mo5>$+q{*Ao4C;PyiEWpJfKTudx zT`+2tl~-m6lPAflY>kP0+b)SBvpQuC7rHj5BFzJhWM&R%>jg%W1nholy+T}Lr^#6c zhu(pk2PnIjUwR~qwKSiVo#`c-t7}Od6pK`hs0v=_vTeb=t~4YmUo8)>&|T}$*K6zl ztZH(*ZHi|D_Hw9oa{YR|(hvUC#3z+4>t&yKB%hSHtLly_R`#DQyG(ScdG4V~0Y=Ft$*jMo9-MJ6SEas%`N?8kP6=1 z%EZ|6T2m$M%4gdvScZVS_QL^Z;} zFw5}^&E*Fcrf>Na){U0lrr-*~wR8}6cHmpJgB4b0Y~7<8e+f2mCD+ZH>TT_8Uw)a= z-j6sNN`2BPvR$!3$|>cI!9v5H`p#BBX=*KSKUFQi|8G8WnvlJa1=v*RD?k^-P~n0XdN)`N(qICJmNib&h4>Y_sFzHE5iM{Tl?{q!fcY3mx<_6gF**)RY7_Q*w}NsHfk=R7SH_aue(RQQACd~J^U+jo1#RF* zkF@{xb(Ql1@jaBJ$qr$Pmn^Bd=&z#nQk8KPtA+W`Wei{?)>NQE!=&tMXaQ-?ZbOR2 zI!yg&3|h5okm%|PlAnV014nN~o3bVg&|)|JfMOAgKv-E)8}D&iSHx|6aD^Ky2o=9%E z=cS6D-f4UB=g{#4EDituM2G#n;^M5m6tCS^Bfq36p)ezz=%W(*knk!$VQ+Zzi0!=6 zyyfGN_i_DV_p;ZFrQ{t_g$g(_0LA5>HdW5sH}LG$Qp9rM?JDf_Q>dMx(5%1P!&IIU5yMnkrzrGh_(}-A)AlljEVLtz z(^|bWxx6$`Bt4skIt7t9D{O7V_Lmdy$CdcR^yG2P>C}Dp zJJ&s;rjaY0jl{VXV|nqAn&{)vM20U-YK480nSMMo##6pgB@{KeP=h!wOkyB*j%_aCi5A7 zNAd(&Sn9z5v>+ArMo%?V{4er2$KmxWok~MvO2VAY)p_blqIFwpq>~Q_>kOdvyE+YA z0`yR84@}wEQuNd1mXu-56eQ|x`58=g~LmGJc?oB^_l zr4mWE-ACUV-l&NX8;h7|*$%5-X{PA21uVPY7tsiZ{nLP<$>W{3G5F>xgA-_vyNV41 zd~Ay56Yef`(5R9WM#1t?zp8&tdtX2O$Fp2ZvUE?VR;+Oetn=SE=rS+jp?%N@rO%c8 zN$NLm zPaa7L#(kCT_tsTsD0NJqFnm!xw=+MW3`GhWg-Re-KB?3tuiuQRvz3!ZEwe{hF=~HG zPI*>RMm_KMucmE(BM}0fxM$%ACIq7DE0O{qZR`N^bNZ^lKhXxs5vevBe>*mjY|n>O zGq=Zrsd*E5Zd}61f?upmDOJHWhl%+30!lD7eG z)WueHc*FcBi@Or6c+Y?80HE(B5i#PD+5$0Zfr>^uFAa@I$U8C0W=1zDSV}SauZCWV zZ9r~OgbBtjF!rWYn4hDsQ9(*LHN8y<#+(6 zAQuWcS4%U_W+Uql8m$}>EeH14PH48b@6hXnoR3q|fLg_pg-*t#!rU+x%^b2_fd4h?wz0%fGa?JN`;Ur`wB(1~(YsUW zMc>-A0h0Q)hbWl;IrHh1t1crk#m1wO)G0aJLr+OnzE$ENDY3CQ!dGUuq8f5{dAh?A zg<;nAAFen+qeF-xuS*<;OD#M-Q8s?yrPczU>DOPX-ByBnOxmWf&}x4hB7T2b+}O^R zodqqaMD@@1-PM{f4SeVN%Exo2$ZpwnuwT#kyM=cRZ9$GHv4i66xBmUB4)?kq2A*$I zIABFl&ig{=q(QZ4i6UzpCV=03%jtq*C635jArUhu6 zF#5{cXHxi4J5oMGYqt~eL<}VaP_$-j;gzz((<|Ca+trK5&M_`A`cV~im24d@k_*NN zC;E>CV(8A*e4mWV3ORp@IL^-xBGa)Y1$%K*nPx(dZD_|9@#&jD%AC%+?Z6)9WBMQL zdu=AsXz;M3XJIztua3O$-Lg=<6Y%TvjU~7+w|RL`;H#51mHKoiD-9QChb0P-wp}y` zqSl$F%gaDY*;mzJHs6x-b8`PV|@-CBgMLUL@S2SV(XcIKG>7B(b(bPWGxZx1#N zvebfEkv-q!RleI>MBL6A;Rr5Nl|r_6ob!}|CN!=MT3>%8#7QLctEHCvIh;~V z?zjFIByEkBI(&mjP^neVwu!6xK>|#+$qFR@TtF>W!iT?#B(na!f5n>RIK!M%Q9jtB z&j^KDOa8s&3zq7O5UHDl-9ne8uz1<&?sAUMH72bcX}P~-N^4|tkxh-8J_YSr!o-B( zZB6iIc-odzhV+Qp)YSKbKTp) z|AX?stO(G{4o$S*epX6So*=36X1ar576%oVGbC!}pDke)cdPtt`uG%whlklCt$Xm$ zMj)|jLzU(s0$rBRBUfRZxIi4~~G7X{qv=8D>OJA7DYNVazb zY^{KjOd9ngjNw=tCin?(SB}l@WHY?n8E#8UZ}n9~?Ogt#fazE}d&5rNORkb=gSU#D zMGbOu@_aI9b~B4=HJ2+>8d-a^fVUqWHvxTun<88UvrQ>H5%U;qy%#_dQ^|U-q6QF> zQ`!3Q97LZfcf)=I<6P>Du8250JebOnXrnAi9$Rp}CuCmcP?-tZa5haIETVL_^;%^f zskUp@&SMOJ@ul{C6Qa1S7O_Pwt7GZ{Vs_q{wk zE3bD^_)W<4r;@~0{SIF_G{K_CyHjevD?fWg9{D`Evtai#jze?exH(|r2@lqzBu1!| zrZw>BfZ#qcutlL{ue*_X53tpK6_0C??d07_*_$Y={=*aY4@Bst$O2CKd(pG|z=KKg zg14BQhTyPBW}!Zcwg{HRV6iw%$1nZ%^6+3%3P}NlGjm3ma|ZmmX8ndpvG>eRdzQi@ z=?vHoAena>bDzm1cFI#}H9l($-vVyy&ha?P@{;@9k#I_7(52WMl9l|wE0_rwTa2wo zemD>GX-T)3!gn6#+y{FFhVN#3UJqov1zt)cmf9TE3{!NLP2X3T0d7V&@%HO;5xG9W z5Pwyp2bRp~q=KhoK>@-EM6S8r{?ZoJ0D_{|@B#S%g!@dsGsM*b!3wUb_L(~yKIaeX z6naUo=*WG~S0!;d{jYP2gVd(aM$P_slbSzK#*Hk8XLVftLP2?f)Fo9_6&B;__LDvG z6R0-+(1xo}%qorWeT(npLEhSxWUNiEh5Z9~o1UWhZbIE4G2%%I?P~4L)FH3+DG*hB z_L`TwF(1&++5tGenFcD|v609a`&%M@6DV*kAqBxScd)H=wL=>J%*TISYCdp1K`Pw8 zBI4Y^$X_-CSN~o~SgHG_5-&Dnt~n;5tVZ#5Z?8OvkD`j3+mI|G%Hc-`n=pKdzVN_bn+<5>W72`ewmZ*g&Eb z+K*l)vi649LAO!=a)-RW=krHCj%!WhOQm<@J{}nEX%Z{AOzV)>Cu&8^MNl8hPxkrv z(dW#b-}90I$FVxxT{4eyKKED_rXm~8x4$W^L%k^PwgMN#A6#oGZu@6=zV_nDt z`}~y8wJ|8(70K}%)$}$~=?TR{d$)M*q~- zJVmqNu=!1keCz+HETdG5T(#yeM$RawKAzC&1h}zmCy9!ga?l30pHsc^`!Fr_;&h0Q zSRAkfTL&DyG!)wC`H!mZ@B{XMbvyJ%0P4io@4^C()>RbY6`eymq?&DcZNr{g=Y`)| zi0~AHESbr>vl@OzrmsIo-`xJnw|Pd%N#rQru?|b^S5$fAv~+HHR@2jof0Q{e9%~(l zRfo>+U0hzmq6?9wHlAIVclao3#>cMlj^Ba>{YqrpRn+_XR~6}7JokD#k4hGf64-_a<4-n&k`;4;cmyckzfv7h)=;OX&puKITq|| z0}Frg7kr8%pG!u3_~u#|R+y2`+bk9X*?VaC$$ND zn<@UHPmyq4zxq~sm4U6h?PZ2|d~mJoyMRS2EvLR; zKXkR~KdQg{z-RN3tIe;Vn9Q{Rcu;{>yKAgj8^+mG)c1Dx#{v?mGLDdTW<`0@!T9sD zUqGxXrwvUceQ`RXvvZnXD?x~TJhfACiTIt~&@Zx)rTG^=&h0?5MzV%|8$9mAU+?G= z)b(3gBX7=*$gyYLRC)}0R!a<@M9FtI2xo5fQ>8lrNLt=CpqVP$@3O#icw)t zL93B>gEo4Hju|n_V!1W7HeF|Q@}*s|?3=cow)EQi{yVm(1F=w&A~77a*n_S{aeFCS zT=KeRHh#Yn|0eIsoZ8uX`#A72F3j*4c$V{dojY;v^BRTBqsE%HYr*l|B1y!1rTzNB z->g^PSHahq{U0;mXKG#-y-%nL6F#n7<0(3#UZ*^|Xn&o!i`{V$p`wOg20`1JOvS}B z6Rn8kr_LSIW804({g28j`Ap{x=q~^-Cb+&5v1p-d9vz=aJaqK z+R40X9p1fjOp0$YI+XR)9xvasPv=N7{gx~P`?gs3j{>kG-ouCX18$rGzjQLTx%#hm z-aw%xs%SuWBxZ}e19&Bvzon#$U!lsYWcqY{8qi3+|GEedT;t+V!w1)RSkHd+i)7A@ zH-;s8y|uW0o98VYA9ci9EGavSV7Rf%dzaDyyxnN@Ima}UqXYo9skDo z7o1THAvo`xMe9?LYf7*5BLRa+3v4!f)RVfyt4rCD41U{TCkkmn z-sp+RdUV4!VI%3|<+9j>M1)e%dp#ey0{)p)ZL)lee=g654?FfRRpQGnvSrVz>5iJJ zA(=W{mA_6Di*@!v9tyL5$lE{}_xnF*av_WsllI}?sRE}@XibzYnmZNJdx|df2wXi* zc)XL`jhJP|`t7ksnc3sh&m+444gyIwP%;?WD~;87-S~Fq!^WZ15^r?a6fwjtZKs2M zatn7LDb5l8A5}}Dq;YMMhO@xiK%Ne0Ul=z-e=?Jv4E9*NaUa?oxT0Ih#^tT}CY-9e zut!6w{kS(xtJ1?FryeEK*KrcIB6@X6M^&eWZD{}+()^M&la(41#v9ASHa&zB#UFZ= z4ma8P>zKJf%LX%=j4%efOqZ?;6!OR$hZLX2uodGype}`3+re;|4RBqe?o%26ysxIU zVZ^vxSo^fX^0I)tCi7cU_w%n`dfwDt!`Q3Njh?}Kwh)O@lGbZcd|3TY4g*C?CpTzT z1jx*1QgI!^3wVYz!=sF%;5AgZjY;-q{Ul@1q!QL@1pCnDJr(a|2$6QZq^lxJ` zY3ggYjGyn{Rv;#54*T}_S~rkUjr9lU!YkQzZ7CR+y0~)@xhUaPe7%pw`O1rah9@Bb z+Kq@9_y zn97LhWFfANDsL0p=EkhU#w!dyn6nyw$Q}QT)ZP}nl8m`_SqqWn5aAX3l*C+)h)MMI?QbD4t+9f_N45_?=O$KXcEiR()MiQN$$ro z9(M#)RH9y=HgVGv zUmZv7Ud50N6`VwdvkDdhXx}^{w&8TQ)%Qvp{%jLfMLT)}aOo!C>Lt{c`ul%110Z00 z&c681Ir~}uln8CJj&!s4+ZZQE7DL3${X)v;85%S|W;C=`ND+w5K7C{t@c4Q(XZ;oa z9ecUjn&u0GHirDpWs9Z%&8{(NMk*fC()9+E;41>Wd*61|SE*lRIxqv`&(WYN^X!{{ zP~WsCHO=RQgZ|)gjZ^%&V!uRypj*)~eJSV3iBP%Jy8&~r$0)X%mzQZ8DnZ41_~N3{ zf{JtTxnurk692la?+sbJ8Mqfk$&=qJ@DS8bw=2+aUA?pw;t5Kw(!%{bgYQOUcaL@0 z8fy?uU!_)=P+ufg`z6o*unAQST`F3)`Ux&S#}-O_{7q@tmSc+TWH3u6${0{qz`@B1 z>zz?_e*LfO1Ale7Oh?CN$tDV0T9G-AQnd!2DAaA5D*`xDLE7HHM(TLpHApvrDJbd0 z|C5U0H~3v6pWAM}Hz%@JM?^QbN_eHY2aIt5(mmj+PFS>Yj5j20SL zy8o0-yTHqdP?BO>OQ>xtfc-niepqW*ms&{fYw=_?*})3szQc`W8hPw-JR!L%Jx-1A zetByzhY(1<-MSWT(_dH{0WWdqSpTayx7avazl>VUOr7)e?!XIbD*Ya!bnnF`yY{s5 zEDIC)XD9)3SC%LV*1wNddczg%r@~ahMI(2Xt-EN@c6JJO^Xn%3uTb;Kgjm|q;I5h& zfamz<4nBM|F(jyodv>S%nHRh%V1ELoI}sn=Ef(Y;F!)4!gg5I{ez!vbj!!v~qNEL2 zta00{Cx0Osf!5vEG7iJnY=YKLx?8kAz-1a8G2%A^rI~A13567&L=-G2>Zv#Uxx0x~ z?^zRuGNyhokrF_>7Ltwn{f79#&NMhUfSi5{4B?M z%Tde555l2!D<&*rKcSN8gy}@mFI8>Xh#oday7zKZ&T|N?gyW$3QX*a+#5-#GEylQc zUfC8tQV@fH+#URns)2&N)BuEu&du873tQKw{zs+n{2DwWoJZGED>|R@A5{=@6d60X z9k*LkwK?6nnk3;5$f^7}%)9a_l$)kqLB=UQ4NGKqe#{Aj3|GD){h-8~-a|hUu?~(E#@^g)SZe zU)Cw=gE+;v&-rex4pNQ|r9*#+yMU8#A3FLo>{}fDM`Z-dA#2$^7(SR3?AElmxO0#9 zD`NZ36JA9>pg2hw7Ek8YTBjM&LLfeO2b}a;k4;-QN^pOF5{tQ4xU6w|l^gAY^d%a) z@|t{;*ZJGN)q)mXM79t?(S#Yv;$+AkTNE{jFiRKEF33_YAmu7Nc6Td7y<%Hwt-eHn+$McrK2`9auykDXT_)BL3MFHi-S%LR3Xr$u($>smLIb!AHRnpyPNLfmL;$qul{4>xyNY2I+Mr)Or~ z*iZ``s@U`ViWaZ$*_Ih*R;affz|mJwk8;l8D|~{^;1fO9Dy#|7=hj1ljfssscbXR? z9LJPM6%v}uTC?DUF7FZaBNR3R9hJ^W+7*SiR7 z$Da1sf{rs(MhAhoHEf-;Y&_-Gf@ueY8?s27I=xzB&5>-(Cz)*Ev9r@{3E^M#&;n&_E z21mHKlCo-E(`c4Bb0k@`O#L~kLwp%#EJ=q7`jz5!HiBW0h3x?qsn`sl?2GzVidGxD z(QF=f9mf|d82u4CY#VuxhrpM-K)-wTzXPqEmzKyyB|W(SS^XTor%PI}W?%QYjgZNcz1yRaJ`sT= zJJ0Q(Z|q@To3x~OK{w;9oTvJ~56>wF096>4GjL}R7uENkX$e<;@-2_&ds2c`$IsjH zYY0r_ZV;#()FIHA%2pIv`^;tMYWqic;iC-8PbQ=&yI-w!UCBu?i2taPW}A4fTvis^ z#PLSV3(I->OlHAcUK)`oOk28 z^0#nr5+yc;o{A*0H72Yiq3>)(D0ws$@Lg7xG)=*c&TK~H3dDjt8zdDL6FXf#kG|zJ za1njVK91aZ9dPW69R`<8udQSe6CoT#y(D+W<9)*AKK$NF^}}cVzD|r@yHB<;6^r&n z>_kbtkJn#5Bfhl>bM1!(07*@s2dMGa$uBYuVM%U|ur}SA6^{kAdd#w6WpXDJnsMxqaOnwSxGt)^4{N^LNMF^>=63d5CC|dkz&E?UF83WM`YIa;bz4!`sYCVjx=@dy|MjMjl7wl%}A;7sW#M? zv#|2}Js4AhHidqcRq);MU^>&{Q> zezky7ki9$D1--S#no)~FqgIAmq{NU2V0w;;{`DLd>d`yil>D2{*tlJn>8ed*e=+E~ z+6%_FVHLMUuO9T=9PsdZj=Q_8I~j4xVs3sSXr8atP#t0R#6onEuH8m}1iM+}diKj6 zbD$byY1$&&gHgEqj*fk7-DBG40Okfwf%i0<2xjpU+;YvXO9p>yni$~u`MoWLV{ZTL z{wzkpG+k}S(s?DSuy;+6_j<3E|ZIK>9oYk$8Q-^eBH6?%_kJNdFp(03N4HF=z4olXLAZO{QPrT(-pDwv9BRi0Up(LkeS};Gojg0suVk@&uQO(&+Ws=c z*JHMz>A3Oni_wg;$@uW52DU&^osYz93O@+W#bq*3hWxR-jinPvd-8y@SYhfBBtL0W zFl^L+;2Ox!G=Fr9^B!z1wPysL7NSeh#ZxsWQc5_THxU`i(A9};r&H)ElWlL_5DrthoP~aFEopueBeLX zP?BK>CPckF$YQTFm$)A94;Jj3GQ5Kg|5G|C=kqYX_9j-` zTH^7Ki)=uvHzxc_!r}mfPH5A6J1cRch$*ik4ZG1$8+Rjxb$}pdS??P1Q@V`kDS*PM zrC5dm)>g$wL|B~GHt^|v`li6X39FUR$YM0*866LtBYy6{^~)A&74{&$%TATV0a%JY z)%!@l(SaIX30V_RD^&2{*+|O*{C9o5ZTI&z?OWS{r2w5e3;4SXoRkE`-;=(EaOXE( zasg&&E(-l3YfMOtn!}f!GKkjxwP`~+vSMGU(-nE% zB#3csA9|~pfF=fh+1ntQ^u3bC#UA}frR9H1;rl_1!M|~$F!V0ku-b;OBR`ksRS#HV z9g6P$zQ2|XB<|(B%lL_Gs!9=;mFXS1AAMGlIPlJdUSMf}oy_C$;*mlo@7br=fZ^P1 zV~$<*R!yNxj3olCJ7%=?GTOrS^Zq%&4Wa$?le0}PVa#%?;|;~}vEWgn;eht$vxCA& zKSKi@wgrz?9;NZ-TPE>Ju7idcg{&T=K^EbaItWh_4n7S}9`)THu9DI5q5d#umL{wK zvU%Zq7O|pG^64CR=R-3u{&@YC6EoJ4H9*qB+4nAi*yA z<}9%6DR#w3+G_*`U=TH5c(477j5kOuFP%=Btw;5V5-g-^^8TZe%N4ls39;ebb*&5< z&|ojCSxZq@i#I!)CM>ok9GDn7++s+el0@X z$&OuYSJ>05kG8)hzQ1PfY;p2dp{n~af&!=7q&Qd^a^kr)PE28xbV>63uPvaTU^g~7 zb1dS`0vCOArJv<^#qX~R@1#EZ#Xy36 zL?4;?*rix-W}l8L@DXfgT1GBeIlENquK9_yxAH}32z3u{bO^A!=El#$GRp=XS%W7~&6|lgMBUm}Z~)T9TN5ST0bRdmZkCMwLKj*$Z!7g$kaCD<`8F81((mYbxvnoYQaD)#$5HYynmHgDa^dsYY}-Cc{37$~-;+H9 zjqZCveHua?G@%c@a#IjHJC;C0x@P;)jCEy!%T+X`B4~$N1U!y#Y~&u4kru6A*5?$S zhudpU9=ce48c|ruJm}=V?tN2qefJU9816^CtgQHpPUnC{g^$hJ%MAZfRs5K8bQf~v z41>Mt+_@W@qs1%BxHqW$*U-R;G5Sk}V$9mqJFRM4{wfnTn_G(cyXdP7Z)Yp@?xwDl zI4|%Q5r-WET-6FR>>uaN=ATyBi-WvIN1^TWx&l`0$;xztzbkMCaaKG=saoJp*RNh* zag{g#@8^(gnT^_^nvNL=_h7kyxRI-dzihTRcNo!TrtM15Y(l?Cz0R)2 zo8?ECZiymL2(+fLiZaCzWKG^Z*%@tg^5B$#tY`_*T<@nbYtCNhDBaN2=i6I6uo8o~ zCSrmFhaPOxJJ+~?SGsOU$xEqhDELg><36t|u(1~y+V4n+U2LmiR?L>0-K8O*;L=V` z*-k^hyYr;`6hP4~mMi;zkB^{C!4dD=Ze0U$(eiZvqFwp2e5Dp2z1j}a?l4Q`HlMZ3 zv3jc?J&<8~FX^d?uj*VTc_^|zF?qjc6_wBWVp?9}Ekr78!8$ZLRbh~N>$AhBosa$D zdTMh`$dbVcf=Hd`JQJmyuj3B*f>WYSf~C011!lM%>{lR3mMIZ_$!&QF^d(0k3Aq#3 ze`xeCb4%)HKTHI>wAoc1HK2z0oA;u8zN!S)WCGkNL7FQu9kM|L67c7qJ^#^4oTP9@ z@ZtKf+)4|s$(i#!Sk z)!%2_qD-ZAQ&a!m6!SEBYNgIAooHr-5A(1Wn)QUfYag5q0r%>kMd2W-8UDUi(g-os zO3qnK^ky`N;N?b5`UwWm{&!@#QoDv$oSlS0BU@vch~J(3a_lFTv2k*foIn27;vt6c zIH~&L{twKVqcM7qalbrCt?#*?uvaR;O(cK)aIMSef%aR*LO- z%U6Avl@#HbY#n2#sUPnzx(h`dXgR{*TvTSQ>$!Z5iy<$az{gwUpflV{s^Rm2kl32I z!yI=FyREd6-1mRg{c@_|qB8nEi2`5&?>5k#{uMv6I*JBWi*(aF13xtuf?F8IgIfIA z&4??(p~P9cndz;?`{355N&tP!TS-m4@jMvWs(O#TvQiE4429o{-oDjlBkBB`Lx_z$@zxFQvDB0G^TsRsV(5lay7srZGzx5EYdM4k&fS-8W zJJiC|>9{7?6gRfxfP#1(S9CRJp#VcebYqhPb(A1>{>vgYt0N6itlU7ulJ`U<3>#-F zX}j$>oTaYfRJdjPyf*7V04`p2t^~;dBTw@3DLDJSpY-(#b+Fm%|OAmNjfP_*SM)*oT%udEmul5>LL!Vou#qT%ReFq!Wmq!-s;Le}(Bz zR-N*mDjG4j?TNdv5?1^^J1MDgU7I?p2|LyyF{S;Ecx-vF@6vg6iJaukc%(7KV!6tq zwlNJJ=wx2wy?p>^h0s3%i)t!x_@;`UlhheOso53lzlpm%V3M64(@nrM1N8hVaGn*HSHa^10TgV4DcQq7%{m=x*?AGTTAu=yboOB z*6f$pG#Rw*O6t&5wi{dH*2je$WF%P`@6SszXw)B!3~_|iZ%rU5DYxpNQ_&fdwOnj+ zhx}qCW}p+jS+is2)dt}1RlH&rG48D|~K(u^#=rwsM#Wam2#PwF)m*y zo}i8Zg5XWW(H0?{zjN}S*=~Q*23fE{p}?I&rQ$kaI!Q3zPv;zzyZr?wVWW$9mD(57 zz1H-LDr^9AZP#e2W~!4h?A}pLyg<;Y1cPC=7w4gzV8AMvU7O%XDdR(l0TF$aY^AqH zMwT=0dO^2o`s*N8JPHoN(Z+3ryhi%s1e{^u7wqM`zhOf#$ z5@-jo*wY;XJ>TCuTCtsg9>637-|5@P5jBX>CMgfMsJcJGKTfBUJXWx!M*|kgXLfl1 zP^i6JPL#WYSaf<*qnCru)hEh-SyMw!+5eBC^YEwo|D(84DMFDXs}N3%$HriJfQh-EFQ{>r?) zBqNq`ugckaH!F4^jb!WNa&s;K7~^=V`$c^F@0=+bt671G3dk`T9OiI6iI;gs6?=>o zYK^_8w)d`tlu2d?Y+k~B_INrusU)-v#Ad)?fL!u?sV!K%Gfwe=n?*Qvn{h(){Wa+A zi_r{3x0W*khLmn+-1KUU0sEyS@+Iof{3yNzlZxwUJs~<*&nPkP%l4{B&+M{m{e@^2 ztGgD=xd_@_OeR=+`F*>I@5OpVY>w-qnRSs9ARxEU+97dy4)HU?7%9mzZ}no~16O7& zXfMlH7L_=*V_;LS0wqn6L8K(2R~s-7|N2>(_%ZK1Z-hwqH3Lm}-ka8D`k<6kYB-=B z5RE+la9$y8m|`ExKFHqe=WlyoboG&z_y%VL{YMq#d3{_$)*kxM*n zj$6mFAcwfGrnScJ;sESb-}w!D8UL-3HY*}+`CLq!Th?KZ(1gkrVDUVMnz?4zpef3s zvMJ-+OLhAX=b7=EJ}|#mzu;5ivOxc^c0{udm#t+t+>BT}{RCK~&i5#Bm_E#KST=ME#(3g#t?hfktiHi1 zENZ;{zV!tyj_|$cgX}jejl)LJU;N*EAkp{TL{+ygz;U?>CiQZsqPlWk^FxnYWEmgW zW=Sa|^?G3813@D8lSjNuvChK;bs%=|6LjD_yCr)Ilia>&$S^*5ATtHtuoi;-5r=u? z-hxgpFiwfIsJc3wphY?`=Vc3^hegKEe%JV7NBKNMu7;ROo=SO=Q%N6<CUj^F??-=-0co?TP-R!~hP{`DfCL@4jB&!1JU^vkW~O(JibCM-vD zdT=?t%KN~A3`d|NzC5pcDgx`MXT3$DHgv8RW__zN+c%JO-RAd~9*q(7sSh!O&{Mn! zLZer@rZ3!UoD_)L;o5|Yoxwx3xj&usoh-+DUtn%=u_~9&%j>`nQgs6h&Bk4x&$rB%)>6Y2!A`+@_+tXo=n7~D(5KoAIOT?{GIb3Vw)^qvru4ptTDkVLyNWoela(l< z6C2@JJcf3>%}l0)r^>!p@HxeG7`YddK(Zz(>(Xq;?r-IAPn&BwRkEQqY}oACjcX{K zIW#UrMhqKo648kyd*4Fn<^7k3L0`bBYY#8Y?7ja0JNHu=Ry9c*#{D?9W`X^Yx?qRc zo@Xpzboa425oMU!kh~jsla67*-qtV7i7&bL9D$zs!~caE&BVAe#%fJN1Y+@_xrZ)2%#<)|3TROnsk3MhaAOQ$iCh0H9~EPK}acV#aantTvP zVGhuaySPu+GvlRH35O0~pkU$B2Ob`$r{55u+p>b*UldE!1PjbSI>{}ACTQK3#i#0P z=W8I+@ymifhY8#Bjr5BXESx?C(};p02WEzQhAobdnBKs}FCKxH3LOqkKGau8KgM=K z+PhPJrR}=o{9ucQW>If35zkLj_w-MpwzB&OvUD^~jP3x*lYrtyQoml74i2zAU&rcV z4+z@m1#2=+BKW=x)Z#|K^zC*x!n%!I^MLg#%b))YgY`U#5mbnHjH z=2U+n71!+SE1bX+&RHNwZeKWc9++FCO!nUc7;a^D)Jm=SPWik0=6fM%3p^UOD57nh z{$uw-Y^n4T`BizRANz~{s94GEW^R$T7P){AG@}u;gTFX7_>@F4_mg{Ke;SD|@*ci8 zA?VkyS=4%9^e;=swVrQ<*4Ww80V4K~MM=Uf9z`6Ld#w!ygYSig@?`W`eMCfOQr87s z{-X*YmD)YZ6a+S6Z0&nRd5ToE9km!GSP=Vp8EN~1_9^)Wz`#_6fRf%$D3w4o3v)p_ z&JKxkW*%RlV?n)CE0yzvB239G3H#mHoJAVPoAXKG(vW8T^YiD5L~Z%D}c zjQQfm#Z>ByILT&<`^GG8sNVRnpDC#Ccg!|2_W3AvDQCn}vewh4KFq2ra0AlNZ*H>0 zw3w?LWam>dG6J`%nzdaFswNBV&bZ^+_(%fe=Mehy+7{InZfX*jNRUS*HD&>o?Cvh5 zd2gO}S2#$R;TesGD{>sRmGB~XoC(5+E9!K6TU)mtm z&^*KM<8$4N(UAn5Df>9`!2N8=lms8();1qh7}UPbs&{_)l3Isp{o(#agzHiW14gGh z98mnqC0@};wRvnn{Yj2f!C+j%@+a_Ys0$3nw2Kkmv8AqWkOJHhk5qG_-N#~0^tV_w zS^d{AB;$w6jGr!83Cz-|X3Alc0~c=EB27|iA>XexowA-lgajw)fh)5P8r}t!n=M&6v?~>|2Iq-T?oL`IDD(cZMkK5Erp&-L zX=nK3rLNfCa0F6N-1>OWfB;O%$<+77)4DncY2$ zSx6{*R&cP_;u8%!{4#7VbqU`kuS@S-Dnm^D_>yb$n#%fkf#60wE6W!5-KRp?T0JvN z7K+Kn=#sG=ds=aMt9E_Yoa*!ss04clNAOo=)i_lle6pb-WewE0?qG@QE*`UYMx}2?9eKnAEBoX0?<1R`Me zy0^u?P@ETW*GQP|auIW*8N}y#XW|#CQ`Jj;e7=he8}SmWDv!^9RJ1#q%Mds>x?vGe zo^&z8w$UOSo0w>Ujb_q-9Kn=~7)7+*?Zy=8r2}%_P zpy|>5xYCV-N?56taU*IvNM8f6tgQ(AZe~PxE`z>a@NVXa?pH?SW1Rh~1H+E#%@o-l z(t6w3c}vPfUwt<-J2MPJMf76C(7ME=hNdy}0+@m1cP*j7LX{0yqRzdL9mU};(o#v) zht}vv@H9<|BH;$HyRK1bQxSbbmUh1vv$DL%9qEBzZh(cV0+)) zexf$5at>5TN)*;HNFe&S2T_dKT6ptpw<%UA%tlg%<-I=u!I4SGZXsBE!#a5=(hW`? z?Mw7y=#|}pZIAfo_ZwHJ?!;o{IgI-OJ-ixwurBE(L?^xn*A~c$#Y63B6%tkc4N@BA z1*Y4GW0dY%dn4B$^XBWF`PBI7wgBm<82^N0Q!Bri!U(-WBh4V0IO!yy>w-xsX)pdq z#o+EByhD5(+jVrBPhDvAA65ACefEVXah)H{Ukx@USF9xPS?_v%ra~CSvbzRlr!Qmc zE;iX+9sdOzX2L-=Lv-%5gGi`;Irc2_Fl43GaW0htq(od?`HyPoK>q*9@5W4$aWwx9 zWN`<1$QWDOndJ8{9oKG%t6}b<8Q0RB9P!4h4`AP;@KavIL30!L#O0-oWi{1M{a4QS-rHMzW-*Yt z&gnmcNVMMeYFzS?agVM@nT#>3aYbTOz%30K&Mla5%l3o*1@Q`TPAWU9_a8HexzrRh zKvt!D*%?Su{d$J%$#wS?s7)D{ZY0aa%HDhU?0uu$KXok2Qrl|`x1gg@kcw{NOS*nk z_9w1u%E6NuNIOn;@ZhVx(~vvAPdumGz2niRXQBdh_shn~XY&+Sy6Eg1J}<`?tQ-*( zU((x_Otqy(qg3}-?>#seVgTy$jRSwxeh4^b1=eq@!qb#fy%$S$ltqr zV>{#Vhn3e#)nv*L!LZN@a(Hy0aRQnXTVeQ&63|ZKK+aZz+!i z8)*wx6Gq#Mn}N2e+WM1p+N4>ax|%9IGEXaTmo+pg;en0(-V8EGc8Apov?ST`j%bUN>s9dq@P z;g`kp4ZDM6f^05&|D$4bXh0>m@Gj-nYhaB0YPF0H=~gMf{5LqfU_0fIPRM4;{RqLYepn8ovs5ns@)c^S&{TH&N0! zpk7xctpX7aqos)KPamvX(mWqO(iBV1a~v004x4Sf(u@2-DLCd%_Pt#O0J9HwESn3h z#Sj8F+n*F`JIok0>Sp`1p#Oen75F464&#_SXbXQ@>t=6qU;yXO%@o9HTv+sg6SXn^ zSs2vMH=&`&rL065r@BVL zfnDy}gSG2JZpBmyo1`fpmEs>eb!rTaOOpiI@XCtHwkhdHkZ`S#)LScicMb|iUfR-6 z&TKe-`9P{A(@>tz{QL_M@>_=8+)7ogSk~mL1GG=>@4UT1?`OZPlJ-Xo|?iI=R5T;Lcem2?gtQI1UJyW zL4|Gi@KV%Z+zmi6prwKm%uF+~t9uq|IkJ=f@zV`1bFO6K)JE75o?9bK#1@H6U$Y!` z^yP&;0jOe@pd#+M<`2Hmx;9b4vEms@=IPG>Bt-_3UajSNts z2EM+Ci*6_%sc>1BaXW|l?{14~iOFj>F}yFPbUoqippMK7lHSjh`R-bB_q|1<+%B;% zP+k~`Uo>g4b`h(O>&7(&j4x+s%dE2%H}e+H|4_0IfXfm*Rvfwgo<_^weOnhlujI9{ zo+6zz*w@1XlwghUkM2z`i(4X3XsgcGG_PbnMwpJQpCz+P)P#O*8o-$x)s0`!TGF52n$-wfK^SS$dbK?z_?|W zF5?^}g8izN9~5=lB@TR@$C+oIQXcp4eA6N~`Pm9$B4M+d1O>~8)pp9B75dtO*ZP7^ z)nszL12tok{D!jPr8nR@ zOK{|0({y%^*&-%)k(uik*kB4)koodvS&pwuqAb?o9o<@lUT18!wi3KfN)fVozG(nB zc~Zlz)SzJUR>eTq!F;iwXZ=}W*&j!+Yg#rgGN&@{06tO*@5xb=o{6u!XRuD5_ zxaR6PP@c~r9TJ2|>OUgoP2+Ek!bW zjg4~mFiB&Rr8E!zqvBsa!!oftgqhn4RyA6`tCJlP9N$5jXcuHgI|WF;Ask#pQXDy* zQv&{&F6_F;G~2x<{6__62<%kPnP)zmN@)Yjrw$IN6}zefp7SaW`kw%oDDkmb@)MKN z63dsIll-recjf(zWAJmCifU|f0xIohA>A!0Uh`U#@N!{8l=?ape{K1>Zl?TpMi^xe zuPblt8}n5a+47|BasMgb?|$WH6eqG?#+`t$4+$LZ$$Y`4sX zjp%vi9QK*%G7D!SiZwFvJV!PI_QZ54I3T(&X!h^tE79$Uca~F9Wy5e&z6!gbgueaF zr$Vh@|6?T>v7E$S8c6NhV-qIhw5Ge0K*hnZ|-Z-_=YjrUu>aY35aW{0dC;9dYc3?gH;#+ zddDB>X|nTO@O)fuff~E(x@J~QwJ5l`h}~b-z&`UkxEL>I76}tN1Pe6w!*30VtdKct zErb;Dsdl+erv-edL5b1yFY_B{xFu+>!XsnZ+;PQKFf(8<(YsJb_Whwz_tA_Qhpb}D z2BT1FGIVTQDDfLh{Hi$T*|b|8eNB0;OW4T}rf_b9-7!8lSr5+n`Gw*}g)R|R+qt0; zInG-PJy)B5Aa}Y9g5l&(GxEaE>>K>+Vu~~ZME|jg@}l#9sy}QQI^I4mGU-TZs%T+n zhq&UuM&N>Y*7zy`pR3qIxUEw^rA%$I($vn?HSGLI74@pydgIYE35`qip*b)H zL6&$6lhg4*=GtZ{>8ciQv9#BsGZAs(48?>}k=;iP zepzC@Hr-Z9mJL73HM!QJ=}uHj?3E7Yfz@CYPa_MO9oXa!B|SB^WTu2TKjcqlJV9^G z480K&9(5Gh;}(9lrZleHG?~HVTpa~xy;Zp5yyj+-9JW5eyV{Su@Olszt4ljiYwAb6 zAv`8rzsH@1d0@-1Aal8o5|p;Nhc2E%UO&p*tX#I1bPZ3=bG8**%WY5z{B~LuqI+E8 za8Pu<7!I6To)wK@liq6IlO}hWJkAJvhRh0|gT&2n7FAk?;rF7Oi;crA)UvKT36s35 zOd`U4UJ~I3Wc}CEyOB{F9sGtHKDPz47aXxfc9*d3=Al~k;{L;)Wsx!M>ePUtInBU% zYTrLaSZ6|)JLObloSb|*g|`EX<2exh>+c=68doCu?({FUG&D_^Env~MGWM29H-tOUjG4vWW#5XU$<%24`P5UK3R?E+@Da>>394j{jQBSPLgvQFiEa(i(a*u*cth?arH1S zV~u9`&Zs-T<%vX~J$r!dmP>Y)C)#ZO-csbqO0b1&I`>>b`uBq$sc-8BdoMLAxouV@MvRMQivYo8X6JrghOZcy{XBMIYfm>wW%N*b zo%Jm>=U|v%@1u`guG@4`_Tj_PRRir#eumB~htz`f>)L~T4}kfs+>8#KN3#V^ zqUHk)hhGz~=LO7ChwJ&EsFnh^%|Wacw!qNCy$x1pj!Mc`Rnj_~?Uz})|H?|hA}9?_ zn{{)y*X4kF4ht;n!`h@Tu)w0_6^3(~47f1R;F{n5uM;~%*Kg=tJ`#o}3mV%8I}eAir2F-gJHY~jjjMIJlj+^YU_$*Vn3 z!pbj%>iKu5r0e~j($c_pT};9=3KqBWKy#}Td!kf>x_qS<>rAft)>}i_)#R?bj$b!mhK9dTTM&#CB9em#ZJ88BaCK8?XyBB!8H+T<<T3P*`at;fw1t0B5l z7TWiFSaRfT4vj~?ilvznzpNLj;APGnP%)+~MPW6#!~ODG?{8CH=Jr(74N8XO?`+j5 zrk=9lvy-n)4Tw|uu5fUtl&ZU>R9AHJD!|1C1%H53*TLzq)YqiGorII%Eq&zm!L?5A zH2Al4p3FgVzK=cMF5`ztlt)!&Ki4a}pgSSh{o1=5=Ro!dn`nMZQ*Wv#&e?Kn^uC2~ z^hTxnPy>sfiRprae1>blJo!PAkBl5Q??=BvrUE9D%x|mdR@Mt1vlEs0-rZ8+?9j4= z4mg-+2p)7_PSr8mLdb1{x8V=PWfv*!e=@_=>0PS^M;bfV23@|n`sE-8;2x+rXPmKv zCGIEj3E7+)it{y3GeHWfPO$>_X8^Ss14JBwIP0p8PKtGp%#pIc$IP;mT zCn+ZTxE$U+HDD-XP=+<@3#R7>{e6_s=3a(*WYmvt5cH;5(&tOm4%|k$@NyqB(U^X9 z{&IkN@a62}=k)+Jl$v51q{~P!arB;pd#j4?Ns&U=K;-SBxNo_xHxk;v#Wsg>ZYk@t zWax^rfBV4`=J(xd?(pQ>pVN?rg3Om-QEa|-Qf~SrB2CwQd!Du=N#vWK)^?OT*II>{ zX|A(+3G+&l-~RSxZO^EpOL(GGCxUdZQ}4Q!SCj@0v=k-c^)5WiL5j`SYr9~cJ2Ra5ot!UfsZQa+2ykLLtfebq7 zU3Y&aa@%e}vIcabrb`pK(!QA6_5d8(j^yqd4P&Jf8}yv`4R>MTm%)mExmi(HI;sz! zE`g4s+p_oLE@;_TDww-aAKjxfjz{{$rrHMG9|SO8zm#;zJbC*Z`*Xd9=%w!+Io&;x zglcX42fcn?tRev&0kKQ}pXJEL-g$PM8zqAbuXUx>k%g5A8xTSi3G{OUcz`B>?-%A2`1E=c)j271(Fvq5?9&yYl4?F(>(!R7&$gt*# zH`A`d?}S=lGBa;^WL84M-^HtHJM-0;o|X)aWVRX1Ns4oe(xM)meKbx{C%ZxTW3jyV z$NT;cwnAn-+#Nb%S`AqExUEz+E38Q#Vqdx2l9kLw>ao>)#!YU!wO6TC|I@g` z{i;Dr4!OVuBhe{Sp9KH9a+K+|ht>9bd0=qse761u!JZ0^EQ65u=M_pc%cBhQrvI$?s+!uH zO;fOU6~93`^vY69Z>z)JD;le@K#2kjis3%51A_*9`IEEv?m`*^%g>NqVbHNe>FDpC zc}p@YF5!DQ+uF$adS}i|2;qFnLEW+>SLO(+kV_IfWN zc~|#h&|Kvv!9Mrvad+FKueq}K(@(GBt$IWs8hNt^vpiU}jdMAF-rtkF(i*pM+M7{P zgs+HH;Uj@70(C}TH?&nBEKMaoMdbu80P5oTb-n+n#N4QHYu$RW{dO@quf8WIr*oMQ zcZEHv70xal%(P$3aw%jk%XR=lnk}2|Uu2^!dz0iZ>g!T?`74JMbJ!wJ8>AX3pZ0Q1 zHl;h;GFtQx4SU3!jY7w;?$=0B=W9~eOQzSNn#TTJ+y#<@z7D=_vTt(GI-Z5s*rRhF z-(b=s|Lw$>nopK`Fy|a&c1Gv7w}s7<~nNZ{+b8Gq(7c41k@06 z=ANDeMA!hLIn1y^Q(aW^MKI6q37cFuq@5YYq!O{<8G>aqZ&a>mjH#)t5IC`X6O7_o z^%^g3LXzJFIj9~?4OXsUN5thhpQMz>r?(9aVcP877qV``{g2>!9sDt}L0Y`~!$a;r zRyUB4WbM(q`04ClVaeF~N>=ZS!`-tlBSL>*i+QOjA5(XFD}oY*rOfln-v))a+3EoC{xQSSKY`kkk@sPgGyHTnqnx$2cTu{v;n-@Bar zQ$v7r8O8lho+3;MZDVE9^r3Ch!>1vJ?`>wq40RTdx5b^eR`LfafutTadyEU$L;~oR zCn%1DvCAKQtQD<36r>m02eI^_hxpOP(Hy>4eBoxfk;lq5)9mK0FD{nlCSN7!dhQI+ zJh+|ce|D3AZtE~OMJkB~xbptX4U30(lQj3iolUu&6<`yBY($IpWku)e7othp4K^>; z3|4#E10yUh?YI`7*DG0;1K1W|(fFvs`t+<$hW(h&l=|Yl-?njdIGPKDH9O5+YVYM{ zr94R7Vx$XuYZpJ=ZXe>unr}*bF>NJw1RFnCC5d) z*Q&2M=tQm-EZKg@3W7-VdLvg@xy<_4!%y3Gv6x0H&u4fuE_Q-L?P7CLuIdz0n`P}o z>y8*-y|Wyj$L#M#$H;{OkH)uOUHEoKi$TtN5$)_sru-G9Sdx}m?fydUEvKJRHqK`d z!BBJBavh0&xh-sjM!|mEHx*@QPaC7cwM@UV`F|=NnO;}RzVk(wM|dpGe^P%Cfc=A@ zs|7g8AE)=6#lBOXdnek@{v?IiK z8hQ5r-cE8BYHTL-x*79y)*%&mzr~FHf;ll>o~Ll0XG7SQ%*lIVT}J-imR7TX*WI3J z?KgPow*WA9udvc4KOkM}UEb&&q!%P=P1ZLeQ%p@wm3ppAE+TljB9LBC2~q+gaQ$HU z#H78ct+5fd(AxbcQBx-LlbYti`PGkrSb0hdI-PO`fFxodwMV%tw&2z?ir{b@g$Y>SF zvtR1jC#`FwN4vFtns2eiQO&eE3CT|wMvPKd+q?gnQhz2fNjq1Y0c7C`_zxZ|Gs4Cv_W>=We5lDC4*D)FaT+<2+|9_wh>Ws2s~cCdfO z^2NxjP$sZ|Z!-fflZFEzK|!scBe42I;1?@ER4W77mu18K2F?4xYYuPHU@KjCH4brBXoi z&$ts6Px4aLy)5DpP`ES!9BxOlDCH^PrVMLhNXm6nB0BY8_75HXhQ~AEG^)_-`2fVU zBI5F<@r2rp|J@T4_koEXZV$!i6Rx@x=%tDLSUYn?SZ!aSjQf0xry!T}Bl}0yev+g^ zW!(V`h$P7WYh{lb8z}VWf||fNb==*EY-kEm(af27K)=O1f9)f;lu+EqGvkXJa588M zSj9q^Qc=Vj%of+fTzqQe7ARoknZV{Kg|@9BZV4LpsLSIlq*>Y(wHs#PsFF>dE=u}| zaaOcNe%aZ_oKIROds(EF2h7v>5&m)--!I1rCZ8rdW8ReGD2766va)2*$rO8vJRqp^FL4jwlT^9}Nb9Vd zUsvr~0IIfgL`sr#mrjndQFyMs(qnpjJMWKTU6Tm!8 z#^Lp@Bubd3u49`rdELQ#u%J?<;dyO0X1q*a4W5{0p68}SdRKM6eTEOwg*jkQ>!&Hno`a(UlNJArPktnb zrJ0}xEou}(J&Ut3&Vv+dY(XL@bIpBH$ip4^K)rVe6z1|&k3Ha|bcdYD-L1vLVsQ>! z;H2cT%=vOX)V=`Mo(tsi?g=AayH*1m_@85!@P{JGKKx_N0q>-cwGj_G9+jzHypOFr^{>|*mE$_(ZkNjv$b^`DRk-nM#}b=v5&pR z?arg$?la=E$?pS=RY|5iq`c*he?nMObP6h5A~eM(?7^*Gc}(obsmb4ewUX7>ZSiHw z9wA9&GuWT^N@8R|%B%W){B%_Lc9b7ggYywS2C4h9e=p8uQJR}1m$`%@{_q-J1nz@6 z-I}Zx2e*{}rU2LRaRIJY_p`9OZQ`D0Ra+wx6)TVv_;%Xnd-Nia+{O5svPLRg3IP#! z&fBEhBdl&Ct5Ex+;cGF-ZH$n#VdfxgA#p%K)ab!=ZkeS~uuQb)p}QP@a>u8<99jh7 zCRN)KFiRfams=&L4?0FIP^@oX236a|=vIz*ZjL@}AsP0bxKu_IqXS_tYbSh3Mhl(V zpB01s3~6~|sPyE1N=2&Ep;`C z`r@<i#rgIWu<_L)|_210!@+*$U;gg!DMbM=&8&243jW2#4VNk7@H zVgNEjxWA~q64h@zU)@4B_HhHJ#=-=Dw|!qhCBDFL)}q$uHs}2+b9-al7I-q)Z-}hF z@*XMmjH}lvR?6ZA4>Yc)iwau~cKs{U-7V4{p7qqN2yy3p5SLvMQ89#ja{7O{e^W*f zd#6;>z~NKMQ0z|J`pcM4_JN8TZXWAxjIobD#7PbdW7@+qIdbiLSx!z{`4`Rcir(=4D+laFfh>P0Qs`S;WG8alD_%c>Y^Y8H!NQ`Lb>u|oN z7H_F_#U@nht=X;1l;MM<(3x$?v%g_ihal5}(O5@zlT&rKgO}APHSS#mT{BJ~>z$l4 z$RFOSawv57P|?ou7~ybU-fq__wqz6ov;ZuDQs$FL1U)H~0+(*pI}s8PVAx`L#z|w{ zJX*T72V2a53Ieg(6U$=XawIZv>J1Yj+T9hOEglWl!5)e(OFrYW#!`{%5 z`>o1NcDe&fX7w)iQ)M^TyX=3`8Z);m*==Np4y*k?ZK!43(0=x9-pi_I@K)68DRCqlW({gP%ir*Z4j zxnjfke>BgHJ|w5t0Nc*61Khl+a_!`$vzfUX*dJLa6XhXLEd+PA-%@!Pn1SoH;;&(~ zwi#ck*P@qhGkWMH2{=uHb9~uh#!(?=Izx~@A)Xh|V!2x`lDs{h9jH4ve%$dCfJ4gub`Qz`2?uk=?p| zbgfrA7OfQszWdN~@E~uUTU_j?lI;N^eHgUBwzqb)vGeZrn%K_7(~c$(8b})6+uaQT zs(j6>t1xjjEU=}#T;D@nf*V=hT}OlJH0k()>xHCY0&lV;iI=M?cBapccX^UVj4${; z2ynI%tYGg@bA~Xxrty$khgl+iWZixizd5RdJSe8zVOCAm9y^+IK)QbO5G@P{_^MHU z``Yi3FAoDi7mC)#&KI^C)i252Xs9YU{nP5cDi;HM_mQ~TTCdI%cZXQQ z;hn!i{b44Fx&lM;=vy?u@9hRp2=8=vCG-mmZwg(7sYv!qc$BtY@1fcXLimqC6(MqU z`x%=+yJ}AFY7qFjplrbw`$jzBl`bE37VL#KH0oQ0pbH^pw7<$X-w^r4WIrmn+unWq zj?iIKP}%-zsHVj=t2z47m+wvwhVKM{<@pAl7;3UqPZ=QOkDngV;OFv4T1&BUOCdt9 z$K9l}ZH>O^mTVH4?gZlXg}c&yKHZGC5^!+tx*;N?Sy}YqzDP~T^ywSnE}{_!b?njp zF{g=OoYv8f5ijG8tAeaf??ijmn?%d)8Kw@Lv!BUgNG(IOcOTOmj;kCA=dN2(F;(+Y zs2>fd^@r>-3JigW6xe&t+Q1~U#*C-IekcR;@UPlU>hTYv6)1zD4M{yPW@`gsT#!wy zc}m=4IO`tUrIB&x9Dxj`r=N2Px_pL~O1Nl#|^f*1I7{ev+tDoDk$8irbj<+tfJ zQ40Q}${M$H@*X`g^@kz3(X6pwynRUHt+62rY$&rIG7|F^mYR38@Bc?N`qKUP11hb{ zElJjr5Er0GK?Sldjdn-uw@1{q`t)Xmr^-hXd@)bc-B+KnRk-y?TvS{EpD;-L4)D#VW6uFO|u1{XQDsU-#BrjDk?8&miYf zW|cU%jQS|}OTKuOq*CE`+Kt|psE0OGoliD+OYg0h;$VNYS{VPMqDyGGRO)o`*wRe# z@cj(2#{4|l9uoB2CK;7B0<=yOJS_{`7dHTK!*jBuI)PhjI2Qdgw69bay1a|I-T{KiSvnyKAmFVd_ihVe``d|8$@-od8YRQ;y)cIK6hJ$a5V z+tD+Y3KFG?uhvV2xXY~XwaJ-6N80I+_gGwIWSLEz2qC`~HQvbTU)F!zk#vBUR9MaV z;>GrxX0!#MHebCmCJp!l|EN5Yjquy7Q_oTrDMNQZ8gAp8g?)@>wUrrTi&d`e4odAs zd^ZF2#E~AUlvd6Q%o=ISh=}q<>A4o860u8c2iL(*-?T`7-Q|`T|AYnBRbkBzJO2 zj=PKAE845Y;0o*xEPFJjDB1a# zJV^9eQcr+Q12>@VrAO}VgzO*b=9yTuR(@gUtC`KO$QYq5d-d;Es6AA7p;Jb4+gcFz zN6Gh?1RP9PuaQC*D-;f}b=d;=YE`fYqEzryC+3cZJzGLJ6uf-NJRy2=Kzhx$iA6`> z`u3Tn7X*J_RTOsw5v+ZQa^lEMry9}ym|Ve^!%E|0t~R({vuqa^AUFE1+cWe2SxT~@y4I01i-TOVt zhiV^wYkE5Du>%LUW;zV|<52mxk-hIoW7k}kwH~kEK6PVVH~nyUS0!4*@6RX@FZN`s z9L~$DC0S<yU}7iDDzAL3rvB7@ zz@08BIk1O87qMnIEzedl4XS^WP(M9av-I%oze=foimDbPTAJKFKeh)>PUe?5n6ID3 zA@+}kooq#VToN^dJmTYII5DOhQTF2{ZcR^ncNMlUl9o(c|?tXoz?7Oa2G z&L3{R!<)0+bx^Ihx7n)TPF+h~S$hHqtgTYCe86ih)ir{U!8QqL7gnWkivwK`jr>v- z)u769U-MFgs0XyyyTl6nwxB-Y1$~*fniOV28Qyd81Uh5J`1xtv4(4vE;k1ay<#}C^ z=8C3JwtzXM*N}de`X^L3A-%|t;I4K~fpEyxig}UVRIX%d3yXWdKL1CxllOSR$cz5B zVAqk7U9j(jW4rR+DQ)bng2j!u6d09bPGV(3jLnQ zvNx*OX%0}znh`J6@ygdMm;=UMbTBt{nv#1EtxzEolr-^+vjb^an9drpL0X-v>li&CYDsy&m4Zz zO;>wyq%?if0ql7@x$lauBfsxTSG;y;2sUBM`Lk*O=BN6s-)C=o63^9oEfAq_9tHvZ zbQyESxx{!BIY^zF#b$C2nD=ybdhE~VNqsk8XONgkh&*iP4)l3V(j^<3JE46n)C)Gx zlC!qZ(x1sYRWCB<9%|M;OdY{C*j;KQ_1#(d)G^}s_>VHn#IECcVRV>6V0ynaHp8lT z{^OCYCJrn)cprn0@+IJdI9VTcm8duf`0G#&%5uE3s}F{A%d=J9PI+pt3*=xsvd4OA zU1qKPNZ;aPDE&0{%vr?IK5kS0Ra-Kf0BNn12cIy=7ueN-2ZEjWs z$KWwZbr8antJOFfmILp3vXf#D5qT`&9N&2n!{5)zMz|AUQ+;ZHhsxScoR`%?;H#%I z5+ddO6p1JGOV=*lJJl3GAPV^ghMWAf<9Ep;d275ku&-n0_|Bon+>Xh1vH zt5XpRHg}(&w52asKQ1hF2FC354YJlQ2kTDLMmdsw4eYb!)r-5wqufFP@LO2rqXl19 zR(+38QanKc;*^cOvMO9Nn9~{kxm=>RX=_0?lMcYE;TuQYD24U0**;C_r8oFNUUhMK8SxyqSab2Xir zBlpToEoTnIjT^VQQ=BN80~K+gjQ4xKe}MxI9`5Jny07azf9D41 zO=Z${0pS$^U?ER^MYrPagcfntM0^qbl91)^`B~RnyB{K&yD+KVf$I5r^=nE2t|f!y zoml3guW5jb+LrafqRb|ukk9l@gMD50`bQ0#=ynT#bX60AytNCBerIT{))9~V=KYgO z21`-7AQ_XZNpR6Y4%HiIg|eyNgL~H2Hu8TR_a$bejMq=h33m007v3u0Jj}Z`5HjY* zXQqUdKF%G=$lf;R)9SI0JUr}nQ6M#D*ICv=cz?^2U_;{ zOFt-i5;ta(;H+AmlFK&=8*BRl>Y(iz>ob9bUA2Ub$le!!HqcvU3Q+}&0e`fo-ZO*2 zJbQ$rT!_J3oY^l+P9L8 zzs#IJ>UM}ck4VmK{yo_rb9>zLSxz&IKeb_DXkn68`#c#{9g$Jr^N{8iFr`{_#o9A2 z4do?OTpi{X zHU4(>SAAW;il@%!z9a7+e1ADF+BbUmDM|XkrV^xTP(uq34AZb)U5OXdw=gzKu_6<% z=z3koNsxB^os+$i0b9JCK)|s=p1r{DNc@bTCt2#?C2mm)9vC6a+be)nCYsmcHcU-Z zT?&GoTt}~lHr0ihhH1?mwQGI~a<$IT>)x$ZAB2uJ*$4&ZAOfV!SqMgQ-Q$h8&|c71om|2@OZVVzsfmx{B&uGT*v6CNDN=j%JCj`@G*@Z)KsH za{p}Vx;SRwer*g)_~yENw<(VeH1s)?h_O{%%LxT#kDLqso_J^BC$nIwTs91dSB_XU z@h9mQ^_GA`Yj$!Hg{Z0ot=|vr(5I$Phx2U>Uhr*o{fo|UZ|=u5>wiDFz}2I*gm^_Z zE#7`=UgXc`$Zg~``{uMf>@Iw@F`sM-$vrNqmdTy7ar zh_0D^RT0<2WxB$1kBkvoNnl#Zes!zJ$UVaS#}v3wJLCPy7o6&qP?mvlR7lqUD^6Fb zX1~HR#pxF}`oX;!2fr8WaSyZ?{W!MSA@=~ zsn|Zir9IRBeJ4<Qz?(t>DL$xgRZPde7#?B`@`w{H?)aal1bX7>q3fW_@ZXD z%e@xa8JwGGkebLUzw;53dgQu3HGi!oWTea-b@s=4dGH8LChxt+ z&h4f&-5Sh^Is7Q8cgRZwo^iwCt?r0*?2QAy?i;B{Az7@rV9{Fmp#II{4`0a}u$QYs-&uP>1yh5rI zWF0|G5+yv$Otco6X`UlQW!+(>BD~>uXM@hSosw*{J7MpFlsZk5#vh?-%#-^q zcZ!YOeF6me`kWwNmX5BoEYx*5UvuQ%*cE>Bc1As5SSlityYu%S zp{ke7c#CRYi6&JGWfhuQURi!y;BsO(s167Sl(?s2Pc7k(ZFQ=Kc;V>T?ICiHoxdR4 zN7=XkoHQPmjv;<77!NOgJozH~>-oBn&-7I3PBeacu+9b3ME$8K=OK{NvSFs3Xbh5w zKdVRNjaZdT72-MxD7JfA9(dcylzc;L_Hyzd`D(7t?829UIIu@Tt;Elx)P)X_d$q~6 zOy%P=e9qe*fo(ymNs?n?4qOm=;+3*$Uw&0rKE=`);6j%s~v zzN!2JfxbDJ@JykR*k4^5=y}VQX?BMHhJSum;40j*u6QtdbjO;5Wv~?m-u^#TLN!3c z&zCO+pdg*ZpIKLUCGzNpHva?9E~Tk0@7MyLI;ww1$TnAjV;^0d44lz{^yGmqP_1;2 zeyGo*(Pmx#%rE|=XBwH(EAs-~y>HkrhNJeuwZ;2i@@fYBBsIqGPNG_ zI-H3K;=LLd8QqO=KpYo!^DZeYt$Y&z42ssfM=dqJI{Vlp<;lds{cUQB77u#eWR_j=+!wEVaJ(^FP^#%V94cs=hrR7W#k7=sCu{ z5O1Kb`Uz{xMtQfuI^}1e6(IEnJyZgD`dQ%9&h(j&#n**G7j(8DUopI`?6b5W3Zx{! z{NTbtMp9XvQ1t@t#0AOm7&Lm4|K`a zJPA#`y{mS}ehy`HinP7TtA;(z7!6)Z(~&y8t`$Tnz>A=~@aIVOJ(&Q)m7XI) z2K6PX?XAlHI4gHWn=fi5`GB*#@=^#3{a35lLV%AY(#%l6!m9R_4Y&-+_cYyaM(W|* z*VRi6?1J9fhDP)XO?v~Lqk7b+U~8g>$nSL})+6gDUS17tciHc~5`Ftel+fObZy1>s zWU!)(Xiih|BbQwnA|#fNA(r2(CCdpVJu$28JYTMz1bfLLMr;cB+EEP-^dRo&Nzl!0x&QqZN5~e z^=4p-#|Crvx|*}XrIx0lHGS2R#$}}kN6cO)X|3*g#x?ApbJ%{B8wS)eR>+SLGcdeV zUa5Ks<;{iz`b*n(@+0#7ZRUEqrkc;o0jdn`rBjkL<*DB@zt`oM{)qHkEm?|Mkom?` zKHDa@_@yp{i?-=W#?zSkW6>YVWpqtL{a`p_1Z{cM3zmXb;^*MY95r#F2WiMTy^6N& z0jcI?0@9A^%C0SUv-OY zLmb#{6XVWzteuw?(2)LS&-5+1@LVBxMWYRf9oJL#3y0+kO!hR)G?YwFPUWcVdAMP; z$=!e3g%Ce~eA|(1rtka)%ifSi=q2K=0nFqro+~A_eclefi&1H7{S`Y)@01GxRbc6j zx+D0>^e}GCW21pDcD=YfEJwgKuh$fnl?oSjYn^{M;H+XGE=+G~OD z@0`FN#I;>e7HBoC%#&E-u9IcjFGGIL2uOyjW(A=&pPQTG^FGf;w&ZUFUFx2mmGCY6 z*Rr;Xp50Tt=I{m>9A*-P65L)jWZ)ea8K{*-vdZ7V<~^m?r)J7}QeXHj$QK{~RIS{4 zEFPzKNo-!~TrRj4BKJ(N2bVFd^g*U=Bf4}6SoMH&VB$N{kaVdNR}!J=_LaZL3Xl&-fBV z8y(R6C?B_V`CHuXxzDkGP7jU%#1})Oa!HeN7xqrgC`OR$UOx98 zhA^UCRsnet*PO{2MTBx)2HfB?&2slv!X+MkS%s>!9Vo0m*ximJsdjREdMSmY3?470 zQMGbFI3DI%S@7b{bbtL=S|XLGmi(b6W`I-S0#yUj{x=L6;EdP))Eo+H(wUH-e`N_L zq8r%;a#?sQK|m+^(>xb|{(9OC4oQ9ltr*?WX?v^lMww}aDR0-jU1o8!m3^{6TqOV7 z!c+Z{9d~EjuX}$)bAbK6Ey6Wm@hF_+c-&d8uh%?PA-yg2Qt;W^#g1a2>ajAhcKVLY zz;m*if!K|&e(bvU_+AT~Ca>X{Wba(A(B-vb`bG7bZ-M*Gzss7R>PM&w=MM(_eD}F5 zY?qJ4?!=YGcjbD;r~IMaqVSZ5gpooS02$oVvz+)%Zp6=b!Js8GIYHRN+4ZC zOfsy)R)i9|H`HwESP@{}Gb>s8ZO$-XSF&@qfsIXv*O-m9C)9tPx3btYKUnUBu)Ha0 z$h$BOu12S|f|B7n!%n$E>mzG9##Dp zBfR^>$upYDFT&$F5vkQQgJmj)eTzpC{?F)%cQZ&feKMMQ(+hi{G(#!>qF+g8v#lKXD22mf81drLF{he8`|E^I$H#9_sVpvXt zl0IsHe!l_7=@tZ9t|cBlxe0U z*e0Zu&{yMsd4^%o-WZNt9(g`p6Y`iIPIFuW{Zof2-fZP3^`yOi4+Cqpl5=}Z+5?JW zn3hAep)bUhmeAXtc*8i2%Z<}h|1mw<3;PiNCYo&BsHht#+W*{5u}Vy?(^uHytXpV{ zs`aeA(0t+=#KkmGdu|T1Q{mIAPTH{j|KBySJ_&bJH+m6g?|Q50!>ut7OWAa0uO;SO zxrK(^S-~SClIZsMPs@tRBXzw_qtAx0Qr9uQEX$hCv+LK}HxlF~oEkYPqCwhzR125? zm`Eh0WJljERJa`1^>&sI7+)&UYPfd1XjVWOXgwb>cS@ok>ge+FV-_RNn?V3 zqdpCopZHgj(40*T$KB2p|0(_Qo0E2?3j^emHTB|M{tq$>#Wm(m2|7T>o{bP1igi0- zi&;>o*y>tf-tVHgvxP|&E5VPtplAGRoqgJc6Sd+%?-h|s? zCw&vF7+7R8M1DJ1YOL@hF}+l3irN%*7&3?SCjOOkal+B=);?`WJ`-jIsXCG9Qk-(L z56KB5hoDsd-qbSef<@gB?EtaNyD!{nq+UpN>a7_eH0RpxU%PVcYHXe!$qcxqOT$L+ zr+f&C1vh&`9W>Z-(*D?^$Rv!b95|J+QI%-2&M~QY1Eg^B)2!C*Se;u}$FpBMpG*TW zRf|A^QSr)jTcEU>;c{?r7PV4i0sP%wpwl7Y{@hZ00evpfwupsYuS{hfk+_a0UHwR8 zKDenl%iMPQsiP^6$I9KmF*3^ea=m*g;EEFq?>h-R=hq`g%-omMXRvkefea^Z+zWAK z6tjyE6_*v)v*Y@ek1L0eAL2r(id&%T&8o||)JZjU7<4Qq&>_hH(>$v?ywKZ%`J}M* zAJZ>H8|F-i6GhPLCnc->)bO){q~7Lo2yVbjK7r`ntYq58&)L(oV5}uJ?JVy#DQ$mX zytE6sD2ycX{}4dXNd|x~97{Q`qpnefNUUxbF$y zngtw|k+2G5`Rmc>-rBV-xw zu#$_Kqp{O7{5X*yzGl;s5dFPwT9CfJ^q+4SRIo{7lCJLJgbWavvv6uA+cs)+oP~-D zL%-@Y7{M_90gNHQT+O9i%6*YFAlabR!kMZHZf=*7dq3P69v`$K&^R4<1lI*LW*7=F z>?tMYC=^s}PP^9M9RdpVf)y^P>8m%hZ6{)d>|#A$_(UoG!crAZTL6KsZR?bprl$Z7 zmUxFRecARgi;?&+*3Mo}x6`S@_jma{?7|#w#ea;CzWL0cw1d9eq6-=x%4_+L2_W|0 zx8|yldpqZ_N?$9KY{0ZU$G<=H~B$Ej&R z^7Kg>1rzx}+o$27m9A`4JhADAqiP_e#Q?~?9@s}OSTQ;D8_A!sY?-FGX`&47(P?DF9%q#!}tHLGu?pH?s zQ3|V_TcOmA>8eH@U?v6R->Oc|eL5cRMcM=6hFO@Y;{b7;*buC6Yo^NA_!oVEQH@Ov-8`aQWo+2ThqGo4kb+Bon^m%5kzV zRtwp~IfFi8i8;d2E1LtCV_JadHvLh%z@3{mvW7LiGhZ&s4DU3r=LQFbMblV-9l|O^ zm>xlsQ@}>ZXT|Av-OU1nCyJDmV)niNtyBZY>pvY3Ql_k(*~JAc4BG)%?G*1OhYQJ@<7!o)wJ4`V}|WaJHJ=b4DZMm7*wa! zrp^MKPD$*Y8p0GiL5h=m%fisV{3#d8(rmrLfjL(Z? zfW{oCp?y?IV%I3DdGyP30z^Xg3DkJl-F9YNPcYV}O{~OcDM}{Og@ywpN;U4^*Z&Pr(r&@Y*X-uWCpaq3L!KV#NW1nhSWU#JN z@1eH|RF!~WZ47-FbrHP#hTOaw??m{J*u!aiJ^)p0@G?!hYsBaaXea{{>v2_elQtM)2x_%QQt}0%3i7fwSXC*&)N)c^Tyq|exdfc-3PD%H zL@gPUwnBNf^(2AT$muHx2Sc$YoVMEz6I&P8OC7=m4ojb5@#6=Z^HTYLhW63G<`UFk zcrE1WSct2<=T9(rP8dDJ{T~wq0qJSFAMoS%&kZNdNYm(m=mcXkR0eH-F2tI2 zPW4hz{!hi33xx0??bj-+4rkS$@qj=fwxge+3I;~X6FHyB)`C(y0i9mi3=zy%O^PGp z!eFn%sK@F)8D(|tM0YC|IWqNiO4A9#*0UuPBobFGFa96Xtv^ck70PDotYAu))H}z4#>2B9-VYuyrjjb+l zGkEzrnW}p;%iyNJGW@FcV7invssm+Qch4qeh*4O$Au+9cRch;!Fz`=Yyz`?SS}at@ zqCi~Svw(5@J-ykmL(Zf%3wH?s0O0!DGZ&=P~8xEj+7uiDOie?!duw~@=fW=OY zOC%*^GW@dwUleAn;M3X@Zj(}}zddi2&uTMH6o_`4O1jDgdm49#Htfj{(q~^0jOy}) zkOK5(jr#$J&LBuQgO~F7^im*AuyMs`GRaOz?#0TvyG8@;b3xg@L)v@OJvR!cw@XQq zJC#z>61%m#V*btbs@E@GytVEk>cZR-2CONe%NPR?pRYNB4(`MTK)^9!wy0*6|9%`79 zV_uF-^G%;MP}kaBp5L!rpn(%u3f(Q{gpvfspy~FzA-F2+i#AhbM!>7@2w7boAE|lb zZFNKbGx|aZ4^xAzaerb{-Oi~!3)f#s4qn|w1dU76hoD#DeWD%V>mbU%PBRTz*PFdLczJubyGDL z|6?k6KYfeXPl}l3ut-ov04VFWUo=&E+@TK8Ju2;Bu#-k&bMF>U?(XDHZIo+EBq|Rk zp4s33>NTBhzrK5g(YdiV{tA`)9}`|FoMwP1SwJetXN7xtiL4LwiEGR^r(&%c3WO=> z_gQ!Q-v!dXo0<-w@UZ*zpRGcW5G_(2N)i*{s|_yq>ADdQx4zcCpOVEZmhTgP&GU$B z9Z^?IWG`ln<<&;!<0ZMdk)20X+C>{bB_h_6{t4h{3n}oL^BTF>AT&J%LVaqR2~($- zciuezyY+4ez~OzT#^=n9v-Eq2{P9A2M2+#X^It>Wm0h^dbPq(J^-}vD5BAUQ4I!GRxO8eZ~6i$YN?*BCUxaUPQBQ3 zA{x8)(+YpNF}3JuL8Nc4*p$OQZU=QxSr0OTh_o0pSmpL0?XB_@p9+MVOD44HhqaCN zHJ+Qax6?<_l zE-Nq1z-7*VtIIHA#S!I^YhPgSV#E_N>?OUR8M0b8!sVXW(vefr_>n|p`3)`EplVUd z?fV0=jG~`*>{1;HDZBL`MoU=M2BOCN-BUrK|7772-BrTcVvzW&y&Y84!&7syUsk>=Mea~}m*Lh8$3l#bI3F1kcZwmTa9`76Y$(d3R5Yz?eEjM-J72iK6ML5T{8MK_h;I zE}70cg%Dbm0RTP!hx>)x!H)tIRjViYI7w-s;Y-gLbmfDx@~%;*+rGG<#+nxz&chzD zbZ6z9*~C)8d9Lc;*qr`?JTr%_MQ#)%f^037_`}*&Noo3~@rzi`?@3G?7v9{~>0Rea zfl>7X(6EgEm{_%bAdf+VttrhTh%e!pr@=?66!v9IG>`eXn}3jhsX~l4cTc_HgJ&8kPr@0QcKx6*j@j5(#c6wSW)dc3*m9kwfZ@Sfu>9%Y5yc6JyvFOK*Za4 zV0_VRQvrUuZDS;?IuLc65LT!`eJx= zOJP_)gDIYnYIvUFSYXCh$`xxQ=n3*!KXe7lkc?Z+TUw0okF!8~=ibeq%}%Zii95uf;;fel5>qqH*o5zYm-ADhxnq zja9t*p5h#1pzqp>`0_PVfn|r3y}nRndS?U zTZCHT-^X|!JlBo?@V!n3R~=W%`E0HsV()^^b!Cy#>X<^4NGB5{VYWmBlJHuT|AXqJ z@{Z149@MFTb zc6#{zCGUAvc;!FzXqsp#EdY3NFfIVvX*JQT6bj07ymqRNhZ>Q0_h%(`acFP!plo@9 z;Vn9nB)8lQxvB;VEu5pLDj(hzLc>!sXC31q32|FF#jdanZ*6GG$<`he3y|kI@dm+9 zU=fWY@gaAnW2XQm<4wm2#r?pnmy#XcFGeGk+cod2yQ4XGpLO&0n~4X&x^8Mvc&Kg^ z(e^X|H{1LO|9SU5`W1M{ztzI-PB#>YJh|@~lT2o6rIdpr8O&qNfHdyB93?GZ&C4xQ zZzIfe+;*N@=LxuTt?i21J!8Qix8g5suTH|wh6qu*NpeSB07DhS8=wddm2|p~+nBl% z+H#=kaxv>pmeb=ZXTm;MqKn){#5ihx)Q}p}T>2Jve+p&Dv6=edW}(E?qNmPEP2FH0 ze~*wZ$H_x}?)997j~t)-ga^@^_5&jHmGwAxtktIu&5xQqtyi|pFI^hWteSJJ`-@Xc zIKEu_jR%t5b+oL5?T7pHtxqw4rI-&KQ$#|9Ql}b|%3^NJSw9N7p{kfm=;-NP_cHHT zid~|bA}Qi5+gX(X1$ab6i0P7mxXILEoJn0)iPgreOT0mxNUz$=JDjMh{Q!SSMcA$Z zW>#)lDasE*5z&kcQJ{xcSO=8qrgCZwPxYuj+8*@I`Q;>+m@q?TdefBkb*=8Fm89hR zXT{$%lIaOM&3QAB_R|;xm`BwHtLD!4B%ax*S}pk78P!(kCpbX%MO53wf&c^OQfZh- zCTE>SR(|&wF5d;j6T55yn;@pDzSABHO~d4(%QU|cz8_4O$>oDphDdll2q8CX=z zQ*^GQ{;1oXIL- zBuFtIk?_WS?|Y}AWj@-+b>CsQ3N7 z14(xKb-O9%{_Dt{omJYvRGC<9Fd^y~TjRedBXvb~rsvE_!?g`bPv4g5%XI^VFZ-&s z(Jq#suiyGmjC_e;i(j^j*Rj%h6Zy=TJiuz!cFsPClzbY3a<%UAY?gT<+!nvN=vmDP zq+RA(VnGt`oJA{?OQ!oX-8v;0Msw#)JqPVvCaz%5z4bO!*&v%7k114S@w;CvC)Cd^ zSlI}@_W4afY8r{L^I1p=cS6Ymk%VUpiNJkdWaQIJoc&bzZWZV(RkC$@?ZLV@{emw==$*Qn82^4fxhtlF7gBxjdM0f_uQ!GOv}eGulr|t)lIx)A>)RkWiqnI)G={ zCX>Xr%=d=#ykO47^9JhKmBlfuXtd67`}!?Oag{LpTkji!>=kwh3SV4?!(EjY?bmDi zWseRvwInMAMZ0eD!hq^|<$P<}kF7KwO}l{I8<(VX*<*xF#O0B@Fqhfm4SB$ zmpaxrhrf(5F_5~Z;hS&wg@-HW^N4~b~}WZRt~@fdsDeW8}Z zKW(%qpIW;>INUm1b?@Jc=NmbT%jMXC3c#mOvE1GVf5zAuq z%JMfKxE;rKYUv7@q3Qw!QqSfGN@w$B`?bBVzpvjbP~iCxc8&Ii0x6zz&4g}&!I9|H zWr^K_=19enyn7ZRMmNlja8oigOSOyBUx7J!x?j#!{Kqg2QVk9V8I)4ER&5pxPT$$F z=@{rg34^6Hy+4NA&(`?eeVM&QmNZStGkXx=@#0RLn#AiV^fc;F(~ zl&%YWr6Xm0oOk!kKXV)^g7273DVDytll%|3Uh2Y2bn<{p$62NH)urs6C9nO10{t5O z-5XC-t;+6JDQwmrVKzIMuRYc0xpezYadtLzNIy^iR}WG!1#cCqTsrgA@Ra78do zcPTs>$3+^SoChHc-K8?QfHt%M2S|#c82@xOdY8SU`tHe0SLuFo|2leMM6X66s(#!) zQwI?!8@guF7%97>Blh=qtB7ufA%Zw`&s zmLuSWwV&JoZ4}oRoP5Z(rIK{N1w-M&#~_Us#X|nnJ#Z=ZpCnjfl9Q>*Q?F~;tB1f` z&g};!dQ)HEg=qZ3T__*4J7y5=Z^EC%*{ciXbW0)+qif^M6OFeQ6*nZu94$s!h13u- z13n|_KdaTIXZ5!OZ3)v}+>geZHk`rT@Oq3}g!oMyuAR zN)TF)i`BO@@Ixqe)j%umed9GV7smKNPQ&@IH(vGG{#)ienjZCuP(_ic28XETI!o&n z#Fzh=#Q8b$c3+!#m6`3Ujbe{X4908v%VGP)eES#Xl7f7{Udp+!$qtd48dLq57OY># z{?XxOfg9$_is+g;i+ZUTewr$3m1qDkMLjy*pN>FD)geQ-SXM>V8_j@9{KpfRi}7|< zZAry0R0@9Q!;o0DcbVaFW01EvM~~)#t|YwFTA~TcEyAPEn|RF2Hjvz_&UxJU>gBM2 zfmS@BKxfCvvZ&!<(ujlxc+EJ6x{MuUS@mDbDBM8%Ky;dBH|6Q4b;~{@^TzaTDx$?S zY>xUpN6^CF(h?80IU?TFc;?ObA+*uC@KI=>I`VVf37q>U`vuGOj|IP;_9c7!2_1|O zjITb{&8Q7^Tb3NH6il3~xH9}VY_&_{BofLhIcY-PGDdw$Dl6Nb50h# z`(nP?mpV78ANs(od2SzS21JX5SO>mu5cT)wV3{f>8rJE8GMeB+)Su^~ag=l4!*f-z z%_yveU9jwOG1jPu;^Db)a_D05HKIZ${#w)fu&G|$yA@LyAw&I(oqmmTL!=fy^wu?~^=XOOf(Go&al(Fj-K_Ph$GyAD?M zbclX*r*0%8&po6wG1l*>fO=kYTJ;(K)CkHv3vr(_yiZO)2$XkzPrwcKR^&o%InPZlJa7lko#MEQ~%krD&d~) z<<)~NBTnJQmdZ%V+QL?pNtb^Uj4=-?4nqA zSJ_cQi6N6u?SW;`#t-_k6y~SqE!p`Tmo{u&Q-ekCT>82Td9r2d+hPQgoJq`Cc{5P` zGz0v)BO&(Db#*VZbjg-Adq>xzm*oTqvJ7{CM+>R`iax7L_>XG4a z%ki`0$-5yHUx`{LrgO_pC1h>6+j1=Jvuw9DOoZh%QU*Ku}m)83W+X31!tA^k$B zR<-49Zw+|+Y}l`-t>5 zZUvFz=%O$3uVbrkFaPO8LZddna7MA&3Ao?09~a8iu=Tt?&_i+z>`T@R5)4SScNc`+ zsyfrEb;~E7YE>cD)o(7`ywLdI(M{rZN!ib+0?*atSX$@Vd{n$yqfWT~YBkS^h_y_ z`Tn*J1O%Yv!_#KL@Pu2$aC9Zg;O&A(EJk|A>uMk=g)FOdr7UA(^R1YwS*qi#;&Ub53^E@3069l~$4Hk1k#_ z<-kY}{t?VR9oOrC;^m{71~^J^A8LHq>r|A9mSd0WybF4hn)>3(04#eTRdyxY6a!#q z&3APpY-0I<8rk6(Yvth~>GWo(>eV17c)$tUfA*-a=uQAEs|me(y}D>wiRpFlgt@Ui z!Wj&=IPUw8Nup?`{#M@!m{Rk{I6uPbS*D+}qbEil;R`&NmR~&g*iUCBq@}l{)u^>E zF(#xdb~RE!WnKP^)rPI|iuvqNN0U;`xVZ6&?j%LQf3I_6}~!<=4;qsYN1pA zYIoSj%n9rs`g_M_%#N?$p6{oo%yRw6*w2k>t_=3TCS@}x8^$UD$jg}0O??_+Ie(m& zc10|8C4XJH1fAexU3?@5wGEAH_@a1h)bfI5u-TbQ;=yn9$5dCay&UaNXxl}Obd`KK zs=05UHq_AS8QZRZKMp$G=8WvwiD#&v0oTWh5oHNtT{Q)GYXc^jPN z2hJy0s}Ogt$%(9$x$^xTkB%9rZtu!1BLateWLDr2!7;^h`Yj{{E$*D05LgC^YV_dG2?AYvogMw0q9%#;t zcPG2{z8Q0L2rX?j)BlWf8Q58U@Jn45byT?8o~9V(4trbj1Lwo1OEbuwDeC>b7ky{Sc8X9oFIIY zv6J8!esa7rm(v1BN&&J=?I+$e7k!`9d{8MZJLraA%_in=5*j@Dg{)oYA~&bR2jJ04 zF1WnLZUN-O>k7}D*}%P|#%KF=Q=Uzh(Wi+Ux<8&1y%;q?P~0(mhfPxh#g#42=XsF< zOzz=?L($u%!{(boRX?T@Y1^+z&Oq65iE_#lZZqaPZ^kRruq&}r?-3t%V$>GOxeO6w z%z>&#KF~Dxw5_J)RTajd<#pR&%e-x3LvN?x6(+38_4djNsq)oNArTt7JZn(nRCN;3 zmJ8^dF(rPbXB-wHhp3}9m8n9O7if0Ky^DD*Ti|6NX*h9SU%AKV+eS$>Ayg{Ng?5|% zU7_+r>lKnzguA=*;I>DFM1aIv*&(% z0b!ri+qXJ}#!81HZv3B5R<^moHRVb4FftgG{*q_^*~$7}e&S0dfd$mT6|4PRPK9K} z|CnB5W}iUnDbvnN196r`dzr4&G3T=^zbTpueD39|hkCoWAzYr3TSeS1n3_0!=_+=0 zK7m{p%6`)Xp@`D3j2l>O6Fvtj*Y41OT6n+c&1`@5t~i(!cQ?A(E~4<;$hE7*~QV z4mQ?XlAZ=Ds0^P~I&SC#b=txO<}!o%>Ye_K(lBzKPCcxTS@!U)AL&TIG-pm(CY|wv zNQo1#jOcqlBLaetw5azdp28!0JIX@-xTG_sW#wn@(VRo6!dW8`fIixb#QxF|!Wj_r z!bVAdyePTX{pS;+Guxl}e?=oVwYJ}$59Ew)Rddf3+Z#?^5)WpDN|rm`w|wHrnxr44 zEBquWkT>j75CmHpxp=)*)GbbEfpwa@(=h5=4LZu6s-CUNs;Nk@X3{*f%~ZZPBYG4_ za{9E#v4ZD`Xjb>abKY<>9ylvek|dSo_Wj~J3u)!PVZ^5mTPr>BjGXD?*u2>{GJD5I zUVF&*hpHnex2gL&$8|dkZ#rz0&b4jx)&q+^`egAajCB6^LzuAT<^xIm>>T!7Rx<@& z7S8N_?O0(lZ1g5OC43o-oose5-ZWz^dGR|CZKPH1b&Ky0Q`w@FlDD#e*r)AJ%U}>+ z*ysZdWH7(Jdq}c4G*c%)P>A=c&}-?>!YU>sXF6D|Pn(?Zk)JfPG#~c;GcKCgS${tMPfAr{Nbheez-(xjYUK+E zw+bLsO$dMLAI46I&NlpA%ICe)uxa)!Wey5|g&*dG4gkWfBx$ln0FuGhN%H24t&G~m z!=zz-{D$?ptFkK#Nk9PS2q{tj9?7JsNhh^Rs}y-`p1jaH63+N%Xs?d`)|dJ{uGI_> z=tp!a31CNPo5W(;<;rDf-rax$z-NRQC_|@Rk%$e-wO$#IHP0~?_yF18-cGynwk0cq zla>N}{)bl#T&pm>P>rk9f>JRH9*7g!+TL@M=nU!q%g6cd%&k=316=0m)JX_x9_>FD zI!hk;pjpEi!C(&X7m({r^>VGN+Zm~rAbMgYCz4(SXYQ`fjaDcj;PhqN^G?M^Br|P- zCBZ|%+M#4waNxp$b`)@Ro@DG`93b4+(-3KF{R0hLrjPo3l1F|!5L!_uBh>p8rK2R$ zr_MhIBWEc!PsT%}eblPEVhe~eNF`UkF5$H4+cmiS%27kgUHNH$OtoP&re=F#bNOq$ zh+$0zTDhU*i zb^zv4T5SnZ9`fgV*obD0bX-NqBR~32yrh^ahn>Nd7puT(-x%p1g;5aNkt;kQ7Y zYUVR}bxOpn<-D2Q<&ST1+8l-WOGcarce!2xZgn2sa~yopC+5qLh!AJ$i?FdIn&~7> z74aP>+b5Zmz5l>EF#4?2lYPOq-d?8DH_gV~kXoRnd4n;|!;l~$IyL_d_=aCVNcGPz zHz2pY1&Kyy3(mxP)q1P2WKVkk94H(-e5FxFkNc0wDep3+3C}gs1>>2w)+qm>tmt1| zGkCQ5B8;SwrKQql%|>1C2om2=Y{)c}1*CP;ZIGHu8W-4-q}?^d`Dmi`A_e)RrnPZj zG?xHVI?E4zL@X*aYGKZttn7W6wSY+gf3VcIxNXd+3 zrVTEmu3}_YLE%?PIr7N;<9t(02WVGp9DMBUy(o@YsXemk@2UwUPE47Se`#zXE}i`s zQTiIOTjCEeraW;!6B#?e=n@MLG9n2{APzuoOkwlYh=9tyalXq)yi;MkmZRNqW5^`` z3|W?sadzU2Smi(jq=o!)(2N@hFQ(nAR4>Ee0n1e0uY_*>5=1ZgwH5-w$l zRyuYSd|ib=9fv`({8XV+SW|`=lck_6xK0C-)yl&c zdQz9OsPHED(`#bAX$KMa9FjpoNBmSdd9RvUFkh3G2HzVqVvhwn{|3sxoa~w?VML)s z45EoKB=^3JI`qVhovq%i?Zj2l6M7@Uz5y+@OV3PWSke}y7WeNlA=pE3Kg*+d9|0-k zu0zL&1%{ZdC7csD?KpisHyac>RcOxMBwm;JMM-^wR~LCc?2zeV$BR5T#jTl?GeBQF zDgh`<+JhyNF(l@0&|dUk9v;y(mx*mBn>i{{kJ-`3CSM#)1*F7CV}}SSUad)|ImKzh z5eg`T>M4a@Byv~lKYN%?I%jv1D>@DayQVMpyy{1vgw?YbO!n;qzWgLxG!?+HwA%?y zYY0n!)DR93Zssj@tK_o~x?(6O_6s{)eI@YrucZ}%rfJ{m(@}GkFw~19?fEN?0rO-@ zvv}SxARZfruZ;PR3C2kgchIacN6IgrrzmxzZRG)jUE&DL?wYqkbw?Lo%cZ)D78hYV zm&(LX%40_?mE~R20EIjpKUj=`aD3aFk4H-_*7@83$1>BNYxncQLx6Y>rnS#Y?%wms zhv^NLAO!Z}%Nk~Z*5ebj>`o~=2Krb`JaoPk<^E|((*?r%SA!YZ^`Hn{;994|jmO`E zNq?)0cYLk4JpXQ;-^W&;dJFiXI`WmX19*X8WEaLDT~{8SGIoJnY)vx*M2I$iD%GdQ-(F9~h(@ zyZxEHn%zWW!Yw7H&<9fq9h2FC-)dQmGX0(ZUg`$k$#J%1ap6bU)@x(=9JlfAn*yi_ zNs)LL=o`yd-(LUipZoC7wkz@02_mvV=#ZfFVQeJ>E}PfFAj&$D`3R8zCw6C@GB`8nYl{Amk^j$aN`&8dqKMpI>sdAGmSo+t2-^7zSeo?W45 zh7oykv=`F=Rq12((X3>Rtj18YY-NQHtu&6&M>Xh*U6iPn+D)nR#0pRUPD%W82R*E`mS@ZDbY3mN*1MKk}ZtivqTkLmlZ>~d(F2>Myt_wq!^!bPb1wThn*KxsGP^=p7nx9zGL? zV|Mu@wS5C|`M8FRRwoZ~cJ7DLl9r?2m1OB5GT|6x&CyZhdfR3Uy$hnGc;i}FetpkD ziW?P=b{P??O;k4gzlB79ARvZosM@jsTqVr&9!)wF1R$FaRMeWrZ z)!KWHE_>D9)Gn#LD=3OmgeXdk)~LNlf=Fs_YKA2Csu4tL2LCtjH%M|_dCob{J$^!e zTCRu?V&&03&z}nupZfGG`>|wDwz=2Jv2rYBT*Qe`Zw-wy;)dPaT za`wb3dY^yeKYvjA1A<3=8?1-FCJ#mIQT0ml+)ueT)K@lTO{p=E=O$8M1EG#y z#BvI*{YQq`cJzGJJs7{Y%iaJTL%I=KfN-%jcYb_r9jiE12o?kNbTwOqhs)Qds(P1Q zkC$(^Z1X6|iZ+<&Bv)bdx6q(Dj#iR4|G?)zGUB9?2rqPc!+#5+7;7zm>rbzbt6uWa z{%Kd+k@7%kqcB{&>i*EA$eZ`c9)v?DdeGn#l9EsY@vE6>*nGkcP=K%Zg>sJ=SG#A57>^KydLKl z?qCycW%FAOy1!Hn941ACu4cKR@R?%o#+HM&14t;Vde>)ln`p8H%q3uZu(l{WYcx15 z68(1QM_3AgpnLuwS&QT`g0sEzO|q{yL7}JOKQjKIUn&&d27P%xBclZnzcLK5W2p6? zO9}Sr)ZA+V|EVc-|Kvt%#ls~wnMlcf=qa0%{~Y-uJd|@YfpH(cR9_hifkxh}3-tQ^ zj*#Qo(Ty3HDDrkk*k|fNUi>BVqLErqIrCsj7JRkK3cYNy??@424lZ|Y4uwbveh`r< ztP3!_BxstO$&b?lKE^>-1r=TDVXe?$jM6r9>___3tn#sm95+(=TKW5GFLXo>8jOAB zmH~%a9O)ZBj>)AW1t|j>G@i~1q3$EQ8}up%*EYOJX6m0rAtv)QP-E4zZ1gxwe3BqZjkem^RiLHvvD=5d$|LzP|828oY6cctrHp2KrKeZ5REg%b z>^J4TGP+5Rx7n;iP$wFiEShDOtR(4$(mr`x(%mw?Le2xW4OMQ(lcpkRPXbCN>HwMI zdlbE%q-dc>4L7N9-0z_K*|~(=^MVp@w&tICX&8ea$dhpR^JY^ffa2@=ldQq}yV&FF zz@HpB+ZP|6v0CybvmH3DFa!9JO z*&H*pNuNbliefl6Hk_ zs*MM@-DNJcQ?I##O!igd1E?!FvT(-?zh}rKN|)j4^jI`ERT4AVLelFE&|BRFjU6Xn z?=FrK1@ydDOgS`L6h+BYtt#EBiyTX;Q_Ipaq4D$H8SIicn! zU8rxXViCc7b4z&pz<2>&vY!7@WX49I%IKcVvJ;yD&url&uBMrqku8SOYE&Y@*3B3o z<+q|DBUx5*e}6pV;Bq!hoqY#p^) zF}1Yz=tF+AhzQ*JwZ8T=b9JULMXuP)cKf>8dQ6S?-;)%7-N|(fdm3hNqoU(g&96?dxlXA3840Y&tZ$1R2~|!_t0uJ z_gxcM@KN|^v}8kRYGm$~xdyl+bCC4T_f(7b^jGztZ2R&e_OA*f6MchCmla98rj)-2 zygr^VKpZj6zuf1G0Y#A{AsmTIT^s05<)CnwWYX7}! z0-xgBIqv-th>n?f^v_z-wNi{=?(can{uIl(v&PR~SH530lg$*I?&}@X>hFbL-~SNP zIsW5vmuGdWhmwm#NRKz3R+(-yg$US6T3?m!)vwGKyBXwWdKTs1*{F$Jw#VHr0lK%q zGTAtcW^kFjF#D#L{#3%^;RVkXQ=HhhN_7K9`(m|>x3vHEm3a7+l?~44B`tEr+fB{c zziJR}m*lNMDn+=lD}~5E_P?0vZH{}t7~=UKSx}N4-v|9P(!9a>=Vz?tb6?d-sm62B zW_9DOZEWlmu6AuOTCOgsFCRE&T>&`udLD>X_^A7O9Gt-Z1aKvo=Re9{TpNq~H-A;J ztxH=oFi5yH5nUPp2V!X;f=T8Y(}3pD;h$p!T_rp4^f3c0PBFIG4B8TcT2H*!(ohk8 zkapeC2+GV{mD{hOTQoRMzSOOy)PUa+g#l}$Fwjvu4Ls#Z?gWs2wQowAjl)sCYLXA0 zQKYlpOb6WayPFne+rbnw?Q30)w?e%>^XE^B$E-~{HxNyc^CwC}PoF&eQu4&|i+rb& ziOy|1fqliliE$3E{CqxlY?S|1aH+7jMBI9Nm0TQBk~wX2l{N!1Yt|bl`d=G>n1NxYZ9&Gv*zl+&6nB`>!_e=Nvz3f$$s^1G4 zM!JEfgQU63;O=z1fV_IIKy{|)_fn4qLbuTseZ%Y?e=0RL_Jaab`-nD_=H}YG;K=dqih!bGLD`14%XJO zw;7d(ST5%-Gi{6bPC?(+p_7$Y-_E_9(<`VE9$#aJ^LoH=yq;h}I}MRi7%m}LF;K5w zU2iwjVW*oEZBR;f$H8=Sy11>)cFNN>Hs`sg;jF|FiQS}589tRup zo@9=?_rzOr{61t2T~V~@Mg{jXs4FifI88Y}Yp9e6pAWL}6fqdj*kb-mqpi=URtm!~ z8!bBDlulTGUEk7N*=IYrlyUwsLcUBS(dFUAv`_r(?00&7A5v@*i7gH zdTk_4mc%-xQBHH!z<^Ta&6Fj_1Zw`)G6ajx=PW6rAZ|&|)>9+QZsjY6PmPMY>K14A z1XDknov4u1Jshg}G6yrA9|X#d=AKlFFYqGWQq-Z)R*OtNbT3Q7Ia;r}Q>D8xs3LW~ z;p_YLG|0wXzI^3sf5?+x zcx0M%ZDQmZWU?%7zB}%4G2>bvA|j)im{O%;HbMpW=I4o4ZZl4LotrYd^L~XWjM(PM zP6u-F7Wi)xw6(4#6{yn8d0_7?&AcYQNB|HSP&<5P7I`A*fucqHWW@^b z57PIsZThFKOy%C_Q!tA?{s#e@>cnGOFrKw-+tIPOHgz?5m&KOx6*#iN^(Tn@ zu#5^oHKp4qB>Y&In0!(*vUTI^T#NkJD(A3j79~*)2h04y*ojN|F@;yW<{uGLxDMp2 zZeLJO*WiW+;X0PJK7V~|GRMwCh(eKf&?ZM4wYNU_;nGHu5WGAmnWx)zg!4Dk-**+r z-w=@a$cdEJ;^d8!#*U3tRJDH|eyp#vR>rcLP4x%87sp)KNT_dh9Bmw+-*f`CN9FsP z{_D^mH*0%8v8n~}+RT?^hvaT;1gx=zITctH>M)8AZfM44GNeI06PFR2{@@MXzv7sq zN0`dkj(XU4fhI^c3J{(>SMh;F-*})p_S{RU+|zE$UqMo;Y?LM!OnX#GD(KXm+$1Vo zmZ8KNz49KXIlJ8JJZDRlBwfVFObEARRNuqWvIhGORA`|dRAAm$5w?r)nMw&%W-WWw z5?l>C+^{0i@5`g~iQ*B)+7D%Hef86H@kwi%9cD8!cbQW><_~LGOD&a`bDDE{(7GFF zIEca{nnSKnz}ZCac6KdG28T>TCgu^wvLPs%_E3y$OjV$EQv?^S35PXcW@Vx2cg4hB zqSeFQRc8EoLOrijQ|rSM3pXqt|3+)b9UKtMh4E}_chU}1Ru>o7JcqI6>d{?C^2PSg zn6l9<77rf}}LK5H#v!5nI-BRyi$?TdpKSts*mcI@UcsjsB?5^HvA||MEfFo|c#2z!nyR`Y? z9~1YQK?$5Jpp|w&gRSJYHT5L61D>xtad0;!{e@QF$BPtLFF=UneY>{MW{N`0nQKZ4 z2f;@7`8C_vreXv-Yauu zJ@#@_uz1A&RQIWVyGg7!nEv1Bw0OfYo` z84Ar_#|ij^@34*D9lhU^bgjQ!RVS8hewHFjx7c58Z(V8qaAF=;57q=hHgtEE%@nsr|)uLCJ-%V5gS!@gtf*a!b6H}M|1!Fc~p1#Jd&FovxrTm1JBpYJS*OpFGv~GuvJ*%U2&w;p~ zjwh5iwJuJQ}>tV%2$#pGvQu5?-yUSTiP^KB?c{1JupYk!p38- zFimsMG&Q@kcs+*rT^5%!`=25_JLTnh7Ap)IdYxWP z#+hN7EpVPOFqLEFoT`xqiEDz_;$fp3*ncX@Y+y$|5+%Td9Vyx*efp%21-^-z&PRJo z&X9Si?C_;^n=@<5#e_5TLo9Ya%YSQ=KZ+nMvna+kV&b0R|MxFOV^cs~g7RSW^;6 zUlmM49;#pEa1KK1uI4&o!Ec5&TP_%Jz9*q|2&YDo1@Jxk&5NT40zE+_oj&EoNY!Yj z=|W@hJNZ?FLi$M|{#QYzV4e;x6W>&U^k`PcK2p-jd{N9WrqM>oQC+D}3U_mD`2+A< zdfmPc_p#yaH1=o2BHXwP?O$`U)vV@Pskqu0e@@DAFK`&btv5({vI$;RP3--Z2xSi} zF%M|pDs~<_625*z!s2wG-G`b#4gKS zn)A~2?IRNm3B~qo&Tt88b+*-|+ARC^n1;G62j^e0hMZ+Ztu zkQ5^hpXH_*SNZ9V5*kC335pKa`0cYu0WAgx+un=}lIQxKhU4N7JgKVPaUodf!T=Wcpml3{!X`#qF%PCU5=?I9amS{nM>are`HUH)1t@KQh_ z`o^E0tFJ>o@9lJka%mrqV|Io-bxs0j566<~1w0o{6T;^@w}0=VTMAK4=1+?~Dg2MT zyRTJdl_+X#$5(JpmXlUHwvAUQ7uGJ{-EMOMsLFVv0Ux>0I{nlDUx4bDW}UJPThJq@ z(Lfei?jz3;b!EJbj#c$+eb^&^(eGoX)?NqSjvl4|CZEmb&8_5U&|;%$>km?(jlw98 zhTEpC5Oi9@uIY4kl`WeEwQ8E$%Z|PZ!^hbnky`}=>P(#fMy)N{QKEG2!8VF3whPhc zpHBG8I}c1Q#~T|5#@l4ywp(wkN8acs6oc5Z8D`Q@9=L0s+`X-T(!YKIyXW5oQ+1z? zK2;$d1^i`Ob;s2Q_b+Ym6rc7MsRfPN>ccT4I&NT=U{vz&Br1Oks!AUa=ja$R5J3=A zrYPlXVo`C9L^j7=ErtF0NnWS?w;?ROVs8JK2JPR6?)XZH3$sLEs|vQQJ~s;9*=4bv zLx)|QR(v$?A7=}RxR95+3N~+vWp2athVxa4?{7JN!M-EEFz4E&49$iD+oS&@^GCi? zets#jXYOJ)R7CFj>bkD3105zryvPw`i`SZ>e2Zpl`Uj zjsobLlrLCJWCMs~8T3(x@Cpsk`n&~rIp zI|^qP&MZ5@VrhASTZ-vlu|@5nsQ#SgT$`Xz7L9t_5Bzh}K)W^}1yPWd$S+l4RFQvO zj1L5ZJQ^vb79wnCgwl$WQ!9@qSc_Gk5l8I>1+f>>o8mw1kUemt8m7`==$ZSZi+S*A z1>;hn$c!f`B2n{ng4efX1D-ZeF|bPz6deYYn0ekATKJ~sQGvVEZja0`!f%13YCm7! zL!yo`f2*Xbm1VI8O)V3ta^$?Z`D6^slq7vG`iyQeRCsmJaHb`4KxVBbT>F9YnBcEG z)<*M0?>~Jd+J+JMe|A3ul13??{=+n9AQKyT4^uJ%B{XMgC4DN7l4k}&yiY0)xsnj< ziy{5$sOrE`&QWU|wPTmo6TwTWj+e?E8a#2Is z<=xDy{78>+@`y<^RTk%?*(?*HB8{@jdggjcN_8ApMj%3kRGM%&-j$Uz+gxTnzui*L zVrS;Lph%`rpq*e`&f?deqh2CYOD}oNP!r2AIg;a9p;_QN|5~<`^LWBy`w-n9YiGVs zYUPt2zkGgHzEYdaNe@LSDVK}cG0+fHrlG5-R}lZ%@Tw-Efql$$QQoNk^JWDjYgp^4j;m2y|eH?z=5_E zNLhS1I<2LjAiF>kQE8j~mKI99As)~neDu+oyBniIo+-05ey1Wj;!=+Q$J}tqwE0K2}gCB8A0GvpxZ za4I-3egwnkxv|Cu-GQ$2qnM`eC>zX9WAj*T1;o&>MoNlTzXz}KT$iz=98#sH& z83N}M$yM?nSt8@M`aup4lsE)HEVL&hKf(-BhFQ;Kb~Mc1uO@sgT{wTiOQMsiOddao z-{88WH+XxvM4Drs_8cBoy_*o%s?#(b-wJ!~c22*I0*_@VGlz=3F6s%<8)!3eEgiAQ z$<}-p8b~_ZZlB~&VEUE6Is8n{eC1OGAE=re9i<6888`-)=+#mV0*m{Q=cv!Bh+ zE*0rnf3$`R+4FwyZzr{l|B-neoIP{RBQl*m z9XnE%4(xb!jrTOWliHUS!}1~P#;3n9X5N2m)qblb@}_p+lWeZa-;dn8Nk2Nk^R^ zB)puyhipYJT4~>VJt)VrhT5owiAFqojpsS>sK*OWi*FxPZx?Q_CTfJN3FRehv0R|~ z?GM$5f6C%G@B$7`dy-vkzqCVL1K8{T-jO?9Fjg8?%toGrgFSZ)S%|{%q8%u6u}wd*86qYn>HkdsA`IOd<33x z$W+g^!Es4EC+Dy4->|2;UO?8{e^PZ}G48vjVC1|r^*&mhAYsRh-svGFEb4N9#P7}d*ixI?&a$+lNZB|!pMZ68mf zQzjd)#v*ZstCZDtOEzKF*--ZgQ#isPy^cC@=+PmRU)m+Bl<~%d!ioNVP^Q zq_pE_X+M2c!^H#_74F*VVP!oa1=`=n99|2Ipb+9A_Ihzz$QABC7%y{xy+&*O95oh2 z*p=y6(-qXrIVybysoK1nCl4CI{aYt`Nf9IILvr3jZ_k=TSF?+8k}3Mul`kIJ=gCRvW#U#Gm7dAn4{B4}o+53J6kM}btErpvCiPku zbVRnn28!g$=87cuau^Js`O~dRUQ6U>n)+-2!Rhkmzmwv&v$Sf9?l0Cx@j&}s(tJ!F z91I@@jdfT!cs02dn0L0h+pb2E3MC^+hihv)IPzhL!d=q%mKqnTeCT<}o;MQqF2ly{ za6o!J|K?RHkdO4)KFe@QoK;qMWM+QEe3x1f)k?n-AaFQ4ML&A5o9f$?ugS1w&vL9j z4Oat{FN8vm1Y2eV4qCq-pC|lP2Sl!@#zgQ$pzR+u)zVlk+V5n}R&G`qj~E+Ft+Kt= z#;7xqJtME=fZai4QL?;>)++dfXEdj}<7RxfKvr;RJ=s2)t6rB?zj-C}nqxGw`aME8 z7yUcS_)g$AP^z=QhVL$@ef$-m19U=vW={Hha=KsN#xs3^>y?L0YDU{C=O%C@j&%z} z1=Zg#O#(}VOIq5uK>L$%~!b|M5yvDt=v}E!hgfRD8jeAS%sA(FLUU*pm;F4X&OvI#>S@Vww zQk@X#S8jQR18Rkb^G&xLYFY``1V4MBx{)ulru-2l>EQDR%bS$kcp!3+7Ln_pcw8>C z3{gTSPP$D-l0`b&Q*cEe0oBjySA})n9QLj^SZ)UeMYh6cp5D6A^vHXmOi1$p%1@rN zg#?himfgsE5v=Z!58)iEg2~=pRx@V}&CU7JglY@5)}+RFfjm*4BD})!5v;HA8Yc)m ze?0I;p-f2yX8!tQtm`($3BaXJ0zTgS6w069%^PLcNc7bC`S+t}bi|D_S*u2TX88*7 zq`*FNa$#MqBjARU<;%I9R>!%qJHLGldqbN&^ch6MY7p@*0zN)+_H#5R4DhQu>0}+V znf;PUAWvcGL21mjiWjd_Z1TMU&QhLI54`smP8Jf;NE6khnUSL`Xp}!{yH0g+ z+9bP;!nBoY7tZUR*=P|Qma^jJ5`xyNU%TIPScC}sSKH1z;hew7LW{b39{k*rHfuN4 zAM}w_bCq|^=V8Zk=sAig2=sMo?$QzPpi>9mNQwFR|7IsHB{dGnZ^UEdTszdW4J_-~ z&5XS}&e^=~v>m2B+H(c@3>2=+-uTm}u%ooV+R?0PyYksiv(t<56;e?^m!(5xTmELI zPRx6fI-#DlWBX`u9iEnS^eC-Q!|wQ;TDBh-HUfQrOtP4Wv&)VL@(3)4v2W!!)nEUK zc#Pro0|X!4LzvpPXcK*R*wdqMHj$>`mdA#N>ec)8f~4DJbVQFpPo*~xg2Z-*cn@_* zEQ#SR%t@!%+u<%6%sIT%PD9?f|5Pv*@4mBZ= zyH!hn4>7%Wx8C1cX>3X#4dCoXu@vla0Y?`X-R)9@LjBMCpZqG3*PG{s zhSShoH7HRQy;soq47dDcZ9Q)jQb<U2-!g_3Y%DMf zw0|r0UU50CZYUqJ2-rN99DCj;_p1=BKdz5(o93#cZrh>vsOx4E&BUClJ?-uKZ2FQi z>_|Vfw%FVPbk|Y=HqSYP{Hh8| z!bzLUliAa1cCUmjzW$-|jktyOPdBW#0;xGqjleQfKZ!b8&-GF@dF{xlZWLHu)<8)s zK)nZ(O0O%`YkITaO_xBom^o;qhC!fw9)!h6KL2bmH|YF}_Q>xbSBl&)yq&=edM6xp z`BLBn^$>Az#=lDw@7mZ{ugTpCb+1tk>GY>m_swJmI>%sr0IzoS6h0PdNon!qwHK&L za<*H9nXelIKjJxhQmR+=3{mbxbj%Pu|1+Jx-2{>D5{S2J#T#o+2nTj(JI}E5^;X(3 zYVjyJC)|5$LKV{|gWon5&=bTG{0r^@-iaCahJ_$Z!-DHC?uC@TO@8C&o$UX2hqN)0 zFJ#n|6_A-umbnCb5j!G`m$pr6MSdoy*o}?&D&)@6YJ9h?lNJPk*$Jw4Q$65q4opaGe7JjR5jajN$wz3D{)Mt<5Ta*`dCSTZDL=9biA%GM}Iq_TDfZmu-NRIXSpb$s#d*Z0fu@Q*eFHcqMp7iF{3z5irr*_j8rn5HYW` z<6!piXZH0nv#Z-WAsQZBtNQHranLxWWt*U4O)q6k4fS*UPbjMAVfnnmf_||7kj#pFq6!&z$>&(pF@a4 zBE_5k$TD-o_a1~F0lW+VDiNJHcGI+rE4Qlfc+I-FCI4-&%3GW!aT;-VQ(Yw*A{lYr zj|*x%EZ40EXsb3&%}9otL%2(;a>)23#K|MGjk-!wPxuJ)lB1#twC8%rKyA#-1u59-pH!Fby_C8V8~*wc2Vq*;?!VBPiDo8rKRE$--22!QSgg+ z7piic?xHTk@auh0&5Sza-jPOi&u zNFK>GRv&Mt@7odjH>4sV@5S|GWQ&RjxP1QALR$w%aT7qe7Lv|b)uOM>V80S8wm|GFt4NK*kXJKsc|`; zbKmFoJD+>wO8FUlxes=U12eWRl*Dq?=@fY7$NW2zedzLV zZ?7!IVJVM<`xTNpoPFm$qnY|N%Hv#C;2p)V&2+_+{^nqnr)mpRLh{>M@98rB$;?JTAeKBOgo9~=QPjaYAga~}wiVp{6kCzApK40YyL{fRK zp8X^`J^fK0Djgrc&j)j{jsmvSTlMUK8(OiZoAa^bc&BO;{GAfc7^187ORpA26r;ju z9{l9QQ@9p9VzlZlZIhNY_JHPg$H#!Bx`OU7*rm>@VCCl&c_|oAgIfnEc>c2cq`Z5W z^5MwKgjR}_=5ck@RK%Q-mLg^(-J{Eb!#T#NIR!8;bDqQopq^m--DkWpz_7PC!*6iz z7$P2XB38MmMuR?Ls|KtM&0F+4D9_B~en>otbO@6dDG`X>0&T!Pc=6_@R*!4{y_8%l z`*oFesr6&5WtTtR$SqoM*f7%DjppI&q&ndF*hsERgx!lOBq-neQu-AM{ckn<(t!8K6q+R+SQMtsb`qy z?h%G562rNU&86;>r4;L9fkgP5or_xd3FwR;x0QEzVARkK#@AGNJDEg@Bu&is)!(yd z&>A1-sqaeKXm>;;)VF1O25YzT5r<5Z6m7>OUM}aFe~IV{dbUX2CW}(Y%46Sr&WNwx zcS_O1lNx9wEMv%%#D^}-TlIKenR`gh62DeH9pnbF-yB-!^#2o3`*qCwxYdRTPf>!& zi9TWMv09RQIE12X3v^#O7amYFiPtY>`?N3XnryVgW?h=VX?(xzC~eNBI80p!9J+oY ze<>jEs%{=~pfcXvB1Ef+Z>xAv-5z~!Pi|D=g4wkh6WF5oeMq)M+Du#dQvQ*?S^87{F^*%4`L>f%f*R`aN<}6eFZR zDn_1x`&su9q?yUBdSQ_1a_-+h!ozdO;lXCH)tDl6C{cD;a>v@&)&%M*_ZMDqo_e= zvl>5!)kkK^*Kh~MS!^sQli~>CrJ}8&MC{ea`|9->-kE$BPn)}n8f+-PpVGFOJ%5g6 z$|dvv$6$8kAOX!sSmR7xZ7|4@U~%^4l(VhG_V5T1B~{jpto>|5x3|RLT;~RVsP{|M z{^pmVRdBu2+o%r#VGis;_(6h=mp!&!3jSOfGz=xXW=I17XD^C0*3W&8Fs1gw=59mm z3I***6bb4#xvKlaBx@M7WxseY>#o>?dkaZ~L^UX24n=cI@+phy(}(Q>mm@*)oh(XG z=*rA>Hrl>kRyoXAY+co&1x#(8z%;PMas}YAfXmWu`72GnVE`|_7^>P*Jkg4N!O_81 z@(?RMlha2~qikeM$dUA#_s`9Ion&IQfw!>JvL3NET_TX;R9oxDtq)$vuW^)}yn79} zUj-6_S)2feFo@xH{vq>DzK$06 z4d!&P1*dOH-;Z<~Lg1ZuyC-oAq8Z*#mloxJrw{q4i?@?j5@nmISSzfgMD$`}mudb?G7?>X^fTl;PHvZ!)14G0vc%2#TJQ4)0yZMsFnZv>>FlJ^+7{o(2O3=5Y zX}?$I0VusKzM;D<@KF2QttY8lH;cgTwZ)cIi~OeVlJZ^mtv5dip7c{7N6i9h7UHz3 zuSX?n^S`u0fwGj)dgk(PRVGe;=tb$-EogQ&uog0qj$_;{_;%ZDi+T60mPexoCxhiF zV^HF2N>9VsF61qGQeJ7sUP8{ zpg4(+bigXjqKuh)o*4c%>%n8KxCsy`rq;UQYOA8CLe46ES$v> z`OhR*YNIh0Gt!j5>;>csi5fW#dV+NN{V~h~SbcReJ6{|7JLrZ-YWQOLsv;MS`;iXKe6XHEPnV3ln~I5w5hqe~ zag98fvw07B>yq64@N^}D)UE4u5=wV>Bh(6OeGYl}OaOm4udKD(j;{hZ@l)}Yo-`?l z%_#)dlL(0ld1f)bQkm^fNs9|hNPzJjbrbem8e8(qtJUb8FPK~93{7M0roqgXpe4nZ zYo#{EUI8aLsNwGt+`y`@2{QkY(RTAIQ&{ByV4KbAP_w{!*$kEGfU)4)A4fO{;nx z5K6CDn2;pU9>Pq0w1r|Ye~ZX;9qsv0&TLAsQign5&l}ub{3N7z&+{o=)i`UtUcJ`o zr$Kq+>8)xtH>$LA@AaOlq2LI@@cUuT--r6o3p|3RE@84#LhV84jw>du>(MG+8unwq z8lm*u$ZSCgFV8fY<35>kbhmP7A&O(bb()SPJ5eYZw!g&LXQX1<&3|T+W%ZV5bY6G< zmF;HDT((Ks*vsAAYiVxF-qHb_K<|T1G(@6`RANQlr}c03YbEmm50)5QxUb>zY)O?r zV@juh)F=afL6{amfRbw)Q~HW=vc+=1qm*`1l?-nsYWH&rNewawd8511XD(CWlJ%wBbsVEh6D?pR3S(gMg z!VB%Iy9DPm7ib^Yhuui+dSl~EXpb^Mx+k+=>XP2#*&)GQ`Hz#mq*R~qM=w|he5j?( zDA<%6beO6gP70_|T|xGdbOg8S`)Z{-5%*@R52RGtUwk-z?m4UDOi;HO3clTw$YWPT z;eP`qJsp9Xg{rn_;Itf;!v(sQG-lw+^hy{12%%sh-r}-l>-}|a8>%g#BEgui-;67R z>x;b#{YiioRP^}X0TBRHo>970Fy9ywJF_oT_3J1oM)0>LH1!tMFzi!^5S;4x>h6?t z>+F-1^OlkN6>A{(!rZfUa16_6g#TIAZ^YB9m`HbnduO%1(1OD{pm>FSm0r0HSDrs5 zRb1pE$8~_yCglK+xBMzn15V)!2rjDZKGNXPxO~dw*c~ab@PI~pwYRrYC3fZbPuANy zqA9{kI-7L$<2B?SU_R0$i7b0F*^e|>g^?pQRZDH@!Td=$so~uOUYArs?uN)mVJwZm z*L`gYdJVq#U5XzHpESFBq3GQ4Qb>h(-Ll_2Dl4j|fCpk*sFh_GGF!{90L!2yI~OQE;YSW_?DVpK)4& zC`PsV1rmw^W#?*C)Jzd1_V2c;?zN~>{HV@gvAA+9h&e9;$tndBR9`B=Sk+!6KfS!# zQxyseyWe?MOI5jSYo_RudA>Mn9zFK_&h{7G2Q>P6Kw*DkNXU*m>#DLDZ<-kKdaP{E z#3>q9Ng9SNTS-a|8}lB)yMYeC;Ya1daQzX5Bh7_QmR&2uqGzM3k|2r00*Rk-d0rvJ z@(v<*CT!cg+U8BNppfLbenWW+_|>OO=Ix_=`A$Xu6hI?sr%Tn1AMT@nEj-$rpW*H0 zk{_J34nJrplWtj1MjW0r8&oXDGmQ5F0^7K<*|OCp|rmWxZ1Z@q!x}Q$VXBf zra(#ma+&7R9+#t17*X5yMh3gs01x{+&`RwC_>{}ke$MD+>CygumA(+G7oUDxBlRm|*<^W7A` z)1H1y*@PYC%(#rQ=E)$o^n=yEnec1zEn*mftmRH?)S@5KL@z$vYcmt8`Yh*28Nl3c zY#$0#ZH9p-8MAPlLF3uBpL3yyjGWO3vg+jBf1YmSkv(*n%e_{Ulk|$wodnP0(OVAuya4CMl*|O+( z4wj`M@bGxq$&pj!H!X=5r=<$ij0pTkc4v<&A8!7eX$cBV5%olk&InJOikuRKba9QF z?6J(9kA@@9o@w-02f_Gl+=cgLz15o&UD8#?m_1^@gzPyPUCa9dKoE!?;K_baCS@OZTkcw44E zgE^$_ne|FD$@v=AeJwUQaXlWUlICOTY1w*r=f&Ee=ZvLrT&#EJ40%M70 zb6qeya@y1$ItqqjfI;3<-SRG!igOxN1HS(OSdd7FN!-4sz2rx!NQDe3Q*>um`Vh)P zHzB7!nBGrXL1d{ELw6{iwtj&MdYfT$MP_Z=>n|yg`p1hv>a&UROZw|YTNO%6wjLRz zV<;vv+nY6SiN~2Nbe}qKNKddRGq1KBMS=`d;ALW#J6>BgqLidpzx=yYK1QTV4)T>N zi8-FVeTZY(#n~yYAgOoqmGGQdKejVRWm?N^NP!(btxzt%ve$Dye%2F!9h&)m9D?kO z1Y%&?m4Py%MLImBFt_qR7tU2$6hk}a{A^!3t5l=>Eic*HrV)I4_pu(DOY>-5x|PTf z45Rtmmn`-W8qDsfuMVv=O9Ft+!Vius)`upd=_soy-qak7%|+>CK;E+7MdRO zM&*Ad*lO&NJ5EK+u-;9P_LZVt&5QN~hTsqS;6Q zVm-5GB*6x%AdmC@W!c2$0+P|1)-#a$0sbFmJy9o6pwL^~#%=gK$|iV=*yJxiIgPm& z6^IY`YrLr6kK>9ZMVe=~!vHj3Qv70`Es{Sf|4OhdM{XmzNMjKzfjbW+XOFSZL)+t8 z*C5o&N;s=k&6TTuw5gFibA^k#$&ILd2?djhh{XuyoTcIGY1sE9;P{5pclN7Q$#c~B zP}2US>i;M@%ebcgHjJYpD1s*+3z{t7q+4KIqIG=NN_PgV{zL!_R`-p;^tn}5G1SzO>J%Pjr*|2w3yTdbx=N zoTB2?Z!Ilq-C+>z3!~^yBF6MCgpDX1DODo67`B4_^?GRWV?=5s2A z2^Nqx>KvtV?xej17@>!u*&NmOe~w-Lj^)`sYFSMmXd`M5B5`8KPtK_&m1rd8(lM@> zzQyV_?2=SEN}b<-90u12_R5sMEDfN^O$6=uW#L($P*H$^7Ip^;3)>CG-m-$IJoUJ1ZJI@%&hI-mrQE1FBukz=J-G2zW6m{&X5OsKTm?foeu8 z&-j(*lN1Y?3~GGEYzWdhzy}Y@$@r1A8jEyT2x@az64(p)y@!~VFpP#_t(8VGhRLDe zFE3tDXPxrXjt{ZBbnqPGaR;?T>$+AcbE*=ObxCPG>4#nOnYAR9s4#Q1NzEgij6(Dd z)hxgwWz<9(ptcW)9vxurg#~vBwbgr^i2Y-bGA&|p{k-{B{%WA^O43m+ntoE8&BX|w zB@aNl9wa~8|9<5pZi>Tzw)c<)f9aC>Oth)S{B^SMQh5G}BDGF*pFPo5D#)-SdhRs; z3B;`62mj}QV?M37U7OVInknRo{sH>}rBcK-J*Yu2sa!oB@DT}6Q9|0npgM#Q^8_W4 zvDoFzQ>L90=l!E1hk=gtR*dT_!B!Ei1@#}AlDqAJSoh~KZnbpl)AHxjbd_E~rm=qv zqc>31u-5#dVzcQjCl{l#CC!qvnB#EXmTvGJ-0ROawn^FvmX=R7O^afhLTI+z^ zy-70Hn&da?jS2PZY_7ZKt7(S=xw@6MW=e)EVxxzgAh=RYYjzwReCh0q!#rw?ue;tL zy$6{qg26Y)XwNKw{BxTw5bbo_P(hJ+_sVI^DcOQUzbfWA|DL&TR7>bThVa<1r4phG zU0f~l+!rG$*d81IMp;W)4lzg`H*BF``#9lQ#VL4$2am*k`JS*#^GU8Nndg{ ze{~#vwF)kdq!zY&<|7C(AR1oHE@hr?iM9J|Z=Y-))s%JCOdxrpJGnn1I_Y=FK5i}| z*P)Du>IogyGt^OWDC`;j$}Knh*wF8cYhl2>XNxLq#3{}l!^Y@s2DJ=T63ElY8&3aI z{%q?z=?VWa0ErQx{q~>3Y#<$%j_S)^c z2gWZ(>8z+jBRK5dw>-}0++n-X(4wHJX@?lBge)XnI+u^us;C17i(iCfQ`(_ zQQ(SgZcq1WL-7TlTkzYn_6=+k)f}-LBh8dZ(o3 zL&Rb*)NK?61 z48zJSp-=0KW~BLe=#5m5W!t?qG0462AL%Lzs!lhfw36m~Vi)p)V_V@LdO2#xMp}A$ zY71juV1Ks{(ASH52)_@GcV^e8W9u~Zv486B#}Qm!_15<>+!cJtNL8Po&yl~J+vR{A zI0Wt8ALYFhyO)RHD$8;h`Sfb3e3PE$sC^=JATt271zbB*#?7Jo=M<`&@ga&IQh#uK z$+kpXvIkh!GPO`MW4-;*qtD^{duap>@s;k&w%sV9WxIsjLfMBS@qs3G8qPn^7Z4?cU+e?w5$)v|yLj3pRUW<3fv>wRk;>1nM1f z@-(YMcPQ#fDV%S1=GxRgHx|UQ=}#5Q;7DO|e(lfJU(a)P6e}$5#&z9L{)t;xTspGbDQn3acWd*@F6?}8TGJZT>Y3j$>jVkihJ@6?9%R1noOe!zpBa9OkiPi- zDLRxu{8wjM4l}8zT@Fy2*T>z3-XfB|!P@ok@_S{$ zhJp^!&7FKiNU8?=ckNYg@+JJN)EXqH#HS@LzxMV!z|U40z9S0E@98Pcv8R6D}^kymSQ@%-SC zWS*gVeR-Qvp+^k+=V;u>r)Tptj@0J{*|6g)Wquv#dYW70MoaCF-e)27XeTYx>t?#( z_GWT>@grN>a17rW^J*>owrzR3#+|i4mNa0a$K1A?{1f&GSMfJ|{0UCA0sz<9F2*x$ zZR(feRiWIq;>(^|7vQGwQQ!IVY9cP%92lP4u`LXLL%H_*U%wxXIh9n<980nbQaQST zdAv=wW`V$Y*smyWIP`M9p+M`ctz;4lfHqdYcDubylXANGfgb-DIK$I^dJ^cC-+u1r zBVC5ZtdFi=y~=xUFeb*Qs6{~U_j*RN%$_KkxVEu1$ar*NW@^x{6{L)J)N-ZWCr__s z4f`$Xb%D{{o8PFiuUWRs33{IrpAt5goS0&SYTw1avMU7i2+8jw-&4SADwZ=%lIT@< zu?yqfB(Y=;X@X`PCQ2G_-Dlgrrrmo_kyPh)RwtQ4u(uCri>H2FsbPeqa^{*B`a6zOVkj#`^1?3 z_S3`P4HR=r;g8#?;-*tBi||8OwSOn#5d*|8pAVgtM^ZR}oxvgx)=oYgh&5F>*dX1( z6~;{YCzp^pb0eF+e02qB)~EM>ueSK9p_cTWLqJ(LQjFUx&A-k|`PbsPb?*r2AZ8A) zNIzP8gPx!J@baaJ{U7sw6aNkOEh`EK|8i{t#caRadQM4G)9-sL=uOn`S8eun+J)}} z8t7J!Xt~-SQn9W;rX`2yZ_&&KSz-I%?-u^hGDoPdmBXUw5&*_$@#?W}|1J{c+aq=! z^#9uR`Ir=1K!J|@C7^#_jTvsiC?R-%SURq z7Q2ttSA-pFMs)@3wAtV^{ntrF&2<;jDSi6UPNbwP^)>n16ul4X2%}ITOGtY28E>_( zIgmPL`sL5KKn54+?UIV6CQm#c!_~eEr1?=`(`jEc&r0b=YJ94<`wK{#!?y;DxH`bM zBDrGfMJS=Wj{1%J5U}ag-m1H#hM>Fg$Pu0mi{aCzX~0~Eo8rH}xn_A{i7D|HX8u}r z_MKXPkDBLk`#h%WAOVtiYG};wyZQc4!=qQDVjFI;d#-#2w?1A{{hRmK1i8xmMoS?a zU@%RIuJE3F-B~<(0+lqAH{dV0@%(%C&*MPNosCXq<*p8WpN>kNa0}})ww9tEm7Q_> zEL&P{SG=bvS+hS$YvK=r+xNH0p!ihR8lNuL(aw5|@%w&@ulvVT^`dsNRn)6VEivtt zJ+^Rp)GD%1i^EN)BgZB8_^R@GrXVM&!IWD#J{oXAzbSkp|SoVE)AiRChl*)v(CYydL-un2D0lFDLER5MY2MJh9o!$FE z8={-}Z#P&EzCCgw<(3}$ylRa%8DZwTAgD)n@SdR8aK*0&y1st%sz-HHB%kKp?-N>! zyY#gMdD?FEYu^06${0R?zDj5;Hw_qwx*9?|6*->Zn~-bq>AFz~`efyT(mC&02Xl^{|)$~CA`p57~ z=Z|*MPoPs#Thg4)!b8wQUothCH%L2%{OafUVKkGM~9`k(yA2l9tSK}FtvJwPUk`hMFgDR`XeXK#)B z;`D+ZW70?oOOl;*iAI4y*37(}yH|6~PhI03%2PD|KJ#18I(m5P(4>BbFx^`=iu%3N z>v(LB05wE`ZDU4CZIn>>+{xehq5aP#;JU707*hOP`=rq4W;_mZsJwZ#%Go!jfYY+e zCbvLAzIOERmFs%wUf%5{P6>P{$i8_t-|L9B6Hr`wvtcatTlI$*@H}pV3(Xj;@-c^u z$(LHSTBP5Z1ah}<%?UuaB2Tn0$Ffn&JdPHEw`c>30W_RUZftODI587{=t5nz`tx47 z%V)H8H8o}pIFUN2alKb@G(Jsrp~fbU`Da6;@Z&E91+x5a27g)3xUEQ*+(Q|f_jkKu z<4&eBXBrV0IrcQ>)1WtbRE7iA%7@PxR$(Km z+m`@;x%Av$5mMC&&+k-oAs@L-cjBD|vHl8S; zsih*Ax;rWMqLJMxvZOc1@||4|9I2Q_V!p zhZhqmT3)L;rw{J^(H1HV*)&L3Lg`q5EICDE%9#uDT*6EhTluZVNN}CoCU$8FT@TEi zKRP<-x`Ql#$GD}`I+h29ttDlu_9xYYsY`n;W1@7zcdc3_uC?4Q=PS6XKSC$h#l_PC zu>ibFf@qMZ^MlPQrJA_ll7@-d%_+-kxSi?BGFwdlyiqg0n^(so%N?`R_rhK2!V@>t zw8WsiG&0vHYEv}F{B1;4XJXUu?yfwLwUtj+&8)}w#TH-vyVQRSwjn=D{6IQsuE?<@ zFt&)vB%mwXqE}?XAy;HnQt{<{5wl3aDin5*KjxCr952-*dNub#&72xj+Dp}|4NYml zJM%%+zBaZY*bV#|#Id~S0d>319~Qo7eD6M)-}y3E#Hg$3En1V~W#Oq=Zo#U=CXk(M z{hN7_GK12L@fn!t_(naY9TVDYO&{~9|1}$vek_TOj07$wHV^kHTu$-h2dds(I2V1J4I-=2cPdWY z`DT;5ceaDL_Jo2kB<2r3T!kW zyuKGJC}wFB_2YrqitTXn7FJLadL^wgt`dK*Ky|l^cO+&aj3i`A7Nsc6cJWj0Dd!b7 z+Q!s{;1(T3Sx<;}3s#={8>9>gU!D$d%w6rMVt?1x4{V$rOw5~5J&KljPM_mV`j?6{ zrCyi%s++6A;iP7k#;$bi(22}-za=A+*$S>24$N44lX04$k@RlYzmJygJ9mIcs#AZ0 z;CARJ_}T;9T?6)w2M;P%mrE47RMXoi*QxbX_4X&E(LpR*l<5H{-DVf1$5yz$#4|~# z2Kn98ml1&{o$E3xX&YMjREJ<+LW-Y<(dJ^A{AeP!3)>Iaib}E zf)(IntafkTOxQ%STKzICMb&2AY`mhF0_Aj&L>wfs=+ku)j06vz`TfQaUaC$FP!qgPNu#xD8~b31ItRcBn1* za|e6JN3L3De)q@Hgp>3n$@MpH_wb2qY&lM}dVhFs>Gp(VQ~qqbT{ps2;}CD0Zz>Na zD{9$$kh7gX0&}Y54yzN2UY{#of!^F`+mg2%6bR4`5isi+sRHMV$hT+z38Rm>(nD%h zxISdRPOFB;25i6dKPWMNo;FmoBi-oB%>#E$7zJTB7KKwbhOIV>3b)t2rP}I(tsQ0* zzm@U`Rmh1fL&)Cn6fYd5$&W{R1 zgPZ1jkh=?+(Ox}@PhL-oabtvVJ$ zp7*Wp>j`Ztc{Y-6y2UfQ5D#!wMj~M7p`7Gxg!;<}pp;dUWE~!50LEo)_^HSi7Z>CR zT!&95sU-)r)NSjo1*LWciS=85uCEKqApyjBucRDR>*2L0*FRTNp%#|?acNAxkt-WD|OBeSm)m!y&sc-oBn;tjC-fDS|!{z7k5-*`w zEB8C5Z)FkLH1)E5rbsQ6H2068b7^N|zi?EX-{6=6bu+YCC*AQA;|--ClRqDx<`T<8 z+B^$F>rj-{P{v4|_GYVKt+b*B;SNP6Z$14I{g(LlpuR?j_9>vQap# zEfDw<*%{iP@p8U6x65_Y<3jfZutVGQ`fOvPt|zGD+n=p^ojxH|-_SL9sqX0y?URH= z#TgqU|o0h^Igu>2%N#5H*-(O7w{nwzWy>(%L5qWGR zj>S}{$ree|oc$W&onuDqy{%&z(=D>kq}4c8C!dY*GW4HBeg2vae{wSvGMal+Ph;id zrmto=xvAV);FLQY+v#js7=yeOQ!KH+h_C*<7Ht5xm#`b==L>Di4}GQuB7MT&Du&tR z{-`X5;LxpgV!sOZM<*1JN_1>w1ngB?p3ZgHz|S9+Nn*;#_ePuI8zNz(af!kE@`D1< zHn&7jF2qliP6%KlITk^}zaP+h}y$GHpL8)tR3$@B><~c&8ytofM z*L)&DvwEXE1Y3pEe3tORntP(2DiT$V#U9CF6Qz8HTBw zoEi-E1eD2jmoVZS!jj+O%G)bOPhdYmy?dO6juZ$Vs28y(fBayrC{g~J| zE%wY!yQU9bkPq`ZnTi?CGVdR;PNv0}9foYQ&6j#*+6fCwDCmtwr3hMyc>IKWCwms{c9isiOg}qH z=lJ%w@HdV8(K=T63~j+Fsm{ho(8>qeL6=M4vOpAC*L%l-TeU-FrBKDl;1e}%NmAK@ zUOToUYTSo0av$ir9M*zAt@J@I03< z$H-q*c>Cbc{&%%e)qoD36Mi`^m2bq8;MkHX;+oxDjlQz$Du-%f?xc6fdP6osHl;yYtZp-yKDElgbr4VJ9)oGfE%rSDZ`M$jOrA?R?pfqig=!N z%k}(;-pSC@ZhOA1wKQi44N0^LR>rqB!#`KawS43+n6e|ayT~*_2sLvktlW_=yI_?d zlvRR|%C8*Spw~XS6x-2pM3In8PTh`Ut*MuLQT5X$C75{z#5o=S=dR?MHfYWADRY1V zvU^FoEc?bbnZUZy7O{;Ll?Ma|=&*W1)J%}R$PA;dj+P0Jm-5`t%>ot2@YVc~YYGu2 zP=Sm}7YBs$XyI6(s@Q*Gd0Tt<*{8HE5GdQ)D7j<3Kxsho+hywXIHh;Z_&*J6$hG6vTDd$$pgB-Oy9b!qU0Kv-X z-j9+!7ypRLuW`q0N{q&*pOtZ>*`QH@^bIrg5QO`8b`J2Pq(t+0e?iu}0o5wWTd6sk zAD-4s^KX#fs!}AHh5zQ}l_oFR3=2HPdVJ(^sOGbV2MTrFqJB`MI%!k8wZy$tY<(-s z1_jLRAHuJ9<}EU|UVrijz_O_2AG9sGcezG)BRhXgHsfj{6X% zAnQ0Sk#XpEE?!TmT2i$P^6ZnZe|KX-x(r2Rf3W{%$Mr=`T)yj_pO@-0^_`6uET2UT z5#)9TqUd%h#_=(j(2&`P1WZGQiQ29s{oN$6>@v^Jme4>5%nxWI)OcBh6t zDa%zw>8g5(^j!J$9JL8{K}n$TFYpn%QfO(xQXL}SR;}gq8FL}C)8l!Et-^+bX%cX` zGL|`*zB>GMW{7a)o0Rf#YnU6KIqmk4e!;`9C zF?TQ?kiQ9UqHM|&idGk*KCd}*$Z0I!PePk4$nskKNvm6_(0Ei*TDYrxnnUwy*SYU0 zzoEvS=KqM|F-_rlHMiw`VqLUg6FShur*ffPU4UzCnyd7_c2Z;ZuR=u(5{X19tXUS* zca|InR_~&emigIiiG9XxWF0DXuIQ!Rvoq}NY!!yDdPW>i_t~G48+slKEck#4O>C8b9yw`*xL;R zupx)`f~E z_a9Etw_Qh(1^_c5*@?A_ysLN0a}UMnkCbt5Uo=qf#)(R%d{lkCSElZG%KCqcF@W8f z2M`KpdoPNu-2shWa+In{NUV`5LXWv_;#_(Ju9|2y9ohd%eXjCqmrMh>lKvJPECyH? zDaIRg0II6h;rS8D--a6|M6Z?LdM1p6&9ed>%T&{(C)`cUppGU|>O1RE3L(6-sR+Tm zNE^Y9@>r}dpTw7p35%GJ?bv#!ei(lbO?jp|#0~3L^8`G1z#lA8M{Kq1yC)vzMf6Ut zESVGZrH76$shJ=#B(ON7g_VmG$Zoz=(lWK?4f?D!(4V#q!~F=!5`c@8Ngma@R82k0 znbSM$>wn6d@LU~36QAzB8XS9-a`_;%3F;7@Y%r6Hw_WO$vY9eW$;5Zx(yeBuFWTaw zFl%755YrouP8V}{x;`~1P+%fzn)ClX+%xjtY5n@U!QMWa-uDdS?&lA$dH#7=HDxbT zaPWCftEL9FLHbR4hze(nX;QTpuk$tD?&D9*_8{I};11^J>N;R+Dnu;c3B}$DvKcP+ z*EmzIBVV7=Ex&JL&*Yr7y#;5cWX6e(^tj-RL$+%DlhqE>pHiFQ(@zh%9F^Kq=nk%d z+-K`$8-F6*y4LqotMhV-{ZwNy^{H6dtjwU4W8T`r)d($*M&zW1I#O;S%B%X0-j$}v zkYD@lz%y~v_urciZ_cfhI;})ja*l}?4PH2(eijCN*U=0ap81Z+0Y#+E?OwY<|B=q% zx<36{cXI=eH#HCm>Ys!EcuIdG;+Eo2T+T$i9084B_H81{=ePc~Z$YZ%oFzu@k`gSa zZ=!CO);KrK(C5*Yytf?unQxsBlpF$j#x6+qb+Mi))Y40xMcXAi6$s;Vg>Q>4N4GYC z14x`V0X?L%PN~89wReU|hKUGw)Sm3_W4b!YGH3BCWklcmt2~#W=~&qq5w-PzX+g;n zHuKX&fwQ#xThOk+hK@a>0P#p z2ys=CxAw{BeZTHc2E(8v%JbH(zvXRz{@7?8c7N8vgV35&2E}(zW)R zg##fyA=@>YKIN9#&8niyqRQi_@D4&{y0FapagqDH{A4H zH4X5G#&KZU7s=*FR$jE}4W4Jeikb4g^`Gw5*F{~&YvW|Sv-*|XTBX9L-Vs?oKcr@o zH$(6CXPOFi7Y6)o?6Ysl)6<7h5R$}N|3GH?T2yd-);mt}0MU&TI)k|J& zbhQFYuE_SK9oo22$*^&M@BwG4$ILs=@)8I3U%)H0-q@>j9J=ASkPX*KqY-@mTDySj zJ2tfb(OOc23Vk2nBV&>~*}uI|mjT>mi4VV=(QZrrO0` z4g9=oi%!l8bW}|kXAe`CE4KCY=&W01>q9Y(5qUj}c6nzXpa0r3j1^W`HJ{ZHnRvwZ zQ7gWad3le*30O)0kcU&pFfHjVwJST=gEQp@@2)RzhACl&25jD`jC3o{Irc4DRmP0h z8wOMx?GH^ohBn~9qeWf0H3Gq9mCCsbajVs+?=T6X_iPbeHL-6H``%bQpZz@^ga)=H z89XMh^B}yH2Wgkt_M7>Yn{Tqt%h7!&5ygQy8p|p4*jCA%bvFbsIpi9gE{lgNMQzSW z`i(`(t{ROEJE` zzT6tpYNS|-l}5B>3t}r*=q#RbX?hS1px!BER|@Rfk!dG8 zDf%o|=&>j-gA5SjMf5wn!;~KKg(5fw+k@3eVeaHMoAT+UklxFl`|%raZ;N8=HFrISCQam2gPI@fZ3>`oo_V?^UCtENq+aP1mfP4);CUeG@4miY zKOf!;u%$*kn&cXTc0gXsOgBW@B7>)UPE29SKV^Wt{ zt5?#W1KVNZH>fXLyT{_}mtVAvAR<*Vt-64&ftbrPu(|HT=P*jFrKvyr$KXD|N>2f? za>Wp-+l@Kx`Q#?c?L{b<)J(uM*XJPW7U>C?`d^~3yVK)?BWNp})1EY{RsieaQ#eZ7 z8#O1r!=VqQw=LT)bsDImT2NuJY?4tO?0F^6!hGqQ-rqAxgYB`MI@KJn)7)M*a?^8H zyb47w^Wf;|O*1|v^zpwk_N2?!m~3|;j5cba|Fz4=7o%UDU+g|Mf(_d-8Lco}syh~dj8zn|1 z<;TLf&JQ2T!iMR&=s4U-wR{t>oNN9uJ6{ih4_{{?t5@2wfinH5`eaaAu8ENN($A;#? zb`B+`m{3(*vC9_tMVDw4gHvZunL>omSNe64d*-vv6vQ{zD=qZp8eOOq@lBVE-M<;e z(hB^`rQ&aiz~(~s%tcb5F3sDyPkUeK3Xb62XvZ(2^bZ8-d`Q6xFDuTcmEd!s#7_+e ze=hnqV)9x5sM{Ug3Gk;d_=K(w=G6ZYuuOfDPi&T)r4|V*&ZE(Hhi|*0LeJ_B$d3ES zJ}ldo%Ev7g&g$!4%H4{xw|k{~2gMJO?&g{taJDX9$YtwPJ*{ty7`+rl0{raB1-!~Np znx{{+0#V*4|4q|hv>zI(J>A9gxa-ywMInNg5m|=7gJo^}r+hUooy3X0eFO{>;rm;; z^3~VGF~3N|+t@n@FN4mavET#t6INY|`)cD*;uJB!b(uN7802~`4FB@Q?xQ}L@g|E+ z!hZ{|7?k?MnQ1Ip2k9$Lsftj)WT6|AB~wjTO5twsboYh+%#fw(K04oyb7;#kg8ubv zPWsU9#r7I$fNHiq;8wPvj+{ClXCg`e_Atc+35#x}M@jbmHN_i$(JS+USmikss9XtY z8+pWDe^P z3l}cXY0W5a+U3~&`8B{#mIA7vV-(yovF%J78TX}S}*Wgvo?a_t|3_H+k7 z`C*h{{j^9@pJ@Z=?WK;@&GYsz!#MOo0>`wQ$c3pBj)2AKyr>=RqXvtawaMM3P;k55 z8FV!^1+Z`ZK|`Eu>)CxpLt&*|)7v~P{M$^8v~))cKCI=|Iere)oWP*8aIP)DzPTT2 z1bO0o#$MsXoP_(U&w}c&zme%_b0RDa>@Z=A(WQ+88IHT-fj6~y&-(i1pXP0*A5X>x zoUcID8A>l(7yR%EdY2XNc;xz<>-p7?t|zN?N%9t}v5(B{qrWNU6G$KU{Z0cFk`nf$ z^$sjX+F{O?v>PB)x5N<*#4n4dD6LnZ4h}WFLvD@_vcXG5Vynq?%^SuN?0m>am)iC~ zAqVq_Sf(hoE<>r9Ts7v^)?5qx5cJKcSe8#TL^SR5ow_14bQLx(zC?0% zMK^VUvH$&%+y$Q9FR^i;(4mqGzTJ(Y)Z_jiqP-i>U5Hj2k9DU=2A5@?6j=767s88 z_YU>OpA9#IED}ODNKWr*(Q!J0gIVv|$3kh_guS6*e9~z*3UH!2)ge`N7JAqdh8mxb zr#$=mg6wi@-1ql7AJV?)ZKud8ayNmjMq$rwWOEt>Uh~zk@h%%sgn9dB*+n3)2eiDv z4{v%*FfDo4^9~uHTLBYJEzH9h2tSx-C zB6x^m?B8~OKGP!~Zri!W*pi_a%EH7H85063@#HDaQ6cfX!f&CAuoKO4-H)J6Hu2-z z-60Ud(biEJ0xJPQO>{4g7W`wlZ#5OmL}zFUo_G511b970Y{zyY`Rh(*z5@r+n7H0C zEBgFV*8R(AT(=XPvo}-RIZraF>HnYf(95%wZLRa&9dq>QBA0!v`x8h5bEY9g)%d%_ zf3p6)b*UYBn?(|z98$Gv&7dW{@Q92$`gci%RWBYfgq9=DS{~h0#(}FH-qPFgooMf! zbZ*+u;w!W(-nKIDI=ok5uMbx(;a)%)j0_=(v8u4Dn8ZC2Oj`jNUMt&8Jdsu}uE6f=pmXuGt4_9b z^tr}7)5?Mvap5uIUFss3IgD@TxVE7Lo{VRWLU{7;DNwp|B-emvB0x$$t=e*PINrN7 zIY<$VyZC$Y{G*<8^+3Q=vhYB?LruBY}i%3cVfAINhbn#|dl9z}z z-#2SGVWFs7zIIw*hCe&|u|gE=Gz+(dW^VSft8G9n-cqpyH-#}qWbl0oW4$U@bcBCO z#F{3Y&dX_liT@aC^h|P>(`J8$M6z^`D2b4@POi2WUulZ5^f_VJ_ofHR_WnPCHR3O# z*gH6%FLb0EI6lK9@L%LAe3xS2GlFjJ2>8cv!<-o;{-swdTPojf`&oOhaEbVSb+26! z(>aZIw&s<0>G4C&+~3zc>3=aINKtB0)E&W3AEH#;<_K@abm=)xAhZ9Hdv8UuKn%|$ zSEL?rr?Cmm&DvN>WjxLgtx$bfbBST|qbz$&_L9BlmKQ>;=9>Xz!__bQv$IBIfNp04BD>RV=wRt6h4RxkwadiTFRv^nNaUyxnV(FzNCT~Dr;A92u zA#m~!hRcIvdS)#`jd;W5?)VxR!Hs=dDtUQitXWRv?n^j}*&{y3%R5-LnmI$YJu$0B zvN~EgVX5BNXA=;7GWa^tS8B@h{q#e4Qo9+q>77qk6&jBj4>Ay*de=cAZXxo&VU;u{ z)Avz;@^Iz5_+6KW8%>wqEMzNG7M-saEyARJgN%JqjHV1s)cKfN! zSJM3Y(hfYZsMN+(WN{V-)XrQ*;5KG+c%MC}nG|1AT@zTFYp4t*EHr6oOx3@6s*~#C znJht|Nwq6y^=xiEhB_MH+N5X5DcBB2%|V#8gBJFA9f(6xG7A0tVfB}=-eX0QSluLe zVvCE*EIYIr;ZSn_(ZnTu9@5;eYBusoxm$boJZ|qWeM$QDKD*Y^EL*iCzw$y@8+>We z*{9g(z_!7IsMKW_7?Di8_iTG0KHL?#22wobnX9TZxPcC8ANu&I{)xVNP3gxlf*=R$k_&l$u6wg_3I&B#S z#(})me9Pi2fyHjKPAwP}xuNA{UmSF7Ff;;-=Oe%J0Mr-9ft%Pl7PhTyqX#IKm$?gu z_E>8KTd(S>n#3-_V*iU3R4hhaSn)c87=}jrDP?5O4-*$KJ?U@tK11RDoBRz$-s|0G zQkZrd3j4IP3n*{r`I}d6AIFy53`olE@_500Sq##s_Uw++fH#(zPNIv_Xq}N+iMU0h zKXninZp`}US3Ysp@>+ho4967NgKREE|B>${&j)9g7^zSVg|&2)y6ryKCzWg1GkVJM zwv96@Z~x;eos9;U%RBYeYqT=r-U&75kuSQVCG4e%!tH$j7pl+4V*b!o z%ge<;cHm0cKL&61q+$*YGq$eMXy;(C5C1dw*36kk!iDO|ms-C*>Q1hQ9P*|^ps8Hr zdp=f5vl&O?y>u?F`@0yW@cO>Kxi-hr(rv2|D5K*mdCXHHAj6TTEiA~}TjpTzs) zDgN~(V*eO&b3n3ifuMIO^9ZLV_g(E(U>bn4;~p$rSvAx6PHvMV6k6_qf93h?iLgE` z@b^`NTPey4s4jGZaiS%^clg|m73C)b8K8%Nkajw!6M6lnCpkVNE#74;Sws=-5StLV zXMZ)QC9HDJGX_~_<)y_38N-f--6CG%Qp}6)>=?({4dB3NctE(QJUqgo_@X_d8htQfEuWMh|S9OJo zxP{s`uYc4}hIc){eQE1xg6HvOcMJ;|r`IKcnKPeey!B!Ozfw;N1RA|O|d=Ar`Z5g*}X;FFBm?%u}YniG{{hYPkIm8vHjv$s~ zuGoOA8)Sxs?+RSV-opxdmKl`<@>i^}{;HXAeT9`LfqMiB{7pQ4MeIIUjX6xf>OeCO zUh2uTngkW;#!49O;9;!FuFmk#O=rL5s|IWnp7nN#H|6;4s)(b9yf(>1!wZN2{cp9O zcig_lkZ(IwFTJW1uVkC>5_OW8Q_@Xbr>l^^6CLV$hMZGQS8E-0fg9D4S$pNh6zwl} zAl*|9csEWTj~uJt2xU^H3o3V=?jed~`GwFXNZAfJXRIWT!e5NzY9YUl-OPuF*MPe- z^PCY1kEMm(EWx$pZn?k+HOZkKs+W|Kxpu1u-OiuNXlLmR5YGvE($j}aVY%&ZT3y!t!;i`$#=$B%Tn;v; z-{>*y?adPmFHgN9E6dv4@+=lp(B@GuyFk2rlH=UUZ&$g~N3(x9yDg}soXh&SxT$$h z$zNjo`lwP8QX1{C4)KooMIUxqkn&{!WrWLgIpvd4k(g7ThR3^Fewk0e*d^NSH&acb z4TgW5BZ|abSU&tvKzENH%K2lZBk-AewlK{q0}&qA;IzlXouR&hJVD}og6U*M@xW64 zYrhe{hRA}J1~&}2Mb+yj!z2TapgHhSp&7U5+gRm4W9n~NiF(XM*_IwCO~_@@^qcTc z$qy1aSrpJk9W$?^tMf~OaNh_lWN9s%OQbYV8>>L%REEVUm|v;lu#6OL85u`@yr!OZ z;;3hGc@I@NF6m%5EGpINW{lm@7BQY#uHkQ`NF2UGVOM#1tE{8RuL=328w5r)T`pXM$OMKyPyk*`hAk#fI zH&YZFa&`FgEyj(t9udvUYro7FN^_L@7WFH7?Yu>kMmj$BQ2L5ZykKnu?%lXlbhw`N z_e?&Kj8^r@zc0Xu2Qxu7snDFLeCQ4|Lu}pPhD1kImiSl%FNdD{|{mk08ca3t_>$=yMf$%7Ih()o8@}% zmrE!NRRy-_SVI+K4-`{$Cw1GCwJ1MFe*|QGyd-*H+|`iz@Z-=(YRkO{=f&}?mW`~l zfT?PmM(;|A-kWXB!hXUoA#N{o7Ha~T;Z9GJt>HMf^O#sP1)QK*^ANmbrHIC zaig}dJy>FQr!MYipz@ohR+KvXY1MZv`#^O@S5g#g@#omJzbY4l5Uo(i4{Hk zPKDoTO>B+oHF-C5bXT+v;@SwB;li--`lW#!)7-F&?nSbT>;;rjibhz4kEP^>N1uF& z*o?zZ*B8_ui}=AUV_6BTr?b9`LI^pCCV zl_qd%m)0xlOz|Rr`cNNXv!&{<1Can1dfJ%M9TCJ&8PseMnOD-PV_C9>4xYfqo3vcX zPXoi`T_aem-s-Pb{%JmCi%_hudOZ{R);=w#nQj@mtfHH|0p{SgHXwaw3=E&Z zlDEsrtY*;al*%BLk*aF&lKkccW0W)*0xD9^U1iV%Ju4@QNb>&O^1;dUVC|WHBG97w|aIHmctHn z|L&5uPyfhQ-BsC`z{|@;0TyL$4W#d;4b`!dB%9PvcZb)?HOUr%`cK$yxgCm`!DB~8 zc!?@972gM=ub?6?Hnlt==ki>a$-b?dQn!eeOznKI)?jtvz-~=9VL!|=fow_M-3z$x z(LK4YL&Cl)JDc}h3lKdLnE#>|uxZ==d2_K&0UGgY!&!=$_F$O~qpHQvS1VyZG=8#E z|KK<{(P9XtlMbpxuQUv0t*d1kWzAnnI+9=1khFSMxEnz#lL+@wfL?JLJ1(QvXz;du zlFiRaZJc*2vTVpC{@+4o^+E1d^J1|{_MbeNM8*GmsT?&O5kyHckKeu0X%`;J?cX+Z zQn_4<)p(Z-wdm+Bjb&j+cB{F~>cj2&w>F`OlZF?J5p8U#Exu|ZXKiyTyZ;ytu2}8I z_F@GV?DZntgUV6)$)KVe89qz+pQMlDm&J@~?bAOU4ZO~lN69CLhwcUSe=V?jKNDct zVD;-SJHknj4zK4=yxlQ(^qU|x>uAl0;QwHhzz|`irt14}Lei^OT;(5wU1?O)KF`lCz(K)-=DO9+QMSfiv};S+_5@e(^?Rt;=-Z2S z=%&|z-M)Q?DE77Y?bA)Lo2SM`Xe9XiHV1m#kK=s*2e)%Btb>~u2u0!52WsG({=QNe z{+EYI$6f=0HCA-y!Cn~35QVu%jOt24_78tl5z^C`UdM#^egHuNDKu?gkaVPEP>T5; zpGe&K4*de@t-!SEP4VpIOieFGvE0~s`5K2X>GhOg^9-cYGFE%b#&C=~OYfG$Fh93L zwR4E7L`Sfq{CBTf;i{J>P($`{B2nM<^tf^!H&Yne=q+T^ESnX_H^EM_ki`2|5YQ>0>>6M3<>O9_PN*d>!Q>|Kt6Ay>@3xK{;< z_0fgR1hfQxo$_TPXy)}y#iTZo$D#62d4m<&=w5-(V;FB~<8HVMLZQ<~u;Nz`0mqeV z)8o^6ICVRcDtVONx`%gJHQ$|qJIagrI^8*61!dOJH0Z@uX*&n7%@;Cu*{75)ID^v$ zKJf2{3#WZ?p%|T&e2tRXAD^hJ#Ta^j|9vZhzzuBFyL!q}4v6Hdm7~}FRzHIx$mut1 zNS=pK`408Rsb5b<7(|PDX1e#E!ITKyF2w>9FVo!Yn6ghd0QVX^FNTvb>0HaPb?LjK z%gAJGy?a6kn`z%`pLtX!vWt$q&C|V&G1@*``m&uIPjtje zcdF3M1Dn0?A_Vu3vUz6uInss zC|oeu*48c8Dr7jWO$Ry`zTR9Z?l(<|VQrd~Av9Va8CGIX-?|=NBmIw}^MGda|H8OV zEp7ce)Rxw)TD3QAwPscAP3_f)O$ceL+L|ef+Evslu_AWVicM`|&l*8ug^d2+|2dB1 z9OsbayzhO#_ul9EJa%q3>FCd@QE#nt+8P09{^CLeO%Qe|;RqPvD;5mY7Q=dkXFeo8 zCN6P;9yeVQMCgpa-sGFe*QuGuPA@Rhq=NlcOd|q{+}M9?O~{_Qq+CA8HN0xFRB?(` z3Y^qv82_2$FnPdtnumhBiwG?`$742O#1Zj)yx(~ zy81WoB5L!t2(hO+$MKV{e*l|zxJa-k_767n`$9R&p0~!%jX2L$6}G_#17bhp?>#xy78Eg~m*<77sP-!3 zRU)!x{+@0BhI2P55majba`RM7+~w4NXf@AUwdnm!{}Z;H-g2SIGqgBS#)RWe*w9=} zrgOZaS?fYAymgM{SYe`xZDoOxpO!3mTu@>+{R>x?KV@kDKtYf{Y27Gc_FR1U&c3I$ zhb>D*V_GusWQksCDo%Vn@9>E;;DTrI@88G8#d;b-SVwd1=DtVWPM_8hdlIKvp-Ed0 zcQY7HV}Hsfw4CAF4;Mqnxf;EQcB`{?rHy-|Yo>=}Cp zAG+2er_aLi0JJ_eD?9I3GshlmrJekM6}k zzJuek6n$cHa}6S;CT$+@X8#dKPMPySama~eiezbnwrur=qa<~=Jpr(u++tqe_xfJ7 zn-S0yTiTB7{(vatY4}XT-iBWH@!I3S&((B|I1Y2m%OtM|TiKD+kKFZ>eWNZ$iLm_F z9plrr&Olg}NFwqW95nFpf7^5Sd`R^R=dPe;o|FMkI zQ~BicRZMQ!ywMWSAlAP2LoVguBI}iNi=2}K zK2O6pa*vhoX2eo;Q^bbb`NXnaD0pWZz&KT?@>#mthG}O(lw)^^jXA~(D;Uu#y*5+1 z5;SYy=(__kU4<)J@Y+1_V@cnuk(J%u-c`8-i-=L3hBCLb|2OjouL(2+LX(Hc{||EB zEB273w{Ie9q_f{ZQ1Tw=4?b`7N zr|CjYc_1h4g}8U)>TmkVa^W}1b~SP2A0E%^YQyC`4DXH!KxHZAW>wJ6t8}mZPRA~v z@+KPtS^}w05A!DP`E737EVQY;1)vCOTnpxIhUS`{p0{W1=I7;7!3+=D&(CH}Z({53 zImO2;gLagb#V=A6S_rmD$Y8%NOYW3q;VA!)Dem`Gw`;sr?J}qZDhkMw$Stp{|O~=nD~gKky2!|E5o{-s{4=OGmeg-?XyaO0`riW*)n;>GN|I5*gtHbtOfd zR}=kNV-z!$X5?v<8b-3Hz_F}C76FiN2u+5)pEtuvuioV}+}dAxMX+!pi-XO{g`rBM z7gKoAX=0;oDAE$!1!0b3(Xz5~Pq`bEveN&kt4JeAG9vZ@w#+C=XQzwBxAJY(bKW=3 zvwK85O<;&s<)eywlB8BI5!#pp#9q!tyuSh(Y(`)gDhAQHq`P|^+#H0wV7{gRaZNO$UvchnBr0b+Ygl=8m$GU%8EkrQIir3PgN*(qJs8E%mm)1d>f&Mc<)r z+afgBa{V8j8E|s!e=|_4my!3Te3vCqp)*ts;EJkXYIaj{nu)8ZEV&Z=%nc^nyaa5S z?*g})OBUofEJwEv(=-|o$6|@n#zPMAd)LzVpw8c}W!`8)G!6s+3umQwOnC91dp3hpOyG?+MD6^f9;f4~e9J~_f_mM~skJ2&?_UBPb{-cv_L92;}ljf~^KXF&LC z+>ksTtG;KVtW+Y}oGAg0S=B4SY>{kLGtVYcM*7Q3$+h$q_!CwkuMA6)=^y4dsypGQ#G7LuA1 z#jetaA!k%AB)=3jRr^{y2Z(@PV+LDnI`igFu+YW^*e?v}h*!JO+olmi*n;_F)iIuU zu(3Y2!0mY{p^Xo$42TQr7nV1=23U^aq)_;>-G3ZIJLEgpXwL*(R~NmT{?TQ7Zith@ z%zlH8&}dcO>Nw-wxq^>y@~VOgoEk6R4ns}MrjHS+ecCoxUvH3eeKoG) z5ISdew5xyt4nz-oNlga35W-{fZ0!boyqQrP!OW{Bj#;tceu!_GL?xdH8>7~dn1+}A zOSIu^>@21liI3R-M|b?QGJWrNI8XJ&t?^pxXC;3IAoo`Dc;EU;+1Pce#iZN)2A$io z6_^+?896+h$FcZnN&Nvnv{Og&RSJJC$&>6K+yJ?_V5|PUJMnRE728eqzWQ^{t*4sz zzUT!32T$ZQ8r$I7#--aane(5F{%wn?dNOy0l2$?+=w4R@-?g<$T;+0Q_T3znWSXm! z&-J#AziPh$Z(TSiX>*Yb4%H?dr6k$PF5xDu4qh_2Yf@8 zg==cn5I1uiwCE8!2XGR9Q=;6?cJ7=aswn{%8Jx2x4EN)D49bF?5P<1p_BlJ8U&l$# zolB7|$qoY-uT4OFGrq2A%*wuGbV@MCGBUaM?z$gEJrDxf!X5x+z7Qr)8X)j+T~Kep zcxJ4cM&R$d$Rr^4UFGRH$!34N=R{ZCAO2kRX;GpaPyij>L$GTj9@Ka;`0H|k#%QvwfuK3ar!d=^w}-+ z;}OE4e9#AlPrLMfqk*L$rrGepbyQ&at`)J|?@2Tcj@UJrj-Tsa=+xx}&jfkVjwD)$ zksfpjT05AKMA^Y5iY|34(j*_T4*2EmLh=C=qfHa?r05)4N5Ce}w`!^GIqI_#iR@E_S;tm!1HczGjMXq5>|b*-(Ou<`Gpf zfE_U6(K_MktG8M^4J*;Y1@WVe!8}#ey>GCwze9yICBq9Rci#Xj;++z4@ip>7NOnIj z+bP@j{|m-i6E0e&9#{1| z{C&qYq>uN#wqv|Rm++2gs4i`y@=J;na2{EhZ&ucj8S_l|>toPf^mnM=Zc1z^90Zg# z17)ki0nl{#+(zelFe2O=#JUrj={Mg3l*IRMX>(_4J620JGD|4b1PX8Xs`&MRqQGco zVoxH|cbO%-+Cs|hjSgE$!q;qB5*&IrV)^sb%SIMgTmdM^?;0436a;wp`}DM{a)gML zPgp%r*Fp^_{+A4n>3WSXZnJjybSMmw(U*|M{B)HvE5)5w2F*1c`C2RW%JW%RnOt-s z2|#>LZ|}L(1}TuCVHOjQiP~gcnDI^UDSurU4(-M0eU5VZ zNamz4URly*UvDs@5IJpcWmk>M*J0^n$S|Y3A%VNFkIcj@0;+|Ih0kg(@F{MtZ#6_u z69JP2>w3(5r-GI9_3JQ2vt6&^B^9;46qnKEv}5LWEG8&~6mwhxeEvb6b|8#9(?wGB z?;0FfyzQiNUfE1fU^D;Lc{&rrYo3wvd>2M@WpEMw_gRU0Z+s?O>s5oB^(!#W@Mz1S z&V~1i;f>|Nf!pnJlNQgbn&w9}+4l?3Z=qa-Av^mSwX-3bKo*B|pwC{?$v2Mi@Li8b z3v%` zBxvMbU;7=Z1Xu!BiQlrKzFe^>rSM<^0)+33fhlO3h?&YS81KkYJ+C`>LYsGJ{?zJV z+iFQ7yA4Ju&T(v0epZ!EELkiFn9QXdl@}~8NKEcD94u%OYw@ZZFxLt-0Sy)TGZS$< z6PpLi&FamwmEATa*&LtxPqyBLGE^qHHk*4rP1DHob%RFL`Yum7Ym!}|`n6cmA7Q;F zfo&O%Ln;!s`F?TWZbU9&qt&kuzx94ynpVQqQv>wHt=wSdpv1^6%Q=<>_B730$F#GnM{RIH~=KtVcxC`pBbDKwHKxKzBh2IaKUbrc}z+^E1Ewg1mf5#gF5K%Cx{{mvHY7;lj6u%dER6)Z=@J7<8}EAJTddNe zsX{nd-iY8>Mnq6RxeL=nr3Y!)Lq{_PT_BlBfj5$(10i_^selZ9s)tb=YjU4bJ53k<$47z(p|kbw<2A zM`=1jN>S5eL3v7V;J`~1tFLpo6mHeS?Nm09yOqO)59g&#WGe&ssyBjTsG>JFwmIk> zY8zm>?Sno~06=X(lbpwZq?M-!UURn`ddZ2*}bHuyYy`Ob{DjXpVFCW7A4*#6PAVW_c2?emujsgV@HR6muV(JHv=& z?b&A`V@m4H0SGst-mentm%omq>v2aMMQg&=c#~&uyzA{+^e0t-c3hN!&I% zP7L9W6tWaV(MGxNkc9GR!wtvpmgQlZ%lh1&`nMOhCW1iDsNq#*^@}$_*^haq*CqJ< zhF#wg;CQzEKH41&_PU>DeWGqh>D1WvDos<#wuS!>q7Yg+0BH5575{c5{M~6X2y5f909(K*et<~gUC54A*wLRipwgSF%E9j;N9l8; zrH}Me2)I710w*BCN~cORP-9_CCDs}vf6v%|IKmhU^I^#Q^nDTLXB#_ei*_|?8B6%f z@)pS%H2%#--b~>KZ1flk1L6(l>!0A_1YMfF-C}rvE?Fx$nlY^1c3g~IhL}VXxJASJ zC1xgI!<*ej|IxWK-8x0AZJQ-fFv8`zB4NQ>92BbXp`_Z>#_!slA;5aI`|&USgndw` zj9S4!Hc6qzg@eRS)s}9LSZa2yzrSPG@aS@z1cK-hRz)*_cf9NdO4g&HeKkcVY98$I z=r7OZ>lQFf!vK``5^K*YsGUow@c0wqjxRK#!%Y9aUi5-n(urd+ofp>b$)4ShNl@ib zd&aYW2bY~@elJp zN6+(%->zbAVWZJ+NK(QH{K)?7dt-?jH1S%U#+U%UyVzwnyBS8S>2=lW68;V_@fZ7t zTH5T6eNGqV8SYq;vO+ zELmNsV4U&81{>`L)m2}=*vY?6@Jh}0BLAG6wieEV{O6{Q4n+jYY4?morjNc_CH$=u zqK_LiGH0Vnfw>=_TxtGz<&`GqYfy-4CH=4+fmt3-duKO`7!qnx^3<(;P7ugXlAHH$ zN|fD*_4b^DzedET&*u`Va4$VGsD>=>ExeLfp?Rn{BW{-`eAkyfq z{Ft^7nRKP<-S=~Bk1Fv7mG8FWJ&X65+U%}Vcs&t2DuTKrUSbIj$vgPY#;SO4Ep8er zvqYd))i0{)X%FEW+i<%*b-f9rUYd}?A-Wa2lOrsC)@7X?axmb$DJku%`~{O#Zxy(( zbp7|K6-N40x*pac@I0ZMh4huSN4uy}GGb9>h2CScI5*Rz=;VL0Ist2N3+K)sFNY}r zO<;MX3rT$G69?~h*?(nFgtj%HHQ->NXm2M`bRen zu4z;PD#wv0d&lQ&qfg{E_2#b|L329*HJrjcx>Vjw@ciAvTsiEYLABhPG_`P!9#^mN z{^jfC&9R%+>4zqiudImg;KVzCzon_SKaS7(pqTtI;*No?vRIt!BfTBt^UMW;-aYc7 zee8!t6R|@1gYHJYNv=bHiCqju_Jf(#&E3)~w-^deHPDi|RBe&1U@{30E60dQD*BgW zXjgJvwo74J=rP01d{l$gr>Ipe8yBgD^A0bN-@;*Q6@|VGBE#rNGt130O*c2ZqxK^?5D6w z<+s&3w>tbEC(k!CbUGytIH$}dauqE!Bk&yR-@{H>Uq6;#y~h0mBk5R2 zSfJeTJVpXu9UvkaafPBn3a`|`2dtOQ-hsScSfEq zJiW+W07eC9??*|Rve|lOL~0=alMJmTfW+++=sjW zmy_XyaRDC&IDSYX5>{?`(I=8qvol|>Y?@k5=yo5}r&)=kIN7sJfE-2_H=vg6BW*WaH4Ra=F@x`L^e_t6yeU zCqAy($Zq}!h+lT0c6B|%&$efBtL{C~krYl@RZN1;TMjflHxaET@W|3W{G(%e`IUT} z;7=u3{pudToPcC^uAMhIz37lzH?aDp&xb<^*-!J>0Y={6*F4rb;@my?BGym{v7PM= zsfY1U&W({$Z?sSjFH?;=rzhZ@E!h@kwbV-!c^PiKfe3-gJ@-nprIeidMT`zVvapaKTb?a7kx{-aDUSX}x z=lOZ!!Ofp8eY@5#N~gT&6YzNBU72%^f{9h|U#Dqz^%_3}51KS@>5H*?<@=p*kO~lv zvYp%YVN7MF>>OJYMC;O7s1JU&ugZ-O*RS2RbUJeGOk{YA+lfWAR$nHNCAO>TnwOw3 z79{?U&bG|Ms0Yde%YiZ!X0SOq4m%-vqq`Hwn9x%=GcRl>irh^* zxf_ri*Qj-qadBhqEKpkAt9H25D`nde{Etq{X5QsbqOQ0y`};wOVrgI2@^p88Wlce==IQe^l%;Hou~m^5np}p}M4x z_N6KAJNKevp-vfNMh`c*QLfU-v|ntFZZ@tJYfl@{de(OS7C1+neCciG-7;(7OO4m%!{ z0c-R*fnJNekEidRcShqOZj1XxVOh*Rq?f{Aw_) z$IKrA;ft&Gh=`57(8#v8ZJ-A^j`{2*X4J1`tCnKkF8t>7o79czUAG5=m8j?OZUqN+ zC(EKyyj{dgs~ni}V2u)`ntK>)CpVKmfyJ%BH~dHSmeWj|0c~ z=D-KDbt^4lLVX^aj>%S02`nDFU#xkd_EiNOU*v8q%x#;Ni`kp6xbvCQ3^Q!>0EuPZ z&nrVA@mt#EB3{5@E|gs(H)!@LOMlP&W1qo=kUU97m3bXW#r*g-(FCckX-L{T(-k^@ z-c7xlDMFLyQ zXga$@Lj-qWC2V{v7k4Rv!*oS|7NoZsWl)%JMMJDo*t2){<+T_ zPC3Gt){-0#(8@kT&DMznj%jbEO-yVI(oKS=YvcME#aV~KlXJoxrIV~5<1%_o%+ccC zep#>n)Z~pnq}%*pcKi^172WSpTp24`KQw#TbxFzJr>ja)r!lB1tUz-BaIK8dzXV=+ zazhI4R)7Dm4d49t&#`kCuH%|52zLTc*du!0^c@ETMDsnDC7Zm0y$f+vs%O1JM|Cx3 z2d_1G#U7J2#%H<0pX4Ad!}2s`*7tG8C9VJHHt7R5`W{VDUSG!qsdZY&0rpo99dh8? z()D6ns}zpZnS86eY3zCffG3#trL=MF!X!8CtM62?&U#koc%$XI_`~t(j6Dr|Smn%R zv$em9fS_*Xy4(zlua%I?eD3(uYv<~r3d-YFO8%enN*>D2McsEfg-?6s$uJE-iowq2 zjtNht${hn~0-!l;^TniT>;}Xpap1;q>>meb1PO6{P>Iv;#BFq!Cqr+BkLblA(g!Gk zPhj7{Z(?s6^l^IcJ^n{W>|2{}G!pZv4mnzBemp87LIfoz00sn>E8nk|WY-N9&?(-H z3J|!jobsYX{87VO+5Hf|y`!?2;FXVqT5TmzdA*UMG~;_c=Tg^KPw)q(oP8p0^?GrP z5Ao69*$1;vOgE66M#~L2hyI?`>Lr$6zCvF5l>^3)Clj|^Q0Q2`mjzE-dXzg6{admX zgA()AyET!hxqIMJp44X=5=W<+y}>d*1uky=5&oVjX2}}kJF3nbgr5U^M!HfoYHn>W z{)M%OJ-rHab-4BYW>Xp`RFu)`evDu7^H&k%_HsQ~B^d_2<&n)=molB=WE!!7((Sfy zKONk-sA~1Fu)^{TF_@4_wX*6an*?f^#qPca{@(!tKeyDl@LzDu(8s5Ej-w}IbVdp^i z(lNoV^o9?9%zp%CPUxI$H`(7|=UPp-snYs9GEFTOS$amy!%1?@W&`b}yFT*_r~?J;T8(P0o!@|@Vn2Zgl4 zBfMe86Ech{_5~GIOkx6ou^9P-m(we=g(^(IO5N-@%*G68sj;P8=T~0UeVm`L5Giy@ zRMDAHQ*Ijcp7JiwLqDAJys(rL-K0&H4{m%_+b{xIHhYY8iQ#X+4M@=UGX!b)=5hZn zEg-QhsTg(GF_$arh5fKG$8yZu{i7?e`ev!%1?v5LTKwhI%z^%%m*Yr7rHuI1dQ|VE zdd8(EB{j2-d&S}Olh-n8tsj@J?MhbhhK)m#wat#U4ZPsBy7i{A);waP9AJZ_q~U`X zf7Zzwi4i;f2~|vqrUy;UO*!9uHQXoAaYdJAdgB;Ax0ue?J2vL|jkG)<<6@xD+g8{O zEQ<8Fzwvl)HPJBh4{gK$VRzrvJ=$P*g%%t)4FY3!L#PuB-(A=cl7Ul}r(7Af=Ouyk=q=Tg!WkJA2`8j>#<6&qY?nA?fKR(07xmD`z&JB*Wl?!8L3vkXn zE98fk2aighj%@l-$9XiSZ)Z#V9x8lcwsEo}N49rUyA0zh+YCv`SynMKOft--{-~~I zQ4@Y^`68nEF_xE=%QHjY`sVuq@c%*z^5Sqs&XY%5e`(%{n^Y*PtNdSsZx!pyz8Vr)!YSobXqY z%g7dJ-xTb?y5vl@`4GS9HB|ffbFBVe6yG)Hw`wmO8X+XUc!VTv=%gpG#coC>?HHM2 zc494SLPl1w(j#ToFsSm3Wv1zz9YNKD23f7X~B!%0UaDmTYeShLqa42Tl_D;1JRJI7fuivn{*W z&wb|`TO7NthYc)-U4k(c%xoUFm`&rSO#+1?%^w)F4oakN{Mx&dP@ptBoWUq1B)K!o z0=ZH4u7{2&oJHzchAOk{qbBXzIkYtn9KTZ%|=j$hLE2xR3B&LPaqdbM%4e z-9D0Q?l37$j!~+E^@VZ-nIJ>B~}`iNLggu%<^|F6|3nrR0RDH_uuhjLEpxb|mv4wa(7g)oZS(xO~{Zclb6ZCfYIux*@& zyS|#D(4J%uVcsx!WJ({+8|7E{m(0eL!A10e~=)bnBQG zlhdKi*Sw$^0#q0mn|Sez7?!eKLBl;g@}s~N2#-Kr7f_l8?~Ui1xI~8*gOVucpLw-!NzFHL3w#Y5^uprj z88$357`H()HK$|gwNW#ZEgSFK$w8#u8BLRkz2j=HsaR&k6OjHvv@x}w;=Uo%uXvp6 z?#C@#V{S9GnRpJFYeu`;xM-sTk^mpM{RxsRu~UBc7RVJ=SeeMPBMAz=TTg;aBY9`E zRZR|y8@c?rHv{EWi}V1bGnYunB3nC;@ca8+1unzIaA9AOzzXzz7QSqy9LwVp zrDmp$pgZ}qfhw1QAPA;0AcIduCWi&yrc{VK9h_(gs83wiaJS?0{_QQ_XZDFUl5;)) z^Ip!hN+1`440g2ojQUu7QP8==b=?@e2u^|svT=W`Eu?-$%{eaFMy-g`VT(vVaF*}I z@w&Rf>I1G)TvguzYYow}fLid&3g}QSQP`G*$=yH4rL*J)>Z-M`eVkVxY=hD*u2h`* z%w%yKxVaiFsd~;NKJ5B6QVnN0LErec^E_aIK3vHLb~VE|7!3BhZCOp`!saAPV28iX zXmD&NSUYO-MPq~ZcpXX`8Gg|%`V59`PyM5F1ijrRlwv2%BxlNV!AoQ~DlGd2G-!0^ z)Iotuj@U2N`A0XCaV$Qfwsg~Z47Eppn!^4w?oI?= zm`9EERcP@dq4E1hG_k}GVjS`+N%LFy80h*@PDF$1*9y`n+HL*wTXwQZeuGm%=XIb? zH`%%epJ0b4vtU;V*H1o$Kd@Xdx3RI9=eyRU{DOJhtcZ><+8lO?(D%HN~vFcglYnY0Kw>!!KWOa+Fd2j`YS5zA^--UjBwb zA!An%g0|ynT&l)ozpm1xv4o+QX#y>XKWYx}i+1iU{+3}KqvE}#0gvkRzY*zp-$l<> zQzKNl=PggcxvgkXVrfBp3DQ2&K_e{8bECjg*zZi79@`|pS^h?~mS&zKh{iuzZY&Kj zBi#5kSW1+e$qzId-8;{uQf-I}pU(NuADV!tSOErF^{=M7n>SNy<&_bRoniK_z>@A{ zpELGH*yTwl$=yJxpr-S#WLbPOIk5cG5|VNoaMKl(-WGd{{<2F<&UWPO*N1JO!;^=M zm|s35YUb+4*9A0c{=e*CDMN@tYGXL>ZysJ!X@`q?WZRY@Po*+2*EpY>alAl^ggVfI zJ_oFy2Iip-$&)RTtl&E?$jz{QS&(_-a%zzyoe-toG_{|IV(7ywFLvk&)BK=t3 zHXw^GRigk%`+8uM!IjlB3H$k$mWBk23RUNF%|!skLcIWd{{%k73$#si&CJ{@N_ZNz zpz`0j9HaP`D-(@eIbwmx0gBAhSWW(n+Jiv}>C)v5(+>&`^Pf*oXbd*4x5Ila_v_tK z?mq5D-q-8k?zlN9#~Fl+Cg~o#QWL`^DHZF=Q&!qU+XD+e^PbK1c%S&D z|LY(24TjDEx|G{$&T9WzxZNEn_DJdGf8WC^&i{x063fD+IOqoD7P+kf^O1IK%5pm$ z+?4}o=&t_l-^eYM`8wjz0N9He760S9Dd_E+v9VGf&<*x3UwJpAWbmmIG zevBMJ;-r>VASd$$Ruw36NPil$BG|Pz{ppDv!zNJC zP@d>?cV~2SgT=75P>-P3#}3^@e0CU2*{JHd{?w!?A!r9e25;Fh9Cgqp zhIg|~-XFYi>*EQVH1wI44J+*U5Yrd3|uV1$AhL@7W(RAtjLcw$laT zAW(QoTS9NjF<}o{`$dcH1gmcDApCr+d7x-CG5^m7W?wH1=-Zc`ZAz4c?>Tyzf_Lj- zH0cHafr?z3?0`h47slj|^ANm>z47a~`B_aruKLyg9N5^%vuNIfG6+dh5np-yr8OiS=M447#~acJ2!zKLg^ zt+HBcL`lw}#p$!`;zy;k*u{OtK;|={B~dQ_EHN3oWP_(Wfc^-<=E*O*6YvV-$zJ6o ztJ#Oy)U6ZS%OH8EbZHpMmUJ!56_5uK>dK%!=6|_Mcui>saF(N=vMg^h0`WFAKr*CF z&n5s(YqWCNdMy&&pElc!u{1*ykDW2c9_CJBCh!@YkzDT-xsL|@er5F(1L%8Q$>Z0i zXBLtz5_DzvQrEHbKdmiekpo2J{M`2Ao49US{HYm5h)_B6JCIUF9FDVh&Dk%I z^fEPuG(Nsr6YkXil+wQtlrBWkh}PM?^NN1B?*L3=H=%JN2cG40z@t;1*|Z`uf=)cM zUu?y`k@K+)g7uxaC4&14$u)6;sT4a=DR1ZBw1?JRDfN>5Rv(L;z*SDLQrZAt+~|6K zLIgmF7oP_>H-=x*D`G$cS-2Ts$O|x)aK$@1-BYK5MlUy+qi7Gmm~M%!-P{Q3@6(%Y z)~6onV8l7XA>^$LkqCz`3sUgFcQ4Rx$^*JO%e!k2|=e$uFvTy zox6oMX%E|qOUp<&kee$G-@Yb34{0`s-)hnWcKV2qyJEb~rc(ord;S;y(JAU{T%YFf z1_oEb*>%b8lWfS#rgZ*}p^Ge*FrB{h+GfN}-ASI~uNQcMSp zXXMaIi7XN7HEDJgl*RV6wOoJTPn~s6Dr*n(N=^laa>pJ3jSNN2i`lTxPpDn~D^80H zSW8Yn)ju}~rOWwt&lC)))7yfZrQ!nW}H1oij5^f+80P7K^;RNk92Surj@F5 z27Yqk*=wt;r1Mhi+>M%l!)?0W!5^IeEV(-X+)--6N(tRxRU-SiJ^`ID9^$h zt2I*>LhQu-J^rr@M!g#USaUBS#^=Pe)FW_@KdvJYR`l6wtu(_RC5axs+)v%I3N##$twh|iHTLaD+*og>QG z4_cllIK}Zlh{dSUONXTde)Dpt2y}sTHSw%tIZluM~Ltbe|5tXZUQrYgslfP&$rSDmKtEpKok{PMn^r zw~NFPOT$!}H~V<|IQAgPI7rV)mD2gp(9vf*F)_=YYiTJ;JvM3YckR-AL(k9Auf0-- zN^akr?~&5;VZ5xjiRHTe{SG56BNS0b4?ePyjf`@nY=aItb$m7k)GQ+s{ zhC##VGS8V$pOYikI!ZmodxwQtSFo&lc|}7qmJ_VC_;}eUi`vtuWIOvI9VdBB!jeHZqbyWNvTFK7D(%hwrdSU;?QfeeW*Ho!pr&wVjhv^ zV%LCU2^`(rHkh8{&x9*dhO#hn1K2n0{*qqY_5dhuckQ(Pu+uw>bLJ{U`b+K9${cZr zc05bwKC;wLMmJ?!m4*%A6!#w$7MBvWhH*Xerp~lYNUDlFR)&bdXAu0%hhZi^I~~IU zTzU&;9`Mco%3HG*Qrq*}w)rN)+c9pO&>r68eJ-@UG&F_}m{n55^#613k4>L127A{a{kbLoEB^^Q$7r!-);hM2|3U+<;W-YF3D|1Q zKsP6c{YEnX0Fd~*!6{n%jTW`wi;=8DZ0ju-Q&+H2M{Wi#m?kH*%QSgN!Jdiu!IX0~ z{%Sr1!Of2{k!>hAYZ682*svvdOH_MqWS&rpTke)l=&s%&wIz|6*2Bm_Z&D34Ib%yO z(B#z7M9GJ2WfSw98ow6WO1>p|>2D0cPRSt8bWF^zz1>|%xtRD}gWJ4Pg-KsH-p=0g z8x&sPJrG?#@G>yT;|PbRdWChuj-_t=9rwr8A5JM7dybf}7@EXQo1{78*mDx#9|AA3 zCjdGqJE;@Mi3#*N?M|hQdN8IjE$=x^;1#tYWHj%yl(SV(N^bbcamHmlgD+&!>xFs0oE(7I|bg_M^|$(=S)2g2Yv z^eA8G#D`v4K1o>FTF+WT`PxGqTd31}3B7okIP>bNQ@B)hSLn4P&RZS|0>V6s_yD`q zwbx{y1uhS+r$lY$=v{#SHiZk^$h~(|9FU#15mvkLFs}g*Kl&Ai{xQo&s`|Q66+4#(y$Of!mOiZVFSyarpw9ds#SYM6- zikKNm4{0sF3wz>`s*mEwpb$HRcWqg{xX-)Z`P5zEAJVHmNeK17jbWCPx+6=`^J>+6 zp2RZDuEkTb|9b9NjTPvY`=-du8#_3x49YaXUT%>odF_1IzC@#pQG2-b2*rMhH2}}E zHEBGOF2v=GN)vN5c{V%6)}vB6(Nx;5wr`++DL7(zgK|GaW#aqHc)LvY9{-BDtK{pW z!Qe$EQ%a_L&ra-Y-q>-B-F2Ks&lP)s;g@7s#e5io*N@rv=H*W0nZ&MSwCPr*sNg6i$yk)mr$rElJ53Q4f1oiA4$zZbzPBlwy!@ihE8kVVdk5O?&s_EA z^u>oCSPt3a*?Ft-U~cRrGiRAsOp?u2<-fbUzPBuxS@Ny8jQ#29Gea4oRVoLL5uzq6 zyH&N=)6g&T)Z$6TwQ7wxS|u8`jrLN^j2{EyF5h@7`|i;MmW>T(leVJ`xg2exjS z$i#rEx40d6HHHo@CBLwWK2+eU2F8S!0DLp_D({ON=(v?HC4z6Ms0EEWsBKx8{ccm# z#nr)ifQuzQ46JU~uwXl(lr?T_UFA#OV55XO{Afz!Lz6{3D^1`Z^?LjD4LK4HzcVBt zXV~Q=PIaXq2i#I9bkHnjqHGT0cKhl<<6VFx!}#vRF5Ya@B=c2{h%{;rqXV{@snVxq^Gg;9K|GC;RaGylG@6eCKstpC zHN)RE&$&UAC5LJ)`GhV80B^Lk21yMTgyIPI;9_r!2xvMi@_`FEO@`Kk1 z_BaQ~tM6Oq`^I6s>ifvO0ro|s%+sa68y8d}*NaoQR~mRNOgL^o2hYCGt`vyU_#ems8-1v=&S3!6rYCPJGA(k6;y zTf(F6XSc2TEvb3VHc9tPr~XILS;sZiws9OE6%++5kVd7Xk(7Q6N<;+dRO#48H%vr8 zNdajDm6DvqHjptSMPynr4q*Gk?n`fe&WrK8RSv$RsA3D2Xs3<#?t8Q4tgbm}alofGGcZskB^<-U5 zmb+yF69}Kgn3eX{E>VRBYVY(>vvAkMuHGwj76t%*GZr$(!w|R_B@aO{RT-5Ja)y&v zU=B7PYj2q>Ag($(Wx3!Eb%szcqv5tHkj8nV`ck8`Y%zxnkqjNM_RAX_Wmfkzfqql! zq9NbtY^{I1m}PP=2|_rZ^M>i9QY>BOu}tHLaZiX5wZ|v2WZf}3;i$?V>>X!8$=5x! z@+l6pS`(5AT(yY%2|?i0jH13i+eJ{bnEgJg9N~^ia@AO;{d(NXhP@#I6Oqd|`#&14 zU+55*5*KFi?Gq`^&U5!>>nR-P;arUr??=z&{^-BVm&|I}e3&^(9XIGu)r`nP@)P_? z^7n^TiPysX)fEko<3U@^=^{dbzG2))duATM>XDEk?z-W?13g(4$u*hxI`1wB3H(r` zjC&xH!XSRU%J>OwRyCy2=A`L?!UYis=>6|HUwlFHuSIKn!n)-ujHo_ITG z9tEw2$mFuyT+lSbYX(^NSqjONc0U0)e7G=bK_*&lblcp`qrdV|>7UKpmSM8o!jiP4 z7LoyW@olw}eN;=4xkrY(SzlvyCygypfn|Hx9A!0myK7$Q!=UWi%}ey(g#ml{ZKB<# zPrvE3@KQ{Dz+wdjn3>f_2C56ip_JHv(Fl#5LSdtpdfTMpaSo#XIh^QXT!3JRvsy+7t(i zg4cCo_IIhd+l7C>`>Y$dcw`-;JnFT3sqNieER^w&TwqNd5v|LY`8)OPTKTd2tT}tyxI~nWUiT3!9Db6&Oc#g=!Txev})`wXq28pSl*Ao)T3@F7mA0SuATk@}Hm1!cNA!>tqNs=OMKVR!>1+h_graqUUyFAZzb#aajg zU=Zv#mJSWATYA6mh6r{v`B$8~{=0b3ij4qCu~m(+v9d&YD}!*Z5dr>**VkVMyS5VU zS64g>2!0EqT$kvSJcOf0VvQzV=bv&?wc1eAHL6B(ry7_hu$H!?$+Ibl83>{6Fz>VI z#+g?lx3))Va8U3|J?fAn>MUt!Wk7wT=-)9A=^qB1GT4XydpB^;exp|1&nCOI>TqoH zI>IXIzPg9q$ZmKjn|`8cS90r}NTI|ze+`R)6zk3VN-wL;aymqMkoA{-KKkilT8b?| zty1EDKPf!cVtm30Fi&(HRN?Go8ff*Bk9)Y39~31dU+U!YlH-^vF)%jy4^ z6iV)D$)fd;b3=%$<)boLDvdh3_;t#MfrIDeQ?3_V*9Kt)9{?P#2Eg`jnr_hd{N#XZ z7=$B`nz9dwj{r}sdYv&sOOSM%>2bx=^j;}}lre4_+Z%!|)vP+SzZ@r8=7mf7M)C1% z4{m8huHr})yK|5H4F&F*(&KO;1Fh*#6m^DYGPC(72yvw;F6jj)-bk@j`XBra$~fx~8hp9mXMK_)snv<*UX|(2|gaKXMKd79Xk228^0#9a&i3 zN=i8p#q;jSw2E<_mhbpuCT;}%L-W6w|2PV#dgcUqn1YEN(RlF+O_~u7o*tmJ=s7Gz z)tlm;&LoaY?O9=lwp;g#S_JCN9%)UXG9;Buc%`8Jx_|iv{j4T0@7?fJS-d?ltonf_wQqRKxE5_<&e(?My{C58M2NC;6*6bZ9%ZHG;?H1@ApK zWNngc4=Olg2VSfY2VzPy!pp0H2T(7HL%Y0jRYxAO=-KoRi|s~jBumNWY4=1_>hvPX zcx1ds=;O{XDPe#herd$}`+@3*roD?~ZR+#Mbq^VzI|{8e(ZRo;{q|)KPF|&gl~-&r z#O3|Yg*>qX-Fy&eQ2LVat~pCeSr~r=m3Ohwg>mC)zFkpC1=(%JxH%#QVaRjRXe5-o zb2F7YAo(!X_L?Um$8tv`Zjnd624zsZDDE9x;}qY1Ra5HVks%eD5UE?@{k+bCf$`-b zV9%;7PcpFwX|a(zt}Dh4&??r=W- zSroTi%w`vAHNxfbqcnNAL6l^Xgf?Ui<=KvT;k_s@LDS`huQgfm1&|P?CEU2F2*Cs` zFJu=qMUac!^Q}MVi#OJ>s;{ijc3xzZcaIc9O6C72s`{I^5)h0`9m_Ak5rub0AK5%R z2zDOZc^L{_9?2}ltaX6vaS$8pFkpWR$b8Fm>w5oi;C0)ilv=?lmrftOg;sIRvqXD1 ztS9Xvh5#e$>nz_M$90=rEv9M=%?a!2g;Wa3Js8*sR_m1tSJR$j9q8+$4pxKNTmH!F z!`+=9j`y~EEVQn>o#_4L9_7^Pfo0TepOi387G9#?Sui&%=)Qv#sVtBXyG3uNw2(SJ zfG4XZL)3C^*QD(JuDNA-%3##bDT{(&?%S^p|6^+M!za3;?(E`S6cuIna>2V%XO7D; z>tVsW#1@L%e5>8M_(y%X2}Hz9v6{Z?VDn=TbM~CM@*bxIo5w4=5A1t*kVdq#&@*NY zOOEb~A_-kcHer>?n7kbD-u*k*{uSn~ODPV_kfbfz5<%@fF_~|?GY^h_nk-X)Sz4tU z1?%Z%4*DQPDm7h#YJUu#R8Njn?3ewCl&Cchs`Sddz*Bck-<{t5cG=~!QQ_H<$j%PkpiKR1ni7ct&8`qAr_7(Hg2S;VpSE-yA4`r8X*Hn6cQBoD>L&^^0I(MM}b`4A#@W<5iy9;vktb&D`-I8A^@->!m@y$Y*X{EIAMG?=I(&s8>Y>CvSQca&4Z#u zy!2ww4(R6Ky7asI=1i#pMdj$j{jEXgG7&Qnwnl|wOhSx}oB@_9^hQ*1-U&(wZt@~n z*V6Leq5hNT-NhmT+H=@#!d{XEJg~siW^CHn43R-Qq?|;lAO0P-@vgARH?CQT2DOJ4 zsi%@*AM=i@{m=$B@-TRT&d%=WGY&sT8KA1bG#L^-jJ{3C7`L=kUP@X>g;XA z5zN=SEd5g?&Ir7-IM3d~xr9f4DxPa^9DQ#l>ZX4cHh|OYgDN|9- zvCeQrBcGuB*dqv+<@EPc-XKJGv0c@)Zz=WYhN_gXthOa}um$a=CC^eD6>eCYR=n;x zCt&r4AxF+!uKOCjC^)SwBLn+g`a?J9PS-8X7`Oq@!VjmCymFFIVNnFBik3+M^n@>U z&DA+C?Ww;ZK@gsbWF3R`!xr%}UZvSi-P9&?nha z_Y*L9dflsTp*x7@SYT@-K2o zBsEok`rAvKed7-9ME}4*zg(RkdbEl3H~0DL?p+fZcp&s%Bwa2DWVY`9;=0tL_MEWa z$-N2EO3MNthPNVKIgMznaC-OzZGi=B*?)RykMZ2U+i{`qhz0JdROF&@OgpF>Ceog$ zo!z<{#_4#Emy)C^6yb%~^&9nj(zjrU(+fO3>8{o9zHaEJ5qToC?KGr=a>ba}_m+kgMO#)1?&gk<^FT1pk!oaAHsBJO7J$S;uudDpMotm~#UyL-HsY zAF(=LgWvN-qqCe$;E%gErf zvSWvV4y|ZNG+Rh<<9w0Thw>!%zIF{o*~O!c#6=?wz1Ct#BY1S%F`cSai&Bp}1mpe0 zR3m#L>t~l{@)E~0wKS#ZTUrfn3zAusbO!N(m`zUfw9|B-kDi>wKclA+5rItjbG zu;Nc}t*_207N1myswQ);h7|)$&Z1A`Srz>5ZpFOen(E-89R28pfHJ%HpBGnh=4eWG ze}2?Z32~;4Ct1O806r{$R`)0dI?QiY513m->SsF%YZiRDOCOni75rj~Dm-BMe2hye z`$gOqM>2A~T+z;PiPkmFp$DlOLub|I?+*u!bxnPT-3S=)O=?PO$X-ahZ3Q{8ZGfkp zpY=8_z;OoK?|{(oHB0FJ^E9T=*rm@KX_{)Gi+9F%UYyk1>>u>WKLxderTGod;CfxwZ*@8e zYrm?0F9#FWoQ&aX_(pwV$3FfTv5&{1q^jLWLfH`#Gp@rexA+wfldmVo#?Iz%MJq@8 z{MKfo>7Wld-phiP8|$BQa=Bc$SL8qUuR*_#vVLQs>%fYMlI>6TCy0Aps<~CIsn7)4 zdfsh<$hT^+2tR^VE*yN%X|W2mQ-bwL>m%pFUfe=B$nw< z6q3a+!_Lt20J8p<#cTAhXfba=fr+K;#SOy&RAWC^|NE#G@k{XDu*D`gCfx*Htwv*4$=WRHWWU&T z{TLDruY5nU3J;j(1%K{VG0Eo_7(}iyPLy8w4$boAK^G|BE7#BdN#4!-(Js5i9R`X4 z+SNoANLvaH;BM)@Xr)(eWMf`}v8c%QJ+r7iGMmPpA!AtC<&bZ8ce@4Y_k@r0Y6?f5 z5ViKC5J0an9y<-s9g_Y_gic@0-fuI!}(Z_JcFU z@Md*=uR^_(?d2qLPXtmwLge<1h)t*$u5{L43 z_N#4AAQBvu!Lk)|Uf=zhfBU7GriSw;9^lD$Mv`6uHT9K^o|KzL$SkEcZRi~lpXi;7 z!Cwg6+QgUfaa%^vSK-VC61w5U5AC?Q1LnZM z5|dQst`@cWvWM2?q9{Cx3lSklJanExh?tIP3sEkh+#i0Ua@42WTvfnw`5SW&hyOY(0`N|rSd*0J3$ zCQJ38Qzg9+xEH=MpMGlmh5Q!Z zldpyT>T+P{?f<6xAhQ3~QQxp}^KO?_D&v=W>Cc>)6h1q#rg`|c z7Rm`I6aT1+^|X)M=mZWIN@$~}$O+U)ng|(Q&X{0`OhJ^4?JPn5L>M9al8sxcJpQh( zb0I(b4PO@Fe-It7mK`fZ%A9vXO%gWUf&hw|`8BJVN~&-LV;X-+j?-3$FElC|vVzjB zaulamNAowya-^WN(-Ed2i+7~1&Sc^QP6emPdT0)E{p&$w=b{uhccg0@yWaWGxI=I5!?2DO$ipHxVyF-&sKZy310Zf+mSrA zgd4qLUzYQ}$@~4npsp%bcupleOER3pZ_m77MLZtM6;SJ0m)x3_v83LQ;g<9!C73lG zz~bhnsa@K)Ca}63Kci&VG>0)BOE5Lf%SToDaVPHssbR>?aCp=FT}Z zGn&t~MRD>d$6LBDMLx>vI+Hiq`OtnI7Vw=sOuYdNT;V^Ucxr6OnfBVu2f}?bm!v?b zIDIwy?|fE(`Ed(Dz^V&BJGvy-lg9n1=uhboBdiJWerR4+N4d<@t z3*@;vk7#!E&nZovvH{Ra+vgC}_}9BjYD*~{E&rY&+K*o1Z7N0wkcdvj!Qo$s(_bdC ztpktw+9T)Dd;tc-hw{HR^T*?@Yxg+ww8!Xc)DNQ&Mq9XPlIc|8wQ2oUnhZT1CGNTp z?pk5#Ve_^h52RcEc~H8EFuSmdey%3dyDT)YAnyklM?NPnQ*Yx!!PL&v;`Y=Lly-fx zO8+1v4GjqptcV#oAK^s2c<|_PH9aXVPSAzC=*|{u$e;aSL1= zlU-xs|IV{Y^!X%yb`AEv=wdV3=|Iu?w_LehQVQ3fjxM%|yJ}Xf>da>CIyt9326SxPkNKjR^oFg`_Qf?do9^&mN%|4-v^n~phBHjIKbWd3+pk7)!|W=;|S%|;0D8Z z*VT-C3`^(M3a^~ergzj~g|L_GGnA|*!Dy4bbg?X61$EjlKu}xc-QP3rUxm~0SZ=>0 zn(I1QAC1q+bDVD9ivB5^-&)}Pc$;;{&F1QHhJxP3m5lojaT|0&#Q{l?7(4A;@grCt zAX)cFi3&M41s1SDf(}I~CM_(PyI!31ugYa9*r+F)LgZt6BjoH-;Yy3cr68?6axAbc zzod0BE}kxjxhuC#Z>m;B;VJ90$F%U7UOY13A^zqUU8qdSzlpHJCO=pS`-9hZ%xKGT z;D^}4z(B-_l)b(9)o!3UE7Xxz1fTXqS_$4lf*!6j?2AQs`{nx6_W3fARvrRgPbG1?Dk{E_Td#ZBSM0i6i!ZHUjfZNUs#YF zpZ$f%IaHgvo8{rTBrumk6|;YMmXM>=&b<-Sl9DZ`>Pu(dEQ_(j(GRjyDAP)A8SE%s zMK_V-==HR+j^C601$997l{$HxUXsvv32yOl&-G9fb;RSyIC^;6=gGJ`DKj?-$SxQ7 zoEGkFv6~Fc?oCd(v}Gs<0%T9wUr8;E_6+q7{9c+%p0oj{ceGZe z!9~fH?DUI?H@m34QSoHB;P}UZcayhYos+$k1O>eye3*8U67837iWUprh1&Sa#oaF) z6fH@zFb|vBiLUFf(1&;}hWGG3Y|TRuvG;c+#U|$3L--&m+Ll4|rQ{-C1K5Bw)hx7f zX9|jhUA1^33H2}{(XE0x2$n#>#0$^aTa(bOok}+k{G=`#5?+IZ2$NC=?kvb#a_;9uGG&u-7{+r7^3cq(QwLtOc&Ws zYh?KX7B$fSZgCgB)wnuZ7BRXbbB39+exUW2>r`qxW9>>**`MFv*o!?`S)gJ9sq} zfKjXdHctT`sP~S$_X?79RkLE(7UCTCUZE(<)lEBbSSxGU<%|Eyqu=wDyY)5~t9l`8eSM3mRF zkw?+!n1>Aa+s7Pp9;_q38}o@3`>AgZ2SJ2I{59Eb-~LM3U;XaN%|wdWSOe@@IfC}$ z!u8*w#TNTzn!@W4GX++!%TOi~l0#pzwZTG6f%E92zdE!VQjf-TT<~)tfEe}?O%~>? zd^Cd<_qf;($(?$~$Il&gRr+N> zLjPD{_58Q2U9MOmmDBf4j!pK#In)cAri*{FLsV~`+Aa=$U-bNQ!gZ*wIX)uZ>nf?e za_yhE=l+Vt=jkQdccGoXfd?H$eiAwnD38b5I6}IVd}2BxnT16YuNN8bNG#&t5s3((@f#%AyY{6d zuVa<=Yr<(s8c`M}-ze$54I&wjZWQJ1ayG_b(Q9Z=mwaUs&YwW{+Qsc!2Wua7B#)P+ zCYnCudYthuVrytZmiVP^zIP$){vUm~c|Ijy8I{Uq!;{w@-ujH=?Cx=oNhBgf ze~@UeJ-@G@C83g6>*#Z~HVwz642VVP05cvN7 zT3Dvd01h1tEeJV9^lQ&M3(>>vs!P%7c5c)5jf$`G>VHvk;G%2G$o%_QfKbNpcc^vSu&bk*_?InFv+|W%hes zTrK1^0CnlF^$oOs1i1smlI;6_zd53tGM>UDA6B=`p{8fYhKg1GJz-*>oTyhw>9cs3 z8J1DE1{%KB@X1yDjlYH|FAS^MS%B2u%L@TxeD&{FKUs7svIkvLkjToi^9HTDvmhS5 zm_m28R1x(+udl?f-u8hfe}jlTM6!WpbMOjZkrqohxp?KA(LwBS z?o?AQu^_n1E9tDEcYyEs8R@#MXN!e`YC@l*N(i7Qc;o%Hzd#bU_SI9=Bjj7P|LUg= zkLTSpUC_q8p3kaXjC)g&x;0HmGpCN=0}z0#fvEf3d2)4RNAh^|$q707b79r7(}zQQ z!xwoE6N6i69Jcg0%`iW|W&9Nzd#&zt%7!V@`+aaz4C3EZmB=sWpXF{G*4W0&)N5G%D3( z7nisw?U#OaPWU`eX0db#5&LCdJ4Y~q>LJsV#z`Z2ZC{@^f*gmHn+thn=z2VX39yH1 z^-AH6pD0&Y)uypp6nuS_wcFDEPciZ0l7r4NzI#|ysr>D9FXh%DXs1pSnf@{1Q?3ge z`~ePs4yFaz3rC8=bXQC+ZmLQtnL)iC%VsR+?2JEk;Wi6i_AiM|-Tn*9YzP0jT%C|TZ z+kcjSCbqz+fbAJ1qKKgz`g*HVLm;`JBn1ikd>GkEz^{Xr_+d)_G0F0Xr8o`ep)GJ+ z0@i7{$yd`SZZtYv2s;0gq$_gCY}0Fv6b8C zT8NlxQmsyIcizGYf$Qxh;YiQ@OE|J90kl(P8ZpPCylU)kkXUj~oum|H}> z74?|y9p^xW>d1y|U_bXXJ2^&GjXx3^nUL%dAIOwC)Bmg>XPcqSUd)Qc4hzniwk)j4 zgNEqZmcnJKL%P9v6W}$emP0-Rle6bFmcu7^%9ma8U0hQd8}DbnTY3r8iWu`_gG+$x zV%I21=qdT87(FJIGJO##C26Fb^v7LmE-Qzc4s8f3S5t7kMt|c`S#1lXNdHXa2USX9 zyW(ZRgvrV9OvT<>UP;97cB!z)%s-)hoNiixIOVI}TfLxk&D!~=HTLu&!2m>IYu5Dr z>-6BY`Gzo`*=4=yUn8EGPw~?4@f!DD{nRN)`@}YgM|chfAqc8h2M!tq+U3)uohmdM z7gOyxCF}$2aM)hFhil3dLUC8V@di(?KF?@)Hr0fxRpYj-+2?dsQAyh$v6q|DRg6In zTC7b(=5cac_;8C`it=nf&*R$&9IIB`4T^zcD} zvaIMePoi+`gp~8Z2X2kX4Uf(~{RgAtWfMNmuBp0oY%gZbH6r9?EYp?HZ5u8mw)ZQm zz-xnL^ct_6T)6De-xb9^%eS6MPDddI zPb&%ctITXr*W`xR)f?{~nwKm`TL7W*yWi*YRHda~Lkq$dt{IY+BEP(9^Bn5~L2i?1 z)gcH-UQ68M-NAqK2mB-c_DCa$8kMz*V7C~hOF`eU?N6q~}93KAmcwQGd~7XJzJGlQkWZOhy%wsU|X$L5_9Fm}TgGzVqo~W$Fp9%VDcX0Ir=~BUuQJ8f9Ixdq0dCqnKWK z+{!-Pb@}YXWjMj9p+?nF5`K`uAfm@!oln5Z0d%w(S=ZdB&bLtr4F3k7H#SumJ5k*9 zXY{<8c~$50tyE_qZ+=75sPjDSUc7?_T{rtdnzAG6VS?#<5-!g07>chvvsU$jjywLH zHs6@+?E}H2s;DZHJ9_RvbG7%HuBqL7d4{AihD^)Zwl97Qq>r<;f9bE+85Bs#q|7?? z?A%iqWU9>v9w}MtH|>GfG4`ug`O$+&EA$!qxANbCI2hbc`UKI?Bl-*BDV*GF_PFBJ zc?7Xz#O|LWg{kHHopyJ8!PZ_M1Jb&8qB`6+9Bknu3qN|xqW9B%0o>t7#qp#d(yBes zj^oT3qF9mB2E0E194*;oJWgrfAfbJ}oz@TR>smLP`f=p7I~&GPaz-pDsfY zD6fpYi|hV?u*nH52#!9C>0C4M znRrFAbkWmwwHF4_@t69Kd%a4{5xPdTKNgi-k87lFf|n(iE*D4grmB4|`IU|U{9JUf zYMO#mJ~-suu2=@ATRKAQXf1@FWQCA${t@v(RRk(7gG_L2=0EB&6txcS5^koV8Y=D~ zHQB>ommOZxYkf=KL(PG3`c=onhTk6^?_}QbNqdi|4t|i?v19zG6kj^HrcQ~-m0hLd z0{TaNEFR0fesP zgrAA^xW`C*FI(-BMi*byYIhPTy7`-}m$r9dNbg{T4*3OI#Iw}GX$RLsDwoVcxZ%Eed(i zi3{m0<`Q9Tkn+e$uI7Jjk|(nYZJt+H_1F0h8{V7!j8^nQUus9}pFb|}{)&c48*^?E zJ=SuWU$;x#QFwT=G!uNu8W|B*2uG?HC#ZAK6!wTz)!0bIFr^})=^Y+fz@|ZCFg<;Z zPhY6@66vGA@2nbkMRYGf_fb74S;^@J@mc;R1|`|?^)@%Sxu+WWPGp_AfEkRzG>)~%FIHguk-p>5Gk@jO~xk#^Znz&!J zwTHT3>Y!}tO#WLt(Paq5t@*xBpkVR6VRy^?tO7{|M8bziu7i;G${e`CuAlK=W-eB4 z4J&sNGnCvC&4cxy(wcvbOw6ovAJL8A6KiOs-3L`&rQ(hz%!%H8jL>+y8qJkp!W^p4 zU_HMq6TV?P@oJym_QtY3>E@L#k>`Ei&pb_z`W2<^v(j!DDWpCh8YK#Ehog~!AJU1d ziy60{FV#g{F+Z@+Z57Km)HSW{;GzD>1W%- zEG=Ap)3o0_$d!)!$;H|(w&N?$VLJd4T(jw}+iyUuxti5t#Loo}N9tEb;~iD%^J;*~ zRhAEN19!vdvYANe_FKKMy{8EbRsn($UqUF{jrtX-3*qYN7fDHO)~0Yayi1#?B%9HbuH_>8KIaKxo?x_lC033RjWXzF^gz^dghSeuOe4uQ5G~4Ua|h z0_VfqccHylU2g{~pUit%d9{R;>__<99LnI0<}b{Qa|w~s!xGO6*Y3^<7f*gA(TpR9sv$}W4Ya(JAF*d4KBvIlR7Wh!b%sTY zgrr`;KyV+ruI@t!8A;t@s-ss}!wzYOxGYT(EDVS|SJB`fgDBfoq6|W87*m+cf z3(Z_nX?s2Ly94mAmwH?-(3<*;!+4ghFu>`XRqfs9>!};0T7JnQna+w3XnKGN`O>o7 z`)u{{oNrqk1-U8l9(qL!*QI1fuw-WyTQPK4ew zsV&$gpgpnCoASbJLgp`yF4TR{qlBod5q?^3>cGRU*lT@7C#e#auldT`&%M^c+R~eudrH-m2d@yUJLSjHMM)^H_ebVe)EM5a?f+sSB=d94@uz5p4caBGYomj~xoP|~GR-XRw2+BPD+8FWG zO<}m5Fut9eHMb-!?3oB%%J+l^cE2NigyLr zAG&W38~w+`Mj(8bp{3W_`&hE~Qxl#Zaa-E&M{TdRCFfC{Xb+`FYgW(@TH5c=4|}=X zL9Ju;hYhFxzWU+&5FEDKDSGJiBu8akFX45GaB0f=KfZkFw;V93e#CrAkqNE~V+5B$ zJqWr~4W5I`qJjE-X`bmPm@MYw+PSm{FF8&D~37{33^ZY-$Wd3CyuA6 z@|1^Ba^mJvZ(dR-71}25MsDvHENQnNP ztAhbl2-V6^spZtKD{VU6w)%-Rfz>HFPA}8Pz6xBxn)Am?jp#4d1uTzZlJE(~(RU_5 z&Nj6)Lxfc7_non8=H=t;|1PDzvudN=+aKQOfXCu5 zf^lfph8OSqA**`+*K%X8323esh7BNy)1*1B8ecQ?^Df60-Mt$3|n@d6QDZ*oJ zT}NFnWPdhYXZ&M&=Z4R0>rF4B<)w*Ydn=3m5<+~%zWi*pt5_ZL*Bq0pj~LG-!uo%S6Y6ught-VDnfyjgwOn%Gsa+JFK=K9+j zjg5U}91vY-I479V%W55o*{;Zjj7?PxGVAUaS+#T53r}T&oe-R#r(>6dI6{LX)WCtY zDx(ANDbA7zkii}Id-7WCtox&HPmf05F+^<^JWqt&qvArkd+xtxKeO{-d)w{_I8cO^ z;v1?1N{YMCs-~2NlVfh;O{ocE@-4 zrybWF=uRd{^RCyv^3QWpkg9F{l+1rMwFHP}(~c1b_TCM~0p{tJ3iyM+#AbJa;mDmz zqp#Gbnj*c*P;Wk=vg{vCzLX5wqO(Bq*yq~6!q_&xQ31@I6hy^uJIDWcZ|-03nOY5qVZdlbkLt%3aY~>ke*guw8V} zW4LxZv+RB3{9)wGALHZ_Hn=V&4)}$6cUKxu6vY0Cj>ubbjqTRdBnHh=x)`i&W#yGr zL2``UuvLOf)d0?JO?l-%ruu~c*Vsc3kDbQ99DsAYp|AX0OtCBTl0SI*#krRbi+Tba zhXI-DOSb~RhBoiEcY@LTkUNCk%-9US7<%wbM{y&Pc6}5B7-C;6*;3KDqCCjKu^0x% zdMWMXtqNs^rrq-86VTv2mRG*^HS9?r1@#&noVsyy|67l?;GcHhR}->eStYJl4Pu!g zIXRIo5*O3sR)b;R0Bz4_#$7VBI(m2uEr!}(DH|O2mUJBc2Zf1vo1E;gcYn#Pl_N#y z$6_p1lhKQoZupSDwfybcqT}c%?@E82D_SgnVNCQ7!1v@uGto;Jyj`$G?aEhGl0zvn zZObX88vAt$7y7jEU5jl7)9(l+nv@rXj@Sa79~_;X&Q90<2wgrh;T2C&{_KUFBUm&vgBGnd?}`>=D86~P!P(2` zX52ck+9{)Yc^9(~?XD<-&-t`n!GghWjvLfiH3keiO-4=P04ih7VdzaHAXWbt^l zkczkMEHvLjc$$?Yvzd@ZhE#c>L_@-TS$xzQqOTxium$-sRIr^Y6OHm{*Un^L873vt zEa(8q!W(o6Kzk59tGq~mehyEyCk5So*%+a$XB3LR1(DVt{+!$Et9mfr?uHVt?635c zpXVfvKejT5w7r!oRw*Y~I0Q<`<|wOfc~lWI&*X&@`6~B>aslho?2`1ieaSp%$a00W zw>Y)6z0J{ZQ{U2XEiUbh!{|QoI}n`2Ve!NlC+B^j9MmcP%nPf1PQap@F5UYr+MJYS zp9Roz9c1_JSv({zoO}mr1%CfAMZL)CBsyb@+6?c6G8hXuRp`yd9<|^qI^a9%m0ohF zdY96Ub;?giyLQrAp>5m$vdyc@EkHK)7cF05j0cV6+5Tga(LPxy@8bSY06Bm&8D3(J zvxZ)R%1)Z~cFXAmL0gA8HNQmtGe)b*Wdb5Ap{k|7yJL+Ih%_A}%{)$XGsrqInVxzg+E;-iJ6vjA=Y#MC>rJdbV z)}gyQ<>++1a63N7_qJ~0q)M&yUY*{01#+M@#K&!P;X47^mW`utNl!2JcDKgfq~cG8 zl?w(5ki`n6MVDM%D!P3nJ(rS{b^Ikmt6fEZAcdx+Iy7_^RH?J1qqM1I70VeWqLIs0Vg)!g^YwG7(GCgVZyEB@*h*O zqsT!rZ&Tf(xTm9?c$~^ZM~B(V7oB68UJ_=o=$vU_*CTq{Ttx%n0CNI(FDE#fC^u{C zI zKG3&1`v%4D+pnV4JQ$MX?Sn^V2k{BZbBr<9(y)mpe^q-S`K(k;;!o&! z-y1J2Si@yg?A9t*2Yvrz3iE0j;(btDK(=k+cih=BwQLZz3;YSH!*?Me`_sxNZ~jt~ z%0A)jno_bT1UBTnyK>{DGqNlT6|#Guh~~CNkG%Z-=4LwzmPc}e6cy|w!Bm`YYrEv& zfp`~PcBEIID)5u&fGd)x{wwfv=9TbTGqrtZrGaJ`Sv=POv9!QiBEQjBykAR-mZoLW zg1+>8_r58+XkIT(thab1%OaT7hYw{jfv1!q4YFneRC7{>F!_5ZR}wj6No*~_&%)|t zn{1^T*fo-e^Hv1p8tb@OjxVs%uVC{~xFRoY+Du0hx>PU7m&V|lc}H}1OEpSU4>P@a zQ9eY&DOI7lC)^|<`WjisjGhz-JO8JhQ(BXSj{0`keXYAL(@Qtn;^Du1=FTjWvWlrD zfE!|myYj`R;uKr9RXdAvAo+P&oBq+a;&Unc1xmCfMh%ux8yQroTvP1TGUU~MM{anu zJW6WYx5?qj1&Y0;DAh^=9IoGEGMCd?e4b|W_0OUJIlYv;wRLKG96!-SN^z@9>27p6 zQ*>`6e7)6#EMbz0Qe5F+qp9szBpk``nI$}c+qJ@e7z1o=(m%WkipUhyMtbWHSb@yZ zrE2~B&{dZ(g(7c*kRRLi{}Q*c)%{s+w{4KfAtH&v`3J-LDHGxxZ-KK7;*id=3URTd zM2IhAbZi^T=lZK1MdV=vB%a{U`c5{XJg?<2*TMxtN9A)pL_AXr;}`6fZhxcl$PI#lE z?IZP@$thnp8P{iI*((E)R_V9}+a;EJ--=O&falk*)+373F>pl*&4*rrGOi)Jxn}BT ztY}C{^;kK<&pkGghy3AAy}x->r|38%i+b?-hr`g~lZM7Sa*I-93gL(5MCbG74K*G^ zl_cbF`k1`d_p*fNIf|@VyS2_o9E^)P`>MtV`a7EhGn zpfjp`^mAaK^@SIaK}y@iFQT1<%0jMh{!q)7ykY)I6(Tm)Gao&w&EA}Da?D=PV&_k6 zGz$K^;ladE`(`pn?cze(Z`uaj0a<6;ahH+~{@~P3#FepOI2BrJUIBeCI{s_MCS$Vl zB-&|-61?%ZPGD|<4o}%MrSB}S((?oPk}PbRqGWaFL%OHy0XvT3045&Ak%$vmrjBPc8WOQs?3i`Z!DS%EUa)oNAO0x-nb&@ zDm@i!fxM^ZfVw)OXB@t_gFJYRS=y}+QYlfitvU9$qg0iNQd;f@uHK`B!6a-{I`^bh zrk^Lpv)6BAc5GM|~=VtzJ-tDbg%?Ti}-v3~lqx3k>HUEDc zoqIgf{rkstt5lRul5<6rV>zF7cW_83IiFTJo6Y$=Rtn`9LXJzw`Ft40mc(KXIUjby z9CFx``aHpl)x^V(bES(Q+o{ z5kdEJcR=2l;N^9piYmC4lEG5Ln>B;uIkqjon2_P-mRbYL?;8f;vv;43c)JgWY3K}p z(R0SU4(Cm2is;+L37s`6@U6)@&;H%}T3ALbOF@!K!jV7f1XK1N(Vt$Da1t3ogpe6K z(?V^a z>79aU&eVnNwxsDV_fx#xzjEiklrBzjdoGGGuwy=0~BsXr@r8Qx`s7F{Eshba`=tcr?^ zHz(k9^iNMf=EJ_ldCJnX>q2Fw3eX39JNsQaa)F>XM;DSkeB^2hM;E{eVf3RXB^=l5 zz9fbRui{k*_A~hDMiRtkc?k*CyXBMh5v*%y@R_W-L~IMW9S7A)&$CJ`n>{TfhR|zH zd8=)}0{T{6PuO}sC-b#J&F25wYk|1KB%58#a%}ZN?<<9&oVUlKt(S)sb^8wT>Acd!2N7n}p?A>@`+!wNB+9x1#D49Q>_bBX0ux8B6^D`TcKA0#FcsBMBv) zv&UN_V~qxC<4DKM&y<=X)TFMe5P^iz_N|m|_{=ipdobzjR%|0hPI_pKo2wa_W(Wy6 zeZx4v%Q#g?i;pwfQiCHE^yTcl5bs7NGM*3AbeHf8Z~ulMs+(Vtg!pl&tK+5hGnu53 zdPOn|x4k@zP!-538x|jJ{yULbxKV(83oMKrppWD~-wQa*w+vd&B>&XC(dwwbH$^>Z z(A>{+x)Gb5Y{Ns9^K)6 zvZiEDiZseTY9mlW)Xyo%NaOL!!&hIcK5SkWjLea_k5h_fl`vb9>}tRe$pNZ%)6{w|3^i_@`Hv&HMIda>9WC84_P`qe zM=_*Z7WE0_YwJyW!)E(o700d&4}(-U_b1o0$g(ddf?3ILm5K6`B4bdZB9sSZKj4J= zFdJbhr(l<+nnJY?Zai)QC(>w<_12m5ZnoS|eOEo1TTrtH8Ps^uu7S*@)ABXYtN;n4 zlxb79+A``t@Oubo2lZ%f_xMy5 zdwk0Rm(A82ie>5%p%XrfsU4V%oJVIn%Jp9ncAf5;*$ihk=ne7$DGlMsm(d!%o>+4i z5;pc|g5Rzu<;S79j-*g*Yuju5*B*%$f1i)gX>g&M&U3GLm4%&yJ*bh zPAgzo=^$Q4p3gWOzxy>s-oiUZ(TBnz7A3PLXEFhqJ&U(8m}c1+HtLuE3F{4CD66zz zrB|u0wX92Co8hPJAv&f-5p3(pPQk0~pUNYy?yiOH-U(crwER}P2z#?-JVz=5gx&)s8za@Oo;5s*rPDO7S^3ho zX~dcY_L%7z`YD2$Ky9t=FkjElB-N?xi40o`a{|FB-CfFevizH5xfdy9Q#-F2rC7xD zzj40UFOPFrjB4$wJ?k|zwYnZKlxb}0S=l^gnyIV1RmzqSYj*z$=FV0|)KB-u+Q^IY z*QKqI^oWu-t?uSs#HP^xTF>nL<=HUFr_xQ43UF&w%cICs$b=LJ7~bI zPL{yP7%rvzvnzqZuhuK~(4VH~;W6)9forg&q`x-xD?smdi((6J2RUnFcBo4;`MJ=A zl2B8l;}K)>N@_&6)K;rm)I@^6Z}^rK1hUxbdC9-YZyw})nP8uGPp?{6-8q)xX_&G2 zTpCs)knj)JfI8P@!^(`J+#%$QD0MIsl5}uRXfzuP5lzEq4H7o+_TV1_=c&wq?Zdfl zWqg7^%095-$kUQgIMVX^glR0qo)WSMK@xlc3It2u9yG6XkTfD(?Z(EA~cfs*s=h9OJuA+~b^H@&;y&Se%^| z(Gazi{TbMKLt21m_t8Xyky~TmcFV$gXOxx9b{S8>p^0GNg~#Be#yfG#q$98*tfJzr zS5mckMfGGE3s#%)?g?fs)_KhE>L# z49@hgeKr|^Rh0A^9>XMvz)4@Y_l*^sULv&)Cx~%NDNn6G`jHQFN`prmjoR?eE3`X- zE3fZFc~#853x_ZUERhU_{%@)d?6)GwGpNHt;o;a1pG*5Xr)cl?otR%vVuN_@FbyjT z>^FF-p5=P1yzLD*0#@-dff?-f=nMumGnJ;;acR@&46Gt?V{M2pwO;Wq)KqE6b4zK&SYk)BA5a$Jl+%0{$6Z2zIZRqqZNE>*GeFqplbW|qD&gn~`X&VWAW)d~>J zs}SDFmt-DS4e{B3xU{UHp%d^X{$oAgSY*mjOnyeLP_AcEkt{3OkP@u*cf?Q8aQIH} z_H!*eO9Fvil(G3R>!RUQ0(8WvGkYQpf`1@VBu!lX3roc+y@!4pN4|JIWaPZ$glQO8-b%^y<{U$bG(|ExJ30)$*1t&8;A#V&L=lyF zPjVqc6P6hd6oC+BTWpZ2b3e0tWzN-<*EDYo^YOf5XY~(eV#Q{D z^?(8+zevIl@pvTr86SGB3N8(xgmg`h{n}qO3Iaosyo<1kG$^Ec<|M~;RQebxw;Ip| z9)J8*E$mf>xE(XiA%G0lQ#14OB%FcxHbOoWGx;w-tjKt|k74Dqa@c86)okk!)*~@_ ze??x-Ps9BW`6uBxs$bx?L}tL&zWcUu?R-1&IS`=X%#}&yNKW!T7J% z8h)SQK1QRRHLw`xEliK*eisUUa^}EoRq#=qkz<3V(WiS1u4vciu^>|=tj=HZ8-M|} zt0OiKkLSm+xZVfZNNkJj&-Ouu=Pyi)w0_^v>+L*RH$kG?k*zbG&unBHdL_Kou1Xz$ z%~5%#E2N@PvoUglg|bezm@2eZ_D_+$kp)*8>|PR1X5>@9ZtI%T)p}FT!_H30Lx8E* zHA6Qe`HN@m2A3m(la($%#2x#O!)o;0>A55Q>Zo6E-c9s1nE8Jk@8ahbW_u@oD4F*8 zr$31cc#By%qvgB`GEX@>LvpBE_3`mhguKbNc1CWs1av(f8?geofYSzU=?;Z18PyN{ zp#i@XziM@YA%VAMt2QcLfUuM(c`^5^F9JN*M4*CR`WmISnu z@8-a!6#N9SXBwq7tp8BAS)zUx60E5UrGt&!+btwBi5I_5%oKxhu*cMTey>f(?({sr zpZ5%XRe6YJu*z6IP-$yxjjia9)r}aIwu$UY(ep}H zwozJEO!+H zgI`pug_G{2${(te8^lnZB|jy4%dUVFaMn4{*MDTqF;NX z@#a_?U7=_5k{1~n*XwhxCT9N7PK@Wz{#Mi4K;j-Vz3gms|M%N3PR|Nd)3ml?4)aH_mAG_0gcJ8l!ZO^f`En;a9 z<|*PFNQVna9mx}ajp}a;%muWIcZeUMl z@ADC*(mS*dcsvwn6xWlwTAIS}01TS9Uqd*gCOkuUUpcigPb8g=wHS5SED?g zhmKL#pF#wb$J3irxF_`h1&(u~*}YR$jazuY_N!W&x0Q36{@Cg>0?>VD^WG@j4&o)r zC^D^wMzF1UFZ_m)kM}X^4)(Pf`*DNY?5Z|(F(+w5sCG8rO=fV*5|R3Q(c-r5%J_ps z#`{N)tTPMThh|IJmyq8F-4O0$u8ixiYJPh?ul>x$83%1!PnM3Y1~e}wz4UEUSk2MU zl$v1p;a4f}2TExFS=M;1gR}M`T>5YH{A0yZ(xaCsuQ)t`()ogYAE_pK7GuG%j;wm? zZNgaU5{$1m2$DzQj&+lx3H4ZYs#c~vQ_uk}BUGn$oJ?$^F>l>(iW zW~T&}0^6?TzL{J zgr#l8c#GuII%cei!5EDS0}y}%2lPT7%jM)c2vkY4wrQB z0Y*P^7g-csAfE0}hiNm+Zu%p)yiHnA)I8xWm3>HqcaqSNTP59KyPhTL4{9qAl(ju< z9U#u6F~oaOjkE{bv_3qA+r{gA>=QrfYQ@}_e4aUXo>ySE=ybG2 z@#22{NIX_^aF z?#L3f=vlkq*Kg&q>t^YZz zxN1c*DX}eDLRE(Q#UC8GwIhlR5*rIzKSXY9$r>!Smp;I~XMg-@!cFo$--D&_mC{v5G3q5cKSi=yzH%Yb*~nHF z^0a@=N8F|PgV{q%XkpkNrFD?T0UT>L)eRCLnv{5DS#3KQOR>X=h97*Z59ft$Nd#&f zQ3KTwP4M^4VC&d5mU*g3Fz(XY#VWN61*fKk#GaARDbsDnpASA*J=-_4IZU&{b_2pv z)HSf0i8R=HZPqbeImR0I6Y5(eoZiK*?9zsmM;1AJL~O$Fx|ZI5-7(cyj?_`j)~dsP zJ`knN%!#X2T5&-F>+yXZ9|y~nOTClSaBY`&Sl#KQ_S?^m2>n4CA0(_80{LG(7O{jQ z@!y9s1icpu(YLqk7otka9c*USg3+SQ3W$j?Q$Zb+VRma|3zmRt;RKAvh{!5A3#>T z=;USncM`!}-Pw_qS(fvOSERH2#3zZz#CunFrAW=PM*?e@rm2m$K;Y~t?3I%8P$R*! z&rOZr&v%&5@C3I#-<~(qdEl4c1DnTQbPovfj*fSA*d*oR={#o1&&yBve5U6Y5(|H38&T8o<=56KZ ze4_|Ub&pBxpPSeX_#CbfdW}xY*`hJ6H@*odjir?eM@*pL)1_T^o4jB;#SIE{oLkaz z_);t{z#ym#g*?%{j68$ihgGd_Gjl_S&MFjKw;=8dEji9u0S6;98yXq%7n|+LVn%Lk z<3PY%_xC-y82V8377brtcu7jTK%!49KfJU{Y=-N*U{BR#^}ND4zDLpboQr=gGmSs+kpb2w1tt$dv&*b@i|1A_ zTZUj6wZ_|y=-Cf>l|BHlg|d!LfVAuRvba--ZBXVMRpjjI^Q2=?IT+Cdi4gUjtY(}V$ z(^l37w%W5ma1^T2d4KDn5BT!SS;PIsRNCDFy}uKHf^nQkhgQysMTeW_*LWgxpv7fY zHqb1W`0j58UVk6kOwQe?vvNe0^Bc!1$h)SjSRILF<+P4_A;hN_%T3jmwVn4E2N4Tm zV!))F54J9sqoG}X}Zu3>oKvGsV=~m1bcj#vFj+* zZM9zEReja9nZW}I>^voMOndR9x)zuq7dUO@BYVG6luA~p_6!4~O8X9H%dI{kw3L%> zmCcB09({+O3F3{#oCq|L`Kfx=xx#L?qJyU^Q+Rhsow&a0RI)Jq`Y-5x&axjAnK%Nk zfJrZ2{I~axsoC+x_>I}2o7sz}$_BSvt`yYu36`fEz~{8BwbzW$F8zCc;7sgF+(s6Q z=KwiZOVwCNGO+j!Z)EFL6S)&C7)5~L?j`i3kx3z5ic|az=*z5pX1i0C@Gbm=^+6WI zChgz7ss_~^W(b5eQ#es`@&V8Ybziletd*|Kc~E3}C+Xwr9n=FDQI-0wFD51%?Mh_p z?i{U!01s{2SADHq;O_GJIaAN~m?jn!>Pj>i=svq$v!({M8Xh21%@2uHIN;b4{c=C- zrfnP%v}xhwHu-|wW9BA1z|~KxUNvFWm$S&-_s$yyuFZf_ga6~`G!G-oJ|W9IKe8lo z5q&z31|JE-J6L#24~|sK3}JlvV?~*(C2@O1)l!uPBriP)kKEMvng4RSqc>UY7>}~+Y!!7kS0nUrEcP8?un>P9BMYNl>lu2H}LSc41c}8Z?%J{B_Q*u?3#ZKEny!` zRiy~o0!v{eHPEU@7mR;|Qy66H1-}*&*0onU3H^^l#jq;4WzCIJ07sdo$aQ_;Qt0mh zlD@ahDFYD9QoZ2}gI_EN6Cc}8?fZ`d?Q#18(|P$BLwejtj7T8MnY3AZQQfSL6iV)< zOjzK_x;@HM=Ym#X&)R6dEeT9o}_E(i^ z&1OzV)?QP6`qKlMnuo)eZ{N)OGun@T_Vg!Hs(kgK?2>z3X%N3N!*~t^%%AVo92P@6 z9tF+KG-7i6V=rx-|#M_y4#=Uno zy2Abb@`D!Gw`t;KDyL8z3%fKIRLcpR8xBW!J)lN$L&QaCB7s=}Z)JUSCy|q>_-j8t zo7p>YvyDgJZ@=y&c<@MwZP9+%tmh*K?nU#D*6PjkkC_|4%PTj`yn64s%*D%Rv7Tq5 zyjwKZLH62wsz*ZNT^XJw#VMVbxdIS!B}vaSB|%qXw8LmgH>-$fdK0&cSKz~@* zo@p(Klitac`!E;LmJ9O(E1VR~9sCO!QLQ z@1}@BDYH>pkt;ZcfK2+Xke6SfPd~=7La(uYlhV}Oq-ulf4%m6S2jp-?SFGwaB)={E z^Vj5^lk`Etf=f~$RmGyp`|2k})NQftvDZcEsIs0g%n$N`jC)Fl)RxlY-@0-KTE_H2 zbY+ZHW3qmZ4mq%1etjx^D&;ZVhu1^Xy=U`4#`^6n>rh2GS0>C(>f_Poi?9r?tE?WI zH{-q$Q(pi%$*pOJPD`J+$4kWX9nHi+C(n%RYH*IlT*Xd)Q@1nPZjD2hAvFH_ocI|I z1c?N24U7EXvO3z+4=`y-Qd3eJ1TgtEYI`qRHA^>eb0}nMYikb0^aIJ(g*19m3G*k! zCBpjEIx3x^66)WO9{(re^2WsU5=hR5kC}s5$`%KHxgL`n6FMS8nCd^cBBt0KbXA*%sUa zd_-4X#N#JItPxli3?`92u+4TaCMbhDJIZw}MHlD9VD2KT1+s_D=&RlHEkMQdu3O(F z_f%p!*P2eHUEoS&l2qoxC+}6%UnOjZC->}n)&&|vg3N&PI(@DJ2C`<`ZdC!Y?)PL( z`0lz|4_T~3s0y6L52t_htZFpg#w|n49*L>mwJbVlp6l!AF}vugq*-r*@p|Z;a_?u9 zbNpW~Kd7p~@MPasmd^~JaUOGDg0rur+q9w&%I6QBL^&2r+B9_G{dv^yhbzb&&~|H6 zW&=GeyEmhrW#?)I;8RK>BY+od?3QFMWjNkRD9&j7#)RF3tr*~7*Q(Sipd?0)r0G2# zrt@z==u`7t-*xzV5Ld+PJ0{sLb*XCl4QQ4i^UNL7i5vHec#NUk`9+X?H`7=avYZNrkxu@W-@TjC1YVNwiGcfxkT4Ab?V7tBaFwO%Kbg z9}s^vBB6a2U0f3&Mq1-_#ytyB$wShMaXy-X##Nn za;|}R*skRsnmLgL6tny821 z35~o;xTR&hkoyRH?w=2zm~z5WP;z@8b=+lYR17$UUI9;(1M4|-E(H{iERddA;O=c6 zX(C=Qzw%K^ma5z;YJ05lmxLP51|V#dZdii>#Ku#4=l)x__Hkv5py6*@I|4x{;r$Br z>f9?`OMm}Jqbk=A-w@KO$s)~xp$}lA^3(xbj8E>?cPyjCP3vhU0iO}Pg{)D>YV6lm z?ru)MouBH~6SfcKcG%K;zr6J`v!03EqY8)H4c~xToIYyAfig}HnGFO?!+IzwCx~ph zgM9dWV&m#)>aFUm7t9&r1Cxr>LU9!-mBM#wKVs%m+CKsB$m664R7!?|fZn9I?8^(9 z=Xj;6Ba?#4J#!0`Dr_RZ@)PUjivS%qsd!~Qp6T6Xv>-9EIajyq3Jh@l`i9aC!J~jX z{m5Zl*FCc&1&2AXKHC&-kr_^nnfkm%m?_d?a<{t}Sn0IsL^b8aOmw1WT-utGRY94c zJDO@EpK|62e=@Hix9gpQSz4!NGVBksHlsMEeqvgFlpTD4=IYw&C3wc+IG3+EN3W>t z9imG-TBu46vxCq!P}&Rjn=}qCjoSAZs9O>&5+ZBtBRGUv`}$ce4QONprupA<+TEn@ zvu1Sz;ys40p4PxV=-Jol%r*Q&IQ)UbcuEQ1SxmR2v;vX>YtrM$%91%@H0L)Zu~Qiy z`L4ZWp&ME+kvPw1TcC7R!;cATc>fk$+d;~Z~QV) zMT1W~p#yJ)omn%I=*fE2*6KW$d~^X+-#tOS|a zKJdl98|4h!$J${UdUu%qekn^%`7C>wSp9)}*`J(@>dsz7=|S40UgHefG4QZV;5TR1 z(Br&<+|SmZrw3Rqy#r-!J{|nfa2GXmFigkQ>Ws&aW&v|VW5LQKV6IQ#262&1meu}h zA58a)yp-qo{*vMHX1FAhUn%T&p&wx=ot;PHjmhNz2eyGC0_hnVl6(@He`FQ69pO7Nam9%`50nJ9CLrC zK1~e29H~I}@nlB0c)|wP*;;k$*lMM0G{yUmE+{vo_GHZC(xh&ux28D+rAn-edMvn#wYMCq4LaUXt8T137yXm z@+0;%E>AWOVn4fNq?zp@Rdu>5@BYf{FVl4;qWqTx>U0jz>Oh@~>>ic=KB&G7in`e0acI&dgE9e@_{?Kc3e06c@QtQb^CUk($$ zrqu9HsLnkB^))3Y72uDG#+>82bcLGJOe!O*vB>b09p6-~G{1q|6zA8vPBOpIDllF; zI+t~!xg#8sr}vV+s8w2^KD7}dYW`&ViiDm-ozQ!1_I8aQ;(n64zs#=2+GB@3-7-4p zz4EZ2M{sy-I^0JkX`x5v@qoAo`zH_Q_Py(m(=?NJmnQXER=TMX3p)iT8qw{!HgV?Q zlkxU&LQ~n2qNKS+xy~s`w9jEI++#f@7DG1!35UiTQ|k_#xYrXLw*`cTJl=VJ4F5QK z8|1oIn~vuG6TT1JIezrbg&0B>Pdlkvf-Z|%PQRc&P>V{`wfE6wk0qV8dpXc9)-q~S z1iBo9#PSq8hkP`wurAll`#Y7*wmK~CkfCQSoJ^T_G&Tnv7^^U>F~H(qelj znBxljDV&|w2P5TRC#eIyFxNSVGfT~Wvg6ZRi`Hi?ca|hWvR=F>g)XT(sRb@zG-1!? z;8#N<_Skf}+LR7M^tH)m?#d7bvAEUng(vLG>6LU)5dcdEUOLE+&o_YZPJr!| zS<-{zii9U6Ekob^sUapbBNb{nZ-%WJwX3>m)rjg~WW>d5Ia{^o#2)J>#x8iu z*{MyVia}Z78*b7%23P-1*vuc|A1O78-y&mH2;r%zL$?zhYxpwV@Iu~>{m+9nv;`x_ zUm5WSC>g1-ZVK(poyq;UYjr(&=ypx!!}Nh5=S2nb6Qo$+9_O2!KrhIoJCQ$I(iXmi z7^4r`Fd@NB2!9nhhWzFWMU9?^_$%`>_KO5Q>rJ{Qo$w~dGkU~EzeDxT_0&wam;3fh z1OpudXA`6+G=1RqUf`^*Rr(MCyE|k40PGW{x@?6pu=@8YCI775*YePWDx- z(Pbva4R9z0YxXty8fbLsC8>hVb~bu9-ebgJU4Ss0(jSKPDoa%-fR(NGj)KN~TxXM( zYiLG&OA&q!pdQ{7r>h5WaT~G&Q^`TrJK>6?#|+`vwu>qe^+BhyuD&tS%jdRQ5a$kbh+ekNiqK_oKOk?BBJ={Yt)$xTQ95!_%>G zbBr&BWu%azdmTKR(fnz04=u1Q-s~Z(aH3_xIU4~ku&CK!Btoe@3c#>OQv~-+$SF!& z9hxZTREmOW9b}Zi?lEL{a49V&JkOMvkLAU!G8DgSipHNj_Xtc>MqbjAA19oneuhlX z!AhH9K%)0?Mr%uo$<}dv2QK%6bACGR4klaj#=n<%qR|dvQk=g72P5x>UCrbpH57Xk z!BEDu(|rOWAJ)JK5u>LSt3Bj_RooWurAL;TOJc4;27MxpdBlar}?KZ!M3aYdk!idCTOWEM0q8g5MV=yf1QlCVCLOPVJkgy(1EP`ro$dS=ah&CHz1MK`^E*|$FFS5bwDo! zOKZU@Kh5&T=rWaa+HR&0*FOFdx3$LI-xx8JH2b&NOuV3#vS|ex-YYSr#H%J*+NO5o zk9@P|5Ix=Jl_nr$<{suWKavL_6nVW9p3f>UT2WC(;(~npt0nv@DjI4e2@Wf-!&WD= zZa>R-Z?~o)9_v}?W+hHrR%Pa0idH<0wM$!@-;{%m2R}4OJ#r;g&H&p5YnNob5%6T> z30W89h3xOlIuklfqCR0%^SNBqe#SlmL!EgEA}HY;6Pr=RRvaiB4a(HPtI2T9UdjU; z9Mvk`B+64u-b>QAj9^tiX7ui=iyvRet};+b$#hEz)QaB3FW*>MmhwlK*^S1T7*5p4 z&4Oc6)r>FJrK#{@iQ*dH*=5gKADi&eAUvt~6OTe#KivqcrxJ#2t$Fgd^b5f^o4ci< zSNeO9;$gUE{bResaMoJ2Ejb|q8*1%kzics0vMV!vcblU3II2ACc<`TXy}u9R`43G8 zzli*#aSBLGY)=pNHLBr+U@?UL0e*iZ?oFRMbSLe}px+s(emw7B6P9szy&$IEJnX(( zw_JAvyFU>%sk73ewNP!}fNe0$#sn9DrC|i#Pr_>9nHOe0K?~(1(s274!9>xeVWJpd z`MBa0p{G(!?k9}YMv2&acyCQ<9C}S8E)G zd8B3N9#umgB*V6$95E{-evR$S;Gd-_Xgr630)mIkBt8;X>6OZ7#%{Jt$cRgS-U~}4 z{PTF%$86tIzP5z*yzipS1K*N;was>R5ohiEQ*79AHN$#Lf0fv)yN>u!Rw)2G^70(~ z-Q4*iWx!S60y5b7pys?^n#NGLB{+)cGhYk!SjA}9DI4Z+4@d(l@QgEwLw+mg@$uX&%LM5H}l zex$k0mJ113N2!(l`zF&#H$%z3=Ud-rJNuMRE#oiPx4sif^H%aKZFOz=oSE7~Wi$F8 z734mKuCJOv4NZ>T*RUpS_ERvT)M=p)68?9ec?}*G3N~2-{J@`l84`rHDF1)|_?g(A z*w*`uyZ8&EKv&L9HWNqRwo|XB{>KsA(9n1VvL<5R!0s++cDxsi5Og4DXW84@>)k%Y ztGN!3H9r|um{~N>&E!8-1(1246+8wc%qPi1Msl`aeX{X1UsiNbf5E>e5zyaNcPk*a z`6vJ5_=Igme5Oa1Gi*-U+w}Pf;lvdi<$q22rrP`AI1BW(taT`6@lIj~juL+BYU|*z zD9(ScEYwOe>O_iP9Ak(!kA~rt*HN^hDjOcMyjmcRz9qJ~v7G5<_G2k3LOmvy$Z z42e{y`yW;`AEyN}kvu#RlT#b^l)h$&F2e}bj7*}AQLi*G6^83HVuvD(YETN=I?~i~GSkHFdcfCx=JQhh-^yAYtoA6# z!Q#45&B_FSR(hYaNFy6}=>$Z+<=%Ru(E zeJYh$Dcmc+_T0CkCbcTD3O}opNSJd;*0fHJhbwF)ZW5PA1jcSY_$naXTVq?$`R;4LyB7N zoffZSSx;L=t&D0U@I1E$HWHt|Gr?~9;j6>E$t~_bz`1-Zwd6p=-Ersx;WAvom;BF^ zLTb*&k&=;0?GL^4CTEz#XW!wiEE%c#KL#__tUbJ0)<58MGt6sU{=;Hz?uGK8B-KgQ zM#y&0$>lo)`{Ekjtl{G?7DbD`sEp|6xeE3F$02^(gyE0y^?;ub+$TFrZ6_Vkp=9+ zYw%N^KA{By6LPbGbr~grF^Lb$j;jhh{IH*V@9f)kON_I^yC~6vwykt*j(Y;6u)|T! znx|T`b9m-gDkBlr3OzX57g+~6o9>6yUo3ZbiJYO6DJk!wX2w(UqP;6nz&CfJs_}+eEoH^0=)&obDw~&g}h0b8*OGe ze7!4{gi6A;j)`q!vR0YPU6fHh+GTz(b5DDxd|6E97D4exzd*j&rZbd?>YSRb*OhWQ zc@Pm*cr%+_Zoil^KzYe|b@9luElf~l@h3Y489dx-5hw!YUEsNa{eg@H2XDh-BUz?P zr<5{erb@sDwzbbSS1bH?bT6QjN5#%N^z!3Emu_Z~=4f#*SZfXcoTKy!9PK}@^c_II z%s{*L4ih(6WF@|h&~@wDq8u>uda9cA9Rk52Op9^-+OBpGO{VBTeD12QI7~mzv^{NJ zR`9fIE7-OJ`IPWaVRz6?|GT4@r-`3#-)`D7pfr42vF!S-1aU$K4-e<2(+H(DR_}DxMv&RY{?g?Oefc&_9BgPV`JM+)>$_Q#I77#-2%aQbEFc!A+vq{>rRTY1x&n8BzucClt zvA-4%ClVChc$lp7k zQ&!$Lt46PpAB{CNE0Nc%&zR4i7xOTosHes~+1lQ%iCaK!xJLpV<@xe0gIM;nk^|Dv zM8B6&>HUz^gRbMdeH*4+^pAG}K-SbR2pMf&*V_i!qIxS~>8?kV!zIu>wM*yF!*Nt0 zLk!nuI_cAa4}X(yI+-*tr)T5qP1-HaUN#W8SfPK~QYslP zX4ic{q)XWxB4E#aO2E(U2+FB)J=H{%SR?5n!RP&XA>B64aX(X)IkL3)OrO_~j&&eJ zSZ^H|K(}wjwr)Oes$BM&9jM;V(6w9{(^*r82b|k%|25=vV@@i_~Q z;1zWiaSgbNW@3kX(Z_r)AE0_tL)A>$;WxUhhN%~w_?X728M7T~+G*C`WW*psSIYYL zw5v?^N?elQFf>NGZtX5jhNL%_S9w^%GS%N!q{W$Jg0k}k>b440_eH`eeBDRCfe8i4 zW|pRtr*#_1Ze8$XvzJuEIMwXOOK9lER)(a^viU!94VI< z0vU#|r0?4(UjqT+WMi$&sP}BX+HikVv&TNdn@-KM2W$&x1~8f}8k9~Q+i&T8w;6ie zhoq?H^m*b717~lMJye++!x}nATE~j4M-74PD??I6Z8I1H-jez{N?pHtU>#M%{>p1N zq0eIZ-l_h_ksAPEm4pPZsn^;Av#Ch?L4AMfp8L}e4BqUx@a=rLDVx+nWHwY(b+$}m zcJ#c~?MRz;74iqu)@%5etA=UBf!@6)0UhpzlnVZvlPBX)+*`n zmrh>%IIpiWWVY%A*e6dwoJ)^-+pD(pN43*?I4gpZ?BT=Am?Ot^pxNXq!vCXvWh18e zKMpAN<;}z#W1Szvg7S0UqYbfA+JC1S-*k`V>w3x*=*nC&SJ8Mz&GBJh4)_i_ujh7X z+Gyd{WgA@IFtBupS0VmlL?AdiU1!uJFdydh|qlf^(w* zVeTWRd&)ZK23zU?kn>I|dt76q@$6YeC3^?~AOz#dxD*Ue#bC5dc z!+SK;q84>+szb(`K741}2YLf=iqZ&$%vO<;8cYL?o)D~DX=e>aJk6%RdeeDbY{q?W zkM2&5na{$|F|*Y)2*QZPrNs}FuSYjSa1sds)=POSE*1i9f}akJ$%ef6fHs^)(-k|;BkpkU zE?`T7$aHgsX*aX8Y`$@Au+Kv6B`@R$UnIb8LyEe{3Td_6;yivXx^?~KOTm^uK_j(N zrW>rOIUg$Dx2O@Za~teOrS`_9Sl>4}w|xgi!(Ea!YK0EJVdg3dt{!Hy1COo(dM(^` zi~l|UqHBXiD1~s$`a9t#Bf6DKB?eff>gWZZ8J|b-9(#RzmbM|PlP}*yM-_SQRz)i8 z8PUlb*e&o+U6n1~4;!Q8pK6K{7fDf6=W|N~E=VrI8;6R-%hc=rO-yJqYY)IrMCXPo z?0wrhS@=~s{2KtVP!py0_>kl$eX^sx@|~^36c5Sl@JeOK zK6VSv+kEn0QT|~2kfXQeikVKpS<(4SnaU^w?IWL`Kmq29xA5kB7gbj!f3cc~r2_at^k9{ zXLUZYt919)jBWtn)1eurmk=(tevCL(E2a{VziQJaaYMz5fEO%s!~bGtR4N&y*}tE) z6w zC@yjtZ<=N@fC=&}zwUw^Y(x8?9wseAj^xPwub1nHc;s`-H~5sHEU{4F(APJX8W`um zrQ{Yxk~^KWSRS^`!(Af5kB9)}STbl9pZl2*1zQGEw1oV1x2JfwaNpJ77tmtl)!=kl zMW=2Fo&nSz?JC!0ii}oWT8Be8;uC^yK%N%*j%fOO@B=RDSy@fAaaxva?VSLrc?uce zqQj2E!(P{pYyy^BfFY_xw_^NDN5_5p^Vj>M@{^X}EqtZ?DUIo4QiQaKDL`2|zIqtz zb{NlATeu!sBi~jQ8gGO5pDC8{5xh8kJOFoP_+FHgk`s0-;zx*+G95CBfT*QSow8;O zKi*w;E;X+(7C#vcc{&i;{fyBYwAt}x4nIK?R=(gO_|A8M+Iqb?1iVgeY9k_&!o7az z%zDN)xD}edv8?*eM@qzR%;#TrW$IxSW-hP2ma4;g7z*zZw}+@sbu)e*Jui37_0CP! zALTuZ9nje2E768;wiUmk2bcDzWOqop`_WU5&REV9%@>$2k0u&YpajKw4f8t&VhYb! zhwp)_fPdn9D1#O7h~Arf8GLi7u>4+TLy>+}v4(R#F~pgZODqG3OPT=IZDm|nwI#Pa z)W^#4(oZ|>yVX^6JM?<&qh7&#{)!=@2&d%^%pOp+MQa`W$I%NHR)+JleYX79XU$?= zjl7lL7X>pU?+X|=!chMFz790}WJ{)EI;_{Pd)zKi?>@$zCR4xGj4f@?yD?psvAx#j~F`Rbiy$)^jVjVOfE7n!+P0n^{A+8&E4cI4o@ zkvg;|73D|w!Ae7xy?2BOI-RGg;pp0 z3ghSVe;l2AIFtYX$8}UGDmkAjq8xLYa!hhg3UfY`GqcV4%sQdu5JCvac{6jGVOYrd zRE{xo-XzU2Y;E@W-QVB;yRQ4b?(5$Be!riu=kxI_;(H0To)|1Ok{(+=;lFTEvkX=7r8EShynUNB`X8GB_0N*rBK(R$&HMhAg|Mv16y^5_ zX*4>Tn>H8#66=VS3rmitK$O>~udeK37T$@)&uSMEJYE~sfhcrC%l@h@-tg0dgFY*b z;8{E$nH3%6oT<4SJw-PBIrweuKel^2I)wo*ma zu_Bo|=)y@W+RUTr)RX^iBn8lHHWrd%Mb@X7LB#3k5QcBG(QZ0iN`LH2^45OT)Ge=)Sx)8VzQvP%H#e|v zJ72C$=qy$PxguKsQutHr+y#sLcB?12RnaHM3XdtqEyZFhL)2dH!)L?{X?7({1Kf5p zmiZ+n(zZw;sPZ>`Ecj8;M{rMI#hzC7qqrl7gQo4g z=v8XY>E&Kg$J*DZ#t9=>@{C*yxILc`#+5X|tTjqW00rtp!=Y((tUdD^&H z^ET;d?I6SC@JD}0Kv*m8{bj{NV`-swwR7~5y~Wh$u@`80UE8`Vqcqbhc^EtK=}T@X zx#zBqw43N^E)Y4rz|;Y(Fgm=DFtx%``PtQ^yQhwm+%$9~Pa)#s9p9J!ZyHX~^%H1*4rm9*-uOHxpL zyGuR}D)5VK-MRZtQ-@@#x_Pcy@lPGE7*hk<@QzYPtT-*>Td3&ev4v3L-BVo#hS%?W ziRt_N*9}KQ{dN(v>qW(Wcj4TZgoLJdHNsQUAT?b9_`%jC?`{DJFI8) zm9|Lj_Cf9ccs%b+VzS{;x9d}WD-WKQ7I+skr`RE)B~w95-dX8Hob%jff5E(4Ww1)2I`!kHU?G3wkvoc)pubXbVT0BYg>N}O7j8f1x}+O9?>>xv zak*O{+2NXi;poCC-ChCf?m(UG$8rjP5RGbY+!g=iF3UK)MT7%A!k6FQ(>(u=GxP6D zrpz`jRmW#tTNQ%1s3M})8R~P2ytc)$pt5ZM`dZoW@+|Pkj>v4-=op4E(>Zmew|De% zc=bHwV0>%yrR@#MWtaN$fw$P86u_@-kGu$-xmu|T9krox?a0^y=g#NRC=EtjGM{S) zFWBbfCy%>Z89+?hmgzj*nr#^n{)g~wL*kR#lZ?>~7cipZMlA2I_Nzw)@RFwSztb%Y z3*Vde z0&S#@X2}N|bn}>SY?f)X)H0!u*^{txfP;0x-@sRhN5r+%FwA`!bK@QT>7?Qe%eFlj z=Sst%)JLs1Te(M<^A5tct4l^@TjaCVcI1h+OCg%)x0|Hq+aDh_v`UqSOD*51;sx#4 z6_*d7L>Cm`(5^}hW)M5ZM#NeS;A} za!V~~S$FvZ2l3uI;j3QhcQ6&29?M(_?b5Wcr7f=61t;%=#u`~m`x!GvbJ_c638T$P z$eFKOv7s(8gi)Ju z`0-_sc*t7$fci_w>v--6v5$6*^+4-yt0R}?(Qn{g^l9h)zK_!2IyGk+0&nqZ&ss{< z!pp?j_70#V@42NFq63SPWbrI(eR^1Q+v%X*$jz=9i^Rm*j<pr`HRhh zu|bQbT3aId<*jqtHmBaX@0xiUGaSO>?}FspVr%PC<*e6#)GzSgp|ocmrL#EK2|TT8 z2oTPL=O5}!X0@DaOT4O|B72xd>Mxm}Dufxnj&TE`iU>#~ktia!GBbUG{A?l=GZJ*y zfkzv*w!e0KXa32{{+rKGk16R6zoNONs2-RFy)}^_8?)pFM5$4AN$7xZ@ctK_S^T$Q z$wzImm12W?E&^&|PVLyk#!7}DP1@_}yx8~Eg*a$qtP4pjdSB=*Q>!8aXtp&usV2yo zpj!6;SpzB*QgILL{={ZmF#oF5A6e_fRhRu%Kq#fjizar$lwlv9PIn_==0T%N4EMs@ zT06{*UtB+R4qooCC$)>~l?c%`i_%OUjnS(bmr^f#eb#!ui4Z&_(A>pN%^9C7PiSzD zyNKMZPxPc0hVB~88I7=OUigCNO3*p;SK;-KIR{#pIc_|5jIjo|=%W8z_*|o9-WWi& zlunD04R_S-wF4Jx4U+v8#nlg*S>AEd2 zHd3m}V*J_nwpWLA4Pg8Fh`Xb|x7goD_N^#T)J0nQ7Fc#iTgj)in656fP zufD_r1G+jyd@N76wOBo{oK0SXloOt*cK2rG&4&i0)P2cFOM2+EkJkb^2q5IE0%-P#?xhwuwnCtL8;A(fFtuHc0XR}%7-YyQyFvP6$ zI<+t18W_=sjTn)XUqjh}*?v5;t5r`CmmJyjW6XBy4{X2hE5xfKfBGDtLqeVbRz$5& zeuEP9C)d2cYFOSqQ9b}r2OiZW=P3o$NglmoLZ9uNII!HVnj$=f46B(rXiPe7sD#<} zcu2jp3oY2+W2a)-55xdbVo7V;Ap)Ryp5*)kolG>XJzrgg2o(xF!^WI@l?WX07t?`7 z@zwTWw=?@>aZ7RoYO3|cyjFWCsFT<)@brw+$K|H2SxfzAIDE4q=F(@U zb_aT(QM!OfpwLZJ#vg4;C4F|bhg&otqYAp`Vg2`|D z6Tf&e`kRjCr$Sw+_*K7~y*dM5+DQ@T(*S+e?SklhYk`d@+T5C>QZ^5_)hWF>_i?2{ zs}hD&hUpWPmt5fe{nS^zk1{VG&#%Y+B|gC!)J6|Cs4I(Ve+HN-nxmP^-ndM9sM>Ja z?u%F7EpvOJD<(G6=LfNQHNsDn=!vD-!M;ShJgz3TZ>f$}&*?xGbroJXQbuL26U-Nu`g>0ZPEDoIG1jyF(=G7$8pBu))qY%l?p=3#* zYbG^g_r-b=_(9m!T>W@{X8vF;*MJa0>c#ZuN{cySZ>w>0PUEIE5qF}Di+@<@-#1@w z$@R=k#9P7}PQ|9s!!H^kDZ@{V)nsnF_ z!8K_*W=-=A`v^X};P#m{9_Ksv>tr2pM#Rv~E=8&G@hglTTb7UIA%3QP$L#a@lcNu# z#_%mXDTrmMcak*3_L|icn%9~keEvsFPP*Y9SO3Mw-vTJ==|R22Bar3)*k%g9*}FWC zmGI3iYgR#~M`TqV#H?SZ2gHA6rwN+JaxO#G&56p^neAM|rL(2q1`#1w9=;P!p}pbz z>Rod`izDOTbY3hl<*P5qUN(a3{BSeHE9sh0ruo3xO|>8wy{xHn zL#|uq)dgNdlm_4F?#|o4+6@&L;v2JJ39+{g-RmPFW6_NZQ9WRBg=;xq-G4PbD&N6G z9iim-SUe(s1f5Wh*x?W9n6!5vyvf&2cR#@knM;kYyJ*ukzN#&pk5#tAB*=O=)m3Ey zuazZN_Kk1AF8*Xd(y?h`C}e@)>shd|1jB+zhrEqt*RDMN7#0!m$LdXQQuStFWU5Kk z!^)Pwzop9Fjo$Zf_}$B4@gWPjmXGLAqpqZD!5;sJxFsV`)F`63-u(LT!GCOOS$4!v zA((P`aYZ6MHVn9A5ZSfBZX;FCMGeuR%{+mk8T5XO^sFp(vTq2x2&Dh59u{8ZHpWiG zjBS4Yv~SJx*IY(ta{)G`BfXSOSt(+LP&{|dxurx>O>aE9V_OLaK$<;MYVVN*efo5m zZ0K`=DA%I&rA+~GIG*2Y?qeEQ_v<T>8xgk(%?s*Z+^3*iZf2140wa=m!aM}*j?OGj zAPEp$>MdNj5H5N{!0l7y-?9fgpwH7{pb2`Wn%IY@`A@lr}8I9MucsHxE>!u?Q)FR<2KpUx*AFkWE9&8c4WfJsSmw}tRd~5UxP#zbmmmr z^$Oh%`H6}1bnF>!S|td(pZk%MAvbP#PN3b&1MHq?ww@lQOoi$8@>ft=mFvEMdOUr= zyn3S4-eY~5UdQtz%BuXU^1@{MJPble)6c^=|IU0oN*#{N$>a-)?qL1u@sAMROMI{7 zi4TW~6o6cA9H2lp{+1mBJN>8^?UNw^Y|xPbf=oq-WAadpE|1jDA81j97C_IYTF>B5 z1l-Z|`UwuLXFQnZ?n`c!-`5HFh+|s~7|XDcGwJ@glzwN%)gvrKZnyESROJQgum%vS zan0j#PjkxGW!J z6|u&$cE#atoCDe(mZB8TehE=prR0S64`nlPn6<^g2tI=GnQZ7=_mC0gQZM7sBGVAz z9+CmC(J<$MHvG&|*>iW1yldDumiS(usc8E zySn%F5ZUq?A}&)e-IoL25HhlTu2m=fEjQtxWxx7SQ5ei=KpR?_+NyQr>uz<=NeE&M z_Q;ueL&Uo+g>P+*wLd!|R9W0%s!w0+R%-iUR!96`C;mXGDPnrF+GH^d*!nVb{w5oP zWJiXRhr2M9>|^cGz~1lWFI)?o_5T@9m&E)fmV=8SdOZUOI?S?>_EDjsKp)k&Q!kx zN}JTdGa6SAFsFG`DvCaDWBm`M&#fy>e=9XpcMsYm6EF8_f{L-wX@1>SYz;43j+!L1 zoB5`#iJsc&{9T~5b7K<&bkg!!qc3Bak#wTA>+|ypPF)2WQ-yyZ%P55lOrsX=esX_> zE)SBvvFB(s;{2qU-S1X^FV9T)%7N}!u$JU+Gmw^Xb;(;oc*}Ey@~d0PU(y1Swz({K z4>4LtX-pyb3g%6!775$kc98jYF<(4=cr|UXJX?M%tyb(F+rLRGltGzbbZSw)x@yt8 zaw?zYpLJfytF`Eq(dHaGJ!CwiSj0ffXJ@D&Y)jiSWEPo>ixasWzF}P6_Y9J%m5H7V z-SS`%4cO+?&riBEC>!?8@m*3ICbXNkMJGXns5j&;MGAaLnetw{B;Clp=9DyZ*Dr0| zF38bj?3tTavV-sDVB5?~;e8 zeN?+s*ij(11BuplIt}NV{jF58PVNo~fZt5xyaF=4^|)9QFs0rdj{U$i`?1_kgD;<{ z7IU5RnSKmg3f+7$;V#N0)fW8<;n#=r`akHZBY{;2t8^%@Eq^M965R!|%X3kCcxjZ4_yaXN8`5?hbyJ)E$p8^`zgEgW1F z|6}_xGZKxp7DiQgcxXJ|Sa9bfMc7Zi>dR4gWMpgI`awY%M4to27VuVY2Bt za`SZj2RCb_+!iwzx5d0sBEGvtzEUa;IWOH;x@^mPCv;Pb>6g+&}hi7$>lq;v-U@9Nlsbc=WmSU?%hkK-wytLsE^6Iub64a zpC!_F7hN%;l#2^WRalqp)Aw$brzN)N<~F6AO}Lg`WcJ?A1Z_SE)c zv~g1!V&{^ooPiKscI@n>tW%ej($BqY>gdJz*>JddNxrIZbP$U3L6>{b#dpI_ow7pW zFp*T&nf@Z5|JW{GtKBh?t1b+8kaeE6&ApXrVHCuD zp;W*&-I%?oZ^K28hFGdjW9X0^!{5{5KwhL_kgrB{K*H-^>+W}bm&%EJ&bz*ow~)b_cxDlnXv9_8ktZZya#YAQcV1^P*U6n$6lS ztoj*=d2QSAWz;_}Y;*%^JcesQXF7%72LTW-R%-!{CPl>bpl2tvR1}8YsN}I7L5{=W zw@)O6X+g4RrGWlfY(D$Mr?vkTo6b>_saW7qW}D1ENEx^@RKQSrw@I zGHJRBr9lwsV(+{AAKQja7T}Dn<9Zb<#^jjVR6(DX(V)J0|0t)~yZ^2{`j&*h(B1Xf z#1L0XGtg!BDFDGa)nQd`5LYs8`k*C3>{PToZ5YYCgPl^rJJtPam(8?3I8(%>@~Y?( z_xH7G_37{SVsWtcW2|A;)z+QUl|1Of6#KJ(REz_sInHgnvmJYTMmVLzMin4dbZBay zEKk+cTQ;*^Fvm{qV=l;Cke^z1-<=IC`u0((Vnicl9|5e9iaQ=|gy~j~XRy@rFQZav zF?^dg{GFfuR=o=DQk{n(&AzE$tt=w_oR7-1FKvh_(Zm)B7sG}0Tc#SO#$D^ftF91c zJe`eabDq7zYsWd1LSum&;;9eO0ddB8t%C8Njt2(9S@DWRF`ZMQz0 zR#TV%1cfyYQ&fU#=lz3{UPi3ZDlN_PZNb{yWT?Dn8ebHPI^h8}94>52nHdHEo1C%N zH$+c3Y;asKZaC7h-(4omE^LVFOCFrXn;1`B!k8)j5d5;eGb(~8EqKs}>MeBly%yAT?(vA_WsIebQEw)FEl`FLBh zD!<(G!^)g`A2D@}BU5vc6O=Z6tt~ksMSiolXt=D5@7pkhb=l?T^w&$j6-3BmcA4Oi zd77d4R^$t3o^3VTrtPh7H)rR`pCNC~n@NMFM*d^dO?eIq=-Y7aV(2^B1Elwb*UYQg zyoZ9-@5&7_uvITsJcDo482Xz_>}$y=u+C1GuD9Pl`ds~G@-Oj%#WX`@ljuPx}`#kCX$Y%#I!;O;ugnB{Zr^y~y^ZwuF-cdd0O18fsZ% z_64g85eRG`zF>zq^mpXUx=Rp|H5z;6J9Uh|RimgEg7Yo0t|dJBkL|WpSbLD}QFgRc zh~&-^l~XNRS)Et{TX>Qb;G(_8Q>PPCx(qVPY)8?>0J~0?5yVC$grk&o3MlLgTN$tR zxpwqXr)gMUY9*)1uV_5SvV63k4&Ew=bSm=)(ZmEn0|AjRAbKvWZ^{XC?31+kd z%|b?*(Y526sumds@20D(dG(ManI7#!IsEo;?00)spZ4hlue_x;Ngp1Z%u$vqy`HtH zqd8F*JE(mzWyuY}G}qu)DAjO)lEmfLs_a|)lc*07 zB!jOfU0)#{Z{eTlY?5n(d_&7eG?zjOKYD&dhU{EMKhi`#I?xUQPJlJO>!qyTmapMZ zO3HG0TCVk-)Jpafm3=FkHeCyKTg=M`Ys=HGsL=+6m!hBMI-}uhrX|E-a#un4v52pO zF|qOgYesmP6)m;H-h-KefPVyYoDGpVY>KzS86Q_Z8NDyn7z9Qv7P5{_Y6~(sey9wG zPB~m~9htcI>nPS)DIjeOzunaPC_y$%^ISs&a^69di(wqwr*89SkHN7qRUpvVlHwf; zNyxfK^%r8xF=g!aGQ>;67yhXI&xo_lN9Eg&9R*KY9ECJzfeXSFM0q{;#5nnGgbNwo z)5v8^A5duUD(3y8T&7;RcPL@jK5oLnVqxek#jW7%)e{9dnCIGOelK9fzA{d4mnAQX zfaWLpH=9~*OFS&rirHEBDERGg)cE0iIj{HypD5J*g+DLnZ~m`e43-REiZ4RQ0Y8qw!1xETP z1L2C`@83Z^-dRg2&={mXIT2j|n_RuD6Vb;JccO;lMRyc}y3WvoAb52=wH%DLNewM! z$lvHI7p^`sEb~`R$*DqFCm~5f<7F!x%F3*>sTKNVtf7C}|FN}BJu4^eDJ^>Gysut( zGOf+cnw=HJE*VTzMeB>^0;M?|CwtUz8SI;l$5`8&O6_0jbe=A}R$u7Sc^L`IS&s5- z1gMPXcGTuy`*GB)U_?4FnXy3ICb0X_aVwk!mV8_XN&|5@JnWmiSHVC8?r5b`)9$`W zJ=r8Z)>PAO-c1RlnNh9j=dNGy5ubqGGr0d;qktJ%>j_KN!z zxU+xjHe`Ri1NSasaYG;}k@DdD0#!H^GfJ2t9=Oro?Vt``j>leSy42Kg(JXeY>dGG(&6q5mTc{3|*PtYcjY4&K*HpQH@OSD70 zjqxrs8ogdGzd+;R(H#Hf8FPiGE|!CguY|1W;V2&PT(rt-1m{5V$HGHILdY}m@vN?A zSO-Y>3df%GxWGA-Rq|D54iJS!RRcKkvCst)9T~|{B>ZvqbK?|zb3B7)zKxYPRk#3f z3@zQdL`m7;D zV>#870d@}0bva2ZHiOC-w?cv)es)zoZ|)s>oMI>*_UO|zjx|cyw&LOsM=XQap0jS2 zq9FE&q3Mg&y)94GQPm@O!U2RrXB(kQci=eCJsNV-35m_UJ;j~=-f)$qXpOzwx4Vf2fGVT zvXsLWI_598*WjSO;H-5Ab8h2ndnRWF)sFe|FGY;Tp7PlDsod@Ng_>XD;q;7YUVSCH zi(&zMfPpgag?>l1!Cn$Z_~Yh$_AY$VEoU+Xf>Uj@EpJbeKVV9s13u7h=YYJuZ zepU>qnXF9(DGaB!E_AoNU)}eO?xz?ngd_0A1C=aZn2Zp~NyOOJ*f`byKemI)K;#Um z*$1pSir>XBCaTcb+Cy(yw`aERhmezb%M{zc0;ZrTYdT_9C(fH5mnY=lJB3IT_wfr$ zm~H)!tp!`E@b;3WZ9N&o55w(93@TC6KH?GB^{Kj$H+nuw`eF+qaz~Rr>M=4dJvJvS zr>mtrJ)FqeaNYIXj!Epv_#W@WXkzFVYyB?<`8rZeMj`Ui+A4v`%Wd7H!>!`rVVnIY zu+E{*z^?ebF_h3XjftddFhVzte&qgM_B79?KuJ+g5!#viS}j5}{^jp+yP>)pfYFpn z#nv;0_h@6jv)HXSd`FVdfhrL4=-1aj&B$aGIsb}F1s+bw0elNkFTrZ4=f-jz?K=^o z$SzOW1*!*c)b?G+WMILXy$pOljwN;!ndsLW(xL{>5F#Y_{1t85ubkEZPp=vuWBha> zKY?oL9z*zLIN zk(9-|p^pcU;^!`2H2$5l-t+rkozZB1yCG?pi8`D_{M+9JtmrHKh58As%K`&?tWgq! zkaa7qGHJ_`o<|FZ5>nB&jY)ILH|Gdc7_kA7to^SS+71Q->uFoUUNx`x8}z~bCa&h} z%}v(DyE@6yPZ$VkQnWobMG9vN=36t*tkd;825=ttF}0f|kauC{fs}*( zelo3R%VZKT5>V7~N4a6v*=yjhJ&)9J^VG*gRPQ-DY#4_`#Wrb~mx6Qkyn>P1#%f## z0zp85)~~cw%iVs^`(HC<$>NN>TGssh5q%V^ASU}vKwvuTF!Jyko?%&%mTNYytgOVW zTA0`BcV4b4&*3TCW#pRYQ66use+n7>jH3K8~sqxL+HXG<}ZpFzmK78r1WmAd} z>J#AEqy|X#aN!OMw-tI*_7@jwqB!8^=U#xOnhS&U8!+eCRz+8{v?n(YliZtTaFC$p zoKRK_YEO9Gfk%A*Pcl&9tM^@yhLVO6C4cPtlcL^72wRr;*xq!iMg7MnX5coSW<~vT zf9^J5<%NfxpZ}C*e+l<#;6#lTe2Jb-#Hf-*$HKm+o5uO1;R4Z26PwQmTTe&>Rrp5S zP#1+U*z1`4pviXC`$;2i2X?S!0kwvr_oyshIwDheS}J$;O0I`X-VnWnCAQ_hPbo{j z-?uU}zqKcg5yBsjdLrx!DN~XplRva1fd3U>#i7JE)4&!rIBT*y32{sVzB5(=Hn5 zzvSFn9`gI_e`ozjCTH8_+c4Kk=&PgVrFU7aWA33YdFQ{s_Ty3$uGBKb_)T-~a36f9 zg>2(`QkSTf_9Ubsxw~#Mnp$;q=|dn_4f~cn#JdN6Ura&ohx_(#``(suzwv4NDcBb2D{wqnZIm(*koN6&qJIpBA*bHf9H|hf*bfi7wxWNhwpK$1lB)6e%zD z2(Nb-WAZJ@~wo_TZ49O!J@OmtxqtogyF?vHe_FVP*e`^^?%V5)RCqw4x zp|ivYtg%o1#tC;WMR~ZvBUcx~V^{oyc z{TO(G#H3@rB0fpOu&Z@E|QrSk^FNlU<4tZWhx+O z)G>>ns3zeZGRFN6N<8<_n%~TR|Hmfl;DDH4DLSY+vbbyQ;hpoUKTEdC##{JU$|vUB zU0fmaut3deF0CM6y7%X-sY~6a zjT8ECdNZExFAy2fqi-tw4hT-mFJx@VkLG<^;a44`Wh@^iFu5?Y>XU!1;Ww(X6>kmW zjVd$Ga4^wX{D09a0{!-9$dwkCVj16Oo4!wxGFM#`-9AJ(1YE!W1oT{alpvPxP@8_{ z@62V0cS)Y_mrZz%p#`YW{+;2pY^zWC(U&Rx=6ch3?A+j?(>-}LsR6?~qYpQ$Fv8LI zezc0gh5t2vZuA~2ZBgLk95a1i>`ia~<@V|6sbS%Ic-HKPxhoOXXi~1aBf`s5@qXh5 zU<``g3ethyVfs#lmU=zzL;mifc${zLTn(WB(C}!h?X5%%uZWmEuJygLa`%;cU`R_of4?sP52m-QhaZaL2kH;=|vYcmdsG28z=v#E2xE=wo=A zEgaf0b-VcUR=Ur>*AR($D+1n@%`8oR68t3pxv2W2&y`-da1^gvC z)8b`5bw(M^N}cIFZ$L;HIGAI9U-h2S=G<&g?EqS^7;qqyKOFm+(mL_DXV<94q^|co z6c@Ryzuxrz?5LI&vU_BMM<>KuRb!Q`SyL=G{p#^=%Z4;!aqE*!CnDLhMQe?X9F=yD zJ7Ux;oMKj$h;J<4-nzqnfjU*>@h)giA(KOGco&m3zDYl`sooQT{9=TT-g{r>t3xBMMSY z@L`7EP*i5S=g*Ew(*h%r$jC{`$l)H?EhBYFvE5u^rBt#=Et~TjNnCBHYGdQ8L?T-y zL@ir#iFubnkcm9;%5boV1WOBr!8bD?r@+`BNpqk+e7yS7Ab7s=Z4 zzsGj4VTMhUTM5pL_2G|B?}>e??Mlq5GU9q)n>9;(+1P(VK}=Z$J?cDZ^|0P(g&a38 zUJvmL@ze?!FZEI?7RoA1w;m6r?q$bQuaifg6om6|uC~VQ?8z?^ZOF2GKN%CDvOkFZ zd+^Y}UnBU)3#h(wdxI*sc;0z*oaeFuv^Aqwys+nm2}rgJ_MT*VEiSsrO1fSl8*q%= z6+J=(7y?h2{Ii?^07e+xBGG`Ye-bJQS zEg{)&tGmc^QnS3g3zu8o^2r>UYbJpavLNh@&b~^H3k=I!Yfqp0ha+PpX=zKNC+GA; zn-LJ#y=&gNA&7ZDfu{nxC#p|J7My~f>2Fimm2|94UV}tr?n6(Hbr)Tvo8)C))(H7Y zkkT{=|LyNfBFs$YgvkafB@^9toy~d!M&@Ns>m)mK=6-uPJDFG9zbawU30M5cD{*Y^ z6x-AEJDS!9uPW^}vZz`OgKD$dAv0I$neCfAZ77&=@A9L0PsK`Orjq&h`pN~};7UsG zT0|nz+O|s^ab`6L92~+1=8D?7Jty3g1X0W8!nCliur#6*M9@*5 zAm8uKyZa14G%XNJCbzfVs$lqRyHxX6ZO#(<=ka2pKbo8Mi1W4icW(?eN-HIRR_l6x zbk;Blt(i|U9o#?>nxfK)#D+1=!p=g__-;M#zesRp*)BN8+IqG(NIJoK&i{_)+Let6 z{nnH&iW9N%i1hXRvBcqq`S>wwUJ-49sza0Z5WM2ixFIF5IOS6++G2aN@CeX^p^Pa{ zdMtE~>tm8yn-4vq|LuL0j8~9)ChYFjOJHV>y9Z-LCm~eCwst*j^!Pi+ytMuZc_Xum zDuUz|sqyS;WN^ibOM`PvX~wF)j`A&fs=mM##-NM3jw(;y;OGE)cctu%iqGOtdKx(+ zY;d>MyhTg>3FKHL>A|2Vb>8AxtOwWk;5%z~w;mftYc?7`1H&$5Ns{oIY1qoffCeQ) zZkT&E2fzg}A2L|7tV0=*!_@nKgoikO3fZ`K$x+esF;MnMnO%^QdagWPYA8D>MI!DZ zxU0!4F9s&xUh|$ZxE$d(%)D@Db)F5}b|iCm$wBq;NJVO#CnLF_Br>Ed^J~^JD92uD zLA>HE?%DL6wO7Ng;qb2qu{=#p={*`6r!vAe<=lAtvo-Qo*=|W}N*v1eG+@#8a$Lsg zzv)c8hP%?BCLvI@$96UH)arCDDfVaK1*(_#c=zn}DnG=eB!*%4waX zYi+4fUCpuU$rDYp{)YVGi3yzq!B*v+%PWG~wa<`Pe5QMSj{M0$?uO%5Ko6dHl3VWV zPIh8L>akzzmA>la{M4+{e6J>>*e74vjFZyCS5&nRy1lVVK&?!I!SW; zSeT)?zmXJL-MM>o+^bsUU3*{!k(nIw! z50I!mmHjYNt}#gsx$x=warBY6;TrB3Qz z2M1w9JZw`j&BD9j^@XLM--Z}O%4mO6vHT8@*Fe)vAJPWcu|u)ed(W%b(tzTG(iU~?Z?WYst)Ebng#)|oc@V126o z*y}1CjoCzIdh~zoaOOf=rP-U7Gm!7sHVq{7*+SSclEshZ_RZd)1Tmw6--xll?p$+7 z;x>7vA7|mc9RC2G(^{7owD*Z;aZPjThxOf3$wQS^4fw$ppO5t~G(}>&`d7&X@=_Py zE)=+~)D$*&t) z(no#FH{(3!Y!<|?w;Hm}T@#)LZq2!5-nFGm)`shHCz-g`qo?pCYjGbF2-Kf{-3$g$ zV#F2z0UU15yrSfha1bzgT%~aD9y~s*CM%&eB9?LHycl)^&*JsYwNiaZEM3DugW> z=)Nv_kQXRccD+moKMrI!@8KkNlPgBI}g;g&hX`A6`xtO{Hm z4eCx?xkHCgyZihrfU}bht<1~wPPtkd-8b3#Yjj{?zPB86g|?l2(dZqZU}?%>vzxB& zv#TH%Le20tThZ@mm$~+e@&@U85s3@m2x?bXFKwkXxD*x2B{K@&%oa4)Gb}vY(?DP9 zYvsSjME%Px@>7L$&NzUDgOmDxS%rx1Z;EZ3op)f3 zWw-)(f=_mK?$UGWZot4u^VM_6T7>+4W{2IO2kttR(Hh`l04URPGd2ewo08N%?%MKz z-^SDVh76<%I6?A;&dbdk`cYDDUlLn?{3|Z$S6Z*B`cXC1WbN6d9J!dXA2h^x@DX6w zFy-)}G0BGIJ#aZDi6|1ZTWy)KPAoMOozV^@Ww8#2(6mH4a7+o7#992Pa$5}^S)hC2 z$I+3PKU=PcHaKMg?FSxa=;Rp@Bh0O2=cNw{qNXv6#LVaG)8D6&tkLlJWU6@%9cfryjm|40mgtQ1+Y>^;c?LXOd0L5>(e7nmNJI}~sF z?m}T<$a6eu^*=VE4(lAcnANAl%^s(qsTC2nbyvm{VkAW}w(J)jVGaT9{*MIAnS8l$r@vV`waOs@OhSjhV; zX+|SK>#6p1_)0I6Cz9CJu8H3+@4}pQp%Ja>12bCB^95Mw@y{4La(>!B7=e7r7tA=c zn2@%PYp#w7fR~qkx_RAh6Z5^3B>jfi~%VO?Sl|%mv9Le>i(zI`%2RY zUoffQes;}GAT^`#wn(o??^qSn4)`4om{9>D#qb@pC&_=dq#fF4S4UQ$mL7fGkfB|r8WaL;{!x}frN->02x zzU;$Gja01eL3Z*NKQ6++9&tQ0f@fdqPY@$KT<>6N`<3%AIl25vWR;Dz%|q>Rh@_HU z7#bU>ax&cF)4r{@{51cTpUt&X-nS{RFEi$81MLoBGU zy(x9;2mUz?%1}TR;$m1u^utiiIO(I`5_y4S1peNcfgwBxV!_HXlsVYk?$V~u7IW^5 zGibBuLqAZo$AO5?R2pHptq)U@KTdTA{$(cE{wWJgOs$@A+5-^ar^&A(U~|h{r_=XUzH;HO0HaeBjgMr=e~V?U6te* zF)Vk?%#oX|5^^qt+?C{<<=BQ{xpU_n=00=HMwm9fzt8Va*xv8Y`}KOiUytYW34FS_ z1b>Ie?6xA{Y*ZZeWE$Of9GFj1G}9b7YVl5n1T3I~LB-2;rfr0BBR{R9dpS6H^ zW9Pgt#XP&2K5#V|~_1j|ubcHfHc(26zS(f&)}5R&77-?tmrYIic*o zK(|o~fEo!G*Y+RVB#>%ys@h2Z(f~Y)Wj#FniKp&6z=iKVX|))7xD1l53S3BOh+syZ zQpDvL@rz;-);OBLyWYgoIr}F4;2Yni3RF!HSzp)rH&HZ$!YT7sl2DzwfVaNFh|fW@ zCE4Oi2U);*T3zO@`&)4?-_;kOP}`q~F6GyLp|%TyW$uf)B6`xZ@M)=66IV@^d*R>T zu#p^GT5^R`O70Wn?1`{RTIu3VoBa9gV@Kwh)45D&HK_yfCbK%!ykkx^XWb@8%26?- z=f>v-rS-FyT%)6NR*`zhX*kmzIW~8GOp;br`*HrseC1=kEl{=}2Gq;B!1g!Ne?B!O zg9@S<>_#^RSJNLX1$yIykM`_(pJolY^!;^Z=ewvYo2C;<$@o5Kp`?I2LV_Z{h{5Ok z&U>1fBHv?ExnVW=(ZPtAMi_7)8WAjB2}BET9c9dC`8)<%zMkkXC} z;6Uhx;j0;-vInre{^{WF<5|0EM&}~`51J^pz|aZMD@p|UhesT1%--Q_fIZSBC-%?Y zs@Mqp@yfdr0(#&%)lmHqJUAWlUWp))3sd=Qrva=u@$?w0swg%xJ|p#P*>Rg9$jD{D zdXUn{*+MSlpNw)iAA}CB)Xu0&yo#^(FqKr${KKEZQF#9si9am)(~N>|-Tz~} zcGCI;i68i}^OGUVB9SP%M?=xitW$;21FjErC&=uL@5B~|KUd9#PI+HChT7k*&@r3* zJtxpZYe@F8?6h7ng+@4>fB-KSGa7QM--E8&mdTiJnXukEnL+2$cCCXD4B7wK+H?lQ z7Yg}0MW0ntiV3M9yrTvFg_)%5wucss#V^~YP25Wp9`N!v)egQ6d}-_wLpZB(kb7Y= zy$*?Z8EKul@16>d)=ivQP`Q5jgbnMR$#JP=H?>K;8T=m$SYGmm~#1!^1jg;IX`^1~X_jz31k>}yem5GaDO>58wUyall4qrcG&UP(q zQAv>DouSsd(PtiTWm~sfg;)eP9}V-Kjux`*=&~v!&+dgKbFtSY zt#CI`dX{w>s>n-)+Z@g`j>88edM0K`M1n80;t2Y)(QG&Ze#c~)H@|2NPOLFMd(E#_?le6K}Y7_j3GrYCzxp(zqH-nMWk(8u?0l!A*pvOdvIKR=t*=Z;Ub`%a|q+T z-&YOk_58<5iO0D|j5v{6CY`!u{Te*AcUVAlejF@^*9SXR6uO|StO&V&bM{ed&N$mO zL|erat8ZUpLvUp=QAtm0*LG)DVDMBVn;g*2QcRxw^_yI>=2!c(@Z9Nlr?U(cQ{xGP zxdf&*1eU_46Q6iZ8)mdYOog0;rvkG%X0;X~d(S_DWif`CwInykKP7=c&a(csLH7+Jnn1%XG>^uy3^S7|+Fsa~Dq&H3q6*nZ&cNyv*-- z3rb9ZO@n-~Z^GlEDXqv`wEK`rhO%LTJoK^yq>7SghnC9hx$!V5nlc&f1twEU-{R(-AFW&Kem;66m9gX7k@b z$pG>iJ&zgn3Y4eJsupHy{{2(qg}x8}Su)^mSe?}-_TX`@HDij7aB3Why^H zRF1+rDi11R9={qXBxZKgz7B>-=p%p33o7Y@BA?Si$x1_0MdJw0sm|5UTw;x^uV2n+ zxqJ-lSq~C|dhIyQy|lc&GI;_F6knNcW=@beRx~vag9(CyXTaiaF{e*8gLIRQcIH~z z5u(rFYCJoN>P@8CNU}+vWcVLE(j?*2KUj~6P_8u9-}nwh9P{kasRrHq&2)sUItAb|(J=I%dJ&yHAf$OUcWI ztUl?rdN7(-u7()dv2scLKemYmus{Tqe!(R(1Lzu0J-5WG%e@M32~NOP|6?0{s*(9q zdm%5}wsW2!lcCwMB|NbtpZr5jwMbGfX~)S*OV@uOlFrk`Z7Ib1l4}vS0t!olNsvR# zeLV1y@)gp}F8f)K#Q2*!vlIkZbm}CzIZe7+mPPL5;hC^__dswbta2h|SLIW3NElJr zK-uU>hJ2T+GwMR4#H$wGpN(QkjgBeRSeS*XH(GJnrglC~*nAf*zv0C7tg^;Ecim$A zI0bJwfaG=W2-7CWi@V8+X~Q@0I6!$PZY$S27^+JP73EyY=?;_{1O%8Zt2RL3qSkT5 zZ`-O<$}ql|eq-oKOmTgjQ@rnoWX6-lt}~P2qGYtGDyrgA8F3BX06yp$iVUv!HkSUW zSn?8Fw$dOOU50Xz;Dxj=h_vk~z{T1q9hI#tT-Opr=6bcB9zX0SMp`Axr8gbY-?#rh z^B!^Sr-_W#A+`^3CDOEo2A^%x2ub#kf~uzvPR`#Rd^EFfmVLT( z7x+K6_~@NqD{jaj+EkrGwd%9ePYZ=yFxNfryY=H1YqlmQHh2^JMXSMh$J_mt6evYM z!xsipn(%s^DCMs*FSp#cT&8eWlzxEii8(1!$LD$;VwR0X&L1N_Q@(ZW?+5SfT1}n) zxK=le53&n3-2=+{O5&R5n6E@{)0AcE0g8S>{wBs9brY!TCw7E=-@p8HF%|oSeu+K~ zVtABnOs2`oMcj&mueD2w40Yui3(yn9=8zRu{?;`J?Io!xPjkuT`G4>EkL@nD2=HA4 z)kzbUhT;WtbaRR)%1WB^2!ua%3tVn3DAfDBy(f46!eWJ%RWMQa(pGyo7$y-eH~l!7^hC zFr;RG;swbAMGs2n6uu^p2!>q|jGDP}=CRfWzHx{l&q;AW_BF1Km6N&Pgn&Mw=lj?0 zUHwMJ&0c`bd1j{%-ux|#7nYU&^Oa#XY6;7)U5EEE zyA2{Ewl;s&f88%~98%iQ-^32oU-locfA&z-K>TM$a16ZC;{8FFw$!530tGvjI#*`)Tw)l;pnso!OY_`H+gzT~;b^Q9}TkcsNgTmf&)_@d9y9>Bd?<)6m zQT}7Y{`;f3bGgfEhqG5xM`_;D$QWn+cb1vukBWbX)j)j!hwC|dK2tcK5Z#}q*-K1- z4+#z3_wjbV;KD>7q0s4+iL^OBMC4%NUTxIu{I}>IN9AXH)jyWB`>S_-hkpzth727U zaYz>6fEx8+mC-{Vg=i3xZ(?5MYp$Lwb)Tyde0TOP;0nD;n#N*Ug3>0ItAgE-w#CQGnIQvrZ=anik7sp`o@6(_9!CxXhf>^gWI~|71xj=+Yz_t zI~T`cANN>>w%J_?2TZi%$t%|LYR3Kj_JlsJ>H4YaB)Cxh+Xlyy*y}vajOSSGF_sB-|5+Z$oS3_%OOn3(sqGc!Wq;Av z^+1=pPA4IPY`2}HsBV!J=eyObpqUo|T}Lqf*Scvu#F3YRm2*K$0K>?(dJ}4EJ!8^7`joUA<2x zENAw35XG7UZy}^~Lcl5|q_?jyBLJ1b=2T1ZUo&g8lgPFUL4b#P@A`(7TglrE)XB>g zWlWQ#$1TQE^1YW$uc}>?1XctBV{O)peP0(=ce2a>(ypdj4$K}z(tBidnUBx%orlGE zY2K*f=qG6o0JDCVO8b7@H55sFDEHJ}E=yO!=~emnkz5D#d#a8VRRh|>Bc=mJtM$dC zI=i{~u=;Q<7B2#H9-n1~_@-&tICd_95mee`5gZsdIt?2jb0!d9vHGq2pm}*I;|fXD z+gEDkSmnJHq#5SY$DH2}`d$-eYt*A*3T8yF5Z%Q_`fr=^*@tdslE$U-3KKg=i88sd zfXP_<53pTU|Cok+Wb|bsGOGSKFq&1i!+igaI!&$WBdmCIb4IB=Y}zYIjU+W~@)MM( zf3Hx*Y7Iz_<85F@r_=8%wrg!Ti4fPwBB_Ogo|4GSEn(XXVgH7fW&Cp5Js_~kx5ux# zYoK9%SB}L>PeZ;Vr}_qisDvBYd@vuM^cQ|nL~D}~$;?AN7vW;~NRWr8BeV9~QRltG zKgp(YJA1BYG$bSIEznErv|>o?h^wbtd}J3W;v|(UIaeq~9Pq9+8Mv`y?Y=l#wPcLK z$Wk?{`P(vL?oDIrN2Zs%m+jej5o1OTs}ndx?=-L?3v= zlUkbJ+^c+;s!9KVf3>CrFu`9$S^&l};IV>esqt$fP+2t%@*GJPP6-v-O~^nlzo|(i~j7I?tpYZ{5Y7(p8kEQBrLng5XbzSSQbd9me>}aGGjVhz->koN?iguC z(fVywe>0#i>muB5xFW2;KAEB))Rt6maUgP@>7_6aA1RK71-W^=#LwskJQNBmxqx)I z6cG9iTdY(`UdwLr`rNhCx5w(1Nrm1|r0%rU0sWi`gB(&u-k7aq;ae&yR%h zlbln@Eu0vK93E8owk-H4HTemfYf#dV{ul0PTzT+@RsyMgR%H`DIK6L++ zmyUi(BByWC#(l+#PrL2&Q~$Bq(nI2_Af0Am{_6_fm~#{4!4O?{2LX}5F@HNyjd{Gx z$f=%w79z~|cT{K7k0JK&hocX>tl|ukbBiwSq;5G;=v&{kkCK`c2u@;SHz2Wuw0VzV zRY&2Mi*^^Tqn!*x5!>jc3J?eDQEcy?`sqlESB8^3x~cUN?2K{i6;I%rB{&pUAp^&6 z|NE&Z;d4>c5j6^avo&p;)lOPdsN5>Nt<0WkuqO1_bYI>%#EKdh=PR)^B!IKq zbu{L)m>V%iqUf>`1Mgh7qzcmpjzNSpAMBvB!VM=GiI3RqD^!rD|m z1%i6Sc2Kzmc`5a##2dvPNfAanJUznjsa;qr;D>5UXlu2A=RQ5k%R4HsrgSUl+j+P{ ze|r(jHewGet`+aqDe}6{A6etUSt0eiW`JyQ1Qbdk0e2U@t01RykA=kVw4^AX+f02} zo~u9=&OinCx7ht1t$QU9jfs>1Ze2%=TZ^RlId1ydxxYqy)Nv!Md;ac?hk~h#@&7n; z$t$Vl9budGr9#b`Oo36`pGE}n2PdzB{#`PB`c{h*+(^~+XKn3A9CG9?6{o~48PXzi z%<=-g)9ibX67h!lCJK3F7AXzac}Mjsz9i+>-NwKG>wWHDOzafml=Et&{HHnJ;UK9r z8G@JosBg6?Z~l!H-?r2gBU^;iJK%Mmym*MF6PArTdV(CaCpMg$1ZeX8{P1bd^zcPS z-?`p`B7*&4;Y(wj<{rEfw`$UV!N&e{- zMp2hUU3W(X=t3yLns%7waq6>~CX)F+{=$ntk^7fgL<%%7?dNQP@7!+5$wl!s-9Q0@ zQ--Wy^ct;JBiFV30Z*aFzR3n>jgY&sPhJK3{S`k=|8Ll!lkyfWM*6bgj>@9!di5A- z@eCf9tW*raYDvnk-4DpE3H-|<&o(AB(Sb~IM@{z`qXg7KUv-^6Nt?GR44>&1;U#&0 zXM@fOS|wozTDO5FfZqA81+b?(j1r(fKe42edvT48NwK($W8vw`etK$l*3HMsMdj6W z&7F7}b@b4kkxJWjqJ>P}!B|qPW4S00EiTn=$=Hr+(}sBWRBQ3~2#eGs!2R~%^Y|T+ zh@wV;#=n^mmE*7l00zCQeoUknDXbk zoNQN7|2_~uaNz0dJW+_PchV2e$lU1hhYg4MFJS>rWtIf%NsH;t35sS)aw!&XO zBXfJg_L(PrK1Xus=mqo-hw)Pd|#gui%({oOusB@ z5NE39-+dW*BDYW#PM$B|8l7HlyZx8BTF+xrBUI;wo~<6>@yyz9NrOb7WXq~LP9BaSS&lfVSLJ9xyQd*Z3?@w9jfPD+}`b}NaDpen?ZA~<_++0hy0h!YZ zqqjU&$~R1v9MwT4BIfmkRNKC(mC{)jByiBLtrGK|H*5r++_LX$Sr{>jL;7j%*e%OH zndC;;ITmWHHR;$A*tPg=5Yz1)<<$*j^(=QLiGDlvKQ<$oB&KaIQ%j;6)$v!?c6sM- zhZC8`5voRAGF++iIAdDx`)sT*td)e=+9B0uVh}Zun20w^Gf64Ksc9xddPedqWgyr* zU)yreIPO{S3CsIRiJs}g(NAq#WjbsbPg=(QF=G%?>fi{uQBlW7$i=-}NuEjJk+P`| z53qW;zYpb7sdrGIU#^7n2X>#bpAG;MG;v+iDua`co<%D|WdYfT@5D6a#m9h7+O zOZ1&N5$K;9xgQv>HtbIX*G%?8-<>=6mE*BaFt*gUPJp4qRN8zS8Un7RBjRv< zHn(TXmtR~sRGGPWYlxlE_#7J?kmFUDyf>!-vs&MML8<`({w~iH@0HY6lZNj^MBGA% zKpJtW3aH?iRDQJOdWss$_=Eb|bXTrMOqs6Wy@#pQM$cN@diOZj`G2jm_^?Y|IGJww zUGBaL2hBL&=Q?HfBvapEDnc`pLZl0IWBnZ^+7a$5Xr!F#i}4cyp}yY`1W9N&gRB@T_qIPeMr@hx7mURk4>xQuapvqB`doMv0TjDk zM1aJ;^-248-H&~ge{r5;4F(m`n**v)9gG;DV)iZ1&xq%Ie4w_OM!4Ohb1w8>G{Wjy zFv<0>z3udR?P=#dvD3o!J4Al_MgCld5r0Zx=QGH>y#w?PJj$c0FzjKE1bf~q6CrHx z7AQG9=9QF+qnZ?a5BuI6d-jTHg&*r#V-6^1X?YEmFM!A}U0G1U=4XoA4j0xNw@FXD zN4K9|{GH)nYVfJXWOS-VJ9%*5=zFiZ6u;J%Q#y@fN#LdHo#BBpui!nitQqp~&hlos z3rR$&Mb$}RDB1GKkxbvXHuKjPV|v2g;G($vVVL0BTtCuk^TLgW&4tyQ9)p#j7`ZF9 zSO#Ek6S}J}&u}%Ye?ko!P?t(yHUCvQE<&H(HG?M3iN+rD9t>OqskGR@e!kaSF~zo7 z(T6Na=svIF`hA{xyPF|aKQBt{{}bsxR#!jP>W}On*t^lA8}a_|EYJwvXll&Xb~Lvv ziLG1o+(84H;#a>Pw%)PyZLd&xnekFs2y|ciUF|ZJ{GCL50PHI~b73yCMb6PuCpgpQ z>jP}gvjv~493V|V8)Yu>_V;kEPvJHhZ6lh#3R3B(VR_!u&6+!AXA478v-(&a>|_c1lmAQg5<~X@AMYA; zys}xJL0HhAuP(FFezh}b+NHJDB!9?5e~!GtFsDPl zWx2>Y@u!_m+(Oz_OS!)XKq(KCJ^xWU{}#a7NwEI}1o$LRk^lo{le4K4!JJBi{?*j* zQGw%n@G^qDhW!Vp&NaF88vCqZm`*voOoMjsPOJUPNGxH*-?M! z4j5R#5pm(3v8;O)Gn3we|2XC(PaF)2@@8~}%J~^Xy*DEzs|fL+g)ccV_)iqK*xn~% zS?l{R?nUoEm(d-!D!lo{Q!~ir1if=EjP81R(R+emt9ixS22b}Q)8&2LRo*se{l4{^ z%v+{lL!v!wR+!P4s!}>z+F!EPUJrEl6?{31C@(Yb^+Pb7+_8JXX-4@F@kU91-g`@= z$wzdTLr8S_*~SZS3yu;>gKW;z9*{218t)t6wXDLAeTXY>CEfu$_239|)$;yHkL5)7 z9O!FGE&_w>*B22qJ$w%_i`PVnunP^1MngqTds>9QGJwJJxjXbP=*20l!mnn-FaO5t zTR-XSvc4_4!q!y444iA}KY2lw96`BD@R)|E9{X=p*OA()Pq!sjr(3j6(w_6tc}_VU zm$r7)SrkXTlDW;!bZG}Sl}-Qp1yp#`v1th?`={}<--YG&+VP4bmPC8=-AGDk1-F{~ zZFPaP@|-)emHlsCg6{i_NTC2$%Hve-xOPH}2#X|j9@#R-NC`w6x z3&mw!^AKsp(s}iReX0p}3|WO{t$i`Y8`_+T2ji)~2%Nf^-E>VF?w-Ikb#^L-%{1(K z7Y`tU4=xg>q#of}q#cVpiITF%qwlCOa?D__ zb{#pth}gAs)Eq1c=_R!rwklsYQq^r-K?o!cxr7ePCjHiB0!NGyIxGg;Aj1WNqstOp3~a^&!tya+k#~dv%XWe2s?{s)+Bry_0i{P)R>3A?{15 z_7fUvQu9z`1muFcu!+ySmWe5!*&_e3xf$^vn{xkmW~s)@J#?-(u?9AADjDiwel0W@ zt|h(aw94sAX|OJcOPJml&wTt)yBa{6XjAEeso*0Z5(z<67NA@dMg zBi^uti8#Fy^}v2i7wkvoqcr&!Cs$hj3cVCc zY}M4Zrq@l7HBSF2XEpgugXHMwN##Rs{K;FE>C&t-E;0E&;_3s^_h*(u+pSTPXN(so zTGFy}gJ&rr%Cz6s{zget3Z=QEl;ZJ>%4Dq@bH$z68s#y^!8tD>A-(5ktX$na;1xvQ zXJ9UARPTiBM~@^ku3P_y`zk_>&C=Il?m_OrNGtDP38M_u_U>|*76)&^)88LP@^Yr$ zXSSUCic2##Ijl6Z1>u)7`Alx+;pL zx(;cYb*tMZod1=Yq)}oGb&39gr$V9@bW7Fkv zO6U?@9ec%5V<3LL21|clnH$7?bujmxaXt_`*Rw6Z^=#B4p?c9p#VWAIbA`a--#3P! zlIBFJV?M>|Miwd$TxVbZCM1gJ)*YYKG^Fu#V_%<&jfgnmXh0E*y}6e?G0u-*mjU?) z+!LvnxqcG(2&ioo2X3{cxR|vRqZE%!J23&X1WJno{5O0Z+dqj#yV2cOJ4qSrC;4`q zYK9peLl%YMzqiF?v@aa{fMM1?M`%j!G9iwIKrE2r=6J`bIEjml8SP*19?5 z`p#vw)el^C^t7pUwy{QuL`4M1jr1o2ZU=$1Jng~7rC)*#K2SO1$00@EcO7X7L;Lv4 z#UWILl!JZq_0+6@cV=6gsXCu6z`3pm>L)&`0wz=akn|+ka&ZPMAU7h;YvxfBj(?5s! zL$d(d3+8AS)GXLWco4M2?IbPFGiajn@4Z&tuTq!wq2b5gAQA82!=1C5Y6gVWIZQ*A zo}bRO#0PZ#!9+>znftl4s`-%l(sk(uWO-i0)ThcZpQv`GOQhcLsh*=(V{kS-@g5CW znn*Pd{57NG)%YtDdM{MI{ngaft#I$|vR=g!Ry5RT{u@%Ket1Wn2>lachwmcdl0FAq z(PkUBG`|9M^u6d`4b{|Y6EIZVaX2%ohPI`;0nUW=oTA7n?6&ouS=#6hLZ;h zY4?d?x;jj~8C_Bn(~#WX0_~GvvZ0;-V?*0c^!X`OjsO`nN`~CWhX(_ZU3$viL&dEg zLT@ZBlIDBzKCyUcyLt1TBbdd#kQ+5^ycwoHFKh3U%ZkY@oX^5DbBcE`ZZPP<{Rukt z_46)p*a@r(hYOzRGIA^rQP$%)C_@fk>8_I=D3pgEN9`X}oo_6{YvENvd-Rj_ObF{d zjp=au8=$NpmxlW|P2P)r{k9KPK~6hKj5bLw?r8{ zs#?de9ZJQMqM24lu3}`yW3F$vp$tmlRBnCD-F(r0pY<|oqYkJ?xPjU2-OvOQ}m;z^nNYG zE!$n?z7y)ouK~kr)MUrh>})(RO8=!Lx~^AYGHku{DM`*Y2=XrV7teMa^X^a7pG`6- zRN2PiHB4`hq;KX-QCleZ`2C+9%hv-yR!-mNt9M@?C`zk@eE6Am<0}ObRMLri^>RPc zB5i7x%p8Bo{6oD%U!>`!6gassLTP6{=zKs)ekaJ+2L-D@jV;eKku-) z@suo=j2Ow(mn*Ez4|#=F=*-5<^!{XEQ-CQa)ci->DxfG0NbtCm2CJ!n_1h+uWL3zY z=L$2J0+&ulQJ#((dXy(6H;@B>lc{#*sC@KJZV2j+26xB#2vN`Tg;79_%+3b{Q3iJ+ z!Y>8!^Ev1kk>nar#sP1N^#Ytu0eqZ_&PFYi&Iyk-*)cUX?H^@(9&S~X#0-O>sPD%+ zt@5Gbm4v`GuO|4z0Zs{z6^6JXe zdSVTIiKVn44vDnqHS z)es2jn2H$#ga~Qs)4pBk zRk!coY6E1TWimf}b@^aXOXdV!7zsUBvmHG3!!1}0mGSI*pK6WH{hxh=_2VPg!jZb5 zo8QxAQNAB_KUL{R|+(v=*HGzFlSyULX^J z5V^0Q7c4%SL}!-0aolrCzAZq8Rthrpq)<2${m04ZcQ5oEo&vP_`;kcP%*qi8QL(cx z)6M2mjewl?wNbc$-hGX_vA^sTL&DNNRiguC+tMd@bWAvsc0Pei1g>s$7A+StZc2Qk zAh?l(+MY@3Xzm$EDE{}}&Zqjuq|c*}#BaWb2ULhy- zuv%j-KlF~Ha(3vTZFqUPZ_x33*=~!8&-E$NIGmwPL}F5fq^#SJOmyC_!>TaTp4nU@ z-SQ4RJ~>Equb|6Nd z8L#y_<4~(~2$I7ev?ZO1-nBmKVTj9?iYkA5G7&`iCSEj`?XNoPEi%-f@DU7IgW9x; zt`)AtD=x>oO*OnWBOJNMS!(SjxJ}!kEzp-MR!jOTTcC=&qj$?Pb7I%ikkfP0P1Oto z>9{Z5{((VDUW;ETd>qG)O=Kb6^}gg-As7#(StlbDPE0A>4I@SHeAo2Sos~_ z=$e1`y!8kR;X>zYi+6F(d8R{^W9(1oQ2z9xL|wrkn#l5MEye4|Vk5XJ6;g-a(^aWd z`7pKi;W*KBW_;}%Wt49K)?IpbVk$zoVz5jydoxvmT9m@UA5~8wVUDfqKfx#mEGU^sAhyI zlaF&xzVReC9LNip2`~=NbT?Jlg9HP*yn5}fC(CDpHcab!MAMYU(h&J}?~0t8qs(m5 zG-8~L;n;@p5apv#VaW#dwhZ*&k+f{gQCDwDJrh&??lRkTy4e#~ro_-uMutYsHieMc zBj)v6jEEtM#LW>~z#j8;X9|p~yg{mNXlHPWrYj3#s}vBx1NDAtGhW3#(K$093JOB* ztv0Ttgj*@Nc_drd2B;yJ6#RP3_dDJKE%(d*h0oOb9@|B*MFdXgM#)f*KK1royomeS zx3?EytoQ7X2ocoR{NijoB(zX=^3kKf*0nSvo0uc25j1;>tn)yuVV^ z-sXUryx5ZI^5a6HN$O`SU?f|Y_D6aFk7xqtzm_vm)kr(tj!7y>i9rtG)C}shNcoo# zvuwotOg&j2*!vw#R>xNQ;9A^(0kR`F%lAjqrPOZwFMyw$#Aq0@WZV8#b{v; z0?uRte)$;UQtEtED-v16uCQ1BtoQ*He>0|!+Aj{C#8M#>FV z!X^b@)3>JqX)*TUbktaM&ikt)%fV=K9<&NMYN`3XW zR`GXz6(28oDbE=m=Xyv`Q(BtFRLZ-9fLE7s=50DUi*U3(ZWY&*O!ThR=mhsh4cEWr5E|mQpBS4iCw}iA%9xqMQuWI3-)R}T zlb0EGG`~^JBZx1=rlw45gva{ZUF;ib3wv~$fA_` z-G^iRS3Gf-Yi8(c}&Nik&LPx!KCrKLP^YyapX9FL`c5ffbUm+roV^@vl zi0{`wZlAL!xTm=9t;DY+2NR_tH2HeE^mIn;7psJ)%}IUA^nlQ_yk^i3`HdMXO{!`N z3S~*PYVN`f)AH+3%7|;Z!6KfioPQJ7K~2F|?U`8K{&btZ*KGII_$KUU55~P9O26e%<6LwqrQCA{D(A?QyBPXj+akZ_uKf;;gf{@taOUj@Y1^UQzQBTvH=q28z zxEG1R87N&v1=W|{nLjg0nK4!;y-N#h769FJn=#c@I`7rgdbcj4%A+Pbuxo#6W-4~U z6al*gCk{R)S`g#~w7PiIktSzF?yFXiXjIwL7iUKK9es}et?@nC^JQ)|`2TQ@yFNbo zSC|;mfpC;TptZc%lkeOJoN1miw@G%M><8>5$DtoK>O%$;?q-0c&;gCxdSX!~C6I5m zYGwbiy+m=4qdV0P2OkG-4y#b=(*&3w zHC3q_Ju99$uXLLIfY$X(-EA_Zd?w)^~yiT{n}jJgOX|t#LxBWv`1}{}K^| zO$RNcHI6+fVhrji_HlWS^j1fnxJ|uiZOnVFerQv?IC+51Mb0LGGis8GQ&dvB{Oypu zj1c%@vndsx<>IUK{cv%d=o-SIwcAsXc;o)smk%S;ZL3y2luSgHEB%}J>m1hilN{1B zE{Q4P;RpJPHZ>jVfLZ%AG1!OLr@XltVEq;xBJnOsR6OH%R=vV^=h+qP_kK*X^~*HQ z>aCn*b!>E_@f+Ml>4Lc#QyJ4G^!8AuPOg-n>4BE|=bODUB87Y`h%iM`tJ)EXc9<><;;{rj$K0~t8+y`Ef^7g<;s?_E1}QF z3r|E}h_%IQUaAV!ss0JuUZfEo)HbDr!r_asr@@+;`HWWg6{e@Urwy$tcd7aO1IQbf zdV&q8G4oD+9H&kNk5jn+blF&h`bS;7zR*dPzU&j^H17sdl=dYH73EUs*<3&7d*>+m z`SIUc@lyuM^pouc>T+>ZH4{WZbFoxLp2G^&v&?H>&GJ+F_u4)z>+)?3d4F6aMTZ;5 z0?qWj+S=M=f4<^M7k=N6Kl_qIPe9kUcAnqe`HwB?l6RVEyT&Z0=Rov%rMEtu_p_@@ zKS|y}wNlwO(E_2Zo|PhQ6L)FH8JEm^V7QppVjUHHz8s^Q}a&lH?j zZkzTiu6S2yZHo4Q?Tqmn2klw~OOA)t3mK7V7eo`*4oU~J zmSC+o+nq~Ke9=A6j#~UvTbGKa8Nt?`(+?thr6`3NNcZ*gB+D3eS=m0A#NY@<795y3 zvHhF)jfA_xs8~>rzg)cZ;BKVBjUN8y%5vwNyI-#g?Wss_6NEt>cd;33&z2k0K|iS& zK-Aj@=PHN^>@w33i5;b;ew>wf31LQ7N4b;HPZnv` zKkALe3MZIDcWeq+oF!*OWk$7@T+9=c8>NP5%EdD)M|fYZeaSQL+Hrx*ti%UD0r!MfxwLk(&iRk4wuRNo?e*iI z(%ZFRlI!bx4<8kM_$y0151^6wSi0!vDxtyceH2_smxtl?AP%h)*o+$(RwB{pX->o? z;5o=iU<(n-9@ExWkeabIWHDyjvu{`U35BsMw>jKn&L0L9QlQjF>k6a02NFK5*nvhQsxy>mv{dNEckm13U^*X zyC@G30tlCyPI3D~tgGpdqj(Pe8{>Aw9YQpDi91Y^l0W(M9K?B**%7#OH&La`tgF~d zoeU|=m#86pGm|)c$B0-;mN6@s7+Q+W4mvlNfd~xa&vE)Yj?ailFQ|lYfaKO!2O>P% zfcNs>aoZ%OLTH~6BVNizJ1)_e|IXHh&nX+VqOMmWKflaWPBV*y-yF*^Pf${_G^)+f zd9_K?9Q=G_b;|!^3(AjBF9z4A*-3S+WqelZZ!g<4ztK`)z1u*q!9>)KlAIlt~4;?{eYGV#dX$m77*D@&q|V#DXl>Ul>vVBsalAM^{6Pbji0aCVAJ$`vk!$S*t(& zyYw2#xYJ$`hpsT4U`n@*Ie=|BYIY0qhP8+`)z_OWx)4#%U(z%s-WQm*``y)|JNK3% za%fq9(8Xc7ve70y`yjsLyNQq&n1ES8+T)$K@I2k=4E-3TD z@9%E9ZFkl@AGXQR`|E72S)eZ`!h<>a(+FgbEn$ot8E5A!xifVl2hN(+W>PP%i{rlk z)c7Ao=N(Vg|HpBC>zhg_MZ+pYnc17hH#0=tYlZBLd#^n&DjCTLAv;;wnHQIPvp3nf z7Z=yaxbD5ib+3D`e&_dhf21DHIiJt#{d_-PyNRWi0&nS$7`!v6v)IkjXVVH0h(9RB zuED}qWZ=f*ei8nk_?*i&Fvb;E-I#7W0YwSJ_m)*fKju5K9lkH}3agG42olUcE(GmC z3>KEt9A3N75OPFp;`tk!J)t!Wu61p7N-U~=xGoq2)%LH=3>Ylc$T#}=c0}@#d+O6l zP5sap_(JW+eu8h+PD@Hj#}q>CkP=qk>O&X6NrGq?HUeIiI*4(pTs<><7CUq!k%utE={D}hkh(D$0`l$Jx&k=ioL7a5DA zIDgKdyypf@xV zV9JIngO3lWr?b>#3Vh(K|^6K+)Tu7&R z$@Xt~OaRf$UzSL+8=B()%Wu}>*j$fDoCcfVje;aFo)8O{G#{7 zOzL_+ytzua1(3^)skoLJTTvDGc0*i#C#00zYr$21s+z;Z};(`}=;ATk!J$exL))k-~#AD4!+| zEH&=V!2GWCx4P}Jw*|dSyOXZ0GT`|}RkFR#BO!)znVPi1`J1x~%~3!_LF!SgtRxu&PTLEIQgp)l&b z&A8T>w4fwsvKHat8OQa`T>xl&4o>SFdDo2l%aS-@^S}u#%cz=YF;3{mvLONo0R@zS zqxSuK47P0%A}%bLfS8NFaG|@u z&KL^wIAizro4&m!%fo0P5chfo=YUe?q3O%JdZfGmGz?qbS2i`KSC%VPNWjqscTfM( zBkx6Fkr3JJ0Zaw4#oY`o$3R9PpSob?w0CDUGXD&!T_Ux+Z40b#P~C1I~ zIItxYt^@nXjY%sbXQdt+1q9I23~C0g^Kdm*l6foX<$XQ*Ky?wOut%E*?uI8`q!MkX z8f~m~KUbRBz7%eAP{zI;^}0XzbGz@yDtf8>FAE|jF`VmULf|Yla7pm8VeyvL=i0H* zGZ*3~9_)fnjRvg7sH$iOvT}FA`DdzuR|-`^tAcwh!=r?nGHAIrU&y?x5^#p2mNAYO zC~x;2TJw~`qe`Em{Wab^(-O!h}!eZRe znESg3w-W3doHt-rp&a!o(g1hgnQ7n$X@);#e$&#lo(n>DXRv?W%Ja3FGlAWNsL~!_ z=R$K1){$dW>A;>paBcei&2ZKU;*4QFmmx=18O)E%IqKOzN~MzLp733SFBYBN%m1Kt zsgHgY2N#-hXoMYHjkYlyj1tn9HcYoiejoKZr2*OQ<7u_*D=Ru~+hMZt zVg%5VcI@I^GEeGCn6f@eGn;1;xa)lYt9xZ<&eI@ci=+618fj)$ga;>6*#4{JN7euMw{!L5!S)`u)8r_BZw{*B!2@^6~%Px-So}{kk?--Jn)D zLNKMsbf^n*y#~bS2Pzuoeu$IXdfJm>7M)ON%-cTCS@V{B_qwSR&!id>bD^O(+Y`R) z;!ayY3Vds<>`41uy@q8NK5b6Ud?5k)7|io}R$G}g8xMcQY(rgVaFLBhV=6t6{uLU* zq$kk5;NU;!PqWZLy*V32&s|-3Pg!4)Hn{8)u6IZ(HW%yyDQ*W#D>Nm9JNv6=KzAiN z4uH)Napg|ygS~8Ub3(rO&iJmy17gP}2<{Jj9OS94--7(()iC{IY3vQvyP9sqJoLek6DV(gOJs3xO8pnS44p=u`n@@ixL}97t*#>o1&K-M)fbys11>Yu*ipI;mv>4dw$?+>}EH!b zb;`G<1zgv`&!Zx`pI3i*LJMx~gt%;{%kX5zA5=sLP;W+X*hy!63t9%9j7i2;xRmn7 zYQEtQ({kTlr}B~yJToyn3H35TWKLjnsp zwbDgUSJ-{MZM&xo6=qsEANAVO*?gd&+NjJUV^OG`E|6R3Hf#H6t~)2w1=8P>&Hf92 z@#{Z6y65Q@!2Hvs6KTg8l;4%$?NLBYX2Z;liDYncuJmb821IL*yMt*)%=bCL$*Xk^ zs#-1<5oAD+b(lX(6L;Jqz=Q#IjsvV;sCmTR2Z|Q-@QSZP$NWvxP z+VysemcP5a{dSY2rrZY&bnZX`R8}s_ldxLwzSUDrwh1Z%ZIKkJ&?mek_-iL=ZT306R(c+aD?e(*Y-c?Ui zCB?C3CKSZsu71&k8Ji{&#ZZAE8&O4x+7}KZ<^-1)V!DZOSL}k`3IXTP(8neXhLqU9 zEWX~iZwtl#I1w^lQYUQApjH~44RT7QW7c2XZLNO>h)esS)o0{_g+0m{!{s>nfPt~S zvPueOUZiTT0n%a~&`XO*N<2v$KbcT_sb)uDUwP;Tql9WVgs&_(p8L^zS@un{puu`U zlHUhjNOHE|{lP=kfwAJ3;^N65;d*nqG-YGs9E5S-Ebd3xuVzyC*S&9lS&CksLqO*D zUY!*=_Gfr3u72+AuR?l+ldXv|r88|}6z=B99fphuM6vbd)3tG%CWWZP(;k~#YL6N0&L zkEbdAQvO_N)kQa5EmMiIm;@qDsQUlK2&-V{6C#P+7w%qpzq_*T2H^Xop=`Cs48p4V zuvK~9g1f)cXzi@w;&|TFyG9ZX20s{B)OOfHIWBbmv>8r^OMw@p(L=M|MW7WgUXERM zQ#Ke=CXt5nv@gm2=OHx}&q`w8LMIcWE7E(_k$jxJ#H5=MJH(|q#Sutmm1X+flV^j& zeeSEPugt#$8J=7SBMs8c5c)NWcW0K3#a=%y(dB!Gt;HpVwNwkAu<=)n*^|J1MuN_B zVWC&*3`#@AQD?7vX+gbl#eRaECoHeSZ!zQjW}2HO!RpL2@+RIMTspNPym`yT&u+^0 z`sOg&MoP$>!t}+OuI7(koB3w;<$i+4(fGdMK<%N5E4dMC9;ruo_(z5<%2RF&&9sEDs*@&frgk`#&_#(E4$6-NgysdZtjtU3p z9W6A#^%Lvh?|#LjY3Af$ZQ6-;S^%T6Lr3lAS`~+-TWzDNs)Vd#nqz|XdTM9{SIm-s z2f-+Ay3plGa;SK@@?cS(u0l_P@+E>@TIw1s!)14)SlB9f;)zJUQm3<-Lk#T>$w*|WM-XcVtbfb;BfChQ$kvnjz3#txc{Mcnz?gwl~cMDPCP%&8oEO| zd$TlJsU=!99E?k!9|TzdYhm*s!vs@|lDZ|Zj+e1vtAf9J>fh!{dzR7xQ|;Ia5tXcc4w_G{;T=&s~idpef$O?oQ3aYzEQ6@&XI< zc!7qiAGCu-XP>xnDa`@1@AM6Hqb5vVBr2e8#|46xxdma72rR0q1W@)#Vt zA#olNxyAFiAfW@l&cqPkoL^4^#dH#{;|GENOL}=TWiuyhg<(k!)uF=RKemqIQNCZU z9o?Dr<~=TbbS=-L+}aJQ?JJ3O#DqIT2K&mEW_z@+DH3#7h<#Fq#y>)Xuunc@48C4% z4E~bii@fX9u|$$xY}Y`XCv3RZuCIR~Ry^8tpQC8MXFRmWk7%v@Wie`wGdu%&;`d2w zE{EA!niI9LX}Z0rFy6+gI56!mp((BMASflYgLhbtJD||fTQWRt75(EcOG0$Z51O6&>GA!b`gzlT*}+l|I6$FzG_RT57-AMeu4fzV6{nHc1;hrmOf}|M z?DtX!4^#+XXhGhJ%36@M3lo{m+1zwrPIVOLPTlTKN0Weg;_Cz%-Cx!4hGZ$BG>7J} z@>x0I=2xo;iY`Ccmy?q;>jWvt}- zOFO$Xi0tR#(p)e&xoW~7(6gnvDI>$fg8+jU)(H@x3yLo%5;sxxv{r8pM04~)W(Inl zH4)CzTTawZ0Vl1;u(hC^TxJMW`5~nlAVF0&7E94%ka(~fw@JXM`{2Z#~G6_ zKarHzkHsOc;!y)zyvJZar62txe2K`l&Ru$fK(NNaCRjQvxH?Ne)rX7>05+SCC)*Gn zu4!73KLO>+3uAoIUoX-Jcm|!{K$64v8qiAfB)KPQqa>+`LZ}`MmT?qUpnHQg&%_`h z*|F6!Md`~e?a*_$yFUjuXG*hrRqXABJ?En4w~xG(`I3*H{rd&tnB{T_34JLX!AaMR z?7cTTvw8E!K43L?3}gq%DBpN;&tsT;`3NFl#%2h~d6X2+h)X{vo10|fpMd>omLjy~ z<-oIqyw5B{o3{}bQ%cNA%Ru;0A4`fR0Qxrs8s4%L(9R48L$(2!hSPIWWDmpZb|WqK zN50$+?32?*ll=1sy?FXyvL4AW3sYfxUiJvD$4c3evU0SrVmaFRRXwNu;WTtP6gE3M)P`K))H_ueX{tqV%}g)A(NyXpuEXI-x7|C>(d*cRE$)$ln7+erSWQo#abf-B>@#1`cN4WFd zHpZ}zx+75FM=NnrzcCk%SGw^cKLerCb4#@Ki_VBpNuSI7_OR#N5?6>rg^_&lP}*;6 zseSlXL5L6FkP&g25*dT#rgL935s)|ZuJa|$l=sDA6zStlSJr8L zf=a$KC5a}uOMfcA7p_|>HN9}kEp2+846+hT^=-Nl@t)DA*}SQHzeQizjmPb()*%Kh z-n8b>?aFe%%~5diimkqaqJRgJ>9QtbwE69-QW45`o9?6TVcEC#ce}Z zq;c(D02H`wrXiZHa&(96ZayDzXn{KSkMQp?(5_$_2(_`W-Cs1mv%1eWI-*1p)`8`Q zJEr&fnu|8G%iRK5^73Zy62>%6_Zc@j`k5)=IeP7~>Fvg6&r!B@3Rcx-rPg@^vGNQ6 zUxm16Hft@ov+)K$>7J-7FOT57i<2qXoGD2v20j$3fe74Jaz)>EcHp%LKcRjAZZ`k%#A;dfQ(mT7(nUm58_h{8Mr9%C-%tdgRfx zbYz9K1or|0_T@^M&gE`VztOCJj1gk$)DT7ay z#5sRaXW%bfxbi71QDV(58c0t3wLb{Rp^@Y#iDl3U=M=;Kk$Q#1<%b+!{!Q0v#%ub5 zQ2#LWrZfb}-}ZX%Rf|p%i<_V5&dK%H!t`P#_9eXkvJ`~O`1|zlDc^8MC?rDenBLP3 zblm;|8HZhqSU8bFi!EHo*REG8kH~dzufx#`^YcEzwo4#3%UsY6I4(Jjckok~1@9BGbPUy|308?0(~p`l)?ttFYfTq!_J2{k5oC7_hl zo1CpnSXjvU+h%fU^*U_ra|l3Z>-}>zu$*M4SQKBGotY0?ME9 z-6E%WXc@Xhy+8vSx{KJkFj?YrT5=|jA}u?LW*u^z$EjK_lDIPM2(|<{J~665O3bFF zv~Ld)wLOT@q;kxBP~7OqG9=?lLy|Y250`F68vlb`Io7AEmoyFbmJI41@qn6}A9Eox zR~tO%Sk~UYOf1xJt>LDP(Rtzg6XA;Cb{9{ig3SBCM}nk;ZH#fT5Q1nnN|h(5fQF5IQzEQ1{K@iN ze_2=$eiPdsN5D$EL{N`3b~e}V(`xsQfQ2VbxOP1=DFW!?*`unWMoPB=$2pQAfzUK-9_Uxhufi)6?~`{yN@X4MvOf{#5v#Fw@E- zK=*w7ePW8v_A^|20wo%x!~fi{#d<`GoO!F+nMlmU;H|#u)&$hkC?~?5D>CKI1@EWgMuQvkI zs*TxxOs$0}Rr-PI>q(uM1{9D0Z>B5E&sXb-?Djq7ILxnYYtet++5$v+(HarUxEpTU z-ru%bp#^+CU+%mvl345iGI)7XRWYA@rO!&RldjY}>(9onHKTJ0+6;;R|HBw8!a=P8 zw)>WnLwZJANV+ePNJLx8BHlXvZs`I&?ZPG0Lv8qmhHsMN%OrwLr5(eCS$kl2c76b9 z(zMt1(IR6A+Xlz(>C4^U3UMsu)*4!@54pXsIevK5Wf#B5Mr}sB{(?WYkMO=3oqo53 zOTlx`v*UTR@NUlA-mPssg3fW6K&ho=dq9@F01l5fK=*-5Wl%K9xHsWqL2A4S((0id z+?`LL+mLlpFJ4x+ec{DYkt^64^ka=HE8}F|PKm0y-IKAFIHk9iZR^+{%3@_3&134w z7o*~8-4jxWk^_PnUQsD`FkQZKJD#UfCllQe*Dh6tIwyi@;Wk5PH)va8$g?^_xh8(| z0B-BR8nMWO(#|S*xhSj{9cd@&Jq0$J|JJ6g1JShD#U6#fRF^is7CE91ll1CeSEhY) zK!-ZQ+x)Z+LuU2;!FN;Yg&|;xbtranoo_?ov5PcYY<76x-YTezps9Cj-;DUHxhIoC zNBwu9AQ|NXuU_0(7ifIE;#>v<7vHw9O4$CYMmPc4%kf~9mf+xLBqgggO=n%vkIt6_r6?d~OX(Ws=V}K7Dh4R;~?6K0dGbc-K|y{V z^>JAab#n6X?}dS6!q{-I;Og@#D9RkG{3VBA)X~-izqqs?Z$5srv?Jma<28w+LOa?I z$rS9l$&P%fHueSYKpb6pUm5AHG>HwgPqtHe2=%O~7Cwix5BObm@~QkG=6+Xd));GC zg2�nykf*XKn+f;k`%i0`$pjx>w+}171k8d+haPg5qf^!bD%YAga4!lD@^Njx!i@ zgG{e0oDNx??N~f*cA_!3{|(=M>Zk;9LCnN?!roFi?nXW|U|nel z;BHy9ruX?w+e~Vg4#kX1#kbT6CU?4A*Uv|t9Eqh8O;Swc1BbDJPz+jnp4=N$YWMnx z2bpIWoUQ=NZENoc>{v8t0uH%n4eGVUbOg`Bf z(VF(=ZDmZ>g2A{hpL0d~2x$X?-U$TR9<zEBAUNK-d4WfKK|x6-?5POoJFR z2+x#)OP8B3&x)0{yTRRcwamoz8JBtU^P}d#`y?4T zfhtk_R&}L|VwMhEmJtsr{S_@~;gAZ%*N$Gd%Fe~*A8|u~p=K|6QZOnM0Jj|3thG5_ zAJ-(b*~6A~W>>6-g1B%5Ha_E1U`b=#7rwkMbjZ?)7Myhk?P|vhBsT8Yl4!lC>8cex zq}zHh<|Wrz@BT4v?<$_1c;@?W)jqa%gZ;!7ON1EN%S&f`Gpl+8>2Y>%A>73d*~Kv} zw7d8FtevbJdf`t<60A4`u-DT89Z%=cl%nA_0pw@H`WQ2Nbop`nNyL|P^~tI6zQ;33 zM*RtkvHMER!t2<^Y{`+MkdPO77Wx7r+ONT5BV!NbF63|6;>Z#d)kz5I>O#;qpc;jQ z{x?xQGig@eo;1+*9x>?r_=kiJ$As>gvv`f!^K?1JwKiakCbOA$wUOqSDz`YY{;x;S zv*ldhUZ26U5$(Tb!Y3ra2fXj6D!uca=}+*&5SkZGW^CXF{*T8WAh_Nc3!^{U;_4F^ z$T#Xc3W)y1j^}%u#~vI(;3o-~%n?@-3kn_`nOR#hVrQS`dFHIDu)TT6YwR(NUP`BU z05e-UXzEUDeN!~Qf-(`RH9Bl%I+*g{r!afoP8<08hkIsFb$$zfG1DiuC%RicJE{L6 zYzPc(am3KizQC;(@s*YeVfL^36Bt0d+z|Trz7Jm=XpBz8r9b_#gLOpITX@?W zT^-^~vutv^IzN?9;I{ED=dR}HlMOGL+ll1@l0H3R$*?7*7yL7tCr)C-;*=RtQb#h& zNJYbwYe$jQjqJ%(MAwJ44GF0O(`r^PeU{nL!7IiynnAy+BHl9l?1j=c00mJ=f2oHn zHDbxS+#@(;t4B22FgPt{QHP_FQ?m^IV;GCw1%v?K(g%0on7#TQv}Xk7>&XE60} zv(`ODc*mmn(>K{(@8mI+n)E_olsXesJ!?o0>+6(qK5*k5vF^XQTwp2-;V>S{QtRkfdvgOo z<#>g4bb{0SL~o#WSt9b+?AVD0@YB@;16~24sasSSY0Jie|H??--WDh{b+znPx?aw$ z4#9h8R%IS%QID4MYF$aQKqlHluzqS-0b%Xtimd|uE){)-hmI7!?Ku5MN2R7QVk!BA zwP6~?Qu0metIO1#l;vV<<0^A~dSQNvL!#t`TNlpz*AUjgN@{e70+>qP)wtmr5pj(& z?AsVMs$tJf&qv_K`JD{Y$Y^h5+AYFhKG6mBhPps5)T1hsD0JJYT=3!<7qHu9P*I1t zs&KWs`DkE1VExeUjA%?{SddN--ldIn!A7^sR__rV58Ajl`1^b14{Ah#zw0yHGk;|^ zsR1}hS>43otTs&*du!ILGqM&zXMS7^V!8X0Oq~^*T2^aH>|Mk>OE}KM)6W7v@yFko zb&6F`rE$Ri^ISiFXKUz|->2j}WBkc%DchE}ovA*@-1XggbO>5HVkw4lzLZ+uM@fe6 z&Azay#D%@}xu*4HGZC#AUZi{dweWL-NPPnYDk7OmFMQ{j2S_%!O{z2n2vCI0DwmweHVQw_Vg@_ z$~9^EpO-8Ezv#s~&07M06zZ>7sD1y0=j$gZAU!?=(Wj+at5-dNi^>0y7qhS_vyuGe z?}e#MS?v!Q>tETVyj+r#n1|06A(*0?A?8*Z*4GubSYD^!gy)U;NPYc}s_azFFk0&B zIx!8reL?`d9%q*(A{v?Z>h1!hR0O7Uq&D{6UgO1r^cJT;rT@IA@_^4He;Ie6_$OST zwxasbMO;^-oA59ML6o640$vZ-jHK*>Gc|iN2u;v21uXd}6S#S8RD{C))mnpFR2p$41k4I&^M+qrtX^hc; z&<_}riF0RRyaj%<=3W}o)fqt~*Cfe&zh6kV32eo6%(Ahi)8g3&k51YS`d(7VHJ@33c2;Q||^cu8bKno7;F{Ul$i% zTK3MGzEqrUyL)u${Wii2@3llXH=-+@^fUo*>kbaGlyL1uTZ`Ur)inpf{ta+aYonzmCyz(5#QNZC`;=Zzt5m zYYBN|tx&N&wt_}bv$3-|L5n#w8QrmC=d2p&jcFG3*wQo~c?9 zbcPr&DR}p5?PNcCXR!QeSBxKETG4g|McGpu$5lE9zo~YV&Q>zeIYKvqOOup7cwAM> z%}e!=FkC~eH#ci*RO3}XTy*by+aLpXX*I!YP-K|j;1Wxs>JLZ~1jN2AAt2DkuHPwl=pvyZgQsnWO${vaYLlouS92-=_6G zyVnzB5hCovy2YW_2v6vm`H6z8he_;D_}k>%KPjAJKoY*Z;yP#lcD5u;bv^Cr#J%r5 ztke88!mHYB4A1O7JCXtK2h@TD;B$CNiIC?>(U#UY_xmm(=b~#uX|)I7$B2voxiHfX zA0eBXzKvW7!^z*`A@-jEA9bRsqE%y^f^+%S)L_mJGKZq%fAmp-3A{VV$%|JmWU}n1 z$YU4V?I`TbXu$06kRKKCn-X$(^8F|gDjFI)ep>Irb&%=a_dXwe^$!}e?4C~is?s|L zcgNwI2b$|!nl-K8aK>4WhS7`I{TKG$$TgZ(TLw>)dYr9v3hcI1 z#(`OJ+P~uIkv_-JII7N(7WWeyVH14PHUGr?UisFf{(|*$Qj50zSP~COfqiKxN&WN( zm@uyieeUPj?CEwh*l$;S_ES{gyWJGMsp{S-;fRQ~>owa4H4B=LJ1MR2`#Fc!s;B1L z%hL;%kRBGcI?-ZVgVUQ`s^v#|bQx;g^=zB*82pLrQVQb~H5(@M=;V4^qK@EJ`X)E! z_>;-$U&qsyC!7r3{cIDh8`B7=WLc}yOAh@}l2)nW@g(_*Vf|Dib^FZP z&CL-X!>^XzWA~#h?dan%U`hw~_GGt#sgX!KrxM~L_X@^O=wzR)P5DNmAV_%IiPfnC z+zz&kKU1jL9`&Hz_|hlc63&@Sy6TnyUv@7KW;SU@vFf>D!Ub%{ncfknPe~bP-WWtq z{iD?gv|?HkcyLD4+U3j}X;~+hhCQsiC!^IIN~;{@s=}=&iq9XnQa#8+04*BrXY||x z#=5mAK!a1O;Oi;3vJG6np70E;qdv0xKQ!oDX?vKZ(RIHp-g|AmDYv0E2Do!@p-`>O zq==6VZZ)?_i)HS93rcK3r1bL0Q!h>@CpV{V&Ci<9Pg7Gn(CmKxSz9y9;i7huzbtI$ z0l}5$(Kqok@447q11w{1e{nrq8!me?na9;i-gpNWTkcK=o^KROo@zt`RJL^wUwA23 zqZYZH*EsW<0u=N$;6AdEWz5LV)79A*D(g09NHLkk4?iWd$nIZGESwciwN_F5msda{ z#VTJY{Fg1y6hn}V@18kcnAp0xFoL(W9W9TooXGtd#p0;C8P{3wglN`fLwZ2zXz>$& zB)NX&YCaE2J}9Fn(lY?lvpV|>YWl?+ z_M^CuKC4*dQTS)L53{5}ChFt{DI&7%^2&`ywwm+R+Y2stpR_6zrO#bb9a!`6wzYXZ z?XNlQTPTf%eivG#Hb*aEE$1y$P_SB8S`9PU(|HtzGgpCKX?^;4h?+^jbR;?4R| zY$|{yUFpu+UV>;aZMvaS{Ch3QV|*8&Ff zy@F3KqTT~v$VXJ;*^{dY$8ECu{=R;%(&oY;%{sRP^v?Wc`J*vAlYwK~aY^#E#L~Ps zR{a;}4?DJxXFq&|fFSwJUO*GjRj)4>f&w2g%KO$O^E74-=>2WjFc)oEO9%7XH10_M zpAsVv7FDJT69jjTzhNuFD2=(G+Ky3HQ=;AXOAO7r=0qK*56bXtTUjCTxACtwW>QSv zAKSM!1wmGHqaLY0xo)>mt;gcG{gQE_+t3Dhz5-(y5lez!AovmcY961~&-Yxg4o-^+ zc^jXULj-^d`H92x{uMmU$<-n*Vd!=noV<^hi3l)Duq(2P>9ApYk%(vhGa{NLlpvE5 zH`Kg}KaH~1@ZEPo=`d>>kbuUxZt?CoSi(uJ(&)(C8=IUcpKQCXYsz$2(pDrtPPn_? zqVZ#D(+61^@pxcn#&G+6Q{-Skatt{nhqF8H9cl@|%piUG$I@e@oQZ}a4dntSW}8m`|98eW!! zc%fxs-Vegf>J`K0g05kMV}L~MFH2LHMUj`&zVO;Lx?xI?QKbN6k&SouU@;95ktLQJwnCuw5(&zmU;`c zJl}E1nHc8>w68_DpfAjOI*ltdF9_Xhgg814z%ws=(%JFOH(=~5v~~|N$F}p%;oE9h zlYezgciBFRGuo`lq>Tffp_{|^Yt?#=8wSIjQ0a;`i^%I2Ltn&D-poKVLbnihi)mTQ zbJzJU;x)|wD3#IWsAjzD76(S6s-nUC#c`two;epkvGBp0`%i8beh(iDxtKk)siyF$ zuo|as@?q`^CyHZ!LvfvMBD^^pJEsl~vKwL~y)R-GHCAm^RolL-5l7ard8r+0te~Qp z?@r`A7S*V+3LCA>sL2VTBR0ttIi2Q(JfBnjFa6fqCFbzV&v11X61GMGR*!|lTWeu zj?=*}Tw61nz*2k#!%k*N^(s9O_9@-9>CeK)j<4;M0$9%4jE1H?_w-2DZX3E4X|dYUn!9S6FdlX4;km1)`c^zf zfUv`E4h)MItjkNSunkJ>X(|ij?xmlDDp~7%w~-tC%HQTApE?;IcMQ}nKUoGa?`z>B zDAC$?f(__7%d9gFHKJqLr>9)M6K%Qa@+Y%aM;)*?O{g0Y(IM$&6kgv}zs6>rFDcG6 zT>RbBEEmJ(Q$n|ICgS8(bvCr={M0T>stIdi_!W$W!t7@80i1fs*MJIb%(9*yB z=dqLjj|_x4%KqKxjNrMO(orpSn5=G4xvAKl^0hCl`Q?2Unf+>A${ng59`-@-66y~8 z1z9u=RsejZO<_{)MZEA{Q}w9ZFV@}_={KZ2gv^sX)G2P{A~eYa2dt<}DiUPOrrNa2 z$25C#r_)eJU;bP35jwfVL2PGEYpRxgCJMZ``)3GniZ%-2NESwCE%9kpZQr>@?tIcq zf#^$hunAbOV?T_kzC1SnQ&M~b@p>7zp&)(>1YWF2wB|oPta+pDpdEd3pZOK-NqCNz zt}Ph)N)4FxuTG^51vX~U0=(?a&Wp-bwLWgN_Wf7&3};*0rqrr#*oeIHBKD}h?~J*$ zsG(kUj1hP7!0IQd-oU!137iCEgYVVN!0ffUweY_zgUE1`R`t;J?7b>CT8v^3&x_cpRGiS?)6stZD#8WjwHR8sHEe!2UkjH_ z6bRclhl;Ry%RgL$1}wCgLw62^HOVisV2w8Fo(t0_#KEGAEa!+1u0e=8Q;&v6=bS;1 z96!FBQU`~Lu9guAO%>tb?D37q$*dwkA3^RY13YE*+Iag4t)juglMqq!8Qw?;UT*T-A(9Q=PEV?ly9WK%0g&+~9dIjB>OO-yK1B2lKg9 z4P1;Pck){g!7@RS(VEue@_ijA@a5KWR5%EhE%g&Wd(|WKbYgU1H+zT-2V8MRCi6(I zspRgpo%N03l&9Yk%0`W?F{mfZY=(Y`#kPRl49q2KjGz=~c=fU@te*DetjH;Rbk4N8ip8osFI9NDtKWR>z5log#IYN-#p#M8w@LX+6rM#R#mkT_fN>U&^P0G z#h~cWz?$q?{p@8 z(`MDvB|mgUNjeQaw($5U7A8-;oP0pA^V$pun9X-?uJ?G~_&QxgXRz+Qtv>iqAhafl zVN+>Be+-8rQ1z40l-{nvNKbN_9vDk>o}|V{#ctH#?OwV0YNak?)q@e5gVudqL>jeM zUu>4UFK6&zsiD19pjw|zwRv%N%LWRZv#lF9WSMWEzCNk1PW@Jsm(*=9%UvuV&&Bykok$0=$y)@p{6YbC8 z?e2;BNlikANZ34P*nC|h#n%LZ2>s|9U^6;=IZ%30Ek$obxbf+Wz9wySd-%RRicG{6 z|NCF?0{`UsGX{IkvjL_pDyxZVAfzSF%9D=){ga^*YP52!?u|Z`G5oVR>uP4Nj>`tM zshailt)miM*y@NVaCCoF4{zr%_9h~(vR5SAx>XdPtYbZNs%wJ{Gl1Yqy@l!C*zKdQ z%*jPCL(5-vkqo5(^iyWmvPQStY0hk)UGTz|Zlm0F9?cZpy~jcspyjj{%vnwauIXqv zrK#D)+?jR~F`%QnX)0PJq4Ni)p|@;l$Bu-lsBBz)Y0+Tbzq?gityC(GlhKGI>K9`p zk;C-iu7JZiq?nk9ch3vGPbs>J>jms+vK$lxMBAzZX9ORbBKC3L>?FkP6K%k1e z-(`-lMxEWQok^#X9ko3#RsQySl%V>0%+92^;PR{ayMG=MvMw#OrZ*0G7taevgA?)t zhmo`AWREhMOt@nd^D#0x>hOxanh|u_d>A>d9;S>bz)X0Ct=!oH*cU?FyFKL?cml8V z^ogX>jE2t;R^ZU|PUA0q5v&Um${PaE%tJ$Yr@(}`tl+}9si&6Qxud@`1C*}K2aLR+ zJIq^GoN=+i$qe&*sq|ILKks6D+Rr+KIES=`8Jn;+{&TrdrnFv~n7`)Yj6?7xZ%3L+ z2TEUq4BoP-5M8sGXU=G)Ic&}M{??XWWp6|WHrHA%!6v?e)MO`QC1th)D)DGlSlims<~7Hb+b$az`$Pr6Hhwnw%;l`gc~d z-VfXFrR#J;=S?%j#1g-JJ+};N4EuJ6z3~TcVYS67USq0G=T$;c0!V9Ls3L^VixYaV z9Ry!%<{&>7c^$B8)0W3N+#Xi;tJe`UKRj4&?rYyHkW0>Dan8Zse6(98ws5lX5ZkE6 zTe?Rv!0IdkjCG37d}4S5m4H2xw#VfAr&+JtPc7XH+06)kF(~gGa6&*qRR|Mr?zv}q zroPnp#2^C;h4=jrmi#wOzgGp*jl>?flCkw`-HX6Yp3hU3|M0?nvNZgJ7a&9idQ_>+E*-PZqg! z9bsP=G(xi$S3qEJkWHGf!z28fm<*2jRW{Y`d6Afh^uktEWA0~d7FUGgz6oL3)jy2m zBY#59?8kj!+C_d+$3pGp?VqcO-c#nKse`|Z_cbav?as?=m#asd?)i6iXWSK5Y270t zRTRuolZ%WExMM4iRNW?S+k)tvTaTYm3%*;|4~c|CRY-1MeYfm0@vklCEj-cb;IPso zA|b=7uagQ_=YLnloJMu;r5l8vBQxAY#g7W6iNhZt2g`~otSsSr3l{a=#qqDJS zSB`DIy8+8nPCWB{kz-brV33M2`|j*w(BShj6(cF3gug5pdHf;b-QiqAE)V25vR;VB zbsd9q{7ehvY)_snjW8GjR>oX!fR9ZsZ<8tm&GfX!HYz`eIR2YC{RuDW)G@}`uenJg zCfI6!IA6)jGwn!!h^@N}kAE=l^aP$0Im;K>ih4(tr<-@IK+L-IAp$cPbzr1w2NOxA zIe!o-*Lsm0J<54hE<5FJS~z6l+Dua1obBERZ35EK;=&0>JK1W{gaFiz{(xp|$EY|l z{Zq9v5j+F|)52KU^_%80MojL3pSA+EQ2DKL=I`85U!Aa-*W7#Qp=wK^iHCb0j@wN3 zyN=N_I%4hzAgC$I?j?C9H|)YotCK@e<_~n>`Viltz_js5W-d2x$PRC&6Z`DCh5)mC zq%FA@YjCnpWVGlE;0y3V)#{g}1`%fZ?g_%Q%6MF`tkC{XftDg>m-Olh4-I5dV@!p{ zD28mpu_gPw!{D%?R_(THZ~KWafCBo270|xYQXP{RQDtR*2YG2hT-U2&UuhT^VJdB; z?ieW@UuU#6t%Y^1J4+q4&$b(0)N&wT8;fX^3a{e!q!5?l3)s5rIA5)Zxy_%H^2QI) zHIH>WDU4Ve&R)D$CTH+L=dy{&D!>!@(lxelTnac$#Y)szSAs$3=$>KO%{_^kOU!!D z>a&;ANI&E8!vEH0G4-06BkkQ2@G>Ye6QenQ>!Pu)YRx+|P`>Lrjdmw~_FH$wd{rxQBi{UFakk@v8&C`E@q!-$d1}fxQO3V{ z?*AYKvIajFlyi;u-rMuGeT8dajXES^eXXV$&nu-G8xtyxnawOF(aeh!NPAJUcy~ia}U$!{W4=)}(IMFts%~E)oSqIv&`D~8UZ8po+ z?BKm)%8Et)vqtswbAMULBM6!O7X_B>}bT+I8q22dZlDVgcEnB`*L9H7>w`_uoqVOgEWsS)=8LX* zn%gUA?9mc`{tj`47=5Bfs)=%l9(pn@+}MnG`*eIB!lYg-H{3Wit%q;&9SN%^U+JFM z2Ifb9Sz>wJhi9`cPLyVR_TPUcDOcyiF_{=#Rwkjq^NW^!a-NsZkc6;~f#T}717DYK zxBCje?QMQOk0c2F61IHJFWAHs2QN89TV;+rqmX2ATCj_LOE(OQ{;CDf5DY7)pA2<1)LF@ zxV>e70fMU4n5p?#TR=HWLBhK%kG(e>7#gpe85dOwH5Ip0m8JM<1#8kq_DTriNd1)G zP26Mt_DJfb(DZp9?6>i6JuV*8(u-cyX?)GQPD?rvwc=k;_3d1dA-{6v%hUXP zZ~e*MpN*E$XY2Yt)<*wdp@1T0Dh;zu{nhe6DJ{gg!S|mAdHv34d*9&AH1}q`37oLt z3(dA4&9DVE(0=`$931#AZs3qc-x5PLH=P@;E>5K)!Ff~tl5qX%1j7+UR;n;xK;|7$ zKe*>BO1a>BE05;w(u7niV(Caby;i6dI`~5plboU&B2hcCpm-(r1}iyA46X1i?JS;#FVoV~z1iEB;+N5HDjg-V!K)&ihelgqEK-KPXaMlv*3 z_ecQsMZ%-;v3ze#U_hS0o80^T`S1W8%-8DEu4(JO$ml9LxZ|M6?dd63?IX{XaK%zp zvdJ5x=i&%WrHm!!H!&%2}#C6GT0X8NN%DLn@*Gd22Z@(@8U?9 z203FXcBya$iXuZorkC*FDdsP3dhrtBl5KZBBVmnbkN)LAdi?U0|74H#(U0ctt+Ye4 z=76RPN2#!CEW~I>Z~PYy^mE{x+7XQyCQ@;?`9BZ}dL8RLebxtGvx$p=@N(LY4rYknZ6 z^HSC3p_&Hox7vuk^`Hq#fg$HbhsOCyc6mEA(AuPCOgl7(=s+p~$~NM&C2z(y`Qk)A zA6kzcWL1=fDVB^aY|o@fskm7u+utd*1S%&<2vqf=xBM4(fx&U)e}g{knj|!Kcm-M< zBq2=VjHlIn`m5lNHJ%Z-_7mhY*o|xV#iSLZTP-|s7Ym{AXGbJxWZE44#kb6ecWJDb z;3>1_WUmg1^MBv8b}WX^fF7OCj61WK8Cqlne&xhXE^+5vM4zt&@e}^Igc|}JO|D#I zZ!vZQMFJe~=cIt0j9Um(g2xdxn$~LDCq2GzRD&!M-|og!5?382I?6B!keLg$;X3#2 z{}TOQlnyHwN{YLU%jjkqAMwMd@>`Ninj2Jp)U@AZv94gw2mez%+#td^dvja;{ojEx>54#`%Zs>_MTI| zRn8GozBIq~5bh6qT9_%!ff<1OL7El^qG&cd(2d83{@8g3of4zw-wq$}FB8xgs;MSM z5+7T}M_f9Z&Q04OeZ~lL{5ykjrK+!pprXbdq|6;aKEzX=jXO3Vp0FjczBZ>+CD=9 z3~b^Ahus}E6CuC+uPpAL@R41iE-my6&dYpYtK`^BWB2J{d$m~i1}jSa!|BH(S!pU^ z&Hp>*S(;Wga;A6My+;6#vOZ6tLYdZacMeJ;<_K}ux7|t(_&n9E>J>|NO0yT;^elNe zzy4c)H^Fsh)nUJOrpVUPJbkmQAE%o{1^gS}7TzfjYdeQ2*^%VId*jOE-bQd_>^Qe}CVR+BFEB8T0*( z;sO*r1;+LHew8-6j>JMnV%w#kx*2&h*V``UxG(v;f^UIU+=t57ZNX;&$L@DwKrq(! z|M{AT?MQ19XCco3YRJ?MYLn|4Oe=kPE|e!IG25Knwt4W`sxAvy!RppJKA5Mr?~K5y zNe7huFT+x63zhn zw4X)^k@weB*Z5#v)01flmjpS?#h8OP%Zuu{^8w;8iWP2b?LIovV9hgDY4E1s zBgNKMKw4^}dGQ!%ze8?qg!|Ay1R|q11l_AE=Yv8?bacoL_Kft={I{B|14wrvt6M`N z-Oc9fyti`Mb;0DFo*n5Nz{oRZ_pVBXa>4Oq3BLPV&%@*&7XDd^oEvTJ z$c4X_1W+tWQ|hg#i$@>XW_cb&DJ#fNyUw70+HYI;7^eDk7Iw^sqCDa3i)fp0_>`N7 zlNR-oO;x<{8pW@qG_-z2ZJ!X0Jm|e3w(GdA$ZD{~bXW4Os_+*+f%N_xv-+1rjA$S_fZT0I+RuVxGeJNc*^D2exz&;- z!lkfOlW&Itkf;X%&akd@f@ zPRxgI%8TkV$Ic&Lb+QW_nd`3ss!ab1i1???<vM-rn83pP!knu|oW`a8=)`=0lRu zsNG-GBXqM82kbd>;V8G-RPgS$cqKZU5pBieU#KV2k){}QcC|}1?&DtB6vX!Ac$R1H zwVEYn4e;EQeFV>DpnWTb_>~M2dN@yFyrNU&V`fX_J#w+&63TA7ZqK zldMwmonM6xLCLaep3k`-U-`1X zoUTr{A8%k}SV$(2af&EcvIVZcrDi={bk?;fz{GOwp!r=NM%1nVhPiQ|#{1k`=QM=Uih!W6zh^FPhD9wwClvq#!&)&h&HWfGCGNhfabK zXsOw$fe^wduvLH1Np@rV+$^S-?@~!d7bXudTkczE9`CMAX_^Sk7#LVo207RI`i=Ye zpFx?i2DL_AED8c@+W7~f5kD#jPiIxF3L%jFG!R(x-=xH|K&R2szA5|*Km^nK@O_*a z1eX2N_s=E^%L%bi4qL}Bc}g*BJ{Pf?Xiu)XKzs2pGNozzRsm{a7yu9cwotEC_z z7}nZb@kA|UOj1A@Yc!hG5ADoV4DG4WC;Y#Ow>4gU+!un@fi!1)9JM2pgD$5uJ zz=eR4V^gk{EdI@^v29qkTE}`GulS?VqNt*;EwQa9ymz-DL!5um%?3?MoIXNzUe-3y zu{T}}nKxCksRvb321P^4TZ-FUEG4-!!VG4X8)Z^@h{jvxt)h>fR)U|N_lRoi#=+@D zSJem)>vPlN@S(yD@2KpxwK+qlhc{ zg$n(yw(wko_0Gsb{>Hf-tri;c{!V7@JXX%C?o7?@VF0f4>$|s#DN}Q8sghGdNeFe|l_R#*n85#h@*m(JDTknrS8t=kb^kSh z7X|iqnh8#p3L#f;)}aL_?ldclE4Q6I+sTdN^=Cm*!x9yQ=mwoawtM|Bd@m^XqS48+ zDN?{(Vxk~j^VPoWd`au#a=!i*)2d>{KM3TQlS2emKt&d}EmrMz=Y3b7I*3?|wX1GVhq8Kd zn>=r_4I}@i>ALOg$+^tm%tp{8t*B#>hgR}gx;ylMLU{V2Rax7OC4ejvHP;JGP4|Tz zX^!iryV1NX_)`g=*wqKBoJ%VZ<6W>EaQVSK7MZsWS4>CkviSKQ9JP7Jw!PO~;gV=; zW3gR9jcD(@daa<4;EmolsEnQVP(TSd+48llU5WR1K@oo7fYg}u8zm@?uPckz9jz&j z%ptO6i*G$QJXpC?R@#exi^=Fj|C>CsTD9F3y<2L{D#`w}Kx!1UP9W>|Ja$TFvsLiJabyA#_YZXFkZ3jpGNTJA*v1OI@8WXU3AVYxyC2y-_^6{s!5{sZ)v zV$HI??*}Jn->f`IouYmJ6gTwsZ4h*aLufN4a;KMa)V3x~Bo~#G7YC&S zJ$#KoH64S*Idl9>#GKgZNqetLUA?USp1KaOcKHH9?LcbeVtM+K)0TDb0yt(cgeO;y zH*K`lqo=2+L6%MM%k%_&EV%<#3EfIAQ967eO&yj}sCy06cllC@!?%f8wpz2oz^9Fv zb?l$t%c@7qt(-NE{|=Zsr0TSt^|}azZ5!fuBU-+CCbK>87?pIePdgV#f&_(#ER$*0 ztrXme4zP$_C*P)f&n63hPs0TW=9Gn81-kbP`gaUi-!NCJokiqSIJBd(#zACMnntdz z)HFW%(a~0~1}Di%%byGwd_$I@_%L1jE}V88OY#vCo7q|@nGfuBn9Qgt0o>^tJ&FEG zk)-rm(X?<#&VMh!8eK|3#~5OD#%RZjm3+GG|AObgvA8W_Oi)nyumSKsLV z|ICCeb_@hthJ;7LgdGXWN3(B&--bYc%kXcV@2Py1-$ziM00xO|v!gWddw>1FaaUV} z;_{7+{@*fxx%sz-xs-GA7p<9SrC>G%$Rh`*9(L$)mdyTm6;(VcK_JKsL|#Q~m-ULi zGadaj$}ic+^jc9_5AZvcL=fhWPtE?M0-~@M{f^|ib=>T#6Z=@jVU_?pW=z2XPI;lb zyhcJnCyQ^*LqgN7J<(^``10{erKI-OW9d)fy}MMlujRk-0X$95hfDA&z_%B>-mbWm zn$pK~ksveGCAJHk)0ggE{6^Rbr4o)jKL>S@xL{A(Yk)&1*H_>bB#j3XS$$(OKP=s4 zOW&1Zm{VFF*q6Q4gBls>a)W~_XSGnHY(^+p57x~ae(rYQsBbSum>6f}^ z4@$&L=ESp#gNBQlzK`<1x+QFu{G9ufkomkC2#$@9dAu}fskUcd`*z@+xY zZ)tPLAXX4ko#8tl9V@-bSzCiZySCinD-Y^?{((uk#}6p$tYr(-U&?Lby|wPpHu_ZDYIma8S? zB!dPhEd=%Ft%S$bJiyX)L7GgmM)W3mB~CuW{%6B(rPnzn1>nB7yVc0QHywV|rK=Am z1prxE=Xd6>Wos&pL?O6kX1cePm;da}cz$)@a%?VxEO70ZX*e?#C|1*{`1}a(_ zYg$*_1Z#RBOvRZ2fHsFvq~JGo)?!cl;jirZ`2kg;@GTfnqZZNRsgnmH_BQFk@pN_c z#db$roROr9GIZuXb&kPmd#{y-l{zJd{UKzzi?Slq8!^ZyA{QSG9t1EEs#D}TMCigK z##4b!5(%Bt?zGafd~x)yT@7Q}zBWvjb6op4uY&Fn&;)kJGRK+PZh@{0eS3--E^2Ob||ep)!p{kuPPf zilwRV^K!3F0NS``rdrxuD%qCf=CJcE&Xc_Ifx6$X?o-sawy*+Cko|bV55_D39xlf2 zU}p^RqrF~3^ruvm=?`58@u~T$eIDaG&aSVRk|OCoY{HC;WTUm}Xq{%Ft}TE+iIF(T z5H#B+F9Jp($mIlQiI+^2+vDYhJfqSm$ZgeFNyTNyzM|ghis^q0*SsCF!Z=DEy3%91 z%}{?}&@=|gb|uIet}LB!54gLM>z|gf7=SE7rsud%w%gu+S2eq@u_o*3+i3(GxzFX} zX2^;{F#u(&zxo-nSsx5GHU(X#@ms?-FA}1s_Y3A?L7V!(o^W~-Z~v~Awr-a21pmqs zu254-@3hj*&U{}EqFs-34TpsB)*B4=(?#S%8LLmK%QlI?IzXj5earp3RFs~pt!Pfq z-#&z9&C%~SceIagS|;f2{zzYTb5d3`|EeVQZD;(gOn7^#g0(yaskqcyd{Rhb^MdE8 zk0lu4vag#z?3X9;>50vIg`1_(cAYTlA~W6y{*p7c0U9G(cN!FG=YuR$xE( z+V8ni)nZawubi)K81%}icTN7)ST*k#Ig@n1+{UbH0AFj~Efq3GE*h%DWFVlHkMmw|(GG)m|k)K21P$m(St0c7gh!u48@$*v%_s zXc)&WNazb_u;EP|4|TYvYH}#&b5>H$gYpcN+aQ+|Dk-_mC~ycf6C@w7*}6&Enh;M) ztx$3}4zEjuXx`Sdwg`*L2jZz|VF*v*gyw5<*X9sl^5=aG$-UxYR=Sl1At*`L3BTsU z^TbSvYKBLo($zsvynzVIl6e{bbbecO&BxLTg%H^f{7zt0sJey@`PhYJ99!5F1 z+eJ0`f^3<-U!k6UwBpXZvfshYU48#gSiBKhVX@@2AOM|eMy@=`OhG>; zgugB+dF53)p*K}6vb4CVt?sGu;me2a1do6&f*itix;WEJl9+A(wtOQJwU$-av$*r; zpa3rEkqtcH4O7sP4qc<)LaR~muWktvI<_b%K24_&uj!+8$BxYMQb8nWOH+UH*?GavKZ&yQ-Oy~RW6aTzP#|u zg{1U>4W~Py1o=8B>tR%5`0<}6pQbF&!2*}atUTEs!7`pT&pXie*!f$gMa3Bea_0~6 z=PV2v;Xc8^j9yDz&wbcn^~4F{M_*hGX&zSKD0}A6h|ai$2<`bxv9c zeK8kuCwG}KPHIr*96cVP5`q)st$qOnRIE~FZJbk{Hbjw2anPA|k)%UW%Hvf9TNN8a_ zY8hb8esp0elC8*@`jc_RjUsRb+KpNFLba*al@E$vgXlFX?cNZXp8gZ>Us+6lRvCOS z7(D!ZSZSt_-3JcX3&SpYzuwL_g6cGl!Ejo+im~!HFc)Y8!nf)MQOtEat0tbx%0$o3 zmHYjTmZZLmxV!qn5>Lm=0@K@q-9J+8mJinCJnWtnWx6MC*v#GKY1XYqm^5LWMxHNU zvBl!}4Q^4V1%I3e8dEtZAN!=oE?$gzT7@`aiHm$;`Am;#X>WdKGew>BJ9-AC|$hCb~& z`)W3h3E-qcFpA`dgiw^_)EBo-8ItOlclC8EW>UZ=JSp9KJ)Uy8yt3*>QEweUwrU>p z3Hd6(Bt;!#`Ydn-3taVn-^R=aaAfv#r)BAl8KSoCAoVMkYM4Z9}IhU&=2Vx7o16%uEF%LxU%0`i5WBd6I2^|XEpA|U=Iak#`R$)^*{|* z+e6iNRiL?nS}?sDdDlJ$pBEe|@uDsjZIId`!xlc@(Efwfg%jjFB zx;xBZtD_S6PDtod2er4(UNqCHfzXy!W7b-BhLP~UV~<9W4{Ihs*d^mak-qru>5DiG zt~J@x!%LFI6WSuL=W9&t@g8}vS|1K~((XGA>-{xch?+9vO&7UzzNg}TarKjecp>lV zd!+_*6za`cbfow-N3GVGtG~uzF{ZK#4Vd!@7by5IH>EBZb`Im3{zEEqPg8*Y||NuOR1&&hx>3Ka^$sPwoE=l$%?i&X*HJ9(kp5$VtqD? z>=HA)E-q5Nb2*lO10w4^v3Q#<^C4yoe4PE{kM6BNG|Re`elGOoU^yv#caeMfgy^mR z_7>vJ0|^U);V7ZWeh|LMZmLMHF@<`%!a42_2y{k=fh`&Nb?G&MmnvE7>T3THxxrTu znzKWHd%}Bb7>62IhaK#|Y!;a2R;Ix2gXQ zhrUKD%3bz8n1he$Mzg$jQCAwe$ox(A2#z%CcffzFA^CUK%kcC7Y6$@$z7SUxZwlm9 ze{O=o1f6vSgYR3FdW&=MC`-WYlJVFKDZJ7oWA~NKTPXFY2Md>;aJ^8Te1+P5g3DQK2ILGS#pzJxGl&Mxs*Mx%ym=6|m+?dp8|(DL5hO`ttf zr&GsMLd9i)a)$9%NYUbx%EiqH(q3})%c9WKdI zi2anP4?PvPJtJg2FCF(HjcljY#nG#sWPoqXg`e*J-!bW?qwN_5Kz-vvh@W{DRMaNOdcfWGB{W~ zYcX`<)T$7rPPt{HUs!sH%r+JaT4asZY}Ca6z`We*siDjbmgnsDsmInKV1vClh%f0{ zy7W{InRcxdDypFvXkZiK)ik$*hk-_cjA`=yO{6xuo)&D*7b`Rm1*Vve>UV}=?~(* zi=Wm#k`p&-VC8+T8OOQt;FcCIeM98;QJU_f11bJB1&2|GQSR^hNC8TLhz{#ap;4*& zs`z-=lboVDr(5E@54vO$)9eTT1>C#R=+rMomA6qzUyG2-AKAZvVU49B#MXcPustdk z|NJ^n9nhxwTt_xIeqiQ<6HyG+yS6ohvaJfj{I zkAOXbxjHsrmSqD2nCVGPRz2*j*37#S<5dErw2HvpT@M!(&4w(*8^^{|GmVUrpqvEv zR|r~;t0I=NxHx+VsCE#%3utlL<_1S1S0l#_XQmKP1;sDJra#138oZdU7RO2v?N)cY zRpUFBUK&7WoKPynrq94<@uYqli5g!bEp;WE{{;F!M&zS%VjC7j0Bh2ESt``cD$Grf z$+RXmb_$7)?Q^sF9*-LWJji~S&Ejr$^@#Swv(KH&x8Gdm(=6Qimng`V_WP5x zh{_>O1$lQSO8sS*ELE8KL|L>QAW~E3?oX3kV$OkL`qCVGdMs{L+ z(IHC%OF;V#WD@OeFO=<;w%{uj#joqwct@=@h9jaQ&%0y3&Ub4Ctaf);w(GZLmXzEr z(j%5oJPx#MS(X~D`_8`bym!^@(k+I-SY9PFfojF{3@NE7!la`1t#DR}vAw%1faq=6 z=RR64n%-oJCxoF7M;Tsya`EE)Bv$o25ZA&{6$&`O6Ua?ztI>2U#Y!PA<|k>#MfLc8 zgEj+mcOwJ?yxYKJ-~3P>48@#X8xaZIBfA*aC!8z3{&My72`Cd|@q2|>pB+(r!?&%& zChAR!oNh{jig0By48Cre6Jw;jWja9F*d#eA{zY$_M;H9>7>vhyE+9YGhB#?cDf^hj zUKQbj-7;(*FyPWk$#vsQNo-q$41Of=$s@1Nf_ZCj^AXQpzsQos3!USBa(Zx^&N=Y5 zH#ljo`!s9)mTnWq4E}`~BEljCj7Wbhqc|lKG_;j~HSk*oX4`(jDrpWLqkAU$VdX?F zW`q8(YP8hV>7uU3G!ex)9G7?=K~FXGq_><)c3QC8ls?^SIP$Q3{=%|sRRH##i1(C`{IIOj)dTE zL*dStL|{Bn#j=)N=x8EG_WvnXYT|#?3fNr?+m*e*LBXy=ScqISN9 zQquSH7UR&37N&cm{Pj>$&DSY6AYa8OwEbE}COxt?Tv*u(T|4HOTg&uF(7_)k;n_E{ z)}>gK;0zq(HX!bYKKW-y(%IVOHZv{$4YoCOE%A*bmaQ5y`M2sg@60ME)MHvG2%hST zhibp49*yV8{&KtCLy4u$$6qQY8$L46!RmI(NBR47It7)zrEv+dW-;FXiJvy{(r|fXZ=~I z*TRDzwN*+VY|~rIn*Mjp77tt-CwlaKZ(f*1cAn`nj@C&?cWzxE-<)HD@;&Zj|7!H3yim<3WhbB; zigPw}{?*v~sZyNw&_g=S3p)HSi$?Ok(!3~O?qmV{!DocooV2oy;yLt%Nrv)@DV!f7 zxR&`e$hZ6aizKPmZwp|hK24nHe2l4PlB{0mufIffvpVuBc-urG!Uq{Rg8I)h;4sls zT*4#85Ep)ENTnWx4pq721vVcpdOL}uo1ZsncmUo(U3CxeDU<|0u(&<8=mGzzfH8&# z?|w~5m5txE_U_tksdb6qpF}r50MGt-erucex6>K6M)?@f->*MKMiXhVE0 zUPD^nP3zNC1pkfpv9CuZ?$=L*W^JoCgSU%OCm1HJ@3d=%{c065)M3QlE7K~8nF!yk z;rdsfLDQvU1wR_1En=m@T@%O?OK+M#@V->$ks5jP9bT51Tv4~)(E}1un=h(UsAOUH z%8oOtfpbls;l7RONbpFRpr=@mm%OaCxjHW(X3!tox%!+ke^TKGSxS!8`2e>TSk?t6 zhH%bg?fA9<=2`#Pr>)ziB{*w7oGLA6gv_o;`OtjQ@Zr}l;aQ)pGzJ`b;;x6-DvdUlk zJ0-<~@6dcDho&hTgF52ixabtB_MX=K*3NvpusfTpsssJ zT+xQkr6R#^CeC;b_sZjql?Ket?Qhv|PBB8ZvuDx2LnZ8XK#A}LxL{xg$+cv}%T)K4 zH=T>?XyM!9=H8Vum80wi87zal?NAFq?2aewO3E8)zsvOE;}*KZ#j}saOyxh>&d7=u zv1cUxbXq4$-C=2;QB7XG+T~1pW4ulAqmAT2R^JSaT4H|RN#}ZSChb}49C;q=?zi=m zy5ehg5PtO4uTijL=486wuV}Loq_d|G)I5WzTt@R6?ETRA20c?+ybzwXZ9NC8^PP*{ z;wI~G!cNwkyh({0=-Ua`vi4p%Y1ApS9t9k;9&kQKqaFL-GrDOWSe~67Aj0y4mvvWvB@|?vBA2+UsNv&!3GwN9VB0Vq&C{RD4JOZqMC-6QVC% zxL`W3kDRmHlGGsC3y!uWK(k+vZYr!M*efA9N}-bune^?}t+vFnlUhK_9Ep^rm3-;? zvbY(Zh`F*(Q*`SA%YxWqu_JHHa<*EO>0ezRB$v9GgvIHnF996BWsa!t^Pg2ELn}R+ zSr6E%3|;_AHPLLtw%$24;B;x7nA_2>qz~ydT)@=%$K(Z02Wj)$^&jODT+>4(S^=kZ zgGhb}Xy(QjyWDI;{zZ3r3sv)p_us#*?39`uAjYfUmjl67xRCRX7(HS!gwG-LvnooPOyow)Q*g?CII z{K>u2!<`T~c;L&h-UfG$Q+W4#c}$+{@HCc~7O(TooCu$>wMK7x$GjEu?i9Q57_wp( zH6u3CaBkQ|u>$!W4_BIw**NF<5 z_}=P2Ux>9^Hsx&#_*J8e7}*4^OjFBb_yyLqB=FmV5rOhBTN6Re=~82=2P#9o6Mpu= z+0IjSc}-}%U-}o;hYyc23xZ*GYR>aILSojw^0@b)Ct5U23*q)a`TXfuw1K3eM+AQ{ z=+bn~`Gg0GTRo{4>dNeiwIO2Wj?=|*c3pjSD|b4)w;UYO{)Ra1oO=Tr#?zTi zB4YxE6ILUyYDskg(>z$reO@~z*Fj4f$!f4B-gzk1=WXUb+g zhp6Rc482s7xMm=cftT;4*Kz^OvJt@EaC)#A%*AlDZxuj{c-Bz8wF&N|WrRqDa*!J- zYxAHi4eA8llh2aW;%%g-XPFZlDNl}a_qC{CyDLYK**i+#nT-|ka<+TTd%a8aLeXtbPiD@fA!rF`F% zSH_{-{hzxsi~EDo1<1t_di?2Ej!_$+7=gS#igA zJ_;FotwsfjkxE|<&R9(gz1kD9fb8a?Ju>u-zMNa00T3Np@adv^B4=^1mJGp8xpghX z#Tkcd+2QaR{=X>LM{ka4&}PhFVaf+z3JJJlnT?A{8^W;cE~zN@c+7M>?|<&&1*Db< zQz@VNoSse}7_ldK_QPMzD0Y4|W2``J_{*pgQJ-nc8MR)5O>%!93_g5tz{N-^W{h;C zq4qz`5~RDf0szh! z_D5GKJ{34JM`=7^Z8E?261#X8N3T6l<7+`cSp~Ij9C38A?6XpoSuYfmLYOVH{zR#O zmAgo!A9N?5)Q_xT|9pn%-Z;G;=UY>kHDz#s*xmxFPynY-E84}`8||OZ-_VeJmz0AD z;8xg;Eqd~5PcADMxEsH(a(GOrj6E7B54G%UTA5$#Z+a-|l6PzX(%y8L&BKV^894~q zE+R1o+XRGBIA=){_~mrxaP0&~7t(TQb?W|0}wZw}ZmC$L8J1wjAEP zUO&WEf#|d+z-}`WQf{>cUx=6}oyOShp&8dBHU=ePn$CAGVEA$~s|x}ntZM6D!!CDU zZ#(^|uA7z9Bl>MYt8$RvX&$kWn2+iM1KW(42Bq(6OYH~6kQK^|*6HQZvpkdk#mK)1 zZ;5%K?l>g__^)P@gFix9*Hbh+UiOOX-% z8(qT(In=UUX5>+Bwt^D&UbNC8X;~i2cbmDL8otq zS+bg#dsvY`(w4wW7EZZ>U3VZ!Oyy+%9j5D-T^aOJ+dXc6@h7$Z|=iU+>GJ2rssr@}de%`&+1N z^bJe>_}qY09E^>@2U<>$7ilAd6*F);2>xawg=-gljUzzo;F)+=1x2r1FRrams>( z!WaMDwNq4Gv4p!U)7FN3Vr8c3ypxFbI2On#2NXC_Nl*sXEFW3~IKlS=9vVrlaLlWYf`P5^2Br_p~eXuGmpHWMk6b zuv#v}{dOgG)NmayGFp4y$NIf~h_!Sm*08FoeD#&)eQ&sZd`bUnw;`tI#-uA0pph<0 z+`GT*F@}D3rM_(1O%jt|eVzadH!!V`1$23izZdfR;XyvkvB!l(a}FpDxYymhmA1_r z7`{$VcPK{2=JyvR=J@I+A6}h(W z<5ER0ct-V2MBjGGxXL1ZQU3K@x6#xP$LF>Cn?g9-19Z=9HSc{tBe1$D;?AygP#kw8 z2WiIzKLhzHET*@@;?qN9afcPHOI_M=8kgg%YBt)gZTW*+o+d9O?iI%dalTbtwx;P? zlO=j4uLyPKdbp3i`uu76KBy8VUtFtibEES=)|mZrlt_4(Bd+FR>I5V>Q_lhC(U5Pe zyXLIBdGy;SPS?SAnDM3s9)CekF!NEYvh>#VN$B(s98_a{HO>2Sw5hOt zW!~1lryy)NcFmV0RPYLy22CdfV(1Oi{x08MS**@>Ir1JZ-X(+tP&@B5ALJR_re*b! zXh7I7JNWo&+E4vy75O=H*8r=*-Uz47xQ5whH9J8nPLTH^?Rs>9J> z9Zji!7h}FZpPwkwP+1S1G=NDY4(OnT3;7}!YI{1c;(zHUpi}z$IyVy>)E0e_1ljj^ z`<3-SuY6-HZ51&IKaivG>Y&j?*nHrz@Y&&3Z_x@PNdsXA&1C2h(~G2kOv)P*oDh{V ztUpvpmP0mMyZke0{`NF%l#%VRuh552&?#y(uYbkz&r`sk6FASp)tce)`7&u4!fHz> zH%n6GmQUv&){_(TVb%C+h9#tlB{CfaKZvL{b4gBL4DA-TM7>z6WqPki6<+@xH}+LU z_1gyN3-Ru6(HQ@Ny#o_Br`y)SWi#->0{ZuJlz`n?o}wa>AiTG0aXYa6fm?fCAUO$C zL)ioYEQQNcifJYvS?jcuRN2zt{pGyfag%&+`WQmFl)nka-4ob;^0x5pH=@*6dcD$1 zJT!4`$(oxb#lnR?Jww1=bcOmibXBV6_KbUoavAygQxCC5&C%FTi$H++<(y-hPEU5B z#$`SO-B(j#%&~wYYPxUt?9Q_vab`dP9x}FHd?b0H;6Tmib+Rc-WPqGOXe-Vt(~-Rj zTd!XNbwnObfuNmSA3CM}oT&Mv-G1C2HcV7N@e*W&KG^cF3mYMG~&IxHN+rGWu&QBwdn?!jR}dS*Dq#bMTbh~2(r42 zJL?_C%1nUdR#4>f^2k!FQ9K#RiyPBDR`#h6>h4o-69`7Sz*V#+3m?5VTm#RXszJX3 zi+duT3ytr62$JhR2xutRn|f2cjEt6lR3}v^aZ56m66W7@B6G%RD(?=eqh^TgF$}}u zm@Y95uE#BrbDtIuGdda;4zB)rf#2yUujh~5pvLt_IeRQTsJh&7dGjTSpm_j}Jo{~Y zh?5^TzdD-VMfGz<`Y^)g^U7JEViEhFz4fO)yc%cRizz^-U$67pAytPEHbTz-Lh=nS zq}ndWUFE8jYw4HX-M9-oBSm`-XNA138RzhB?};P{o0MgwP2*>;eyOjZb@uSGrdHGT zoF*sw(htzX=~QUbmDH)^d)HL7OZA`8+Ct>A#9qH}mP$Ul5W}n7`Irv@@VQ7p3IK%h ztULk&&+w;lr;DvXK1OGmP7Taxr=ZJGM?`4bIQn;pAbQh+}+crjbkd9%7*-wmK=CefXXq=LwD7#IkyJWKGM^3G{wz^ zOuai%_q_AEgU%Kim5+rVh({zgZ(~0-cSPe<-dU9?Y9|rZ)l)P2 zvcNKN8NQY;!quj)S-I+g+pO~eQ$bbax5!dOoIxEH!T{xO_oBqBjwe6$9&5!tFtj_1rr`2&3 z*NgKh*Y8CfzH`dRx>3(K;>nOPvnp78>5 zsB3&}V54NMm|nLai3nzQkE>=0dphChaaq47K!>OwFDQ+a3aNODySL-0_}43?GZ3US zPPzEUFpAuCrV`*jp=Sp#2mZr9w1q8Optzri8|o62)H0IU5_mcQM5fu7AG9a14a>Kc z-g$AL)=!ep6}s9=VFDhew_eray6M)spi}=wp2+Fdm1AIbE}88ZVAMRS9UqtkF4+k5 z8NsDq(_G)bJ^r+7p=h~5tAiq5#iM>e#8^+PB<+QqV(EPQbsxrW;++5%_+45bIy9(o zaT?uxQ}?Q8rVyiUhwHc9mnf=xpexSSrU#$qB>TicJm;h&?VyytKyM{nMw%RzV<}IE z*jrpAd)()(YYz8&zHgkryr^PSyC8}vJ3GSB_Rzfq%sxdPx^mmDEFOuDbNt_m1rNnn zpI<$G9}{*mS5GqF-gGq`LFL&ge!x)wnb%m@3YYB4Rq$GJQVhXHCLhZ`wy6`094)p_ zPcMA7^oIe|v9B@g^Vz2f+u$gq%!TwHYoFK5e;*uFh^3sprO&vM#eChdsX`fV+TDik z5m&&Kp&mDdCDL&t`L@@Yx^ zSG4<&A`;)C99wCk*2GM~YKRkW=cT4@P_k?ElBN8cQ{#i4D{V%#*+0|BiH@Mvub>Hi z7Cy!2(B)c*4Y35hMp=GTL2dP;0z{P`)h_X%aHh>B%>0XzSnaw4rqk@-=M2PL92Wih zAR^%kh+Vz~ZM4}LfFuXw#qM}M#u|>qQ76|GrOCybMI}&i0f(+@q>hEp(|*fXll;^v z+ni^ZH&$+|$vVn9#kBkqgJI9x<+_cH?&?{5iqEpI%KER$DI z>s!`J^X>MLrKQ(xBP~J=$CtUP<0#0^G-hR*uI?i zlA~nBbu1paLXkjUUtC6d8C^sb2zd+E<13PnoOv^GKn41h>osA zD_&r@uhiS7Z6_IZH3~06E5TSVVc_OM4@^~rg8}HL`@55m&0dp(7SPB7mRi;%Bs|Ru zj|f2y@9bT)G5Qo}mv8S)JIMd-xrqcoJOT9x2U2@jL|10j^N$gQ10$Z3`LH??U{V%h3@d|2+9gb&%^+MldNDx)|ZyKAj7bcVhpl+@x z&HIjvu43{RUkB}1yGQDKpG9ZxvAXVdIJ##M-icZJg&i7cwvdi`nf&#D^o}h~FW2~1 z+SezIi}d z12R%zTb%Us$QsbJ{A!~=(&ppNYC=@P!KB(&JXzKIqCm#^tK(z7Ibe}@Gi5U-2C>Xl zhsW^=qx!k)?LzN<4PvSy!H9+hE-!aL6DOpge`}#7z`EfNT((f#WOh(ebz#AV_npG= zH*XuYjRvdWFF2pn3l6j8>bCaZ?DkcKw+m^-S~Q@V-f`;88y+!(t{wK!Quso0(=&b zyfcswwB4(oX75)JpJHN9yh$xe>F#r3uUuP;yzy^m)#DXI5l*811t3CH@=QqGg2wU( zM3sH~cZDybHuJ8BQ;VdK=47&QySdanEpA-jXyHU+fLY4@X?K($g?=*skd6p( zO7y@K7FTdAQ2AfR!&yAh$3|1ork-AD6{_gEl$ZF!mp_*(n{aj`Wa~d30%%SY4!~u; zP3HaRS&4}SmPZ~=`D(MLb^`j&a3gIJU!G{9RhDk*C12E2^pVhCjk{u!0RdQqCG9<= z2`3Mrm%$9ww{`rt(g=UoFN{E;A)i2!|1z}a#IM#%+x|PdNG)fQ{>#F5ws2}K-Z!*khnu>O6shIU*yfmCkFf) z3n9H7s*-YEO^7B|Z9M&!bW@A(c3jbOiGb<4>=qxET8M4CE zVl-R&OdCh-qa)B?HD!zP$rq{t24+`Q4lYKtlr7^T56zxz$5=M9l)Oz_Glp&Gx3!DsFwi@#SXoruUYCx8advmu>0^jyt)sFM zTGu*5X{`j{6?N=Fin^hzi6qg^tU0tt_V_VEv`g6OT@>_reUMuy+}}Q0LBrTx)@RSi zYscurtZ>ut{H+D^BSOz-t3onpX@fy%;oV|1BX8bE52@q~GXwZTRm_ZWUA3z4xf_to z5eC}+&dEo=%9X}#7DTi{p~G!tZ3B#Tt#?@Ghpcb)6Hk-w&yxOb8~;45sx1*wu_6u| zyqztsbNuLyBb_a*qFWOL4y9=0HW) zFEj{#nYjLXYDllimYiT4d8ws7=|QE&P;I?tZ#|lS`OxH%TRmk}8i=!f@cPZEwMmO2 z*vARAhY>$C1%-Dw^7+*g);2FSi{|r>p5_v{e3S$3WWmXuM!bB1@bjKtLU7fHs>&{3 z!+{k_8Bd=7bfZEx@h8w`Y1R7~OQuC%iqv2v!(7Scw@Cw0?H4cQgo{@?M6~ZwK7GHu z`5#ZRa@LdNHp6Ra{eA>n^9F*9p16`Bt}1j$_8V$N@9I4DR0S(MqML?}-R(0HU_?sX z?ppGt_^S4-CRQ;m>jAS2;NgQ$_5nUKQzCySP~FB?x|)B@@%!G-)XodFzCL~-$JTTa zX^=;n@J>LGqA_nOp5|{P*ZtH+=)CUPOx1YQ5TL-Cs~3{=@%+@zxQ zS?pn8Y(g+9xFSY-%_9l5rocp&`1HIGcxHHzoDh)Qtb&+D;*93%gwD3Jq}R@w?N5YE z3$gl3gN-ue$+&pZ;mHotCV=blvTqIB%m)sgD7JMheDv+XKKWAa*`Ji%p^^wCN98?V zmz93kISwXOcYxm^)&=;|3ZIvb16TocN;)x!O1Nk;G@85w;v_*`8UIVf5ZxN5lN?Fa znR>GM11q7!Sv;U?DcxemKaf{A@sZbMyJ&=H->eKl+{ofgL1+>FXaEV1DVXB3gv8=D z9}kKD)lDl7K5vF{F1~B?y!6+l(-yQ(b3qR49rt^QF9Mz}6UJDK?S! zSCu(->)pWwXV`g)AhSEdT_7O`!q<@Rrq`PhsO{0|c*m{nax(YGL)OT(RHi0W;V&LM+jn2cjZh53Jc=XDTa6p}3fm=a13nF#F0x?-ip(-jC{&YPv~U*Mb9v z%$5h$0y##VoVA$yHpFyTdJKvB$8HG?C0Lqx+!qEUGp*mV)qTCM0Zd418MvMz8O$30 z`XwibI>Z_?-v6PcrXdzrhX7PEr=&v_is7iNEF+_9-btYJA7V5_-TreHvQw&_Hist# z2izduJedSj^|*{?|6F<$31bHb-T-Gj^ksV4Mcd5a`dysd9J6^Ho3(Pdu?+gQfZUJ&C}?pDPfu27{rM~%;g!L<;279EJWBoXd0_VHa}XnAL!^zG5Oed2y~Ml zbZ0y4A>q%loQ;?rImQ~FIDKwCNNLz0U5b(-TvZ!PGDf) zS4T8sD;+Qvf#y2cp+HRpwm0iZOYNfl~uWVq&sLqGMAlkgH7aw@}l07ujh)6 zQilKyl@E<^WiW?j4}XN-sxDg?I^z|#m;IJx5o=+Ws%@Q{n|h*VrLp^kt48Z8Zu1uA zJFL!sOTH`hj*RHMTb6*Ea5vG(b2N8yHFiiWG;!aSQT{8@Bh3potK5$=a;h%s8~A#* zy*+zPR&g_V9uHS!zzP|WdNJ9gd$lnG5})Kvmb%V|@+RcEu_jpm@c>@B*JG0@wG^vu zB!~XU7!xeNk7xl(HR~FcURRcU%EPe~Z~2!vYA$b225=@IEmjY{+NVcSX&I@v=yDv| zUb(wiriiJoj1_7#F}*Sa@NmG2hB^&)z^QAEPLvx3m5Nx*7mqTndB+&;RZyo7Q zd$vJpal73I{&zaD7wQWyt@Kj)8@5~mJ+IjTEt`BB zE64vQPWs%G4H6FtItsQw>*z|ATTeCNIej{OYjPDLiJx_LoR+H`DNewJI#Q$X*g9ST zx#KH+WNGrFgB)@!%$m5Zc(lq~uNGhB(c3MSg$ci=eCO6BCr9QV;Hqkxz0 zPhWo4-%nb}?kYJV8)WT&F6liBWH%fs%znW5Q*c(_m@HoyXN8-md_lp1Z#3lj$<8g{fV@xk!a!0zfOQW4K(^64?~*vb^~d6jOZKf z3?G)GLI;*#`SQO6@QPM{2*i%9Invz0={J|zjp*B!OJDRKje;m4en~#jD&V8q_Sraw zg0hC|sXPeDXzej;^L^&oeTXl zN{lvUWOLHDbga0YdZbfIMbUMpgUau>k?A<~7!%18+f?E{E>G%#W}Re)I+e!n2b5znQ2$7U2CPt5){}&vc5`Qr#daA&Uha*(_s_ zt3PYB4Gj!n4h-_%LGlLfg2KY-I^Wpf9zuQHxo(}6%R!Shz+i;E%fw#mw8{U+^d$^B zbh;*iQ!AJPPXBB)uuWaT%|q@yH@w1#*g7sD&plUhqL@4MzS0+`^e5yn3Bg+R|6APEos$75$D-E?DMMLh@5V4u(=PSN66y$yk2`#Sn@jS>^0#6Cr0D*(jE zT6j)Tj}J<|GmP+e%L$I89R0JRzazm!>f`qbWU(NB;QFLL=AYHvbH>zh=@%OZoX~y7 zD9so|PVg*|kUg8H-6nUf7i>_>%pN;X+f!uN7Bk}8!#*`76+Bf)l$lxqq;?}heqvbI z?SJNMYw+Abt_W5&>KmTj8^qlE%T9{b?&*FZx`cSDr>z)yk)-1jG3%;UsJW`kQyldN zo|x>gSCOosx&g&8)>Q!OqQLWk#5GTkfqiSMuY z*b#-qQ(qQugQ~34_PjPbTiT;XUggcu3O2~_gl>Orsp{~!9pxKYKS+VNX)X%VKLg|` z1HF0#41X9MJ+o(2zr~Tm0n={Q%08qH7QKwJ(u&>D45W*=$ZM0cy(C}Tf8yi8lzXKQ!k`@V; zn*qGgG#O&wc2tj1pL%s@lJ0YOH}K-TyJ=BE22FPzjGEQ40{e6ahn2v^Q^pSi^>=n1 zD2Qi}Bcu=?Kx)w+mR?z}7AoGlCQx)dqGf$jgCfX(&c3Ai16G9;o}9yHaLTT3bQDx) z_w3%?dsBTFpO*ohuSP5W^ghxj1NbMfTg*AKgg~lhe@{xzf=QExv#6~C;FxU@IuJF9 zNhR~A%-Z+&@n(G*;~71J!12qu`#S8bm_KPr<3R95VH3T%2Y(N=SI;{6tkLK^`*Iz& zAyfn$`R7-`Po`4F)c-?^ui4T}W=`!&?fbe^86 zxB$8?b>cPr=aC%gQ=OP?AEMD*p{|&BL9Nk;k%`&0l}F9@>d-MKY#Tz+c^#*|Z19|< z>i>gUZ@QS~Q@px4ZGXE0CVB*#-x3CH@wt=i6q{uj4zESZBS}t~UVyeLZWZ9HH)C_sPZv zlE#`g0(k=$XQ;f=5;O~zxxBaq%J#ofUa0N^#EK|e9F`V&mBDG*r18(v=hCKZ! zKt$QX_8k=`FE~Gx!h`oTY1AaPpYcQmq-S`>XnNAS9tefOB=H^nT#qUAI7OGr%d;&t z8howLE!xCR+^&O@I)5Hw?tX`-`PoR|WLhgpKpi&yyCT$~%`-kYw^?3uq`Wdz8eBhi zZep_6bE>~2lfm%i7B9S(TRUF0^bTz6gcczV^6XJS4X7Klp*5HnaLrk<=Z~k7!yuZ1 z*;@C4oIA0QriP0#g(zpN9}&Hb@5RZ775F}<^Zqt^fjom~yR|vWJ(&7-j8Mi-_^^8ql+MRT!%yB^$2$`7Tn2 zj-y(B0zo8-LRI_W9nVA+VjoNs@6^QPWo zK#)twzL@F8kry&f&wWGX#3IjqVr#mS}e zF>R(?01fYxp_;HOOeZdE17XZ)^xeNs*{s`0!|Il8hm~`igBC{dhp@f3AB$U z6}W_z^FN+O%#%5Kr-FhlJYn{wJk@y$hH2FiaDOqLE|t8@ zm0?D`THJj8&xv@EtD`F5AQNJ=p7t9$+Lw;L9Qur4rdr`^Bf*Cg2>tBa;j>MrM|AnNt9R8nBSpYz0Z@Qxr!^FP(uu3R zqkaRPRF15BSrIYUyrUtMxwn+2=i&ZzA8S6XpKo9ww?Fl4JBZy2u;4Tp#EJ$U4^r(E zek^@eaaN&{Xd`~uVi;Ug^x!KqMpFOf)4R&aQ3e&d&WI-2Ik_$$EfPJ1%?D{JdOgp1htRDRVse;l)<#8)Y$j3+gtuHc-sV+|xWOvt_9< zL}!GTlbZ29IGN?M%|)qaFs!Ws7qt`=3b5qDSH7x3o4{$_*Esk(W&huYlUJ;M#%Q~q zqSKg~98O7+KQp*Y-A(9B4?c{%bRSyTj}iG`psKxU`LnyQkPV3Zy+Y?uSHZba*|D? z@BrXe@6s;D68B{F;6t+!%ghFsnSi%mf^O0FTu3?qTm+Z$;&c1g%1f7>+i6M@R%6@O zcv6}%?~H=I-{Gq;eSB%ZzRM&G{8OYfFzxR0_|uJUi`ck~wMk#*(IsfhWLO!jR72ns z;j5){eOC$AhKL@Gn$);fc9;MqThBDC!1@|(d3l$`bH~t`j#co)9Pme9u=85O%KAi6 zsB$d z0S9VGdo=7T+P3;Nx-`$-F_>`T##F=gg3qtJWfN>i2|yaJkJ+{og%DLv)xNl!xuAS{ zdcC(!@cA;DnL>sZygHk3@n4r)_pDD?eKHF8gf0VxlW@W8diTn&FOs4RCBF+*OKj^!;|JG9V} zg%$hj^VC&(qIdKT3QNmeN}-=S?kZ)Fd~qD@RocDx??U2Lu$ximvT{Fj2&u!CudjcS z?f(uMF=(n2R;r=XyEnxI0>h)1HwSYr$L@a|voVefDG8Y9()qJ@bj;6NJNCWvy==j4f6)pR7Os0VZFf2A83AiA6i}G% z?u0z`dv0v2)kZ_leVe;3ABNUBY^9*zGHUuB@J=&<%z+;NB1>J^fg+$+b)s6QoT)-#ro|^kM}a12|?(x zUl&RQ4So30KQc7kPoaY}%e59P_`^P=X95>sMjQcavrSSQ-Kp49HR|tcL~|s)VC!+! zHR%mAI8`bj)THuB@V9{E?_GCFlFX`I!)Qt5WKvUF7lQ{(LbcL-aLab%xacV5zTf-n zpyxIkVqE7+5qn2hcyqpPAO%eON>`lhhh*WJu|Vm{`h%`hN|9o(eN4%R*@>`_aBH@ z{ikZNSK1uw3SA0f0nd^*p??DU-TN%*0$odUY4+=+a;xFjnz8+=>%Y67xnFeUUkEAz zfK=Kq-H8gAj|QhRKTp1@**?icwaMK9$wBVaSaJHf zJ)-o3aqak}F4rfW@AZKMIdID6hzqlF{Qr%D(u+jqQt1e!u`iDcfO z^5*+@1%p|}=Ry@5H%V-P6MN6o+QRswn(gN$H0@E4Q)?;reCti!wyizfWzO&qEJr_1 zGV~3b^U&^st)eEqde#9QvSa5NMqj(8Zb_}Gu_}K` zmh|>s!iyf+k0A$D0TV{2cXGsnx5;)?0W3o5M%|G^w(_H;j7c+}lMc|TmU>DGp}Zrf zMK?FaZh$U&Dmr`CymDh0a|D*Nr88jYBdpxqXA&8*e7iuacN&H$QG=xtocE~*S`bj% zw}(}OkFoZK?o8aFUzP4(UoDO5vuVAaaWF+255S$G@P-Nw zG^AbEC@S!}VzX9}-K=9LH`y-(<8p40hgl@jD%MDWJm_{^D(p!hT!l3aw1gheoeH{s zUmb=EMfi&+@`gSnqyxD|p6LAwxbl|ejZS~TCx6XNf9B^+Z(5e&S-=Y3OYu1ON{_E4 zjJ8p*z<-({>ol$*;k|s#S0-xXvFzvIt_J4dgz!oYUsWhz>fO@#UGPFrxPtm<2B~)} z;p5BjxO|=DUfOn74eMh~!^I&h2OAGA1~npowP5IkDeJ@))Y> zv4;miD987yN)5Bi&Qpgk%|$X4cD1>`g4Hu}ySyL6Zt3Pt`Q5YoO{wb2z>fjcbg&#% z$C-UHW^U_IhL@;`lsoC7eO7H^H;-G`*wY{7skOL%yGpAHB~PF1NZ#6HJI0%*5*^<4 ztJiEk*s0bVKGMVnq=xagVZQd~%e z*Q^R^(-KL>t_iSdQhV*4jA3;h$zV2W^jVshZ^K8WjkA;49`T#9?HPUpFu~+!`L0y3 zqg|Fz{?X&9d|^9gcem3mh?OKDfjB>ZTz0zsVFC_O(8AW<7uX)W#u}m|1hd(QaD5tx zAv;gh6*=Q&6I9lWrYep|s^lNL#B(|TVhG^a=G;?^aC1(+| zN{YISYA>Oj9eO`dllpC8nX*hUJkI&dJs+Y>Mz`V4hFJW^V^cSRm9_7My)sL@f9q7` zu#9krq_*_y>AABQ{WmT(Uj;bnfZv-F-g-c-EA|o1{D3?;sWSaQ+U(NpL&E<1MOQSW z59%U($T(dyv96{%Se?_IYY{zP;kAaA27W#^>zxDNAG{6X>=f95rPh4bO70&N$W?d+ zMM#xJc8T(Lo`_I}F#H#WPES48O|LYmuy=6^wbgww)lp)doTKe)5Miv52y}_ijklyH zniQiKh>i@8i4%6!`faOCm#l$DbBh`aL>{W0^xeUH>mRAqi=z-5tpn$H8EzxqF47U+ z1Rvi-si&B48(|S@V2ix0+;Vz_$e)^|GuUU9AJUm&ZUMWU;joRIx&L_nf!l5J$2ZF& zNnTB|an=5YQHWP<0)3ZdRHpPjV{uPpX;>FoYQ3i+5<2j{os|ot1vypW20! zN6uR6iXYfa!0u@Gc27$3^R=gtEqqYXG~+y=ZB zrDl_4B4~IGfcj$Kcjj3dbz{&#`2_v8e-NQ(9tA7$8+3;;kCQuWn@|-TWFP%Opigr(%N{QHfQ6FnQ?+!FYv)rqy+Pf166rN5$po+t%hO`GXjbg$gb3$v?5lbtp5anxA2S!NSb*XcpqtjD^ zUA@9pE*@92ggh3AAn}O*C0ih31cPnpkQqk;ijFvcN6b(6$s3pF6)VOl$0ZNqc0Hx^ zuMghHJ>2LjOn+*xo|eAHk&nGdF{wlIzOP(^8@u67zamlijr!0wu!CngIDN2*;kng9 zx6T$^|4PtQ+a^dVZoQh!Sp{A}g@Eb%1jMiy-$*MTSKPYrV#n^qQ|k|c8X(qsT!Ft= zP<9T-bIX^Br5G=9w_*o4YnHY)+DjhHEINsOp<>T}66b}Oo;5$wt|eHrX5y!GPX5Dj zV-@i;4=e)`2@waA8Z52Io~Hav){X8tq+t6K3e0W7s^YdxVpdvI%;7UQW#6DZbP5|LJKk=wGj3>+=9>shUI0HpyXSr)T}3F zevWD0vUu{o`1j*NQbBx%u@f!l_m%-l#+@bAwIt z_cz()UL|nW+!|A?1!tPoA_cmp|0w-x@!toMB1$QW%~VT5`E|5nTOvsY5W)OYcDdul zlrsT1ce$@q3h82p>e)C&t$q%Eu1@uT2l9SgNqv>cS;ME7>)9k?*&(-n|J;Zr z*vdnI`dnrrFn1H+-CRkURW^tuB~d+zs}^>A)y1pPT>2U6&%)Phg5#-yWN{RZgDM52Yw*{$vI=Tj9x&%D+E+xnbEtwII{ zm*}`#oN_l8-Nzlc)l1<`UydPOSwskN^=_V1gL>d`@)4xH=ieR#Roep(s5JnP(JKe5 zj+_G8V>AP81t)XH0r)Xc`X!V^hhw4xbR>quqJKO8$D`(p#|0GuFaHbt&7^ivzC>jM zV70drxE%n9{KGOT&&}8j&LX0iBk+NtehhYhrzBK`V7xgREEjV*SZlV}L}sqy4S*@W zlJ|8=&MLq9v8PciJs6Sp*qrXHJOrd+m`nMlNzo8N+5HVGO9VQ6jFi(qBL+logllDC z1bJirXIt_U;SK;NW@5BP7zzEqQ$FHXB&Amu?$d_&Xm3vA#C4 z#(%?KjtT;#P;k5wN%0GG=`*G6EfJgkczk-}VRa$iNDSdwkR*wc1PV;7Ivo(PTzMbO zy#vMZj`B2OMBW7jmZiq=MoHyM=h=!o$gf782tplM767nWc3zMZSjDx+-X;NpOX+G? z>L0m!UGg=O?e7-nm>Asvu5$JNcwop_L=7n!2<>o@hPqEWjF*^cS5^fxW$JT7mmW*RemI%znqkgaRdD@|aha{}U;{Y<~ zt?Gbe0&eaL>D=ymmj0^5GWtU)gj8Nxa#L8i^~`)!z<&5L&dg9dau9ot^R;TDJ05OO zyq$$>MP-zRwG%U(QTEHW}Q0HeNXpg>N3b`k)Ls`n=QcGNjmAPe+szt<~<5H zU&#fM#cG6E z$AXzyJ=4o=N2lq2NA;3)kU!x5EG@PU1F`ULyz8Dc&nvHCL0MLPO#nykv%rpRT*=rwn|X=pK%aEb zALGN4T7669uML}nE6#gpN&(&(>~08HQAE2c*+cZ#gG?9^k10btLJ7+$U|S9{^8(9W zYQ_+_v*0MYaVLl&C)BPS{U6UcZCjzx4x zp1I%@lFu|%e_od!&-u#mw-35OsY^fp!@~-_M67SF>m;EkUu$seS5zTg?=g=BNiPz+ zEgbozcU#NmIrWATK%s68)L~mJ9h7%*tbQiH!w+%%z|DmoNVplms~mzdTnU5u(;<^?akr=tEWK;(?iy@W>1Ck8eyasjL&0k&hU6 z<|U(y1e%{T-A~!Xm?zzTKcv2Y9-iTUh&Aakq-U(3+}mVWNjQXonm?U#P{iA7G45pxjw0WQP zX*lxe8svE*b~NynA=tUR<~6@d))1LtJGF2}7KjI~1#SbM`2vOvKhWF2;GY*5p4in3 z_lf=V!Wf!-nv$izl~xybK(ON!>x;=0@K5c=2c-ti)M$N1CR@Epj>N9SF=t*u>ODu6 zm@b+q0o_-{lc~C1NWoe6yUx9;xY^Z*Ha_1Vv%UbgBTx-8W-QI?y*G+L+7~D8gL8t% zw$>etHnGhDV#Y8|l}{6>xrZc|>zOxIEmIkYa3$C8sj{;E+Uiwlw?*>{D|e2@)k*+nH)|H3BJd0oonGUhVgT7PU8YFn)1~;vk#X) z3^k=1+ys`y3W|@b)E%2hpP1I(X6G!rr`m(cEv8<~?kpy3N2U~&lI3z|Ka>UROx3hK zAV}|>1HBUuj});7kDS6M?M}0XTbbd0YROyGqQVI|7qt4iX!EOs=0R3SiWhxfd+FY2 zSzk+XjnR`vsU}7+5J?CW5)%m%=3m@$cNRB~ghv@SV(&pR*>s2=w=+_uZUoLB2vbOL zMD>6Dl3{ZKlboCXj{mj~(QQj6Mf{o(N_{uTnP4+7=4Wv17jhsV5XcbQdl=7e8FJ0^ z2144Ud%EvuK`>1TpSHnuZ>py{0`u|7XSEAk9tG+cL*i3uJrjH#|Gf4}fkR8tIv(1Q z<2j~21&(yT-*6XNlp4me%?Lkn48oM0v2X=P7v1BKkpmp>qc*6No8T!@XeI-v8?)Xi zsP{T)jp!>4{XV1$?Fw5lOji&79dY{aV%)qCP2r&=p+54ba34Py#z#N)m3U&qTkKZR+c$s}|i~Iu-Q!w%@ zh|$WI#-f`V(RGiPD^0cJ>Rv;ZrC!T-{C|L*^(Nx|w?vO06EBEZ)=xvX&=r6X=JnF> zhrON5n6^ zvic(+d{36ofbRS`%-?^ktvEY9WyiCvAQ3Cfs4A>ljxW0xAXb{a(SMfGNK1RodY3qRwbB5_|TM!BEZ-gLsv93wva0qtGv9SqmXVokBbEUJ1N6iOmNU8r$f!SvFoNy= zv$;@r!?n$6qea_-$Sz%P?nnX9MFctT^IL#}Lakp#RXF^XR(Tf;`q-$=bL98pO0a2` zW&D1Ar)~lZH%Ft~n8PJZ(2a|I1nayXkQ6J7uQvCcx!FPS=Pb0Qbob6|4Mk4WIjmwb zefMBF-kg!yg6PQ5)y!j?{M_Rv^ND((?W(H4pC5d`p!-7od#Mf@r_x0Z9Ru?DZ*)dR znJ-+9C@CR7D9DbL#TFK zmJlpAj@Yi#t<@v@Kv}JiPW1Qwf4MrO*$?z6VqHev&P&v}(QO8|DX`16j=z+z(%-;D zAKCw_a{;j2kIFD3t?w$4v;tZea%B6|%53i0oI)AyUmVv`bSygsRJ1;|eI_qJ+;5QN zggL^EYc*i$Vm=XJ`9E=6yHe*8$}7;DYhl4fkKQYdvo?NXV6$LiH>5<6&o}Dw*zF1t z5%hy@*k(P5CsISq;h0kPON?{CK6ZP~zh}QpVUlwhj>`k15lzOtB4vxogH4x7&#Dbq z`lykm>i^VlAivev7sY__IcPPl0knA9`eP;u)9L|mifGR?Qa+=!8yJgM)c&`S+GF?Z z4wAiFPbjUIIvk7Ia3U}D$avchtzVWIw zyLYmega0jlLo6p&y1u`TkH;-yoUF0t9>Vt_$MNbIT}|QF(?U!g1#~#1kkIL1(466m zKH*m&Pd!;4hQo$i8*QT0%_2-Hm&c)&OTx+@>tsLIY7v=sQMpI8caVadIQA2+^rku6 z1Miqq+~iYi>x@%hluNb6^^G)B7ZxC*k;8bhb5m7<+EAe3YD)T(7^5rKPwVvd*q$H( z!bbOGyy>aGN!LAanCQDG&#}HO$M(cB8KRH*?8wFk(K}-1Q9sY-o(74NHHJ}bziaG+ z)s#u@!oDk|EpWUWK;sN|z1Lq&Y@1pw0rduZb1$!dY)csK5JA^QbGgJKX>MRwP~!86+55fB z53t03lG4UYkhn(y%%dOc3LjF{vaWaO+fp< zHcUVD`TRqiVJBAxl9pd!aee)nD@l&J4NjUM#H2mn+b>V*=<}~%R|xVIQLWeys;B%i z_KR4{{Jeh#oiX(n7cBN+aknBBNQ7_n)uhY}VEos@z+yIm=)~J<`pIY@7pfzdH)`~s zsu%K3L0^|$l*nSh#1szepPq}rd*r*OdxbkLx`ouK_GMURkdA&_&R@YA*$gSpAABVt7ywq*?(>Je(CRY7!~z2P93VTp z>i6DWsSC`wGzCSS20cR^C)U2jJ^JRtG?0 z@{Y|>%fxM}&B@9OVHd;3ZroYy>0PVo7JEVZS>ZpZyRu2V785S&T59C@66M$clWjzFX?3$s=pC*@piqbpFGIw^jlzy?H5t>R zRCeXB2<%Uu0fXk%bhKHmJ{uR|$jkQDc2yWSFEdW2qLI>1hF{=Ta}CGwfXJo1bvw-Z z;ZPvfnX*(AxvCxLOsc*y`&y>%>B-b9?1VmQWl54@-gPBu%@KKKcoCSjhDrBtU9>bg z8GPpF`~P_Kv^LTGU;K{pd;1ob`3{JHH!zutzB&fl>W9RkSt>${?%a!^Ya!|sxw+b= zp7Ml5lxEHS-;}6sQ|~S}mM(<_h{yIb4T~*Jq=Sd43jH%2QeN0x;PSV7cQe3>VmBb^ zb^BNw7h;6mF-3SoB=zt3?OF<{wUj`K5tIQfOlhKtCnhhkM)3lv0t#y%+TbKv7tqA} zckv(;bm1PUjtZ~BAZ0I&hlkAKHIEbQ9T|}}PCI)V^3D;3;&s0FdXas3#hYqLV+6tH zj#mlZ?6vatC7vgNyBas6Y!VEx_5xtXpyfyXm=HsZ9GyLKSLvEn5%1(-q^^1fM_i-OrqlD-~NtmevyCVVm!Q1-lHwE$CXths(KchA#Vy zl&4W$vrM*prL%=td&v!NdMSw%OiM46}KEEjZ(I2*~-$#hIn6o`F@hqV;zUz_mF(K=YhC*90ndDQN zUN1Dv^m@oo>Nxr9FRSmY8DJ)`fESk0#S==K2#w-;oj` zyCvJdVIFnz@^F&U%(t0MgL1u)hlDpky@`EfRKt~OuRSC8kyI&6&Yo0inm#o>tu3wIDjG=&pRurMEdA6TeMEr}=}vyrUFG?5L-oE&g&G_4nN13wdZ{=5 znKE7kHpiSlfq5R$%cm`syZj|vwN8%83Ju zeCZ)n{C(y3A_kxW68=kED}4B#rr6oC=#FRxJHnpmE{2aAygXPQ$WXrOcHfVwSmJEHR z9toA~P$roD;__|@mX$)hC07q#Y~Q<@gYT_<@M!K#&+)BE(z;7@=$8)1p?J!_1T%Ib zrk;-v>oZ4ti{*y_7|O4khF83_f+|8?i>VEX&bQSbq`t4cNy;sknoAiCZh>xCJui4p30OnE z!~N9E+3Idr_0B#SAK{UC?(PUvhFAmxQFD(vNv>P6ZvrbbEJ`<`YVv~y><6d$2I?Lv zb*Xr|`@weD4l)t=wlu^UB=;iQY-^>B@^Tw&cA_ZU2d4k)qL&E!8@@PT|H9@?W@eO2 z#n$<`i&YCC{7ARWSW#V0n~lHFduJ!8b59PICaf2?Z85_IE5$t&08(}!Kwp|UKmo=_ zUTYY6MX@2$oHKjS4V?bW6F+L?kWu+!t1fAQo*E_HpBxl7+I^HBH!d!UGS2ViZcc3? zDE^y+>$g!Ecnb1T{9`llzazJ|Vb4s-DS})dnzQCSvU0u=s9bz^x_kiV8zM5K)9Goc zsh*G{=`S{8k|tVLZM*zUGuy;E+ zfsh)ghVwH;J`fy3)Q7QZPhU85Xnj2)Y;x^!rlR^1D!FSZ)Y=OcAmdZyFPkMwOEg@g z&h|~64(&9Yg((e1PhsjQCvBtm40kDzpZl#GwRuDgTwWt5^!FZr{;G8?k%yNzWj&oT z>MP%M*+wp2d9d;;82x_~orhmi`ya-=w{BLh+b}a%rDZwGz0%uomH8XQ>0TqRE;nv)WfZ`s2BL!siJHLN`7aYzx-|zSHJkR^#w!!xu7xx;iy;Q#z zFSxT`tYDwd-C>^uJKJ_!AK{4zZu4ZX4}-Hzk2Q-)P5j= zNQR?q?sqpP@^3a@KUfE)yRP~rQYs2tiJ_wWd`3tf-n0z3GsguWLnZz0wwX|^7YAkvQOLn8no*C~eEyHL*R%ki)uX~^G8!>$!e9EM zy4@j}Xi(05ux8(K;CKQfn{&D)STgD#EBA8Tp#8yL}=Hnf8aPB28kTS4Z^RhFwf5 zH7(iqj=OQ+Puw6Yr5<2ke zJEA4%xK}vauWRv*%$^+^VTTkc9#5XR%qt!t5iv_=GZoeyAOK*KB=jnn&z>dW?=K&- zlFyXN){1&POs=XpW-zm)1N8s=CQQlRUt{M*6n9BAzp#&mhP^~V0XoYD;d67Eb@7AB zVM@*;bNxsf&{67{`Wkv8!-6xki%cy5-z8bwG{z*!%{Ui^O0NR#jr{Nd&NPfmMF23K zVr>t_MJI#hZF@+QQ9!gu=}vbW-bjk;mZ2|9(CbqC`uj{_eW$&VTdcuqcsLJo6=05e zlhoYs?N+>)ZBmAhQXda`C3OXq7uqcG@L*)NbipDHEwd4UjE}MkFPm8}5b-~cIJ7)T zQ7CciJ>B&$7x!-IO?%;c@{PTrv9@ztlGr`uu1sMk+$brj-+X2|)5ap(i<}CXYR3VJ zRsEv&{{=pl1s!m@eb@*I1-VW%Ra^L&iNu|DGdz~opMGj%7|3quo@3|g3P;_ddoH#+ zV&h5jK9;*SZJ{p^cK6OVS_WqN2Fbj0CF@^?a zE^kaLouVA3uV^FSZH}|9c$(;ESZg$DI*l_$Y@CNR61!6CX66CxYwo*yqz-$xvu3=0 z>i>Y7d$~h3Hm2GwIHy1)vQVdQnMin~?!HG8!K@8X%jDq#rEcv?JZ~Kw~r% zn4wUdF|c+_^YT(VAS=h<7f(7Yq@H^bC)L>cvS*dqKC4@`$pt6ftt1kgE_gul9hQ6) z!Zqe($2mNlF#^|4!K=PN5?S7UMUMG>{(R)Ww-fev{R6&}(ui;S{eP9^l`6Ir8aW%e zf!g=R!EPS!Qc1Np^A6|f&Jd3zg39Q!NXm*mQY+QT^?LPBrf<}>^gH$R5d%DXGA|Mt zwcrU4Q!3WjaGiT1=L|1VZ2q0)jM+v-;VNX~^J&j=3MugWi^MZt1huho%duK{$hP0D zUnY=SX^y+Xf9>J+VX?_KXf2H@}GW?F4YG${U<+*QbQhlGb;TbqSJvA%j& ze96Z>DXzjCnH9`J?*C1ebYE&*>$|y$kRxbI@w|%Ng`Img0P4~|9e;NtgXSa6;ql`2 zVqPM~*@i~Wn3`e~rbMuyqCZ@tz>bD4t=m%m|1uDSCol%~rb9@!>Gl6rw`Um_$oEa3 zHqypM`8gcPiJ!O}5%_C1+5UuXz0|bn z(19dC{zV5SGo4^R&D*SYh@_9u6ZGhB8xhk93Lg~uq|zac{pKtENeZX;?v4;PWjn8r zk;Y&PHR6}m6l#c1ePTgP7xtyXmI6oaChh4}-(_+EUy#R>{ceiziFRbPAi&Q59F)L-dileRN3b352|T#)Ea=I;E%CBnM)j6bo~LY)0@c)sIs zb9wQ@O<5`LF#kR=gRqfxz;_V5rFbz6DrRWWf^3C1JNL<`tvrP`*A~LS)EVv$;K~@h zE%9p2UoHAJRPs>zO{6nw;!Pm!BVdctEwUT6t73`l@M3tPB)_j$`X9dkjSH)uq`|6A zz7B{UmL2HU3b2dcczl>WvHcBs2H0TWSeqA;4uSidT<);6>ds6eMii%?5%pa)8zhFb z;pW$6&FYu?Jb+mCUMV(98@*;KzTC;B9Yu!HS-_;Qhz z8u&`)RWE3f5 z=vRY^1vF+(la(7IOnwi!_ccu#WlTfUSSRxK{pQsu-|TgIClO@emh{49A_dw8oKX2w z&4tS95){@%`Yq=lvanriRF9J0?xrvjJdd-%#8yn*(46;Y&w0=D5$TkH8ERklNO*$9iopZ4hc#nx0(^db6<@LtpAYDLms%sJALeqU6j&YqmswhxU$MQ>z?BJM{G*?epJcc_U?u`Nj+xK6^s7F4)a zI@Q#{j8H2nh@u~io+~_?Cjzwvh;@|^pp$0w_-6kM4n?)Q!o26@zgc+dz$aY9)fjRW zV$1k=>vGy}!Kr7@)`_aFtb03y=vzC{tA(NkCe9CjL6}3a$3>whN=!0|gX7sb%6p-l zlfg_~;IZ`VN=?}Jj!?+1V7~=?CtUU`h4Q|@eK zv4I5N!h0==PKo#|wCXPLJ)9~`k2B6h|Cl~{ovShZ^i<{z?%vQdROENr`sZ~+Hy^st z{8s&oZKTh~19<71AJGEzl?7r=~Vs_^d zBCDH&JFnN4p~>Y3`sAu-&i=1fhAs;zAA;jxj;t5w20eah?dd4+c*B(Z#+jN|z(|CYkx!C0| zYDZIEP0W(ltd>jHft4~S4U`Ild$IuZKeT)|uj^7_+?8?2Z?k)QCduje^BIG#pI?4E zlTqjmAa+ynWF`)6Q<3pvXMT>PZwtJ)SZ%pD0hgeXArT4v&Nf5Pjf$;D@Hs>o%Uoi| zR3gPrhzBrCIA2%adkf}F=-m)|J!4?;g>$GiaSPZzDswdZ?hJ@YnB|0!o#$T7%^qHU zd18APg!HF}OolA#k|@5c`AKI-lQ+XcZn3v2;>OxfYvzYcZbw_USzt@5HKIpYBONBx znQRg=<{usrxEg<-TnJ?WLcQ&4}#FR#~4dw zQ9JpUg>FxC^Yc&AsUHQ}!i5Li5(+t||JsfFNxYy^_}9A21z;Q3K)3DCphQhQNOtd= ze{Az9-C!&bw^zM*VN9nr-FAYpIXu#bvSaiPgJ zK46Cc&0gg5*lkk}|4PhzUsJs#fO^?u^q6%&l>3$Aoq7k@d5l-;=`a8^)B(M)|+xpN@Z6WT`Es#2NtWZ#B35#_O?CzNi zYK9zsyHIcBX5@Mo4nR52#YiI}o<6mCcGIEc=pPf6v`xLn&sxJRi}dNcEmJF867HLO=bK zV&BHXp}Eqpw|%!=V^yEv1ChS2MN8jhcqC$u9?r|fN@O}hM_PKtUTO>lFhP>IKV0vD zV~@EI0s71oEswt(E$y@~3A_1W4o&YPkLbm`2!olmj*{Jw6VKWj+mt@OsFA$+gXY&B zUOQGxw`#R5s*p-|ti*~y5{I1ot3Rh322y;M3vrdk&H|)=s$PCApK(U8XNBkUmm~Qn z$!@BO3CJ`CHD1)8U7j((xBby?s&Zlv#5)^}>YBP$DdPdOUWb+oOYdxep0S|xQ4BY( z(|>)#^V$$6n@6XivmH@3^Os-F$Q@XFcU0ilc~x`?{yxxhvdz$nwD=kXfiab`5@H{kC%{`P6P4N60g&nj#6$Hv9FvGK}mi zzw)fz&^DyUz*yeNiP*vs8yr9Z0m^NkN^bMV-#(@|Jt&r`c{$U$YY`8Z)nJub?p_Iz ztAw=Mr*cITuw!3snY#J*Z zr%;OM|8Xs(yaM9(ukDa7Q9|P!n?3TVKeHrBVSzvTj?aSf!xWA3TIHjRH(^Y^H+}1i zrS}dUX)IyJK=5v&{T@L&!_p_3DH5c_*-n|?r$bd>9aEE;Y0d{8&LuYX?$&*4MYUsz zwQr6@(;fT7lFsyrn&zdSH^Zfn%(fth3AhHWES1pF~BoZAEt5*KyD*mZC7c|w~j$X;G3(%!&6IDlqqfB35NP*(1 z9_gx`7VYxOZa?NBFB$UnN74w7PQzCzLdL zLhU9bcB}*d3)gu)4>2G8U-Az7wv*RhpHV-)FKK^FUApvGt>6@=2Yn1hhcH#>CI%B= zTjHbfpp^t0-$uVsLKmRb`(sN5r_H}62_joY926{Db))HU=1t(t)eyQZK*DPq$CAJX zOf%Ww;I3@-bX3uu+cBpvy1wGR69F8Mc1)P>{V=ZiCwLyru8h3gZ%~rG?WOCKf(eDV zOm6EnNxxd4$L##!dNi&8hE8PfD1|#FoYK9=EqPHQIVzN?L(d>_Z{M4XjYadc?%HPi zE6(YS&Xmf2_#2@VCb|IQ1CuourgKI-1J?`ViA{wuQOdigbgl)pe%)-iIX7wu4@@ez zbxkQQGUZXFN+ z!mp4_yAU!ewOxOuLD>lCW<=ZI_YRg4O8h-v&P|NTrA(3cWhnC%TD-RTHBx!p0Ts7c zaZ`1Eb0UTTPgX9FTc9A44M&v!=C6i%HRAVGP+my*_aX24c^SkXE)>d-+?2(LjQYMF z%0gw+0}GbWH=kT@RH^*v?@h+4HzcldC#Eo+BxOC0s@B zP&@NoZ8Eb6A{zGj1xlO6!q4w5FCh_|bkreu_j-QGd>9}Y*thw3DO7zAVmufgo9~0? z-(8PF3owV~&@t>r9h-319pKz0FP}vMdlfg@;I6L_FV8R3zAUOgI0Tb6HxbG$%F?&qD@uFMXy7NE@TUc6B^=3pe_0&&d6}kbp;2o2{p$Izt!Fq` zf=rw-9Ud)em&n)NVJ2U}h{e0z`1@Xnr&osbWr+^>5<8osW47yKGeK1~%IXFU%?tn- zUy*pZHqQ`3@j-V$7GT7q>WZ@>##Y9D=e_?OM!D)-e>?c`r4ymr?T!doV#x~!`dcS@ z=&l2sAi}6dDt+x55;6767?z7XTbybdEjxCY5Ma*d-TL`usZ0>V+t9~-yYWhLE1UDFNWw;%O|i&iC}IGYVeY?)5SLS^}u z%uk9;fKjA7G0>NFG2FvuB^yF;9lf-(48JpB!rPr85uO8pHc&G*k?Y-ELzkVIj&#SB z=V&Y;-}4Wbco{Q~nl*0+!Bf+WCBt8?QI!|e2U?yKm>IG9t(=Xob$JUt2MoKdM0Ken z|Hrtwd5|H`cRXr93q$bT(TcQ2Iu^s5v;C$|J9;Ar_Frn~X7Z=rHmkktoEI8}Q6RTP z-w;q5F7at~pQ&0ORF`4(&xm<ue6t3Gp}odvO%)mBP+_|? z%`VU#lgafsJW-~ibg_>qAT!mC`ZM5Pn-FXc7ROITq671;UTKmZ75)zo&q%g?{^;>Iq zY8@Xg;y3ZL>!3hL(&K`*J;ZI>#@p`uQjpeWFur-@;a5Yv)AL{vT|3Lcp}m@jztW67 zaK$-}k#dDHzk?Ytm#<%*xVE)DNm)z2-I9s$!}@u58mZu(P5~FI z8ac}UPW*TN5g*XBJSO+}-XAVmNc%wYnH)$qZ~LtieEKgFJ(VPspQ{P2JWu)}(2@d3il&k+w%6qb zu1_%>U14XJ0}m=_=Zsgk-RF`p3dF$APuJj%>3VQ8_{vO!tDoJfW%zQnwpXs|^FpmC zRN>m;dHzE;wFY4Yx0eakKu};WcbYFsVdJ8aYv$nzst;9G-K zi~|rmU$bZTxrjfJI%&VZXukKgud#u82HEn=P6j9+lwZ1#E{3aL!R$PP(&`UO=kS+f z&GPJpR`4s7l~mJ&nlV2c?VJ$A3M2G)iTrEr1{;qQPr?9PnN~c9znzp|E^G~@d5of< zhx37{4t_;JLd$l0#F#luxc~Iqsrb5T5xG17>lGfdXQ6tBCu?bY*-QQpR~QQVw4xu^ z;<_GQ3(P|ozCQF_8htw7KeRS-EwHSTrTj*_ae;9i&sgF+1jLbT;O+HL{lDc>Wwf23rrg5Pb2ryL`16vqN zc$-h8^L<-*0UzN>8hGycJ+Zz4zIH>6`I%a9|M?aMsz9emhN2UXQkYs#0?oK|&6|;g zFU(yFeo`1^ub&zYY1I;aRVw~DVp^|w7M;g*R7q~t6tZq*MAapfue4sVHAgiL8=fC| z(>k4?`!{{S8m?uwGFibWmv7@+z5kJTUa4lm9FGHuVY$&-u(x`As*1u#3dU67fsZ;C80ThU-bI&n;Ixazk~$wtFz|w0@lHtvm;YsD_Dt zh*(p-o>A28!vju3st*oUqx_;%;g8_^QEkZKd7yEJO<71e2pHa}40p6g-VC;7bQ}uq zsoCicTl%IiV12F{mBZ~*$QZ>s-H&NFxg_%c17%7qRBL2vM3CB|op&F~CwdY*uh?iE z;C!te-4kqHs6Ou(UXdA}+$(SE-kj{l$fM6f!7a-LUSmd5UT3nQSOBc#Vj(5~H(o(W zYB*PILTQ-hZ?B8e7x9mCiaFQ7>=Vk2iJp~*U3LHh0R!}1cYoqgx!&B&s>{mgi|)_i z*?*RuVtlY=rAV>4uSB*5=vK5}TZFHz$Z%mbwJ9bM56R0NyB=`nD?WJTA4Vo72C1kA z@=o!%kp0ku5qjI*87GqVdc<@M{-m`<9aUoEPR!cIhaF97N2~i1UV1s`Ld|fofQ^n( zA?5e2`cjK*qbH5C#g#K6whzjU0Cf`2MFH;qH}ArToPXKipq4CKpYo^R4JnHOUNw;b z#IM%`j7g20;V0ZT_YfQW{&|;h)-FhpGYD)@qV6sdaZHk0N!fd1ZKX#FiN4Z`jCIMc? zk|e?SHtdi`)3FN0iSEho?WNvp&vScOaWCI|O_>j_AjqTXc{>tILUCxhb%J1G*PKAo z_66BW$8g}_Xj z$!I(pC(L|U!)`EKeO+hVv~p2m@#n?bu~eQ;FaO0EKi}DcIY=(wpp?gdx-ND)h1uVI z76nq0NfJ0f=jTJRu4KE2jk5s6;X->ePHO(Q$YJvA0_Vlt?fip_Oo!vzn}~mdca>A zT)#y>AJ+7EoKq8^@&M>Vs^>IOP{eFiu2Ag{mxiF52fjz`)m;vJq-HIIzv;zPvT^0N zLkiT}m}%^NA!4N~waUeyHVa17>yO|U0&=@I?GC?A*31d(At?EItJYat5j`+nt(yP= z0#McWJ3@ti5izm9Ax)Ct=ZFo7PuwBLR;2H2zJoPdyg7)!=p5#FKmAsbU~Z3U2p47L z!?6$HCkmUKQ|HR*uRq?<*U?4n=?dl@CQU52dZH%%GDBTg+T{DTeo8G&wyQ67Idfn3U9#S%Tw#WAYQWi^4{X|1R(Dix(VJUy2{PHorL3OqHpAQ~t0(!d|~7 z|M8x0fa*l@&3#8t8n9%cj&Zq(7I@*lCKqQG_Raqk@rejNuHJ4tZtXBwK~(&>qOLwb zi*)m!ZnwCG$&q?)V}I@?VE3p|PUqL$0DZ?AMWrrf`-Maz$*ScF)jQcg)%H65`6je{ zZ&ikm$=q1XEA78~tXaw~rgi|K%J}G+1wx^|%xmqs)bD1HVl$U4{-%S2>@pQpn0L>w z57FEM1V0or`HPv8%i7B^IZN&-`b^Bv9}5Bx*M5$#ln!iyQ_4zJZyf4F&Nx;dW^L+B zys+*^TlwuB^8Ph*000r~6n%EBtl#-|FVzsKCZ7c?c597y#4v}YsVc!QR^5#|DDJ#7 z5AdlULsbt$V>yBwNQ7G7we|}8o;Ol&`;7mNl~DSyusak*J!_Hm%`S}@`p(HYuD@=w ze5z<c zJC(l!mot*s>q3orhnhL_hQZSZyrH9#JC~UAg2103B?gV!RCd46F#dp50Hji z)NbCh@H!xh!#cJPT_Qp2&~7G>a^q{AFy4SlnZqAX^&T$ks)rFRF*}LuiaQU9t}#S^ z-uDerad+y0sj*n?WcB?;^K5mAh&x5L*R3;!UTpNQ0W$`GEAfxf&ch8@BfG9KmY}-N zLhj{xjQ!j>P2*nKpxe?T;wOwH`$u#hbdYwGJ9}b2XJV=aMkHc5^2qUEo=ADuN0V1Z zSDS4op2EQ_Pu_cL+;2gSQ4tyUMq#e)d{A+a32cXA66;tF5n^ATBBx%p!pWnGE=PS4 zectAC2;PCbLTj>4O|)H!taw4--DOuVwvWTb^rP~e?@60pOzJ;%JgSA4i&>>PtQ`wJ zwxGD3R~e<;HVwqpDt#Q1vT0T`(4(P1_L{;pJ7FQxWdCwqn!_6IG($b9o;7 zUF*4%1uqU$KfGjimgq1}fg9JZwYDSn)%yI7osEB`iI2fL`8hG8Cd-JrB`;~W8>9EC zQ5<{9S_*v#{BUDm`Sg(d`%oo=ltN_#q7s{kVhb!eiVN(TMkuuV2;vXe=*++yJ`;`4 z)58tR&Ho$Lo_a`*3rYj?ZrW$U;&lEE+;SNLdN@Ff)b5dETP`Pe&C9>j?YivFRj+1O z1N8e){6ZI~qE^Bp7x9?_S1xVY<|vG*h^d|;pM_d})?Yg=iMs)Fq&3UNgqvW8&WJvUHzr8qBClGKDB#fFt&zOzEP3e2 z{=~Y!=ua{M{kw_2+(sa}4|GBrJ#LlO-z+F}k@X~<3zI#>&@GBK)e5xgc6#8&v)%4x zv!EVl>oQ!XZ2pgf%+Bdo)Uy&I-UwMBF;Q(B&42h0PGYu~ z_ur+@B;O+@S%p&%0U-_bLHNpB~_ zXQ+;ot(`NJ0slg4?EN!t34J;XBS$Q6WC(KbOas*QC+TbRPMe;) zO@YJ`lk2>qDr2tF(a`$V2wE)ZIVXl*##cW$JP=dTu_7B z7k{|8q1Qq7z4B2aONy<|;_~84fu7}dHf#H}Z3)r)jXOnLh@-*|^F>?dxb$(?U6w2@VygooWQqni z@eZ+E9Q;_jrVxRd9<)6o9_a6~dvO%#;?x+g*N}pt$6Fyjp4ANj{$^{I>@KJS^GXp+ z8t_s%j6!i8}e2N3eb+; z_yUi|kz_dZ`VL=pK{Z6a&2L}DnD*xUKd*VMciD4H2ta8^1q2e04RPD!WvpxL9ALbEf}ZaSsX1qU!Okd&Fd9 zg$Uv|Tg8jMHuQZb4;6m_Jl@l}4F2-RNia>~;>{Qmd;!VU+#Fj%= zxu$-@{QB4p?x2Luq#Emm1CeIRos2`+ZV9%l_U(~*J51DedalVNXjCDjL)7iBf(SuX z24IE((WNmxz&AZc@{C)hkB~|xRqpUx`JayngxKdT|D$Ac{Mnm;mqv`{jap(>nl{_! zc~dy@L@HEO`(`-WBF}sJRLl8nGv12Q|C12BgVF_Vxl)k$vZeV3KRspG=ke*=6pjSR z;nZDmkr+Uv#Vp>dd-NlkJi~x~G(-*K|8S*@4sS`G`Gp3|=0T&6$R)tGi_p|3sr^ZU z0*rEpB#msrfRDzKdQ_ zIr>qlFut?Vc#JZbqgZ|QL0TI0DN%u%O-KAP&s59$2TEfMo&SrX=e{=^%O+B-Lc@KF zkk+NbzHBOGf8W|{kIV;%!8Q8OIB(3|#iZonNeADwZhdsaLu-_|5ae>i)+K= z1k%c*h8hF+D9lQu8JXfh&rm|CK_yax0LjUHb!ki(_|43ud+l~l&CnRi?P z;4VE-JK4RX#>Z{oK87{0)V-23ye|1%IF&guTm4{Ql^choS_$@3ujPqa`r(^l5#RND z%ufDF{q%=xyS?1?gI@=WxN`}T73!wQKDd7qpvKBtr{)}-Ac}tSV1%&e%)XnOfB`u+ z)oLl#I}1Kc1IE}jxyRezAWJd=E znDUQ`eKt)inOWLBGFqGl~3VYTDr&5pIo5 z!(%H4f_q|X+ss{Q;}nvxjxb5pePnpF0MFi{B|uKw8?Kp3+Gb?V&oClI#j%8zNQrk^ zS`{jY+gcr+-VLcvYm(KG7o$3?7yHA5Z*5w((9?pMs!^t6cC>;MyGo6SDLqdD@itaF zkiMEPy*;vf+t!%-70aMMNuBYin7mZWYrIs8bYKIv#CNBAF8twoQ2*qpwigKZY#9-G zgD_21Uq@WA`?9j&xz40rA_2*n%y!i)$F|Tt1%61pr|Dly{Xvjq>Pcuj9^Tod&P>2| zilJAY0No})LuKv*MxIBZRGvY!^%)||hi0&~NJ)$iMw5nbqW?oV+(xE8 zO5rkft_ps0{}i~1vX^(#%G-V2U|@-~qC+fqMmqBEGXqUp$5$O=_R?)` zH@b3T4r=S0@DEMs^OQZ>GX&ffM~4zEevQpZJ(<#Js9>+^mQEq$LU6Mci}oS;ILt_O zc&7A-f@?$mk_i94@OK6jT)D4maT;^fP9#Tf7K^?yV9;cuH=718sWM=RjESxq&q%>< z6Q$1=g&*7LDM!Kg1jv0Q^IPI-b-6d(o2}zZqU*Bf?#}71v%+iZRBsliNP*h-FS!5V zy0i*U<*}z{Tl&N{#(xK6l+`9Xerp`muufbXt*DS38GN~QPXCwTTInq08+>1KoRaz( zXXoolk7)TV{7ucS;sRcts)J>&OX}Ue10bHJYe&UQ7W4Bb2)^a#^D=z=9<{?xyTSN_ zdQyEH=9-)^M`;-8l&|PG_H!@X2L|lm8Ksmi@mF}D!uXx4oyyzpwn;||{u{)e2Q@n-hmn_;|t3kV;(e!Czd()!4vQ%q*q5D)en)3gKV zvaU6Trjd`D)2hQy0nDsxjX8j|F(fnGwFobZ>#tOfs@Xz@5X=K->_*dX`-Lh1tLz^x z@2}&(n^l5Ajh*LV3e?Pdvgf8t&nvw~t;`RWpvh5aEmXDrM6^ZykI_RFn`@)>V&i5n zafmt)YCj^<#!IKyqn}M|XA?UT9b?no=TK=-5H(0peYk?CwgPN4UfbQAGCT}!&Jo5V zl~VT$A0`}m?w`FwMA_{A?ETVcH5Nfc*%d!B?6T4BIu z%T}$LUvsv={mjF1`Ne;~M&;R~Js3#860f9ekq`zrwVnNiA=e`r>Xo;`k?8zvmHhs>YD>D%F>eZp zba*taSP`Wc>l5cCNmPl4=TXSKf!)Ep-yhh>vm{H)f0sx7JdDO6f$r`@vaw0MfkNRo zY{|xLTz8AQrpJ77XzAk=IBA;0WAlQ)L{8vR-%#N8#3;I~zU|Y16(}J+VV8zvtSq&09l8)29c7B|3^g zbOcRRe0$XR7x9QYwJi)|=k@7n;gL%T;@_gT@b*ke*nb|u0 zH-m5T%C}psBt!T9Z~+x?H6@-e+(HZ(*>afe4_chy6KgMQBwjq3xIW2Mc6zqt5gf-p@(x75_5)Cu?<>v!T(h$?%L}HfTl6DDQ*=_)#|>NiR+$p$j_Y@RoS+6 zT?qhIo?-tcFrxsdHl9*4>R+4`#4Kos27YGC7~LN_ZGZ{pViMS1^+F~=_xIEl;nDQt z3Bz{y`bzn;CvBF9l8E0Ka;Q37>VL2+2IDXLlkyOVRouQGS0r=1xe>kyeU7C@wR1yy zGSUG~z;=Z$2>NZc?9D$mIk|V*{E(5xQa@1rK+Jh^1M3%YSmp|<=PcUiIAhvraaP?= z&eVR!eVa>L3{@W(&qxX>#g#SN-iGex>8TS|Fh}#&AMM~VzRUYoLwIQ#$AE!(n02&g zR{n|BLvFE;ZWg<_Z!rDnn>zwQA}a2Nh)O)HEWZ%*K_+StA8v*-q)*PPuA4*$FAs?e z(L)aJ=+$`Xyj9xP16m3gh=XO$M~tU^HBDK&cLs!_rMi6mhRktX%~|n;EHVd1j^(;- z(gYVTpr2UJr)#>~JV!+amrMxjj^dzHAeAm*?ydPe;&M>uX5%&;51!bGimY04PewE)!jH6$XjOl>5UO1TPNr3q(p7wYxCVA*2$T-)Z7?N9uGm6Q z!`$BPB^B70;~#;(51XY`?6J4{2cjV@B6aX=HfUGkFciF0R+ME1NXS{HvWmQI0pSPb z3KM;GZ9d|}v=CMsf1oL{G16Yj1CoiOPfw4gdMlQh_$2h-1IE>9uo$#cp(`O@d?0vs z4~tbQCfGh!&ShV*j-86Y# z+~T6C>v4q>;ykdo4arN1t*(f_;>oNk1Ugbsh(itPkQ#x=zVaD4&#;0F{a6y6s653c z=}!0wg^;V0mXjWfy>U$IsH*FW_4M^+WJ3uDSv&oRZRWIVEe#pHl=O6}V$elLqJ3m= z0GV}UbLSV{u|iT-N)9lb)oA^-HT5werY}gx3&_`l2)>O`xCsBGpzkVIH6}9W254vy zw%WwU55aj(u_F{Y2J)d<;@sht4H)6rZ>3-s)#$Dt!}x6LUYE#FMH;K ztE<4GBd8UN9GE!wiF7Y@lZ)2#{kXgUR)qkUsMS)^07UKj+&b>#%Xvj)>A@GXd6Qnw zuQ%oO#lS5V>Pjf{c5sTwOprosUG4da4i-Ru-tnU(CnM*VFV%(@HW{Ej z`&b|ae2Z@JT!oU)v#1nL&c83y&CYxGH^?gKn4ktc$W7DtzpP{R8*OA)dMiN8e2rtf z)!GC8s0iH^QzRb0trhs##fabvlp6TcU~$I^1RQ=nbneV<(A+>@obeG#j8qVy5OUx0__ws8+{ZLb ze5k_8+Uwrp{C1IR%k-c!KyC{yPL(${et!?w z+u$t`7QCp4$NgCToYL-9>AylfJ-F3TGsRh7UKs5MqI9y#H*9%v_9ma%H@MOlj4u^S zLO^Y(x3xnP9A__~zYW|N$eZAb?uZ=?mDK?m3ShKa1*6-7k1TtK_&4r_zc1{-=$Uic zU;KR{8A1NXK0~h)`SRF=|5Q53tj%oB}M>po^UKGv-5&f%4 z!gLCrUp~HMOiD5EI!8yl|6H)~$uzr85R1n|f*Fo0PW)jiCu_yCfWiSe)FK4ca^LUR z1|dWL*VECZ7ti%U%2YC#RZyB+aEIfnhDYhzy4Ynck1-%{WYl0Khh~*p$g3?+ zORi!9OMBp#zT&61g8p#DC6+dM==;PVJIcbJPwyf;mk z6v#osLU)c`Z4pRyc%89`ZfXQNEbCww#2g`)&rrf@fItxPG!yMilvS`R1zv@XszWDm zT^9l!2%U$C_SwGgw@`y4(z#5#2vnt7#s{De<#~awAA@R#FS&{pH=lh&=M? zx|$W-)!L!iltjKQ-#VmQ8n4N@8)>@FPxk68M~uT3jn~zX4~0w` zk#nVMMu*C-uTFAo4hnI*$c`u=V{LA>Pl>V;o1W7fd+d=G3Omcl*WjWZT`CC=J}!gg zxmqdf`=V29p7(=Id*pNUDw1yaRentQ$?P@+(AVbZ$G+PUsueq60*z|EU^iQajeD#n zf+j8HsiJTh)O&W(5Ryd4F3JVWu^e{jK8^z+KJRStya?)Mfd3nft-|W)#ZvqYcq()? zt$tr!2kD#evymR?${Vk8vc65uCWO^)Au8cbFbTF=c~vRBtBzkZ;2JT9lU6?wtB1^| zbl=__fR>odmOG8+dLUzZorztjmxRu0L(u}qWra!KsETgKlu1$Tk3hJsK*JWdA4EHE zcyV7HOc*3~?gx_-_S{9pvG-WobB6ywL7C8CO2k5{H$$0odZ--c8TA)7O<}f%2QjF` zD*I2oEdyZo*-c$&jBdccW-?O;`qgz#5A0^gf}+5^7&<=YsY?ARDH@=)9BAGQ@F1DJmV_VK+3s0B)w8Jhg`Q zu^_uQye~Kt>`C%+{6xkN!S@`)BPTf{S5o!q31veF;<;@a`jm)v98hCYHC zI^<{X|LgziHckcR6@KdJv;kBO@M>~M(}R18xkft;RAk1ASm3yZwOiWJLHT~ib(Z7XFf@x((d+lQ?0G)rH<R9z0`6lu$T* zG(E1jV}wGL(CbNtk=i9p=juF3cK&RLRLk>|9C4rDksTNwUlrkx8;843=D|0He3%G# z&-uGz(|7dkk#v*q>qqG>GqW>Ki2JS9aHIUh&jr@}?OO#1&0&QbWuq&hS~+@SzOGj= zVSSTOsD-(Jcif;)n4Mge9k9bVENw~}Wf7xwX#;d#iH8>2kil~ivVzf-sM4vn#tMb) z%C&1fMCIitxZ3gg$Y~UGcu(<=_ZK%{?+PU_XT@YY(EYAy{zzcw#t8-Di+aZIQx)aic}%?6rOVs zwMaRmCioE$-OKH>3}l&oaLCJ=p>aSM(#?MYg@?X+`b+7<_xh|sN81c+Ay|M$POx3c7{fdZEP`X z$M^U7{Q8BauLH65LD1Dg&+tmRjD*qN&PlwOaTTWyVo|x?UK=1$N+StD-#8FfDz^Sr z!L_D0W8$O#&UVyuY=$d_j>qcS$E!+2sd^bcswoBGLe8l`(8vF8BrVr$|M7WS=qM)& z6)lEA1{^>()i+VhGzgYmEW?8Ck^&w8xTH+7nsVD=WCP z;oS!!1xOONY)xv9bFFrE0j58MO!5!%`QdAn7@|OldKU)0!E7>$+pFC0`RdbCANHm9 z$xyBUb5qD-unS)>81#|}Iac+5p9Ci5p8E7z{o-56;KM6EqCs8Mi>^GPaPx}mVQln) z0AN%OpU8a>(fa{N-wmqz143MaJ_zVk&AU3$9c2Ybz!nIYhJnU>%}$_=U180%X)>eX zWth}l1`vg9rJoLIYMKgA#1(WA@z#j@Gcc+wxsWX$iMTmM^i?7Xhl|5LT8!N!2Xkv7y<#s={e zd@yU*MfRCpW%BID09zGf6Ut}+RH_JW4dGzjXFI9YX&*tL(jB+g)5KyszJ%-wv_(DS zM7+D1#jfcU4EYjZr7nqwPXfb(ilyzJ8>ZI!y=vJkHQU@?$|cv++ml^eFiBXoy!z>l zeY8_8P*Atj#0tv@l4Ha*w+c`5Kh85-Jj&Jkk`Qr+IC`*e!VjTUad)4kWQh~_@si4_ zO*Hhpkq2O>*>b)Y=+AtJy${+nvCE;6#3dCzvl26Uf&pefJ95K z`EON`)S5<@l#p+H>Y})|kj&_+*{2P<_fX8#RsUX*-fc1*oRpW1li+|aWe|I3i7QD( z*df=`$>QsO2x>?sZ5S4y=R7MBB4nXv&mw_b_r=+`Pn$yj1X%l(pLO(MWP~DMei*dF zuoo(p-MwfVI<(`M2W>Dq3`4w0rArNq$cYi&gWMe_w$S7uW zuKUe@C#70yTcy=d%;T=##PVAI%lXzD^(@TAe)yTL+9OIm%%&IrciuClMn{Fpxt~=d zDW=l{Bk66zJJ0i}!7SW=s|I|Bktu!QrciB4Z`h zj_z8vb{14jamsBXK9A5kY;)&>+8x1-PHis$Iny|oSV>CnJD7D9{u_`8jf={w&UM4e z9l74eSJp$m{y^BVJkZ)+o{@K@5TV|eN0oNH*44%loY?!yI;wwianlCaa!CPEB_1af z`Mis3&abIX7_+y9c~ zB+vd6SQjVz4SBfn{jR0g!^<---gyzNl;efpRX$fd!tlBu)pIqX3~K$fn=r4Zir$bC ze@9=}I*~uFZ9;kULqA)|eoo|z3Of;H{Hx@g{_mv;e3WRIspZ^`dvN?FZJrT;9Be-o zalZEP7%|fOi2;)c0J2hre>Gz1)9F0}WA)F)Daqa-GXJEyWlhQE z=nc1FBc!Xs46;X~=QgFF zCfQ$KDE~F+sNK>zNPQk~58D#RvMqj6a=AWa{p*sZlECB@!eZdX70+=+hL2BsYR?E4 z1t$rafdbq^=jwZtM#CfQH2PR{l9oVHbX7Gt{nmk440qo;O^ z-z=P9jYxjgDi(^7>-9zjhpFhIIc`U+;_y={AU)kO!sG4=I}~=3WiJoy`)6hPndY`) z`yy0#&rxtBO=ctBiXJ|&|0`t^FXoH4kIMSW#rP+r>vfICSKnit`P3gL*_}#K*r-2y zn+f-ilZ7tMY}n?5_i{TZjqox4RO6|>XViT%kTpnn^cO*>W0Xr9 zsIRAn)^C{s-k6^6vK^xhYQ7<(U4JwOX#(8g$NPi?`&8iFZ~a)kY1Z}I%Htaf)9UE0 zc_w$V7`b5&^tIaUI^*w-e)7Ns0|RkLGfX#@xwSQsZ)kcj*1cg#likKL(r`$d*sa_d z<~^jmP81?EYQ_!?@$RC%ds{%o>%J%tSI%7sself;xQXna0AF=DNp0ppjDz$ms$}RH zcHpPjpOr8F7?sZWCqWNfK|)<}laxl%+%BplTWEA`Aq*38ll8WU+VtYo$ukqaN$=AW zICrR*ECG@3#N_;Au~1G;L7uc5WLP_T)aVyW?*>}zgCFPnx$Z0>XT@^cuhw&`aDv>; zDlT2>J{M;7;kJhdqO%PPgIsJ&9{>D70%z5$=Huesmj5*#As&)^aC*i+h>0cxS*KFi zJL4Mudp2fotb*b%;P5|?r|yJ$>D?5Lu0+W&tbuDs@k<7$KULgUoKuzv6ZxSIcl}!B zp0^Yf{zS-pLvM=<6WA%(uH2hK5_A)dnL#z12zhRPi+q1~l$p#2$@}3RY2nzAhn)fz zrteGlXYXa3n;Q)qfvmx{H&-GMq%b&J#mAK(dj8RCr5gzY%pGnq*c9=tb%s}vH<9mY z)g(=oIO$K#TCnoq{Lc^;liZwjh5yU#&QewQl$HY{=%NiDIePmGF}E z`T6=V@M>GkmTS)7@#6807hGhMsd!wR>rs4euY)d<=!L;bUTOTdDli@*akTYBimQ7< z{`SbUIz*XFXjSinytpf^kOTR}Sh3;5uLXAc8K3R=CX}FnaS;%2EO~5-6b1DzsCZL& z$>;&^3IT+x68TUC=ZN15(!!Aed7VHGhBwX<|DcvewaF5x_g86VHn~O{O!<-b7XVe` zyYI59z1pxlh`dJ;Bn30GQYyS*d@s~dYC{H+csP+E!m##>XV^X>^@AOZgFU;rjeLv5 zsozWXd0YKps!2Eo3xuP@uf7)E2bGxDP zCVtw*QU+RRmPI~M@h?|rU(E?>?eO@@;oH+L(KF2i%K{!7M1 zisabEla}u%IF=5k_*AB%~b+z(wVA_y)q>-x_TZjesOc9Mr4uZRo)m zUcpC2?2F$rl$|E>V3Pqd+3pRqX9%tGbgDV=hliXL`0$g^>F^7-lOG#*kN4|G$zoYB zjnPn&=S5We=KiYoDxScY9%3;iM8VQr*88-)ux-v^6z6ViRJ9*oBGR8Ksvv!P{cI;A z=bkF>)AzuAZln#Ooonw&&1rZkIBrX`;)kDo-&4#}nNZQW{^t?>bQo99*23nkZY%up zDYVtT?1I~LTYIL`d2Tc{XW1$&%LqBdvYS=5ohmLm0x>^FD*+1($rRYwt952#>v;%o zEJ4I#vQr<{DO)3HKm-oZjpRVmZVLXXv4BJ6*n7;uZ&G(Ny&T&|DO2iQLGr`_Z4I5j@pS^}OQ=s8 zDl=rOs&BX0PzW{Yn<~&J1)_kkpYhUn8q#(yzS>4VHyt6+S zsZCTrXw)ZI7vjm9vI6vSd}8qWS;qq-(`fNHi&Dv+aR3l~=L`)=JP4bNSd|zWaID$P zP6#9$m~wtiN-Mk@xH=crCTXM5#NQLnCFG7SRuQJ8yLFKwx+xmIGHZA@WVhjj%Y+Av%uYKyonrx*Qrjjwr5RI-jy5*m zz%B5B|1tuC#u}E(GVbPZDSiO@c}ngT^-Ju!$NQ4kq(@?b95=9>$2xHN zMn_M5cKzE;?}%9=IG~+L4T1M|g6ewJgZ(mE z$i*)Ej|3SZ{xbYjO9hLuxr5olGh1?I;3ku{NFtYk7e(-1HvKEg+Y2)B(u9ZOZ^s)jLem^wjWE!EH#yF0a*4tF`pQ2c*q z!a18~PWSP8cVR(y_}uTC?n&`>w{tG|k+(HS6Gbm`d*fd3$A3t)bc5e@!A7cv|GK+` z7i#qC2bkl{m3Ud4v}>Qok&)5OHN?gZ!v#OC<4K!I5px4A=Qp>d=a4swajC zmhYYFPQO+oRCLSHi$7bteO|zlt+hIRl3CoLsIIB1lU_#WZfDwmzvxGOBxUoe_?DyA zt_C9s)=cR-E@#n00CCD+ZQe{HBPB(#r{YFnzcTjWryPkPl!-=>qIW3X^}Zmm)Fbz~ z+R8+hy0m=i0e%~UeB%P^zg0)!bAu1R0vo`gom~b(>icieaIRu7JRE)JPvJMdc|D!H zuUM;d`!k0%=qs1W>lYKJ6m!`F@L&0h4Ow&uhajWCr|Z2xt9ye;7m;InsuA{F-;CET zp^=k0k;_q1=GBEtHahN6`o`Xjf7A(>D9p3njbV{W@}UC1mY`tD2vZHN8ub$wBBISG%^Qrg1HsVV+((}Hl99Ak9*=JU?Hd*`YcZ7xc zRDQ#6FR?hxt}qJw$lu}hDDgnU!svUO zC%ZRCZSMX`nWhUf-kWE}c6m>sEfTIZ0|GbOcL#Q+D$x0KjhgZgJrbySg@FnCD4-g^ zHeIty|)p9}%Y!*w8vI zjra1G)gnl_^YHgA*m2C*^8WaXO-+MKe%mM3CQlssXl@yAclXY#bpyWH&paQG+Fw=o zs4Xcgse3W98>1WBTki@5DW3&%Mle97Vg>x(i!)O|a*IfvK#h$M|hhcAsP;g>vi=Bhfo z2mM)4@!N)aoTiE)kFDbBn+4gWthmN&kfymN9D%mAAPQ1pyA~BKjzLe z7P&Ufu$?$y==g$Nyx#w0*~l+)h8>T?@!_27pH_R7U{?aSAYkm zWoAiM9`g7?7sc-zAaHG~DZVN-ZzZ-DaxoA1WDY*lXDIgA)9-MyX3DR3z6_G=0O1~{v8ibS#6qibH+eCBy zw?4kU$}TTgV8Z(g@!u-HlLW!_hCYO$6ItMqUg`F$+r?a@kzR7P;S;S*gF#M1!p4@Z z<}i(%L95K#(XGv)jY1MP&#zUdKa5@ngV$azsI4QY5ffQ)i)vBWH@nr&e-FYTUtBh@nm!ytL8F;&C-Vr`RJpu4ZcR?i#PBb*0FetB$`&x`PG|j^5c75^M<; zrPL?`G}|%mZjL~#9glEkD;NFyqAg(3&Z{P;!PF)t?}wyXG_tPXVnr2;W38~ay5aE$ z{;+sY20uOwUWwmK<&~nux<({~too$`pBFGuJ-hl#nyEnUQ-b?d=|pjEV@n2gjoFTi zH!{B9gGlC|SMP#Ibug*fFNEI!<|6$X#8yh0;;LBTxrRODJc@^cKI8Z-=Plg!J`HF$ z&MREiO{)9>#qdF*fMW+i;6zgAK=SQzYR zk!MZ;gEsi`D@M`tgTN1dhlOctS~%{DNdzLbR3rP7cK#vWR}V52Rv92Ha>zutUCxAo zMGP{dyTD;~($*L}5hP#7Z59M&%Ms&pYNxBOslbCP!w}Bv-yRji*s@@w7j4U*>hyyr zbHESeI8{k#_zQLh)%sUWoI&=w!p7{jLI>`^^bMY0Z2TDvPC*%3yEJrJw!_lA*nCe6yq^CH3U` z#rQA#lT7;ZkiE|cQY!-im!=%vnX8>5t)WCEv?6dT)t9!nRqNw$C0IrCC92*w5&&9J z6;_8m07esSBbC{>&}k7BaGN9lP5O6Sp#b#yN{F%b#)GP<=y0NV=4yyW; zGp2JvrV`6-f8?~+Ip>zpL%n3aOC|mDzg4EJ3{Mm&7CZIkr1_o$)Zf~xu2=^wdnDZg z<_K}Gq5Cy4+Agxz^?={x)!HsjFGA5QXxFIK0z3-6p@+{N_CPF$ATujhLMm_lMH!sz z2p7sdrvmazTfUALcrr441T6A%q}Y2K-n<@$msRWd_R@_K_*{9-^OCcXm91&_5W0bV zX(FNGO~Iizb@K=7#8^@0k{R&vVE`4NEO(E37I=AkM_p>UW^j20W+Kvl{}Hd^w!Btl z?H`IS&|U_HQlVkV+YN!Uoe;D6l+eb(<*!=MY%J)>?Vu^`AP)}pNQL7Ywh!au`R%p|WUTHBkN2M- zUgwllUe(6<=Q3+&Eg#5S1Ab9MUc6-7Q zad`?r+`4mBv;M<`;&R0vcAx~XBn3g2G0meN3d%@n^COL7$W1=n<2qv=Ei(5^pSBzR z9jF(~()z&GocrkBKz!@ORZ@??&_DkYbz=W|w|CmoO65+)vdNHru$Cq(ly$)fjDJH5 zdRWf;R3;8hwg?~O($>MnRL+YYq= zfH6_Zc$Ut$D}mMEB1=yXm#3#1uRcWmk^NFzUt@Hx`6odq_kDjz(>Q1h`!S!|Y^~fm z_#tlArn6K1a_^Gc9_~KfYmR6CId**Dwl{CviZ@_xxDI5#lCnB%;n=;H$4b!D`RTEV z5uc|!?nI6qK1AATGhz3F3B`1s_;1y1eky1UCY+o!l3-iQ30}5tVzFnhy*U9*+oJi8 z?qK%7HO`$*%#8&^I$)wNu_t;o02ibg6V&1ICUhi7)S%;@HBKL;_uEr|c#`n<;{R)0z}$(9F-_zRDWd@yD!Xzv*vieJ4np_#anX}^r`ULK@Ommaw&O5dPdU&#_iw~#!8 zY%@Q1qKjs2#mP1fWuKeI*rZ$;`g%w9)2wcFI=oXi_5kjGt4B2RWTwA_OT8#UHMJXHVFxyo% zhAC*{0E$Q%kmvVsfq->yZzl!$B&?O>+n;40=wt#Ol*q!%@x_VZJ5oE4r*bCFTb|Hp zwAMw#e+dd*nyS>MXg^*huVQGP?}D43=i4ZSUnsK5&+gXwVVmd;6o{Nyzc88l>v>-D zDRGK}Q^a1w=_okdQ}C-Sm=3$cj}kzZ=gxB2RB|tkYIZjF%0Ymp#-hDOCB{zFOime+ z#HL_Fu^->UjO#lzTiV~x&DfhCfF%LIJ&hWokda!0vR;sWCDi04gAJ)>bn;5WjQnf< z`<%~&O`&)_1dw7y5%C_EOkYcS^70s~Pa+E9lG-e5GxpbM!Z2j@%z))^M*iCE=J+VG zdhK9I`L=I*4V$_s&`q`Ud>B<24+@PcY7qGmMg`$@95)uXPX7j>1t`%v$@~6rZp~t5 zzp=Lf%1_LbE!Qlr-o4y27;Z@RNrv%@jIGzti+A&4?VxHCGPPuro zb5d)bGPd^HBqDn?X8APJ_t8(M=3U{yuCJNUb_%upY903okUy3D0`L+XoxCEu;1*_QNyYKl}q2nR7B6!y`O# ztrt{-?S~D#jTCa5w@_4}Tl+QzGiuloMRXF0hR7l0eNO3wf^T_Z?U_?T7?aE zyb^I-Va~vY1_nF5UJ8iP2F_kL>1xdl;jrCBY$@Q~(P%*Y-P(~3{2UW=z@Qy=J1%0W zqUgymO?Iqhh;S6CVgnJ)tpSytmze5;0}}XiOSOQ+nOWAulLwD;N{N}g79#tOTA zT7#7>_iN~S33Sy&yu$69Po9WyH@gVZK}@jTOv;_Pnk+|hY}X;xpmFZQhXW%I^>Z$f z3yM%8zgG6cK|aATrm>l@??!m$MHUmdiN(!P>yI9KnUr@AgGGI!rg(?{3k?uk5J%Wb zFW`Z2^R^E2iGk!1O{bvp*wD9uTYITMt;kdV{quP0$)|!NoTE)eT%Ty_f??f=|M2ab zI@`|x>uqJz(oOu!v@1A|EpgCROxS}s25mA!*QdWO{?L`87$7os%-4@TDWW(Kp}95?20`=D~R zKu&r9D!+m<9MQuGlJ|_EFHS}!be>c{Sbo;LA3Yh)`4-eywFDTU9$e&*-A(!AzG?eB zJ#Qr+6AB29!s4`gG9S&FkH)3hR7TC%lhpSsY9+=uG8p?qQEZa+2_ z#T##T-QRwxmgkQ;7LZ5X(N+2?dY3IEbNrc}Ic0a$ZKA9v^iuOLP8R?Ul;KeR-^w%6 zjK2kWLjGG7-6n+mxK2w43`izq@eLh&)+W3A3M!b772n#V5l+KvR3Y--5=ch9{zE?( z^)Fq;0S+Uv+5RZL)!y1h#5VA-uTcU!CQy84#|QJ4501uYsDLd)nVlLw61YA#puN`1 zQw*D473Fb*W6ZbXvR#-mA9i;4MFc3dsY8hx6ccbC?S=ZcA};8Ml2` zkb->$!4F=cnoNRbZ=|;~oK6 zM4uF+v2-dm2W-9VC7j({&rF^JtUML4dnsWsCy=J(cX0h5AQV%?-1hPx{UPn3jsHAA9eieH{&PQ-1|I$+Nm?0nKKN5=)GM z0IqUbS2J>moL1G7-BSa}-l1E7jg$_!LJH5eczI#%%^SfYO2KkY`wYozGgJ@t)htzl6pK4ra-sqp?X&vFcV(3*x}lzW@^p4Mupt#QBZUFd+z{XF$6 zK!Y2T>Tq+%gO>;dr9pH`o%gd4F)v+Xy>%e!Z~+i(qCuh$?%#~`*IKZuPripZc!JoT zguqU5Y)2iJ?|%k|^%633ziwKp`Ywn3h@EO!@Vpi?naKhjt{4rt-ECv`&+lkT$=>-i z2Dj61G|Dvb#GL=52E4W6iVQ`s&0!@Iim|#8E5BAi;5GGT!k%|TQ|h{unpVXe{-0?co(+)<$Q4<1HO_wKFD?81d(Vp3;`wXj~*l52YaK@n?OyLa zHXmtsaK*ZO*2g;x(+nGrGvyD;hYDTZ?>BNL-Sikasy7|lE}k1DL~p+Tf4hpT+S5eM z1l_FW+$i1B3%a*}aBLc?h?&2WRDeprH(>tm2JkslC(7MeV;H;d@4OBwPLHZR{HX`Y z!KAHFo?jy8ok8HD|NjC0{hF`S5DR>#c2akD$2CAT!?HnJS=9rF5D`l6Ac|9Hz;__&j53*aof_vZC zQ_JENovwl3s%bReU#Y)!!>zLIMiT0>o(fO-3)5xo(+%2m3bioZ?U~n=4T!F6+O zZTMI~WMhTk@3)R1)7am?tmIgQo|-6zMeA-8$Me|BSjZ#9JR6dHA;=@rNmp_WEsE{qes(Wea00EFE8ey; zv#7zp`8gW)cZSJkxEvH_vTd1J zu`342({62ibf(dFLsxXP)XBpRD%!YyYO-*VzhX$5zX+UEk}$+1Uj4Ysrddz5_Tt5% zy{UHCuy)(1XM^i5jjrAkRn#VbzTG*|LJ=4O^h4}+D=il8WhMZ~_0i?HYh%$yMi8@o zU8{`RwGTRc+FblD&NC<+a?-*4@l`?c_Rz&(Id1vY%Iig!iQV%9 z=W@-+ayzURxp;x$m**a+bL!;-W^6&`>G%T|5!qu8yIAF8Bb*qIp5TNwlQ#(zA)^%O z*y(8YB(QKsXS)ftTarv5wI1*;DnaI)ZiLxeV>$zDg_SJ>QDYzbTNeCUIy;K5lOVZM z**A`nvnV!0V2bwO>zRA-N_AV(6ww%UB#29fIqk!A2zCPX*5ojn04h+8Misw2*rAK0ZCh}n(%K)>R}CrWpqV24tb--pG~@IYzJ3Ko1|R?B2#=_fX$c zZnDpK?X?MYI1*!Ct&zeHl5g1Dl)oZTzobDaRQkFbj=~h8bnm_bs%bi*@pdnBmc*z?5KTL9lbLh z?2jlq(K7C9xOSbseSC#jwAgc0U!Iqxl3qX^2{SSZ6b+dWPwsx2B z=98N2w26W941>)6Ca$d|P=l7Mbtr%#p-FmuHOk`BM{63@#O5RxsR4*v#htE9gON!A ziyfRzMU{ww>u4UXuWFvPv3+db078k>JHZAi!HAXJi|FQ0qkX*M+M^H*l7vd#CtEj3p%USmZ=4d01cpasLH&xHY4knjdcb{>w97UnoM z7QEO_#ug0?=r>)pPUt-P#fbDtH?&?Qy#|GN`0;@dX4R}srtLGZPL$GK=z1+zFbUYJ z6wQ!JhuVZU&QT(X%k1{j|5oMWdKpxqTg5Xu?4gVT8wM$xr$sd?mXwppbNzY=LvEw; zDn9Y8HQRjTgFc%F7ToUUh8L(c-Z+)L=+g~cK`-6&y>vGhIXo%wz}rE+vSj(MW;sH6 z)gRm9ho3x?$FQho3W(N=FQo}=PZT%Q`9tI+Y?T)WjSvaTap4I@Fo3#oWXd>AJq!d( zkpB2@)yL27u%Yza!?HXSCJrY^g4)LthjPID=kCT`v0Pb*)%|uKEeNZ&hCo&f>)rct zj*U|m-VvJh3!BL#i`&?pZI7SlSZNv{RebN*+{mV#Fg9^$^IzMKg5qILQ}@dfXWuxA zdKY1Udmj+V!fJrKLXClhyr`H5$`dd+7>GN@DVS$=V>P?vo*`90_4gK$7m{WDf>Xz1 zG-u)^NdaUv6B=xENjIn2^5F_wiis=aQ#`nmSAYiktB#!?8A%9+p2Q#-yTvzP8)}hi z%YO6?pU}=rtvInYjn7pZhN?8qwd29-nT6Uk;Q;q_DeIdWBt}~fv@_0$*zWa1+gs%o zx(yjXuCjW`o)K{PZ<0mgaFuh<%yF`4XzrkKEa=1BRs2n#6Wmc#G8)mTgqXj-3!HF~ zgQt49S!!A?N?f`&&*PugslS(#Y3R2oH7iJ$EhZa&+30ErZz_iEjHGPP6cmT8{`6qd;3tmAJp&``B|hq;7mK9TFW z!&93A?U{9xI!YS{^;;EeG_<0Y!A?tHQ0E7=MM+TB{k^4#0%8`>BFG#fwCMTq!Lv!8 z{n-x{_%rRBZuXDpiRyWkW@4Sos$rmKSxu{LXaGc4D=4=>KVYMfo=NVx;*?8P)lXD= zoIfa))XPG&9o%8uw%~B#og*#p@Pv@XSr2%IG=XZqT#L|HS?~OHX>BVQPqAMDY@(fW z(IlXe4X_s6zpwld`E`7_ZV!!|D~73!hr&X!+nP6}{b&>_ZQMt9=*IME z$|!!kr2{1|MoV1svB!&2+wGHJr%o|Gvui4CJ%ib~La)NN_7HRW zLs>PrPFN{`0xpeX^4)G`@6npgU*P$dZcAil%t2Yo(8!OpDPQR83=ArptZ1en0ickl zVtB)g?trsj4V&&E|5P?dkd3LLuSQSHZs^`|s{>-p9WTF;@0vX6@qxqxfJ@m|qwIVN zvG=9B?QPw3t_cD<$tzV`d_n<(dmb*z0$#zv;C+q2th`c_gX3uN!jN%SvKC!>-HP*c zCuuFol$9)XRs^M8u!F=k*J!^?oZxfI5x8K@_WyfnPjDpEr=YcWa4v;YUr!VYJnzrR z8b)~?c<(Qw<`-UYLQqBlMUl|4nmrfb&h>suag%z27FWMJwt{yFi+`c~2*7!iwXdRj zC;f{-dq&B6Dcc^q@SaNPS55T*gpV~{C0bgi4gHu!MlGGt9*kkX6Mk1PYrZxzx^W4y zz75|uJy`XiMj8W1h~|lsL-;=OG!)X$t$dg@(it=I*r(XCifOxtR>Nh>Vhk5hu=+9We(rlU4`^1V$l?%t-fFr!#HHL^}v`fB~$$Sc1s z6SiP3B0_>`^vSGTJ?Ge*3Ti62woBrbW~66EBR6&|RZV(k-+ca!pdO79d)EGnohrC> z^!_}ae5V@fKfTy}r78wJtDPBZ0xu=HYe}oc?|z_4*%#3Le(8OLE0$1Cd2Av+v*-_| zw**=9j8;QMscNGN^B&;1=T409#>!Gc?qT7=*KvP{LcV&@h>C;B9@)n-ls-;B3ejI4 z92&%4fXGSX6lnq(x8iit;3cEUIiutljE$C^w$HQE)g-6YH>DxH^3E%1p5lF4z3CGr zm~vi7QUcp65DJhVu8s7*7Q3+itTe5{n^)6H3U*J)?Ne6opWQRg)h#t0Vz&@U%*P{j zMBD?S*yz0BLGTF1Eb@C~Wa!0)twbbEeGiZdv@6_})8bR~=7XA{_IY{vE*(Hh{Xksd zMRR%1L7}_foQn6NKh#GMbJs&Mw(FSAmWxsPQ{8wzSyn zx**Zjg`pWbWet^6#V@1hz7;0K6po|k!+?3O` zE^>cv0l>@+tmf1~W7Kw|IxbxY)>~c5a%_zUw*+mzF@7^#H#cl8i)t#GCY(JqT42)% z%(?{fYf~m}BI_Lec(1~%2|Ryc+y8rNBFk7p^xC|RQ4a-GhyI;eiT`WsPmk{m0 zpSgds`qWd1SMo^6F+esPZJ&2-#CjLX-#uS~H-aI!&wrZ7KX^0g*!pO|Y+u!Y)Kp+H zIwL$sifjw|vU5D}uU6YU(zKBbb&t&|*-sISL-L{|D(<)MH@rTXlGZvzhc}ul+2qx8 z9(q}V+tP3kHW!k*WM8xwwZ(G?uYY9&S0KJ1_e3!VU#g=w^Ioen&jI~R5~^+b^>lft zS1oG0!=G@E_y4Wxh$!r*3{K~aI38GU`@5#Nn%eyD_Ya9bdTfq4%br zwQ+BNmu=jT$JM!n!EOUVkXj3uJ5#*0Gu?}12{QnwH7UrL@2aE5&p99T-Z!=b93M|{ zV5aR-Mb6KV8*59rOtUWRWL#Z(eMDy)Y$9+xM)s|6GRCLc={N|XJ@)etxG3OdhhOb~)Q z(oayHMHvPDbE0<4WE$G~loHJHs{wKlDl11V5w9Y@wM_3yw&J$z*g&TEvC$>{6{Hrn zmKpuORs54yJG|x3%I<(Y#?da=2=Pc|=E=XKb#n+*9jK^SuDmXP+ug2G*g4gp#n1TS36 zUlqz2k=c01KHS}3u%1S>FpcfC8;a5oFbXumw9ZK?dC(<9xkpgG{c&uV(Q%ITI^PF7 z1%+YvnafbjGvbsVKDQUXvD+Va71L1r8s$JWg89u-US`E@Opi8<4Q+CikVK;)YVFC9 z!Uo|TbnqmE)lGeJATG5j?A~Fv&YE!A3<(ajBHg;r$22*W_id2hWs{&^J8}n0Ld~YO zXO`Z5BJ{K^!2V=M-7u+V6Q&@*{_|l?X zM7jMNEH5z_xYFmQT)HBM9C`ob&zM)npYHm7sT<({Od8JO(#(}suO5X@Xu66Iglnri zz1lNxl1^rNUXY_KgNRkX;|uYK&D|59-kc`;9!y~4hSJf`kH%&n8T+Y^V$`I%g~4`q63ox1zCwpfukD#{o5X`M8BY>WuVuDxjeW)oUD!|XkAqVeR#5bc4 zuDa_k4GYVo(LCy4u}~f!5Lt>cAJ=<#f>NeO>hkyKsiX=2vXLsD%jwObG3UEv2M)Gh zIq~In7MiO-)zj<=@t#lA``N)n{Pu$sMgrfvhj`S@(RrUyaqV}tu5yP;Q1`k@Ie1VQ zj1?U{oLjs!m*1Xnza~qhq*`;|Ri3|--yqzm7G9%)8%fIbzeiI7wjCumeJee;?ep0K z-_#;LPJE-Uh#yTsh<>Y%e!U&@8&<(omtR5@wlZtB8LbW91!Z4bkK`n=T^YT|ajB7s zy%_V;a_zBkEHEmb07^oF>N{|um-ZN0GtV87T3f&%gjJDEMh2cnN=VQfkhLryFBQ-M zrl9Z#tOIBW3~lV0Xo?N{0OQI?ZU6!X;M1RcfjuhgnH|5LF#lvsEjI)iTiL9H0^dHs$Ylk9;%(~qc|I$hv(A(&K&yWb z2o>$9rw^m6IHvrG%BI-Re!kUT{{r5mHa~K8@hz`{^MD2Wp*!xesTdbJsbXc0qpl`V z2g==3^%_ZveVJ^T9%c*B9r1oi6pUj)1oK^gO)3cn`I-wHW5cs>mGmGO~TyIWS*afyG&Gh zT}UunbZ2M?14$_L>8pO9C8dV7C|9Fgqeny`@Xr3DOv1VZ2H2TJo8n3L0CoCuHRQ2F z*A9`%wTGWGkhQH)?vz_W9<*Pq?kUg@DtMfbp_&aiB98|H4@>C7-rEee=ie0J;lU{m zA1t1zAcDUq@P*gMvY%u4mKyq($zBu~2at$`g4tUpmlQ3Qd}A88Zlvn2YbP}Y!907; zxWrT}HnC1ZANARRc*mh9vt=GHsO0ZTs@0#!*~|C>9l+Mm%`Uv-t5>hKCB9%7@Lp2_ zCX_WrnW*FZHcvsoa@DRP%?wFzvq;fXCi!5DK_OYSP}>4PD)l6_?-}3l^Yunw^x|8x zm*P{}>c>;1Xc$&PSp*`w5!&rqtSi z8tIMKrkDAZzXGtLCb;*S;U3{u02+iv!6m?wofRgDrmx$XdDgeaV<*fz3YlIL#!r8Ny>{~a;NZ>wFswt7omj5ru ze}>%9i=I=EfN_W#e)~`8d$LaDxVLs(*3@byAoTB|(;-?zQiV(rZt8fhSy0?u!9^Ee)$GZNHhotfRMi&Yam| zp`E*>hSstp3ha4@q;Q}4Q=Z z@;|uxUJ(fG<5Bc$_qLMk7tEGJHJ`3YZ{yH_Ks;`>jukm^ez?lr@jWmhmMsk5^z!mi z)wG4vz8+P}=#cGqw>$o~Dq%RbOoNOQ5&UAem8_*8mP5;jZkHwEWzzwTk-Ai6uZ6V&_%Be3?%UQ#XiPkw78YAv@bu*col{j z93l6@qqBPJphgmLx!2WWb-MQ}YVyMYe2(brf_|^Ot6IO9o2HuL0wmtcg9mG>)#8Q0 zSm<^8@0QE3S|CHIuqtn>mqt%zs1Vp7$idQeKobO-p=gJdhwKi`paPI!*E3(yQh{GB zaQ8mZr*2b#+Lv!BNCz^FNjGBS-E)A`Sk)hj$M8eM7Grzs1rghsEpr6O$mb30U~`hs zYY6|2h5~=$UW_U*01F`s!d0L838Pkv>r`OZy0=obN^1Ah9{k(EQ-TH*r$GBhqLMkr$|M}y;5{_DU!?Pepb1}*j8iKX%4QbYDz!~pnYGLLz5V{_j~ zSs|H3VO4h?Arn+_Tm2F(WlMvr*elpiYNM{gTuPtPkp>v^zlJZ-B9_~!IjPF0^|W7) z@tf?-f<>7t7XQ<%$vvvS@Mj-&3N)E`{?L0(gDQ zPN^%&YS;YHO5&xr-TL+45fIg!f#J%DrbAoa8rdL~W%ZNLsTlE(rx+b90hiZWXtmDPqAC_~1Sa@!uM=rz|7y=dXmQBMKN z{r-gm-!8!aT|v#(QFGeGf-~YT-Y4fZ12KnoW%IzqB4~G9Oj+>Lw+#kVDZ|dS=^7p* z;Q5NGCad4x`W!!wTQOQ&hz{&A0OW!n`U{8Xa0`KKF&A=nLoV>IS$s<|D~;kr4$V`x znS~>v3yP=(so3)Jj@Qs9K&R}m{^df&ZeK{jpPzCtz8jHvNC-Y%xN%)0-JhwNW5y?{c`71aT?ciI? znZAsPK@&7k&J%p@wWy~DfIP=Tk&7mYsCQo%?w4VbF}fi!xl8<(Ew5;q z*G_FetJiW5Lt`yotIG|OD$Lu6%I5L&Jm@|D5`Ve2_nok!_C^2lP-`2mB^b`hmHFCb zrUv~@sZ{?Pe9*#(*NW8q>1_JdfAIkS72ITKz)32$D;YPT#>SPcrXF&H-LZ#KC0m;^ zn2@z{S0)eyj7~dcHzn3Y=5ZV7mzi{(_w&quRDNG}aatjY0B_NpLz`9En&DY-*Oo6y z><8gZv@AvkY4hyYpnYJK&Stuvy@=Q(^2}(%T>F(iCFN|dqMKU)0bDbGoD4Kr(cdn$ zZ$oCx(>zDRauBudbR}6@Z=26w`$JJVxsYWII97iCR6C0veknMvG5uP>!wcT}KOGBS z6C8$TQDEtUZsS76!2?38d9`g@`-~n&&#TNwjhY@TLsHgF<02+mnYb3Vx)>7Qo~gK; zIUQ7w@@@P3bVZ%w6X-{i%zqF2{@~yKWp~@rXNm_bmx8)% z7lnP=B-v9sbe(#G@!w0^_H(?Ks$Rqaa;P1rMO?5Rhhtk@yMAr!lh}7lEsqeh? z8=ylhx`J(<_eI+H_UFAHVGCDMe!q&_F|j}TkCuCPc;A?r6#=6fy)SuJ8++D01ytW)Y;P<-x0qPFK5*XcvJ7KG3({CQV%diP}^@fqqCFV1Kjpjd3N=CZ0WW?Z` zq~pH?L@}t{^zVheuPvpi*5y;H<>AV$7HK|$jIn2=+t)uzsiCu0#4 zN9fnnhT2Jt-G~Ox)_PV8$>gD1hlyk%YGE|=%Um^gF$sEW zqBfYSs^!~(sHHw7qsJ@wA2TfAE>wK;v(;0AWV_*8Zm);|_ys?tc1uPIztabZQ?0;d z40l$96*KHb6wPo=UaE_|HYl7%+$c-qmKLK&F4C6C@oBmKctc0O_fP42xwjY?@u=>V zN&LWA%_Br#M6aBrb00j!o99=Ag|dq2{var<23>q74E*0^CHtv!j##9qVKwWRsmwr3 z1ZC}|zsy<-smC@VC-=B z%_0!RKlRjcB~6h_v#%C{aB!Yqye?dDHgJ{=UA`fK&Mh3`R= zZg*4m2rz^aKT3fx1g~S2BUko*cVHd+!xph;kdcf*E22lN6!=a$;$Yo`fjJ28L`_v0 zZG5!OGo+d}tiPQvviw>7pVnC2IxNMhJ?1_G zmNU`G?e*eBSf|Q%vwOJ!#Fg0#HF9Ty2RH9ra2(}i)$3=RM)7Ph1*)$TXs}Ucx61V@ zkjQG@F+I3Kn|-haj4xFbxvWOtE;C2vx03do+(PPnM^Ju{*AqZEVebSD3fmhw`*hfS zg^Tjp_AY2u-C1h{@CV5;K8=q-M6`z@|BACk)Uxo*c!VKFJ*R(QV1UuBo_la`q3M78 zq&z*0%X?6+FaBKlG~lCQluxjb>s=dZ7cn^iI(a$+OQC~67?D@bx(P${jkcBd8v#N> z{N)=+RkJ{NFZ0aXOdErR5!2#Y@FP}*#2m=BGo7kss{CAc$_{FDNTVJ`v8yKeQyR;p z-VCSS@XmqN^D*=jn`tO3$=Jm`nP4oI-0KML4r zB1`rRRIkTUWWE6r0VRbb!{)U{oH7eO_<;6G$DhX0>n+ALhVATrll2CB!EnWD(R(q1 zFCJ-HLo@JF3l^#78UsCx*Vd)x@g4h*GdL-goDxIgj#oD9ddbN~24)8N> zU{O)$5B<&``|)*z1{Exk)J*IUD!O0`__QjXKvj}}zoRCl65$QzO{yr&-0x}^o9(UK zwi=3&8A#~_T~()-%$|f*7G?Q)8Z46+ww3RsSiuU>Hff-xj)tVy5Atp7c9BnB`4nS1 zOSW@sAiI>?3rkm%^(=JG(3qzWPoFij5Q1)Xb7$!ehITbKQ(VWFM`dr4djT68itgk3 z7t~uGRd~{DJ3YI#9J7m-{TJsjO&)ErwSUJj9Rf!%Eai-h1Xp9{4gn4Ebmz_nalmM@ z8UC~1YwCkT9rMI;CBW61S1sXAHmfy;bU(N8haL=GD4!?sn0(t$puhKR5{P%kYm$aZ zELx0dlf#roq;>Kd-vTG{)P5VmOyR_42tD}rf}oaGQ&JW%{5^eVTj?L-#!^e>E7hMk zhLXz(0Xgyv8J4Byqis7z4PzSy-FRvV*rV@i^r%hR zT&^n%sPW`#B(^!zc!XK4t$^r$}2t>oDS%=6L-puTH4T*pPvf?7VB)Y3r=Hem2HqBEOC zs3|Nx@fUk{+@(VWVgU|X&TBC+b1mRc@w{#RGh=x z0Ff;#I@&9o9E*MeMLGejha|gXe+gqB4EB!BvP-o&iNxnTsd_E|hbY4gG%Jj_ZRsk| zgV87|6MItciy^i>sVRL@@YZfg!v;@dG zk}~%?p-L}LG%RG6R84K>Cf4jMIuIs=+GfDY6xQZfspmOCZaulIRfC0rwBd%Sji?>tqr zJY@uj2Y+{yJAK(M2UZLI4rtbQ5OF_`Ug_&-Mr18JtJYDUkowXMz3 zCAs;6@(o5n81VDy3GAy?G|SBu=fr`~8iE-imUbGr;H$IH)q57ZM8EOmKpT@hk_v|G zr0|oKEr0QPZEuz-{NsSS=+`I)LD+0Bk@#-8#FV9sSM9%DXCUCo;o&H_TW+ur~Pd>#1tkIm8 zSG^L-Yo!g;FST6(l*~nd+&8KP8j&3inL$HnnYsDc4Uk6Msiy^9KkbOu(hb0))0L9| zOvmGCY?rOPDk3xiU6szC`*_WGjIw2y;2$l(r9bgh9+z!4EV`j*nwNS)MV5F%qK)E= z75)NvUH}8MsZKw>UU%Vxy_b33&#j{>V8ILtG=1>MY1y9)Yc@gXHs~}b*67FP)eX{v zg{4ngcYvxQ?9{`&+5i6n)Ui~;9T*X#arC&(Wel*FEx#S9Tyj}iDm~a=@1j|9461?? zK--_nOh@dv+t&+s_4d$$>J6wX#vK9GDg7{?$?Plb&Sd zGtYzcW=;)&O8lj?sjBV$Yjp)a6sfqH_z4+^gVEJf`(*CYkD#JrQVSSMWemQ9ee}5t z>a>#0<9R7<)m(?=e2lU=)|<8-TpDi6{Hp#!g3!n!1Lp&w%@vqyUtQkPOBOfEqZ*2j zzI5dPCcBrB@uT{B^wy1e6*CZ+18%2FfrM$iCb89k%pGg z>Elnb`7wLVT5_X|Mz1nnE-IqIKv+Y2PPY5%F=Go6JsNVR4ue3^A%9qR#H}@XGw!vh z9Vo>(1MI)I2Jv1TtLhf3*dMBdJE>&+nJ2HzuR|^|Y<%riER_da8QS=|RS^vks#JwD zN6B7!(@zW}kU^73R6e+?Yqq%XZpt%N>+)jBR))!-5Vl?EVzZfW(-{rma=(`#c(R6j zKV6}KM75|tTB^qsQF|Zk2BNKG=Xq0m2`XpNSyB{79qZ*m%Avf~A};=i{)Sf&bHn}I zqH^g_0X;azH%!@T-UcnUcL0NJzn@=mw)ISUFOk^QLTQA(TZ5tVLx6SklQL910XikUOg(O zvg0Ev1sI!I#GjKMv9Zatr6Q)1+m@)nPgOrMlwikpkueca_%Zqhh;*VsUPCAtYfwvy z$`3_v#wSaB2Fafg=5);bu>T43ib#b<3M$XxuP6HWJY|V|%vAh0#+2d^{Wt!Dv)$^e zlkS@vo4~}g5n>K)ji4fuX*o|C*^djm%0!kno>t^6qc;AhWtvpa%u`_euGAMyaOF67 zF2;>vJ-pJR3axD`mTlfRtw}IW#}1rx3Zvf8`^~X1^Sj@?MsgKUVImiXbr@Q*5N)rP zs8<)EH~H_5lsQ2{c}}QK&xm!*7K|^1THGywRM`?AoDe~)khd7#*)|B)Cc0@oi%K*m z2AFT)K2hM)?=Gyx{DDC*RV)v~mpxsPHBZiyOT=ms>#Jw^<&SgwO}{Fh{zU*E`1 z;|r2d7EN7r@1c5x2=>__NIw)fZlFY?B&x7x?ErK|%jbI_%3T6qbY^eWqRE2Iy?)eL?2 zWn`>C?0Oa)xh#00TJ@>HNX31TgG!PO-iswp)Vua^|_i z{^owYR?@7*$87+p7J^J}CqDK)Bx^JP2(;E;1)d<39X%RO2n;MPME|IA5Pyu^e7_2m z%4RC3=2dm4w<3uc@LPNk(uH~+Ky#qS+uS2X8kXg+x9TzAyB17%A^(^x#?dym-VP_#tHeT-$@Sk?$6;rOsQjk z`^F$=9#dMb=!(@G_k7`b5?|zt24;KFs*tQO=|^w%+?rog{(>^h<7z%eP)$R)Kq8@V ztr$xQQ2+yR0?b<1XZ8Y=#1eSq+Gwjo`8_`>``aR)!-!EDzfHUL9T?dN&e_k9HF;sQ z3;caGy7BJCbZQF6vkYiTIk(&xtp*Z6)gsvvN944;sQ9YB8<&QiGm3|gShKNF#xMlfzawzw))0+~|Nf1u|e&idLZ(Z`HJPV&7@A`@i3Pb7! zYPLVUVJI(mwq*6VjN0CRr5Y&d*4PTNPxI4Wk`YkbCaVYpBYCk4)_F`DV!mTN!oNlz zWpb3C(x%z*vW!z=nx^oVAb(cPH_R#-JTkIJw(i~fUE)kooKy>6(Qhhf_`|!i{6MK8 zN#SI?;nL%gkzc75^amgB6;jEWbSc^QRoI*7sN7%)U_ug!j0uf|1d1KLO?^`VsUvt<@a+LX5*8dhj{Pbe z`u^LMCM#54xm5L{4GLtgkbm&>Q~!n&8vNrOrnnx1xsRwHz{L{rI&h(6S|f7EofQu= zEQUc?vsRG~r;SHf&lz9b;HzY)-I@@Q?Yw zJuI`qo%K^Fj=^%HBOHdH>HTGXH#G*UosZaMNoQ0KfzVJpg&Rj9$1 z_jco3V6YSb zf|agmzJvB+oyj&!K+y5u=fdIKL3Iiq0RtHQ_vdp#zrS|^ZLhM~#^Q<&Vb`1ilf(c=;AnpBYF zUi0t|WI`78yHqW99Hq=ey$zs_KMB(|5+iCsbBiS?TPFF|OL)iVvh8P)VRW@M(0^)y27)=L9G)_^rSm5rTEz~Tbs4$n#+*VHUDYV zM8ec-rXJISj*RMuZMX~Rf>w$*5KSE9p>kjbEwZ`sDckUZ_5$Gi+9e5EeKzV68tzDu) zPA_=5r%O+#hV2pr13Yz*35Z%B#L;yi8)y!@CoZBZNGt4sR{@xD4A-+)47dUvVNG!1 zR{VPNlY-*=_UcI$@AGod{Uip9Y4H2|d^3Nh=qlNt{h5%+AiR=+zM=nC^ij=MugfYR zo0cr<>@VPDcI-XKZRrAtP;^{E)U0+f3sSe)#>%kgEDa3CD0F{CK!^W6SQ5J4=9w8QHb< zKdlAZer{|`s-oxym|GDrxK2gZuqe)4PFXSgGA!v#m6tIr$kK6 z$OuXFg&yxP*xX^0BAHe;BQ~@dCXsf#mhOK6;6Pvb7ET~eBCYlpWXWW}hkAC~Yxe@f ze8g|N+m56bUeN)`%wMmBhmL^H)8b9-C;~UJ;nYDg1Ous3nY=r65r`J zZa|fLK53M)G<(=mbM%z^UCDk#?;zO|t4M^&gUWN%qVC0L%GPWX2!h^5+IzEcWIr5$ z;=&r^fj%ZZu3ojK=yE=-nBlzWLlt~N&uQsE05%TkT96Pc*2~=9qvTzW#uRM;D_)qx zJQ@N1r!LUp&fn*f&CKGsc|}u1;M$O#-($9-PE2vDb*vM@@`Y6{ z-BlV#x51}JO6bQP{8=x0DHqzURyB(M+ zyET&lj9O$5KZAT)gr8Zvxi6kdq{Rbs-TY{gUE)^!Y;%UDfx+7xvbwR*Xc8=kDk@;X z`japOJJ|fw*&49#DZYVelc4Ucezukt?_dC;j5m{>n!G@80i8TpZc3s_T&<_W>T|xHRFADCpDk-YZFk-!&=JPF- zp9r`x^&BLWJfulIEq2`(?9-Z6nnISg*qoglmhyY#)Uk=p_#NX=jXqpNK!av1d)8p3 z8RH)y2RheBIFnatwxg4{81>);tE7E$_&nWZ3|4e&Drg!U88h6o%?X#eGJV}ooU~lY6=9OVB zPxCz=3hgR6nvC8A>-mO?ze^ z7u1a-0AVC8T}4EW0j(MR#OqEBa*1h(Kd)fP{*WF0V-gXG>ZqmT;Mx{$jRyC&<2g$H z>?uYYUV`PqfBP6!*2~j?V_adZ2(s=-5tJ653M@oZgC&0TJ3bEsLBi>i1}Ve-h$D^` z)3i7+%KBK*GvM8d(pYwSM_?Qc^HBrN^s`rYDxD29@+pmY-?Kpj%n<#On8Q?6|L;A! z>4K>kHB*(y4MXL}+aSQzlaorwobrCyR(g>4U9)RDX`v+G(OD`) zdM^L|0q`H@$0Ww~FpL{N=9)#@Pz@ZB4Fxu zcXBXZ#Q5`rfx+g-`hs^{9^@w#y#?7ZG$3 zZ7}tZcdH%XPmvepI;f?PU*+PgTg)+dF?3)Cl%GDzca56478c_C`zX-@h|} zn>_4eB%?Hro=~%~T)DZyYVxJm0tx4CWhCUDd*CH*v8@ftnF~sbAS5bs zgAGN#;RU2=5XRNn{v=`pegajL?S2CS`ph4u7kDq41R@>?8me>{XhYG}rY@-bs5wC2 zAs;!oAed)@H<{lKu|aBs3(YS$FkFB`@O#d!+g!7mjuRVTph|W#_2~%bA2a-VEZYLQ zdyk5MNR#S$-VpxIhK}yMznasI;fY|@RE+s~ornO&!uSh8pKiB24}23;F(WMp@G++{a<*yBzUG8V|&WP2|efCIe6 zt;xt{qj>l|w`D;^QQ29eo)~?+Dl~H#RN_R33Ip4~exa5TXdV~@ge!e3HN(;ab1^BB zB%?j-wO|TPY}J$!)ao8xFs8hQwI@tYI#ekI{U}O2re$;S5x}oU%N`;xP+IGm5R))^ zg1h!}&MS-YQfgfYbT@8c8X)36M;yy88K77Y=tY{do%{9~g{f0yB-}k9ulB4!915Ob zP?9RW3^X&j6ObIk>nR*Uxq8-+p>l-3@3`Z&CvUJD)U-)8reXw%FM*_G1=$TC00Y0R zBsnt||FV3v57=d?p!=1O?z;<}034{m!7VHfP@0rWAJp01g>KO72IcDN@P<0UCFitM zm{pqwh)R;~&YG>)UTTSS4tvz+odHklxVNeJRl0*k(BlayTPIRcoo!BFo`A zKHnI>w7q^0LxJy-oL~@e?dj*=AlQBbbuG|kdqOAM3@wIKNtIDt!B8Ln)!4QHqX?L^ z%FzUQU(k)_4)Nf|vG%UY<~sroo_^LKWdxrg z9zG~G?OT$5g4IF4@7UO>8FOQ*U`bE2t>|$nk{Lzy_HX@qxwJ4~&z>_n&&-iSi<}mm z>0Sgh0DaVRD+&%qDHQ%dl?=}m_XD_*t1a8|RUWM?vDuhgy$NFky^MAQuXWQI?m`p5 zMikIuqg9z#G+UO0*Reh2V5}D7&eYA-0>|SBzS7RjT6Bplv+*;}%*Ba0xxvf`nB@G5 ziFDFG;EE{;3RO~XfzBjSVga)$s0Ci!G4{dD2nUkku9EJL1uu>Y2-EVNe`ZGQ(Bb)_GvUx-JX^FTzh3 znC&yj$IQ9|-Iq2UE}i<(v!rqb6dGl@PgJs-PVjmeKC$K@p@IuG@;#e9hOZ`+?1maH zO-;hSs(jz&KhV1vltmQu3VaajUnom><%Q^SQ|I&?jL9jSo0y;U_$^6BN6D)ZbbobG zR$;?Zk#x_mZ=OVgX5|L$p5%t&ggfX`mgR5`&zEr#kF)KV}Kh{=~s(Byuv3D zZ{f;x-*zY`4aDGHeONo8Kf6914k9pLEG-48ZW1&&ry9tP7rRh04*8MA_-y&ZPZIE^ zqw}wFSTaiuD}4(;IYpuwxVLjZ16)dDA?5CqF$qJ142icb&Lh@k97b1+)W(vYH(8Gi z^nRNIM6$;9Xpel1(-&lPygVhc|C*`XK*=*oK zKB)(E!GNcEJGnjqm5)*S6*c(p%67JJF?_|Qr>P7(-LIN_(V+qNCh$iik=p^(=(Ym2 z-&HO1fbeKB;5*UzQ$JJ!c?50W=qy1t4Ea zaiRHtTJOjH7&HRee`q1^905%;mlHKBJk6ydUP(TH4dM5CI?rZHRuCsW@C zq=Lb#81T2=eq*2;ut4L5(%M2maC5RAW1rO6U6^#gGf#23k$7FRQ%*BK16>E5P*&Ve<-KVyxNxd$wtPTvn#Xd4 z)4+&iulLMovC1AE~G+}vm@RM`nX`reVrV*wF^*xT z%q2ZTrZ|bT${nII;sCmlS47f94YIs0PY$4wk)UMt#FCyFn&E?%KPO_lFxt($!I6DD z`M$=G_~ttPG(7%Fhdqx14!Be;Z3B0@xfJ=uQ?}ts+#oj^_qHuS1XHhmQshNk6OaGa ztmSbQsG8QfO@N*SI8%R(9{Ssr)n1WG%VXl7M=d|(1jcPIOg%~;cw1)>Z|;7zAPLWh z@v2WK@aUTk7sJ}E-MWR5s3PLkLSh^sJyol7FgaIC7M9L6_f}T#0KLZHQqVKEe}o9W zjUUF>x+Vkx>uj$;(67=3XVSjh=39VSPCe~+ncf>7xJ3B)BPE^ZvbsV5zu=ryC@hd~ zS2Eh+I$b?5x zyZf?F@9YY}vK{81DX1-uF)nY`D9NYvATJa|iM^2Y?dV&{NuNUl$S#0pk3Oe^2mj>R%r0i%t|9|f?x{qbIF8E4G zYW_^c0~bOlBeh_}l`!~4W>n9l{ThWjAKtb_kqeSpz8IB21Lx18KIsNiWNoql(Aj=UycsdWIE$d#lV8*O@4 z7n~3-4NT+BG3><{eCpvtE5Ly5di9U7!?#`f^Rfa|&A!4{S#=B0D2-TBl#Yqm!MBoUws0qxG(4T-^`DWtg=By46$fpimS1yzhNTadnjf%enwmzQ2jJ= zYjjXD7DfK9t4a*PBBF^7tWj~xcC7~E#5q1jm45kmW@cd`uchnzX1muwV3YjIHw?kd z0>|oew76229pe_97YcHw-QH(`7ZIEpzmRflcv4;pcMPy+;g^68^Rr$nq-(C$`{P4W{PUVfrMsBTvYa|z`P~s z!3|q?IjDrTK#OX(99fN^E3+Z2FkKKm@XX&b!|43x%_J8Qyoi68mx_DVVq`DiRB?jx1~zRy=5>Swu5N*k<$>9_Lg zOZlIUdqB_Kp6gfW+}XlND{l^K%fRw~{k|{qrR4P(r^RZ|qb;GJ=v{AjYLIsl-$X4G zf=0H-tvh}nG~&z?hd7rbV2^v>sKQJI5$u~E+g$avCD5ILwsGYlT;yy1qHc?O3kZl; z1QirK6l+t9g{!`R5RjtE1(OBc!h?q0ULiCW(EY26Vy|CD(WxaMDy_xSk>E&((AF@K zO2$-;Kd`bmFi%D-+#rLcXgcZQuop_{wfBu)qz>#;q>ghGOR=^nIf=`W{EAc7R0ksx9x6EKZ zScp;zpJabcd?`}kKOFI!B&N$&@tP!~H?8eKI^C+Sh*h}DH8h9fo0^{oza9MMsmuQh zAmB1vQxRviaE>076&}HPdN=$i?(hG!EWi6aEH`z47$!#NV7p`ROwd|6iVWXL{Nh}2 zP;)>y{jtlv0j=WVc~2bNNP1mf)3BLJQM3ujfghvor zSQ4)XUuYKrl;twaWFp{Nq4Y%O9vRNIoa{CiED(7{F9*hwCkv{wIMtZ9>24^`cwl*Z zBW(%eyCmV>QjwBHPtP{t?o!c<3JoR3 z{Yr`tVlojyuQoaLHP3I7PP5w|Yn;^}6~V^K2*i&H#snNcIq4*&I!P$L#@7haRzr)q z+P1&FfN;>uIK#jK7m05N#Qr9$2;lTeD*tVQh?)w@GKfV;>n5@6ac`OgOOZzhZIbI0 z;yY=;o~5}!@Y`4ztS)jw<)Wz^xA{RJY*&%n3EYwupyZ!z-n26;v@yQDD_Bi&{_xZq z_Xe-~WPUQ~Tz++MML|0zx_I};xI3jopJ09`rL|8c0uO-~vI6IUf8pD4GQJk~UY9B+ zifVs+J$umM1o2|5?&Vc3=T64|i(dwFf4QiCy%yF;s;kBFb;9PR5Bxoz)6{-+))U0} zwZnZq3!9Hx9Q2Q|UoaiH{Mc;c@j3026fm~Za%zTGd(FTxiaQvn8c)=V!<{JKc1=04 zZJ{@4(c1Afg52fL%>!XOQ&yv2IE8i}Gm;C$dKWcwb^LalzN2w5KVUz-RxVUMQMAu) zNSbo}yrE>?KZacGui3|iSp{ZTyD0l>u`IW>*7qZ#P%OLeb1U3HZjLvJe_k?;JMj5uU9*neN#O%7z4T_Tr20^zM>ns+|sZ zkGNN#4y)o0Jfk}zA}_xgUQ^QzLEXeRV{YT4V;q@7Yv()@f6qU7YZhyAwC-5!a+i&( zlJpOq9>i>`Jp{a{)*}cj;NH6r)c@^Fw_fnpXrCHj?(pK(tnO{#nk-kb&J5VwJ3*>D zrVUy2c>Frbl@dee=%L>}7-?PSR2EI%|DqK((|vw<7;3;@P+hK^ z#16C==j?ZOq>jO6G@>gdYXR_-xk45DJ+0;G^~)i&amybE^MZ$(1lb3Mnz8R+C|dv8 zp}p)Qx|W|TfL8Db<-p}>iF`!S)6VjYI>)Ee6IQ;qk3EPe1@|>q`lCwskD4_C9q$US2lr)99pZ6&tCZT8`W&PeaZLfNW_ARm1r z!rh!)00U2uPAkIK03(KlAVfVEo2?BRD9fpuz4-*b#K*F)&7cdFkJxIy3v^_JDj}zK zkRczk)v{!DrCg6Ou_eEac@cc3m&VQ~Zn)jXeZW zP5C(s(nV)&vd4c~|2yJLyW-+P{Bz%r*Usm<#tQf}+RG?Ohd3L>K*RN6zq1T%lnS_GSgnd;K+`Tzu&$l%!V!Q^?$L5p)Y?4?A0`vOd*#($ZNj#*GJh|HMFw50gq%O z$6bGk9&}gNLNn!h0h+na;R<>it9V=x|H<$@@m;h zV_eX;;&4Lw#^#!n&1oxjUKmc*2oRq==FAJfysasCrX*9#xuEc&tDMK%7<$-%d3iT~ z9r)~V@>i%nGCjk=pP9K1LXn)XiOtlDg%K=^N*t?s`<;pxCHZ8fO(ILLtv8OB4 z!L21C@N$G@a~r4Q_jB%_O?$gb?&+_2y>aEl;y>L%*>mkj7qB&uK!aO;X;7^iFcQvj zS$#_fBL|Fl_a3Z5&oJ!y^m73(C++cfKzt!~GEI?}_B^#oKt^!e?|!En5H*S_67VS_ z$nId3H-T)*#h>oYXd~22D1VRAuLoi%@ok&pGVX}kaSl_?$!ZS9DVfcaap+)#!(DRPF=JKv(^-UdAW z`1Gd{)*hvnOqFMQvC6giduiKo!OxLw?CkY6JF zNtd^(dKvfBL)ttEv|?=EKS^ba5Ju;@Y>&oj1^(BM{_W6MlmfGHx^#_2@D&c%Rn~JT zn0Y62am!rH#qj5FG;cCAo069|l0*tx zd^>U5WhBO8d;s(YS)Q$rUOK_rfo6=$YVj8+*=r8GR?nyaG4r+BB+LkK?I?*~la1|! zHh^^stqTpDF$kxd$xnf>9bMZ=OX0)O_I>3k`~{L-&Ntc8Q#_tC$OXO#ziYb3a-wn! zs8mVknc6L|PMIasGy7zd5vT?dplSETu^=_;H)zw?E5J}XUk_mSYRiSMHRcSY6KNKb z+^A(=l`TFDXVlBb!!s#g_w+Gk=2qe6z27b6@aGYJpM;YP2c_*YNZ9}An>8ji{#H~2 z$rWy1L2VKeqOr`y{WMIVY1cC4_*A_9>IuDz2e3$Pd+|0R$dDRj{93DH;3=KX-vF#j zwnFV;(2GV#{b8L7#qli!k<~c)AkeBd&^SgBOX@-#9D9FfrsEaRM0B^`FwWM=0`?kR z1jEj*X~zeqw9dZ8@d}vqvyle_K`lv1z&v$n%LTr*nxl9B{x{bOJI3`vy#*1_x>(v~ z2(h2=Q>Z-BFRh%D0;+-FGgHlp>up5>_6pyb?sB)GKXi_%GM7g?AdX;3V@78_zU^H| zgF=*S-z{JAV(}R9Ti*e*9j_VIG+rnJgRnoeZr(Y=_WlGQ4KlrL#F@*`rtfTy9gUG-jZj2$nZx|><@2cGwgQrRa*0$Ryn{DP^36}$Z{7z+oWQX*dOLmmV^YQx@bJSa zOh=lFQ+OzNoXrGz0bUn0)Ia@V45udPftpAaJaB6woK8f2$Lp-WqfTF$u@_hC+U1soLU)?4+6G~9vVWz4zZ`(caf4&`FYjodwFGxm|_)zTurQ7o7 z>+q}xDj=2OA;Q9^~ zi7mS2Hqj-XL$J*qO$m8tk{o<^f4uFGj!bhwq zFcmLZtBNcxn*=}<*YR?a+sDWwmIG~(zaR%O%ZAj_7AH|{D=POtt%qRq^=?)2%}>*X z3h?`@ja#J)si<5$#d%PH(Lu1a@;9({K&Yb^vrj{The(t(%t%&(XbJ6{Rx#ic9#J<_ zcSlGU0ce{4{b{81W$_^SKdmR;yVe?%6qOd8;NC^$135}Jfl}?BrvQjEi1b0LD8Qfs z>DNfU`|Kxzbe|uU4#?Dki;)0{R@d!QW z=_d?0c~51p)oXeuX5%hwYizOxjc?_tzR+Hv0e40h>zUKVnKP9Z;UDqO;VE?DMMU%N zIMoxkwSW z1PHnXm16Z01^IqhdouAn^A;V?D}UfjTmw|P06xjH=gAkr*gQ@JGNWky?oUrmY4akG zJ90a*q`RF+Up$G3RI;DV94(U|hFCuLd!==Q3T%Xeq24s``Blk zXs~8U=a5!>?^MisEaQ4TlUl_3Dnpj1?$A-sBFurdldZeyw@l}&M9F#WfMi4@l6`+F zeBfjXUp%bGuVSi9o8M1b%;TUD8q<|V`*?ITNOkhs7J*T5w>*U?$uzW3QB=-rD?p?) z|5~=Ec;R~J0uZD4f3NRnESi}#xA%%dZPWktdLR4L|8EGSz!J-WQ(`v;I z{X6Bb?-uGiUa_gd&EZW?#;-{}4C`(sNi^M*3>#f=|7=A8LZJ9SyE z31!VqhHG?`%NB>slGlGi7Bo7IWk9XHZw;k*<9Jtj?eGa?@xc& z-h01a@7M7>9uE>~x`%J%+nMF3W@Lj|tV7WCXi(XK7_59p31Zqc{#nu8`D;aZQt*5S zVve6nR2*QdkPm2LQcAz=1{<1ZZ-1oFV0ebts+pouKR}QC6+&YEW)gki_B^FCTZ0IwmTp%eGt{&wit z0i^{$<8~$KId{DVu)yt!o@@|)32Agsz@7Z9rK$$=7#!C3J?G}3^ik`>?j@^MXI*f( zcOiQkvq8MA<7tCUEWH|J8D~iDxGr zR06)v2^Q-T#awZ)UA0N8d8kGF-_zltbC~zq;#c{~wGj4eF^*|hT~&g)2f4)%FJYl@ z0#3MgLf2sZRA|KH)Ev}_luJ+0j7=#2%}Cc+fNa1#lq*11mm)Z8r(1a;r|op7`bntk<$Kw-jAPIElu9?2T208IH9N608JUArjHlPmMJ1H+8n$nC`HvVZ=`B>iTIh?9~S&yGL znIp_Csn);>3p;6iZIL$FyH)RsY_>3XTQVsPF>RQKZQLJcz9{B|GxJ>M6&wgUZJHs9 z8mHH^TpU|Vu0C;471c?Ez2|@R3e1ZecVLpU!8o({V@4y2S&QRJPqv07pMx!QT$Qk@ zkF?xXm?PATd0wwgUxFC+CwkebZ#h2DC7%(%Kk zR%vQ}T5ym-SK(2iu3*@Q#p?n{n{L==Mh6y_kh@_~9c^4joL;pCo4YozVo-x*1Wl)+ znw||Lee``9eCo_D5ftyB)&@`bHRUAkDCOy9hnH{Z^{zMSqVt+%X%LmCH@A|$?O9bNAe0sRA9b8 z6x~krX{H~j`rnaOdy}8TQo5Z=PonMxoF$!bxl>d4;S9q z9rNGz;qRB0x;Qg)W_ELvK$qSaV60`KJsRnPgo2-LFRnr1DTXpf5XM@3zJ30a39Z(i z$tITfpVRd+n6OPrLuT`QX+XTh3RP1~P(lv2ATSnKY3g@eHs?P+o!fNv+)N`Ymo|gyaQhF+pSHSm^GXkoa3X@$SF}E9y8f4vU`^rsDukL1D9}LmuC&k%- zzSs?OuQ2S;w7`PBZI5EQMR54iStA@L`NW*?_RxU6#`KLiGtR zt=J!(<&I9C7n?nltS{!>#$WF>o!awK@=OCQ9!$h0Oe36R^Vs?EOp~8>$x0evl99c* zizn2+TkvDb-%Z$QREO#x--T+XtZ-NGB1+lx?(YXixrA-;J8AD~ST@?MjL-Yb2HNFf z@Zbl)m|Cuz2j^AZwi>>0KQSpqgt^9_A&bL_7r$uk+VdvoaA=N~;lWkIEA*i?0^2`W zj$Sd@prmytumL~1kN|z{rXTilE*a{dQvYJ@u!0T!e_V8{5?f=cvb!yy)>xV%(xS|g z74PAf=D+@XyQKY^P<6+Dd`!j0tiq>tC|6suOiZ-bNsL*&26kZS=$HAZN7qzi>Nc|; zj-fn-nF^_cuR^>rqIxHr*rysR#e+E?sHx+d$(L(C9@)3H z!TFuWtxlFkFCI*vPYVw0IWy5Q^L69OwtG@SQ+09GIp|a`dzc6BBehJfKscg0^pIiP zY2H9!xbld1I3Xl&m0qUPB@X{S<0de(i*Hw(nc2LfZ{}Y^-hsqLAsb+e37CU>S+_Pd zw>W6lr}sNmbPHTgBgT#U)Ji)g zQ)z{`xLVNY4c7TcGi(oNNJ%o78hf#xmbFwLn?3t*28o|7B=}7lv@;$!Jt+jR<@iFR5 zW(qWYo6GU6Q!o@{y>d#u#UWr2S3AmfSQ2JpUc$`<01=j*YJa^f@?Gt#+^oDF-7!69 zV@Xw^Ukp@R{TXeJ*Ul#_Y+(h_Jp$n~^# zs;!wJj4qR#o2bm;ACYd>)`xS0f(V#X^xw>hNcSjUpE7k~)6s{8TYdkn zmv&jZ`lrDn0XuzObBWXdB8*~fC_SkSgOgyN!a3p4Q6cj1Diy(BpiF1ww=Y(kPG5iH zhR>V$-)(nst7%D<-bzLdjK52mTNEngkc8UxH&wS5`vPZ;-m=Tk5Xi9chf6{;tKm|h zwfZK!X2`>^%(;-P*7^O9&$B`27RN2+Z!uA8$(6JL1jX)K*g4)GH?rrUnDFZ!gi zsv!t`DU9%xQ5`DC>tbsw3;G*5xxOXL97$o!&&hXAB25W2{^hSZ9zQEOy?k?6dtBVW ze#!Pfz9$fIqyaO2J~uj7cs=tpqLcR7#Op+^Tk<2nJ+W8Ct;Nl6&Zk-huE@=)a70ba zHxQAF!#w3+EenathL2&i%E!sGD+9Ne?p}zwafH@Q9iDTKAu^0Qy4NPagzm>t+m!0A zp4RH32=Wx3h9(#1miJE}bV+GmHb?qPYsO_#3+6$@^OAu zrO+gO=CYFlS@(OrpW*oz)X6~!4Uo60go=AT$**Y8 zWz$XnU1_iu{Vg|(qgJs>7fTB*TF#anJm#_JADhYSD zxc@g@T&7-IDh?*D4tu3{4DJqVVV{0&b{c!F2fyqeAr)P%wF%6=<#X$u*?X%3RKy%8 zYNXh=m1~thnvz~!z4T7A{P6tSp30C(j;NcFGPqqwx;HB(l|m47r)j4;>9ms^e!9jQ84 zTR55Y-hglMds0qUyFg8KI%=+va^x{Ho9z@V+^!e!W8(9-y||(iHiM!!{dB(vmIpu= zWqgU)b>>C6HHA60%CrF-W;#NJSL@1uCOgdP%S{)?8y}PxHTM%Y(|IMO96C3SzIegf zkcdC3cPTh%9^c8%J?<$HQE}~h{qDsfkH~Mk*iB~_m#M#rtx=X>fT5A6zH@-=4pEJI z>flL&>h&D_CUart;>=;q_?1143X8e?97h}zaBlWEG=0w0Z^doo{I+v-q(v%t)mpjM zrTlpRBVcW>2Y633QIBClNJpk5Vj)-bmvsw+RCR%U?IEhr;B)!0-7hbfZ0!_GcL~(H zlX!~UHk>F@XVdRzCgp8@%~(#m=cVIcsLlJyV~5-&%^Yox&Qq8QQ5`BrgZoaOS%i+& z2PJQrXtcCNY9#u_y}qS(*?P@4VTC`FX-02k`XS+9%b@(7b3DkWGQT3tS1Hrc+qF)! zSGS>i|I*1_ACc&5HjUs4tsu_1f=ns;O;hLFBb9&3tM?6wtl6ab7OE<$UNv3}u@boQ zVd&QV!!to;^k+AzPD5ZeeT{Xr)moEYI3SI)X&kp7hyQpLIUUQ}+%MOtO?`NreGGiA zLAVre5LP?%<~i5Ti>0ym4Sc)}9W6nQD?HYfVJMe_?}}N_FpDE%x>cCxTZdO|;zLmR z71n{6d-*1jqA9Pj(b{r-_r!D;tGvK5?6nK83&^q~*y_K+&rhneuOrx=mz1Tbq6=m! zVT*n8)Ay9M4qqGZOZNO)RzFmScgGVK+aV3^Q8Wz|0k1TMr5%ny5P&JKcGccE+ITby(r>a8wqd42K)pt7 zm=DE1JU%?JaQ)aFFVfXxCx?}$91E|WrXPyM@#ZA zkw6!fRYcg+qm9%dj!tQ^8?g|S)Y(Ui1qm?2saNK?L{O#-X}h5>Ah-$&z8oJJ$CENZ z>5>P}L8GOHCrfIuPqjfnf`S<3Cb<9Yob?dZc=UVQ;@)7*lFj;)EVO-A+I%CmXW$;j zCjQwv)(h2+b`H-YJTY>3{=pSs?`W4~%&}#4XYDXP@bWF5dIjZa(t8>l-(|H+GW=Hp znWDAv*K$(fS`r5Z0?Y;#<$d7gc_kPfR1ax|XMrT-uNwzfM6(F4)@JjCg3#=74Cn{N z(gL032vVDtjfqOnNT9I%JHK1Xx2Rm~Bv`Q?uwu}0Vm|9>xl7bvjIdFklRh^b{%rsi z?^S}jgr2VeM`lS|wnLbhqvuwZ1 zlr1xA7dlg;TxP)`> zN89*U0}8R=y9s#h6?l0=aEbd;FON=4aMcS^08bh@F5`FUArw#i``xJa($=I@2b6Z2 zIDf+_7TD0bEY!2opB4LTjq91w(|_L(O3GTE$@O1$8b43<2&#jNoJ!w2zTFJE7VvkI zuQJp?%KfKq(5HRfB#C?ATjl@tYV*`#^l=@5 z3>v_KdwdJo{}sd8R{)wfB3ZsIA1lNiKta=PhveGCj>y^)Iay3GZ79N96KY`7f{MU#HBn?B6orPe6y8_p`S)ORQJ`8!mFfW-Tu?g;Wh$ zJdkH8tz4A!ghG8lndWSn)|mntm3$B2;9POAO|)DZF-c9tF=D0?NPS}rQW#39ED~*O zxEC7C3PRRbN)4oJ3-cQIo%;NdeOVd6^apTE@TAX>rR;0gJy5BAJ!VVx27W8?d z`9{$XC7I|OKD)oAGz0P3;_@RTdhC~0fPnuCVl>W2pue2EO3FJnlToWJ6;i_+SNPVb zhg!-7RQQH7-zz~D0{nJAQEO}PtJkgl6l;9Gz~ebe+4Yl6u1%{Eqfayl*QmlhjYhp4xfIaCA(;gU2nW_JA29@B8%bF-eZd7!rR)9$*~}J2A9-w$ zrATuR1JrolONyZiF~S+Md8qh|bQ%ptNB@r;oi63>#tPD!B~#5SDphG@-YS=j+i|Mi z(_adSDG{_bEiOuu^Rsp%C(Z*VPpTo?3BC6nOB?VzDvipwUFt3&GC%&yY&e2WL;`oB z$aCF6z)RCH|2D5wCeb8?u;(7>fu$&KD zA}j1a$*Lh&A&Ox*2BS=N*WJYRC#9ZbW0@2`%)l?+fI+j{;5ybs{f#GwB5(EZQIx+A zo6>pnF8RQlkiK@5*yaO_*Q3VO2w9~wbMh#~UOZvB3{+;*UyjIwvz`}lCL)7&d+^{S zo25K_6f-l)nIv}*WVWD=_``T{Sn^5s^H?eJuA7ZZZ7l~_E4m?Iy5d?auC*9ftTM*VPysp z&i9BTW|bv_W`FEl{Zoypg3Ki}##Idm=Wv}Y84js>o4RT3{3MZFU+`6tY@yMX;Fzt2 zI|fdb`=`?w-F`ZO1zaD(Uku|IQ%B9-uey~1VM_Na$gN?K{UnT+n1#11fXF6Fed?_) zpBQjPWB~V#56hR>dYdlB+Hu=#LOCN zM%@Ej5ZD7(-nD6ed-BQoW9yTtcm3fNc0l+L2G*d`e%h?PW>rkWD)jrb z?yp}Y={@f%8)|0I^lA-bnB_>AR3?7o9%ZTzIxV|HTes% zX3D-~7yb>DhU4DM{Va4S0|Vy@O*!p)e1HOOISHGlSD5nqK{ydsm%%O2+rRqoWMn|Z zdLuQvK4)I$qD%{w(QF}zj>9cPHfEc#Ki7%OPDn~ zzdZde?&Iah31)k7ukp7~?x!zQ<6R)TrcJjTwIaMNpyX|TkCWQJVRFn)-T})6p)k7f zu-?h)7~C*jNWa0gCGC36mjV3Imocix!;Toqc_r{?eb?A?&pmFQU$n&3y zqNaI4`xo~g78v=ss&KOV@Cuk`ImaYc%_8v|7VA>MD9eC`))u&>DNG}hb-^UJURL-* zY)=Cy4*!$LysFj}jhIJ8*$by(R2^4G8b+v+RA_$Ec{v&3%v)1eA*-YkaVq5L5L4Et zY(bc4!V{Hyt!wH#@8q+(<5NXD`#&9;)%5$B!y{Jkp%Nd3A)X4VLxuz0Bp7>9gSv^u z4GU8%@yB?74VxpcCYyGM>|dl{W-Fa7lxSWb-UUry4IM)Z?4-e zhVdVF_BfjWjWlE2T!~@(&*Lf!NW5;`nQ_^1CGg;$iyt>c-6o^ zR7W6qVV?jE>AAJB!E#nDO<_}OdD8)6G^ks`mEQKNPMue~504Lti);sdp)lnrU2Qt; zkd5fo+#@Qa&ZGEmLRHN1S8uH$fucozo~E2 zH#+wIFmJv5?NFr0u^Y8WrZ%FjR}l9D?4Ms>n6aA$-+$`d=en4VGYdNHzhn~nD+7Nz z6Ou2V)H!u%CD3@+l|NFP zLFcE@jMFxGdmT3Z9;d5tU$5i%c%!hRx?wL$?Z{ej>&kMrXXDVsiey&dZX0Pi1Yd3y zfOWo(Ms+}T%t!)XbNF)z4sdzM!Bs+t?9}c0*d*+pH<5ys312a~e!|`@@s?he%P6Ki z@RmDgEk>>VS{Q&TOPZ!BT-T&4Ts6$7`H}GG&fpEHEA89+7eh`h+z4XRp=j>QYB2ckfKD3ktY$) ze{)GWvv>FqJ;;~si3S|66_{vv`+t0rNRK%@^G-wJTT4o?n}Juzf?ck&LsA_4B&RMW z-9l-1ENJ6<b?9bH>BsYx+KhTsTZsMTYH2OSwP&hdceq!p?K8s1V%{Lw6mDpD zVH?faLA@f}k=ITSMSPKBD&o7zqN{Kns+eg|z@xsA*4)-K(d4rOal7z&r&8NBb|{<^ zv0W3hN4YWKXHA1EYkwOho##?Anm@iS;Kzu|eO_+G(!qZ0b)4PFr#d6c3(k~F)@`3=R2M#1nT8o}K-NG?OsG{e zwqWW%K9_;V2o(;}_`thUy(TOEqKfy!FnosuS5R{w@ip0uHII$(|M)sH6ENJi3t;?* zoxs_}LmlIGm&C=l89pq@Y)L(S%ce1^3nx1a#m}`KB@Lagp2iW-4kb$cfrqQ!oZ5YJ z2n_s@BBp=&X<^>Mnt;Qlxvq&{ExtVx`LV@W|8u7aqc9aY{pKT$)w~ZEwF%=K$JlSm zaZWhjVSXht{%ZbPcF!EbtLfAI56a%q{y`JxrD{<(!CK7BTC_<(LKam7V3?>@_fIn+ zAS@FrKe@|@sM*nU#5+|4M{dZR^5;|+9q z#KWAIe2`ssW2KcY9+H)IMZp7JfL>_jrCK|Oq%e03L)bslRlruhm{{H;d$OtvFzL`M z@_&!N7V&Kk2W_+;bRJcW^CS%5HJoxR0-UpIs7mF*fbstYhRBMAw8r$wB%euURl)lR@t-AD^*!m@Qx#MKF zm+g*lRA{}8g35H2V##Z3v(y5c=rR2KN6<~@l`j?Mg%WW^n%BHAnIEhv>1xihs?8b5 z@NI#ps%CYE#r+7QR+bXdjN76=I(}M6TuS+BEoZ!G@F_@hrzP7p8o!iv!0A3paru)| zO?4VO(1-DxRI*)-Q^C)@#2;;dd;XnoeNfb$K3Z3PJtIWKSoc%_qX*__`2$P{Vd3X* zyGqN&dW)xcDW*)-!q5I;8DE7Ig~uA|b!;gNSuV=Eo-C1FJU)k*54ePJXFH$-W2t8x zRnF(Hvnxn#p~9hTCWtJyQjP=}NOfC_9qoYa_BB6iwn*ZbMZI@?gw!AN)%#_u)m77L{z0! zP~6$t#?smyXJ78>)ywI|LzSzD1?uwFm>XIynn11wTnYW~={i9WyNH{@q5!)`*P zeM*W861)p^Pn>ZT10pIi4U$nC4k|u_Rhxg_$gnyf_C$1-)ZX{W zSGGR>^?xV^KIk0ywceh1DV)3q zJg@v-3D;o0VB2$ShkbO_$~+%9dIYUa)DqmEDJ^E)UUF#{oLYaApgDO5?&7l0pU6CG z6R&&oKfVJ|3D1qm_}a{gOHLQ!6u9}9_6QF>;&V)dRfY+3#Gd?}keZqxPLtDqHDrYm z0&H)W>)yH*{^amz{8Y!DKfm6+P~aV4utlcB`@)ao%<-F=rzp@)v-{WQBm2dVU12r#Ri7{ZoptNI zQ^U1&rYxGIvSzYDH*xA?NZh+mSVjt3lgX@^IZOyIOSAJfvt8UDD zUA%Q5tH5smW7;!n&za^$0kDI3?eVK}UTVswlOVEGx%1K98*@MjXD5DFw`9-UM`R~t zZ2~MwI`ptflt%SLjTU+^4)te1+DsLMei37nQ4-k1+|n{hb%udZHTlDYOqUXQgo+$q9d+sSCkKg-)?p)GO&vfczwrDVBQH+{2 z2YG9+G??Y=HSbVl2hEdunqS3bDyBYp5UHu z2Ce0??;}GuW>e>363i&$lsk|cGIfM{ z-k|1EcuF{Iyo)IasRWX-nMOIm^T>#vTapRa^)Gamw0uQLxEZh2lzjCie6ihNXHcH+T8RF>M4LBVm#0b*nAQ%L?hhwhrzibfPxw z5PQfEjp@%#-l}6zit@`wYWw9z{i{cC4Pfl$d8S$8KUc?GNCiCpo6@7MAi_EvjdP?v z+12BngY^O!!;5lXU`#vMhPA2iZQcl68Gh@aH3n~lT){NOsHtXGzBB7>UOY+a3KfWl zJW3=A&|hZu+}x~=hX)MpnHpl3xi+!Y<3)L=ZoS>*DsWQQxx^WI$*%C*lJ|D`^)rl4 z{DuKU)rgjnms*6{8R$k1H%D7SC9h zP|vaD$jlPDP7CwJywO};h|=O~nKTb+D1YP9AzwytPXio`&2WL=l)9lcOdiwbtJqP! z^1_0fI(G)Y$!W7p{6crmzPK15(zW(*r4!s#y!%T5|>E7@;9q3UEjyyN;~ zr)M#Hx?F0*7$s%L^rvqylL}T<4ut;m-P^U}$YTL>zN)4Ce3nE92Xm zSv2q?Jq?dqzC!J7=WPV?UtPv6ax%P>-MWcRUktu9PLS_; zeWv0y^;Sm|;14|>ze7&5`^KhaB{PC7?|*r3Iph6~M#lQl3b!>I1-RQ5&uYq)nmt>; z^VpCtlpwf8&;{b(W2&jpyj;(fK%#5+azr#MRnIfRMKACcKx^7RGL!q;Ff`EYS+ofH znIO#KGPn-}`SnE?2vesvs$H4hhJV^$082eg$w)6U+DsMf!qK5+@I}cw&{P_Nip)^| zqKD1S!0qhvde;cW(U#rvjSnghZ=r`}?J`i&=`k_-*PkA=bqLV0Mg7!!AG_5U$ia6S zARD|JK`7TPO;bUVpQE%j{Nlj7xTyXa2(~e)Kr;QGtZ(|M8?4nj}_p{6hjqeOfo*l#nZCZTO zoJyDK+Sbr;pq29E??k6QgtSnKuIVa>Sg;fb7BS6hO*k$`vZ#^I$9VTOHb z&9c@ef+rDODA*ci!RjdX(}S%8rl#UlvYwt3+9u#ZQ~R7Iz^+9&B;V=-^hl^oO^D1a z4sb>_7DdW&!=tk+_RH5(&(apE+|xf zRN8QB>|dtPjb753be2fb8@+MN_@F@_CCnc=Hk1V{G1kC<|LPeDQ-v0{&{Ea^BdcIy~SE3y#fC?z9d!)N7(5kF-t#Vh1gs)_Zby4bHmP|ZlA0PP3V9+!eFGq&W}ykF!JbZh z-pTM80q%~ehuFVXRLh`eUu#P^`?AisT1(=IV3eiolI=;xx_JAPVnp2t$OUh{CtOKO8DOON^uHS5z z!!o-b=T4}vTIV%fX&sn>Ll?3oMcfXNNb9H|Vi7j;;*|fDANz_`8334ZmOJy2yS`w5 z5T1lv=j@A^avo5g{Mt|`g6<&>aspvobSd>y7}>B4)bTp;9jy5`oYGO&f&w6fF`gM_gOP+$MV zWb=x=aPZcJ(MD)OO+Lhi-8?Grtznl-xInbxz^=RzErMJt106eMb(hUMgJyWA>$`7N z;)4cS3X<+5U(w^Bj+^s8PU)Zdje*;4--~5n0EB{oN)P-e@Aj}(+J@`9LU}tT7t#u> ziCCO9>953#QK2cp|M-+OM@14->S+IxwGX6yepFG%_4yseA=3)?y09h>KLRArV0Qe0)yO&4kj57g9*`o%n{tfy`uE3zwpa!Tn% z^vI%@FGw`sKXyPejSTt}(`jQ5gV+id%9?dR4|71M2@_*FZExhDQqNr~(~Q&>+N!0Y zy|Dd(unZ_J3vI0OO@i9-PndKn?prTUW&W?_*(SG#Vu6%}GMWAuiq>q;z>On@+dj&a z4N;y-k;*aUC7!%&V*d*KXchTW^`_-dz5msG6%RqQS^A#x6d-^RaG^ck7;L?4zVtL{ z(mhMptO8HA%?pkmj+K}}3DZ>>4=sN8XJf0GkJ^uKE>W@a7pjoth#Y}ESIyW=bc151jWu<+r z35c@6qgWgxcbk6Vjstz${ZPTf6FPx)AOh9stn1<*6mxpxuVka0;cKg^KV8EljV-JExBe^@D`dE|Q7N`0GIRY zj(k5TEA`+h_1Cj1P8F)!71NG;JrK$?8k~joQ-IEP>}kamIVM_d+lMDb8xbX?I8Y;O z_mRwRw_zTKyA6>`77-hqdNjHm`%i+ldn{R9-wCf)hq@b|w_W&7)yHhzf-2YqYo#*E zY!s&eOa|y|&F@<8=Q)A@fX$cwh^womIsv_SVLJn~!Fdd0)?Xn)1uqRCB&xa+X^Ws< zA#EcTFi9In`a6oB5I}2p!MYaPYM1l}l7~DVKk4+YCY3nW;UEW;mQg(V|Z@O7kaAzCZ7BcHB`e*)zr7vM}7JWXqfGiPQh{{ zVO!(M`+oy|=6ik(dngg)A)n}cOE~Fxo`awGWF4>sgzXKI`)06#qjrSntg@HAll@Lr zSPZJpn459}{uQYw|Dv3SS#<{&2Yu1dOWkZ0}P+cWXVLV)zpd0jyJ}f0@M_eoIXE z@!0$lUr&YCcgIhdfj&PrM8SOT2fBI&sd6{LbJU>mto}up((Yal*+FBYc+Y-#i=uJ zZj8{6{EEb1grzgfZL+fcCqf&lq9|M=>x6Dp)?*UntQ(JEBsXKmKsWIU?l6z)FjZA&qzb}VthPH{}-_x z(X#e$#$T+TfIh0gYi*1rRZX81!f#wCwCyzPqvhW*d0b~-V35Ji!?$fMqX&y2^H36( zSl95tRu$|*c>`yRQrl1w_JvJr&=f|t-p)YVwOnM`%mv7vH@#emXfs&_uPHuY0z=GSt5bq53N${S3|_t0Ed`F z?lb*%r-A$1ae#3GikM3KI(-rTi-`&Njr%WP3ovTeCywKrud%1AQiAq&dX#&vt%(X> zh}^gVoM2{?pZ>1g8(A0y4!VpQMo@$8vL?Wy(JHSLcw`)2Pm7XeoUjTNtf=d6Z(OK{ zb5~BR%Pm8l@EcN|sFWYHP9Gu5&we#EU8g+1%7aNhi#F!Ieu=bIy@`50R{Pk-3p|9r z{CQ{h8E|RE7}35jA#Vnjo@P2rUy@Q`k4-~@Nl_fZ1c&9nApH3>ZK>Pd)~rpA0X|9S zn9d46d(05CbdaOXDkEf1vq?ZOa;MyBCg$pNRyN6oi+-LFA8zl@KgvZ*E+sv~PNORK zmOnqA!a$;gHy_l|UX!eI`t;l&%Hsek{-N_ch64TMEX^eWi5M2zq!U=ZX`w#rKEME2 zQIBNfZB&pyN<_U%OqQtm7zFzmPGFfn_B>d=P7liz*PWro~v2N8d)dV zi{43XB0R7 z%JbIhtM7I~cjW?Xf|Zfdm(P#?AwxOpq{I)4KGg9u>ngNj&}g9WxNwnKx?A702E0*0 zaGS*vCrV$oIuKX0Jo-CP|J1H+H?lrYz|m7IaKjFhNo81^Yfs+@a%}J%OeK)o9|+p8 ze~|*Iu(qx5Cf4H51`f}2mrFAwosZ0>%GCVNsS}j(2WIjcfcYEAd%izG*QiRXYSmaq z)nScyz9Tci*&6z9Czfpb!|)wmbDm|+|2n%emDHGI_aq4iqMuI6Kay(oTv43R2%W-k zJ%B=dd9;zvu4H5uB;7We0y|4fdi~|nKq%-3N3yLHV@UoDHtXhmgtudLK5k3a+08E2 z0<`Mc62tRr-<$}hPYK4`NW98y{+!0MI!!$|p(RUmUg8}|jEfGOuZgJ!7!2)Vb~w0t+$_!~fdGH3Fq6uhdl-l?t zj8{|`P}FoWYxc=vAZ4C>^TCsWMm-QajV>}4)iBrlJsu(xBJ219xMv-Dr88=_!8S)o z?4YMz{2PZRA>PQaxzX~h);YW38Zb7F4I3(TDGhliYrqSb>C1T-`5$#!MaI(Lc7aL4 zEo-a4PjdyqhJFn_8g$N;NV)}v)3!yuHz^P>EQutOvw}0+Rjsrchh=LRQ{?nP2}*!5 zZ++H2K|51V69F1rs2$mw+zD1V6`TtSFl11lqH&rpKHLuAH3=NqcRp_Ihy_-v^~c(f zgf4)h1cL;TeqE9_{5?az?ahEH{2&&7i{w8EE~dv5o@XPl%tEWEfWKVvMG8~7?lUkQ zPaydjKNN=HuD4|(M+&`T41krG;qg&#K`)Re;W1O3d-D#e^^x8-*v64emOy&4p0cu0 z=!Mh_LXI&>9&V7(4~v1lKc0~8YnB$5R8hLK&$Bw0SPqDR+u>B3~9T@`=7g~CphmfPAs>!WCu3>cr!5Yxfgi-9VXTTbp?9>?SbmCra&3A^Wknz5_m@@)Koatp6oY zp*Cu(^3j$Dx`LP6wDktH$&j=4-mjROL z{#3lf(hQ*BLhZXhf9{U^Cb=6Q#v1djB4f*br!KB*$i&tmHq|bFGIbkb zM(CN!2ZdRsk@_@MfUPKbJf^1}%p~+O z4POmkQ8T4x_Q0*?ZJa9$(%Nt$e%Um44whE5lpe{-0*kW90o!ArLBM@l;oliAt_ze| zqObDo^yqf@BBPN5E-ajzTd}J4fy59{$*?QW#ZG_#PEwXWg>Hy+5aqZj^rf>Y)zj3` z)DesI_Tp0L_{j1ZtqTE$2hT)9GjNt1NT(IFLen_S1o#US#x8@IAVwu{D>?}4uB(ntb_!%~_zx=L) zpo3_^W2{t|9|v#mc?&!d-UKm7(2D9*zt{kDk%0erbV|BLD%sw^9ZXv-4fYEL*81RN z90a%9-rck8!yX&R%LwuTTDD7qw`D9FKA_t163$nw&FDD$=T}@EmN~qgP_^@T3M1B-H_q|Us2}9}QP=WxrtRTfpK?tv; z&u|D_Mr?jM(EOy?iFB!4T9qo9wah9z$I41$IY1UoggRw`#14`Al+Wc#EwF$5$Cohr zg*EtQT}>IhrS7L!E7UY61$@YzCzw+`YL820Z;UExiAw>Fdi&NS1eAkQ|Qr{-SXD1eBGT+Ss@Rf>ae^L9?u<>XKUuYFZ%aE?9ZA`!*;Sj6~?X*;@OzjuQ1B zCzJ3k^?Y&tMGnjs%iE_1(%54$L0USgs7<2LI7V|FJiKtvL#qdx6m<-NZK}*h39DF% zIWa9G`0p&m@HiI{{sa>HZ#(_^iLtERdm1UX&8QLsPKp!_Ax1iwcni`JxfJXTqtM6D z8?3a{ng)M>BrS`XeNwOw>;p^%2juqR*88w+7iF~6lV4C$?X#9>)*$0IHJTcTP5~v% zg4AC_`a7_RFz8uBlJ;+=h2Da`Bs{_3eJF8#AZ7V zjSoqSAFMNQScbAnC1PFUDbE4@m{Fz~tyRh&dqdx)U|yJUryJ2 z?W^7f^yxO^Wzm`X*qjOysKRW!OZj>`)Z9!#qECe61yDvFnlz%Pu^0hx_YvzB`_9-` z&ysdN?J=+D69oHBeB0e}1|8E^X>v->UmmEN+6>bqK#iFapZ0qe5;?YEl;n}SHJZp? zj!Yq>K*&;qZ$2d(kiUSlnPNpzDq%Ym6k%{%a)sVDkI;ryIT)0DmoKcWU-C?P3%ipDLp zguy@6a>I>7C~Tb<988@rJNvC5A!WlnRt>`g?@rPT0tD(^Y<^{dO;lhZyiy_(j`fHW z&iDdWeG`m-t=24z6ZrC&$8PkSZOha*#%WGi&-$=TS4kYeDXm)#*H{DKlKS3nRgyuw zg2F}%y2mZB*7>%5SRs<;s7sdL6?Xr?P1Ts=+@M`JXhA=_lZl!wbgb5azULA}ZqX#c zR`jR(9_PnEg-WDc16);3nYD;d_-ey3gZ@g60*KdIu(IrIe8596E{`vdl|~YBTVwxP zDPmJ!=~zdmLem4O<-DOvp*q?cXc^fl^Z9}C{a9_rfR?fE`CW!EsRlKPPXE+*cG5%u zhv{nhcsHSwCI;@xPpeod!g#o+XRnA&P=Ec;aF3IT%)_hs=f=TNXCc0IqXn_mq#xo0=1uF z`F(09P&`YeCEwmw4tMnwdhdP4XNm;q?v>}_s6cEeOk*I+!7G0)z!crdgv2tNKOr&4 zeZd)f^^w$9hhJtX2fuJ9N~Ir+amPPtd+Ql%?l_Tf_OI>q+(2}jU};pc#5>(!vAC4+ zmhyibU3py6_y4zAwGP)hw5gRV%}P`Af;CH9&8sx?z%#Q_DM+B~8_ZJZm{yuOHN2Q< z-hxM|fJ(}iWhv01XvHBjgPH}DR7f2Az5M;}1L1SLU$58m^*o@6m?1rLFKMH0Y4S@< z?=m<|JSbNCGCJRWQ644}zBIb)_Z0gTzS9e|QFSpSf3VJ#5{hX{k7+56@3G8IPyRyb zS@XT_o6*x!%4Hy3k9I83QA1YqUi06mTt8?HzScSZXOa(d(k2(#XB0(}-DJPCfhOWtpZ`_9r_X-B zLR+_VLRtK5f>y5Lq|DW{bJzEsj?elO`v1(3fXX@&+ihuzckeN=*GShY)8l9QI^CPo z5YZ+bEJmKV@?@3e_3RgSl(vo^S*0&I+81R7$bu6INlT+q`)}#^?>xD^Y6BZ_pH}wll4)B z)ejFLneF3+1ihFI;5$n-;ToGZ$-1iSjo4^n`DweY-Qt?4V$IiSJx5x5R&#_eEFx|x95{ zzE2s@opfmR(M(WBp~7FzS<36aZ3~y*e3P_bp%m9(nztvIy~4%jKeOk1)97`5I9Y$} z`E+rQ5^cH>^dsuAkyc*zpV?N}%0F%5q%q{}2JU#`<5usLTVhvaHU?-YE8rIOhTxjJ zeVz9>++x4RF}k@NP2{!ZtltS#@|US$@5Sy<6StRSXL5nb7Ba*kvH937KLpZiz@Yt0 zlN6EChb7s%c@9}YiSDC&9c@4Jgcp*6F1RjnUR=HVA?%uP$2L`MNhr`|2i+z)w(<7% zqyOPP&=Q61Zu*)L)BKQpEZY~UJ)YC!u=o9O$wzSF;&S$j;=IwdLtGb;4kD0j8lQJHARkGq*T`w_x47spS+WIo>KyMD~V0< zfH03H5dmV644$4xy^^$$&4-DpEw`~ID{r@SV}|nV(jaG6IGWj3o*s0GioMS~Vy`2$8)|am z(=BoTw5qkosn>X>CrdP$Q)wpUZ?LdaeSP-*6qj5*DvjhAY< zFB>O~utRN^JuXu0u+Ym8@@o6y^#o@w$E0-kkFEWi@TIs0y_TC@Y2#WdyDveRJLUT? z0sUB9`3PALKkMSua(fz$EY~waCnDrF7vZF(A1&YFv=Yv@C*zHG`bLl3m*MUJ_&P;}ob5VU%9K{%*--T^=i2a3V7$MYxU2&5wAM60@bPVb{CRt03 zs>$1jI|30kJ406x(CZOTLz-Q`GWD`^;A-l$Kw3$Y*CUAZd`{2J%5%Qbs_K~M6vINj za57Jf{prOWMQxFq@)syW??1xJ3ZPL5LdBNibr@tuvyaC1mB~72+tVZxm>YI)aFMoT zK@5nM+ea<5$70`^8oNydE%1))MS{P8l z1DvbZ2!2FAQgXjWSme;##uGWAQcb1+&Iv;#ZEnP-53pQ4aR!0bfySxlmL$#}qQ*p4 zxxv>3BPLzk;h%#bc##d0#OF0@ADX__2l9s@8`laIT`UpI1}n_#WrsUu$PlBo$0^qU z6IFvBw)i9$F=giPM~8d<^znR!s0L7)v4Y5qniO56HR2;HP235N-pt2n!7_( z?iMX^0uWypRi$=xMNpsrCh(3{2gz(87-nAX?r)q7-tepTF~@ceH49-0#piBZvOenM z&v4>?bJg=QKRlO7eixDSpILN;>};V|N;oKv^}?oguL8j2(=4xy)#`&v>}8enk(Q3l zT#`zdyG`>GcvUh(dI&C|-Q95)Yw$I`M8iU1@Weh~c z4L@IZQR(Yr{bxaY>tdtqU3l}6T!b3Fg@dL4LojR<#@!$K;xxE!?BPc*H*)MMOFj3! zaQaBnVErBq9@3@LIL8;^-4EMu*K=WLn5fx+`2mJwUy{5!xSgK=N-un7hug(HO%%=j zl@{CW>uAgQ+^D#Og~HJE&bq<7k6<9y6o$I>X{CuX=5wQ_eAYNl0+zgDbam`D5~XAR z^_1{ilB_L2a@f(tKqUU`YCf%POpT_SI6t(6k)8N@7ROk!CXIL*#U(%=)R5Q4fg z%1TaeH|Ih`Tj38wDil6qhNc>cPc2H)ch0aGj@K)R7nV@xASsi~HF=sOm5NYY;emwi zA1ie330j4p-G6?Qs|k8I#M9DIn|Mcn3$BiIV-2p&#i!^nJdJ-X{77lld04GC+azdh(ww0HM&`)yDz)ODJQ);&yyjdxZWh>YF z{40se4%1l2T2SK`X`6iB{*`cxp0l9ezY8!>4Ec)$0g35lHm(wLW^si!0Aj!AL>uGH zxgG}?3MVv;qd3?$t`~CO*`>T?gt(^%zFtqt0K>vY@zQQ{(`N`xfcgp3u4yMEnQpjp zPl@&>N7W7irUVtZhA=d0_%p#_}l^hp^%Y#JO4~}V@@g$1OYn6<1 z&hK?E%;ZBRjLe5UDry~VD*Z0P=bQLo2GJS=s-pRDKoa$TU=4s5iReCI#gtKsi_ zgz^Xv7a!#w=O*;gctQv>%puxNv@u_i*aIH0*mPaZi~&=rDI}m1QhG2 z*dHdRzpUU;xtDua&eu`

    D1}_2k~k-`;T{P^vd%S{uwgCr_ODZi}AU<1(t}5(^>) zHktA!g~Q(d)u+%4r6uy}(7TW#Qu!eCMI7$$KG>hV*N>iwj>o;Ia`@||gq(aNt9ZGjn>_W@ik(uTLX3S4w@k@nBLxth6XdX9Ov0g?g}Rai zY$9w52%O+7ZvJUy;>S7(@^D6PG!97|GksB0qsq^o|Ca>}L%Ebg_%O^IP;XmCb#zLx zBa)L7OBA1*EcQSD0m6Kwp^e|1fZ$fBa=`@`1w2Ps=wgRex@g~@TRcuUC1;MAv>!&H zHMkzae~rTlgErU}0q9*{v-PwSPKW6Tv_{`k5_en-jQC}+ikmAA4=5|6c8SA6s0S?|b_uvvn6=mXPZlvK z9a`*;D-Wfjme8!Z14HD`0iEsbm7M6O3tIoRdj!v>_QR)!4>Z_s7&pu0ZQ8yB<}%UJ zo#ccUkf8arXb|n&E6{Yj?=ew`O@o|F%RJNs_)8+MjgmwGn*_I+OQiYlt zwQe0pC{uI{TqnGfV$%)I2vPQCzh)ty6McI45&TY;s(w&E*qu1Bhnbz{b|>mf_m z@m_KY;9oNsE7tXRob3Z`=H|J6x-Q!@^cP3OYv;zx!Q$k+m;k@{d3nFho)gFwD8GV7Tm6ent60sVgsi1>`M- zEhMdb=go5f$Fzg>`-<-lV=2rT~zD7CF!}GnctcwOV7|h%44B(HQ&1P z2ezQ6`XBbj*oCEkL*I(A_AlV}FxR9OFjfed+?)c9yUO{YY3F{YU(T#~kpjdH%A~Nj z9U|C|PEd0*)xEmKG1F7BagzmoZL6JA@X)fM7Srfb-l9~Oss9bNSYOb%3s<Sbr^qo!Ynug2Mw$i0c`#8+{@9?9qK`c5zPNvT6g*F7^tj&R=CDH88? zHvf&ig1H6u8*gzJ7=7gZOve2_`X zl$CsJJQBt^;k*-e+2H+V5}3IbXFQnC9cRodeh_YaU9{cTWvY^Y-|;~oy2>S39NP`_ zwvqUy0%qT5RQ8??cL=ZaodG{a1HZ89sigyEL1YJDFZ-jm(q&t8EbvHfu(Pt+$oVUnWL*W#sb|iG$sQgG?j64#8tN+_V_qL z9AXv>RK*M@@&}w=Xlxc-(%^A2YH-b|`}PN9ZaT2D=+aSKrP2c`_YmU)lSPyDPGDrg z?h3c4Yv%Rhp(Oyyu5cA-=@v(1a_MwSpy1|zW^hgsbLU@;Y?adbuvcrmyL3&_z*d0_ z-p7Iw(m0$2Ppz-ZW2ulYD&2cWh1Qj^GXxyRqgY(gV)2g3B?=KV6%PeeLxhwcBZ z+BXWwx5A+c0^_2RY^C72U=%G%xSBDL@>mMSAbv$$qo$|y1!~ZSovCaIChY0Cm~k=4 za%VSg2t=QKo!se>O%Q7f311tE43P}Z8(p;G;kd5LbB+td573O|A=Unb3GuHvtLw+2 zz;lP!P3=R!I&T-ggImx`aU_(n36Eu7!CkuS*$lEz^?}v?BC=ZBxMj(Z()WJnn55-y zWp9`S`SoWgFuC%&{1g4zQRpf`d{dGsW`GY?2rGu&vr}>U&KJ@A{5dQ~qlhw|GM@!6 z8nNz%lZ*UsfSH;&&q;7z_F;D1rT;O`*e^MfvYv#e&#|eQw+DB9=L0tW-mu%^W*=Z! zd>Tmfz-H@(bL=u;;)higI=`1y`J-RHt@MFgG-;s%xIT{*d|HqW1+bt!zGZf9Eul`3 z6NDTRetx5k;;jdMEXo7}io7dn-BUWftKq#-bOB)7=pHmmGA>;1g0Icalvq?FwnE?> zfnyq7e$N`AW8-wiSp~^Z9fjZPbDov04FDa`6!F;_**P_3h0xa{@UrT29icdsqk*+L zXV-;x&ebzgl`vp^LNizOOrA9;;v%(;`kEXwLWzFB{3W*{W?xE5Vj1n2H1RB2R&vth z`X;c&RXUs4WnmU#x8V`#l*v;mbJ-1DXNhVwP)SN~`7Gt=M*n8{R7$HBFcu`}sTg8& zDkq){$JPOJewV8j+~-4M?+voyLnei0|CxClPlaQ~K`FR2+l_e^ux%e0r~IYNM(ezX ztYkfpiHY8Pt$*fJu<5O|JL)DqnP6OS!JI%X+m|79D#mXq+!9OqC@Zf+8OH*C@gckPsFqN=`Y^b7S^I5e~xGr{9g$LAHAZ3EJP|a~zDHUJL;Chpvgus5_Q;x6*kZ z&%?b{%6$+PJnZ-y9_UVBy;~KdH*(eVvgBok_;_P^UTH=xWrYfxc4vB8=4BT6A|=V- zyoWWa+iigO#gpRNaGw;B?_Qg&k#LiVPtE#?GMYR%^3)@Hw5Vm8X_vu$4+*q3H8Bsh z+(Vsa|F$h0N|Z~OiG1I58eUPayZpGn?IXDp#wtwX+)ygGB=W-ki6ZG;*aY&rjJDtIe-ww6Hh_ibY^S=s0U8hhz)m4D#SB;+LsBkaufL? z>8;PyOsL_5O!^V&$?BcbR?hM!Q1uX$R(io%KV+Ol@y@dCY^0I1) z&#?+?h%R9dF;`V0OZVWVA=$1ngpEAzz~8kL8ur=Awd;tDV)n6dLd%NHFXbwcY+M`` z-xLmkq39<2Bl>=A85!GHYY)AGA+&Louf)ePmc5}#5LFXp!LkK66KQh zj$&%x=MYZnZ$P9MPOf|Lg@6vwvGgPO`u?%y4)YjWM z=mfI3`5I47FP0jB$ipunLJu%jdgoC)f{aeoD=w^5>3=Om$f(hHc*RpINt?ydwq8Gb zrCaY3mykX>ueQQf&e9i`Mn3vB_FB$gMtG^tKeN9ysDHOkCf}!+Z*K%}Z@2hrZDb~= zQa^s<*M&}2HHl>;B%is^-M_ZI!wJ_U@{IWcKd!|jKpsz+MHUUdr1GjCo@S%X4Iym9 zs~U;VC{)0|uo$;Blyo1hVR01-MOz;m`)-?X2PTb?sAog3^ETcmaNgjWxmv-JitZhNLp*E( z!<|#8j5aO#i_e#-tQ!!L1dq+32AcE0s9s99G;JWqWd`5^lk=!Ab67xnpTMRjhuE4= zw~fb@2RmnNxEXzfP#(KO18V7W^2xGa^hR~C! zY4IF3uE|dS64oa_CUGh`yYHY6%M2kWhY&lD5AMt=-2Z^A9@o(wBz$1_0QMo;Cdq$Q zOQ4<7&n{aFuRM1K@In?z-|YZXG<}7S@>g;B{^ez-wAhoJ)wXB2A4Pc`HW{tbu`ARS zUPS~01lHXosKn;eswVqHFN!FU6Qb}6(^6hmdl!1u2C>e|lqeLg-NOWb;`7 zLV%`@2}2OI`uf^Ij|~QTB`~eeuRP&|Pt=kV&*u2K4RXlpk{NnP z!|T~Cd4$Ui<>6S6oSN?@uJ<-a`)1${T@#mIb>QJ39(OhN0(fY#GdlZD0#gVu=uWT0 z*#0pBH5W0uYS117CTeMrQ9}32Pg6O<1MDhA*`6aFkAC|Tbu5Jc7sY&g%o&sIyL~^} zkTRuQXSe;MNz1J@g6wx?^e|$Ul=d1ZZdUyfF9cmG_x;E~As6 z9yoMkmG3E0ZKZ)o2fBSvigeobW2Dk9uv^0XW}6ZU1@gc*ro(t5>%NZSm^Kmbn5zL7 zuHG=u2Ys^-!Y!DS0fsK(13n`chpA#qHW3VqOP@WoI}9}&UH(j$DlU;%-3VGbXpddU z7uMJi0ekhc&M$FfdiXOyALxtJ@B3w!K%Vh;Ssyl;(pLnuyUOy*H2%L@Ur}w(eIhjS zDeO$O>gn8|4b6WV-g9S^dvCScNn(k0(b?`T#Q?M`WyAG(WOP4HYVcg~dyMIet-My; zkyC^bU(z^^pe`sbW{D85T@?g`1nmvN}1#o^Iev|NroJ)mK94n!Z64`yKP;@kq0E%fp5sytppp?jYFiRPXJPM4(&&!QY35Mx zX#1325D6?}V&18l+^?T#J#FKr&t@K&7!yh_^V%NI7aM$?5fOU9HCca10r}aw<*e2z zv(x@<>yRp4A2vp4hg&=wKe;5lzriC&^K(1SH!hWyLpM%2pWH~`^y9=K^ZjWLyOt>e3F|j0GnEPAiMkC0pIMd za3NoM#|F#5V=1M>-cCk&)!fiM17i*Go1-*qeN>nuI&}0ING|{EgO0UNEWw!}PMjaf zl$CKmP93y_fGNWGE#I*W;e#kC4kOR>gTfFIuJ43uh?538=c? zs!nuG{D@9s6J`20o-GxOykhAGfG$d$6f?zP3G1WZWB~aq|{0fIA@L5Jm!lQhw+6{ zY~gmR-}GX-k0ruaEAVf}r2;V;F39}mht0IwlhFWx9?X>BrO(fJJU(d1gR9)hTr-5| zSe&`&`upS)-Jo+!;-}8;BTPSI#t&HpnH=*v*p6Jsk=}yc0vp_;#InA)^G!CZ+Qw}W zvVSAm1nUqg={`0VLZoU=I(cp$Iozr)0ZvNfGgZt_35=dzZs%hb>p|XdP$`Oq+4C&j{(is^JrAaV8FT+<6}eQY zX*4)`@n2qUx7O|dM~ux`f0Z39{6df_Z65?@{oXvO=gyw`AGN5)IkCT|uKJ8cNsuJ* zv@o@<-lQ5I-Q)`i*YLUL=l^sN4rXt@+o!n8{5SK7J+pFA<_culD6l@Qoli0!X%`$5 zPfs+pZzgCd>T=@KmWNVL*(;FHzpNfx5<}!St{S+EJ?x@DOEnRb#@9I0=j|oV`Cmfz zCfD!cY0{9m21Hycq>_tj31wGTNgvb2C=!LKK^<&80-m+wAeplvF_uk0Ze7s2_}Bji zV~W4knFBY~(uU2;-=u1#I3^cv8X{3<-;4(5zi5@<`mlN{Et)hAw0JX4E^sDaB8VH8!sB2KYVq4DzZV-#5Si}vGMgE#A)JK%3bc+ z^FQX1qvo@5;5QR^hc)I1JlBf8p%+rl>Bt<}-FwPO1&%v(-a;k&Ctayh3nVaAyEOIY53$NblZz9b;D90p*81SB5{SDIp~pl`1= zIqRcxm-CJy!f*crDiDg}=^)k)B`V6~7*y)%I1dMvN0>J~0On`B9n95MbKCesK7dBW z+(#~S0*U_tadOFKLGN=#L;uNk5I}>9uj1>-s*_<~ z_WWbxq#myLOgxFVSBVcg>LuQ!_kD0c;HD{t<|&;ua#x;rGM=a|z9nh*ug#P`i0!*E z()FEGHwZHMFBKq#RgWRyo;=0!P8f2yBnSAaftq#KyKQ~t)+ zc(Q5=K-8v-Y?&^e8FDJu>u9p1K`u5N941c9Pxr7nLbA|H%WE_=(lX|ux_oo|H6BxI zTU@PUyJt5M-+psPHT^QSht2y`cWrAy`vQqf8QyPj^htsA*O&FoQg(sJw<{hKW%$=@ zAYc1<8T78IXLgG$fNUB1%7j{9nsu0r)-z0kUBf^s7Q;im?m^@(SZO@r$er>B>hpfZ z@l;U>qiasQaZ%`4AaX9kkG=p_ND6(bvwD>M6GIPhp`O3I{zd z3Y)Vv<1fP$@9WdKd{d~MX+G-pAG(`IT?|N`!OOR}#d0o7VN$vlFo~BFT8!$wb6>9v zc@xMXtE617-TmHA#_Ed^k|CccaQd}?8PwK&mKKCvFq$(QB!76%2;0(}Oi=C(XGke8 z_1)DM)@kHr)W})o%`xWoBK&(;YSCp>x6E_OI_M8Xahih_PvURnE2hWFyWSa~F0vnU zW(U5!wIMk_qC-ow{o)F4Y#VZs3KdLm_A+4Q3<)0*2fHj&q*^R%&XE^l6QKkzE59-^ zJ!AX9I_p$VC=D+vgx41U!Oy9|e|*uQ;KJ-~Oip;lAc!>?;u3Xak-KtedURQ-y~J14 zbfbCETPMibL?{RxlxXKLo}i6>7qRuCkIxhn`5OIDkl)))$!;hg$Y2YTmU;ZhaMjCP zrmhE4NSCJDnL&v7H+tEdRb!Xma zi3dLianLeD2C`@L*OQX}@zG_0FRn25*?3YOXhBm%-@?7@+#T;*S_`D(pCd?bw;%et zvct;iRLI@MjLN$_R9(TBRvWx}LdvSnp47ffkyNT9IiJ_dnp}P@bmjFFdVgQC^t9GQ zD6d?n020!hX=N}_kB|SQW2ZEI+pbx*aTf~Cm0Kys$IFSWO5WZM+k$;~kqpV(cXD87 zR`f{%^aJLRd#~I~V17m*{OZ7xc99`15XIY_cYqRXD`MOik z5lwUifjjxAlq-iU8f`-iGJ=esFMN7$#m=A2mQ-RXaHd-C2q>7puUx$O%>)OS!eWVPjNcZm-wZLqeb{6 zsz%t$T#r}Xq6G{s9FNP`uFIC~ja{93j;Kr-m`cTI4uc;3JMZhqpA+=nO(-(@7Y&{u z-(RGq?PkelkxX;{;dCGtg-;d{3 z=ij-;@7~Hu*LN1}M$lVDF~s{V2IsxQ3-WDB(nc&R77kSJw_+)qqLT>oh-0s+FJv1s z8kJmiWbU?nRV&1Gl#flOwUQQKb5y%{7dSx5 zqHjEQJ=ij#CFsW`4xxP6J>mS;z&jOue;G$h;e_w8zA`cc&qD>!M%|Xc@wofn@IBu> zh~O$xbl^Etabqu(S=Zyh^>G|A^l!2~gDJ#`s-R4<4+LL`aoU2TSJ#}Vr;(rpOx54L zQ2VGp{UK3Z@$W&2CT@N!e$7@y`#k z#~X=P_P$X__s7n|+s#1ZLOp+jrHGx2hbN~H_pD=^sHs1aa{RaW%ev^V!#cirkGnzm zSC9`*?1QGfB2283Umir+uyLj{4$>ip!8uIBEJ4q%=r-oT!}r$nVWM+9EXtvMp~drH z4G)SxPo+6ro7Ll03zU+6Uq|+M9OdQE!y7ux&>LdFEN4G-2NH^F#?yI8e&ECKjue-5 z*gfzc*iyvg?fslsUcpxTwtcE9+xq~;F6aZZ18D7sTBa*Y@Y2eP__7XL+lL1{H|AuB z^MOpY7Z-CYPvdTYP~`~qu^DWPLc*W#XqpbT1*w?b&%cuo{cAyfM`1>lD5f~9SJiso z5*HG_$ss(zoEblJ+{4Na@t)o~)?~S>+lJ(5XbDR{M^k4=hN1Uisb{_u%?o=ku04oH zMa_!GN4CA}a*;m7%g$c7BKeDM=u~?vj{1C#46(C!*PL*X^$f`#959YN*k|W~pyV3q zS*3>l87?P$&18x5U?R0i@FT2+%gAwUHXgxneWjX=QBQF!E1w43VXJ(F|7rHp>Y6;- zAf(e8mBO1rk4d1}DZO)8wG+ z@8~I8Q}VTB+v;L#jkMFEDzPA)>QTtaI*km!@XNKR~Z-j`IJU012Ve# z-h^Mf4oq)NN~?BJ3SEa@EaRSWtHe@my^XSarR}(XwTb%9$u1=>$fe|T5^1PX+Q?EJ z@`*dE_(_-{E-xfdV=qL3Qla>D=Xj(4QNY*Wtfk3|FE50O2HrN;z0e}ENmdLjv9jH4 zDWTW+K7x9A=xc#);HQrj{Lz(&(T5*KULd1@Ml0}RvRd|6D_Ga8avm{QbvO5HsL7Nv z69;iGouLnP@<`|J$q=Sr_8Rp0lm~5kgx0bw1hx><#wqrlnuBX$ZQ7`HSR2rMG3W(y zc5PTa$vZ&GoMhDn4t0D#o)?DGSWzw$Ogm9&wF85;YIk2wchmL0gQYrpjIe`3Ea*d> z^f?BFxS{kW?whclU?9iXG})MMs8kt6r;#O0c82T$V0q>aQm*TV(Svn#yE1CG$(6I4 z-m%`dUlUm)*9A!7E#7-Q$S~N>bp(|}S^>n*;##y#dKNvekL!i-N52ktA%1{8;c>gN zstMFd4uCVn!l05g>U-{kJsB;Rj1z&Nhp&5MoLb2Dy3_rqW9xfYUa-E`=biAjJQiT2 z7h7=yK+_k_&q|RF>KQ@ZRFDhy`@b4C%1lEA&-wC4g)E0`bupds`_1H2#0Qkw1}Q+d6|zL7;Vpd+H&8T9FQuI{gEd5V@4o z0k$KdXvq*VQ#(RdO0A9|H>!W4qQEKnDaRJydz z70U?J${fy|&Zvk~Th=_E;Rl^6a+?Z1w!kgNqV=Kd0f6^u9=o)my<2 z<<>~@&7b}=OV@1rpn6wc(Lz$~R%#%6*~y}NNg&*!_w2Eo?N(N-Ho^Y#jrqr&I5TXD zg@@uqCQlpBId?!Qbh-CxSI35Ym4OFu?^tY@1t~-36+qbF`k@2)(JSUMawP&_c12wD zzQauI!UF&w9L(n&2%+Xx&itky-FiB`$cJ(n!UJ#;qdc+KPj$68&+}MoQeTq6o8&qf zJ_udH{bwgR$sqDJeFST<>i&19_J!Rd8qkXqE8eYd7G>$<#(Xx7}hnB4J zNsvvTNFMHhP_nSrcg$nD3CL0oS>st`Z`L^U{jVX4Rll9IJ@>O_(Lwu_LGV7Hg&Ktfq-?W~iU||2*^wPk)Wi-mFEOr#8 z4{sK=n6ym4#kjIsw5~)R=XVW1m~gFkHR)aOf`kBl*A>xlrfjSlV~OBV&ej*HS}pp} zwI`x(hFnq*RC*XCbh+71;1$)W6nCLOUnw?X&HsW7Y#HrDn0-nzu7NmJHpl*i!iADk z=!db_)7Tl1a&Kj|_d+)n=sa{j*3xS!A2jNo8&6suUN4U=$qaBnu{|>?XKjKlE^KEgR0 z*d^bQP46ROFB)O#_D0`bPj5H9&y>gE?q2jRph}u5wa3>!4AKi;Lp%ibTgmQbG5Pa8 z`-PG4{k1~c=Ew0?L4rifdi$< zVN6`nSukLS>nBRNb*^7oaCF^$i9dVanNz9i2&c2g;}s3AL#;6Ba-AFjD*8wvwJguO zFTDb|QPdD$CavGLmW+dz5(fu33?NFE!qq^kG&Rc*P832iD^4Cj=x+YH~JkVn(;1MbDTg*?`+0ut^C+zw}TlvPBPq**w? zHja}trsp3Il({#&NX}ygQx>=J!hVw4AjUg&2(~wi{qaB=eH)lETIhOEKfNfk7%gLE zB~k%bJRO>fdj#D5AWb@!&gd{!7MC}VtikEhYXiZp;<2o}DqmXx)*+mA)(B_zDHs%o zYo>!w-7(iVM{M~cV2h+5Snvg>?Qs>1Sxus287+tOax9cak~VD$`~Fnrgvs&5QM81N zN~EI5ac2!Q%15be=$Z;`a^X5ho?BJozu}S1apwxz_^o)w(bWK6PjXJLVow{zol-%h6t*qgm<8oSeKXrEo6jTULKN<(6QkmsO{Hy%i{x8H}@ALm_^!OUwB ziHb>FU-HHVMgHvi=dhD4C#>BZ&~g+U$$_PVh)~0Vy35NM;9P}T{Kzf};ubQeGAM4k z%Cxo*LfIYX!sd%VP1}<6s6(%g^6OA!!o;oH?ORZ~?F~)@k(i8i&ivcy`oWG2nUhzL z&Ch?@77?@%-)4bdZQf0j>&Qx9x%h%9ozBc*UJT0hpje7_aNQ^(y)e%TCs9V#N!fU~ zjpwa~*xHkTmWpH~ldkR!Nzc<_7(e1EpEfqVsJQ4Qb|5RG?nu{tcrWOt^HO@8y(Yc6 zA{4zl+SbnX&l)wTp6Opls`L5Bwt@~0R*vgpBS{lr+u{3iG)b>d*xYr{&nQWE>ZTbq zyMZrg2gRu-&D|j8{^Pv+cJArQi9`@2Hg+Af_J!r7uxNA6jt=E9Ec(?44fxp%Gh9ov zo?~HBXk^}dzT&5sx6%Y`<5XG|Dm6o>vyaNp?+s2_Dh7JQkmcfAAG@lj%MK=3Fi-v9kCU#$x|mhKmkbM z^puOsJ}@9sBdDz0-#b0-ncLnNL%g92jl`VUd+HmZC+L+kMnLCT%8O?Tobf&52o_oiMx& zmgye(9{Ceh3kNtw^S~vh$*!QR9Z|t`od|2boMw2T!@RRChP|g*K`fAo#SqmH!wK<< zzmv-R**{Pb#(|TRG;26^l-1g#g_n((@5;*y_y`cij_{83OdFVYz$!*wKhML}`}kb` zHdRzuH#AnOrA?NrA*oawAlP@z3Z2R}et!4sFhK`8%((5TbN!)1SV`$P(1HKQl?VIo zLeC?+62#n`Z2n-LIO_a5NZSMjVxn6lxb#@MGnnyboSYnA8^nP1ExOTCRT!X+^7Lb-$o6oLIo@qGE+8Dds)53oO#^yJtS>Xadg3Mf&7s` zJvyl4=~$7`*6-K9Vrt~JS5+FL#q@@ z8uE0A!`{{hvy+xMn&iX;Nr}y3{t-C}WdQ+6O+!Nu?r5A4Q#mPU_G3AGo69%^!t$e1 zFTbOq5YIal9@#YK_zK5s8KCHoIMw6#WQZ5;FRn>^g*8j7c8zV$z=4$=+6+~R|lB3|fmZGdUiZ1)S@>FHt6nN)Jd zXlyqh622}848uKh~jjzu@aq!k!fw=@-~uBis*eO(34=)!?fw6U#!!oo90w zht}=ZaY#s>CR5r8ik`3G_!nfg01B@#rSA|W*QBE}&!^^f-&i2ZE6-v(xf|iRwT>#g z`(QmK7cV-L9PJ{Gs^5h?H4UV`_SVq^e&^GnW=^ymI64BowCX>zyUZVv)B<9gAYyCQ zok~#tF4+Rp1LbAYuND89iF5!=-(Hrl1->5=G<%OoUiaQ)A5;;BX@;$PB6EL;{bByB z$CD};l>NaxE%&Q%jQ79Ud$(6vq;3N>Eh6^z_Nb)r{ZGR3Yz5i6664hWPISG_9BnL% zSJ)X|Ro-`N8wYg}{c4cY+m$XaS(W9CCb7o~`VbXU>tEzejW&Iy3znVHw?wY^Hd(?e z)}ctw?kk>v;ml)M-S!)q#lG;?pLRk-x>|zw!HuqZneF^{34SV#B_Bkal$*@gQF3Q7+gYWhT^>za$96J~ z#ubOOd(7p6;x*(S|H=p580%l;N)exXrs@8vWDlqGpbiD7b^i@1yDq^eme;;$cdt#I zVi>$^i^XnKaU?27vjtNk7d2_i8xGhUH}8(tcfN~{uzvIyq#{_0D8%2O9qQ@r-Mmuq z_UG+$JF<0A#ePBC<=hr2<*-^fnxSwQ3T8xH*Z9>Bp9WWoR(^#BT;B+{%@a z1%C{?`MQGjuq^~aLKxew0o~2y9hnMUISu`YBXm)SqQQ{5l7pHDt`gYj3a%6C*RpS0 zN=E~<+{@}nQppnFhEc&{NE1;fUQ=c>i(9Xy4?A`~9_%F@ZET7YEya`v3IU9JkKyE( z4#KpRR~)sgg+nrG_InrmEmXA|r^;4-9|;{c2h5heoZQp#%OHNR^BO04kYG4ljb4YI zl_&kr#N82IVePsRbp|CDwVvG7fzY82yqPo%5t z2gA!(O$Bzic-}#C?m3{cl!dC7@i?AO>^)CRGaOk;Ci3fpiDUnbjY| z_t?ICNh2Bs9K|PP#L)b#f*e51Cb|84?cIZ8e4Zy3S6`3fSwbt@VxM-TWQIF#V(v*T zKK?79w3M^AFnv!2?YWFgn|#Ob8AW+DIC_6RP5$-3k0~Plez`8o`;_+;7*70$1`D)Z z(%l2%va%BStT~*ySz!D8GSE7a6Cu6?r3)j1vfDkR8^?7m(>C2aX?{T)t$O-RUY?+m zW}3gZ2AGtZ)4IsL6SWC4Vu>KJqVJva{9j{tbhA}BTC^G!iwyXVlAk};9HI%z<9ckC zhJ`R=D@j8)Rv}Wvoho26xQ>-}#Y%V6+y66L5tI2{Dwlk!JHnoUb-gC|V7tp|f}W|^ z>A5r7X60bk8x>u6stG-4>l|SJkN}=spy#}-p!9KxS5&aIGUg!Y;P1!R$FeD_c_F~p z&DBt3PJ5dzQ@mNgFPaqYJJ}t=!pY0%emdwIIg#gnJ$DBlLf!$H2T&z!n(mh^L+Nh+ zCJw_n*;L3jfz~2lQKZh`kO{?Qr>0p?=?pFX?%&_VBK>6~EKmwDz*aZs7%L}gG2fJI z-K|Q1zr-fFs=M`nB7t==OivhG`^GYHW|{GGuyk6ZoE|X&a-ebcA3600r~LQT3I2oA zDsPe_5`Jv%VwvM4k&Go7Sohk7WL}Qq%91U9@6nT)*_joi>GhqsHAx?vp5xz})_of6 z!}w_7;O2yQQy*pH041!)auGnW^uGQcPxwMVbAS$L`z!kJX0!=9iAmw38>u^^v6CdJ z$=1~CQ91*@-}hVgb}!*&2>TAHK)I)F{4s&fJx9uKi9D%gB#wAzhhBr zmw+8{{Uf9k@Sa=Dolog6GUol7gBC&ZYF&!hVVM-I7xsnnUrONSJc!s3cbne8hI-Xx z-Da*WF8233Xggs7!%g0Hlk2Nnb6@z2Ikpej(5(Uvw#)QI#@Wr_)92Ea;O#cv6fe&z zB8;0Xn>O7#^nDJ;e=P2%n+Eo}lgvZM4Ub|nN6*G2O@DdsP3dXTVylO8w+2|@UJ|Gn zo8{9!;D}g2#%zA}@u5Z6>s1gN9Uc7Z5lme}CU#??Dkh(m`u|Ml3Q+)AVLhIPWm zU6x{UXew}DN4Gf#(AxX1Og0$$x^~c72K;pvlw4utxws#`%-0ctK=O{hxggoYWwk0NIR}s_l~~Ja zo32mKiaxGGaY4);73%VaXO0yre+?0V0?*-2RXvo(1q#nAxSh`xEbBP~7M1rUe_sB@(T-ZcXiw8KD$Hl+O+}pFknabd)_@iTUVgU$F z{873KP)Lu@g`?ORcz#s8E49Q|3U9~qfrQ($%SLQPSI6O}`)uEkKV~bNxo0rQtVD3{ z(|4Zw^J@mf@D{y#Ir{@^YLWeQH@5Hpb#(UeOz!_5SDiZNP{*lrBvek3PHqyy>FA_e zH$`qYxjQN>#59$zMbrG&-6sm((FN&kIEDQ;eLvG=4&De}yWvzQzP@!kn*8$? zwFY6=z?qgb;H$;3F{o}_ph}okm3Lq>$RZX>VjSx3^OMVpzC+3v*#7LfJ#tDXR8mir zC=Q13&gXqc+T^M&KR>}j0S(K^Tp)iERu`XqtuTRTr(1w-hKf_*nDkGFL_LC6@b zCF&*Led@h%4i(W#D5(TnnkYZ1t5FagQF`%v^L-}U7GaTBxM%fC;BVPMaMl6n-{s-5 zjwBm-+9X)kofWYm$LTjfs2~9(6&yP_ob*p~i!1-q7U;*JKWtCe?^69!sp-aHb6mluG7YeW3?8RCcN~(&X zBw0Nbq~NT^Pa}~htdo_&97z!2b2*7PS=z&TEaF6z(p)ZBpDxyYgTw9~Y&o8aaIjZq zHI}B42l%Y8+(8r3$^R}=%DO9@ubZLkjmh-tL1@= z#bGK0I1r|5qpo@8K|_-|p6*u9Yj+nAko^FLOs~=Y;m4lFD2Xkp49Wf{yE_N?1>_JN z5>NJ4H9EbdZ&C&Dq4p~3CbDEpuk_1BuKm!mnQJ>sOuN;Ce^jh$!vTcCeZBwAm##26 z?8SzI`nHyU$fVlOUg_68#!!j>=|}<-4n`8b5JzcukGdl2y6wfOHTW@Y!7uyTQTGQB zAmETCyi0Ni+jrh;{~4gOrE1|vrq>y+3X%arzAya8V-&ZzRgX1HbST2{w9lrix6c8` zk(kYQ`*z-Wx?)R{dAzY}TYU$d0I_DK=k$Se!hQ=)YW!j zjL5@-Y51PEZeglE;5>}d7n%LnN0`r>{K#;4N|ZUOv8`VVW}I!DoTdg2OQY{$Y(RCo z+TwuG|H`&q;Sj&*$tWSYXWFyS5wF2?XPx=m1o^A;pmNNpAAK-RZhxU=^47p0=;Y?U zq;1>eXJ)lgIGpJ(beelzVP<0WSG@`06DWE^48?!CcCwSq!1VJWwRJ4|*eFGJ$d}G0 zZfj;swTkI`VeBR3kSibJJgQO$O%;^P^wp=Iza@Oq?#%vTen_mxW*?dR46OE zl@*I?F;3!M1FgzVMdNlKMWb@L6E)tsZNE-7W`g>2A7OK!!zLBH-+(dNt0yYR<#r;X z8fxO^1Yr+Emsd_Aw=`p_)Mf;u5xI|Cm%nV@dIK7XuUe{#m0Q!@3(=SAoI~-LC zTEte;Afo+xceey1cy~1R+kO*33382fvTn9GK|37;w!RlPEZa>uCytmUKm9vjL_j=f zMr5gkd8g!0%$_5-h)!*ypNA;2Kd{-&=osavz<~Xc@y?$B$o8Fi+sb}geWT_*jH&mA zCdeOTbugoGG=@5my~gRyCh`~8E7gY{JDcU>#a$ZVYwhQQO4#$q0>F}NrQUv0!%xIqk2y9I#>)m<^6Yyjmc`eP5+%8WQrpyCA z+IctiFIduYa2)|v5%xln>O(gDfJZP<&CtBR4xPu|J&P=ZrRw)tKlX{}`chkH*WWQh zJj~2g!h7yc6PqSY2rAd~t`GsJ9`9yW3e`ZM>ROq0Aji$$9Y6l%xn+h%vv2QMRaE zrv<{{tl!_lOJ_66$jC^CXC>{uURKTkL+&I*0)8=Rvv0bFN7ag{=S6H=l`F9(a|7>! zjJEyN*f)G~KSMDFB4;H^XWa5nKXGA|B0C%5v1Q7?BlyN7t#w9wc-^M-H|EF{20R`^( zCr{~$!rWQQ`bZe$4?ZZ0&AzD_j|a~57McAv`~Czz8CO5H-X0Q-Ly5kOJw zBpCZCb$HJh)Fn#V|6V`0+V+tKLol>nJ5h?R%6k?1@=iV$dWBgpcAKY>lV^LZV}iSV zK@N;IHQTPeq2>Ry;jD`XN}q_#s@B(aPF?>_c;ke_h3< zNoy-}h{wwQ=FXLtx+#lHQ-I8bJB0AiU36R6+_`*rN|3MO+5(E#w+7C%^Y^mZ>TWn4 zFm#W{Mn$H{*u3^NL0h2Cgp{NZ}oI~?^{3x zo5h+(W`k=G{?>Hs1E=XG<((gy);4dQ1*$QFTU&X5^E)}vvz?ob%HKk49{Og!SM>Oi zdJ%`{=YFf%YB^37OJ%$Fn7=Sh)Cj5A|8#!W@#Z8(YG}8Ecb8SA%^@tB+dX0%92%5P zPy{wWN`ixpj-FBUQw{f%v9p7`i9+%YcIqvEt(E){<&mu7bLXG$T}d^8@uP6Mk|$Wi z00?UCCSPlZ92{lU4D|X3tDYF{=*tDiW=-;?x642YaPL^}AWS#L17xCeDz2knkijw5 za6gTqATqY*nZS%~^i3};QzK^XBs6d1?_HJG*LIR8qEk}DA?CON*9>SsdJa7fA(U_c z8DAN_Y9kP$st-OXF?{+)&GVru&>vR_;E1E^f3-@!Q@~DT_~eGn9BbBmR8Nl%H+f{; zgpAhrCmY5wt7JJdTFDW%%|(Pt;4Sz&oJyccrdl7`%nDRpDo6kcu*^U~5#^4plv0Q_ z*-g*pDTXt9zyFf(La&L%R+Qe$x4fkuXk8nhCaC8UD+`@vV@Fbj(-q&JJ2qAXbYz;s ze>v>WwNEF@qGYpsUFRC5qd`_*GX3|Y@%BEr7L5sf*1wo4D|#Idi>OKL+5VxM(cyz0 ztj05DYtxWgL%$EYcUv6r1S#F0p4tXuDRM~UelFT1OXVcgeiIVagBAWyAB z@9(d&e9*}AG={2>O87LylP%V8Lw1oj8V|h#r zJB|tm#K154#Me9~i9#%KutBUG)Pp@c>?tWks16Js{B-68K~N2|!h4hqj%0_oYVaPZ zVKUBJl*;YdvdkvApO?KTDmh;nd)2;4YutF>@;+FJRbv+8$}=Eo|A*w@;DAFD3d?u8 zaOA0UKPPd{Twp!JVi@YaB_TQ|`;ZzHLI%d8>$wUwy?-du<}?ry`ConesrO-n_Mr9K z8^F9;Tp%5$v*QdvI~-e&;ur9>5^FnUE?o+Wn7tiYySsS3S{Kh>cKI5LtGA(MiF0!S z=>7bwY8toy;`e3*+XBp~T#h6-H=k977ct=aL8pB5nl}s zuCa1nLXNHqZ(`}vhL+9ZuJy5#JWW#D^}H_DnVz^K*FQ$B-WqB&$gTh@Q~u6%dfCs&p6+2IxNlBgX`?6Mc4VZkbt4xREX zi84uKmQcmm^K2em5U*=H<{)|)rk*L!EhdU=5E66gHN0cBOtB*g{c4-`toT~|nHNOY z%#zK@`Z~5Kf|_)AfL8y#5}kfC-f0~uVrij?6ht;sl3KE7PObZwY}gJYPNV&g$wXS? zr=fl8#7@h^0^jYW(!8L1kic{DEk6-fv!?TFT`M0UyU5Ojk+} z>CjrEQx^ZcWDBtQ19GFw*u3en6FGo^0*pP7H-~6KLB)4#9dpQr=bOi_ruMcG5W~4Uz<3?>PaJ(&;e~3mG)d8o6Jy^4bESux06B=ij(W zQ8dyl#mq?pwNw)K_o{}iCfPCt-i34)Op4<<*oMW> zDgOqeqJ<#oa2Qzv6j+IZ?bomCvC7M^6oq5<2A{tXA}%aCG32_(7kZ=^OS*|_ zQQP=r-z+a9&uKm%#IHHz+NzhSLQtU2sq5N5jI&}cPA`~XvP|KG*N;-K!%j^mp_!v` zJT~z?epcbbV=u%!u_*&6SD9rhqj&o53%xM>2=hMO2W4_b1J_9oVxd1Bg1%u3Yi-Tv zL-i)BC4z^lL1_G)H!#Wz9ys%k+OS2d+9?^d9rvhW72{CXYtP~!9g3mmvwPkinBO_N z%$(~ALh9e!{`-!>wad!qtK;>zcB+YEpc9DuJIpdX$3O$X7 z@fr7gS-pNj=Oco}L%^#qCf8MFG}EEB)L>`)-#k-plRa>WPtZ-qbgc9)G|35>)X@(0_GC&^y)}~MHpnKa(Itj?X zwY5YRNJ&$>wafN%eS_Xx!o;{k)q1~rt~hPHYKnN@>Zoi2b()vmRos*6(SHD^2e_K+ z7StFOt)urWmogW)F%dFBm9#Cz1kiFWP02V3Mv!|f_Us`fxn;e5GfoqmTNiyCJTg?$ z!f1zm0~s98KfEFRcwyt754M9xFDu4V*c3WwCa627!>C14_9v!Un9Bj?@9@>910~_+ z#n`2%4U4MXf9T<<`&;R%&YHPGW$bV&{UY3-BZs@%7grWPt* zIGQ``blHKh)ChJLweQpx7)KT6?KQZWCKyz7{)lZ!xQe6!anD9%<;v5b&cPgL`=!O>oB6LbPKd5zoi&d{SbAblJBNYdz5{YU`chgk;BbdvRRJ(_kx}OqNFKR`LWS`2dQkfQ#{$4Sz zO~v{5-6px2Z>Xq3cgE+bK5QnyHxs$b*W_pAI$JjoX)@grtV~EuUmLrlzlSZkd#6o_ z`ow3c2U%CX7ymIv9SAcmA*Hr9Z_7OgO6tNL2xa2k!M{*9rAn%!n3p)dS@wml52}@@ zbFsT3LT=pe#=8*3CG7i3PDH2wQhlP<6006e2WAh<1V6}F?gK*U@ODyw|NW3zi()np zyp!{R-q*R^{$78NofanKfd=%dbYv{QNzcs%ga*c%x?|hLK=!Zmisa37x?Z^}JK$hC z6RnA1mIQ4;2Bt}PSn8)x=#dJbXv})HI=c|7g^HLjHn4wacr^BR;1i@*5E7SqU;a5l zI%K|qgEDni?d)6nq~0hEO+{~^uYS_aJ6@i0S|A&C|6U+AeXwYz1dqM6@zbz%X7nt4 z?&nKa@Aitqd@I5dM~{t}fKZ;c*41(rH2i~}VjNiaW?R4NjOXy)^)Gf;B!dtfC!(KA z`ijcLpm2k5$smfBKuk$>TbH_yEgf;F-TaswY$^tgrh1jkh zo`4+xpTM6s^h#Dv0g`8YJqtAAWtH1_sl21tcSH$fY#<`W_9ndfX#V^8W@uxJ=5P=y z8;>el0``^ItEW$(mCmrq?xh_tlXyW_1}bplE$z2oE036NBG1jIj8bBjiB(U9Hpg-y zeL9u-r%z{_K1@_MR_$`@4)NySFF#*dvcGUk?1xR!CluiGpv$+1Ty%G<5n~9QAb+Tl ztm(`C_bJ(52ut02F$xELL^ibN(iJ1u%Or@Y9q5M!pP`jbM!6z6F@mE!{NT<8^R@K| z=ga#7{8D#0cuMBq=bTCtY(opQAJT-Ka#ZOLX#VE6kOdn==r{s;o3A5iQw!%M+^aAs z?)`~9*zTj+sk0ypDxXo-qGGAZQ=PGl2aXtGcn$mkMpqw!X&Prctu@y1H2kRYnI=a1 zwO$4`T^*+AX>^zRZ|>pjk~@NIuJe3~UtC6m=lbZP6dDvU@BZA+e}W-jw!8GLWRx*vn#snU+crF&>-hgIPyt36YW2a_108#x9Pzqh$uatI zOZDJ`@^dxB&ji(5>1gP6#iY<_TR%~XLZK?Y4IPm09{^!PZWIchsDu&o-n<%;kNSLR zy|Z0}>itFBnIeCq4wg+PrE$1iRG)wYeXu5WFe6?A2m+tU7p|5pSG&E#O_u8B9ahW; z5sZvWNRa)kV*a!W6!#<1)d5T*;%k2>Vi##`L}|^sn3v@sWA$s_52R0dKvjNxKg>&+ zk5oa0AM(EuNrv;E+{pJ*Z~F}k1(#=6~T6exqqppUa& z>)P4A_yAXU7zDX~aGjqt+uUH;$AoN4_4!hUr;S^Htbn6rN&mSY>)5hykS5pYAhvO#zJvh3S{LUYPO*9=!Cw#JHB#h)4xTWW(Y6rVg$U zDdac0LRqv>n_Fxo>QLz9p+arr~QDKTIm5R@YM8u$bKmA8*jQh>ar=}j~sXh4=IPK7meYb&E#-lN|J?W>Tk;8=CQ(zd~XhEpWw*TgxE|^ z*W?>QN2j%<>|#p!JqJa(1B9?IysM~)HFoN+0riJgav6Vs%!Uxe{x32v9!0U zfie3fMh9<6v`~-J*nH5_}{z56AcNe(%V^4BFlQEdt_EYI9Z=n>s!0=>K$ngQRw%C>;FsN^Hk~L7R%{^y+y7`9B>;)H-lM=N2h_R~<{l%f8f1 zLzIFeH=!Fzn?xTUfT4Wb6u(yX)IQXOa^=FRSZDht6+_lIemCF71VBl#!?wJ9Sie`} z)XwJM)eU0=94%J=Qr5&|s0 z^{1;^+TyZGCWy`ADrJ^$5VlrO=T<>!a{ zvNoM2M{7+PJ0Fep6Yr3p$+v&8CV$>b`>Vct&URX$v5dJ%6Lr3TxA{ogGd|5UWiplNFGLRlqoEzHCmsCe|eZSzNo(> z;Y1NJ=w4OW^NlE?DK&cYDW1QOLixl9C0e}L5<`v#4Y>Nx&$=BsW>VD?A+g?zCu%w* zl;ffaGd%}3MhOAJJ=4y)*?#FJKoV&ENYEU4=i`$jzk*#YeUzbZ#Y6=y)NQ?H7s*b< z!G9V#`ljF9>X%qn8B#+2Y~`t9Ze744VKxt1sm{)VaQX*-+HEZ#hyrWxD-F-apI^*T z$5a%q-da@l9@Ih$*l^)lHq6yACE^ufnMx8ogu6#;Y6FedUmo~{(s{(}7Pv@Mtqu6c*vfAbeHWC4_>3L~}Vmw#K@CU4sx&ht_4A-mbp`yAW1X?pO-N zP!SW(dhc&OSq~xTpDVs&NXshSEqN_2r1R&8AqxI&MCYK{4!J$CK?shJLsrNtcuP9? zF-wM{%hsojJ%w-;qXV#*h4MrF?o%@m;T|}`(ml}otg-h6&YZGGr+{hN8!-n2{leU1 zy=FKcSnNZ{v%?OXjEJ|sQXK6_>N`1Ljhn)^2WLjAo{R;D=9F+ybyW`p>^LY!wPR?x zt~7yPP#lOkV3r)2=m2)A6rGyBa|53WRloM@ z&&gT(+1IR9p-?;gJeD7ClRdywkXr+opN-}c+=96i5haE6!Cz3AQ!lyaYw{w+pyosU z`F`pwYcU0GnzbGZ=QIZj;#@)JYTR(2_Um z4$8yWJj_~O06_AuXvW~zPWs(*_aKCGJQ5xrxxczOGrL6wm9cQA)F?0q@f+wLY~=!* z^6WW*f<;ezzxlIXdPI?FnR7uzCp(d1nfszp#drX#Ql6U&{Yc)+-M9ao1xRk>`iPV{ z$|}dI$qCbL1#O${%JLL3QM;w$vei#WvdR5H2rc?Uqd#wR;LF_>nto|@{FFWLQsE3~ z+`BF8Y=0_K$r@W1DKN{K6|h1wI&RWT6 zEa3yNeAMrD0px;UgB@EcwMB+zddCM0X?=wiI{5CGZzlVlvsT4>UNVtt;CWu zJP`CYqA*>=saz)(7DjY}raZ7bMz#Al&~ARN9zae2`6anC77{_*UAr~!Ne-|>+$`}j zoeNAn=`lg+^ohMlKf$J~+FT24gc9zg5{us^wd|HtNJ$nwm`Fuo`G$v>SsX#3cxS^UTcO1ysi-?;0ZsFa}&Hv64UL{(1f9H$PxJ_YvB0amGE5RYP0qBhWmAJ zTyCs0=Q~)j)hp7spjLNlB*H~+*o%c*5H%o4Wv(oVkjlN|pY-1eBEWW~T%42BG3fWC z+5k-{O8Px6y*X+tPcxZSB{xXmrqwR}e#wLPeAd7J=|nv@mQ3n@8Y=)JpQ{xluUxr4 zaj?i+o?5dI(h6p4s;(1z8fzZDSoP^I(sxSJcSx*c@Y{3hBEz3=b8&|(LSq_zbHQSW zdbZGM#aOh~7>$yH^Q&UGZo?NTfJ0&O%WvmkB4%hW*wfyxw+=Q@u6{t9t3W6vEUgoS zFdq&6k}nR!1xWU;9d}ZeFQ910jyY`OvsGjMVi<2vm!Sz*Kt#()3*li zfbXr{qjD$GBhflGp@DJ8vB^n zTMEs<1F<2=;W53v#5t9#IbS$^a-0U?vHQ%7s=}(@V9(^Ar5bRbRD3_dhEqEl7USpo9F7FCy<30z2>2lLpVYS_E^>Gt|pCO5W(&3e@FTIxiVk6@!#TT}mxOyF7J2=DMF>CFi4u2D@B?ux0UGZa6 z*M$o}9cY z8+I}4|6)8IhmEL97I{IYkeX18X)sk<*~z^;UtyE*wGN}=1HfRFU2_K>lss^|`#lkM z_`!qg8yFPTiJbe*&;y<08)-`jfumbhj^_3=tz`77m^Vp(A7Zqb; zg$qMYoE&V0iX?4Y&2bwCJd9#_3Q}N#H4^!fe}2)|7L|whSug~ng3pG(Q8R#=IzU=t zBF<(nrjg`tcxmt(P6*NS3LpyXG$TU$LYS%A&-RZlR>lJuRtYkUN*ghLF^fAz`nn>l z9(znJ>^{=Y2|z%VyZ7Vmo?5ZM3^rM2Zc$L~!adkp_~Gq-t|hp^c#1mSW;Gbji!=?t z{)ApvkDvk;fR!`)h0iu6kzmARGPfG6v*X1R{Jem-xYqAVUL@?&1|63L z%D=`*9dUZ6xeov7tgb@4{%T!MKip4zn?M`-=2{P{76&y$f@a2V%7ec{9|Wh813NtJ zpsQs5k|RQ7XsMkYiKmh7ZulXDDbM@?Mot5 z$dwsl1By6Ox_?T)Q)6j#3#S@){J}dYlCJ6&@X1+4K_NGN-K8~&fJU3e$uA=$DC5qbTem0 ziNz48Z!jno()s@8HG_gZhv*S8CV`6<&t->a-$cCDWw0UX-bU^;NLRmW@-V#w5+>fk zVM@o~UdNL$U-&f19UtD~ab?|Aga;N9@37vswG{^@*dEXoPs0awF717!_vTNvG_F*f z8;VVRS`UNym|Zs?w?74I6E>HMe^wHFHNZ)l9q9BvY2>>xUC^-x9`GCXg2Zy^`Ad?^ z1eG@&hah4rE{Aagrnc&awdLQ5YU@#clmGgb>XihufV0B-JQO@oH}4w9}kvul7mbL)Jam7J2XChYrN5i=0|QIvy?zw*PZ99~mS z-J@?0sGd?f%SJWGiIWIKGSeaM6I6-4Si%ms_090*Yd`z`_;`1ZuQ2UqXPDk5H>ZCEIYl@t z_lz?zQltQkg3#*r4A$2B;vYZM%*o#!YFJK0^Lcn1?HIVOCqXW5MM;kRV5D2ZXV#f) zB*Fhx%S=D1u78+X%LP$~=`ABZevZm8FNxg~>qJizfTB98+li7z{$M+eUHKTd#%d}2 zh&38f&8Lp7@O#H10md__gEWMjRZBGO;!2ro+Y+YEl8(rA{?oA^YRf(S41r~&pZ70$ z(NhRc;OMFUe!zJN#Tw^j{EQi9MP*^$ys=9X4 zV!8GC##$j*929ltHzZSlE0swrR@j3eY4LHZz^qmy=dgKkm8O;mtC6Q2M7Q0beS*ac zNV#>aNhS>&NU61uL*^|4UTcw5yHlKPhE@{c4efDvng@;SE7u;>W?$MjXT;v{c9KNZ zE#DiS#vvgERUWhZ)G)$aivC=S!!L8V?34f1|7bT>l>K-E@0}WDIh7ozc5%Hz@7r-q z1{*PBLUAf*4+fjsCEDQnRb<7E3*45GduuCD(C7WVH^uImTZkOaOiS6IxSwPvB*fxHCoGB0eh$B;H35URT58_d@6Cdu@?8X}V1hv>%2dpIpTOCI=P5 zDE=*X_X!ds2yG?aF5uHfYENj!P+C(;$c0EgzJ@d~!T~B7kgJbx6@3YXn)kOuxs9JLe%yNHJ4~+iv%Bsu{2maY+!oxfRO||>vP5AYdM2Qkz*@ok8)7o}=#TpSWmfI@m zgQ8RPwTy~)CL|Ni&6nEf6CfBtSe2L?pevIA&-}!j7C3iLsTfBJZo0&xXBX;>cMRss z0@m)^_-YRdBpWShLnhc^(Q$XPRN5*xuDx0a+7p|RwYfp?Z5qNk_H*8f02y9M@_qd< z&Mw$c51_7A4r$L`KU3?0US9+`J=t3e0r-M&GnsyA2L=B-9u>VjNHbPv7@73W&jSgv zQnW`%ucd7(Ydh9lOHlk|g2*ZR}KGcK;$d;sQFD*ffQ( z$!8N9E|Mc*<^>#`F&DAic?G1#SeJJSGL?1X(%sKW|9WJicaEQMA0dDCBF^BO8RDOcgZ7@$Cl^*m^Sdv@$5k@unmmOv++f zoPDpwi)b_e{hzu?LE)ZTwUWnv3l96#QQYR1XbyyknB!zkd?w6W%1^C&0P#cM1+Vus zp36B+@F~1EmCA|)H1f_b*Q{a3>wtp-ax5hF`hb1`iVZr8O22guP(B z{3JcLONpu_6clGD>&g=_o7hm)t+L-0^4eY1kK%U9#xwLz51#ESf6zK%(g(ax+`X98 zhujqGuhmLd&g*p3ILwHHM=;BBq`_Psj0(jIJ7uuT|6ukq=;Y#03M#pjTK-6Q{wC{Z zmPwM+hty5V67m;ek->7#Kamj#=!1_@6>-Mdz#JR)TpiTS=4r<7x_m>lIvRZEG`B}H z>Fw&hcD~7~{SEwK(oX>mWPft_AQMaUH;2p7XQtZjMz@Ss-a$v^&Ih{91fL5Z^!MoU zR%J@s(bYT2N8ElQJ=2aYNiZ^39gNqrf>Wm(jbib8jly!Br?57HXI8 zJs9T^g@GtlfN)@oHt)CsB}%vV^$q=ZsB>u}4;b~ET~gn=&IK_0N9ux9yyqd*orgQp zMA#P5TyY&J6sBuS?U4>Hq=?!aAE}tLG0O^U6le{qAJCdXkJl;pmsn|^sUl`PPd{y{ z18H>CQcsoGPr-t3WcwT6{zaLKZ|_-)q^`wlpepYVF3uSQ*at00tHE}RCo6kkiYY#;WS`(U7+lEp zB17fJ(1_|rqz#5~zH9V%upoab&F=@)twvK@SQW^=Dh)W9U7a6GfYIt6kN$sQ)17&t`j04?(6zhwt>4aTjDr7kc2&FYD0Ny+jsOCe ze~13-iuQQNsM1*9Rw|J_z&wGmcUa132k1hrv3JKZL^FAN*Ro!K+PCVutdYo#3PPcR z0Rzz_-DF$z;+iPm<(Q?KY1}KK-NB9O9%2@|^%>!~fP0N+n=M9$2ljJa0O#BNfN`u` z0I6WavN7_3q3q)QG)8Hi7G#~wCUdV?$LrkhhL$bu?*LS z@sCP)@Z7OyJ(&`Cv7YUk9Ls@X!XL9**>tNAt-MP9`3p{6R$pCA-%L-TFcq|<|1~#) zxyB5I#+ddzyhrGGNhmp%+Ir=hzJL$g`@G>%djvNLPLowu*_l3ex0X-QI$9`}7$Z!d zG8bYkEDEY)CW;`1D9hQ&6)+-gjwiiqo+`Pjjj;$PKJ86N!@zKOBv}L^#)-OuBOWxs zSSy1mSLg*-kKUb#4uUVJX4*Vr&T?co*ESI*W~x?N_YZf-SjT-y&1)Pdg;wB1QD4cM zIcP^;i^kF&U*v97YO~F^R<8a zihsF(U{Q{{GT)Njr{GB6NB&7``3Ovu+TGn7KQUTJ14ztLf^`_KOU;u>>YU86LXt>K zcdy-oq|I@-4yGZ6+YWeC(9|Gg^(??|*DuQme+rL4z2~|=7e|r+Dl+trJNs-A07YoD z8SyxPNA(IS{A`}|t1d}YTq}dxS!HDE?{xpN%fHx=XkTbA`L=Vhn9sXMYNjB5{qjrg~HXg%$q7tiiq^P9bHar-Zgds%DO?N9;l=y{a6+%BmZTjTIg{Vw_Ou2J4Z4}Has3R_!FHC` z02|-;!#r?B$4Ut2*w0%UKkY(CNK2hxVtENE)ezfeBGTG^@crv~;a-!(<}$96@Sf+E zzHFA+;v*JouB3`!4}ZWLkIp#}eYW+| z=(^2z_us8!yP?o0{F76HmKTYifrXM`9+^N-0}%V|dj9=TX*r_#=<8=8h7CBABk?hx zJ~^*Ot-rdSVi%7O$*QuW(Hel6w9Nd56)xFOQ$FWto^QY}>qrxfeIv9YSn><$o(@t- zCp!lh*3j~+Su2Z-tmKYnVc(m-6`^XS>n!OTn@&u_a5Eh@MFJk*vFT$|<;As75fpU2;aQA5QL>34p((>d_agur8yIU}|FaZDSTJxm z&ss^nJf9})D!1EiRY#m*dwc|pqsG#aV1MX@jI!#0M$jurM?g)ejvyrko8KQ~ z5@FD(;&ZTN_?6Ta9>oCTefqg(9C$xi4`*5vI0Q4*@0OhRygaZ+#=@?>kxX&^G@Y$R8fI>K+Tgw^)IC zI-t@2ykW-cdh#g^wA(Le^s~k@Ww37qIIl+&{Q#2%4<&fty9S)p2sv6H*=wktW!{9w zR{fg#z{l1U#v=QAnW(r%8>oQJSLa2Qg_>|5z<#qw=SV9}&1k1|jP{&tW}DE=Be!}F vT$PO?myXEP(-FL{0YND`VPyG@0mNhuceg6r4T#-Y@6^FN14Nip|4sZKGU5nw diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM.sln b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM.sln deleted file mode 100644 index f6be6b9ab..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM.sln +++ /dev/null @@ -1,31 +0,0 @@ - -Microsoft Visual Studio Solution File, Format Version 12.00 -# Visual Studio 15 -VisualStudioVersion = 15.0.27004.2009 -MinimumVisualStudioVersion = 10.0.40219.1 -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VCOM-TPM", "VCOM-TPM\VCOM-TPM.vcxproj", "{137D2EE5-E1D6-44E7-B11F-B082EEBD86E3}" -EndProject -Global - GlobalSection(SolutionConfigurationPlatforms) = preSolution - Debug|x64 = Debug|x64 - Debug|x86 = Debug|x86 - Release|x64 = Release|x64 - Release|x86 = Release|x86 - EndGlobalSection - GlobalSection(ProjectConfigurationPlatforms) = postSolution - {137D2EE5-E1D6-44E7-B11F-B082EEBD86E3}.Debug|x64.ActiveCfg = Debug|x64 - {137D2EE5-E1D6-44E7-B11F-B082EEBD86E3}.Debug|x64.Build.0 = Debug|x64 - {137D2EE5-E1D6-44E7-B11F-B082EEBD86E3}.Debug|x86.ActiveCfg = Debug|Win32 - {137D2EE5-E1D6-44E7-B11F-B082EEBD86E3}.Debug|x86.Build.0 = Debug|Win32 - {137D2EE5-E1D6-44E7-B11F-B082EEBD86E3}.Release|x64.ActiveCfg = Release|x64 - {137D2EE5-E1D6-44E7-B11F-B082EEBD86E3}.Release|x64.Build.0 = Release|x64 - {137D2EE5-E1D6-44E7-B11F-B082EEBD86E3}.Release|x86.ActiveCfg = Release|Win32 - {137D2EE5-E1D6-44E7-B11F-B082EEBD86E3}.Release|x86.Build.0 = Release|Win32 - EndGlobalSection - GlobalSection(SolutionProperties) = preSolution - HideSolutionNode = FALSE - EndGlobalSection - GlobalSection(ExtensibilityGlobals) = postSolution - SolutionGuid = {C3149E18-AC8A-49A8-BEE5-BC5854EC0506} - EndGlobalSection -EndGlobal diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM/VCOM-TPM.cpp b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM/VCOM-TPM.cpp deleted file mode 100644 index fad3053e9ea611a56bab3f7da038a9aa71ed70b2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 13340 zcmeHNYi}FJ6`juo`X8ti5J)$cm8MRE1TA1mwh}1xwqAf%c1xkKZ$zN}K z&RibN+}T}fS<0x<76iG=-I+W0aqeRt|NO^;@E~-;4`DOxh23yJ48uOIYhe^F@acqa z@ZAc>VH{4vIj)!Ze-&Qiu7mG6?x*1c?k~b5wz$Im828hx-3b5B(Q^_`W52^l`xNa* z;Sdx~;`_Dm+wdE3^B`V%|GP+WgkEpLQSA8{s9fRx5M#Utm#@QTH?6-5kHS;%x)UB_ z?AKAINjSs(pYi=3?|wjw9o%h&gOImAn7w(1p5I1#JJ7-=bTPoUkKS*=DQWHFcM1-S z<`C_FM2jxCF#UanyWWh(n<(>1cop?_gg(?D`-<8SPtG9M1oDaIL%hF-?^j`ccJ~GD z_%Y6;moaEjCu6iSn;n4DO-MEf&v4xYZv%X+y|pw8&TrqrNY;neJpza08x1#0v<*(K zz=z2*!2Ka4yMSiiLb?;s=|w8n@wWq>`FR3c&{{)WcX91t#7TIED=l`7FLm(iOmg+w zfff5<8|@FGRcQtOqn!+CZ^2EnQb~u>iI$$hevqw1bvBmJ?n=0aey4}JaYoXfiK5WqiV(Fhlp#G0QN;iCg5AXT;Q}{A^gLy&e z73*l<0}Vzod5T(kUC^Fa(X!`gJ73$@^Vb&0A4IA{VEqgTWPD^KWVA~*G5_vjY(B4x z2tt^(tn(F%FT2o@`N|%2#`r{ZPVhU=W7uLXaz`6|4=#w9DSYz~*c5W|D5Pj39C->u z(4!}meRm<@Dc+nw2aN65a?KZ00*3f!h2#bhgY$b=>d4H*$CiK1Kx} zp6fCqT|^F8KeK<8XL-NIysdrDMGG6-%VzT24}U?+waE7?=x{W%%mCiHjXH(1h+X_{ z)Go;F)Y8K$mf2XYZ#hG@mb`YghE$r&WSKwZn4HJ8LR z_aZ)PkFS@A6CPjXf5}?nAY~8nybrWbQOO?PWY98W?xQ}^ETNBC+Gd<-aOThnzu=p{ zAG-JD=+fv)M4;6bs_M&8t6HLr)u)owa=VWLeD)OF@8HAQwp|AHF{gdjmquT~J6U6N zpefE*SaH39^*u(bmXLOG8Hsd8GD<0|tI{D|%?34gJp%JM$*9WO)qJRokfPHZDW|Z3 zMF-;5Q_1x!N{dwWz8>vh4JFM)N-T-Kw6=0nl{X=36*$j%7oL*e`S-o(WnExr9~nlO zrUws}4(H)Z{MB1TZ>u?OalDCEJKU+Y;ZOf`l{O`z@K;7Uwg0rGtHWb1S+zotT#KMq zbLHC*%DGB^=6y{VRjyGr*g@tvfuDD4u-nUD={9Gp5kMx z`hD8y5SO~%yQ$cG3@i_($tX}!gD#m=zYlP=%$E(gy zw-7luK>Y}Gewrb(+-*_(QRGkSnjKUYoF%l~ne*BD+T|6E!rU`~A0A_W&t@8&%jC1P zQoHJz^R)<99w)v&HNC8%4yT^T$vNT)cTWv*K3-U>l0VVdfIQpVTBBMaMeXQSb zzvLm}dfF$HTav7>^ek9lU6H{ z`&8$8AE4KAr;+23L+-ZrasMc;<#AP^eEWPR$>TUHTaUlWQ=~>|N$&u^KY}8;r$21h zw6}dOn_0K_ndUmVx(h+Q8oF|iA)l)=A14oO{Lsg&_OnCpKX+N5HpfQI-wg-G>k!Cd z%r}kLPIl>;oNYDjR}lZI9Bfu*k!ciuj+T8GJ(ZgEnVkDPHZtG&_@Fm7SISZ3aV0+U zd8D_8)=yIA@U@|xC*YY7W`F_W&QG|~*X#+`b18Y(#o!H~c@OIjwt{3)nC)%1@jZI` zDl@NeE--?p?b~|(m~G~@E-Ck6seE7dHrnmmv$DO2*{|%=RNHz^a`r{JTv(4zdHDC#rjA~~~71Zh*T=p2ns^K|p%vxt;VG`)yttX>v%d6k0Zon?Q; z7sGz;Js$t8(A!rbX;wn1n`~n5@)e(^mR4bvyjS~|Ev%pIwB+@Mq-Hd*`h8xOXRB3w za_uO8*_w78ZBf2NotD8vK(gQe zeY^e)>Zj=2$|9U^^1ePltCCrnWsGW0XAGIY&z#3v(Q99Ob2dCe=0C;!m#6vC{y*rp;>;)tp5V}(q;4j diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM/VCOM-TPM.vcxproj b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM/VCOM-TPM.vcxproj deleted file mode 100644 index f2d4e7bfa..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM/VCOM-TPM.vcxproj +++ /dev/null @@ -1,163 +0,0 @@ - - - - - Debug - Win32 - - - Release - Win32 - - - Debug - x64 - - - Release - x64 - - - - 15.0 - {137D2EE5-E1D6-44E7-B11F-B082EEBD86E3} - Win32Proj - VCOMTPM - 10.0.16299.0 - - - - Application - true - v141 - Unicode - - - Application - false - v141 - true - Unicode - - - Application - true - v141 - Unicode - - - Application - false - v141 - true - Unicode - - - - - - - - - - - - - - - - - - - - - true - - - true - - - false - - - false - - - - Use - Level3 - Disabled - true - WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - $(SolutionDir)..\external\Urchin\Inc - - - Console - true - crypt32.lib;bcrypt.lib;tbs.lib;kernel32.lib;user32.lib;gdi32.lib;winspool.lib;comdlg32.lib;advapi32.lib;shell32.lib;ole32.lib;oleaut32.lib;uuid.lib;odbc32.lib;odbccp32.lib;%(AdditionalDependencies) - - - - - Use - Level3 - Disabled - true - _DEBUG;_CONSOLE;%(PreprocessorDefinitions) - - - Console - true - - - - - Use - Level3 - MaxSpeed - true - true - true - WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - - - Console - true - true - true - - - - - Use - Level3 - MaxSpeed - true - true - true - NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - - - Console - true - true - true - - - - - - - - - Create - Create - Create - Create - - - - - - - \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM/VCOM-TPM.vcxproj.filters b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM/VCOM-TPM.vcxproj.filters deleted file mode 100644 index ad33d7c04..000000000 --- a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM/VCOM-TPM.vcxproj.filters +++ /dev/null @@ -1,33 +0,0 @@ - - - - - {4FC737F1-C7A5-4376-A066-2A32D752A2FF} - cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx - - - {93995380-89BD-4b04-88EB-625FBE52EBFB} - h;hh;hpp;hxx;hm;inl;inc;xsd - - - {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} - rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms - - - - - Header Files - - - Header Files - - - - - Source Files - - - Source Files - - - \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM/stdafx.cpp b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM/stdafx.cpp deleted file mode 100644 index 199d498545fbd6c05c1fd8ba485b0767ded7365f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 592 zcmZ`%O>4qH6r8ir|FGz}dhbmtr5CYKDPChf$VyBkMl^q3oq3B%V=3}{yZb(7-n`td zGtA&{M1uqoGF&i4j01lTZx*R=Le007w+tSIof_oKZ}{d>GFmVzVdTh{9nb3MXt`zU z7BNp4HUIxsyLCb(>63`Mw6H7LX@tp`Gk}D4m09Th6-pmE%}`2OV*~{CLF%0_5yQ!U_-?}f2kGr TrizNa!-PQ-Z`*!+6JmV_0)J$h diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM/stdafx.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM/stdafx.h deleted file mode 100644 index b93ac60846963b6bf993a124f00b671367569b10..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3116 zcmc&$?@tp!5S`B^{tp-YQjE$E6%$1hS`kQq5{iNn(j3=osY0)oL#>2=U43u%w(aiy zs2@yBb9dX_*_rp=%+B5KUrVwifm}-}9SNl?KjevAVCE&Rz6>OiOS!>XjQ?HCTxO$0 zM%lg)R@^(nou0<(Etaba57+WY?#n&IW_06g2oH&ThW`j?=xM0qzQ&Czy#?5D0Sw$n zBt&}y53yqE>daTn#K4+@!x-@cImb*ogTwBO)Ym|I*?#I!BKtvUqD475iz)j%qfQj=w9@l;m9t^dCU&hV=&aZh}#Me=&*%@H5&W;vL{whwAU}%lr6S zye3YHdga+S`Ue;dke@5f%B|i5FypU;i4ps) z^>YgT#a3sq^4DBl46-IP;Y-&d5$1k@dg8ZtBVODWd8$;+a&>AVy@&BN`1Cwj0 zZ_h^q7-0`zFuQ*TCX(wXn10Xzj^%*%9q*1^J!h0Q|<< zM?&y$_x>wnrb|uFu^VMRvk3X_cv-N!>@%;6{l*ATCER~1D{|&B^wnY2PPwEy84ZfgM0Kr9PuR5XSlzCsRcf3=37!-7$pn3~=A7H9*TsoiKIdc9 edkBVnYnsY0;+(fK82#_oA$-~Iq69w8Tlo)+w&CFb diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM/targetver.h b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/VCOM/VCOM-TPM/targetver.h deleted file mode 100644 index 567cd346efccbe2d1f43a4056bdcb58a2b93e1a8..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 630 zcmaiyOKZYV5QWcL=zj>fEfw0WxN;+co0fK2Vs4B9U*sm0{`t1wOo&Foy0~*EXI^K{ z&F{}p2USW{Xp2p>*G`#oJ!s%(q!H-M(Ty4fmG}kNtEQTB%)V1m=}BwwfWPvrT#@e@ zH0NG}74Ao{glS)#QXA|NYdIfY7hrMp+Ji@H`t9kzWx_SD6;~Ri;cvXH)6CO{-I1p_IJPQ#X=r zigZeSqQguJz35q;zt9^Q_C^^>*mmuXUCp&pw^fPoGX+dho4RCrySs7j@9_UipWkA5 OQDt4mH~x-^Z~X_?9czaG diff --git a/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/microUSB_Hookup.jpg b/simulator/ms-tpm-20-ref/Samples/Nucleo-TPM/microUSB_Hookup.jpg deleted file mode 100644 index 22b5e577eeac5c0b6a771341208c8a2068464c96..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 858243 zcmbSyXFyX~*X{{+5FHB^P*Gt}snUXqf{m((lz@O3l_DTXR3wp>SO!!S5s(@kRB956 z(gFm?D1u6eg(jpB0TUEWB18x=g}ZUynfLqg{kZoYIGn{kyO&j-wa!fc%tz=qS4S5| z2nK^e&fo`{8CrP4;Zk@g1i86Eh7bfTgft;tXda+o;3mVCLTcbSAKX>2-+s|c09_B$ z{x?rMOy^(v4Qwkk2fT;P=7gF5%D)W!-v_h!MXv<(=j-9n++TShNO9x$f9Uxi3oU-t z1Kus1TWI+!KWKNMexcPb+8EHYJ)FH3gB!N*+_}gQDEw#`1|71|X5-Pw=&0FuU{t^Q z{_A<}R5<#gDLUlhMk~|prWWQ9WU<|R$FA)byDZE%n%nF$x87x84M7{O=KV7UwTP<^ z{-rP6*!^LeK)x&fM)57Up;7{4+MS*t>K8rSGJ{{>}qan**i8Aoaid zrS>>o?ce&z>2v-~uS%c$FWs2F;6H7Fl}KOoANn^ytN&Z}dHTv<>0rLpI@053+nNjJ zMXf76?N=Y>Zr@=IrKkUwe)vzH&9`rV2>VZ+V3i-L{j&xOK0ciD4?XYm;nuKs|*zH1<%=an7u%quvG92Ucj3-x{x%_;@AGz81C)`UVz=b66E-&AB(`O zfO2Z4;MH8v)7d)0AZU&S82vwaU|^>Ip(nrz_=g?`x&NVI;JnPPE7ngO>eTr{6)@=b)$ml${5y`jx&Oq<@B1|Cf-k8?#t958<-W$9A*mJ3e$(_!er1i^cDI9em+7f zXeCSwwhOic1_wEo!WO|6!dTE7r~_(;UO)_}2U-hT1KSI;2YD=Ed}svfgIpmvWDD&9 zKX#BOc)t$j2y=k#0c{Atdlpmx6&6M~v>0%-02l()um>gvCBH$ly%+{#<3LdN~Q0q@f49d1cZO{kM`T%Hu9SjX}1i+5KDd&?3HcW=1K5pr)aj8CDGh{hkOi zrTwQ{D*(N5ySbIaK5MwS$v!K%jfs_wIoxE&KF6IVaPxzX2e-p5Ev(^i2-+8NOD-${khi1!a{+nkI%*L;D@7eTa z|E3GT8UAnjnt#(p(E4BL8lcXp*&^UF1NUs(27f<)17Zpa26yb=|NmM|@Lps4-|4}i zKM?mi~ZuU7V z_2>OB5_jY2Q$c4p21lQY+!%BU6>{O!MoZJ3J5i{Op=Rc$JD?dhbO2I=!DfH|bIqAI zXZD&uckY~d3+69aFncdtq_Jq>LiL3U7N~2gt7|L<*Mdb$mTE3uGE2`^GFyDM6!=}d zaKXaa9RF|E%wN#5g$q8;`#cA>8B$vYo3jiy^8&C-2%N`X7Z~8L>z}>9NL>SDs09lN zn=?lZbavicAZlR=v*LX2vU$rlneUsw!sFC}&F5EITuFPhP;dX!XIh@`zw29`zHoJs z`l{7y)@uK5ux0BuLn~{z&5oVB4jgoFbaHla_3}pe_#X4~4+;(mJrfol5p^*di@OvP zd+m?Jr0X|sCZ}iI%goBo$<2FQP*_x4Qc5CMRoB$kQR^ETpSQkfYk&Fbbw^isPjBCc z{sGp|@W>~=VD$5svGEDXkI5K7aW>j|HdBuh?vHW#P*GX^);hTcl^{`CaSuh4<>K^sR<|ADvKhj`hXWsp6joPL~av|WAc<6D+LHC2>sht53VXhhSbDtZ1R zS#1YnU%y#hfY4p}Wd>sTYjqkMoO|UeGpUQb?94iXkNiP7%3YcpAWjfxPm^`(RlK=r zqG$_)x1EGP@AoZxuj8;GNWST7>{QYB3g>vY;u+{n#470rW8YEU_89+tdaLwTos{j+ z4{f$^kbJZYh;NltnosW=Kjho1vYF0*=Km=+y7uLD)X1M7UM<-$#{I7K8p}9|`m|)p z$0KLE(Iy?Q8v@Rn98M|d3HIG^A%$nO^qx47)^g9}@$0CD>_6!?;|bedn?1TST z4#vKV!ya)p&4yJ@k|kO%N11La(s!)rt9aUbKlcDS1^eg68Axk)AjLG;ak0pR zh+0$9kTLbv1n-DI4*MMMeE|Pyt*KMdiy1}|f0WHY)lG3%*bNcKd@m*+K!vC#=NC7v z-tMmF7=YffRC<7r=-qsCbG<~v=p{|i8sFitzfuxx%2ULqJ8n1>f>qQ86gWJjYUlWk zq+#Ds29$foTBxOMG4WOYm09HGwQ+L9wqkQ;E1K;QBX2p$m{9Z{e>iDCqoZ7RNXfFa z+m>eIaU&nTAi!V)snJ_%^-Z6vse({>@9v_gRX!u%P#p?hj2|Hr(Ug8Dr7C|& zh8>^iNmGf@p9ab7T)&n{?ZoCL3!{L;U3xQ+Mgm{2uf~75Z*F`Wl6cm{u>+48=FqvM zm@DM9!A6$xJhSiRR%LTF9@Oi$O2b%d&oLxs+>(<*<_?0ElXWiY`1LZv;0zR-Hv^f? zBL(?z*mVjgu@J$#D%SD zd2Bf^autimEt0@r^~jvr!v$BxDE6l z+PJkVlkt&CE}OtDb}njEFsNe0&6cAbN4UKjHsX~V!s<2F#UNNT-x+8_u|-mdEuJt` z5+qQG{e!y*ON307(AB`AeqehQq1Me|usll^P78P=YYD9BFEq>WUd~-^T~EX?rTCB; zD726(?+A|EUn!-=_k7V|pnV0%;fIv#Iz8QJt^CfHgUH-)pG`eBojv3iMybs-)z62< z`_x6Ff)LEK)}E+$HcS`-b6JDOF`f4*+vr}#WAQV8Toc6WrEsCAEX$UPo!oG9xsfqSA}rcr6vKSKpSJCJ6ENB zF#-{=KAp@Cdl>kJA@i;+TW)7zCzf0B|8Sx4(cyHtjWo<}ZX98NInU8&SwUEEJ1;xW#hfoR zs=I5()s4nWnTJ(hEdk3Ne^?p*?pD5~*vJ!&;AXN_U0uS7P>vmDs4xf|(LQ;trzO9x z;8BJ&7eiE%YuDw+VR_QJpS|vu7`@sfJPQRqws7vTm-qYSG(u7VGWVW#T0z)@C}~1o z4x5N$O!OsX>(sP!2(kBXcks+!tArce6&giG&K;fCm7=X0bK=>D;(4uZgv|3aCCjZX zn6s?~$xLU5!DxB#(*Y&l`(oKOHtF``_Do4!->v)|X3SbLJT*9%J<)S|Ue%+OgS!354gqV7I(J#!iMT^Vn?23200piUbzcMg3yQuk-oda}Ee1g9A3%K70P zkFt}Y*x{Y#N?u;NV{lqFRyhM%Z{Z%#&n0DS_h}cfz}i_=s5vRSCDw2)WIdbKRXNx$ zR<&QI!=2=G8!pomXRu#n7mC1(zxSXfl;X@8sK~ZcL)U(=0Np!?4?#8``C#y2x!FCT zPhr|0#O!IGeA+0N%8v-nNeP(7DQf(moz+;%Fc8uLFia0JbYLn+(K`)!i4TB2hlvf$;GL*%dkcdC$;idvVdjfb{)?0p}+b;WnsHOjD2P z9y@S`Uy_oGa&O2E5ms~kbNxesDg#+qwPuZ00gJs~(IhPLnBe=KML+Vc zQnbuK-?~SRer}NS`Z6=N-L%r{9JE6Y%|MsD>XdymP)k@E4(_Cs98TpQ7XjW}*n4x4 z<+@a5Ux`sXGph*0L&F-eg$VhJ8A#I^y)%f_=`>EjW@LRbV7WcFQ=5VQ!g*R+{6LX; zHgcdlH3YW zf%G;{7wLs;}XYJ+D_G(|f_@w1n2u4Z@ zmepNTjz!dQ`(^I(8o_Z>iPZjw;ezrq^ULkLsk$yp6h=8e2}Q?=j#BDB#nXk>o~!S+ zgbpUt%?6P}5q80mO0jZ5-fB$)0!@Oy_~%J34a0qOxv!m*DI=9MSFMtf#;=w!sp6w*Rq;1fz56T`%p{d=Ub%A# zV+O)L40~sEA0^qPTDiz*Sv&2Hnvm@&*2&4w46kQP%*MT>R~cYCHt#DpCpHNiWLPCD zf`471UUU~GK|L!*83)+6NsflCVK+GPn%(^rO#1Vtaj}Op&(vMcrp9_@A-R=|272=4 z^_$pzNkJ1Me72OXjmiC5i%VbyIm2h5T7|vv^sO8kZ{L{=obC%cwjd=ni$RU*&b?-l zrkd14A!K-o2cyTjr2sBVenb?6g3S>Ae0_PwM5TS3l$3AjoFnrK5O5#Vm(+>Pru~52 zT3-_P`FP=b?Wca0wRLp_7N$Mj`E}|!)LRA8#7%pZ@%k1o7sCp%NT?Dw@0ildy;{*5 zNXM-dzKj)Na`6&NuUyyaAihs&zc52Rxr32PoF@OleeNhK!c`8IF3z_Qh02K2VH1k< z1>dRPm0PjiY3j-k@?MMIxMdx#3MTDGq3+jesZaJfzcq@^WWvWouAMl`d2;$736}00 zn}x}iQyTxQc6>JkxVO}g{JR$oE6xlz2tjaZd|$3=ay>-VHzx-xC^YPzFXSyPk`_FwsWV>dE3oGxgP1AaY+kVKh1fvRg32g^{_d1v2012y0?gl*F5u-H8!fL%ZPi-`DfNa!+MqXw+${ zx2ri-*HFn*HSfGo6$NGu+8N4jNaZ5fM?%ARCJOt}L-GvqoK2&955a0nSDxPT6#EN1oYcpix>F)IEzYY z^O(t_dJ~#5F9ScoK8yCx-+b}2k(0cApw{<6{)-+@w23KKo-IZ_uC}z_zx8plQnUKg z^W<$6T*{V>>)o(Ix5ou6h?e41-$la~_bo5|3Gss(|7126xHr3(ad@8T^QrA#kc%LYRF>gmgo<39Z{S>I@N3VO`h%?P{D5ymJ_@UlGWb)E^+?Dt^zTrF}r z+X*wrJOpDVVArFE%lE^{qx=n%`4#=Sp920Ec90PUBHlP1#Mvb@O<(zFo6pXBd9>-wfvl_DhYpd$E(WnjZJ5T%ij#?#B%oE zDLQ74Sa5ZRy?^%8>Xf|GYj*c=%H?f}F?brfToujgXb!JBL?7MOaQ(5+KE=r@jT^8l z{xwbBoB6})c3h^Zb?6{@j9ERMmnFb@)TiE)mYSd!2kw8B-}d!zBf($~J$BWeZ3fX^ z$pNccCbqrl?jsM5)eUK{nt=koc4O%El)JB&-Na^WR`$(1=R0Qqydi&CKgZ?Jy% z%T6m>-Xxj!NYKW@d& z&SM*}U$W1}(_4=qR+ujkC9ujD6A^dtlg2hT&)Tk_2~@w!=;lX=R%r)3J*L_RBxX{w z&as0g5@9rEh&1UwJ?-Pfsmz*zCVS4;4cK8Cdmn8+?wH*99*u~MFIQN}*Nh||rhL0N ziZXXjt6L9LSlci;4NjE@h8Laty{X=>!cu((YHFGE%~GwW%s>yjsDrP7ArNhHAKgu5 z(ByRC(ca6b5zF(mC`8QqTpf9D=-De9KA9`%gR0-HeL^Kcp~$A1du8pJ?Xossk&t^h zRS>E&p)_Qr@Zi|4=ZEd>2O}zwvBUSSc)ymUW<3sFOn*UXEGFU*2yjr#eK@Y4%Dvv1 zy2qS8HL%&D2_?m&XCT){db&H`eoqy9ce#u@K16fMY2&4bLdgdoI}oGJOZ~zyx!6RX zK%R*sLqD$@LmdgZi(ZwY+I~Q zHR+_co|!1;VXxfa!G+Bc*1%YfaCpO`fwd1$Hyf0dnrD6TjA!1Pf!>j{Tz|0GKzH!0 z<9sx+u-+jfe6(7whZh|*raU23E5n*(xy~|dcW;tFPt>g+w1u&E*<)G8Mw7a1#)JUV z$P;?D)8Teg9Iq@(tA5=Wpz*z%d%Gnd2rHf{W!Jvxm0gne^l{hSUW-SHk5)x~=6%X>v|T@sHf>X!b=py8zSq`Pi)4qF6l6%(?4s&~=|K9*8|+3BQ8^b{dD zh`MS5&x*+|Iy?hqxEZA^jx;l-;eldOWg}9F8J@2%b8LVP@US~@AL8w}wdOI*zCTY0 z>8%ZCli$ZUC!@__TvJTwALy+ zrNzIn%+p89gG!k4zWvxy&UWV(`mIG=mU%0B26WE&$bmvxWBWtbBH%`cRx7SxrBPd+q=mF#z&6LG5tQV#MQxmGaPl5; zW4`$4(|B5o4_C>8;Ke;arpIPrKTl<{=&?zGw5zF8^m09OKMTT5a<`>^xDErE9U)YP z6O#r5MBUh=$Qfv_v8yK$@H=Re9um1s)54?W2LxrDXwNUQ4G z1DuUCf$aP?w?;InAnRI+!9q44T9+~k?~(IjFQY$Iws!@Hy>_yAHVjwx;as+=GTH6f zw8}8>pnjT|o!ZE=VIDY)KaCH;WJjA0eGq%Dr{&C(1&H4Fl-|uWY3Fuw*OE;Jk%kQb zf+-Bchin-|ih=IWU{NITJ)md-$zyQi+ame~+AEyFb#31b_Ej@2Pq9yrFbf0 z@6NymWMGZ*S@z2OIJBK~++-&q=B-k)_u`t4PUZwya2^YR5TX%)T~2#Nb>7YSU=87RJo)*`Y` z41?JLi?;g6kl$WRR;~fhe4i|no_xPGLP5vn50$L{%k9}E?jgZi{dlnLi>{LMiBSnG z?E?+R%$TZf50k$vR!?IUJ?UGyY2Yw-fu1eli>F-P2Iy&dX*RIP+^G+oS*g~=EfX`|C*E7>C5pKgfo>Eow zq@`Q!dtYCZ`pRpZBxnZOp(v0YMMW71oAFX9erinPHrmKWG%XAG=^b}Rghw%{0IqQl zo#!o7X$P5OrU;GY`(h8e@yy&a@qtXmZm;YJroynSrZ3}l;3FK`Kad?8&rnz`+lD-) zmUUb=TOml@UK2s2qGT;1mX7FS!q}PnomHkYP%a)A=X)17(krESp?(BK2cR)+2lD}@ zF{EqJ9sgGcudNzjVUH-OCdRh24HDPOlI5RsxFKzd? z>@c=cEROG?WA{A5QoQsK>{PiRn~%01P#K=*tRrf%U#q@)2N2)9;dYGhjXWzE8^q02 zk*L_1h`3t8swljvx1nA}V3o#5*0x9pKv&RQetL)WK^Gd6cXOqcG0$Y1rfVy8&8L&V z(z#jM)P`v1va5f3DOzh=zFH`G?T;nvvDYSMplGt=r~XN91AYXps_DBeWK+>%qP)i_ zCZ!%Fqkps|jnUc<#M6}#rU;hv%|erxT$S*^=$d*xz*2>z!cf^h6nnJ*GgNG>K&u+iTT_j-J=%J=8&!aF=WYTgXgN4mSBLJJ3u#}z`#hLeDg-XvF>r+>M?_Ml(?;%RkFl&CViYaEl9 zMo*+SJNO{j1`~FZTDiGDH!H*0q*N)%=$oN;wO!y+&bCS^X)6g)0~K<%t^HE_)=>1( zXkDHwx&vPB)MxudU$XT~>Gztko5NO10DjB%>KwRAk_gmSvh`dgpRJ&)WAeroWsJ>KX^WTZ{*pHo zYV;XqkaM|H#ubm(@9)^ec^DZ#O5%?6QQYh^q`@Qda+US{l#RDEE;idF@Q4DkP4`V- zu?6)JS-QH*>3m(tV5O3GuNUQX^v({IR|8#dy649(Qdf_J$Lf=Nchf__T)P#rIe`&b zKlgOjscBd@rti#Lw7B%e;t}l99bc~xX(Ib=h70YrW}slg0G$-VPYY|>`{qrx#Y^o++y5s@*dC%9LK4QS* z=BE}Mi!3(H7I#sQjkxC!7KF({wD*nC9~@Xu5uRpBjKF|GNZQM&x^n9+M(g9LI+}g$ zp1vjHCbq&ip^;VOS*HMt6rG^mD#hA!0|6>QZFEc(xC0GPYhh`&I5cOXaz$(fuNe`a zi`HWSR865y;yJ$mmS=q?b=r@RR9$J1O+L(^i%}TYLl^G4*v_S02^xfmkdy**ib!P^aWxdE4y_a2`lpOSd?UJb44b-6 z9gd2ZABd-gA@=xAhoL&R<9(3RnmY@^fIrN~zgM&B(vZ*f&H-Q&-OM5l9!G_s0JvE4 z($e%}d5!&`|J9*e7C^U|yKAQwanlD}2x*F%Ua^{w6!iscVW!hEk;H$!zxq5wUL7#f_8~h*!&36nP?N5p3$jpQ67yn))i4ry6BBS z*01Kjt?YYjo0+ii(i|KR)3mmi=Ui-tMe+ByZy zX}4F)8^0?0dHSvIrM`v@vKIeE`bgpf291>-q8uEOW@T|-pdQdKd3G|?N3p^mu;sI; zm!-+3P(MrBG|5Kl?^Z%W)p{Bp=yQAjiK?7DR1eHl-ZvnB9IJ5lt&StqBxEkxMPIcJ z?ekJfvVebr^M?FG@gce~gj*=%+wf93@7udMxkq?XLi5+desu~SPEJn*2>NAYW{U(Z zt1pyOu1UjSewl@D73%jpwXJoh$9gP60`h6n`jTxEKyJ#%$PUhN+f!mxQf{dfo$)(i z;IYdpxXLW=t|+WOg+BO5Z5{o&n`7szOUO)88M}brA|5Q{?5?vVOq0`{Y#7hvoehQI z_RT>4eYWEAEK$W(vin&w^5c$M`gis+W})QJ#OJRk>iDCAV&hTtg6}gB&-*!3my3~- z%RJu^FP+fBmRmR)GZY6zLTOQ8SwDstZIhUGIk0Bsq*joo>aE<0+?>xZ(%`?$PsV^5dfb@u6ad6|v#H1()r zHuw|QB?9v_96!<3I$>!E7ZYb~g2J>v&tx|oKyxP)HGPP?-`0Uuzue8{9~W|XLN6V3 zzof?UD2ygJsUs-N$u|>;eqdC!TTEzxf2gz_Wxk+}X75~=RGcxHhb7VkkzJ;6AW-)g zhK6Et$rXs_j@%7%P;Kk|62jQhJKNq5(UUIM^O}JTC@Koo-Oiq%j;lKta4z75dRwX3 zIcN0<*vn6@@2K=MERaoH2u*LfAxN5!%R=R+ zGBysVEZ8)2nxJIcnf=QhYkKwi^jD03b(Bq7r>ntBULN5U}tuJB(;lnYVC7n7n{rcxSJU5{L$;=c&zy zbCV@BEXTy4;`p(2$54I?MoLf4zTOcv-!Sg!%M7xOP4K{0nH$4eBn=ppS84O)84lsdg8)mzJD~*7o z^1oHR>%H14UAxw=1)Ldm1wGULJc}ZYk`QV=jN;4O6$`!>d3|*WC|%fjY^!dY!aJ8m zyUzR*-ql`!28w!k)z;K7IY5@PuA?t&KB!meN?U|FcZ6&eFipdTQ4Q>g_!{6H#0&z4 zw0FzTHd%{UN)p<1(C{JtDcMf~DXtBHU!|)>y$9!=F`-6*4Ii3#yaI=2y9nkZr&sZ$ zrE+G6sBJmyxf_tOz{`HQJHC0s62(@sY@}b0q%>fr$a~!$A+E4^Lc+zaAU+ELyo=iQ z+q}PpswQ`oavs+8l5Z@!jd}?p33`b5DeY{WVjeD@axg#P>4cCBPjuf1Vk?)j|(w)16o3M3Udgi>g zv{mW@dsa*nlGD6_>hM>M1C^_Jm(eCh`C!GXdLYdXPM3uoNX%&?lf$*T(5=A1m8#3n!Arq?{OAFGV0)&){ z8Gg9Xclx|E!hU=8c7%-1qRfjQsGAS`iD$lexNMi*OAz*2z-R<4xmAE6%4;=Rg#B{H zME8hNZuUKsxkddr3NS9hWa$lc^4fa|y`#~~ol0SS64VM zLmc@MtZob0Okc@omDU0oERxf47rFxkp=)FSgqr-UX7c<{LOI`}I-Z7~=rM19C(>qC9m0G{+Z8@ z-5SDcS6(=IIBD-5r12_P*Cl-F`jh-t8I4 zrp<)IZGC%KVOKW<&fm0#u5uoVLdEa%L zJ<5`Gbh2?OTelmqEev3emw!DDGz<7`D}9%_FJV;F*xJG6rk8%3BtB)^jLXqok-3md^FkD63u=qXX7LOJiC%KwJ0>e zmt`mBawt-KZFc-ylV_-oW;;Y=xeIwWW9h5GGxcM1{{qdP>?JS0zgETdq1_+#9{IEA z^@!xIBeP~nsvmW{@%6;33X0+YpK^m7fXSue9QJHWKbW}Y)j$d%#ST?`>vc7m85tCK zT+c{+U8q3~N61{0WrX3;Z(<ew*5cPqiGMT$&BH6R`P1EU>$>J5H|vV>kF-~lF9sG8`HpG_ zsB<4s>ObOlBOGW0d4A0Ulk2lzd^I_6|^)m zo8EI!n8tF6?=`|RbG*s%_%q6T#%$lFs$T0o8)8gCvii)I$7~edlE$x@J|472cFCYQ z+yA@imp;{7<%Y0*A;Box^>a?m%YCd;tm<~Zz9 z78@aM6(t67H}q!Qv2V_+yy)qGAo4LoA+qp$naL@oI`E4(iI{P-?}Ad^3FFSPr;#Wc z9!Z-dnVB$~?kj+L-hf9vf1KhUp6S%WipySos;+8n<#M>pzoxb}$=!HkzpvPoRS=Di z6gZmHW?r{%JJKU=dDrP$ZseEe=xcPLjG^#eCo?V()mo$>RemCFW6i1Me)=H@o&>0K z-jlvz(!`+%Ynkr@GLIYa=lYWeLf_RG4t)MPA>1(e`){26At?`hr(@XOp*gSEsa#4L zN9(v5!`oEP{I!xdT(0*>Gr2nEO7*Oq>+$_9wV5jLk5x%hL6m`d#+xud*UB7vbXGaC zG}&b0RiRxUSL$D8@)w%Ul|_VS2BX;U#!5ybsaoqR5OLerQ604I2{EGXyn`7G`)E1{ zF?w?-ftAiNW9HLbcn_DayR)q&R4_V?53EV%J-792TXtgUxL3+wkrB9aJZqoE(@cdi zy>*gQjM;)?BKERr0vWjoU-+nu?Fzi)htpa@Iws#Tjs$Zz4`qf|s})_BlCKr4X{y#8 z27ZBlApTaH)DV`x7tH(kZUx81qFgz)gPY&Tl#kU1_K&r{Yw*w8aYNLpSO77V z!h#ql18bJH(`K3U;`6 zx`NPDLtNzgi5GW8f>uph0}OGp$UZKq(08yNxYusZNsLUL)^updL%kH)#KwgL==cgi zyv130gU-dc?qdGK1*XBA{j|;9xd##i#S$7n6gh;PN;Knr1VbQcZGwx&=(y>;T-Kgc{Aj>L{mpvm!+v3D4(Ll4mEO0+%kd|ew zZet_&uCjRmf`^BSLN)}=q4L3|-ZFT6!&caCrhK1DJ3fwx6)UjBbs=^6O#mytX&`vp zS;mVA+j1}VrG)Tj4Tzn~=7*NVB!Zygz5=u$@_mU%(Wx6eS_oV9)pIv7M$V+lypkUb z*kZfAZ!3k&BcHwcZxSwbB3k?d8MRk9+V?xONR~;M+)QkKR=&mOIR$qq3Csb1XO-U? z6h>^y^FK3)*aTcd#63D^JvvYS(8>{c?wNr;TDceuIt}`Vj?|u`o9KSESqc!?uBRS) z$SlX-8;~^TPT&ubN=buAu%@vEL%}Br$~;_xnt46@c6-_UK5XIBMw?|%4PVy+EBr{W zRm{Y9-wVJvJWNeA0oo%E%p*x~YHNQ6=Cz8c-^%dzlAuXiR4@O1N`5GrHs;)iG$9Pw zW7F+(p8!9k7g3#kgh!)^6Iht6pve5(0A*#~W&O1H>IWT6=d!8`b`ghe?#}5E$*7(c ze%U5KZ+@o+;1K^LM|0tpyo`v%-6H?s)CTWl>(Ac)W5BVrCV@9x?D!}EFJv~}?^@o# zs_8$)zh%QX*A`gA|lp8WpYy3V!P z(bg>z;nbr-Lwei9a8h7r*pse$dQ1zzP_Z{YaW%kJ)$qbg%or23yWkpnAviM!fGOQN zet@3h%&yCPfICO@BLTJNi56j?v_e1ZgY;|zQO;}i>X=ic@62nX=>Vt$E<1-u^$0FJ z!zs%8OG8mrLDN}xj)K;G#b~hIVZ)g@KPF2*o$d+}iB!4~CvZX2KIA^N(2&5(Ho$9) z%yp6Z=AAuBSi+?b7K_a+GF^G{aRC}=HT39-5DTsdB7oF8+(fj;H$+d;0H1x@yRp1=LIyuG~}c)n6BqiT|! zI%s4^8Sxy512;gi32&`d?nziJ2$7M}M&F$F1;%_tHe(q&1l7T7JtRHF;h8a&V~bz) z;)4z87F4Cg-Dl#{X`Y2>%)+m_N1N-j7KDbDht%#VPmV0lWELcV*tO`46CyD3TjBSfr zU}PZKmk|Z5nBv#94JyNw^Ex9Kd$HF*(`%df8e+ZXP%sBCbTY7u1hMty?wCRN(nqC@ zqD^(cf^*$#(rWSYD&r~PfpJ9HZzwr~rYtUYlfRNocNb)w-Dn@z?CU0_RcCVtVVu zXtXD6?e*MrUThJ91q|n=+Le(uX!SB$_}EZg67a0xP|i!!txpit?>MkJ!4BbWnEsoSrmz8mAh!)7}zT#G*ZCEPdQ|{N>=wCjyOM2A#My)TZK(>YZahq z0l?{ToAJc3f=7&Y;@=nu0E`PmFSqS9NNU5x?$LDt>&CShoY z%6es#)orE}U@qjq7D$f?(9%h)_sVbN4F=Y# z_1}tF^HOh%+(cz z8LeKE^Rp@awN&>Kau}J`D38`U(Hju8ic|iQ>AyPb_x&}lz-`YP^grDuZ|;Bl)o-A> z;y$7yyGx5T&>Rc^7o|4LiQ=V7M8r54*#QzfCTuD#sp; zuW-JG{Ejav8at|d{L;H7tIONRu(KlZ$ih$2UjuG!r5-mF1@f?u`^u9Zm3(}VqOb=M z#J07iiquZz^p>dtn{OofdEM)ce-_1*r1%?AE(y`O^J;qz#D9+;S=@Cw2bSc*y)*d} zgWdfVcWj#18|T}ePbGZYRx*~CJKb8s`f6im{QbU>6{Y0#5W4I=x5$9=@%3g(-Qt)X zBMWXPERq}G-~F@~F8i+GJZ_gwP!?&uz4G6Yv>~}WI2skSo&s-U z)273GmH~HrR!NV5O7jjINO$9%s~lxIU3#noH>R;u=-+xUq=O&Q%?6~VTn3`J>1=6l zK*S_@{J14J@n$MphZiAr858AON|yy{r971qKzw)BhmOx*C1%WK!-^tW#2g6-RvaR~ zf0}ZSf_fAYR#22;By@Ie2|!_yjdE<2GUAVXV6R5FH*W#oO5`tDb$A3w!aw zdZ7ydZmQ|n@AYyVQE5_fV5KZuUVBKum6-M+haPEd>OMhpEPM>&C`;R(v9C>3%B=(( zcC|EMI-IC&?IkU}GlKhU-)ZZMUI3HO4 z>Xc7nOHf1jSDRB3pq)G|m6uGn2%Y#(zDN)b9OJA{8RlvCdc)V)tQ6O*Vl5ry9U5BJ*f(*I2E#7ECEwr^@?>2Kwhdk5HVd7ocVKvYmLu@gB9eQQ~j zrcSqn0`2VVevfq>IJCTs*Xr@g<~;SRiHku%I9o!{vhI#TY0~+mkY!cEwQ}BfL-*~n ze4BCLkCtYCD&cGmEQWLFKQ%q{BWXmPx=Pg^4_RDnouGs|4lo0=pKn%+k1o3vr=}Xm z^Ys*6+iiWa9CXgp1f?S!J0BV0hR3JnxBRa@2^^RWA=h?DvK}N-6L?uEB~ici3~V2J z2)@OLSs~c0NO?Jk$xF+Rzdg_Jsn08!yUO;!w)EY)*(gZk9(SVK-`epshzptMrp_Ou zfjH}vX*fa*_T3!QHIQwV-)Rw6T}5fLe|B$^~k*Z)?FeQ;QKL`jtgbD z_?~NF=rCCDQN2hd>(pJxCNqX>z`4?aE=$ zw(vzYpZnwMk!dadYCfM2m#xN(TN3=wp7NvLvX7JZOr{{}RYLQt)U97xR~@T_$5C8v zLd5n?yGfUhx&!e&?I*q}qJ5wGK5;CGwnzINi!TRGkv8ifd4V$TTxvw+xRFQax)(Vj z!{0HvbPyTfgW@Cz0cO7$FuSLPy?^v3iPmt|)`?0igt-B;VHka06Pm!E((@s(i4xB^ zqIYBRBoBPRGEgW(P57kg|L$&(A@6ql7} zH+0hkY@kL6ZXGi@S7P+>KlN#KzLv?B_F;aNP@@NBq-F2KZFvFOm*FuywLz z;%S{PmX+>SA6Q;XXFYCzpgvCGfEaYI_-bthPo${b{G#L7Do)R9efAchaKE5`duRHG z+m-ip=MrA0ieKGz6hNLwO~u_N=rfe5uX0wWc+!#Vf~1@D{S z@+tt*FX-fS0jD}$iO^M4zvZaRveJkbDwzszXa?GD!=MUEhuW1_z;`z6Fs@1h7v~jC z#5d=+?p^rw0ozqM=91KZ4g})O2FnnYq2eimxWI#R5`YeBArVkYK;+I44uB>mJ=25h z#928!Tq+RpE4wqIXb#V86;t)E$HF-CXhMqoh5SZS-m z#JTmHhx3c2jF()l$A!+0*-uJxG*x}9n*~5=g;ou^bIDanrp!c;sRUoIwG|Jl1y z?=HE;ok3NS(frWU+qxmYV^K7*cf_OY@IV?F9e&s+2hEleK3Z?)Yn`WFP;R3&y&dM( z-5+S*MUH0^#YeT~rFC}>;Q_W^gs1~}O4U2NpgimxxZ&ea%jqg#0cQBI!?Kr3AuslU zK`&Q<&{Ar7@WITtZf*DpqF-tF(yT(jWTEATWw+T{tg_EO z4n()zI%f;~5#hd4REL=B{B#7zka$+*6YX2U5!ox!Gwpq;V$|jpsD9Utz5k-RPQa|&#K$gX#SPh-UIj5W68bb!E1LTq~2+a2tNa4iINg~CcX z7)&k!at-}uKmF*Mf#=sIgmR{v#O}SeqK2Id7loi0^^~J!lo~S-xIn<>dT6zTKc#{1 zW28}@#wSg2rhFvL!=l=v1o)%=WFs=2xCoWO!-t{fLS1R^vR9@6-YqT8xOfSe*~V_Q z=aqdcS8NW+cpZvtu1gCL@xi{R8mwIvAT*(gfY(9qwp7k8-D;}OeQ)>GJMvjTzBDuZ z!*cK)SZmvUTArg0KIGy0Z-)d{=}xtEl!P&#)Ts5$1`wWiv`TgX&gU={R(v9w1A@E` zDM(RkZ|b4aZX5@(5h*QS*i=PWT2ni6sF-XyDW|m{MZkvBG0NLt6f!zZ|9ISMBxr+p z*h^y5m)E_>&SwOTk2pLxZ~JP#%J?GSlm=SyPu|uNqt%P8M!WLpro+C#S%#O6c&b$! zQ8osa1CYEYbxV5Z{9e`ME}Lb-3v!|ocs;9E**@uk(zi=27!y?>K(gFAC?GnT(^0PK z-P1B9rX6N!{U4IPJ&@`B|6ixuIl7(d$dPKF6R8NfO{J`xTaxQ0x3kJ6mTi?xa#@!{ zMG~6p5pv&LiZKkU6xpncP^KpBEcM0G*m936; zjonhFKT%#KHG64~ziW`jm81IAwl{iWRw~HTK%)mK(%2|XA+C|zOa$ux2zrUyfz>G* zyX%}Zin3-111lCpj|G!0&0(^u)yrKI{GZMmN69h-hbaaqF)$@;na%1M>PhL)C9`A+ zc0Q=D?ZT{jEAuA7;4zl!!=eADgV4y`jR#t%E|P&}i_`%`JrQWztKu4kT@P`zMSm6- zBC=W0+3AbyM3`BKwLhkGGdj`J(qoW_jBe9&A0Ga6EYc2`ERRSADQM7J0FtQ<`OBxz+|E) zd!jeX2m<;iV>5ZlxJvY7@A3#9tB)~Ddg*2yPJSbrBSp?8@yP%Fc`{B|LrM2Ldzd}C zZBC%@^YiksJJna8auPh@r5L%j!E}ereren{+*%@~+oRsIAp6}577mTCpCNZC$h#J# ziQ?c)Ikq7F<+kZzFe-X_i>I)cck4#bxrn?^Q`< z0fr}_*&ucd71`au-xJme9m9!gQWhl)v!4k*7fsZi!(LD8^oChuDj*Bps&z%CQV_4< zHq};}_fKeeHB00^eY@Ht<`unGac0q&4iHPjohdS*an238QM8D6A4Qc%uHlNg^JCZ5 zXRxdHteEyA{uNAZ6>>GA={n&dyCL&K?V~0#s5mp!pJ6$He5L(rTXy_csn7QeUdlSnJHGP)M zPkIst@5IlM=v~EMyNH5@kx+#{?jDVS!5eoUN9&4&ABQ;CJ?d$Hz6J}M1Nzj^mw#66 zi>WEtsQVJ1vzzi+Ib^fV>cR7lqwk?IF?^&dUxKiOm0A!du5X^N=-Og?!+-w{=_ZUo z{{o}lspfCXoK8?!nwjrfBh=08gcfrjb)Wcv<~w>26R21OJaW?Ale|3_)huf>ma3OJ%VuZ+cS9 z5w200^GrtHo>BN^r!#a;PVU@2|0mi6v&K1u%_d13pIXkEZSFy=OlFf?^HQ{C=PyjY z8+(ps1<|e*dbAD(A9Ocus_{C|n|aF(l~BDv;_>mtd)^yOT8^ii5pZ^M(#nQ19MX&! zj)ln~PLGqgYW7ow_C<;AH|(F0?xvp#g-wEk8H#b^U)ZNTO^@t)?G(Q|Cl(Jl=QC5@ z+M3per{yPD5_9WQj~eA>rsR*d_iDp=0EM~(^X$j68tq@Q&G)b8?9U3%A-|b7!L5S& z_|tG0;xT2Q%PP*0`(>Omwxa22I7uUcN8eCytJthqRvLAabI8i2(WLvdk)H`3xTXoQ zs=k$)>KKa1o1~3xXxk9h&kD8w3Z>VWon~OX@tN>ql4$nx);fOb(g8NG27FA*g7EIF zph+~Cbq|}7<8%M_to~) zPZaPI|Jf_*0Z(Id@=uQ^-NbQRM!D(<1-gyWSL;8-2L+LY^lbIZ%g90N3|fkczDAi0 zGY-?aYk@Amz?p|ZSQtu&qM2k~VBFR=z0c^{U9o!2GnZuE1T(`#mi1s0CEQReLGFcO zRsfAx#)Zp_{dOn9I0QjtMq+Dp!V9)P*o0A!SBw#vM<%ljCl_W$sfP6nW?mXUL3f7? zJxq<323mM;%SU5>kkbm*N+%1$OhJCAub>)KkZsIn)JzaD-(BzuDQt%$!0Ph;m-=Bg z>K0A!p)#2`Ufryxbm97inm@e9Co>Ob6W(fgtCwt6(fccQ&y$-k_~+G{V4x7{F1*Y$bG+O)lZ&goAKWrxPD96{M(o(TPIiNEy-2Qe}-d8Yunr+G3 zL)i2m;G2O*`L1hY`^AkBesL)O_RPQFY~ZL ziXYK7Py2>7|sR%ihcy>|NZM@Q7o%XjePxOeU$eWGa z#INZ;BS(sfc~Ys0-fLL?ToD!cJFS>S$~z5c?Pc4Jd#U?HTCOu^<_uir!yB99gUHO8 zS2y*E1N61OTRt~B4y{Vp0V}yaSVW~$XBpfp3QC5FvqUsjLHVct#aVGcTq3jPs7wAE zt?8*GN#A7PIcrPye(7hot3Ix$vpx{SlZ7*8XP7eYHn(;cVa@v^&lRnig*8LQ$}oIM zZ1;D&_xQ$=*=0*+q|gF7d5NH==q(B}|KCm2k8X*(Sn`pTFj?hBFaYQG59;Hf06&S6 zHC7t;Cwq;fL*npiOX-^=2}|N9+5EJeD6BE|6M_+0v(V)61OW-8(3_B&7L(z>9j981 zGZ~o_03!5sH3u7q{?f>|^BI~(<`Kg}=f$`ock4$1X+ya)gkW>4o5yy6P`@SubsjVw zD2F11onM;|NAp8#IbON|%^P5LOC0yGS<+W}q(1Fy?G^Vna>6OIMB3g}QgbHaG5v}0 z0ca^yer=#yCt}}KMlHqFGr-nL9xeU#hdN(HAIa1N2;0HQSsOH)3?)N16HHXHy-Tw_ z$HINZpU?_CA3B`0ifl{E(+HUOhqeu{D+qY{L|f&3)A6FsKtdoa907!x;Mm)lA%jw@ zPMW7mw`~uaEMvvd8EhK3?+cpG@2}p+MQh|denGia?MT^eQm-%ljFju z`~8!_0P(LjcNN7MP2x_}%I)zg(X)%p+<)%;J@g??y{KqL<}D|LS3hks-tv(3)@~)y zDn{+l`r>fWg-k&}6Y8z4SZP?&<=r3-p?~wLd!VjsaSP5eT*`*W5$G)3Je>%04gZA( zx8sdWJJYhR)QS~zZ<#8^ZL<)JJ0-sh;Vm{4E3a6NX-#QI7d>4XfJ`FBaT6KE)j= zGSO>SM)6(PXj0eCxa$SoA-xxk1SB=fzR27b991Oq@BNanScsn8KdpIS(53{n;&=;zxAa)7dcoI z`HK^A%$_?#)l5Z`?S)!|%&TrAz9^1RekR-Q5gS>i>+gUjq)N z;{VC{xbG%<%Xg8MBpz_4j3Zl$yhW3I@X6iN=R(FQgINnZ@EJl!Mn@)~vg zyi#qhs1Y)=Al@a6b9yJgF!MCOm>Hy^7yn!qRP+5-F%=D>37@AANhf9GLnr>zDbJS3 z&B!7@*|;wgz&~A$li9ho%53BbR&00R(f6JOafFlF?`9T~aS+&$nXWG-dL;NbC@^38Qj{2e@zmK>`;>`2iN5Pbc7Gt za&JjQFa(omO@nS3+;)I=x$jVF-F%5Q3ZZ#BBw?aitd6_7RCaQBM761QIz173==byA zYsMc91$hoEfh(N!FT&cwA8*x=7ZWPGFm%z9&3630l1f94w+BhpbZ*}ORz`02**w6^ z;-2nbE&9HbD~vJ z;hPKwUf4plE0TCi5!O=3Nrs{!esf73rmw{H7 zj9I)E{`5Wah|pt@nLl^;M$QCOfKgQ=t`2r-2`Cc71ZeSb^g0%91>ED76KLO-81qHXeq}j=(C0hS<-M_TkMKW ztWly2Jv%8c>&Fj2iVwb#?Yui2&G6kYp}@w?vbrehPcJ+A4KITE;mtCw9Xc1KJZU2O zfe;I4Uu?OH?htg6Mdm&-`K$Lip_bKS*k{yc$y@9HbUH+F@~V9KhW8;XDNeZnWYdfN&s_~U-b9+O9!$q{HK$Z#?<@fp*}C1)lw`lX1R~+n3s#w zxN0ntmm1-#$jT8Brn1LkDUKNV;>JTaeICXzag7RAZ-vpS73PI|*;Aau9or;qD&uRb z6m`hNRoxl`aC_dQ-m>0MEG49%Xf|HxHA+8`%0Kk_{`P?w{PTX8c^k0Hu4Z1K#bPFR zVNDEcv&xfh{-6$RiX(`J-qV^Zlw5kT-3N~w2 zvdqTC^zF7H)>RU({zCD(jx`obvwBJYHu|Ows4$=MVvxhN(v~x;EVu(41;{GamfL;c zF|191B$$Xj^eb&O_Q*X+Hi}Xtizqmgu##UwDS+?HZe5PUfnsLPY$3J&9W6QwbC5W@ z#BwnGV{~xjfnAaUMI&|NT662r?WWmtADeraP11d$|7&7yv2JDW8H-&rfpzj~xyatHed zjz`ZHevV4q*bz%fP&%tMIQ~Xj2IJJWQ;b+A(|rC}YbZqB z)J1I(McbHhWRac2RFt{9Bp)B3r*NL*a_Hw%optRS6@g^||1M3MN_@4P&+xMgbqrc5 z*b=};SgOoFxreqCP2z71|G`!<5S{)q@`Yle+K4`7T`T z>#r|Q75W+#9*bA8z?u=A<)WzNs^Qzx7gjY%Gh9_1Uv}Cp+oCoUDdjn~gZ{)JNIPF` zX9fqhYk%6ulV<{MHy~kZ^X@Z|a2fCcxDtj8!R#m`$IlE07cEE6YfTXh>pfDMmvn(2 zVQBhG<{3F0j>8?t#nXzKUl!&>pVyj(nJbE*fAtLCgLagxOMJi>7}AL^Nl>vS+$T-@ zQk9YD^^Rz*9>?o`gRqVdRsWZT`OU`~mA2oHLF+*>sycA!1)X*L}s{#@0?XACjn0odidjU3dioiG*r@g0JMv-~$(l z&tyDm075F=5E>xJiVM5eJ8Rxi7NHy>KfqP&H~vp2Hx0#dr&~hCnI7rsg9b4e+-o=N zV~`vr7Ae1-*Tz_K=)Q(aM(!LLV;#Ege`=RT48H6zkA}xtnE+B$N%tg6N2*;oK$?}% zZS!qkwO5=o+{{@!A@j8-K)x1W^&w1b$;?*Lbptoh-Q04!i4kNdk^^^S99>v}h)V(0 zNl<^VX6{i}WHGO1zflb%^7X}lLiM*Z68V?{#w3S8&GK0{unPeDdJ|cP%Rv2Sw{__) zm!;63Bd?=I12?W*Z_fdD7M)p}F1P&J$ekJNr*rzoDn7L|vA&v?wF#0Z*48XxYN+UI z2cF_tW97Mr5nUi&jJDQH&2xT~IA?D4rmf-mlQ}-yQuK*z&S9S*l!b6;si#$W1R`Nl zSsS6%aSR8?WbY{I>sk!aIvf=j$5nbQ7yvm;azxdkM?0+@BPs=szB8?|A5nExJ3%%B z0BJy{rm}ViulfVe<_KtGGQHJ15TuKSOtB9ODa$QC-rfubEFb%)ok>$CYB4>D{Ezdf zl_CwVm`r*DR7QH2oqzOsjIwrM>?B4^X6{|07`;f$1K7JXV(F-MZNQ~b1__hjHZ!X% zNDisryMSuMfZUDrj+&?$_gJJt=}k^;+#caHCqs+K(mRfd!*xggLR81X%}?O96N}>H zHIyr6zlcm<6_EO}!2XmRsB^Y4cVJ1yd=EQ9dECd%dCkNDph4ezvxvfoQZ=wUT2tp9dq^T23tZn} zz}7g!7p10K81vPKxJQo5x1g*CweK2{&SQXL$ zfEFF}Kq5hDP@DFo075_DuXqZ=B77x>y+Q^0;?jkf4H2SuAXikDbcXM?`|DWcemF^Q z{g~a+g*6xN90PTy_PZN`OJC8Y9d=@JKtpv(Q;6Z%FJo#Nr>VajS`Cz-?uQA_(^iZmsndsy8M@bhE7xyU^lByJQ?4S`?>Vj5lq} zS0XG%AQnU!q$yz@iMH8}l}ZCw-CJ%x^R|&a^t{l~5rdsBYeR1qoC~itvBa~!9352)x zo&Yh}GC4@4*0*gdQ1P2vZ%D%py8}b5vYpJ^DaleENgVJ;N#11Xt`!)gxr~sa$rZQt zl*tMe9Z6zLljEkVz&(^1iB(Od7k=B%_{qwf#QumfG_}VoYiTpBfCNEHzRd3SZ~BP$ zFORS4v+h?1LGV}RnXGnYQK12;aY;LaybG7ZKnQU%aBZ{sKPW$;RzMqMlbx41cW$-gm^>L6JMmLI1UMAtq(`f5YG|) zP~k4>t&_&0;&g@b$hQV{)C*$#d!P_M!*6Zxrxw{L3TeNF);y6qhp=Pb8 z)qRaDw=yH$1!%oSA#T?tqom=`*Rhy_BVST#15yW92(caY-U8RYNIzb`ulWN|S*Ji; z-q^SL)5m$}IQy{*^uVdi0@hV{c|*90?(eS4+S*q3-Ky`(Ph=(J9LW*SXhXQqrxWSV zx7(hRlb0Hl-Ytx@Gv5H&^)61f%TbMdom=Q0nc9Kx3Ix&xj}mf zM|QaF1moy3Mw~`|Fnfhf2_;!_;LMD0E8@NH&GA#Kn=i z^JvIr&F2*0ElK%{^Jz>&N)g;E6PcE(nm09*$G9^Ryy!wvr`y`A$}YX`K!ZKkbHXwn z-=ry`&_Q?AWsVrW;>@?2k>T*zWA(tVCx~myu?|EoLp8kV7j6e~9s{M3KQY@WyvX;@ z7%M1G(Mm^Z_~HzRoKf#D*}H*ia8wF<%xHdvk3WvV=|~aWpO^)&a#os}%~IJpKx(|z zBqWNF^6S=oKBfdow)>;+crG(;-1SvFo<$gm;DI)8;iKB%W<02iPf1@M%+Df`S0_n^ zeCEp*q$EDiqOh(Kgdo%4)h|@-4lg&KY4jNW+c~nx=v0^=ig$UTl5$B4?0%9{yqX(* zI>F(~(U2o%3UA}&phk9O_uomT5k5udm1O6-Cmp9!=Md^s1k)jVR!<6+JYMnsO@hN} z59G+hx%>41g8c?-&g$$Wo2E{E?ez}aGtHW&`T8r|^Lcx_{7?A|B{KfkU4S8unVFFj zV6ttlUKqdoDZ8nW{pRz};UI4FR=g^JoI?F`)2QjaFtE$WHVh5_EKD#fFU^Lcckvs) zl^QaIJr=&L`vl@gJGSrDXEfh?(K?M(6ek@?dY?KTz!)bp4|Bb2C4`al{UNpO$zh+A zzUA-s$rHP%_3e>$Ij6Rzb$3NQ86E;)t8xu8!{PVOm>UXHb{#x!U&Dftottt}Ct?VC z6*+VfGXkS~b`S0jE!EIid5FPwTIh^?d28TFvJW3D)P}UGcs&<3@Ts0Rqx4wuoAc9W z08}f8(e3RQGYSmmaGY{2-B2&gKjXHPuT@O@8lJ;zMsUr0-b4=Axco8wQ}f#Q3vLH~ ziN)X)OMoGM_FZ+?ySpQIU%#-WTa`406DD%N=YR{+-1iV$vPHdylYDelc=$1nyirKR z-M!i$J4sxk*uiJ!))<2vu$P$C{eyS5Z!+;x90AfPtn=T8h4F?~lsUU{yLzat@3HC& zl%Qw95H{!698mDnQdl$WLZ(pP`5jsPqh?nBq{=mM{@Fa!9i;dx-b!Wi#j}NW<}e(6&Ho!|?gnUl1xRnEP6>4^*h%_uUL{pV8f=RWxVN*)o(;^DxTfGnb{K)7E8jbo{OF zy_11?Bnf~fq(Zot)%DLJpSA6E!qKJM#g zkWxfc>a9*z=7|ON=uIb1w)Nh^2e%4`-iOC9k|%LD-`TW7rVV7{@Xnp7?@+Ul;;Mc2 zihH8i6bo6GoGd~w%?@wAW)sCV#a z5F@Y~ucC3iudj<&9=GbNs z6J0(53=*Ur=yhWt;%Si9_TuE0mb;rUz!<%&5Gk%|9W+r)#?lmJZ5;W+W#_&;(ad-4 z_d|ofj(-4mP)cj>s4`DO-TgdIlUtg!h-M+6@LTgAdAz|gea!H}IUuQFiA^|3QhFfF zSK*@Fb0A4z4_cv#+mckNNpRTJ!1E8EHLfYGN4ki+w z3j+XVf;=_wjXZ^cypBDyfe|`n{nOYKr0T1k_Z#^;Fy^9j0>jduFVjlg+8LHyMyyrET&Icm64Y5c z2^q8g(pH{cQ|JFh?EHo2Qm{;qOfmEiX5?k_*Oi53c?y$Qq{}@VP}~3twqhhD*iy^g zPi+vWpNZ^r5RxRv&q-6pJxE8HS~sI72CovB8(!}AWC_dvzUacZ7fthFI4z#6Ky8ML z43`%rxO?$`1##px61v!k12R8et>d$RW{tQCIUH`t8ZBM?Kh5YSZOD+d=8J_09$tpg zJbCD3cy((SZv}U+-mvqR5(@dMyf$!sb;)?>;qX21J^D2V6QaMo>6vAC!I+Ty7XvX? z)of<5;%mKK(SRRX*scwXaW)cn<3VDa=3$=N|7S*<>i?e65pbyTaFeL~XyJid+4n~C z@elFLS{ua?p~!q`#drJ=^qL+Wl+>MnCibXUvp;Z1On^R-+mV8AR|cfGj(!63T+(k& z5gCP_FGy7Upt#C_BEmPXIrd4RMKZQ)uM5dxw^!35^#ApPuI*8d zQ}r8LC9@$+K;S+0O>3u*;z1mPwz&evL(vzt5Es&GH$g;<+~xT=BgRSxPFW0xqaZh% z{JKn4)D2oZ>YX>j9!QDyYF_w0NygMlbhfeWr`0G@K6_Izu#jm3j$n(OI|Ip58A!Ku zws~vRNh4Z`@u`^)Qc1Nlhk>%>dUuRBD?o%g>TZFWp1O%N-Of)YG7p~JFb6qAtxpFU zDWcF{Cv|_PrLaobSFMOL#$IicXA8?G#Pj0F39-BE z`y4>g$nkr>k?=OL{&Q;mif7XnqH2^iy>=CtG>;R>y*>_+*sCYVQ!`-+eez#{BHsd>En4g`; z86~ncn3_PZ!I*Y`O(FUg;hAi9+1g7c@A%0w6T;(yE>U~T3`O_abCP(A%`e>_LQdhv8ysgqTISTY zoJoS~tA=3AM{pE{so&Oxo;w=xpN^~c2k%H2F>khsPqlmYg#y_CPf#2@Kp(4K?2IDh}jqlyqdju?{9{6|I#2w40qva81aYiEOq@OyU-cX z(8j>0_{+Q^j&KyI;v_KZP?be{f#%B>#U4$X3K^h6#y|Ox&bg9Kd>OpjU>AM-`qxUd z{?8$r+{I`ae>9bs(TxE$8Q3>U7vZg%)gm*W_>x_hS_9bq4L^Ph7`J85{fUM9D_bx^n{ zU?uCi|72y5m0$R%hm@TIWVb7<}xD(qedL_cB`r-jJgWM&zGkuEG zNa|gWXnxDx!@N3eDy7N{tW6xzXj4p;ATF_{o*}a#>p8y>JeG!PhZiuv&jazmh3ly6 zUIU z(3iin{Mj-OYK)H?gv@EbALNLeKB)R;Ywhu$6ma7fUbuY}W7rCB)g^P6oDUn5K7P_a zm)_RMu7_N2>?RhE*mWTA;_$#(1f)iohP^^UVh|XheN8D5iy=9>p!=f|4V==Md8?&O z8VSqBJL60Btp8+{6ajNWkIc1+AV8(hvPNs?9Ziz@qe(r$Z5S&t#g&Lcx6taB*Gvjw+_`9qtAUyD&!4{;c;g=GV`Bsk+X zd)-HS23UY}TW46k_U97}aUV3fHETb*nFt|f3D-G_?;){csU1%sxf;Kyl0&jiWCCHf zHjizXES*YqxT1Rx1V}v|D$EE5EI<$%v1FCy8-KG$b63GrnIY#XnkX|j9&{d=4Nw?O zh)JrJLvFiU*es!nz5vZBi3+GdJLIHg;GtO@fcaW9SeELHuh58WVi- z@^=3DhX7h#{|>B0_+KO%nz@8UxA2s{|2wrH>B8&q@+`E@u_e{hevkE}C$Wc(RQ+=M zfjWA6qsx1|Su2sL<>;pS;G0ZoL0qxxx$)^K*G)&)S8RW{J|oWA1YenTk0qos zfYE&>VLh&EsSEPlw?lYT9j&>Uyz|t5I$sZy`L6&+Rpyu00 zPYQZA|AUU+@bBv{x#>0gs7L$GEJ)wjk&3|xUzfZ;H7=Spd;P^Me7flEcTq;C74gi9 z8@qSiP0D4>Xcj?6qQPF{CYhk(cjvLTcO8gXqt}w1NfRqB{q#@SO=9F~x4e3pyYP;6 z{icq@`>QVG&|{RZ(XPD}Np}U0^l#KXZ?b48v^!>qgDz?sZNjnFrucvVHB_$8!S`qy zyZoMW0q@CeuqnkgjM3kd%_&zBMWmD)(&yleijL1mS@0I0N*e%{{(@8cS(cs6Jni9#BS=tvda=J+M3oqD?NbQY$lSL-NgzcZXG3r{tI^w({*EPuJO3 zK5u4t8FSG%xB+lSA7-k!N3fzZ8qo*u{@iFUcg#wL?TxDP$N?az_|PwncqL=B;Ixd$ zf-Nn;I~UeQdwL^tl?*~vU&b5NkekWKxIKu*4RNn-_DDCv6$W} zy3v%yHPI9xM14&S;Sl;NL)wxv=-lA5m5Z@+unL+EkzmTV8#f*m6wclWl#s1(-Q zJ<0UeR#oUR=*nP3(Gk59?DDbE)2HcjuW< zQrcBPz z4wF(*oT580YwwL2$R?i;@3?ktJlBg7(U=_Kw4IKFv^5A?m$RXh zM&iG5n+O9;K>IFGj?$u4A_;yjKmelvG+od`M35+9a>Ku3+o^&Y2e#{8h^h&Xi2iJKWzu2t0;`8I2YvyC~&Qk)jHH}A`zd?vV44`CSSczf&nd<70)O$5yZ9H1u| zcbNRl+O(J% z)%pXH0g~n9z#M}380XQ;_iHmU(Ej3xxn)A@B!VDm;}|SG$%#L8X{P>nakqC11ATB& zQ;B(u;(~hUzh%HlrFyaJLi9blw?da%=4ZY!y%-s03@hL8Kw3s zqi7=_6KZ$g7r!NP>mNzA-(edKOp`J{yuGYQQw8~7N8bxLa(wlw%BJ-t=5I1*m#wlG ze$+U?x==2NySD_Y!9>gE0#&7wl`f_lpR$BtHPLv*_#!|r+!ff<%E*wiWN^z}jqB3c z&tY8oPv_(M_CLgn|M@%E~+Lg_ICgQ)M?# zW=AugqON1=57i7b&}Jm1aZP_ktp62yJU<+tlr&jua2axC^JG4*z0MD?%)LczqkFU= zq7SxuGyElLcexK$O@mcK;)z%@Ie7`8^gz&Lj&1h#TL>xGBi&lc!c{Ca+5zIl0x#8{ z+nB1C>YRgXCIHT>{o~W>I0&l9lcm@mal_1q64AVOkL_9!GXyfnGj_V-S#cU_M&2YE zHY&+|%lVVX$^E7KX^4FC@+lmR@GzuCM9STk_}GTr)q1CHd-)^}EOUMbF&YtStSa~f z5@8A2xcWUu>xy7}vvorhv{1l3bGPt*xRL@r_KHf=MsCSFtQ6Erxu1>fjJ84sNC;=_ z;zyU|80S6#@Gf;jG!rR(Sh!)FF%^k&uu`$UA_^~Vj=Gw?LhFF8C@6>l5fRsY^T5B2 z+{3&ww+%E;woSiE((=|8YK2n>4SXzQ$*Si#ox%>}2Qbcf@zJ?dB%BM~)a|CDGJ zUECDK8r(t5BXYIFJD+`goe&N3Axt4PedA9si5nkUuU*fr14HNWgp6~K*$ zVuFERLABqz6Y<0|<3>Wv-0h@e?b`SJFI74)Ax}L1QL?Y9hHcr*5Rm9;5#u%X@k`r* zGESuHjO3jC5R*tBbwvBXxMs=mQKsZc8)RLxzNa13!YTf}qSeoM+tL22AzDi2LWa>C z$J0BI#!kk5t<^_Fgm9RUl<9s=kSaYvWd`9L-4>6jhNusZV^9D_xz-yV$R4sgvG)FA zE5@?+5Gd~646y*z&y?bT0MN9qvF6e@PRIxq8&Q@q;r^N_&uz+oCAgSy{mgfGdWOMG zCoL@LL68oE(}4OgU>_cI%pV}q(<7@@f*4a4P_x^9Gg>4}g}N|ScCTOVTR`f4U@cLJ ziZ|9`g4Jx1-MUg2I{gkD-clDaKrf0?`x58h@3Gua-(NWi*}PObBV!Ol`Ht zeqn(kFqpS$Lluk~>xPXEzgsj5yENn3mvg(pBFyr;0Po@NV*&c@xh>-;;~es6rn zN&rQ?VZZVv1u*}q?3u^5=Jy$m3g9I&vpFDL*YI=$v+cf78(3yWZI34v0!jPxY4o+pQ^_kC&Z0-0!p3bV3*@WvqW%SsS+!WgPzTwM{=NGqF{+l)9PXMh!-qM$S?T()lA%;$CTQ~Cf z>>F<36w&};V|TRWmfP|X&spFdY@(_;@|8etCQE+rSM0?Dy04$Kw|SkpVdL|bAhq1z zX**n`*W0=0gZbLI>TBOcWtm&mF=;VN%FMP5z5P*%9p z{D(B;sVElc+-LtXCo*LOOyw%^{RIh$liP04ys$xa_;y2aZ5Uf>B!!6S?;Ap`@x)>> zkGj$~!A9&)RME>WVSM;O->Th+?;Dr3mSvJLwhJ!hH-43(X=`$=ZQ@_HjsW9Qe$%7A zXwDU)iI!Eo1ytE&oRVZ8|t6- z|3}j4T^St6S*y7tKD5hzpluIr=H!nz^x1UPJnitE_0xOqbkRc2A9=F*iu;vk8g8cz z$GDld@a^%Nlf1|Brwpre|GX4QS*wc&=zN2`q`Ii_tbuOR?^)OKksgXSGQyL zw7>nCF+A*CZS*?yj^Ee^v}%W%F!-NNWaE{eo@ut%*MxO2Fvb4j$oG9a4R$oJo%m{$ zr6K$v+TZk5p25lepm#A!TsPhMI+vGR8*koS{Nw3+=ax>(nZE3vXrJTL6r-3ePYoJJ zihb+?ic}eLa}S)U^{dcBXYm195;yzf!vRql2ErVb%4YC<3=?T?R1@%5w46;#QEg%MAD%%FFE+^jt@Y;Azw(F9&y z{yr>4U*^j&?PtseApn7{e?fW&x(GY7(6bV_{C&}mged>nOR%YlnpLj zJ9s}=)sZ{>Yg7BNni9`KdX5_k92%B;~xu4;jDfznAI1>b7u-|g45|eGi z$Q%dN@UJKHT41}tf`8{yRbrz8y1!}>utjx8k6ST)o^3Q6_<2C1>h3zh<{FBh(Xm9) zm%$k3e28(2{KcH5;F^~1uGjaiFWlXfpSww?+2*ZI(&sDFo)Z1>#$|_I9yraT3>J5z z@5(-Cq$OE)Ev9;=4*P;l{ciY7o;*J`mtsMxITgrlyee7tL@Zcy?^5w#n^$td=UM-3 z96~QKX5xCDO5Yv7;g$A+t>d{HduFzy{`y|G-uL0!4% zG+q68Y|oHMrcY-la_anz?!Syi_w{}Ho3d@ghFtcSca#g+!eZ97-9~Rw^ZN~Pg~Hd@ zzME{SxcNYtmGd#|^!-=vh4ghUSK|NNlWgh%EHL&%N~yVU7q(b z=0;rO9?Iy;)^E}Z7(n{gUZunuZM(_25zW74H8dUMQQLr_hxK`2K8zsAEr=^0Qg@nk zb~FpDF$pJ?j+OIQJS~)d<2r*@;O5M;NNKcGKhdX`Pw6|t3cf-5U)rokt4J@~K3p(A zbjNe@p>LU^A0}?Fmd0MG#`(JPmQ9E+8fH}db7?X&dg=CcSy%dX5EiXL8!(@U{C1(c zfdz3aI>|?5s;0FRFuYhc)>36HzS3PBU=$v9%wXN`?6)(&8r3+`Cw)Iyp-7#+gGPm` zhvNuXmAFkWR`V6}|r2#KWpwz9Q&s zi#figrM1H6SS$E>r!KocW)$33mk5Qv1AMG%U^ufO$_BTzQm<92Jc>TIWi(TfCbIue zr=gH#^<10cUdd}IrvBzgLL|({4h2QTXR z!@?5qOgC8t=$qDS|KN%wNyB_sTFZIC*f*Vze21&B9rot<+O zpd>{aOR+`L;aIbp`;aTnrnw?p-|FKAtqJ_hf}lTs_|$79+jAc!$%>#z_z(1o3Tipm zLcNkBa2Z8s0T|;9UJn17)s%S$8Aup>+5_z5tBU;AFOA$jVPN$6Y{xi4X=?GU;fSJB zkY_QQMBRxRIhHhaF6|Ej!umzm!_uraWizZp&ULr3R}GsC)~5nQp1oH;1z!h4Q_Wh+ zwSvb9VXC3~O%!a=Brfk%{0;|q-`)3HTmTFb6Wit5e;l22u-o3gT$toX9_Goz|A%Jwd4B(cuip6HjOA_jh&qn7U z;=rhMAz~UriVH7p7_cen7^CDrX(rKDquaboJ>kjc@nj764mPPrP0Jx1*R?6JeTjnn zEOMT458h}ptRkA#&k$n^Gpaelc67-f)+II$-QlG*UCt@GPn_&2{5upQ7xB~j;ZJ&? z9+jJUt-^#^hnlD5j_t3b`qyvH0X#S!lfu|G3W{dw3s>7QcO=lO&LjC&%NWD~mPB{$ zp5~JTI0}7aQ~M1m-I9d|Y z!;$Q#Z}3!>-Mq|coN{!y8~h&9dKcpp zcFNWvW^02dvCAv?sRdHw`c$96wRJ#y&LV!-!Coo zh(#EhSs>M{N5dw8FPDjWX@S$?B2&hMwh`1f4BU9J)1h&DDz$Gnj5(-4Dy3BuA{2H7@`s+t)Bpy#f8mpy~Rxt&<@Y-b>nOSm1ofj zDNm$$Q7Pa3^bJTCn&&pkm|EYTA8emrA%SfY^x05Mgn(sl2xu+VT+k#TcFBEt)`QOE zF74~j`_{c)4H-FdYleDJ)_pPHk(J@dnOzN{0-Qs}9MrAfGJhe~+G*JgO*g?cPD$pP%K;{%STx4NdBS?KIi4uhFd2h-T(AAUvmBdeHW#AqH0ea_ zV%Sa!KWtI4p6p$zZX&==G^W$S*3`ui@ZhAAH0bQ;&tp4E4mO*&hwxiLsDn1?9^D}1 zcWv!Y`p`?I$s51E&fPGOJ9U06*p>New%Bn-`%6LG@jpGScjktx+W6ex-P(f&ocqq| z7e<#Z!YpkvJI5ZUmfzcg^Um_lTS#j0AX;Iwa^`h^#w*WP@4(uNF=%2i`da#d_L!MF zLZ?-4K8l;ngaOw!=}*}G{)X~+VDm(WLqQr$^a>NF+e2XoXU2An zdMZXLQa{GyGiYAYQ&oQEGdJ)xqjyF;%_(`BDUUba89ywI7a9rH?`Jd~9`g4}5|}a& zJ${&(Q*q<1$t>hvx-Hk3pVcviqGnQKK6()M$Is~ zSwwBty|@xB6SwXMUC7(sn#V|HT>=f~T8L8HN3# zCELa8&oIA4KOJDBu736k8hA+qSPT|Ly4gd`fJod)H>P1Z0Sxa5zdJ2nynohN*_fbcBAA84=zeXt@mKT!Lo zWI5p+Yo#EnwR`(Z=_dE|qeg#qW-C)(qvA=$?eE3$A9B9umRCM$h*V&#B?$>njTsa} zX}{s+I@Ir{rZayGXznD!w6UO3(_EKG9xuXst5?ULS$EG}pPfZ>d`-6yoLgE&3p z$j+q>zsLRJ;2&#?6C?>+I1%&+Ha8^t03hJWxY~1lP=t%bG!J{&BOn4dwr1ii2xk2L zz8jwskAekSe(~8>a6Lo?xF?B~xfdS>WzDqA&wV?nE{emWtGais7n!@7=OfWa>z7vE zezDOcr0y~K*DAbxN2MS^Bd+O2f0%_$3A)!t^;z7Rm+)SQ{C+4YsnV@CSoUU$NMl@M z!2_&nvg9#&>)%^9{y&b+J)Y_BkK_7wQ7-AGlGwLM<(k`&T)Meb?nZ7&?w3udxo^6l z2qDDE{m$GOhE;MMkvlVU+mzbeV%BEg-|_p`qX+A=?VR`J^?E(wrS03P?*x#~?rOUqMzxdBL9!Nv!=w1t`KYd&7zQmeMsD{$GS21CN3=VhA0R zIjLDikULqW<`xY9fkosvFaXy;ZdZsWvJMJS|I_GftOQ`i)Rx$9<=>8n&=Wtf4F z>d2iRDG^F7=k4Dxt!5+ z{8KqFm!C`m-s&Vo(~n&aGFGW6nhgvRvo!w}e9#M*4q@(=EC82bB~m8+8TJ?hD;4{U z1F_3fNw1iKSs_uZcz!1kCe~XD5_obx=#_%60sgvqN|)g}c=6GF(qICr>F3(-vi+jd z*74<$o)WKr*B>4;y@`li!jVy-z} zpf8Qpa%EI@F*J(aJRiE6nKwW1hAX=I*tcOhl?$p?;z5)2bK394bk17uMYHvSUUbgo ztj51M&rsi>ihk45ofR5uQm=Q60{LAHJzE1O9B*hS3cdyRX&YIeoxS6I>MNv9yfsu{ ztXU^{?w3g8Ay;ly5eOzD3jh30eEerK4TvNwqQ&kR8G3wdJ&gYfK2c9E%YpgKwea~I z&t}E*HtEQ;y)~V!AnqDf9}7NH7e8}((_K~>7-*h~&voy`L!!^Mc>CW5Ok1Z>C<7%9 zxG8z5=0FWO318<;sXP~#FNGAfhJ`VF@Q_tZjbi<#yZeG;LZ;MOecAo~z^!oYN7r!; zj#9EAenj-A*A?e4of++AHIaLIzA-i>b5d`+$uRc(@VFc44*wA(h8)pQYlK$|Txz%_ zjc{Ge3>_KsrCq+LX(u7FXew|HjriZbu6F!a$DusVqqUXDNXqlD{myeT(1>?gR!=kkKGL7LzsUFEhlTd0 zZ-?SCGBx0C;j~Zkih%PqBy*rOJaks!C~3R>^AxH8E*YR7_)n9|?+MXofBs!O5_0Be z`|uLnzO!!HDtgJJJ?nJ{GcwGH_c`jEz2Sd6hu~wZj_G#(%PXR4Zl^z;-usLsygYEI z!9?yQX86MbZoD)-#b zZhE`6H;d&)`CYBfTm9>E@6L&#;7Cx?)USq<;|HyCZQ~)4Ro$X$%>Ug<6};sD=>@S!f|t3;2dkK)fJfP zD{az@WP6U{}z&jj^FWj{cg2_44Pe5H6;8yqN!b&r)yw;)(}5J%(U6V_W7D>cRi z34iGu$_UP-Jt9N|ciBR+E47hjy~_mI_^09U=+wyAz+#{~kz0L;IF56d@8AaZ2uN-4phA=#90W{*rpGu{bp3-et3fTW_9hfk-t?nR8T zN{mH|ID8rOjc{^b9nVTitWXOjB$>D&%Ekv5BfLjr^(5@DR)HsVE9$iYRzJK$&Vg z)GO_IgSSC}00E02urFlV7Ni^R^0D?5PcUv8R*5vhY!YS)aM!O`$+d!*^n0%(K}Nt! zpGmG1*?{+|(@!-4_uUN$%^rA3yoMMXFg<`5JaXVa9-ElB_fO@_{Y9nTm#jCE@PWwE zJ>?`9b8V}lo7~D&t}LhiOs8eBZ;ID#mJ65`C}i6|xYl`byTry^TZnkiz6>s7l6*`V z{C5AJkEzZg(cSF~LSJ37qNng385ucgCu(!WR9RCRcfY>cjry~cma}vKE^7so z@eX5$a=^=`UwkhLI&vF^`Nn?sZuk+oP>Jr7kOtSX)B}bhe1IB6`g^v@#GB7Z4hdLv z;F^93i5$mmx|)aU68CRjq+=_y_~JXniXzC)1WRY{#qwwX#%+6775D9HDTjjmkk{wC zW&5naNmy^(cST{NI1ySJS4yCVPbF{v#B!^3SwKSFuiL%wXnJP{yIx5y9!TGSf?OT& zO*CAul?PfGFdWsh@{y-zs~%kBN~|*q=^G;HyG4R{fd_Y;Q?@>I^WP~dlD^=@9^97* zX7f0}Mk`$HE8_mOH56@Rp<@|;!GjM5QEb_s6ITE6SikY>w_Xnf_;cH$+e&aa5yC80 ztk1WCfCwKRa%XoDnwbWEd+CrfQhOaVFIHO|5(Z$P%6gi>LLR)HXNL`;6$5P)@``cN zY)v!?5-8$DUdA*5>|JsX z8OQxg;#l(C&_4~Q+O4QwO#Oe@3bMdWvF9xqMuRVV#^m(ZoiT^HV^D2p2MV*Fhd#}= z4i#EC8t9heeAVfQB}OsM{0xFCK(=zX3)J}Pgce3MvE+r@Zh7yz*g?t zl!UJmc*w547-}J~ildlomT%e-3wRnEsQLA!Y+W7jHb0S3iCyFg67oB@$*dg?yl6KK zzpVf+Fweaq?wT=Wp0DoOivUHyz1do!8rdMbBAVdf9rtu`ZdwB}mk80vGxk1rc7FTa z7VPs8U6E$6T0OFbY6M;cGVPw))+cH3^5MtXWN$4svSD=_obWV=Z0w!9_tH~0iERgD zeXx1W#E)mS0_j%vJ0MSH@s%N@k09s1)A&A6YHUgyjy1xKgKRn2uKKdE_0T(8>)Wi~ z&y0F|iTEE@xl<+UalQ58dGn&d3tjJ;5O&+PCG8~`8?}plSdQG!n}LJhl;B|_NfM-|ySw)^obDWv|#^A+gH@|%rN7PhEI+9j|J-WS=CP5V~T4kb2u* zO`&?7Yh+)`3Pb_d`OJeum_?Q~5E$wPI3$(@hx(UN{tC+6OGfOumbHcc^1g~-WmLx9 z)Uu{h17Ww)?|dCgyUWK?mS6O326opHKWfF?nVRABrq3XE#!Ey}wojjPpw3k==_bBR zRbi&E2rQ@ZcLh2%+Gy1LkI%<1Y9hg?r}!o!S+vBh(ar4=kiNl=LwB%ob-W6WfM({g!$; zS4|GVwb5kerj-9xgHsaf5|6K0=dWXdo$IGW{QBsEZ%VbTMQm*Iq0Z&5#TCx+tS#Ia z0ElD}#4Fm4hTW)d9)8m5#Z||Sy7aeYDQkZ+b$M}i;(_&>jTwS%#rLDBv&gl9=&=i9Et-4WV2=`1oMoXASL^~S=Vov^v+-zLG)LuB zyXES|*9cb=u^=N!T%+Af&p7 zoIY(|0CYoAgMdD@DBJNr9tQ<&cP3zA)S0!{ao=a)g|Y%7MtXN9ewnm|@0xWDAAlOQwBNNV;06aR*)mUV;I0+(z)#*?$3 zN^VsuZb!1MgWNwGs+g)|U_YHE2_0p8Q^c2m)BZ)q_)acB+jA60u=j@S=(UYaujIOt zq%zghbM<_UwtWIGUHzjY!zDJuvpy>vvYif!>RkHzKw2Z5`AwVX)$w}zACTXXSp*qt zEhi`xsE67T{64?>+N-qq`q%d`z3s#`1K|m2D&hS3 zwwLn!=ufrwaUC;10EWElKx=X5iP4g>vkDou-GAtITM-R|PU~SZb97BZShrotf(=4T z3FK4!%Ghu`&AB<+;`DgP%QkZKSKtQZ65;w_IL|+|Zh$wvaaCYG2d=p%W){Sw-pilK zzM=4sU^^rsBxdWc=d*RL+d?Gw-BPW66qy;a=XUeFNpo4<+OLF=zDFHCBsFD~P<>SA z$1OkQu-b;-Ay12HgE`@&+^4peXzc4EGG}&XLSh2{`MRc-wvOxnbweLVbrZW9V&V3d zR9O)c@Xhl^`ca$c`H=6Aj~Phx^m3Yt6OT&TKwpY4y)eI9pSE3{;X0D@@0OV2%=^PZ zL-uv(uR2$MqV{sEF>`KBTXysPIm=36OB!s^Ka@Y}i$ay-ZyOq?v<_*7U#^|%32f4~ zzp^BOJyJX;?-64;Y~@~p8lu$ggCH7KX>oo6!+kfWt2A!3!frn4`NgtM+Fpj#dFprw zoNIh}?2X=)(2_0H7bRiWGRA(o*S-~jz2Gs1LcC@Or>3~C8ki@m3OcVfIR+B{-CSsW zdZ#9X<|f|XF?n|7i;y_(^~qm%o2Q3usfn+s7CKK8iht{ydRHDbge&zUR?ZGqJ$WLj zbVXyI_}8cXZb3IcrJ{}=9xScz`*cWBf~HNmGjn6_m93vKOGAG}uyaTJUXZ@(Kx$!Oh#cVX{QLKyuH3+QnQN6anAmk_M*2X*#vhe;P~Rl8Rt}2^Q$Lh zx<6mUK1REQhKvCH2&faZdva9A+0ZmW7c@*E2B}uo@n?Qw5h-Y*>_OCwdww? zeD|08s0qB0`^NhT$8=_^2!hw-u&Pnf-q@h`UD9O^`H#lFk3`%(ho1T1ep<1@Z~W|d zAI`B>FteoCFmyiL*=p?oHaM**bAB$J8Zc6O?0!~Bx$iMl_tld{kGhP!F&b4NZJPsw zR_x>235uSW zfrP*K^2|%CKWGKEqr%KqWiMq?VJl^g_qW!X>J#*lyQ zhKwi(24!}2J~&-BszQ9fqC&oNA#=(_NA_71I4*ykS*@K;pDmSsm!*0+OyLj8W7Gcw z@z<5bk^%z;!P3#@IUU5A)F|s`r3EsJpP?+#EuiDq+o6pKHnat2mYwdCh_kWwR#oM? z%@Lwk5Jf%W)Hxi`#&uY%gGlt!ONe2d&Nh==q?fDnez2OsN&qLn7e)%n0ZcsUIS^Ze z#I%NWaK%POlf7L)8*#T$<#kqb9nTKQIt$~CzIx^w6mWBCg{6@o5t7WY^V|VJeB3&o ziOGfrlvhYqT+>vKnX)@lG>}>H9T4>BBm&smWHe?p%6?9-2H^-^ro7aE z4KO`VzZi;}v1M4X?5L!>bu6zyV8^=L`|HNZUm#iZP2VI5&(6(v!24e&K!5L$M?^|g zG&M2o5t)M|KLB1Ykn|!1g58d>PYQrW74u4cy+{Lkst9_a%t<#8EWO?Oa|k-AGg%1y zDN5LVakojGqpoPoQz<%7eeSZF5psBl{1l93trMKKZCm=UKq)Dn0>DJj3KL>;nx6yM zQ<0lf-31z_$_VTcQk6jRE^HKbTv>$}3H(A9OUxktCfnR8Z6Hxz7^#@~bhH7s8^I@n z4#MK7MSA!^9uji6M%dpfnP7VE{yo20We_bN>$kLm7QX5!)Vp8Nd3_wbU(H10fBD-H z5YXtvtykF5y!=Gd;)tMO6wj%yuOZ=JJeS0+4g&TZi9Ns=NeTnwSw)=E;6HFNFr6@V zmG0AtiVy1tUQ#T#GGT`=LgX9GnWKWuQq`X!->u_J+Ug|`9Y8WYNLNkPc0RhUYzbel z_Pt#a2>-<_g~Hq(11uv@;_qp3j$|3hK*txhJ?5OJ$_&M6ac$vbWc}Xw`B@o79aTX( zkVtw;OcMu~Xj|BuCt4y+e+R8i7eHasub&F7Tr-mho8;$6f&J!NV8H+-D_2E8CtBwV zAyg%%7drr`$iTZ-c3=?{Nh-0YjX`I@6Ay*=bu^TPjr}QXVv4bGM zF?%nOd%*~g+Prz5ju3&Nu_jW^j?4h=sBWpvNX@R?xy@sbon`<&0I+Sngx|=fyG{X> z&C!IF z^iuFfBp8M>p9}&a(_!eD>?HLO#*{W)8!FwO;szp-t)?c(1h{@<85AUwZSolGP6kHp zhu!+#WOGUZK<-^NE=yUAAgAd!J;$Bno;mQogOv|H$+yzU15BW6LrdeBDJ54yqBM9+ zpZ&PY$rGz-kmYX(z38EOMr2$Rh6tU>du_2Z}o>%El_2Wo^YpwSP(at)p`qqbEm;vxl)CD(XkiWT-o&kNh0#6vw%B&r!*Zy z?IOc~D_ED*PTXCc|y?bU#3Cc8J1H_5< ziQETke*FE;aukgFPWp8Wm>vy%AmxG7l;y#5ur^oj@_#&6h3^_rItMmPztgVOfQ^+L zH#lFwDcwMTKz3w&uhf-DwEO0=p#~NNguoLPsDb*FfO>Q+jno|TQTOkgQpv=UMRViw4WMAf+hBSC4@ z0^nif)ihd}LC8*ZWHYwWveFNF23k9anv0ho;kEM9KEJHxxF>CY8LQ z;6H;MX`&rmZ<3q{LIg{YKP(Y5Oytuet-Q(xt6*@9^?0ty?iN zd#kJdl=zc}fsJ6R#Fd2W$DGx^iEm3{O#~!1w0oDl1Ji-+|<% zf$<&RSxy~eVJ*vF(OjB?@}syjh@i{Ij?^Ra zqC_(cbB@VdgQ)?@_+FVmK~CoKeP$T88H3YBO7PdCm_#mJ<}!sDXiB+k>#axz1Botg z*J?Sa+WW24jQBKQ)hwi8Tof@|N&X85WjxBfo6cN8{y>j4m zWe0lulF;vsdGxjvg>IC`F}3!+n^xj+G1e*jXZzo(Bqqk1)TBdk2Jvv^l|HjQ@?rFk{^Jrv^RI+ z!MSbs1<{V^cINnvelm$^wQ((?Lw;ch`px)?^7i=ehP0>R)p;cHO%)4-<1C!yea`{n zuG#KpbSB>0OteVOpijaTOm|7(Jdp>B#&)R8n+c;1V;~XeHvf+|5}qRPm;PQ^0q1PzYxrqWqfo06x!O(#O2NbYF8C|Ve*;ps5i;nRLsb=<-M4Kc zi&?kS>32DD8{y092q?Ya!Ktiy?xtjiw_v0l%@@QeK)w)ug9n|q4P3V(crcxd81~h5 zh@wL-7pPk;fk=!3pc-qVE9Ps0@Jq}O?S>0(OTf1$T7i!AY^ennMiIT)yI>4;`^&f> zMIIe{BJQ+9AIcWi)f))Ub=#S*1TKMGJ!K9s^HW(siI&SCb1XZi%K`owvy*|C!>2HF zKl}BSV`C6^zzBPQBe%00nEq?SY@rbh7 zv%t#3YvJBAyEZV|k~2KFn7EGHEV^^+%_N%$_GWS#h38@~_IATE(wUejcKx$8p^k>O zGecIIWxrw%$-kbIyd&_;dVeotzrLx`b@p^XH|xvFyxQyX%)h>Z+j*8PtBh3(Yp-TptX3TJRvqoLs)bC`XtvE_$Bm zDEbzCPR)Ji;g9Q`Mim>%(XjpQs~7Ejk8X#%a=)hT z5B-tYSGaJ_+OMZG@XBJ9q`>~p{ZG7|d0+iGy(y*3|z*SmAcIiamDXhHaolfw%dx$aM;!A>@p=O;mgE53Z@k=+z&`S=aWv=f1Z*&8xta{k#$k#a&+rDAS8TJX-#$lKpUT?)^Upza1*A zn^akrOTR-?HSO@jHyF9`a~zb)L+$d8NN?2&__sKT_Pwrxjcz+_7E_58VASa0Z2vJ}d7YUTy@ z8u6TcPo2E9jLjLn3+iT{wNoA$*lOqk$fUU!b|lH5LKr*F&fip-%(Hs6#K0ZMYngVk z4{Ox;`C$Z^lNAL2>X%T|diS@^m8fs(Tl5E~ibCp{Su-!EsvCrCy}Cgz{LHoaV!Jrk zbrNG!$Nu~I2yHL_-bq-O_^9A!?`^4ZSBIIRN>=}#vA)DB7NFI;ns|!(tEc#w>IC11 z%YTGry(1lq?(kqdTqJnbW@;+1F2f8fj~aEI8=5iSt@q7_b$*mYc}$tu7E`h_ni2wi z2_OV6y4U!ozvbUE#Z1#5#p7znNbMrjNetvcy~3+M>MOD|+&jZXd--w2COz?&R~C zYV<#zBjsUwf?42U(?! z%ZXphZ;PGbpyvjDRTa~`{Wv=0?EQeG2Iwx%Awo>gb+z8cU5!#SZC5xHanxVL z5+FG!vS)J~Q&W+U%OqwA@~HF+=6wVxZON||-;`Don>@iCpMb8l=$!zBB#=F|nsNI} z1Hd?9ojeDlw~=(v9^9H75SCwPBDCTeSk-mXt5T`#{?CD7ZSUY02*9QRKiI^Ne=5kX z=Q5TBK3fN%>rGgJmvustuGP>%l3O*Gj8n+h3WAQ7fmD&(+R!1@b+Q&T9VVOKUK1sZv4HYFs3 z&avL`bKW?tyN*jAMt6`3QU<^ZlB>sizrau!$R% zwma7X6=hG7?oCsklrr*@C6YOgWbPR~cp0$3Zh0OP#XUv=cod{B8_q&UB_l`8QJY%M zU*CZ66xgkOQ=n7_bcX8OT0yclV;S8?+$^jO>oWsRlu@3cMpso)cW(g>(KyMdFP{U# z%QiHDUkn*>p!4_fJ9xWNMqcVH&`)`tyn^jo#qwz2koLo_ouf;aG@p6jyl}h#iXXfn+dxw{afoj0bVo=rug2XPZFAR`bB{7sB zND9u(d*8?Qy-0oF)&wd00IY=p$rVBW@%&I>=#ZVSD^9ynFe-+xMHA*6GZHN;epiye zfz4NjGHx#eyZ`B#iK!CYw%6^wL^B*>dN{1AH=rTKly0gMP0M~%^DYj_=>x$du5MPM zpvh-?g06KAbPv+6v7eGJG=TT0rWCi|>++!dZvd0&94nUG*&1~t{l~MMeV{x`dKau0 zI+mD2zM2f!X6WSi)(|xy;EbhtrU^2^3dQo{-+ktG$x66%yzfk|s%8!4($Yp=YQhp% z;pe@07f+yb#AT$R3JRO~1-wWRaFQL(ajmc}IzTYC-p-3rg5=WEkf3?=4#{sj%I|o@8geezTqpxHQP|Idx%XJ`CHw>veL= zyWjQU>&_?}y9-q;|GG0}D0u`2mK&^Jw|hdw~0tnOC?3`LNL-}!$8|*gbB&z;F~#M zM?xH!@nshC%%vNtCO>&Y_oI|;XHM#{)#i*QsSKSCrdI?Mm{h+|=phz%f>8cagagr>F^xCr$NwF%&|h3X6;jF7 z)IFloX)v*~r3VIBGxcY>8uTwW!K&BUF)20Em!>K|mex@&l@;@^?=15O2X;?#bue(% zyp0rNI^OH{LoC5phGY4I%Z97~8p+^4*cyhZs5e^Bu#q_hR#B=)Umgbx^HxtO#~Ej^ zVv0CayWxbay#m^J(|##(FKS0Cj|_TfkV0pMAmasqx9&i1k*wZO1tBEnj4qLxXhXnn znCU_uB3PhwXUmy(TYu|zXe#4xf%0)EPd(H4s&;mIM`_(ZqRpkuMsVa}T-fO4H^E^D zQvWT2+8W?Ru~nsB{`wc=y9)Z^ki551vta$&(SV_*`r`3$gK}%HkEBtLe*koPV09Rl zFaxG$G39_BB(v+`z$5>#vE~tu$^ikOy)tXU%_qX{hcCnQtOl4n;WAdgjVd%yh`P21 zb8qp*?21#_aC*}tb&BQ)=;6m2hngOY zbxa}Me3OAzvrGVQ6TzxL<8&8rp%o&1%2;aGU7`rJSUIs3ig^@jHv!Il@ zLJ%uY^$NY>wm>Va6$bM{M@~q@nIy3oJ6aJ#5OU%x@ z+4}L8N9@jGrzzr^yN<%%ed9o{wa;Ov@!y>sZISewbBhp zC6BCL2^7d+-?SQZT04;N)cHxw7Sl|{m@s3#4>C9o+(&eqS+X_v5GZi=AFN(ON69hH zt)j4xYYIm-p_;V&O&Xe4x?T)qf0G%`yI?NfYxn2c6ak-AX9sB*Kj@4RMUEUTCWF$j zT;YYz2_Fs!Q)lFF-h3@1Ovj5P*(VVPir z9Fk5gJL$^uv_*74E6IfnYpVkVl;Y85K`U{`H8u8Kj;c^vy&VL)jOinHuCyAha}jnc zrYXHY^m=Uo?cJNjS8W`HATva(KfUV<7`yKWcymyOahaAhv7u$7iN;V}t z+pv&7;bb!7C3&{t=)15+hyKnLpaJQL@=0O8+cX1f!iBons3mI2o>I^ZTw+Ch0g@u< zZT?HVNN_{6dFVmZ!bi=dZrs2-cl)*)FHm{8d-VpfH-TXQsGvr_evF(x9bhDlVvy_p z<6+Ea>_#wLc!*dG6i{>aXB3m7W(|;@Bg#-w|G|AmP}&Whs3=w- zWW~HrqH+z9pQJ1bBp15knryh|Rqz`2Z_3@&*U#86s&CXyjJFO8(++u~RJ_2R{2@cj zdZ9K1i4+$hH`aQ-MeK9e!P}2hgpN&Lmo%3)66l3}A5m)4JNWPF^*@#GwY4}3xNWET ziKvfo;fmz2NP2D@vI}v2PoC-3OWpqp@SNT=)E0ZOqX<&g`d8doJJw_>FR8XV{(hw# zYJfIDx#gT<^0$6TQb%1nTrn|ICMm%>dX^A3ZtPvmxTfY`c+g;fTpf#CC6IL7$ztQJ z;Wfd0>$`jPWtG}5D)wFJHQ`+?&l3KL)K*_DpVBV#drB?2?q(?@uWcfWtTsRW##v-w zsI{r{$879!e5_SX)Vz+;1wAm?BzFIeshq78u@AetX4dGa1ee}86nq4-yfy^elo)R0 z$h_E=S(E>Dqb=>rgMVE-d#J$&?R%af?YaQwl zq1$gItSQ{zMi<@n_NGox*19QNIX0G=9a0&FtT35x@egxdZQV+l=kLtuWbs{<#RzL1 z{3G#PsJMbsemgH~;?7bg=kQMcZ`7rmzFSf8Iyl2;d=dN0JM=979?;Nn#D+vp%bnes z3|*=Z%VA&T_B^<>3hAKVnP2}qVp$HXxbOhWoB_KJ9B0v;CMA8 zi)x^V^ZRiqKY-S)2KW8p30Yx~;wS&fnAIN-v>$GKeXI1q_w5fbxbxQ#bX47V%Sff% z6Oypz0~!q$bwZo5cu6PD_${mKH(BZG_}8rZqR$Q%pLC8$jbzyMTbPU%2Fq2*yLe`d z;QE~Qt!BH-3Ov>-3sD(a>g`+Z>2QEpayK1)4`eS(*Q!{S7i(ZV_bpoEh zYR^Q7UnY`K!JQw)Qe~uIktoNmr@_AAXV>h*GeZMyoID)8^D3o3rPSS7jb9w(UI=^zKh0Bcsl1 z488$pdH3je$nk=c=om_j9OMPF`}k<=xVk^rJ~cT-Heo}o!1#*6vieqq=0Y^*M8K`p zP}T$S>e{KISZvta@x7yR5q#U{SVCwLTr|8E?w(Y@wPSx1t zUZ+>qI+uw{A`+Rbx$iH3_T25~%g?*im?dP-u&Le|9(tKZMCG)loWP0u)F9>(B&ITI z9Nm)p`C{QjWt>21jLVs37`-%buJs)m0v-RoO2N%CD z+|TutBsz8;;N={A(&hIi#CqYkveMD1=7cDnW2y>K+Dg@9b(j*YZ@KF+y&oiFec#T; z4cWHLtI<_u>)~0OP2bZNie6&rPB<7DGT82lCOK|-9d-lO{>qt3@ts#XUTl-8tU1BV zf_2jJph9xsN&UWM4X4dt3F}&^>Rg|M=GG~Kc&C%JQ)#oRRq>9p(5uK0FRa#k`0Y4d zR>M$DO(jHn%l3g9)Q;-AWY7mgLNGM4eP_D_34fst^sUd#5u`@3es1WX1Ro`IWvGHY zU8}Y|g!qE^RMun}zI=bt6#zC$DRTVm2H%Y2#|f$6_!Ocb84Eg#IDO~ zA3#CNEMp;zjoo>vZQKrp+5r_7zk>^VVaC1aZ%rM@{#&1AMmSvDuz$wW2PNl#)21bn(4# zuiMFTz;H8ED_sc*d2VkjCW$g0guVnq%gti#^-D$lQa>h5`lK&dh(3DON!Bl6m1NrK zgZ|;bvW-sgKXD{bLkRP8Bvvf5{eEABT;VEg5&n)$DguMvP{nWy`V`x;9MI0u+Zj2X zP_VrBWq=ZQq0U#sj614NQ*+%NZHN%jpzr6qDVhAJiq-0g;q;eNo|b-1jEcL?vH=NL zf;Y-)Zu4^g7EbO>RU!l<872JUgiv2{e!?+BW<$~H;1K)=MNT~;v5VSpQ;o>?wel2yx*GXp3AoiC)+XGM>$Gn)WK`dU_66dR;qD*H`$t(cdS z2e?|dF%yl;s_zcp;eb3P4EiN#AXI9?u)RCWw^$}*7IJ4&oZa&}qJ8$F$aK2EuL24BwyEFU2deJIo2Y(MT}kn}URyp>p?v1aY0l}AX_H{ zYxu82{st^V$FT)ujMr<5BqIPS3SX*`<+ZVa;J%|x2p<5(ueGT+_u7C)n-KH*jDLev z`yv7~SCRQC1piXez)+e;6ENJr1)c;XiebHiJ|1fN&neP|3>@Z|k&I@b=!$L->6GbyX6;?c ztUzk#GLL@)x!nuLhKa%vWk95Tr)(X_7*3HLTlJHGHM|30!^HAvkIIHwW=8AlB$K{= zju8{+v8!BcL!ZnlcYgqC9$3k)OR9RE@)`gqcjsB)SjK}t|IAY4QR9Wuk-KMK z^(DcdfJtJUL=AL%FM_37=}+R=ZS^vb z6uSnv{nl=K!1s?mvPZt87@Gf`)r}wK+D5W4%hHFf6Xrn5BPb|nAM3ga7yAHt-SW<> z8ExNr->uTiPj2ut`p+?l)YtqGzsZnoaz-(ryvkafgO564t zZRWGvr+Ma{Fu9@44=e&OsISeubSL)JUytAo&9nq}Icj8=j*MRX+~MgDkoQlz$&UIG zXs{j@D`sFjMn5EWiu^UenaHn^Yn0){}kir6DCAxwKMet+c; zvzhyC!_KRx=3eujxXIIQBD2!-1dA0pTXK^$KW@>=cZpTY3M z^;qmCttTN_a9G=Q@4hR?rL}d{iHfs+j%AeEtS&jtt*CAN-0i%3LHP}%atj}!U~}QZ z>-0xrsJZ&B`JFnbyVfb!-fy`kbKvEO=MY9$395$ITrptUw;Y+~zp!F`HvUytRb|v- zIKcn(2m`1S``6fqzEc1;9QXc-4l=*&i73ZWPB7|$Rl3BHrp{&cr}mt>kQGSJ~-xW<%shevAdRr_M8J1h5|=H7p<-_+IjfmYjAa9-neqc3@9 z^Feq?%d3W2)J3eOT);^+X>NM4+fEOEqoPFNRa5Ik34Pk<4;yb#!eZruFS^LIS0A^+ zx*l#85Ra}K*sbR2x*Ddmd}(L8Pr%}!tM?pi64E~;nV1=`Pvj_vm4=(xMpC0DR-#T~ zycSc~rCL*kib{tjcm?i{ zsn2|udlO(`m$}!*#TFm3^DQAw(Ys>D`g^A7bm%V=SN^0#v{pAbwVrJy=iyB{E zG;$@wWxjG1xYODy+sTFf-q8Ft8$*#ec;23K_G@1%cu_3XpJv20b7p>%^#WI4%*Rb! ze3=Ori0(2aK|{;j&3v4nU|p8qb@uGEmF-)5@{2HT?xnwW%>K@mS}9Wo9r zHhPH9hb9hooo44G7=3%J_C)=B+lOs{Ar#m)AHT7x772H*UVXXIsUT%Vn+q&)b6YlC z?hBcHvR8Ocry3+PG;wq;l-bf40*v4IaSxeA0@;yYO$k?0K%~+Mr!Su3N7_RmANCbM|)yi7LWe? z5RhQ|#a#E#pF%u$4d;%09H1NWcNz5?mXMWMvAEW@T$RKML#Y}=XZ(f=AIP{$WSVIu zZ{6RiXfa_c1~rS4Ptx1EBxA;*aomcBI*H86$;wI0RuZVL=^Cp;;}5dTN`+n z>XVxnDu@4WR(=X9Bt2MQpWu#%jQ_4&(;GLhO(`5kh@B_Yx@kLnwONuFAKVmPShA5- z{L@O7mdip*g#;VJuZi8gdtYnZR|Q2yXaZzmG#jK2M$SSYo|NM)V(t~5{=umsFE2}P zBw^k`53PJY%iNLiY`YJ5(q5cY?B!uhk*XU`N59BiIp%}d@X<8nGzTn}1J~e?;7e`- zz3A4vcp8!)4|Wb=W5_1kEAjVa5_Y><(G4|L!x77)hfj-9`%WiW{| z1P$++gTY6Qbh2Mhbx3RG9`!x*b@!sikY4 zbOg2VX{yr(WUdfu=K)aww?jEaI)X%))j@tF1Slg|Xl;)@5CO1f(#r#>gIy&e@ifqS zmQ2&9M|fJKE2u1RGX`VO&68w93AhhXv61R)cR-Z!)V>A3vXm+9W!#ztK$WDph`tB) zIWiX}ON!*lbNY{GeE_s^g|aVbrW7^sze}mb>$Gz$Tk3)!D{^}!(C^@o&!9t6>nr`- z24JlJvI01k2@u9KFw-7*xq2>@8V;0Pbos?RS({)?FbBy#1!9j8#LggifX%|@iE28=a7-fqJ-{Z(i2icAsxG+ zde!rVK|gNA0`==5fZDj9D-F~)rdmU`=~BB1Xi9TXB|3S-Jn)A)sknMx@7qdh#50$N z6d*3!%(0_^$wyLHBcz?nRFT=dOv;x2*wR48g8ybnT2yj?IV&__dJ3$gsPHoIv(|gB z1vNl(UXu$-0F*EL*IEgD13Jfqp`(8qIoHST2Rr?JZ&S!;=G5G|dvC&7?SA;(Sxden zru6@i!B+jpIr%2(H9#cEBTY}Vq_eEYUTb?QGjCe<*IQF(>IH~QKPEcr#q|$m=uo(Z z^DZRDHe({a79Sv|x#Knr-23}`pL;OnzwZuUs_0MoLHNKaCPw9K^%AuRE?o?k54_$- zgHi7Ccu=1RD)&nh6EHieCAjcu@DFDSl_AQgm1auEimssBItd73ReA|Pqzv-#>?4=J z5&{IMclHCNb|{<&z)c&cx(V&gNw;PDIs)NEGEjO43cx(0h=wWf5uO2-8=eqNE8b4@ zf(@icIpXh>$MuGlWA&abDyF4;2`eAz=u2GM20@pLU$S=if89$=vG8J$xua*I-y)WF zS!c5NW)NLa(OV?yk2OPBfw{<@McIk_gF-17?tUZ3%@*9w=H0WzM%PBp0XfRZ8t79|4G%~U$Z1Y{#Oi;xtN77*!{7y|}OrDJq%jL{$+!ZsJ*-}U#mFXr}a z&vWlRpL5>ldq+vn5GU0Nv>M$kuZY3{vw50HcAWRWrn%_BddyCIys86ZSVmmb>!Qg| zI=T(R#kW0N{l^wf%sUU?@Bj>PkLd+(YBD+`+vF&SJ~o26o!Hp0MME`~s;kvkBn?5N zd=GJew1C&^bG(%#Vdp`n_-D-f$=G={F7qL^vY8|oMx!0o#0sRu1un0~0z1hDXq(6o z;2Iw*F;Lt(451QaH_!oI!;d&+Rmp{_|18$G;=1k0OrUWE86hgQC@tEeq5lju%)-~P zb|i2Vx}Puh3~XEf=5>hm{X}hJR}88`G~oZRen^`0K8wd~HE6Jn8_gy$2qY6Mcvhr} z1|uD+%cw}uJ!AuZ0!vUy4kcuflG?w$Ci8kH$pWZdPMnuxtK%J&YvBN8s7uOzjzJoG zl0KwnFcHCaB-i!)%pFT7wq%K}6&SX~LE>+sgBy1O2?pzA1%dVc8-zs}?nF@kBhsa? zKM;VONne#;35f(H$X!9g*=u(cIEU6O!{xa|&h8)z9G{+&e+CDxB(ijRa??wLE&b=y0M+3x~9u|9WidBkb9~KbEN;wPVUZPyiiW;5OpX z!k!Q~K`Kx<#43=P7XWZ`lgd-27N(CRnDQBW-#UM=D0?VV%NP)ExW!$I4oNy+nq`hW zM^9vwm?Ut41LV*+zg4ik<``H=rIw5G2;O@!l5wse_plFj)C9@BVWf~`ZwG9#gW1m} z)`%-0y6_KN z9uFLbY?x@iygb2^N=tZi5tv(25<5@$LT9p^+pg~zNdB;cEvv4Hk&EJOh9#tUC78Op z$#2`@wujwd9Or){U~%(o9*4rUIKbS_wup?%XsAvTmhB~I)*pyZjz>XL(#scF3;A}2 zc_}`_Kck1MS<42lQ+fl3ZHg)D!zg{`;i5KA@oN3xF zUPHOY&C?s@`j-} zBC$S|nHb2!vOhRRtJ7l}SB^8Efpa=8@CxMn##-`J zMnwAA!50|p@WxzyP54nGhvKc87jq{dUl1Y_$hNFEpYj_bvA>tSX1>k3WbJ+1zBwQh zOv0`Yi*;fl0SrtlyBqvOZm<;sh5DH4xf3PxX{^t(8`_G6m95A2;a(&6*VBVWG1E>v9sZ~xJQhh_qP z@MIU9q56LuBMw1;ZMGZzlucGS8GxYI6{(Crqji<)d56!5t|Dx9+F>tks;s)>LcRJHX z8}eeICE7(2X(Y8tM%5Wt*!Jk9_zJw_9Ui3@R<5JBwghH*gHfklBz$HvPA@eIVV^w? zYFxW?W;S2lE>X4fSXmUPOrl8vIMU&5i$Jx$^+20fIiV!D#cJ`;R#oBYg?4VGBV9{M zi!l$6#J?!lr=Ef#$AdN=#+{AMyl-1vGC#Vmx?Nilz0G$i;lf;q$+e|rJ{zr{2ZfJ{ zl$SN3X_BVz{>|TrZ91t<{(GrG&tdLy_uQpTU8*`xMAaRu{$!{w@sV4Z?^uUe17$CU zRm`+u1fhD6{xR=-)}UIr{#nmLU;j>{<2FSx$pVi2CT-#nq@b`a%8~YVeR@7#Dj8dC zGTf#Xwu+7q3NiX<{55+~1)aEyXC7FTJwfDg&lFP5$O3sCv$ck4O1R~@JE)u@%cdgB zZxZyj4wniQ0gmq%-$ma!J<=HRu33SYmW@2m1^2`%cUI5aiyS#9oP|{#ra8D2m&OLR zUguY7sBA*X|ADX8GVE5+2X{HGdND!|AJ)O8mIo{pKl1YZV4vq}Uk##{jz4?l=7Ku$ z>vnU=7-P02ows)LNaTMU)7SbOLRVoT5vj<_qk(QePZ!OG)<8k)eIj-?C^{TMxBpB~uQK10F4{!DUS!Ixog`iJtOm2&W3ytWZKnpViS0 z%?>qInLBRo<(r6_B;2n2g4z^OmYI5~sdwy0nK(uvM&rxKqK|lBBfEz9kbGypp}Y7j8&J*rDp`eaN{>Ef!tdwQ=`o5(!wgaqi)J? z9V$MT{r#bTDF$IZwKz6H^Y{E*A|gKc+3r=465}>|#Gkhf?B8scjK(H?y$#}f_a2jZ z9ELvI&2?rZ7%FkL-@Yig8RRvq#W)aqQM@TK4w_u)x^^&ZgvxcIx)gg_=Pc}#;=xn* zmye2If}%E^_6YE3f1jvtG`R6Frik-si3bd3Z(g!kWB8+|_icL);*(kf?hC9nsrXLb zMoC!Hh<9L__n364{a=c{6SVlpK2y;Nn04G(4gOy7|%iGBX8{f*?Jbt-c2)0X=SW&@ep4EVA*I>oIt~ ztIU-mg+rLy?OEs#&&dMX;FM`?j<1r>@8Si9;A@^ZyXS8<2uP!jSr7Lo^!jQ|p(i6| z)xrup%l>VVc({t2EyfLcV$5<$!8Mh4wR|lVf2EFXveO$A=u<|EUe{mKS*f+Rt2uVz z4;wQa$Pw-aJ$F4wIOwT%+vhMHMMk~T-RL%q50t;8Ub<|#%O}uEGkWrdfVqW-hfs*B zA@4r))D!Mm+cY&NT`!}k25!}F1AK+?`4lNfA0uW4LM^m6>=>(d~WXT{zW1E#~J!H?NR2{WAs*k z)2QCC((~izD%BEyy+s+&jsu1zEa2RqjL`n2O=;prwn?h;H!NJ=sBe*2$0fWbmyxI+ z1sjC~zNu#{VpZb_T}71|wev%Zh=3r8?=-V%0ZN3b$UCipk@F4lHhtQc+iuWfw{#N^PwtXhu)> zUyT~8Bc^v}eeccF?>1X$3@s(m;?yyX<;hYdQkiF3E(?YjL3>pbdB@4VjNHb*V4q>n zrfB}y8K?2KBt9XkH_;KiPdMc(%YQs%cc@M{;V*37&I+Csiy7Gj?o7*^VRVX0aj2@f ze}-u(YqS!~L)uwa#C7b^vy_3HZF)PsdQjxKsAru_d+`B@>+Ki+^2euk0pB9(5h_N& zJQPmo0f6FN*6Py-*!u^BC`cbA(8+)yTotxEgI^ysY5eCi zhku>_F6-x7Y_<^y=pPo1@C}rY*v2hi%V-ToX5u;^lE<$~ENPr8+g#&hj}mlh#20~> z!X?#LVaK3=gG8Bjl~yq~0lU|{Vjn1h2t zYOnZC#b8oORCy$ftiSWN`Ut@wi91CnPV zu&CGiG_G48L{V1gO5L~{^+t1s4Qin@tPu|$0Z7$5_fAAb#`Ja;Y!7JtjDN!x%Tpwb z&U=U}-NFXbW2pK2XcMIBEpS#F3IK8wmq3aFe8#Lr$?i}h1dPf!+#|N<6o@YhY*jZH z&?X~T=Tsn`ocUs+xNSqR>%OFzs5|ex1g_+&sv~#T1CLs*i}Ye5qT_pgS)OOYDfHC zmvL(NAdINr#Z-3b?j%)^JOQX~sCPZBq%I8$zv>M}pC4q-BJMD8jcdo7Br;MGySS?Q z&Q*Zj5sR3m0ICHkQp@V#K*WTuJuTYC+))sy0Y!lM*Is#2CqUS-Et!gkLqEH>a@hHTifkE-5Ct;8S2Hr3p(zeU=t4 zHT#dFJR883rzi082csNS*lY4u)C>T{inoQ~f!c8@kaUkRRBCO~Cf!{U6OS&rmFYa& zI-l2Gw1egbp18t!mxK;0g51P&URPA7@FbCV}j9ddO;*jMb?($iVUjSE2wawFv0kJ6ClA&#{M z{5V_svAbtf)W1vYP=KJPU9Si%{|?GVo`h)SdCgbnsxA-uk!r!`7}lF8xjG5L6Tv+T zbUgWMCck_T2?BPo>;6%Snvr_sRSeaoRsvFoWUYUc>8 zP`{BBzHVwmiIUlhRJMpu^>7}|Ke62eMvqQ3mx1S+2{;7yAJONl6UfP*kFOX|>|$Pi zjcFARHn{}S0+Ln5g%beZz%FdUC}^R*fEGwGKKq?eCN`h|Ry<^i_pKUoEn*E!G%=6> z>hs180pdpuHMQO^VQ5wMHpQZ z!-;F8Pz%59hY8q#FWbyb0Ue&8)kZb*4kYv0(p`lFST2mlE zUphVkJZXH3ZXy>}5-4P^`KYyO3IKeUgE5$&PxROTvImG=#C5|m>{6{3fj(QeDAQuI>NT^((=_;p^zs-Q0v7zWczg;o#_KB2kN2cg!C~N_@BJEJnHV zf0uvG7uh`vJ4c>z-u!0_34on@ALNXMI75>a6+y54+-*njVo!BU_rKu5Rw}ZU4aBhz zFnyEVjYdaPd!oLRilkh}eZ*O2hl&@M7OpTQHM{GLOktgPNe(W)C|{uL zWd>?{#v1BgBFDrBKccyEAQnvBvEbjY3f1+Gy8zN6PFG_}1u0=K3(NWRqAeyqA<27` zP0t^HCvkdPMM>kwiEa{B5m=4z3dh%g;a=BJ{8G%g@qtrbN zBFgVuMOiwM8&IzMH|U_}5Z$0YcHow2XFtx{0jLSFfR10#jrvX6{f}d}Z@+>p)%ALk z;-Nc1s_?o%Hwp!19mb4|+%wzBf_|2eCK#4cz_J`;6j(3pvh@p5YLUu5 zpfkBo)us~}SfVXwRWs3zk=kbsna+G!T!eK6AG%O+`Je%59lAag+sylk0zhffXC$~A z3@XBC41)0idm`aqL3}$feg||SL85|_J_HMaHtb05cb$<6P-I}FW+q}9ux>B1KsQ_$ z(13Z=UOKcxQ&OM(5fJ?;GLHt<6URmku*_po?LaER99hN99D9K^8-AsXz*lB?n#FVp zw6`C*82rq)=Z;-Tkhd5Lo;V7s#xv#XCNwq)#|bCGO=f)P_Ci1Z4iDr{%ZoY~ihFvh z-3C*C3WbQlPea|%oIarb$*5`clS)ZRD^KS8FEZC9Kb_HSx^RKqg8Dph^V5?u3A)(~ zwz)(KJ$8i6$>o;c2HDdKow4d$sZGmF_OPeV5%Saje(o1yO4BOVUm_FrILCoo!ih>ql_HgeWW;t)qiCi^1Er6l8X zJh*KTIlWy}Z*8pW4%3)Ns2!Y^fu>)%zbGS-MKop1#8#I)314n;N&9BvXr@2y2u%(u zsO1zx1`;0LGzH&Ks@R1h54vfJz5KI4tQsP#?x#EWDn%4VUYrGw4v;1y_D>C-8ll%P zx~tH~t^!fbG1k1jUXf92sbp$I9ma1Ia+nWkuI1@DP>4Z&Fu2qN1 zP;8svLvQ6*`%`pr7fGhl-K26VzJXd(NK7w)XZ{}LO~jtxt4>(5Pw>k={VV)Vg58e; zL!&?OSYGCN31gb_EZ4(d>_eNZJYq4Tl~|h1ulIOv^*!vs!AM!z17x?Iw%N8d^w!zE z7@)g8pD8gii_$Y3|Dx`8dfo8ouhzWk2k)XKR&UQ43PUMIzAdS^r3vW{KEep@Vx!l3dKJAbX@;DN_ zc^e&&m`qK;hqU#)sO)wKIy-L*U982Nh$26lL} zMz78r(c}Xzgl}eYcG*P-D-FjdF8ETKq@z&RXht&{L-n%xx^{lz7xbDfc!u`Gf4rlG zr?wKM!%)|0zk;lcDxy0VO+7`UxXKbDwK%>>-&nUFM zPA9}J+I$|R|Fu=tyzafBuPaeot~J`KnsQKKB;EPaYoYemlm6?gnmjwhJGyW^HQAA@ z1kj;FSI0XkKlg@v5I-mK$4|3b@>$FEEy0W0{?XA z{(S3K``7;I$2#_Smenfrerd}ISu(6gc?2v|Opiu;J%etQJ=j9!Q^5~ zFe*m9^x+Jiv+V@Tt-u9)TK1lObJoJasCr>e;hH~-JoGHaV-x`iolA(>m!p_A;a4**JefW9yvEL!S|JK>H}q2MYIbz{ojBTYF(%NgQ*G0P`%St64Y?Wf zaO-?k+58GIj!;-eI&UHHQu@M5P213y{rfoApgg_;d*P#v0$ur19~8$khf0VeGtyHj zGWW$b^Ez+;w)Jn)@Er8+i+8!djKa|3W~pxj`KHY=QC7{ScY@Lecrm7$Zbd(rKfb{U zNB-kn_&1(p)!^M(0<+wauau=Zn*#QPa$D*5AcuGsbGZNc_xz1XkX zJZ|!ESaS!WEgPn|Bl#&!gvZ+|V%syLYpx=3U0yjmr0^z#b7yX8D?NYLV!qi@Nm}^` zjWF^)C{v`sKDV}J^ViBK!t9&9s{EF4S)om`JYT7Wz4Gf9{w#@l+My|xBW;(^)fkeB znAi)x#T%aOLg&shgWZ{0w3x4e_u#&^QN>c|U3Kyn5Oqv{xP%V-zOlIEo}c|v5)yqZ9SvpS)n%h5otVU%hhsA|CjnE^~3rCFp-&QV?T$%FVJ0X z3Qi-R#jV~M)z4%1>*p?UXLorQt)v8o@vfF3M)ur|Uz(pNKhOvJJDTAeFE(t{lQQG> zmRDfzBW~aCPu?*e@x5cd@AL<+aNZ~s@H~+xxMS2sP9(ri53EqmVA5>OqWE4h6m+8w zeLHH`#xMu08W~-OD{tyJJkDrMZN=44S#Eu*vVliZr@?biQo2=*lw#dgEUs;5cNVo- zx()IFZnQnCcFlphEJ0xJXZKl#{^Ab%z7lng|J~(^8%8l?3E}r^KL!7u@|-L;538v) z8cul}VPuf11QmQz=d)r}QPDw7)}Q2w{hBuF>Ph-CYO;lEPRVOg6PR52`&pr!Y*W3! zxUv6sZ!X8)x}VCn+sFPz{-8+)fivD_jxtecv4fA;PsSLe*NcM2F#&VU{S|L& z77?oOo?>TyjhtDV$I3Rmx(QpKy?*dS9Vxmsb^Lesrv7{8x$a4cEdkfj=bB8NS4Q<& z{&H<|906x-3?kFRes)NQ&HgD7(?8`JOCo*hZa!pN+}5{`5X7_jaO!Z$RFIk8*7*{@ zT-xK-5tAhSg0A_Fn}Q!>W6~;=U)1MH6P1`(T}K)@`~Cn-a+!WrKCfa$Szsr#0L&_m zXXW@}jklo5p7}P`wok0%ZVXh#^j`hsZ6mk2eKS5tAI>Uiyi8M@xf<~tx7n;1<$o?` zm(+SWWHtK0p_L5pA-lVyX})GZN7Jv=McF+luRQ2Ct{tsb!131v&9&s^hWve8M8VJN zFaq?|^ylfGjQ?i!yKf#g-Er}?%*0%VH9NlF(2eU5Pp#bV01KNhTxCs5?pSTPbbpD@ z27L2d{pDj2lw0m*@B5NnjxmhyfZWxW4<=^cy!IyO6j_(F{31OX(Ce&i7O~g<>rMMR z+`#YfCP7}?JX&kw9=uek#m}eQD3zMl`ylOT+qA}Fi0O`A6qqTxOZ5y}$PGqgi3HTLy7# zz(7)ciVI?!oUlEq#F;Lt^>%j27rv;G!;mNB@-%MlQa7GoHvT|5c)FcP4x>V%d~DB| zXMa?w-i`cYaaR0aIo}cD!`u6^ghNy*1~y}X#2hY{uKB*5tqc4i%x2_2idJ*(oMP=>8_WbdNfnHn^Cr`f1eVOwy&qlAWb z$X(qrr&1NohJYC6*`2+f)MoFpCN+VsJ?J?XiM=3&1*b*BD9yjsDtB89;+5#5tjrzX z`um>;TLu&C-r8=DctZagvdp^wR9JWB^1B@fM@G=D{Krv^A6!?haIonFsB>oHX9csj zI5Qezpqlp^YdL({BKbSXY8?}JZ0{|0l5Xa)9ECE{vo0)Tt>J0A+M;%Rr0^qMp5le$qI1+y5nTt@z?U3V9Kp7?42 zrU6DUn5U)O%8gWz;pUFkt$>l(YuEqdFvc_F)u~7!5@M+SuCJO5hC`6mPc{7p%F08C zAiy#3SfOB|W5-ZC=5qy;;s;m{f~o`HDA4f4K}JCl2K))#s@|+&P*m{b>`Tdiet~^e z<<@xMMEIJbf74?cpx69N>33v3TwfGP1QKeIPoKnh1pX@DV#-Y-?LBM=TKWAuOli={ zf+W2Cd?BK9Qx$B8T~oUK?L3w>V8L4SWS5hG2JH4At7Zgx3k7!#-B4t5dJTPYs0M`% zPdh}g-S{8F$(EG++jeDJ@|W{%#>lk*bkykW0jv+?0)E+@TZLg3y8=veHkDdvLI+v} zFf*-9sQuyjYcv8$L~Jw|Ye^HTB!JT4(zraZrl!hg5iAl|^lQx$-d(c#D-Izk5!MY3 zoPHZSQWV_dPDLykyvM!*T(Unn2>)of?#=!AlM+%2u_m!SAjOB}p2?>FE9hx#gbgii zHXxW3xg5fbL)hJ9JAeG^P&kA7)2Xh1XGUgpyipFc3}} zK>?rkAvIrau#_|ws_lliA-B*t!(H|WOHy^{=$5!Zhs$RDj*gS3LXzdEzLrItB-e*DJ)3NbgXL4bFwgj&fo zIWyZ01=53`^FBZNCdEHC(H)KS5lBULDvF?a2hw)5#VGao=AmPIhhmeYS^;JaK9ipd zy+vc6C$kAE+2r0yq$cj>V_|Ve z;Di(o-Ji)HY)E*VwlrZIBn8&4nvtkza`v>|#te|iI6%!Gg4Jot+Af`g5%e6*7uumX zT^CjNG*TnrAv`>41E#}`1#8@0X{qRl4MVFUxoCanAy@74IVORcFPm=$-%Tdff<{K1 zuJdTeQ;ICG91(Q3fyW5|FdVElfbf8M;UE#)UOeGWx4?&dx?o}P7Tm3dTJx#<@I*Rb zdzeY=2w!jhbiHvy2tQ6QRFXR2iDe%!^n2&AHOiJ0N#6oj>d|HI_0vFpq9jRS^kce}YXHgD0@3S|FN(wfm z`+?6!!dSe6vG+DCAJ(0F!Dog9MnXHUL+!fUnhI2?eb{>?y z{KM;zpf4G?x^RsyjV7AaMi8p%smSu)dyjS^0|mpk7{KUBK*O!0_-AV?RDyEMI5(|s z3-s3Vj=|DFKlYl=<>LNXB*CDN?%sx2DB$ISFih^9-@YS#sL)UPZtrdct*q~aC6UR?lT4%>9h{Oq{qzSB9 z@+nGbPG-IIh}tolU)>Ko(XHd2r-g#!b+;J<*v?wcogm6y!R@gF8L9Im7BM)N2-GIE zZt=0!jlBY%z;(?|g2vR9h9c{tgLM3dg48EoH`!MhL+MtQgm^f+GhTJa2{FRnRef5w zEbw^S3U+yYq76Bjhvq#OiT6eON63G-Q8`tqFw)5)io{8#m0)3~K#t24x>q0|UP}Vc zm zW|6gHD$l8uRcUb$ErRAT4taQ$4Vo1>lpH0PR*613HL{A}#a|EdQg4izYtKIjK9{u)P|6*z(4Fop%Y zgHag$Ch2~z2N75xhwop@`5yb7Ud~3}(Ezm~aUL6qUKN9U!^xWDf{*GSs@CkV2=Tjs zdxPH;kM}BK4}e$JSg8U3sZLU0gSH633mGQRD^!=kz{z{Sw~;t%>UP!9f;T2Zf-W3_ z&1z1?fADq1EnSzf*aFlFX{zh_p4F7&X#nV(3dXQLj!&a9s0FErbw)8p6vpn^*voff zP$Z4DW6xfjsE6gx*-#Y7ICMzynueOZj25CJc1N1(lJi{Qp{S#L>l(;dN#5|)%aEov zxY#ewD<}SbGQrbm0<1#H^F#u!8??F3vm|0@4L))x9ti=U8jG|NT4Ju2c_f1zIcMFI z_z8TItSn87TgTrp9$2xWwk&zhyCugTqsf3lad`zGhTjt{ z3e+fX`1_ZyHNrFkdp{* zSR+_b-UhJ8;L~e*Z9mweHStviR$YVHF5zKG=@&h|iU_Cek6Uv4qd8snYYoCa8y2YJ z>2#vk?j-HTOqh6x($xh~505WXc0;3`GdCMs13%Gam#&TMl`mTDsve_lY+df1GK+!B ztt{;x!?beW*ekN{lP_Aol=Up==-tx$We2y+TGdVkYBZS7Wa#$uES%1dr&>Rwb_nj9 zhDN&zCeC+PtyG^-!z7%0`TvES+Nd*OQ}X{@_=RYX1YRM+hrhz2V@glKt9?B(Zef& z@0#kmOSu!lemmhLg)F%v;Z&;W86!n2-&ECq53MpL3JuD{yJy{ac1-!O;B3y*A+)`l zfPIjT4z8xWF6`K)N1*Rha87Wq?b*>1ZXqT*(LC`NVaC~X*1CVrIAM9x!LcsvB~l9M zbl~o&Eq@-~nb~vq(b<@Kf2ZaMmXpz@%b-tcM3mv=(fe42T{1#!;)K)f+2}iF1or7o z`1@66fcq%%po}@aQ%H9r)96U4Z2R6_v+sfGtV-tD*)aaeNu4Ogj))G^hWA-F+rF){ zeP%3Unz@gS*;IjN+w9E=5ll5g>5uZSn6{Mp0zExlsk}$7ni{=2;A?+NQ*7eR;B?CX_~58wwf4@l^T_?QdMPruj&tPq_+7>wiXyK?g)q7 z;fAs)>d&#pJIuSdZ4Wt?d@;#=n`|8x4>?#WJCyD#I4amM9-y=S%3Dd@NXL#)f4x|H zrUf&&QJU=-ak^#UmV?C75%{kn8g-h`_Fjs5i+r$o)gwE|g-8u9YZRmrbyXKTtO%-4 z^SEjuH5dP$?g?6%#Qetr(cHrQB0}E%VO>>stTTp7_1yFrFkp&lawMz_zWZXLF2^E& zsB@VNYaxWDU!SL5&OOPqGjhidPhK+5-P$Sl;OW|bb_t#;}~U8SYX zaPyCmh)~<3?y%3Irq%tD^&$uOuD#x`@1>z@uj$aP;<;kUzBBlzOYMxFTtGxb7Z<2E zG!M*$|2S*0`Du2c%qzTZSXdXf9-5PW&VNy?PXFkP^eyARL2ifnI4}$gyG_Hyl6aXvB{y*vs1DJ@k@^u42wKWbeJ+(_#i9Mzw!XqhuN1X&K@6ztc#cXU&@-kX3l>}wxVSAelEq66ZM zeaUPA6d8<91JUBRc5DU+!T3^w%cTBXAA0!NcB``O_C4pS9Pm?ef1P z-ZjE$dBjSR)PEdFH>XD5qlOg>Y052@yb*HaDZPf($xl1Z!t4`d>lFS*3ZvrJ>jXE> zCmHk}h%d`P!=%q;+d?pyi4$?Q^w(#5c=XlsnJXjH%b%iEkGcOr#dvr1xD-5_C%a~( zsL}x1#N7=-O#R8p)%=k}E7FPNWH<;s>H2Z@+MlcWd_VsjJWkc6NSqyhi7VQqOeMDI z+D*Zmg%q1pgxbb8imk5JJqC{blK@J}^Ow$$LJg@xSOsi>wqh3j2aigTgIy6GnjwK7Q}d8Wo|E&f7aF^(ixqEsEZDpp4f3R)4(C zHIh_A51jqPmtc7DY5-BMYNlIVK|!enR$T0jKUvZLN(%BZZ%59$78r_t+<` zIuZpqw@dEG@2I|@1pGUgc%zo40L^+|hM$)iOf;3J1{!b17#7=*jy2G|{M{Oe7b|@S z-NEJ5#;r5K{w+2UDX}9Rg!hj_PF`gnNa08!{{j{4T_L87stoWcPr4YvCmg_J1Q?b0 zG-Om^H6)gc0LTL^I2u;TDy&MNG1$qsN*>KF+SC3>y6Y7>l0QJPyUAnN)vf?qH+1$I z>A4tb9N#;u%NAn`0SDG7tP?~%&{J}SKNAsagnPfE&Dl%Rcv>u?&2vIkC_+JfSXv_k&x8cV$5-Re?nq?j&jxFbat)F|djZ}4VJ=f-#9 zwD_>hHpZ`%t{t?0f{Q|7Fdf)$vIRcdGf9OBuXj%aZabB*^RIsHOSk`VH>pWJFtGOc zXD64xVftH&2s=mnQ~VeU|gdW;L7thgsL(E z)%lz`ddWDPtOc5}L6zGLTqoG3u9U~H`5CbUR8{Grf)TB0Ma*~l!lxaXV|9zo2oP?DK#JSi-?n+>Q{pM0^ zGB^jB(5*IeV%(E|RS$pD;1mOaq%BEl&Nk5UU3S07M~Ip|0ZJja^2Z-kdVn`bF2!TUC5Jj)G~)m(Gyp+bE!i8&`x^Nc_INU5IK$l77x}N0Ei>%kN?^6WntU}=9^ zC&f=Kq?nF+=3Yk5PIZGxP*E$A91ps=T7gY5C0UH`vpBN=+!7hG+{p^-WY)6lW(}L? z>prY_=|(D&u#HjY&tL|u4@FSTLg>Fmnq{QBFsZcseFVq5X$3oqTT;Xi&*@1CXm*3H z2n^tgsgthW;u?i{fSa<9o8k_MPo$wg%+kDCX4LKFKtee{rNZ2FJNmMzxxEmG}(5pb0OK zuQHNODjLVa2EcCjy}k5o}Yxo@pFByCJV1Yx`pTIEX4uXFCu9 zf`ZL28k?M|YzAi@j{iOZNhuUknMhmK|75=d-4&oEWB@OS!D&_a1(a*IPFXRGByksE`5+rwnT*(lHW=xOt*fpR zgOlnO=jr(H_r)CB9u90COD~NE;I~|P;xJ!{f&{Vu9S%^EZk52@OvfvL-( zx_)`Bl98S!TPqE^Jy*3RUHIPNTc0j`*}c(?CEzNL%diETDg*HiGjVKbDE*r<;bz z`h(VOM-m48!PW8km+;c95C<^ja1AMTZo3g4v7^`xOwfYs&zWleNwqG#kS4=*f%5HY zm*$=aFispRMUMx0h+G%d;!EDf+`>=kR_A}p&C4V%>k8-y{}zFDg8RtYx(q(eNjC&X zfN5Po>c-tSnBc?rQe6}wd*~_oOCt0k~@Z5g1(#>m&nW-P%_PVY@Qhj+GTh17i=c}57teqNyC}>+);ag z|A!fprz0G|Z0RI%hAp#%z!Ig2SDc@xpRxeAVVUN|9rPqs+DO4O_8ZUN%u1!J8URo~kgiq1w|hvJCPCy7XPyw_CF zdd+N!lP~F~ez9eX?CIKbEjLZ3zBtA1mT(I$o$)nmlX3q0wmseUYIz-SscFZk`RP+X zZ*~m{`yD*%Z6qyE@+<8e)#9|fA^^#2Km}`LJMdg<;M*RE&}}I(pvN&@u{%bgC+aml zXSftd>?>xUD(`%=>lEGnu?CgtPGU;z$<83(OV;a8cewi~d**8Zfz$iTx}pDKuI6@G zH-*@?hlraBjTTs~P#O6Ul zLyHP0wA}hIl_{CQ$FuRv&JR_&~_sw-bs>-<8wyS#E4H~FWZ)7^y8^JTR{ zC;9aA<-5Xvwbm=~^@lds$u3wy@}azHZfVj+1CBK|jzYIJ&xN0VdhxREkEoS)wQC}g zUh08eTcLZ@0jXD%a!rrM%V~OZv1aY&f}S5)Rw8};^h(n$uF(jgQt8rlDKMPOh5^H& z>ToSXMt8MQfwCvSSP@Kj-|av=2RULUuClr>aupCU4XY zOqB4ljsQW%;Ks?&1yS@(|I@!)f|Rz}9u0!=V@7b%mPnIApJs_m|NAYmXnp9S9Jx>1i=3DCRm;MK$(RXrkew!jR_mB3( zeG2^b81loYME>kIH?z~)+by?liv|sb*TQ5n$yGO(-O_V-`22*<6)8#ID#%+Hs;KT~ zUaRMBH*oU!cBxixZ|N30$kpy8A2x_g-oIB^l3Op+&ng!=*9q!}W00mT%xfHio}3R#n?ejes@%S4m(pWAG5k&5K-2px(6RyuX20Tm zQ}rur;&h%~@q4ft9>7Mok1B4)SwfG~h^;gBpWMWfO_#5cxJCWw)qCXM=@P#;UZ>b+ zocWWgqR^}V?rHzC$og`<%mlLEtoVUb=5vdriP2B&LAA=Z{8E`G!$>( zgF*ILrUs?~H#j$R!#($mwnxQl#z#a@_Oohzy>v{EC2hrW$Q@QSG9;Z-g%SO^@AGQJ zg!Dbvob}YZjO0&`9C{X>>H44BV2W& zi(UM7`<_tz8vM$xMtE80fBYhQVsW4je%!ezz=gl+vc?Na3-$s_T*bS|%fi-uJ4I#U ztH&-`FB0av?$w$7ZB5Y!1bk)19y9YY*(PZca*9GX54oC8yw|@@67V`V3(^!3*NCe( zUI$JTsA4K&Wbj73s+u0b87Cy`6Sk9iUv=(#>Tjk#O?!gmdb9n#)h(r=5+-iGfH94B zw+~k0FteJDD69UR&+x=}1KOc?KWIu&CKf(Su!E(WZ!wqrMX%n`Jp|Grn za6g>vw&E=7%^31(iSJBWM~rQ4K~=-!#YYX%%RLqsQ^Yze(z5v@O?ga%bLy5|LR)H- zGt6iK(@(TR;-6F?o#vwu{)$aw#?tGW^R~R3WqbHUty?78+X=F?zRF>NEuodAm;+4r zO?3F$86B8oulGrVRJXh#pRzNh{I4eS_b!FKuS?-azY#gG5Q#D=cbf`(@E=DZw6p4u z{^_N^VXU5In+$^oZPd+Ul(aCr11S1U-&efsEUrUt9AUM2hIjXQVGK&?+bh<{!s zJT9LxylAGS{ypCLen9ueU7amN@6U9hxV29=kOtgo`kS+O+R5GN3MMD*1H+nD$*|Jx zTd3?eroXhID8_meq<_UqrsDz6H|W?Vyd2%Ez;@F^`gXWZ8MNmRZCY2u;-Ch`Dw z-a7<&_pOG%T}fc<7G-Z4*}>Y zD=0P(;pe;j{fn`~<{nUcUD^F=m3k4IyiLn%TLKS;nfE_)=UCqBZn~QB<;-CfYpIuR z+gk6k$ z%jHwpIbaVs4`r>~V`ul;htwRP;lE`$Bk(M`s?$^#8|kow}rpa;~Bj zNyt%-CApI1nER;YZiH+RTP2h;@37vj}N5{M)*;^C%TEDFi z$G^7M4=l$&@iDsBs2@%r6|Wz%W!W1ong(3*jdcD`paaL?O(_OOYvlWysDL^h_Eie#c|4Ju_Zr4u9NHSYd-OfZX@;qCRnsjr_1nix=wiDi{aBRD?D2AmKn!W8t(I z%5}|5^)�oP1T@26#ZJgsBoqfJEcdRYbw)#iw7KC$W5Pio6XjnzBbn2M&vxvqY|B z^KyuQw+9k!!l^L(vQM709lWKdZvFrzdW+m--g4u)5dRn0PSZ=OXmN?nR7&w>Dw4*| z1hUoj^ER`DnDX%>Z+N8aw8Az?kfC~E);H|vE5a{AhEVCSwqcm?GU6!yszK_`S39h*Bl zX8rIYc_jC)d)QES{oMvO5-q&trJVX}UC}~0c}X@i8)2(in0)_VHI6NB%0;9>8!ZCX zuJz^s>zV%doA_htPbXl?YkyTZL+XwTP?ak0H>KupcvPmMjx88a=^Oxix;Uik;Gfx; zk@}xNa9OS&lb4nLXgw842gaAZ6|V@*fWhJLAcUPjZ81%F!uEQ}aF@Z6-=C5tYGszsI?4 z8na~!M5?6Jn_N(KFz+{`-ZTu029e3b@=Q`9{+4f)x0rb!zSSprUcT3;_n!}BJ@py9 za)hz-TgSqUNzSO`(=0zk>LSSPwRQk|ikHpWxcBs^#`!cEHk)K&3JP8JQJ06*X6*P3 z@^Ab?>5c5xAV73j&`0dPkFV#B?of_Ip|{eCm|H0LsK`)wJ`U1c7ZRJ1D|Tb(5>(|A z1JZG;8Rl_IsSmr)ZymQUS6kt{JG=hd*>1YmW|T7^u7W1Wv-WmE6+pcB0Q25|uN78e z*y?x@1XihP+mC2Y+JavB7PDmKcf6^vatXvJ`w1Iq1w%X{HahaM1bn(2)bE3DZG`3# zpUo==IW;y2aR5K7wU6#Y2LECn`TbtSAJf%|%|L|h(Lzd9+_FF5GXrOX`Mu{&v&{diB{@Y;VYGCjb?(6zbl`UfNb zSr2wu4bw3(o1w9)K`Hr^K{}-lhKtt5_j@&VC8C(-v!IQ3AhwY(Rq8z0i&=xSQ?qhw zcfG#Gu8AiRVqSbO6X#Y+fM}@&J36q84U8TKmy#aXcxa)3L(u{*?dZ9{Zr$*@vk*Pt zpIXlaak~)Lu0f%tQ25aA(~HC*x6^0!xfjd@rzQC!OMo)^iJ(3PNxjFli|YO&y{oyV zdHQSb0|Q9N0|;{C{lTD3*A<=WM2`_Q!Dj1Vc*0E2SIO~V4d7-&frJIHTVEh~%TKiC> z>F~VYGEmi9^lwP)a%5WiO*>wOq^@HTV{azh(yu(^E#;ou+<^I1Vw!G)QC;pGtOn*A z5#R3h-SL!ySLo=v&z9P}^TZ`jDp^bBc z!dgsUMVw;hiI_(mKqY3fgw$jX|0f_yA1Pp>ao6mU9BK1RG$MEqYz*oWu+`gMSXiNQ zj}hBy3n?x?D;Le@6tdIFk^EJel3)F(eu`>1c+@?Ing3K+P3P~UtNhNxML)Y|>;4!9 z(zs+EW9Hh4ll6{rjig`BY|mBKf-9@8`=Iy3cBn47?ETo3Dz4t};tCAiwC88gPxD=~C#J*D536@o`fiS$!WtWmpUsSnvpJaA-v~q@I5yag=KY7jx|Zs4w0%HBxjv zk@2lh?3Y-p4Yc#xPU=PQYg)*Z*+sKujKmSKkAS}@GX3!d{ctL0sVM955wl_giA+0d zD^%~O}P1a6q-VMBy z^2~I{voDEAxxSW^O%d0o&G0-nlqHv)&~`O;%8HDV%WyCOj8LN}%#RpN{@t*C)_ucA zMm3w&r+E2j4>EMFJ7Pmfo#xiz;kCWG|5zSnV+VAY(xNoGm~bJ?>^(b{AM2x7qxa`n7fn16YA6r!bBX4uE|V708^?yyYeO)-!= zX4QVvmmmrWU&4LgxVNeO4d>XPi1lcR%L-qTH6L#5fphzH=^uAo5<5qsED+SVRK8LYru#1i(X6_o!X-jh*I?2G*S zEX1|QL;qpB`_zeuUT%xmTPwZ(GFyupb!MXxneIHkys=8MWU0;*bu7O(e+{BJlQjO~ zONE6c4!%6h4z8U16P(;>(7`1Rbaq+W>Xc5|lTE_%@uGP>{OX|e)1d%4!Db*JwY^yGVU7nnBx z2^icFv=nJ|OT0Ig_?(K<_@XqqriuBZV^KVmf3Tv&#l!I)KKc5Od$j|4{NTjZyv?-FFE5fBA`Abr^!lRS86WuEpRfn|~8r&nxR;cD*mLrY1&bRR{tTQX)Gs8IUSr?7} z1YVZhiSy(@Z`?b*n6Q7lbua_HkG3H^<)?FS?**>#Y>r%q4d!!0nsQJ`qVt!#kk5Ic z>n%_-$Jo?$yKXVgz){rqKTL}bNHSTarS+}Rt`m$S)#}Z!n~mnAY`Ywyr?8lt>y{0E zrqjlbYlC{rnx&XI>v>%}x$1jX%`bl4XJ2RgzWB^zR_inc=%?liD?Z4);YNEMwOq4g zn|RCiWLMbLMs2Xo5bnwNu>vh-DW!c^Qa)%U%iqW*p4P*B9Lh^4*1Y@l9Hl4%#A z&MDc^*Wm@pt5Pq~v^J55jXu$}+f>r6LRoIC`7d;Tjsx9hcwo&K(wvD1qK?PlAW_T9 zMX)T7%%0K+ z9)kx+y-TByx}w*??ge8TrnG;OVzQu=E?=I1UGp-C!1eL^k2%)w|bTyE>> ztzL~U;o%h~#nEpqFZyf9DFCOm4hV& zkE(v){+J#4`@L}YD9vs=Jt_34HIJChxIX6m?4wS|@U775HkLCYq;EnTO? zj)sLlO>{_?sCptIc8=h#^SU57aL><>vi&nQ;gN%H5IC}qPC3)xhmvC;8#G$dyWDB7 zx|No9EKwp1gZmj$yl1m)(8pSPUzMfX+4{?LZPQZwb8AdL8Sr0RSGWm%?eOQ)o^gi} z(M!5Z)0g30`bSSvi))#SOhp$kaq$dQK z8(!8b#&YJI^{LEy!OCU3y^MNlN^HC@jDJ>ibGH_HQaku;>(Qt?MmqTM(Y%#g{*&28 ztjT#ZN1N3%mEuu}`CkMli=Y>haWW?lJra;>&`}tyjw-o*@dG?W=2N71uZb%8veMM? z&-|Uf@p3chj*w=9^72T>-=?BoCSN&gxWRQ2|m^vxJvaosP$S6D@v+rtYf zgU%Po?11y1Wg-vUR{owblQM-xsiWI&Uxqy2(#RD7y3|wnly&^W;j4S#Ztk*Dr3H!+ zRGFf%^i@ajD2ZH6wD89IA9gj^uTI0(1^Mqp8#o;uFOwb94AZe?8k}Rd*cbVXP@Bm8 z%-4AzOTG+7I9#48E_t6eOtDtB)!^3Hwd<+U@-FZSJ2Qq7W@UAE=&Fo( zjA%;)yb?9B4a;(TY=7)| zSg(81&aDiJJUJ7k35^V6bMCX;uCGAokU1UIjwBQRlBwwfT}~>Ur?zD%J$j!ToitqJ zZTT)hd*YU*r42u8`D=;AEIZ%?(lcn2-_Dm{-OJi5ldJGjSTd$9*+AyhbIC(SCljz< z;WN7bga+4l{|T&^nzPRBbdXJh3UR%|PS<7`#NHS=d$)$9EVrdn^D_?I%8_z;Z)s>l zQ7Wn(bVp)cQx?U{oLULBxiz7ke|))|s_35~2sd*v6YG+KB|P-^ee(-Z_ie$!MdBm0 zr)ajYja^C+HLwECgzC$GqUci-00nS-F`f_`ESI?e*|cSRn}qd%(%JhpNo=-Fqz4&` za(8VprmD=SQ!_L;Bc1mvCtX{v9Z^RxTxWgUl-+w=0f{$>2CLyM$-dzh_;Bk4@`4ul zXW3pJ%q`o*v@8j%j3<8=Ft|L*-pW&<-=&ht#zRLzjNT?v3k3(vmOInv+NPqt3VXMr zIa+0)3x)j8ETHMKoz6d-KN;4!14s)e%BgsN#*os=N1wndT_$Km@ZRB;#_8ux2_zWW zZH0{tK*a+()YPoGRP|8@0hseh0##KAkNDoeea{`yU|t1BGC|^6(i&Jl*Nxo+@gyu) ztK4w9^1YP?^!hmMo4m~zvkuk(2L-9PHn+MrIQfL9a6#@7l3;aS`Q4+w>t})7Q&iS>0-l9iT zjaADNTS_1wRKiqRVelWL>rf6Ac4>@lU;~yGPu0-=&ad_F$Ck2hf75k;uh(#{o4YUR zA9o?R6~KHNLSpuT$?Li0N6zOkQt6rf4IzqYpv1QzMez$9A1tG6AO~0bNX!Av7UODu z?Q~#JfN==%SFSM#h^z^Ba609)L9*v#s()7b*l9~CywATMLf#DjqYd;r6aelCUzjn> zZCmhU;8xXkQsyK>wD@mLa_|IZUe>GeA7A0UBiRX#iQuHHcMSxdD2479s6j}e@7#7x z_d{)5h$967C##e1MfwEHb<_K}O3whff=6vh4BcMoQ@~VH_4fG64jXLYO>J)r0G|pw zya1{gl4$lw03;eH^x(W#)3~=T7TsU}>~N-=I|wsMr1%0Y@CiEpNY{6D4F&&x`Rjen z#S5-!&xG>bJRpc{T+l^bCWXH=!~;N;DplT;t5P6{mR&nQgW)cY^8vcs3?{rToQ>qI zTZ*oy*7HTA=dsYJXD5bsCmHHG7`jqC0RV|~ds;R-l2ezyEld3_DfG?`37#iJiQj)K z*<2|eU;hs)uF%8ImPqw_s8S7@ceiYwHA-f}--D^bN9I9dNk4y7K^~Zi!22~$z7{P_ zCxUO`&~zUDR+5CjPz}0iWUk8qcr_f{jMtp}{;y03?fm-qWSvhN-v^f12P1=TBQ!@k zY&i_W?;T=DygNh!_n`5l%J-(k)ND@c+wwMBfFD+rmG^K0ExLb)Dr50p&LaZZ1mqTC zs3)G&3eQ^}2~-VvmEZaR-hYD>hMn#oN6uf{f0{mRzG`jOB(01?_Tqs}VIgy04j8>P zLXy_-sVE--6IC(LV|_wQTs0fUgm-HzaEteFtqZ z*_=_i)mo5uQ1PMy-6iO}yFNfD18+kmp&fbgUjxsmNkcjP0+muGdQa9j6~E1H6a)9@K;gZmKMOyUjH$0&sd>FhgCjY|(fVnJ8Q`MJBQxD4q;@7uYf5W$m z{u8k8UXihct0){HAplD0^3Tiyw)rY|g!Ym4(SPm7S3Y#MQt5>EqV@2?OF}Xu5}Yds zuae_kOzP28HFJv^=bK^$2YUN+1_&YMx6dWCNySM(_Op;(W9N%5Hir0CJIa$PYwooY zkANba1MidYxYf|_E|3+$8D{5x$Sd(e>69~k3pWvU{+;;XyPi8(Wthkx{9^+uzv@)yQn`@14t( zb>nXzIqz5T?~b{}X$ghJ1)ZBBv=hPKTa0^m09@JyS^upv4)ErOm!3VD6t(EziOdTy5*>DEh7H$9Kl=6O-0H4FO*LWYK;cvhQD@$ZV<;L>?T9EgoKZc$V3W zZZT z?YKW9HZ3uVjgIu<^mZcsfLilxNS-^%X$16jKT-!A_5r$AKQ&?cQi&lx)qDkWx+aMb z&C9aOrUA1U%SV3O$*KO{?_Hpv#2X*0sIdSD$>*OjFDL+~SH2~04A>0=o5Pv>7Rd@v zmcljBhklm2J~6jS9a8JrXmpUG!C7&2L0|a$oqW-Ms{@%2_5T{L{Q)rd+Q2fM4G7)a zTK$^oh5Rj|@lXhSjYpj;(-3YJF-2poQ#%!-)_L?gIu!|31@D23$iJ3Vj{>$zX~(bY z+@znvA`s4)H7@lg*8`l*o?S=DpxdmP&qykF3ia1*BJilSs>wAKy?Nc7Yt`d~*GG(m zqZqOtlQrm6lmUOBX;%qd3LHb85Soq{lzML-U!Rt_+Qg3E)}At)(-yvsr|^w9?|l$kuS z_|?Ij5ns1P0=nsKG`=Jgy^hyLA%j?*}Su*yJ(6L$YVX=EQ`_~n~ z<9Dk?!e{t_Ghh{pW$D$GW6#nKl%U2O_Qg3)fOaw>j#hFx@9Hednb5Ir{SH)=)X=r|aSHfK(9d2K=8Teu@xD+~Z+nW-vwzaY9*Op=Mcwgr zS}P-dpYzpO+7}E&EF~+scKFEmsi|+HtRi58gE`YYU$B88MQ_^pM~5zMZl>;6&wdgl z|6z5<#+A)0)tMzYwEI-*r7>}7iM*Okv84|M-|+Puh8wc8`qu7 zgxyN<({;SWwzm1}(A>SiwjFBOF`M_fG|Z@2y|&We^h7)Q5gt8`W1&@V;uPgkLsgyk zel;c25*8DGN*^2zvwgZ?n9$oTk*NQtYE1Z9#jb3L{{Hh~=LZ6owy(P+1^Y_JsycQH zPmZbV>)zWX2p=3@D-Etb)Zv8;Z!(^&c^knz`YWkFj2G4(h=^`##_9aE)9idYRhuxR zE5-8f;5gp-9_)+hI8QT-iBnAoG~vUFLS_dKE-BZ&o(=HdesQ~uK*zUt8_=60iFS_N zUi8Y~-7wj@>MQF9!>>UG3eEH_8sa+qrAFJkblo3n=m`9Bav8-{cp80jPU7!ko2tG0-B&M+6J*e!|s zrx1z$6Wh9;0=D7Yym?FBV1mDDt{>*JNp${$dE~5P$8k%@eomifbX;C@V#Y?I5amhW zYJNkMX~?0q6V_9rA8K^9Gi(+4*c45u!`}#Vmap6DS<0+ZJ(<;oqhA=Cw(_-ZIVLVC4U5%H;uTB zVASjUY4v-8ubc}vFe;OACEXu9@2-G_bq7xgx2F+b9fl)l#9!tw!klc=9V$CXkDU{#%bPATGYr%nFY=$r9 z>{&nV`#4x9Uh8V$xQAyy9e~5FOovOpA&unv-Y=*_z9{%j1ve%>>b`AY+=~mCXBp2= z)xJ@S?79Nd`jOD*)Pf^eyGgEb^5$?)!0AQ5K;@|_J2LxM6z8|8WNh#r{+WAh*!g^4 z1q?B_`LJpFWUG6vB>JheQIlM2%~V(?r=;{xv3}UM;xT7(TiJ(^r1XW}?+ZrIE%Ch5 zEi*lf2wKHqnGu;c{|OwD8L|G}_X#Ygo)@2qA>S$!uV2vI7W!_yCF}%v<@j>1v8ugA z{)`2%{7nMz^sM|#FLLvBSGmu&ifr)3)yl&KVqCfCu9xGkD~mH4v8apG@Vt)DgGJ@W zxA*JsT^nBNra@kdY~*z$Mi6Qfm#a_ti?OmGl22Yx6>0jCDUM(Ce##`un@dUNy)Q?L zKxZlm6X}~*(H-XdCVz%1zKiJB5MBB}+r}w>b?ur_*y1mzwJz(lxAW^BHSJa$OG5tY zcx>+w@y^ zID+f6EzszA3`Q|A^Z34@1~IQQ{|R_W()|M_#upZ9;7ZZKzOh-H$VtqLk$R+J2*cG^c}avKAUwTr(>mLcU9I~l$@8HPf(a+#sOJ-fu*(zP8uDxKH@0Mnb%HE6Fm$1 zC-3fQJ1NcT_MufO6}_63O3hf&>((Lgg17QMD^216SmHB4GDK15q7&-W$FSxnDMeUf z(utk3#|%lB$BV-@MJU?8htf*Yf9Geg=5Mg z(IR2W!Ty(jn7NwOZrS|3M)TDtNKQUY=`oif^xr*Uzc3V|6y^~VZvk!IHt7u_*9lxj z1+0!Qn`T8U!`|*ThwJf4n8LdQ$G@p>ujcO3o5ws+%j z+gBaXZPy8I*%gGt*R%Xz)t&Jgh9#+Y4V`9C^B8X~b<~@WwF-XYnugCnMfHPAC^{H^ z_9NLB3lyhgj~_-EO3xfJ2)zIC@w)ht4qH~*U@epH^|O7hnG@H>2O%rw1X77PucCRIRBn+Xh7eyjQS>JgmWrec z*Y|2r2D!WQIah!N;gKgBWd=C4SCmf!*ROskXrcF?C5BJgIM=EQXZx>w$D*wMwOPwP zM7l8*EW&q`(mTM6&{_|)*3{eN0rh%xw0~&4ogW}Xek;=tp9aH$xYA=OgJkC#)qQpk z5Q%b#CEu`0LT6*ELsB-Mz3>ik3@1KmZFT*{zajE->s#Qk2?wYT-=k|7p!}tW%M`JTsxu~ z@-z_)#+mCOPasd@>r_6KbE%!{@Deyw1LVr~VDJI%q-$Li#5d~2Z;qfjv%fXy0et!` z*m!4tq;`Ugl1*<#SUIWH;eHP;fJ1rv)6Te`Ki+?B`;nTDd~q`pA=U@%9A#7Xp5;)L z$N*B|7IzUKDas#M8-)=EDbCcVtTL(SjEQLyAu}KSl1By;dClmq|MZ$8&2@IO zH0yeQU0693Z+h1A2RbxU*2~e0ue5lr+mGBu#hZctH-h5DgBJDQf% zvKM+d)Xt5fl*N=?tB8&ZSfAQ0Hq37Av;D9|r=l3&J?Kv6I=Eye%uX9=uCI`+z2RVB(am9?>b zK~(c*9FFqP@9&VxC!lO@Oph?Na4XniXk;@ID6Qd6{$3?DC#5Xm$S)5i^buf=*L$r43j z``9x0gI-ln{dWOkxP4}xwS43>bag4Tn#doRdi@CL#+wSQ@yknn^o8+eA#S;gURQBa zD}mYcA?Z^y1aEN*Z=ZwOB;$QvpP6=>g8osOEz#(e*bn?b7KR=E3g**D-l$KeI(Az> zHVSFEj!T^5U?uJbfet5liv-ikOzn}ZrJzHUfrx?zG2%|oDfezl;qrF3J|_tNdYMfd zP&H$^)CVaJ&K*b*hsUQ}->brbX>D~%LX2ImLv7~&C$LpUdE}x__Yo|`8;&lryknE< z=p_meB`qIaM>!5wtVrGzjx%yh4YfH7LSZE; zA-;)o1&FaWP8}Tb1ig6~6dyl?1=Ob#p-+)38>N|XX8$NC^V6eBM|@3-S*V5C){Q1n z5Z*0KI&Tkwf+L+C!HeknoUmhqe)DN6uF+UrL3UcC>dd{h=SzBvJKiaV0R!sJQ!L@| zx&755VK!r@tQ*FvWlinJ%+qGlcUvA>lz4DJ^^JM|NRShRd+hhTH5Dt^WiA|c_M01a zMAoq=C+qxvwMw>*om9hN$$3enPQ{<}O*57foO6{w$d_8_v)NpkcAWe&?qXT;cPJv@ z>kipmlMQl$!nbrrDYZiLKY`bFe=?Oc{2)l=D$KV1Qz>8G@ik5z8kN-uBcg>Kkz4GC ziT9EXZGAxp9yNQl;y^!*?waW>V#ttxpc$9wt3(D+xU_66tY!CAthGX#QYV9z5xrs7qfo!3=8x(4l?tOTXDfdX8phO0=wn+|wMTZjG!TDg* z`@wyZ9gp@tRpNtEQ=?*I>Dt(wI$v}yDvmMtAxjYOkm zlE>D`-e<$I%URdgXI*1{tfbXQu9Jwzvx|IQ1|W~DY|}=u4}R;ImW~th^&a;}r09o; z*S(oPP(XVV8u8nOzUnrM%3F17V-`;nQXWNz=S)>C)@BH&erD*{HvG|)S%eDvq-TlZ z!i#<%Vqfh_p4R=zc5+OWs`}gcqbkZQ# zie>9RAHJK>RNZmAT0+eKSgMBTcdxuR*pAa z2u-bc^`qy_?mNnjPh(c0Q;-?OyiW4=g|W2}{Ud%Vnwu7QE!d=v+;*)piRiv!fb4 zqF!DLEAJl|o;dgWuZ_?Tjj^rDsh98tw><6mFPrR;?s-=!)Z$3+1tC9Jyg{~72H}ZX z*D**y7PiR8q5bQSJ5uvP7mE4EbDbqvBKDhGYzmL zR7D%qVsNZtisE{v?op3UnT<0>vSvoO1fU}F>xcY2>f|N*>_{&kc3+muYcd{O7qQ62 zr=0tV3>D(^+Soaq7oUE3q+PvcGhiBVWuct4)o#I}c8sT6ZSxQJX?^%$wMDN@kXlW% zcM*zquf!dq+#Cnz$qQvF@vIFnxI+4DZ?~RQVflodjXAb1<8EW|*-sC$I9300D)}wa zFfe{JbKS7zsbpwmWo}@eyk0}-jH?*cqY50Q+IkwNrKNlzFMN@U z*?Jqmv>Qg>H!?7$JM2`qh3}*|hEwuxVuO5ehi4Kq4jz=(BJBXF{4~Zc=au55@M;R6 zr(ya>`r8XF(mixDwntucMLgYEFz8darK(uydp_pV3{s>>)--s}JWc1|Ra+pq?k3D+ zP%g7_bTE`g@h7&1N%}4Qv)e68hO`%<%=@j?D@NQSd9&gykKg8r7A<2N`iG^Tv|7j> zFgkD;C1Rr zLZ}?nS8APYG{Gw*z7O<}i9e?()?Unx~bhV_+cyf=#cIO?gbQ{suJ41N+hb;h4*Y9h*_n&}M+dO}# zUfE?=mZD&S;^n-HoDM#ub>#3dqsOrMlm7`EJ}G%5eD^nnK0a7Wn4lEG?j+Aq%n$bz z+D&sY2lGxmJN?encU$x0K}u;{jXHL`v?YEgJ9*^q`gH(wCa~l@pKUz(lY=rtyJWDB zi?;s^`Si8rrSDpm#*UO8DUR)8cPCTQY&B?3v|>)8(~c4BO_?1PXkUCkb71DKrP^==S@#JFyrOnK(wAw0-)!oD$}a!QHL)fh)S?KD_sAc+PZg zHKyl_VS#Dt6X;n1J zCcR7#IyX2B>200iJtO!!3(i5FSL+@NGi$=~dm3MMmXKX_M|PZ8%N)FZwM;G{H+5Cs zM>%hm_&J{uDttzmZ4>=aro_$bm44;5qajR-XB)dg6Yu z+%rj{b|;rPxI;6@pW&~olNXwKn-hG$5Vg<&lMEJ*d{@TvUagQ!M zFqN|UvXurHPFZU2ri>blRR_A=o@sX9;)@JA9$ERu`%_KAs~1EkoVI;Fj~3!z;_9t1 zUv3B=Wcgc;z8?;jX_}*ax5sU2em)bZDeEQ^VTVK?3^Vf5CdSKICa5n4IcoA#H>2ax zUXUn=KwaMQQ&DWhok;a;t^KYl2AX`0o!eN+;Z3$8vx%ewX2A!twxWZbe5pcDmttwvT0OBpciYO-xhTSl z+?;4$^-rYLufN5a=aMA1Yarx5Z`g?KGT(V*k4y~j9WM#(>%4!nj^%l^JA3||o=9@kWM2y<)o+&-qZIPd2wTYl%L>R4! zJzy7qVrB_O^z6%1(;%d0axSjah1FBMMWKordD*OrB-W|byc@iHU5Q`(^DDe|bI-7d zzC^@>y0_a}k4t5maP@XR(yOX6B#$$&C|8HLUuMIlm@@@N)7J}q3~nF%wS3jA_C_I^ z3fm8NiN(V&WWYXi>L?}7#M9yB_{_A}=LdRK-uwBdFBGk9 z>DPr-@TSDlgLbUZi~WT7V@nr~I~%bj?Df&YYen%W7w@D9{282OEuiVTu2ZrQf}S7g z%lHH;&|Xe}{%{#3vV$`S-~cOsR+LNk0%-Liw~vYU1~zgk^p$!Er>mH=#Z||B7-g!| zmc349@$nG>Aj$qt_#bF<;2D zI^dBuzmJGpuq_SyT=9aia<=H?LJgEM&#;o%*SN2jRJyL+3Vh+#l^uaJz=^qWrAiI` zgkkUKRX~Ka<5LOvn?rt1jH&)x>l)_K94eypwQvfj6G1P&XpfFSu4-&~xoth?Zyeic zr00tTO2r^X=j|ecOQmosOcta7)YV1SzXiWevXU`=`G&vR>VMPZn9*lArOt%Y0>~J~ z^Dqyhb?T$pY!EW>i7{fog|u+hWK=%kI8a395fGkYs&KLSIc*5`!+hICHqMfL&utdy zUY~ImYYcR%1%d~(98rU0ch_v73>^Wcrwrr#3;-{_<(`PQ|r74R)(I#ikElra?GX>jsqNxW5tX;>&%{HB5rV zcs4KhoH*`|-2kYoZcOaI5s+aI%SQ6G>uP2nz(_YH*H7^NiH4CL>r(Z+vEOC@E<<(g zygBI(6XFl6hBaG1B|IqsY9%jA@EeHAI6N3u4Fm>xdz|sVqH#^WCvZ(lzrWV|0417^ zps}-$WydKsX!LWfdrqjTqnt5%DiS%}S}2E5+)65(gmT3g$@n=b85ACHq$B;$@H3oHGzc-4&<689@BfIkTxXg9RP zG)jPr9r0}U6xr5~3g(yG2l2QCP;WHwZ36szfkngIv%>|tF1yM2geerg2FOd`lTwQ5 z`zmh&EhOkB5eqBb28)%iPzBA{eYsA3=ZR5y`v_1s%5_z=XxUZBe!g5 zJMKXFv?}b({p61o{GupoGw3t2FP)6@1kjJc%e7y3W>{GC6*&g@r@en+b1DQNMIBp= z7A4Ce&47#ylY$|t=u|}1{ZHsmK)Mo;ja`86$I;-JjSorlq=my^(!V1(sud9ky&70g zIlfp7B4>DD1)0*<;72%}W4tLg!=x3ibpwDD{6Ge@!(^>|b#3&BQ0*t)(jyO;6F}O` zrndSR>O@n@5|+0W?kaVMlL#%h7X1vM<4{EL`-6t$!BtB*8I%yS(vpJKXr;wF%fSL7Lh}} z{E8fBdB;^O1mXYWXSZrtD)kSLN$8kJRQ}=L@e>@(?YoYC(5Q@0yQb~aawNn5agn-h za`VrguA(_{0dig;tRe-7GzQ0w@39m6aU84=t$m8rT)kG!*MdFp>{GR9-mXJMeqi{p zh57s79PbJKAo?Kl!l`Cl!gJ`%U;$K7xyXQA~xFBScOdK_$9bagc1xNh(O-`S8e8i!T8#I?R!tkgUU zirdnhU#nU=@l?sz)-AWl*Zb%YVJ3l46O~`}q!D!vGzQHwT+Sy?n+m5lzAKfjcr3GU zaz1(V@BQT%qNHiP=D1Ha&SwzxGtjkv40{4)b9iFRj#ocAJkEi%fhSBAsd@i!~r z{wxuL#_Tr)rB$mj^?0NxXk@GVspC#whm-2F2p7V_FgKpC;{}Bp7KbYPeD5IzsA@(V z9v&r5U>!h5BQh$M2*BXxFn_y!M&*a1%*F46#HOSS!(NaL(sA611)8+ds)es;Zd_!# zf@w;l*;#5%%~q)s2pX3{CV&}(+n)STQ7hnAjGGDe1cU7*i8zX&2osYm7#@kdEE8F2 zQ)NKvk0A{V^$|Mx{c?UqLMTG22J=Af`3H#)!~95Q2$Hlpx#)4d9A(LH!e#)p+r@vb zn!%$fB`V-O;_%Q%+;FhB!c6O}2`!40T2gn)Hfp-=4WF3;_6j(rm@SQs@^85{@SZB` zsYPIAxm72Fo^GqEDDwNF>y@J5QJi*6EHRkWkeCe!IRL6zgz?R_5MNdsYLNbn}yRT%7R9 z7s7%`apFr@q0^AV6AG8zf=>F$FLpDdhMu@t=5;yTc=%1S756ZLcCLW0`xYH?O``jH z0dkjJJs>E0VNH#T6JW`gX(2yLFyRZwkBg6tI-u1i^Auj?%Uk_O=U!P?qT@LVO0i*z z>eyn3M0)InOA}Wb^tRHaTe`oE_ikF5%~c;@*hJ~*o3k%+N2X!61@nYr9p4Ro*f3_} zxA(p}e~BZQy2ahC(!5%NN9?`0l)1h&D@tGD1-op1?@Yd!Ql>ohy?$pP1m-rZ8`T2QUkST(kw&atbIR!? zh_9`l5SuMo{%zQ|af#LYB;)DLi$B*|Bxc@TypinKEv>t>>(|Cs)eFcAQH}HKj;Daj zZoGVg6>R%~pIWv%vQ9YtPh};%Y&M-*dpkX>BseRqLrNhRNRA%fml5la8)f757DQ#c zs20EnH2VEmg6*Gjhq;NLX_jWe7any*T(J97`J-S&P1kr8`3$S5!qCEN!lo`y2JB&b zyf!j)VF;F}^>aBY&UTk-B$lJqy> zb0LcpwnP`XRkN*lHIuVxmZSu+^>)rSm$V%_&J%M(4Z@dayYA2LS;O>^Vrzo}zjyci z?4R_x`##cY;M?w?+fln-oDvrhEYk`9Rd(1Oq#Ag>KXFKH7vJ|&MkpQcrIz(>%()Vo zW%63ZgTr5cU3){Ga0*2f4YX|(?#;WIH8kM6xHcPOa$@t2Nx=Fwm~! z>FVM-eJ`#QzkJqfPVUh;mb;hknom8-^_-!ygftf&&vr;5l#myC~2nM(FlENTZQJ4@z^{oW?(=b7<`y489@$opxW^Y3dQx1Uu_jkDxhD>H#=I z(w&|X6-eq^o>#z51!?T^?R{-)c-s-}*QOUCa(j)bB0|!-~Ai?mAYZeb+Xh zD-Cc$=COavNk&2=p-!?F#*fq_ocsJ^TQ1?6*0_*Y`;kq|+SXO?Mw7s9s{w6-9(^PK z?enkI6@T(3j5#_M*qw_8Zxvw@n(ztN^Tt^Wwg0(rI=87;jba4+(24+Gcs8# zBWObaWnbk_kGmRMymz&474d&@bzmt;QJgFu?Jx7^p`e_%;@EhCmRk4MZvm>r!0*Z-_7rkd0#y^v{%yBeI<6TxL~FF%l9RR;O?Yz z5)btIf|R!GLecUIeUDVC&8NxYcYk-i-I&bEJKVa*ha%1*KFNwTPQ#5C8#JS2ye4at zyPqe_PqjY#xQ6N!C)L5Xms(FCFA98Kz-miy99VL5XY-^=UO%)Ed=s|Xe<`XoNVuv-soa5eQ}!uj)mHQM}7TzYp@+o-;s z<24@8{1$Vrl+trH%a`Ie{y&<|JDlqOf8&~3@~MonPDKgHCXv%ZlD+3i_Bc++KF(>O zWQ6P_**o*#;8a$b+2c5l(XkH)an5l@zgOSu`u*2c*X2~_{eF%6dEbvaPVcF#xt8t^{$h)+R8Jn|K zHE(1@9{O`qp)@KqzFgq}jgal3Ku0K!mVG#!pitTJ%5|qb=qwWRrfQ+YAxEO)#`1;? zHWV4R^k7PF1}9YEnkxBJ%78xhC6gEu?{PXT@k8^;xLtV~eV%)~bIyaH=jrD^o2fG> zY&|G5t*vcPLa{k4>gBB#-%s)4x_v;4dq$@8Ce0hXEWtY-w5ZfY6yPZT?ZwM~HSEmV#pSpyt z{Cd^#k%<_`(T*UYO`{B-mz_U#&)wE49;jdTU*s=iZjijEPbw^B-FYwUeXb|CNY}EX z*w}iv=;TNHUMdbf)KD+Atjo>|L?1_gEt!vt#8FIyjoUi8-_!_tF6}9Gd|Wsuw_;RP ziVD{ZjRQkIyy)ykn|bVY{~v$wDV=-D`8b#JAMtTN48Azp*2w(<1tQ2lP{v(JSO4)U%K*}*>_xJ=ejVzhAUs- z-^z4J)iVkCnW?nBl0)>QmL0L)1$idnO5AU7(&y!>*U6gwbQo@?DY}qtP4$um|KWLA(Z8x#qo1;8pV_0#b74D@D&B&) zvP-z$dPqk8N&vak&peIGGWv6g1SA;OtpD~G;JSSD#Q^*0{ZBvY?V@pgC7&YKAaaai zFsDn9ZxxpW_c6U#P0yHe979D>601B%6jv)cR4!A$f(r=mR&XVG=w$OBD;9L=Ls@H0 zPI1$CCA>}nf3_LG^UM!_D3LwZS8-?VY#(rFAKK0DJWtmjrQrYQJLEl{ik`Ly@zts;&QsX$%+5XI&ZB1C%x>EV6Utf2`HtRvZYN<|L%M;C@Zyvq4z>0V9i*#SWH7bteIK| zk_R+;hQE;tZ{4~b=s6*aa;If5aD?6LI=Tlp47B;sb2`Y~^-3Hv$G_K+&~pgubFm}D zZ8)NtB~fzTY<>X@v~|RsL2)~VtM1vb7HeS+RG6tK2CSS}uRZ<6{4xIqnoFD7010?T zdc3Y?!2t8%q^t!;s+q^l9z5r?i-W%7Hkk{(2CZh)nw&_FovM+xb7IT_cNn#~&oV7lC!hWo@*d+H6SRxRZF15KVo zB*a{PZ&DocRh}9TZE)|6LiWSHO#!eCltumpHfpFMv7%2KM z2fADhM0~F`=@1{*^u-c7in?e zV{wO)a*#L$|4&Ch!wA)f=_z|d%49ntF_*CQTZS>*@))@7+}%5UI-ekt>hXr^;TQ?K zQgky@eK z-@NpRyTm}>Lp_{PtDsGip%!Ji((B7b9I@~3Po!2d%5>{D7`WEkunfRaYJJd6@`t4W z)z9>PJD8N&(A>|Nr9j(_l~o>p_NwTnV$dPa1Tmg~FuW4q9EkoJFvKscC*n%rIU|)2 zHmyA5j{4I84M}{mwb}S0_<1#J1N+eB@Z zApobMRR9ZMr_F(S$`~G!@aF8UON?pDjHp9BBC1e^;Ud$;MCtnzgn#s2t^S5o8Ojhu zw)C?GYUSVZgpH#XeRPNcnrKMYR^8wg;a{_7T^7;@KqFbeNC8>U26VHTwd|tbxQXPb zSCdp2Q1B3VA8SJP>SSdA7sGS`YaJcA_sd0D^GE|vJ-pZk7;+2ll!--w3NO}*R{g2< z>;FEwmqT_R!Ts`xXk~aDp|ni5lkdhulvCopFFE0X=p<9j!;deOwsB+txHu$0fqu1I zh+Q#=J*lD7|VZjFC9@y>@Pf)=3bwrACHwpY-usI)l^Xb3Og zNQ(LJa~pbG$fMv8A(kX;LA=RPk&kwO(Zs@V-wDA;olU-uG0PDn)crh1`4XZ3e1Wp* z8QPO=LxCW zQ#_J|d&fR1ImfryTHN&LLv&Z>-SCjQjo)9Zl<(}Vu`-D19a|qlX_|M9Nqk9=!`Cy3 zWHi@3kh}U`D=IV1=?fN%Y&>Zb19V!K=XpLB13^Wij9gH_RJKzXkUYuRRkI=PJ)`PU z@XOfzF%w@29;N&UJiGU%FJLF@$j9Q^&4gbk|29T~AgbsBeMcYMe0?}63VgR0Rw05i1+w9iFbAD5g5I-m&v`|AWz6^ z#9CM=O!HEE0<2il76~)*RbjyY+UcQlwggG^2kBdQ%VXBYuA4&W1?7U?xa2e}0@`Y# zbFsJ_$b?)L?wq%ZOLXu>rkyn}3mDLL;6D?BG_zI$rNLoCSG=nfJwc$lnJ?MkZb$VJ zFmPbuR3Xr<6QCJ^y%6$~p}DVp(*9D>MO2bY@w}!%Wtg7p5SUU4jv7a#p_8=8b^7L6HCm-> zCD`>^EzE&zSo5s{LABV~6j9csUVDxcfg0u(sUUG4>{IL!(J#^o*g(Tu3HN!;?l4DY z?GskYWRJf%A^L5?a=|Ca+o zlS3Ni6Rf9rEnRHoW&3NNreh+nX^5<@!o{YYOP@!duH07;?f4S!``cAWXp!T;gXy{Z zH$15LExC=jRhUm?X}XyNwmh8uJ>u8p_DDMow6B~ppLIl_Y0(up% zf7dGeBrNlGMZ^YkYO2m>Edzf!SaVLYJ~jDKJliQWbn7=Hbe8_;@VPS4V=g=UA_<*B zCp|klj6ba~ZkP^+;cp7v^l0h-Xo8Dhu3kzEGSOFo{?`ND z%Qv04MgSi^X@B$+rJ&vOEk6HE9$(Aj1_%6;v)A{=-m!bLs%k69a0;SLAg=@G<1;T6 zeDsB?_>?TaXplOyvn8lPot4%kT~3qQEgw(}_Rjs~FK9C>)JOjEj9c`>fp~ngZ|Bh? z4OWaF)0R=Oy%qi+VVfzl$_A$#Ud!yt0itE17GQ#v4Yw}J&Jx@KFvZOmUQf%h;7K9W8AZ_8$sQ3 z2Cp^5JYoV%Jpw0_TC;HKrHhoGY_pgLW}YQ_TNQ1CO75+e9{r!8GkNF(Nby-|M}y6{ zSG7`n)td?mN~I^xSv97e5qd-wjzQ)sMC||zL3K(ScPv}8JT7m=V)Weyu>@~E%3?)N z5HDiBVhuJQH$gS9>GjhC5i6JDyRU_G&T71h%}R2QOuFH2?1xn-J37o-l#ZXb&b=@* zg)+C_Ihm&T&NimtLjB(GWK-&KNQJec+w-fPU%nO>R#*^@=@nmN2=FVoOgvZjuRwq- zN(ho~b1|ANz0AHyiI%&I_&g;u>AlXq&TBAzcjdvZ(AWzPs)$_!Y{Lg^&|EEQLD<<# znIv4K65*~+q#=iX-4^d@$A7-A>h`-C_mf@@s)Rx+p!_(eihW3rP2sxAIq4gMDSJamk(6W7eX>oC^i9dwncbKdMuoI3HY~l2d|a7$m$eb4HfdbPUrZxD74Eq!^9 zuBug^p*Ae?E*gJlsPq~w)eWy@YE4G-Ra9;-1HWT|_P3d&iiew!waEDmZjWjkOys(^ zdIjC{fK&%6QmLDkGAr{&{i2G;jca*s&At>Nlt2E2nM7C~HOf>Rt99Do;vYm?R0`uZ z2HBOLvsD-C$L4u`eW5WS40Ol5T?*k|Ba|)OK(sesMxVa_#oedp+@vPq>`ja#&2M-N z59VG-7Ow&H#W}-btU=4kQO;L8 zC9fTtt4&Ub_#rVykeS8k=y~DxAk|S3-v^&ZJM)sdWWCe2VQ*1Vt3=+~qKX~(odtK5 zGdvF#yTikHLyxh}|K)h;+j7zxsKqGB6%ny7cDfIT;7=J+LD$BRp`>6!)XS+ODH^>n zXi&xOkxHzB!6%}&o6BSN-Exx2(h=46kd!r8=w|4yqROZS?`A|w-g3zMW&c8}O!?y# zwem5=fj=_FIO4+}srIRjku)wltLFQ(21R4U3XA5%ySv3Dv_?NTk+0+rxhvMJHr`z0 zmcDw=!_49VJB)icix2$`%I2ljsg4?)tj(I_$<1=XCYe1aSElCQtQ!Ls6Oe(!_eY?v z4qv;5RGE+C4}zBq)kn+;hAv$YTRgVE4X>U3IBXRG?gKAcR$<4RZj9NB4l&hG4*CZ* zoK8Q`Ml`jGPk6qg^fQIhX7@c6-Q;hDo*FNI0(&@|-69r3j(1>I)5f-1IA1XXeiD^! ztjkQXX5pIPhCBkt>6=WpKd$n4oAO@*U5S?S0}0-k!vnNcU0|(J*cAUB(xI_5yjHHr zYGqH*X%&K-MCN}fyD=14>SznkAW~BZnWot6GX6UxJT1rX&+&AYD21QNpRyacnUyS~ zggX`FoXZwA&`jIS@xF zp=&YfzqlFh0#&HmubK{}HY;$~OU=Jk9y}RP)O0dgukS@0?xBj{CHSLd-sc;`8`X_D zO=z)_Ee*4FGHsj19@g-PPjA24WIRpfW-JNpY!UP8u6<}w@cJwtW-ECe&nCPVr}~K= zn>xc^CeRyF!q$WIaYmqBD)@r(f7#jEbR#_K7fd3~@5xy2ZiHu55+m0hN6Z7fkW_?V zwAdr=axPT=DzPf1HSRR`pSZ(I?i+B<2?O>WysZ`hTpV1Y`4uX!Uf(Gbi#4>KUN^lN za$lt7FUNsDU9-{J4R5loBXb?DuvU;ny2MX*-be(-7zH*KnPDbUz>Y0*+uaXyrBZ{*GQ(x_QZMy0&rEgC+*`FUgoPgcAwdVb`O>}G50hh^(JdH%l~1@RvQ{&HaQcv_Yr zCav@_9?Ea}mY3!Osn9$2t2^OSuwI4vX7uj9&G*(~A;~YL<6cWU*-cwRC)Rmh+@=eW zSJYI+2b&_>r}vLC51@DL5IVz(MGWa-E)hVS5p#&F|4}i*9SJ*xw3^vCTGmqFx?p#| zSM;@&)6uNiu8$$E1xUZ>q1p{jR*7B$-hAlcXpfv&U;sYHVZBt=v)eK{QrKKqvVADM zB<%NjaL#BAw1@rfAH;>KC$E2SEhp0`FU|P!B7$^JSOTH$}fJI9B~x#jKfj`O{jU~S)*F9G6X z*os}NpE419SGWfk*=<&&a{6waW}+(*)`V--H=~;Z@gW09e~UcI#>zk%`X^V~hDx}r zGD_GXCXNoGvW)14e*sBHM^RVrX`GUX%lIytfm1s858Y zhJrO~r#i8Pi_5SJJ3O4S#KwB4lJb51-)c$bxz1cz65TpJ$BN&bfO&$)j4!+>zkPAt z?7)T;XqeH$$uo=bkqoRyu;Xb7A`>P#sOeqY!04&rkX(1}?`4xu;F`aJ8o2PH_PRPw zLcTn+`}P&o9IhQhq8IVgS`f(}O4WNHjFnVEAQw)`&`=8buL`L^GNvS)EdvZ>S4(do zhi6|*p?Nvv5rh&XHmz7?UjP#uD1Cp$s-8g%UC7rtI*Cmo0m{!oB>ipXKUa%m4zio6 zhzrqT^X4x4GE4p`>My`qmr*?2FWXARy`>ec@mjEm$vKjjoy`FR`alCAk-aqpC{VrI z$YFUhNPz;tjBojfEqHo8-l}{VX^e?m2w;ohO_WjK;XeG?oc`hD`?76O;1Hy{RolG8 z+yTp49l!rQoRsTPgQ@O|iyLq{swU(9bp$mKedC~<#YP{Pp?TCx=-5Jrv)OhfgoHsKMY(G-^pg54p*$t`;vi^tkxjr zMR}k%z|9usIw)rBXBHDfr!%(c-PC|}webCcOByA(CR`Ea?dnY$14Fql>el4ao(t*=tc7n}A?tc!B*m+0bUetT5<8jG(V& z_`l|9KL>|d^dw;e827d)8UW(*AS2f+j8vpLS3c)g=YjYVdrvCk6`V%K)nwN6}!VJi!qnxFwpj=*3M?gmf z3Fzm_1{pEf_rDI1e@}IFx_}1u2L;rGL-gXquRtaNVMl;s{}idu)&i1z3)vJtT!=3$ zyS#ih8TRl0K9{gv=#0<88p%qFp4kF#Q>XiGX_b^C$UO#{5}xvo-AbhC6Pxc~lJN%9 zd5OL|)()^)d@UG;NEwY^jtqn~62If5c}m-Z=_qrS+h?2iVRv2U1l5+$ij8g+Gw~xY z#b*dds6u9)^-)U1W^kXVfW`QtzX8aD7w*+wQUj$kRz^um%}HS`#Z+Fa)IhJ=v2b-d zgPZKbc*;D`V1qavq&(lIwLiRW~zZw2=^ToO->3Y##G5YxJoyZYLwQN;S z@2e@`40a~47AiU$pfh!l8u4dO8L9pi;VS06@NHcmR#vd!9l>Wh@9%RCZ>F!R3;yNc z6uMBk<-ZXbvheX|1D}mlZo`{Yk$SZwduQTOG=|wZ7HbocqZh{R?r3I9`hrTvsI=eo zmt{QcdjoICF!^83@YT8sii0pO z;YFjZO;^mhjd!Lf$BP9kN*k1_+6~LCD#ZdCMr`n#Q$XF2Qx-mKCD$mYBQsr#bfKg;}1e z4l88>4&>RXoug-^96i0+J9iftqkNH@Io~HqQC&)9N&{QP%l?AC*VjDnKm^?RjcVQz zHN_;cO#@WHCC`t!PK~_hGIxrbsATWjI?wId-@jQZMxzi?!wxf zwK~G2(wNF?7ZDlWBt()ywxXs+w*Rldlv-bY)}-Ku1XOakjASjdaqS|&(G}NBhL@`0 zf=a-cCl%hm_#o_Xmctr0LlEVhU*l2I53u<9o~v#nHa%|=X;wD=Hxv$aUUX}L?S@+_ zPn@ps0hNP8e3uX#a2VDElk~ef>@&g0Vu2pnZAiF!6?yi*7v-Z?C|8H44h*h)LK+4x9--;ZIK_Jx_|LfuQ!J5K#RUI1c7Z>sD2Hux?bl5A0yjS$o|N4ubm*$x z?_+P*49ZZ3v{m-8p-tGF_8XocwQqsJ$BuLVvj#k+b%L-b4S z*6&Gha?%dCPI#uUjA8Ft)5Yh$NfeU^6+--xu!=#aGT`vSK4QIEYPo_wrQ|X!7XG%MbFcj!&$s9Xwe5tq|DGsU z@a{>?;*KoapTg*d-RPK}Jd0ZR0m|XSJr%=~A_>+-j+Z=5%#RG{27uG+5wt7%DDwE= zEQZ34b9lUbx^3_qLI`pB7spj2(=(lP^)a8DovB^NyBIROX@3=p(vT##y^koV3_a+`7``X;W?>R9nvD`!}Uky)iA3d*F6(SU)|MbL(U2daK7bVl*#doQh9b~&`V zVfhl|G?8ptwo!}28eujaP-F?OOZDvz#0?dw%2uwyv@*&ZfxS0)ZIscD!|K#FWi_^Y zga~Lqi4WxEWDu#nnit85;TEt}lPA3|sdYo=qA*i*cfMN?P-DuTrwuy zZg@0$ZLVhDmkwiPFwPJt%nUL}&+mq}EA(8&g#yL#^NflMt*!r^*Hzcmq*r7b%at=i+|>BmP%JE$@x*x#g=B8Bg2Dvowi6B?F8!uUnz2RRk$$4MgH67 zSFc#p`HHeYNL}1oj_YRVz2Vw04W&5CDv`%t2dLe#x2Y9&QI9kj7?(LJc`ZbkPLmDp{ z>_T_dX)z2dq^1FHP_nSfH;=CeCF12cHs75L3{8-Vqogo-?%t(oQ|7u2C~+?o88_h$ zr>1Owz9^mXB~GiZ{w&5FM2REyS(PpFmezKw>A5$2^%ft(b)v2t`aRP|KOFm5Xd1py zvmH`htRyNW&5SG407sB->TF@8N+tZRWq8x=prS_IOwHB`eSL07Ch|BV$fM;<3ytXS zIm>mUqf>8a_)f>jEvu}CnRlqqEq$yy4XKrn0u&`&EBfg8igj{Dq4n!@OLWjc!5y0e zs!H2n6_=r10?*Ww)7x!hhBQ>)?fOWy1t!+?(eFnf>J{Fi8 z;Wt_9vgut?x;(mv#Ed1{+}+YV@Sx|-+F>6n@iLtQHNN{b>>FsI!0CPCuAd9h+tIUc5ih`Gu~nkvoc6 zyTmXD_gsM%hz)bOHjHp@Lt?pYd}LbjLMB(jgr&-Wh+n%uexdC)ZaG&xb3 z`d`fNqNO9N@%E;95@t_VySfV;2h9zQKi8^gTmc|Sb+a<=N}5(j=l4c0*CSs#1RkO< z(2ngw$1%I9!#FQts4c}H7JgwQ`{Q_H-+$Nm&z_Hi`Pgey;@C$$=eQmdWSX3dCTKAI zj)l|rPmJ$9g~Wt-r)|c~M6R8_3_IDY@<#o>qnz$l0hiEm|%DE5%O z0+;WnAu-gV@9GRQ?{)Z*NoAQJL@U)^a?I-wUP<0|8qCf@6JZE9)HMoq&4Lou*T-I1 zaf$D4^2zM?kq`=BJA{m+sI(ac>CV-?EY!ahF}dS_Tl<$}L_S0Jvl;5Ro;>e(egng=i-%=yj$MH)I zMkRXUa`_4kzl6@b<2?Iwb-Lx*FE$5_XjB!nvvG_SwW37-IK6iqYZFI(@?CRJex6v1 z1k<~NUpG}EaIT2Ad!v=}aGj?r84o;<8{C*QKlIU(P-Uh+b)-{V*z-^5cgWc$sd>C+ zhV~|3T%i_0y(AZCBFIJ2O)X`&?Od27)xqu8oflkgR?*x*{@MAqw|=W{A& zoUB@Np0)b@`?CV&j1a7jV$Fbmbp!n`2Ur|i1AT+M=dA~yN_7ja8ZGFa2^=`YV%72_$pP zp^s~oAWH3DkHvtFX{e~37_k-?<$Ydq@>L`&_tsg9A(2bq5G&bnT>0&MM<=B#dw%JLIq@ahg%#SKGEh38 zRFUfY@Z|!tgiJinZXZJ47(x&H5w5+I{x z@z3cNn!-5;6Q)8m?sESLipm<|^HSX#(c4Po zU$E2`<(HkHA@Oq%WL7#h!4kEl%0oVi@eV5)DN_uO`gZ4PuVnNo4C(L(c=mvodiQb} z*+EQWkSO<;L*0BtE=e4Fb9~lO(CWXXMzLujJS)>*`6FOfhgH8v^ec@oK}3-Lvzup! zkTw;(u$hm`>%5!;)GOt(%sWHt8U9Uh@dWI>$O6)I6(Z4e)E}x^d$WO-ds(AM24HOXj-s6V^=#>{fs8Dv7E{c3Y&;hq##eRs&+dqQeT`tcQxf{soEKl zDGN^um3{2!9Nb=Sa_q$)Mo?%fVp5fpc`yf+Yw@$%a}pN**}}!jQiz`LuKkTh(rA$9 z_ZAIW^XeD|9n{bW%DJ&{{%EO3I)qht{;M=zgpIiqPmN;`}l!4n?Gfs zAK@B&p zCOrwN(s^;+w$BsV19r~)Z@?sJGP`mEe}=7^G>hy#<1&99^n$~OMBfEuuHF7E+`Y~f zG8+DAg7&xYcdG4=FqOH4Glgwi|4ps z=E~liSefMy7OCURhhtu`hjXMHYo5dCFRe$>f;&Nnog@1Eg}ZnWzvll`@UzeNzdmQ) zV6UWDXIN&;z3w5k=^Xa>eT&#rfr_tsqQ$<3_`ZiNb;H z@1PqAo;Q-3?7MkO?&MjPf2di7Exga8<%iHU&~Lj|7+%$aty3ZX6nSb> zg?(gfURbavWPfHJHXb=Q_Dnb;dj@jqM#W`aDFjA~ zv&b#*Ic;o>H>*wWB#kRQsd$kcq5?#y?8mib6%NgIzj}qbSE2>!7MUg;C#AXx)en!w z(Xx#*n0B}WyFG80Pqo$GFAnN^cxU5Mw@eEk3~2+rSnzeECIx4;EgI(7y7yx9ol|Yf zp1@9ABbGIrzmG>eey~Vy>UEO{A1Wmk+ z-M%F?fs~qW7VHc-?*DmZ5>+H}R2qKcXEkf)q$xv4V0;tCJdK_idrcLz6E*)efgNA* z{Qz+QEAK;#Okl&KXh}m1n)&VdY2kCyd~*t^x%G9rkp?s#_$j6)>UlEjLVZYC@})k= z+)H3_Q^kpHGl#?}c=_gs7+#x0;)A)u_hn@KyL89W?IW|3k9}Z*ezXxwAdmW3Bi3GS zZqIfVyR(%kanYqY%O|T6@5+hv758RQKSVA4DLX!Q`6D0nzn}xgwfJw1gB#?XBit>& zx>aUGfd%J)^rlI;+^A_~%^Xoj7ksY|D(MUE-)d#4AGyzHpE^lN2kz{zlD>MlOMGr6 zfo!s3MQ>JPnK`;@!}dZ#t0Cru{Gs;JcaOeiSAO$>_B&G0tqD@4V6;_y^YE}eH;GhX2Aj#3W6+Tru zOl$%z5bT|sPK3+EdN4$|_-?Ma=P$>0Uyixt2jl9bM8WjTjs<*O@tBxvvLGwTTHu!G zV>E$Y)V= zt=AFau>;`1q0y|9yg_i{9^zegtY=k_PLX!mUt|#DH+YkUBC>`oPMGmd90b z$*(S|@+1)eGkjUM!6KaQUW$KvZPX0R(XW4ce1pBc4`uCYb}0k+<}`Ga>t;Yd0oB~Y zQBtOx38%VoxIHMJD<%?hsGi@vYs$pC<8Y1PiQO4$C^OJh;;Gf$#f1mqODoHYZkGGj z{n7?VC}Viy+?_fL67Uws#Qfz@p0rZN2%@L)ciOP;<3OWfUW8JDi#UnEy0Wjd`?xnG zlvNxtH@p8D3c&322k03-+wjtj|L{MB8xQLB^=|z-wDep4TA()|Pr7$26DI6%(&oSB z+)B-y2@8jz>mzAAjbGSg4w=kG$gU0W=iV)mfd<#D=ikFRk*XUrE(gjIYTdX(xSSE~ zg_B}j=_ukgD7H3(eaNWB*&>hvCQk<|h5@_pH7`9qeS#4Gpa-?|Zw|vf-HPlHB;jv; z*E&7|ytR)}^xBB}0U zz*ZTOvH|Z02J8~=Nnl#0_8x~Iz{l#l(5ujIX>Klp7Ep=+hbZV<$RtwxH%*-01!n}H zzv5E!B1v9oZg#k?s7Qu|2lzS9E=-nT1(TArd+(uF0ZA~c2^Tc<+iqadg#>O!-WwTe zZu>O?{~<8d9=fall-ow)2t_seL6lV9(D_*-tR%!T@{+$yxvW6EjLHd15N*9Rqgrh2*pQ2(drI* zA(1_uf-Pia1U9a5#HZ*=NxnD_RlBdT^WTch`8vnBo)(x#k1j2_@l*0g9(FO%dK-5N z{p|>9-^wUPP%+a=EG>YExozgR6tGFNn20Lw?Y%!xqRrl*jC2axIE#vF2^-N{=Qn7| z#995KV{s>GZ`(p_ffAWgbed!uxabDe*B-4WJF>Yd%<2r*WL}phh*Q@dc<*#ep)8Fy z(pmajeItTyCmg(v4PIYa_V}?^tBlg7y=8N)&?;vGv@w-k|h&tbt?c$jU zec5Sip(f5eEw!6V$sFp;VQMD0hCi?=YiafqxYD6|$nWb)*v-{lGp94ke%oP_F)7^{ z>m_h7SRDxqKs^kPj2dV9)Uw_JITd%HRg7j)r2xu?T6!VOKXZBjyZ|G*&wmCnT zdXoocY|N5>Hkm2>Xcv|di=7im`#IiI!n}SRV$F)&&P)MW{{f1bGJs=hkHMToz6C-B zWYmoqLCb1zr@G+^(JAG&T$NtLdo!<)CTTrongV#b4ajvLADM zT@i)G?vnm@gt zl(nJ!3tOyKczQX>4z)ri>=f_)LC2rkv4YLH&gYi_ZT=do)XTd(8FBbtW$V_1!Dab} zo0~s=EPo{CNmnp=_;*V;55>}uXRcl)V(E(bhyY=QZMpM-YjR{*B|LYsx3;$#mx^mA z<)|!1#lo)*^=uz1!=+kyLX%Z|XvWFP8IwoGR`$I6JEhP7F3>cRehR>PBW+SdjCBj> z9uo(B>R*1?l1Ja|A|f4FwM?A?R%Q*5l%z9!*9P0Xr|bK>$6jU)MX{n|N5vC+wnprN z%<l9=X7e(uPsjX`cnZ<)w|cuUYN9)RUsA1#R(#m~02I<~^o1x}9Y!djy2V#w zAPPzn4nu6ZwWoFmn1ywS|Mxm+k$5o2RZKh1-k=usDlc?wV2$da1iaq%G3K{GLmdf6 z{6cObXz9|6y-S>qc=VoQS};*tEfoaKlti@~>ObpfbdTQr%P~za+%JLA#wd=al3SJJ zb=1jiAWC*0HP5~NYk!V+*72=PJ&^lTjPF3UoC;Jx^Vi-lwMo3~@rj77i=YRwcSN;% zCLr>ITZDje4UaUQJfD^T@;Jzep=#hF)))$g>OKvd2I&*`3r>2izEu^yrglFtyhuqh zdq+ovu%Z$M2sL1AFwuLBDCdXWaCza(*OqWAE(tzzMrXOfh6aF!VfX+?fB-xy9Y^Ec zAN7UgWJy7}xUePpscGd)@I&~m`+4M>-TV!INO)2wcclIQx4Mq}jG1vA7eTn`7bLlQ%nfA&79Thp(HCrU^Xl3dAhp$MkP2Ef1WM3f}N3I71^*x^5n_Ugiw`+yO|_SczPW*}g@w`(773otHI4L-r>YYZ&o8I{pe4?Bhc+wE?c>gZ zKM8*jKUAlYw0leZbUS_Z0&z`x(ny5;oH~WS= zg;u5MseI_7PK(>b-W8>dxmkhX;Gv-J+dWI&qQoc* zg>7wT7Hk68>tQ#gI$A_%qHXrdn>=#M%IV=F!?8!)%-#s?{HVa;JUyilhfv>>)6s9l z+;^O7qr|!wZp)lyV#l7g`oPcFxn2;(9|@>(`}cEy<&oWA3{e>%3nqV&0T& z{3y|f?LU|Qeu9|3tL&OmVZ0DiZs#TttrFm;gYfbGHXncT-2ElZP=g5I63qF_!J~db zpkkL{*MV#GJKYl0Y3tG?1-)c4awcH3bX7|}ws>LKW}&wK!Db5i_$L4E`%Tk;KIxleQOfG=oVtlj$XOQi|l3b)B3+!r#$m-s9`;r*7YnrdG4(LAJJiRjj6Fo z7zW*HqZ_vm?|EAL?C@2BVLe2lXw7q8=fbJJ)=&MsR8@V6$3=cS8ZcqaUqxLVw^b5Y z3ibqw!ftsph4+0(Kz>}Y`zGrvj2h2ITzhf`QG6Y zYpH;q@5JP1)uPlqFIcnjts&u!<%ut7c38kCB^OCiEqyEDBRGB|J(`p7wEvbrE46YkD}T3w_ZEdLFnIi z1RQJ9A$xbDnA~Y?G>cZtxH*T%xK?n|S(X+denJfh=zlSDsU9xtCWAWYcX+73WI6eC0=VdZ_u1vla9!yEYbAeb*zT6g?@xd|M#8 ze;MxnChy!&!L%Rt3Vqx|V}uF~NYlBk^&E%J={xmoe=UO}_JwqFRnB4@te+>R?W5=n zuvjXw&zdrg5t~P$d|O#_#zjWgK71)be^AY%rQx_yf{>Ma_(E8BnK zKYNwPXBqnZA64HS&UX90ty7nJT1Cw~Ev?$M>5xvNR;g7hZ51^lRkb7OLd_IKQPS2P zp|ye_eQNL8Gh$TCAXX9?-}mnCzxO{!4su97_qeX}I*0YS;k9WNULf?i8*?NloQ8S} zV9Z7hu80gXpX)Z{0+6~BXDV7BU4Uqt7;Sh!QYWdGmIFe^FLsp8F_LSJupNW*6xuJE zqQGySuv$UCKm9Lfz8Jw>5d@gSp14*dQvw!e5y1fe-tLt18rZGbTD-H+=qn$It%v`| zvmNLA#n#b0+KW|DSTw)jJzsotF8{)PQJuui^SHaS(PDrp4*L;tqeD-g+(`2`d5CCvH0&@vcdQ6@vmX!HIh(EkY>(u$$k8x2G{(o!5ORvuE}EG;%tr! z6HO{b#RmJ?XvoSc%b?p>*EChb&tGE%6_n82OY4vHMK}l{k~3wVJ+wVtTn|#?O$eR) z>=E5YVnU8Y5-#Y0wQIk6G19rfy|7y{Cpd$)pmLKTDR0p^$NOH<*qLfRsqCv@#NpBC z4yA(Vh(?p~;)z-)@ij+Oyj^M`hci2An;WIlitK zCZ)2N3mvV2RoIdm33Xm&`*xO`Y$~ljzBY;X$01E0PooddR_>Kbtsm`1iT6NX*ES70 znt7HpI%in;afGDMc7hNj|DbgxK2|-tnIxI_WORi!e-L$W1WbU>x5U_Z0!DbjWl~5b zc&}~uwq?(^O+&eCrYrFhv8i9X-A}*&eou;uLVRtz*oh+9Ht6m9z_v9lf{nDB0Po-^ z#m8<&HWmk}nT_Nm*o4j0esHF0mS3-L+cOfefxNZ3TF6kIz4%rn{TD>&+QYnib-0G_ z?M45s?)xNsU^2NhvL#f^H%6g8_hDR2+W4|1d3v6Sy_?+E>4Td0GW(Gd^ve{&IHLn# zss!7;!u6Ttw;>thUb0vw#TXoe4F<*Oy|3-A|Kv=jeE4u#<=@A9G2F^cr6Se?)ByU( z=18q_7~9hgGL<>io;n&LZ6db7<+*G18$DgAHEuOlNt0>BDn09w)~rpuvxr{#9G}Si zUaIM!IGb!r4R0Dua1`_`{pg`iJV4!;`p50;9%|y!OCR&)C9AidLxwFzec5bGQ7P1I z7(!bwDA-L9M|}aCqOE};g0uG(uycSfl{p9iv&(%>jx%Nq1;j5Z!ejXgI;!F!|CBpi zD(&31N}Db45YSjcfvx=}j4etFCzl6q-NU@Rd2yl{cutiec4A)Z9ueA0?ac{!@X8GQ)d79WQ9B>6mU z8s56oJ@&hFtMoar16t=}EFSn47;$^}z=^lcXu%eJ_P$tnS%kyo6a4o*`+kL9D0jG4 zqb7b(Y^787Ca3>_uG*<2(~mWBGQwj;(BDiP%I^sj3`!)wqFmdVNkxlS*LmHqVA)9b zDpm1?i-IIRmj{J%w{o^-7xaVf*H3JZbYjY-5+Vg|*@b9F!m^${Wez2c6iA(6Y;A=OI}UAk7#3xz*cod<o*4kquSXD6=zBZMV)~eJ=c{qG9KpG z57??03vW4Ul+`2h8qPTS{pHC?Ho+Y|pR2nGJX_{KcyK3oNCzFDnn3gg&Jh;(H5Vu5 z5%h+Sv5=H4w10SOYCIr)+vz>&#LSL+d^3LM0+EF((~uQG*akpQ_qauV30VuzcF}#J z!y@kSnd?5TXsau2Cs5dOdM+M_srVH9RCWZS6S&jT^Z8W>Mw-)PxuMwBbxExU&i9Kj zNq98hamj^8o%n$5FZ)e8*?()SV*^smBz!3ePG0L%4@(Jychfzf^)=}fmoJANY9XKu zs$ALHqxK4o+XPQ<1i^IcsMP_^I`I6cekma)Q3pf=h7nUhQL$T4-aXIs(1llEr*2I= zY=94GoqU^mOKEOP9`O3TNhaE1HUMVU5G@(LWshJHHRsF{{U^~u1qqp15^?hi#Nc$% zFa)8J?oG1L>a5V3%8wgHitfKdsOtE$<^ec${}=xQzi#8dy5`~W1CtCy34eOVNQM5{7;N8-ajavx%8(nwEzQEGl_(^OLaMfg zcvrw>G3!^N-8Cs^(v3altx|0UhEp#NVKDWk2{Vr)q-TiRay*gQ@J^yfIdTH;pOdaq zuEHFNIt!Xs(f}oo%6yKZ@@RF9<2D!k3`MCV>@1VWu>@&_HZS_0Pa=W0gjiBKXW8?z z*x&zjQKvu(v(87cyz2A#E!{m~#(m;obi$~|i`KB#Dr)zQQ+Mfs z1;X>wz9xv2Z)pAXD%p`art$V`H&gSC3olErm@#ka>xyLq~ zoLpvlDqe|1CVedu5UPy>%TMgY3!qEM(d)8*cKjZ>k=uQa@KX5sYQ?}gCLJxvw?dfD z@}KV^?>;+qrf+S9ZqF!)A^0b6)n{6DRoHGii=uYT`W@}K6O@fEX>qb_Y} zhy{cWk@UX$=vs5>>Y0rc>ztmcqDnJTZt-ioS21B;@;;jb`r_!5vZyU2h<^jV&D@Us{FXsHc>qRl96mYG6)`bT7m9lz}iga4I!OHo+{*V zIROHf)8kelTTxmPgeoeR3P_gqH`1!Lx@wMBrn3g4nv+nlRFq?dni_!Dv<}6;Vs$={ zwH2r?I`<%h06vlRZ9Hea-mtfOvp;n0xYdc^g%^XdE9`p}a7DsZ^jMx8$R_)J&`Zr5 zr28sNM2C(W2LsaeV2_~X+Lxo6SOOg!m4ZrrgrsaQp-Ger0K!zPp5O?Ke4a!Iy%Sl1 zyX+Ze4es0IFI&f7pg{CZ(Zyjf@IgGc_TnrTNQaFlyX!iDN0w!C+7FTT_R1TBzwvKl z?uEr=$RR0N5*KU|Y|u^k#4|M!>BlvQdakS?ED{F+Q7^!f6tHU0W#9MBgJ?r z`A^#-U&9FfSOCllYI)E1PBEXoH+a?wKi9CMY0_8t2Dnxhh=e>4gIq?`RZmzNbY&FV zQ(!|T0{*vHL)-4%XA|hN}oq;%GxUw^LGqE zrWCRD^pyFW$)}igy>8qL2mr6)(h6=Sb3iop8G&_bu6IJp)vpu)S`qU*}^4q~s=^kreQl2fE7UE>43ez&)1%Fht?-qaY z-({7ym`T<6H&8ib5WI11(DR5mwtn42Go$ZxjJF8+Ae)w?JUR6mht2QjwNn(kjVQ67}MC3Ac7 z(OwkC4eOsL+9=263jTS$Hxh;#1PnkNN@)@1T#cc})5KptHz(K(xiETNnJydU&CN4b zR(`eDjHdai$QD-|rNSKzX6A)MLujNR6b-BiMis z_(OQ{mp>^DHyEuOi4PdpXFFpxxff0HREX}vKZ>D876T+@M{ujoQ&YaLo~yl{9Kk){ zJu>wz(I}Mv;@QZ&_6r5OR_oN}yhRvIilIMU-KgA_a*=-|4z1=O6W4H(ZOh5ZwZ{l} z^yy0m%ozBr)e!4;Z zR#+q`V2s+>+27!A%akQPN-3J$&3YS440L5+xkq{1M*dFozs!YdcS=sKVec&ht*+U_ z4a=XS%fi;v;#8ZfW;0H@S7nk6efuZ3zo&k*47wP)#k$NEs$wVxlo*UBOls!*`NsQ; z>5;yLDVbr~e9tP5uCcwmbC{@^#VNdIC5If(jv=X9=X;i`a_fdB>YSx=fr;>JP^IWSOd&Q#~ zs=GCf+P;beoq|qj7cU2Xovk|H(8wnj>6gKaXh@4<-@`=cia2looR#7o*GS?n$C+(h z#v%XxE?2C%(TI=j9xh#)I>WjaD~%E6_1{F@4_&z>|9(LvcBr-R^FV$h=Yp??>YuL5 zml1_AIsCuwJ)PCX=(s%FdgN1Plrtv+P&lQ-ruDvg?mn06>g*$>#OkUeI(Tz@gN2(A z48u&T{_UD?ES>Q}XQusR+G@$mX#2)g9DH84^sI;TGyev&HZl;M_dyL znx)#WHi&F+c5yz{3JEt-!SO!n2duo#Cw{T; zhR%BR<=J}QyPUkQ1Bz0Wk`k4bRqx;itA9@EpWU{ccy&EoelctN%}i9(;QS@xdJBw& z(4ruB%nk%5CzpJFN+etYWBVQ%F;HLbUKpv&mr8F2@m`K~QFoF>y`?|x=Ra(rDSrS{ zTXJOWYKYCNhW!lv8DG6U>uA>$gRdyk6((Ij=BWWwK6BF`_F9X zZYRw~|Ka(f=VIJL#@3RiTF7p;Rg&{usF)RGaW5k#E=2KHGP^vjE=AJI8PQW8Ij2Fs zEvQ#U$jWF@{QZmgCh!l+@d2I07bC{T z-)?mERqY3r6VANa;;GGjD?+^4j2m)`z#9Br-v}pdX^z7$7XLE0a4566Ev)zBQ~ZSr zMer%nSF)h*6kH*4?P3C$Bv1!vQhbL~>;sKZjQh2Ephq7Z{o&(@4F?(`JXCRNC5@(BDyrhbPeo;!=JE^zrXpZ7uw+ zVd1Dc%TGk8&ehy@-0rB?UC|4nRePk!b*U2=sUucvJBITpOc_8_SPvqxyDR-U%{m_W5y zSxbk-_j0oWD?k2^r)E~hTq(XJyTLqv*Pkc7l%kMQhV|2_ ze`;gjKMSbz_v2radc``-2H1kx!>sD3nysc~Ni%jC`5^f|x164_VN!-Gh> zmVRV)ox1&|H#9ANC~VJ|G8**4)%J+ike)>@cS$zm51HTq@`pCMF*7Af*YC|j2v&P4?W1W}mDQ z2VIprie@J)=FeHCOw%%&0!iX34yujA#p+fRvN z_B7o&W!k`76}xM&^3c4arL9S=G%f8_Vxz5-8Uq0+JMWV{4_AI$+WY4GNb4VYb>I;> z1^XFQDI8V&N1oM!;njA5_7}%mkJE-42826*ds7-B_^~d5Ngh@+^4k>5dKyhVM;u@GLiiovBP(GrdH2v9M?MC1m!}Vq-Y0r`DyEK z*zF2bxF5@E!7qkbcVJ4h(QPciW-3yyi+vceTcCAR6SIq%+QoUg1bP(Gthc$v=vy0P z%xA}>91$DasL;X^H_+hb=F!_rr8XOFf3JgMrn2O#TR@LmFwcnZ#>#FL zBWa@q(E5HL-Ae5n|JethuXU&Xl&HgZyx!hVyjiC|T`$uTjE*mIuey>`LI(O7g+kr* z*Z(jXYe}3sSgR=ouQvv`$B)i-%XdaJjlb0DixUm`7l24nx-U?1-x|Ug z;By?(+`wXDd`b#(CMKbhcQ-3Pr*3zi2Do^w3G%@lAVA5C#3B_N951XQ?|Ri=i`aB) zt<~k7KAT1(3NW;+H>^O5<`=8VGOk`YMY_?a782VSza~GY!anf9YCt5#V(0#SGyq@G z5BgKWxDvFdj!u%za=yXipVtvIi;Qt6!yBBm@0_ozYf{$9E%0JhQIR_!C+xFzb6yMX z@E;{+9-cJN^$yG7)nGJEo5eK9G2G;;B1)F81Q+yvOjvt|4V<`yKIJqvt<1Q@t;x-P z9+;?CHuTNu8p~R9fd7TAi}ULKk*+65!Rcb__^^BYta3Q|&oVlmi9Qu7p`CRgXg=v& z6b3QVyY@GoxqbZ)D(fLYh3^iUtyLPG4i&whx2cVL<}FoY(pTHoQ20U~c;)RwjidS5 z0rPr(x4)6JZ2hD+(VG{I(Tttos-)u9fc=xBB>6jyvI?i?ZG+$NYiv~$vvl{DQ98?y zD$Cw9TKD+~r$a!E-~|6@wX0Ji^fHIDSWWJ$bX!i>?;o-L2c|SO6YjG8l8?P|kv`M# zHXmKwPvzzK!T?+6W^-VD1ZD@PB`=8!+1%c`phQe`t-|SQdk&woGsLZ>FzVWF0G6tc z(}4|vn6i=XkIq?uKsQ)m!aYW2s{G-2e{PTt5GEf`zxspq!wp{zf`B1rn#SH(Z$#`I2gY<hT&TLox!F{PLQg@@HqWiLJ z4k1JI13K6T_V&WevrbT>ZtV<5gyed&?q&?0LoZ|-6T7VLnx9-%?wA}Iu)0TY3`XSu zKS?1?-;g@FR;CR;g>y-0bd|S95V|`8;Z$Su?OlA6!-}4rC+hKV@_pZK-!|B5_Xf`KVrDo$iLb6Pf*Y9_$<(zPtXDIjndV3ta=O>zfbvZ1%U$2uIzK>RJedDfvBwp;w5yIbr zv!P04&T;kTpYTFraHRC+1Zzl4c1sxGs=)`7rARdqQy@gF?5IdMnP9HQj4#Bd_e-n_j3=nfCwVk;v10ScamC-Kye%7;~Q36r|U&l5qq5Jep;! zR>w~eAs3uADe_$~2|YzJB!3yIja0{~{X z%AowtnKXMoW9kF8dQh`JyJ(X`@z7)5Li2ai1CWD73Ed#;PI~Qp)x0#jgRDGvuhF9j z&Kiu}q@I|tLM`{r6HHzYfJEV&`#E2eszOO)9tO0{YCy%m0!w}Poe-<#Kl(|lV^Hu^ zcZ1GlU~0df=20>x5~dLQev6K-H?@XIt^GD=Zaj=2{Ez3$0EUFP=So%;7i8fK7p{4< z&cn&dBvx*;!vP;x2jpOb>wM30Y)Y2`{|3I3aUaKOfyRw1K9Yu|mK#dn?qULuo3vP; zbAMx>T(hmsQlKIJ%ci6o;dkX&QJnF(P4bI{b#G>JuG)c%Xo8V?gd0?Io$Vjy{pvPC za;TSmEa_9Z3e?YC7`g#jGIcr8UGvv}x}o4zx|LPBKZyAXOZ1S1sID>b!4|8V1ILI! zLavHQO7UJ`K16-wNi-z;4|63d#bc|kt#L(72tD!W35)`5uqNt&&*+{yr}C z42MLX+Q}=2JMh<=w@kQpmQW^uJaOp!2WA5zomDZ+Ay2u0ACue#W1?!9_5quD-WFZ_ zQ;2j*!Q?-rDd+D90+)Iw_Uz^$!jVYtzzO@aBXUfCI@L(nt@0G~PH$=$bTw zXV2^LlJZ_m9-1&&AfRcMJiTi3E!5({&_xEEYC3*$rqUjTa*-*Y5^wMJ4dRVb~a_|6{J3k9$2x<_c1to5Hb(1L*=H+e~Wcm=F zOlL@YWP@O1Xdol z1$c9x;V}$fBx}fP&M$DrjsM!641-7P;eW2^Bt-Qx#LvB+yE_DyPk7>dEBCqqt{Po` z$Hk}3aSF!mG+_q#Y*s>6#K3ist2{OD4~7XIkr$jG&=5{q0B5tf@~m{#-FsQ{7M-)zqVqDp6FmPG&XtLe2tZl0cmLYLD-z zUbp<@V5ZK5n*=fecLhsN{W}M!yv6SNkJxjGqW0N-H1c&X$agF#?f{8%Ly`3%e72@a{4^Ul*E<-?y~tEABgfua{uRk&B?Hds+3#V$F;gU*xhEZ z+Od2toIvQ?I)J|Xrq6%1WO_{i$kjF9Ii4ye%!y$Yu~tC8p~Us=${?i%Al2zL_Xl>lMk*!*{5kPT}zpS!hDDccCY zibsdg^2hFY6yj>q-h5NZR;adPFT7X-O9?sfG_)I#Ri9moG6-LVlQ!32 zGuhARhVj5hUMJUG^NkifPu}_M=I;Z}h&nL@`&jZF61Q3U1J#QVx;_J&zw=Yg8R#h_ zjo}~2Qhr%o4@JT$69zq3{#tQeoa-BTf+u;Lcv>ufi7&Py0a-DONEeyJnE;1wDdo{*(A`^|`dA;wJ8R z#uzLIu2->S0;0oOa{ezm%&n(3w9_LvL<)hguXK$vAcyNYiJT37o943n`s9!7)Tgiv z!|9l$(pwDDM!!)iq$$myd#4V)^!?jbkZ9al=i>KS2Wsx~x(K!gdOpAp72kicc81Vt0Mpu(fZZza3}iW*QePnKVRs7Ee%5o zgyth98L=m*$8gO>N#k>GVc)OpzLj7kz9?NkeAYRNLEIhTB#qdn!F})IZA)-1F0uOL z1NEVL_E9l&J026)F#;mDx~;<(yJ!wH4FxNc$STbX@MUs@B<3uK`^s!?Wpf-netD z*!73Ek8RGsElrtqwzzL$?mkx3JT}$azS^^ATWA}F7EE0dU~BzGTsx#3K4Mzwcyji@ zK76cy!GlT2x?2Xxx5u~Jig9z=jA5C18s9(8SyNnnk-w(v>OjN(`nqA$oWa`^KwC-< z@Cjn6oe650zVdooqMo<%8T;OE1n5jMZjBgKvy{F{>$myRjnFSylBv|sBis1Xe*$$i zXF47xTM3E|jt~T0Jdu{zys@Rq;_P1D#J|jE-)&3Xb0FFIgq}Wg$>}3(c zW3|{PL4IRWXuqu;GD!jpQ$9~i;?x`coHMtxV%lu2+liWmEA2$SX+%gDlSvPpI5Wzl zJ6|(}1|gIu$Nv@I=fs>*9%C79%ojtSRL0sro9wFhG@N@jFkvkhs8j!NQ~xc|P0`FY z_0UhDukWW9{N)$5=`I8g}j)CFj|v$W0gT>vhFc+kBJq${Z_lXa}qUrp!H&a3Na7t4T;kJz}PS zL;fj{ZD39$PnR;zdHMnt$D^zc!()9e@`KqU z-`2-9(RJbjvvR?xIgrHDwNS@q?i6k+`HqOVeX`^-8i&jS3QV)XsAjpef{_{?V^OY=w(FATaXUR|C<&+*e@ z)h;&I;Upmv5ou}?VvL@frpteuOw+ht8K-O@5SL(Goz5o}am;0sSxuas<2l2~hn^+OWi_iKV)=f-nBbMvVzxJWE52IMIo!*(( z*2-mDTZ`*MKbBVzr#baMQ?$0J^^+!(2WLKenH$f(6_1Bw-GYegVbx;?+huw)RuSbK z59C?eS$mlGdJ0}+gw%s%4<_N%Vl6y6sgLt7>7n-+;A2|PkUmX;;z7H{vc>9V6~mC; z2*z$p%Vya4Eg3YzBkWO{aMx}UVf}KuLMh8B7W+t6V(KpEgdL9RbC{XZyHsCTp)b;U zTd!k-;Hq`|!rpt%-J;Uy4E9mA+cceuom$r^4DK|`=fU5WVU)|$A?uDepPOn#9ohaw z^cd~zwhKWhX(_7mi{KQ>Emspua|^94O5m3mx1Zm79{-qxU2a6gViXj)C2jK9LUp=i zxk`P0WX;#n zeUfG8?egv)(HaRQo*M*j-g+_e#!QbN-K5Z+3okV5GnFPQokBCW1C$|qLZ=_c#!beN zx-J5efK~5JSntrKAbPmkE77tmxhEIvjQ#9B@N!>A{G;P8c2~JTHC3y*Evej#;Qnhq z{Y>CWG5=}C6~2t2H*A`(JL35-1swqFV3ytIQm!^a!9cKEs5wb&JCyuExqGScu4TuI z_r`Z6T{s%Jt695f9-~kdO{%Fb^am_+1BY=@0q>(6t)N)WkY47bCb^`Z*YBk>Q-|_4 z7s$k~M5FxX2FatlGqRL;uAv8ull#<37=MG+(@#-L9Rj40cm2Jf%K9T>wl3QOY2bN= zX7l%=sAno6Rv#BMa2Y>%62w#8xCYwY{9_@6(eeO?UVN&lw1T-UaUVu)dBakt_!Da` zP+t|gjU*;iza^NITea^i(p~@IAzW{OG%#@72niRvU!peubj?Hs(ax1>NG4KDUG6N> zMdkDP?gbTV7m7laaymT*%6XHsrlW4ZVV2`hpIi%8EZFThgJk{)z}?(9F?sZXUX-zIf^7cllP9z1;OvQ~ed5CsnYn%gY=B`R+$^A)t&lL_+80fx;3V3kK9I z1)pQ@C5yAZf8UdY%Jfs{)1`i|kcEohfnn~Pxm1ZCC*)M^9nm)4D=J7`QVlrci~V46 zvq?hC7Krq2i1)TJP4#FHk;%bal@Vo5x;{F7&n{$uUELAin}R{M{j*)ggH8UgoZODCEqi+kMjg#(5r zdIbjw2Du)2hRR$#D;#-b&+kPR!v~X?-g%6oW2kSDbK*^FkvH4!h3N|#5&FvQ<0{=j z%Abp;pn!z`s2>0hcXIH(%Hc(S6A@AC-Pd*Jd;^v?hd_^r1hA~W6Sx< z$z5{%Zp{xqCBg*{09`(2A7;)-+fd05fp*EgSG->_WiAw^!&igRO#$0ST#jqS>G&?% z$u&)I8~H32>-z<$9=PsRQTFm8Bvg@PV{y}PyA#X{#22q%EmS|M*20AuF#&?`McwS%)(b(uErqR$E!kKAHXo5@k0Gt>+MWi{(Asxt zJO?AXUrU@T5xw$L0-+`RM%Cjtx2DT}(D!}*M^_})hti8Q!bRu@`ADuAH>9vqHt>Kw zi}I{``xYW94X}d-rnD{0HXntMUaI22_J|EqOJQVr0Qrooa>KA95=dB-x{CCE^)FH71*R z8ji+gR>cfbq2~9^938?jj~F*WoH2iLxOD4cq-iQ6UrnIm0J!(oW`exbciE93-;V~= zo-#yrY+7blIzvef5DgwO=n?hdN*6ACKdr1A`5T}Dl#l8lTdU`u*IBxqyr68g_UX?P zUJ0rzm2s(Aw~WULyeQWYoW;VyXpe~;ndis}m7vk*eb$U@ly%oGG3bO+Zg$kT#pZMH<8sqNaJ@xv|;)KxMu#o7v(uxtDD` zt3Uh)!vMB{G=exmuI8V!ry9mqrp+sJZG+JZ10=E}< zxhxa(jt@u!OD4CA3rx)_hxt7cGRgk+_brYx%G*LbR9qd*Nvuvl-@%_o(nJ<|we$-o z?ka4(ax464@519Ht!Hzuc=^qo*8$~#IZU15pdr+T(Lmj>%rVAM-b61^Yk%|l(R1|j z*?!Ly`vem`7kKSNj^L@>3hS)F8J$IJ){(6iMe1k^#VFg_UfF>lwBRfm?2l}TlX?3AP zWyyP=Jaws!HD?2LxXO^Xw039ZFZORh4tR{5Q5g&$ojcQ0aTNn? zkRXL}NLofQ|PFx#NLwqbU5o(SP z#=m$Cq$G7bV7w^`zuuhpC(^1~+brjC)eX4vX!S*&=3;Oh--BkI?sDyCM_=1E`T|st zcss>n<@MKiAniLj*)r(Y7oBox9#78Lcc7)@+vO^m0ujWJ{(B@ovguL?5E3Kh&~6(K z2`-pXPF5j?ePP=-N4CDnc2=~}HY(PZPeAw=MD_25LaP%5u1NW-KVI3-_qnv6x8pas=s8isD~3g??M%9BizRs zddeCm2N&lp1ovov25wv)Q@EoV`jVsJCjNr$E@NZhSTwRwK&iN>Os2dkkr6HWlb`E- z&XQlL#3`U|cHrclgf!xm#1nqHS~Shr0JZ56qX6^^b2n4#)nWRmzi|Pj&{W;n>^z`*q>H%r z5yPJ+l7IT6;VnsoQc$sTJc2hUnzUFAiY+=IeooxHv^3)|~J9 zr?x{xR(eoDgNgOvXq!7`(kHz&seZSFj-GU^$kb=o6K}iZ$ZHPT?#!gZZ$likqtA;- zBwvfOBfp$H@uO4vPZ|t`bI1Z=os}6v)^!W% z%AXquT#>bgy|%|J-qo4XnfD)KjV7$nf~weYwkZSg8&mJU8^B6Z*~Y!sqzaD+dq+n_ zb%puel@E!2P;dyh1JB?0bF3npuE!)paXC(L{APe$t zzFS!Vi%u%({ceBKN2j{KZI;O`yDEeFSX;ij7o6!()KEPw_Zaf!eCZcYBiBD>mGScF zSPQw?{r0ez_;WQupGx-|fQVy@f*B zoAjZq=|inmGo(e(2QSGgRD2v~dM^5{Tk)|r^{Icw9CG}Y3)-o6KHJodc)QxFrmsEW zaiDjndRKM0t>m;W%-np-V^)-yx}vB&`j0M>mntTkE$2$Kbd$m~>-=AR!LW69D_8`W zVLRRZ`qi-n-A1=V-90KKZ@g-ud~AJQ*6xVaEL zVkct0dtX=^l}qxho6Nzb0(r6Olj{}`R+KB6+g1JQmW<^;x|^;RRk0pf4Zx6`59-u&EHc}(R(WZY2K2uaT#4*87Ts4 zBUMb_q&DeOkUxJ=9%R1zB0YmwyDRBL7fSFEL+<@&UFSmS;q>_;$D<8I{rMOm6RB=z?Z^V} zB71SD#gtJ5>O9>NbMZf~0SSS_HEA>L8z(0Q!p2rOHT9`qz01t=#x)Mm?${A76q6Eo zys1AdWwy7 z!8P-;?Ra*11-3Tc634c!QkIyaFur}y{l9bE>$RpqT#ut?ei-k{Q@D2hnj0=oyXF7% zHwEH__Rjv%o!z81BPq6@czmBs)Lf%Smh#_`?V|CYX39b$FvB+g=v-Ywc!w6f?#`@> z3Fr!>F+Vaqf9Av+9kjhMY**qhGzX7Cx|B}KC4N7SH;ftAEgyN^d76Kpu&{oEgNUvr zF%RctRtjdi<%IxtDJDYigVqX&hD@oey+}1a6yKyO&xM**D1pNtWKH~Rbw{4=7E(~V zLK}<0z*zk1#h{HtO{!-42K!Z6?7|1MB(hw?M9C>-`~TvR_svub=R(nLE_sZ+@7hM2 zjCF?|#+Pa@5SQg%A>o;isxwco^Fn~7ipQPFx1@>BJd^|#XCP1 zic5;Kt%Ebp#;$(XrB$Xnw+%7vn7SNs9R19Hq{p=4NPj_8OE8_m7oUz*hgFWG=-+;G z=94B;=K@iDd|81%PF3V7=dH4W0%7E=59coqfe+h|^jf3M-CcJ5vZ_5Fk=Mz_Z=Eb< z&^;hUy3Gsx2Zb!CMs31<>k?vjs&Xi?;!I@$@OP%2*F^S@uE9cjd9PGBmi*ua))KLQ zZ*{qEj;15)H(1RpIFXZzD^aF-$g9JEG96xWtP<-40q13M;*<&#k{f-6=8UtSWWCiQ}0l5}sQ# z6c=*fy((?iMH{5fp77#gajA?-rz1c%@W}OG7TsSt`FlY6KyHXk1C6y|k>y1b{02UD z#S@iH%+>~cDL;PLMr4eiG0g79s7t`ZRldGBUH6CaJZV>O^bv|7)tP?Xv*^zMqutCk zoVtJp^2_N?6R64o%A+_DK-t2bo45omnC&BgfzSWujHGt&G#}4fVCf$**1KJ48H%HV z@FCA$l)QUqzgm}}GxwL_Z@I&sa%ec4iU_F)aTgUFa_Vmh!4ppg3LFV2T**)!Eeo z@H4uL^X*(N7|j^&NdwY&v#tWm9%B+UPe5i){}trV;H2d^X3gr7oUM zCN4);dFS5qoKm@ARu1swkha zR-b+gkwe-HlB@P*8A~PSVju^f%rRE^qW|b-RGi*l2sABwy5@%=IHg)p299Ql>kAJu z+fWmLPPO&xpc=K~L3px$$eK>3Sj=x4empv4%whmd2{^X?(SN;;SjC!)tb~5leA6BC z`or;fs@p6l|4ze3UvEe19q()8-4S-(V~MkLuiGLNK__4MVNiDa4CPdW%zG@jmC8$#VUI3Z2(Sj9 zCREX8%uSw5llJ#-+JxMPy(VAwdl?1NsSHUM3BZ(9W(NFrMR!xXP`hiNbiefGwNv}0 zPq*v9oMJdH7(m-jC{2w{sagLckPNn^>CHCl^^&)mp%%`@bzvu{NU>*<(?r4=Abcvo zvSs6#K5R?O}hRMr9ppGRM(+nl`%ulyL(W?n;hUqqes4`8hxqVK25i;Fz4~ zkJ0D_(i5hAhSH;-c{;Or+am%TUkQE_e4%>fxZ$`!6Z+#gwV3N5%TIg*j2u^1x}qe1 zrmTYi^1k!25nr~jE|usp96j6KHR;fo1EJ<#OQU8D zp8KA23U#XTKiiY1f_BGgx7{c#|LDRZj!}Zyc>ynvAQYI^Vxf@C?<8^9(~VXWmIUxjsYr?mjP%uQFo734}yZC-OOH5F5+sn z&1;_c-SYSr-JZD)DU_Tn@_ZO03;IXr?VB%P&L8gq0>cxROZCiiO|gktD=OFd7aAtf zlxO2AB2>=ydEPr_C7A^}1(TJvPh@3wM{Rvm zM)Ga*^*RsKd6Bw1MwIu*oKz=3NTWu-qhhf~vZBY;!-c1&9OERbS*OkR%((tznjUw{ z0eVk0lnaVTU1&>KFp4StcC6lf*NOloB-#(26nTDA)ST9p#GFg6=6<*SH&Zq<{eF5u zH}BC`StSRt`zvHXgF&{)cT7-pA9@;gIqgBuv-wk|@ut7rRq1xu0PQbA;7Y7`%gdki zbRJ6H`8jXvo&eWIj8P(I2xK8oTB5gqXNzc~7pZ!On8o!gcSJl+e6t(3Q}V2Z_Z&@P zLC{6KGKeuhfi{t1>FpRry>;DZPh#sB4Eo7QK9fi(1QqwC$o|l?8h|ft1R!V28k##{ zYym1lS(Q-@;_G)f0u)tP+bv-ERG?lAyX{XCns14{ElwVSCXDY+rW~H*6keiL5?3!g z!)?*9xk|%EUIEKVxPqT&6r}B<(WGgU+Vx$ZV+gZ9>L_MNj;J6AHdX!wN{p$YW0D60 zjbepFGx4)$#@%5P=%)BVnCj5A;NDyvQ2#w~kr6dfS5u|L=n{cyKjBiWan?lF?KhtF zAvxo!c2dpo`&~VKv$NKx!R@jKBk+x36^6-W)z?Es1WJf8s?i0{pL6`mYNy2_B-1u; z10@W?g^Er&UJ4KRMduC&nJBi~BrE`#$$d2rc{J}qakw~tMJ3L&A0dA0&d7yCUsw|X zn6AEG)L%BpqNP%7DhoRKQ1~m#jl6Zgm(FW*s}h*Qc4Sjv(1Hml9+ynS8Ml|@;cqmB)jggVL6Ds)kTKei_)|!OA5<^7rRKiZuI*&A?h|6S}xyzDfb`!3-1%R zSs<;lw0Ym3YP9Q0dpfX5V4G~cKH6h3gAW-g*Ser`oxQ8atCH^9ySkCL1VJnw)8^oe z@-1p#CdH)hC^H9&mx}vb&qpA{x=>y{6XjfoE5k!|4?Zk|wWV8SYyPNXSK4$!)RD+> zY@M9upxynxM$GKSCgMDo$ckzT&fB;BR9@S2@s;T11mm5j@eXrciQrpcD@ zqZFf--FMHF#fC7XGJ+!rN<{zSF3d}NZPyi}=(-h5rrtevG-5jI%D4}qKOSx*T;Ih- znpsp8mqIR84{u&Rw-<4KO=tBtcmF-R4&X+8WEs*|1zk|?2P8X8G)*a+!r)8;f|QN5 zPD{MdSC8XGfmn!Q74|1K)iSqPRDveK7i~#D;LV!p1}AItZ|#elBYP4!;u~J|lL2Ux z3BJ?|UbL4Jd-RX4&FGykFZNRl>MBipSjBqYnpwMQX!GqZxENnX| zVT{D*+t_!7?h$vbr$T8wppK7{qh#)c9jEg}Hz0SE>!xU3w|xYH2NO>`J&lTkH?vM6 z9lMIgA64UeKWWhui;-I{>~}Z$*UIthocc^zdPQ-2P#zZ{p#3^?^iOR(U$~h8U1_=Ib%(6W)b_ys3W<|{bP}|y|LBsJJVV-0OeF#iJj{bj@CLG`+ugSI zQsLicY2y(gW4sJV`JGG+EKnuF+6{)5YHS^MESubyzLbgoo=4VyfBY>@r2&0Ja2%X2vgGH7u9t#oLI29iK+TUe9+n~+Y%LdKIik$G|RZm%jUMP z0d_|x$qR*g_>+~@rPwW0Ii!i3aUn6h|kbx062; zW#k8RPj4IOTqJ*1?!-hzaJoIm>`qHu5W4@Q#cQ_Ibq_uvK7eX+@c*$3wJqryG z9K`%Ku7LTz*X=wiE!Yyk>}i5eV!swjmn_Ho?ZB*1p~%ZY#-}dRr;(u*?he;3+G-U> z?78o?o}$lqdJ%9Df9+;<_t>hUbw^C;GJEIA)6G7GB~M{;>Bf&8ilVstHj-mLwKvM) zAKi;gTVR-gS-xc4hy?z6|5?z4)L=;Ku`tAU&{}1-$s1VV+Vt@y9Oqu*jWbSN@ z^dyxxcXtK0f`uq&cK_(q$ww7^Ij4!VbFg00ApLha)--sy_0JgsyJW!%pp-{ z3iI)YQjPD&;PsX>j#2SQ%a%A@#~EnjK1gidq}i2hr>Hd_gn;DY*i%y!Qdi)01heMg zEjfoEyJC%>mW?vXOX$rjsR{QZ?Yme1i<17Z*$UUIi1{3DY%-de#NNPkCWEv(t-wp{ zDz~UzZWt6>!dFI!C@avCyi;ZQ&S4y;=i}R%!2~8429keV)am^0d|mpa)FIt1l`2({&BA`h)hV@D28(t#H)$XpZaW_cQkfs=I37BJQ@G^6I=f#|^Y%wsWcKYXBt6ikLQW%S zy1V)<8NA~v^w}i;$d|vqPC%wsaj$ysXJgXbLwB+?#A+g)jv^#~7ps4UT&8LLAB1l$ z)acY$o7)iC;JuyODw6{3kv8(xHmZ5(-?a^fFOb^$)YjbYz(liM_^SOE`+G%Qgc4(; zM1VTX3w%KI{$v!uy2WZs?TWi9_n*Q!E2mNub)`0i{0DC+2*Rfo=64}-Aw$5Kdv@I= zgnn3!p(#9@*nZmrUxx9wgT#8w_=E3lsWK_Oi!!Z6HOc_s(_%Qq0d2F(+amJ0R3%`c zy92X!3cEkbGjrqlkY>$^InOidP>s6qyLQMA{$aZv+KfBIDGYw7_or>P`^)}b6jW{L zHLg&0NFWil$|;R?04`{_76bz6i%6&e%nwiH99l=XvD%>OnQCRQptEm<$7A%D-_*0O zi6)v(`!5Qw5pnL$J>vD%wqIOq&CPAUNF=&dZ@!-ND7fvx-XK&;V<<#9C7`<_6tan- zr!B1(j};Y67lpD~5vlq$s+261#4kTx%vrikeP36D+J!D@d3yB)`kqgkb*`Od{azs@ zM=EM z+U(J&WkNW)#&B&OdZ-V2-#62z-|pz6(_06#!#+hZkJrd@k6Z-koY|5OC*U>#~)y)dn%g_aprZra~rQBU@(X5W9dE&{;1}4@sO* zR=x?7#+gCuVXc68FGE!u$kvna!x^3g%AIumm8vU$XJE@Yd69g|dfcZpEV})^qJEml z>D!S2_z%HcyJ2Y6YN5kIG31PwMB>+I!?75^fc{2-^9g_|5_pLfHYt1cvNlZl=ZkQW zY0tG%PGW_eZk%6TQy z&Ht6Nar~a{ySTu2$AgqCnTOj9&G!|E!a9@+@jb@d4?T3Z$B!#!vM7u{YS__0ts`;1 z7dFuCCA77G5eW$G5`}kfMreFNU=6i*0Yl;PG5g|nnEIX4Qv3txinJ(>ZO2T9B6b$f z|MB_zC%-BSvfUodp_>TfW3uTu;k-xo8Cq&j@yaJ&xFzS4&h5=jPy;qs-+#Vh-_i}f zx6sm+ORvD|f6LE%x&9iHl7G<8$viArp==T=YJyfBjvOrR2kgUCIhr0}ci}j(B`|oj zEsI}2K)L%YYOKKl$OgH!Kzbkit%Loe!iia204ot`4vfj+tVrkKEvP7*rI{*24Wj18 ziJ2&X`3NtwX8ZPEq$yu>^5R(_q~dCbKUJ~Ve$213_x?po{(d@&Uf60O75UQQ*Faqg zlVE*7Re{T#nN&1UwmH7+mt|kP%7L=Ut1EBrumM% z$?nmI1Kfb1TeQBuM|roczcD`Y(?2@hy>F=>1V@ddw$u{(Xuy-C*xzW*D4Or)X)0*+ zTP+@^6}_>=ks<8{|CP0;()+Wn_Dz-B>ZaoY$6fM@;}@%~ld9YvV2E&jvAg-ghEm|T zvPXr*WPN@10;@;V7>>st%H{IzbIwUZj3Q%3P};Z(FnI2dH|UE<4(51GDOR4E;uZ3j znCERZ3JZibYvz#5u}!ICzGf19DVz%Z3Ag$gC0W=)E-Q+3&P5!k16YkRfanekC|K37 z3&naOf5yz>{O{Kqn6NRt*hW8w#k>-nE?>z=dt2W&^H3&fqX$g+v(Eda!3m6|_BnWd zvz6!GFgp^REQA8-xitnAa@KeK4co+iPfGc?1M@-Os^U~|n$`Wd8U^=^&__aoBr9Y3*T;m4jPU6#u9P=izFtz~ds48|QT^h2Ne*)I zkXFDMl)oIaU<7bY-Q27GlzArc3U5H_;{p^`_w9!_;W=oeotuof`B^{TpKoz;y0qtq zt^Tx08GETpuPp+R&T{sJ@eDR}SzeOhS&~y6K7t5NX?Rfe(y7~!X zza``!9l>i~R`dEnx5uUn=Zh~})&o*j+F0!;G0y^$*T>gil!c1{Q?5EyWaQwb^OGdjvo}H0P z>V)vBDUqQ&{WItb=6atIsy<~ei@}NQfQ_7rpJr?`~zZ-*27ag z3%jK4^mfc5y`S=4#Zc-1T!M!FxKvOto=ezTAD2v7SO zzdUUjBi#!wi=D5nrmA$6LdiJ`5(iE|6A`$T71n&uI_F*d`b_eJbhTxuMc)j&+vmx2 zFlb7G?~UOyW8Dh4Z7}}ib#%T}dB@l|BlS-tEIgv2Pw&6CU(R!0P&wmzEpo5AY(Ezx zCY7QK9S2Rrz7-7J~iwb&=;oZIEtt59IF6{WpIz*I)LM4XBOR&tA-1 zdNKZ7ie?eYpB5k;F3uDP`dr+5gC*3w!4zJTe_T+sWl|yVaLhKN!>wFMcMT z>{;d>iR>3nb!3$xS5}lP=W(LsKwDF$Zlz)nK6Pwz>{>Vy+&5xdiPoBwYe~Bg+2_Oa);nqUQFFfc&8+y&adQ> z6KOK9*hy--xMl2!f%R^{r5@21GQnPX?1_S6o0=6v&5z0SXMKz-nzCKYDUULyUes;9 z-RY9sY9AR@R+z8ER!cUsrngb5;Zo`qy3#D%hQ(4Ou3OC_m=nG z!<>;-@C7GP{4FJr3v1r+YpLJ@U5+Z5s#U3rX zCGNrNj)yVUl#Oi8nKXM060tqI?F=OjPU!}OxrY03-Fr*%zfT{Y*Ebtl(7nYgx0+y1 zGSQGKnf>a(n??@2X4=IIwB-Iq3!|kIvMw@zY-Z%C-1Va~8Gx2!*`-JP`(@=s22hON zfy($8J6relR1VvOkb$*=;r8XruQ_{C6TfHxb6Nz|ciNy3X)-8t7-N}q*3F<~(IcMz zV*jK<&$w;(;b-yD&O6cm94nI@3%L-`z^?R(Y-mHuBmcU2RE!GayfTWlA-sf5xix$t zz_tb$aE~C55`KKVbjh=sTb;}F7gF*x4-2^w(ia$3R?vwkhOCz93|Qe35Gz*&Za&}s zMStzv3hZ3d?pRfbghe}0g%g2a-WdlM(u(j;Tq%o#HpzU(8&>a2RE~jn5P{I`+t;M0YkTWOd6n49vaP+YncKCAguY@n|W`YTbg zgH&29B)NO&U<^tsME#vXEu@4TQvJI z+2~g$J3l@Pn3s50^F2pZbpDvJI)};7eRXOaYxYy%5~(iJVyFK<)D0Egxl?tss-3e$ zpAr|-)!XdF0lBBOY*$n!9Rl8-*ZIt8IG}w!jR(7m`h}me$y(@+j10<$$#&jzS^3a+ zOPg$T@4CpdhkayDPw8RooeeI~BOI%n3-rvct1QlE^?^{(y5EnEzZs6zDY8)_DxR&& zrRi57k1ICmdtU@kK@WQ2cgsZ#7#$i`=FRT?=0E`4=qg|8QW z1#)rQ6x78`VkX7xEW@;Xzz_`R;jBc@tkgd`@r2#jN&c;)5r7<%*d3-WX?jyiQ$F!X zYq?8znx~l+MzWQUQ~BJn_mEmQ?B}gn_K&`|+-2)E0M?M(Z=q=M|zuI%U0re!|P604Vw= zH$d(LDxw^awATK2eSRbnRHauOkM(%H#N3plE0D4~4ja)@UlU-exH3#nhH20rZa=xP z6%C8>dwlY_2=pN1aSt&Nxw`$rCp_UczX9(}wJ{cc)J<-`^U5QEIU+I{R`NF=YBH?f zs;^ktzWHH~iqMq{o3XCbY7kPF&WAkCAdXkF8Vg$9SW6sdn^NtzsH{*MLbKu5gyWS92+RYJy^w|i6ofbg<4uJj5+=Q~2h-bp_akt|H{mio8M6BgLY3%yq zyQo+?6#OK~o0u&XoNsM;#K=2^{C$~@4msJmLaYz5KkESKJRjBVw$ZbNgfMcw9r$V_|y>;F^qR8I5o=5vgYD}Q)yjFie0ZnFp+ znKHwrti_s^HW}=@wI;Q%8C~*?!7iuZTI%|bAF^*|%@H%1oH2X;cFpp@DisTUI51%msN~c8eLm0cDk?EFPr^>e)1`^0ASoV z+aSI>h+c#X|yKM^%C8|0R{5sE{ zw|HbrUR=7yQpdH#Bt(fi%_rQWJwMHoIAcXhj>x35(&T=VT=%!pJyV}8?swuH>`_}$ z8O*Hh07?=0WcC8eRXseDL7WYOng8()JRt>EvL$%qg5Y_a$T+o5qt{_$A&1Ob9Qi{C9^^GZyGb=fzCBF~ zk#j~dpGnDoI$T$0gSuUJ9J?K-85=G}XD_nP#%ZX{`-tN*q1){F|-w%-jeY=u7q-u zkmF6Nh=RhDMp(2ebjh7$cWPa(b;Blaa?scZiA2}%yIZ7>z+WQxB6#_Z%5pj0Jiu-~ zlZga@)Dq37emf+b4cz?7Q+@4;5VvIKAH|ZOl;IC)U*D#}-5CAyl8eU7@=X2Dpe5g* zL)$N0`*ANKWk}b)V&6D9T^^ZVZvRHjiWR1Da8N3Wrc4|gaMx1E!+cxaKozr<0ZC0 z`mLj<=Ql!F6TEm019?P}j^`=*sIb6X{8rI8xG1x}s{nH^En!h%)rwrY*$S+NRjiKV z7W$wOT|hSxw?M)*^ysv0{G`lz_laPR8>trl%&i&R)fEGHU0WZNZ-rQ`sNao~k69qm z^7}DozkN%hgikjNx%{pzf8E*t`o};-c}DcabJzUPEu7&rOTdNW*1TpDv~BeItm;^* zTaEjWvfRlcwV)@a&R7llhlc4lI=(K}iZ}Qv`gvEX9cx~~-tBl3y(luBd5Wn*ax8SK zUtNz3{`sdWaLJ7>{9b*O)zhLSIf}4GM?25x-w*N8BJDxE{rhNHO9P_iZD6lDYq67_ zk$?!cBR3ZcxWQEb3ZQOmO;6UD%>;czcSII8vFfaAfvrVyxIkbwi1-YprT$`;_v{wWuIhu?m*7EJYM35&|_j1Jjls=hEWZbWql zH0A)x1=u(0TQuw+I=joS>6Fu-QsdgaGE?uUplY%E>dmMaHHl-52O~UeyKKeZn!O$d zy#0SA&!@_GZ7%5MF|b`ePX2lPcYiYw+uN4qQ|G0R;GfoMNxNYd-=1rCsNLUVT7|?H zHN~(wPf6mA+Dulehy&x5Ax#YzHbWGVrUc9$hmQy^)9*y61NoC%r*2bQv%=mn zfO>Un6Ia2;_g>!*Ce`6Q@pJE{DplkcdYu~m4AdeET~kE5nu8{6blrzMbVz0Ie)qH1 z>ySLNuZ-xDG7Uq9XPHCf{L2k2U)Akkuuk*!YWD^;*jk1UjzQCOtHH2 zyf=`6r_o3r@9T2wpqc?BNp67=bW4}RoQc#}Ll^U8yY7PxyA!}pJ}jOYg0KL1XMyet z)urfV`V&31<+f==>np$sYs89F9^aBJy|$i$2}j*$P2b3iecnBg{Zm;lc9=hAqD1qP zi>tTxP0q}xX9GN!YL1nuO2^VoxT6`!=c0|J+WNBjv#tl-|IIf4X9!H*E%2!njh*Z0 z)_yeRE@&e$AL`{MT3%ir5Ou?$(MC&^*>!cUDnt1MdwBw>lR=Rm1md6< z=%V7ue;Ez{<#GY$v{**wWj+@MXADCYl-GKG;#xfSE7(mhRxeVvY2g9GTCR{|RWQ2V zJM&lw_20Hk^^5$XEeA+~L{v~Xx6ZwH$DmZ+;|KrfJ`e_F#+Aapbqn>xO5d3bI#=W0 zPB>Q@H~{v_D`d`~f7?a;P!RK<-A~pEC&AScelW=X#J3Q-x)HoiE_fX`amtX%wE{@- z{A2gQK<#m{cP9;8ENty2*S&&a7;l@G`?=(CjxJ+GuvR?`IOFyD&mA|dt?4H;m~Bo7 zYqDjDPvcC8LV4B!Hu?&{)mte`W9*Ji{vaH4t%iYW~EW;NA zP1){aH7^gN_;Ji_$s@V6fZ!E0aB4NOo!#zrjma<7t?^U(N9UqDKH|N&4(11h3L-SI zupk$;_M-1FlK80!B$Xa*Q@_5kt}t}Rlsr{bsWW3sJ_DT{VUg4}Q@D9U@&>B7rgjWO zKFV;|5u#WE0GZ$1JhKKno3%tUVx3Y!hxv(eji?l2sQ$rM94A-~Qnzm`|M&N7vtbx3 zWMQUGnwCB}zkmRVj8L%F#C-+zDX00UhC64Mj^mrhD4Vjar)lBm1!fFaeYqRt zm=pmG77c%z29#baz$f-T{vSox9nWUlw&~Iq)rHz^DYa|QCQpaGii$0*O(dcAOjRjr zD~h6O)vg&kYSyYfBlf7B1Q8N>zx(?;$?r~bt@ApM_1Ov!?C4B8spy0SnU__TsV0ku zbc1GsN{&WFd8WJfXb(*fgewfX7q3z!SJQKY?Ou+13yaUl8hF6CD>-bw+Fn~lt8(sl z*gefoHq}Ur{J!mq28&P`2sN+HbHPYGaCf;~NHOZt@TEHkj&+~@s3>^6Z=qriBt(%U zIm2KjG-<85f?qO9&u%#7?2YO#5fAIC%5AMx^_U2( zmEVEyGrs+x<&(}gQc8PUK<(naoMkagvL?e;?zu?{P{eN5?A1xGSAAgP`aA#L{0aR< zm4*XonXk>|vC6{Oie2&jU)YqQ7|^^g$Np0nG3v!44emenKET9D)ON!*`YpXy9n

    9}^Dy2K0Jz*YRXF_YgtgZ2!bJ6!#tTp?%PW+HkhGG3o<4zTPXF$g3Hbx@)p_RixZWbYN0dBNU~ z`2^L1@kx0*-$*;4K*a^euU8>+fc{!R?0dIxY*XlsMD2Pmm?VD0vVO5uvy21yOWIA> z3#(`kPB3%duL;=JNDei7%d5{VF3=8*{4*Q!6K^bpKyd%vs(oNT&y$|sX5r-)aE>cK zN&Pl!13DPev-;U*-HiD}wg|0Qsg6q9uTh|Y#qX}ajrb8dca}{XLL-L`#YL9Wa#D&d zM=B45A3~p0AyXUey)P^qsML?Akul9$0w{%k>`%x%*7d*m_^+tz6RzLo4-SlHPvpVT zsV_wuDZm2`UR{Dyy4|P)S{M`;gB98_9T@SCIB-%b+GF#i77s}}@rBjhVyx`9^x$b2g3g=Nr&1Ql#~x6= zJm#g$@3*qp9u7CJTYvY|=3^h^s%|_zU11?hDnyFYr2UdRI5j%W09MOwnjibFuj!2; zP9?g8yYJ}ww)Sjl@a#0kr$4CA3D5mZyF*x;@Zd;+NL4MALLdLF1f|mm)F=K+gp5in!iu5x$T%Lnz%0E=lfY8;flG|DpGL^YGQCv9RgT~-%E$3BQuz5HBmhy%e9y0yEe724PbR>Sm0H`$*e6uV_W)*yGdx5EO zg0DYxpWRhdCfpj^k>xhczsRUx(GD?a0^)d*_c;UlI^HFe@hCcBGbo7ew)5a)^JJ}xZ|{gEaT zKiG?X9WYN3A_0iZhju?G$%GsQU&fZRn@_WC)4PvvVYythKP4~nPPRLP@g54D$i2s_ z0FOsHj=dj|st9u28`FQfv!jJ^%(-MX*ZXK8`E9T#49RVviq9+SzQgf*?p7bC?IXVAJ&w=Te1K-~@j3#mlPfzndUfKHCCKwTdL?%LoHy<&T?-_)3$EN0HzN_pz1mN@Y z?IcG=L5A}~lRCJa!Keiv;9xf+-g#L)+y1jBZ@Ux+RYrek7k2$!X04&9W;Z)!lC>lL zQF9S$;XKT#;+f>}5~tZM5?zRcy>GN^;XoLWA%0A_cWb#T3sWX)Cklw5ZY7IXKfxB zNz2=B&1n#bevx=kHF5bgb6x0S<&?v5-gU;Wr)4G_O@HO9h;g%PpX?AZU?6GQx6MGY z(0wdq&om%-10ufR^JjR+W{6@Q(iZ^jDCg>=iQpa4#V{K#!o^dFOF-^EL|>n0Lgc;j z4UBJ&@#F%qUSz2zOYyTsUC>*qc5-d;9)%W}pDiyn=%hK*o?Ca>zgNXH(Vw_^*nH@I zKCQSOk>oVA-QSAxTg1@_eA+-uEU!0Rz!CDQ8M=ncDKM!?-X>N<$Ze$awH2@e?&E89Do=^i>h8X^{VI+*ynmt5JH>)N%^1=oUioxcBT zyEUR}jz57+)|=dHE(53VMf zJ!B5ey7GJ zHR)EKem|kcTLsKYQsxa9qaOcN^453+XGs;`3{=Fjkm}}2iM#3dvbEpD4#a&knj7L- z-4Om^ntZ)VAlu-pXYGBK_fqpGh32!Lqxh4|%*P)(zJ7g{GDdohk=25$4iVQqk z%iGGoOnB3_X3Et0W~RIlS@A`vH|YY+(-n`x+s3x5+9{4a_tp~xzA9c<;y;_7WaoO@ z;Di+RID~J=yLoXFpklOk6-R<#ou{lTX$SEW&3rY}EB^kod)}vM7d?bxXo77&&D)6G z+-PxLLx|*p41F)%;q>@n<*?_TRLr^QCzqk6l^@Yf`7+YWnYO4qIvoF$-w*VzxOQj# zhRMB5uaK|&GSr}%72r91A(hMD!a&SQ?Z$4!R6@tzZ(F6+(8Z!wSLp13TnTtKLoQK$ z+E2UGDF*Ru#&_$$Ms)sU^?BvXx3Y;fs*gwgqbWY3a0i|UuINT4K~@v&iJwW@lOrB! zMQY%rr_7M#HzVPcYbMyJl&W^R8z{c1a;O$kz~i@_TytOT!Rv;r+w4DYVR#5RQ}0ta z6HSvI#G*B~4;n2WZ}$sWdG{<2ubQ8*OLtO!rq_$gh=?-G8PMJAsL((VgPLstD)AuT zgA$bEeX8|8I;H%kk@cMYY5@Fq1=mXQTv^*B6a;dgdC4H^9=q8!G&ChW&XD^bU3LWa z{eN_+m;D9X?8%crxq`q;cIJF$Sw^wA1Z>93F-v%|u58uAq_KbAi>lqNs(;jpnD?jK z=P8{7w5;q_L66AnE5J!<&PyEDYHIjkrdpaKp}8XXWJE9Nbst)Q=|hR<&LIo+w$M`6 z7gWvPs#QJ173eL$Qmc$BIUYJ+ZR70#I{jlv3N9)p!S~H77lXBkN76>(?UZnE7t48S%V}KEn8~hLO~eaT~A;rTOvE*!le~8jVt4 zHP!lV{I1-yM^i-l$;1!cqDZN4zy+#M&A)Y;dgp(1ufs@x<5xgwFWrh?NJDB@ot?SC*Kj0xeLL1f3VxOI_@53TK?Mb z!aF5~X^x5}FFPZjs39W=_;s69kbCucRtVS5g2 zl#GYou0_T2;kAQ}ts4w}m1VeDSZT3+pEf`~YVMF(ySd<+?&orC9%PrTM8M2le4T|_ zN}w^l)G;&SiiFc(#qcbPm3L#gHpy4G^cnao{JI}6PwnP7&yA1_m{7lAZG0LYNY;}G zRfqgJD=EE2Cp1R0Z|&0aS$Jn03s(c{k-=~199IXbRw&GViYnyII@Dah5zRO(2xCJw za=kp|I2MZ8?{)_RL|-o0;tXZ^U(U;4je*uz&-6823XtZ1sv4KgqX$oIH6yLpNYEIbpg%KQT)ZFf6Ghc zTYek=QPaxloNTl;<{#O_@e^W12`o+jE&Ev1LQ7TR#zuW?+K@w6AMd_Lc2RUCYsO4_ z_Z-e~p$hTg1()cp)YBWLIcZawocnO1NN0^$$+n%hUGIVovwzWB9@6&#&ej?o#?C{* z9$c**-Q|$RvPg-R`li$+5zU4}#!{?2!^KO?MMBO;2bO7bVH$Q+WAV1@NJIC;_fMok zv$c?@j2|_J8Ms-K+EE&JT+#B7A3>>`FBpE*9(q~Jli>62QA_(~DIJE9%UK5#XL%@kj; zHy-c%`ZinXo(Y|C6TU)313yKZn*^;QYdysjnGk8z^`+<9Jo$e#)st zJQcap&>;2V^8e^&UmCWQt#G|J ziTdaFhgA6m^JbB$d&MAfE_{#bgF?nl$h;hTTF@n9^~WJq6D$C5#RPom6+p2o9Rt=WMMw`hn?LpqL*t#%nI)2RcwIyC|KX0OZ%0=41I(`F= z>s8#EDh+yl{!6Tlh1|5NHeTEOneugSwE^eg^)^#R^G&osL~zMi(%r;A^fguo(O?I; zu{H(Cs9j_&7OZ?U|0uf{VP~l%pz4UiQ|*(G%2eLfz;VJCC3a&dHuB1w?DBqJO)RDRLnH+ zm9GgOr{0yf#+GXT@^@TV{-}D_)T(F9KQ#1yViqp^4ONCr$fv#}BP;#l4sY2VyNjz}CS0FijY~O~4lK`#->Ua^j=cZF zh|M)=4t1W_?p#FysP-vk=x!&0Q%iEsNKZ|`;Nix^7SVFp`{Y-@ycWM@oOT=wyj45h z`d)|O6cwj(nQ5gCXsb@GPfr|~p_aaL>K7NBCk?1g^QtsFKvmD$s0FXp{eEQl7GAkY zmm?h${?EVs;3I(aMu5buhhTT+T`ax~xs!g$JPrHvb3vE>Qb9t0@4@}20ZarNZ_0Ht z>c7eF(`}QSINd=fVjYh>;8PGA6@goBeCc!>J;-fW#Lv1J0>W>k;B!bN^`o^L4e?sz z$D&G;wJw)WX5WM>R6kF4d?A_D?EdGXCm}(&mp=U4w&8~W(W3cbiVnwhFM>>xOS5dN zLBsLCp5(R#hg3N6}w9Nm*t^_(r!Kv3QP(=q;j{IG&pJ z9ah*{nkSQOjo}?k7o>>yaC+tyIWXq+|xcSp2Mt`Clum8&`=x+_$f+x^DvWP>0FkOxhHTP^=2 zB=T`|jxUM(Z%>C8P2OUB7L>>9E}PlKdr!6?<=FwhHLPd$?5Pf%M|sm*#^|=5YTETo zdv)>FRj|b9`{nUgE0fNQF5kH>-{{H?9HUL_%Ce+Pg_d@!(p*TLeE4s(19{5>-=UTsUex@J2Up1@vh~?cX*>yOGy7l zms5UZ`kr;R{z~$_f3y~_U63ms+Xu()?lkQ^GD$ause){O3JL5ReC76$L%__-bJLfA zlF4OcV9mVRs%V&4+285z#W5G z9b}c^nCZlp^;0v=b!w!{u&X)uW>XKQ)vie@?15_bY`Ji@-U~1KR82e4*6(kawe-|ET?ppDDB}?mN}eE;`RWQZV7Wv-F5pv^<2F3`EbapPrpdsL$5fou$_ZCdzD^w+ig*zeSzaN!=$e841SCwy$r;&e;^ zV!N}^gGcwvm!{cV6K`k0|E&C;?QHRGtgo>xcr+@-?pbS`sd)2K`pxw%0I4)c&f8%T zfc|T?0r_M)on9eQgBtsKxnHOLDl8YN+nf_fTH&uZUtQQ87F-o1_nvhq6ZT=C9+h0? z?rL@HhV{Q(beq-w;dO191QlM7xk?xGSV^has5)tI{D&aL*Ns|2jcwfffVy!s)+n9w zdC@uWD=yEcNfStn!CO_Z^yfQmaO|MVO){3t?CUI5;+6SiWqwf0??owp@i>V(qHa~& zsAxTKUWr?A#7WMH55i=fzuxw*ig8kLXHncUmdJdHJG12ANOg$!R4y2Ncjxf7Sx~=* zzJLC!B)7mwJGE$@5)L0!p1i@|&5P^9K`f*aabw>|j{J-%;e7PK%kd6FU(j7}=1mGV zqy;{tdbZ-AN&1%C-SHy zD(iVm#y5rO$OlO2Y5x?IUz!$?Ni-(5otC#z3Q=rI;2{O9lekSKS0zJ1cgR^~mfM`&AL2^WkPHnu!Y8yM1Z&Cu|#B96G$f(5M&>C7$rOnOZI+YL0$JukiPI>F!E+_?TfI{S%Y(W%s8bF)(v zNsSz}ynzoXW-IXgzJ*Sc$s`vw#8W^krw;e+`@ufuuO+U~p9a`fNCMYN=H4ib^H$xD z*hh7P>}kIY{EFY5-26^a<{KS$5a{LwOQI{h6iHQ(myag!~}|~ z4Ifry?!8DT+aQ)tJt53%xDVBttTH9B4QstR^Lbb%qv!a;;E}zSf_6#uqmE_uQDV;5 z0Dwb)5HIIAs^0(Dl4zG9eSoZ+&D@OX*i~n}YQJ>r(0j)e=*t({AU+=~-H?r~ zL7YZXr8te<`0Y;L?K-uhA3*hR>h-m>VlTX{J~Wk!QkEHJ>YyswTUu8RHv z=pV5eit|NZbKBrwlfY?|*5AXc`p<3$n!g!ePTsrTJUV~?+_$8^FClDXax6?JdXt}r zyofcR8TO#J(>Yo1`4fU&GhYZ8p1KG?Md2y7wq-ahee-I$Sv^1+>)+m4B-^kJ5GI21 z-z#S%g*U~m=$Jg2*HQR}QPsMiC?K}V01IlbobY({KRU$I()-acZ)}PKggEzK3w>R+ zqU_!a`NKc^HE;u9ROTDFS<-`D(Ln6DtPehD`=5e{JYb7-$bIpz>kr+qS8!lHB9HmFQquXm69s=Y%dc z4hGm7x^OJu`Z-+-8vfP>r(0hst6M_awR4_rO5o$aZ<-LqasJus0Fch#RyABXm$aO$ zl%yKCPv80N_2bgVVv!FI-(Q#kOCejQ<5EWTU4`fW8a7V*WvH-3gfLIZeTMneWg7g- z-r23kw8o!!B;LHGw9`TT{@!QlI+X&5N3T(h$iT|E#uC@UN}zAKQ?{KEgSYBNX1;EV zx~al~tGIYg|A{80C2)J|htQ_2&pQ5a{0ZxACzx>DL)g?!PIKV_*=pWx_8%{C{ zvknO0Lnex3nBE ziDmEmAo*CBNLq0OI!w)&&nf)(_l_f*J)J4(6t>h)1DHC6UCc5|I50jS9zUJm?{qv$ za4-?HcGLTY1|phT(XZL{Jz`FA1*6%*UKISPv))I#uV&zbVjFTEbM@NaYu2+zibFx? z6cqpj03GFo(}2nKF}_PVyL^@J&b|o@XK33HCwEWCHMDt%PQ*XF<{ty=QEY76miTHo z$iy0JyuUu|jw4tdZwo(_JCrYCOU>VLh45whR-+fv(ZTy5qW4MzcuuALEWVp19DVlm zbB$HsVS8p+ex~B9_QP*Szxgco>(tQzR_e#)7So+pCea-7>WSZ9SFS+c%)wM&6Yma$ z_wJR|L&>0NP?011EoIiX7TE-s^WF`BCs@7MWetV|n&7*~`jEn*vw~q8Z)X@h&O-b) za??n5_P_v2XCo!~85H zJC$^Bo`a|sTv-%FAQZV3&*#4N>L-o>$lm$!t1&o&9$DoRlGHGr}Kmc4% zORs>g9LIS2@d08jTkoWWmrhOb>#wNwR!o$zo%;ID$&e|9{dllE!ShM?QpxhB_BCyB zYp*5{J37|6FOEfA^zq0=m1ai{_}y2vedubaqOOw1BuxB z$1Pg?QxcC%T$0xQY+>$54y9P*e$#pAz#8EYIr#3uVPzJ2aCZEi0>`j{#ksQbI5?pc zrXU2EbNx91&xtzZwDW!P+4B%z^O#NZZHON{yr4$h_vU)fqt-$HekD!JBFtGGT&~4dz#T z==%M){fSUFRHZ8^`kQ|< zUn^NE$HDJ9>pw@Y(>%c@!4&lPhX3??)KVd5TRei`7xn@@#jnP-aP1aH)$taPdq__W zhPI>duNLY23fNSlBxE@heJIFz_`x5c1o`P$sy5KAvxo6=p#5d}?##`LJOqT{HGYo9 zy;sb_g#XNYhW>;7@m`$eTJen#n_EFLxMqZ7BuTN#;Ccy$T6;7GSDE5bAjy9+=Pz{G zi9MCqm6;TT2^%@*#SeGIv-q7Y`Xv5zY5GxpfJJ(-rm5bLu>k{pXqF~XzzZxYy8cw~ z1I{{cKJoohLYF&z4?TFH@`D{_GKjrY9isO_ttB$eWPa*z>oZ_qQUT_4==CuIW{+WI z;NX)*YKnik6?DexyL$98CR~3v5K{ZIVMvQlri=G>8HlY==vt)FN8^A4vU3ntpl8?u z7P&fK`q(FWOMU9;Xa|bLBZuV5xRtuSwI=ebwR8Wq8kZ?glk{)CXgt%c)@D zQ-e32bD4Lp@%7KvWv=6D>-QG&3DNUpJA95M8Mk^h2>iVZ&6%uDtQq3pjgX~u|M`dU za+(d}U%pPjZC^V@{L}t*X@U~q(^%`Q)yzNGHd6X9zOfO7v)W7uTpeo# z&TFj4BlI5p2Satvl z^lFvefzI({xJe=_drKg`C8;W;JH_5X`0$B}x#jc(pX&kb zV)q@_G)9tl()w38jolC{*I|xrop=Y2EqrMdqP9?aynopT3NS+lRv3#-Qtaod9#;6$ zG|;UcwxBD%Z&xN#hP`5g8cckG7ngrdVm?tO>fH`?n=?0-(;ctGabyThHgt~i6udyK#n=(eBjIHeJ*Ud&8>gl)s*z^&+7i9idxdHvyzZx z`(bwRu1sDX!6=2`*?S592^A@}40->@%tdT))<$I!yUrq<x;($G?VW#Cxrx`0!jJ# zcA~{g`~ntm1#HAVflQQtZE{v?Vj$`UY#PWu0d|~_3*;fZ`l>NOA?zsUrmIEDWXCBw zb;aeu+`1p4^t~cqtZz$Uj7h~`=hYIM-hV~E7XdH@T+17sQTee&t8fPrNJUdrL+9>H z+cB+MGUT2e{RBM;nX;if&syvK47_8Ds4)0ze^KVap9R)u0`^Z@)al((V3>$Nbdsr1MS6xDr^`P z+WpM%j)!3uMqKILU@x*?xVV>L19~7X0Yp(BN)k}am*O_xy{}Dj@a4h!zUucOVgfQ2 zr2&coV6#Wp_a)!?LQP;Legfs1@fPjdcY;QV{3@-N9|+!-uUO|Nhn$=^bNVo2BR>#007d>EVx$$e^^-{ z`4uBf!3K-64P7YQ%)b!lE{(kecz#MxN;hpMXom{jA5YR-lq%dm z_0ULV1*D_Ei=s^FZH~RPr_bZlD77`xwG9`&1*crE)qRDF*N$0<)ZdlBO^BpGTkDh5 z=jM%k|5>07OL-N!(u;jk?okHLx6NkI&=g1-av;978I0%D7Y{=}Z`O(eoeUY4vO#(m zkSoRZA1l=zaa1{WYV9heR?X~LT}lWt?Yv~QP1*8*99R<6e9~^}LMiX|-t8TvolqwG zsaAE_hn>V1mqP4xo58Jzy!73#9~}tl#KrQ(@YNu9S=jf`6sX@}Cwo9EE$v6g;k;^- zeU4LN&EtD^Svdb;RnigQSiu62Tx!WW6h^WmEdIKS0%uyJp?p2MSQmk0Ut4=%8}zHo z{v++sGfp(+|6xN~CrI%epkKNSbC8G4;&sqt-lpkdNsLhvg3j62GoFI-iNwSKyA5s+ zD3to&Sfzycts#WX%Qr z=QAW$YCpzPefQ!A#nngEGC5QAU^nFZ02bg{y22h2q=WC!zzwNC|*j-)l0u8_Y}v=l78)$s|i`R36Mf?{Rv6o0)yYe9^b5>CQ#6 zAaw6C#XiV-Jjj@E(4B$ES>BV!<1Dt6p=p8}M(Om=_hOV|Zfhaaz6-X7M~5E>Z^4_t z@%Ct2@bARW*^$1WuG0XO1U@ymdZA;3(up759G14M(G#F^H;eyTwR9tpX&Sg_{Jt8( z`v-J)Cq%jhssbUH>}VsM2GI)iAp{Bk-;b)55mv_=fGkaTb2n$@VD92l1z?gxx8-y4 zWX@m8-;~`(TfGXebbm86p3Ghzh@svYCK)4V2T1Smq<9o1%k>_5p?lN6k9%m~GJgzj z%XI=wKOCyFw8a1 z*4~`J7X~tw-X*Z!FD!@2oUS*J8&|ISaOu4;f>$#SFl5BFd;a-zDIi(`1R}TQ-JEyL z$oD8#xwX-tZaq(kSXH9xq5ebR`)SPS34K3i`_?yIYlVr)(;R#`<?=MOcuyvM4xwu(@GYw2wB2EfH<0fql^H1cNWqIG z&OkrKn8vOU^)@kj`$T*67xZ|z`6*tSWeW;O{cd5Lpf}J_l9idy#*I&wM^o>jlb+^y z728~=cpbBL?eH-KDHU4@pfe;gy=7f**{n>-2j>-9n+nj6wMLu$X;@4+-1cistv~n( z1z2zVgwLc8gyY4iI-M)6Eln*+z+zbWH&_y|cEt`|`HZ?_x3rK)}-w;M1lX6e@g&*;%p&)+1#;E?rOlxkcb@*c7lx!-l; zLR?Oo>sH%cvXfrj`Nzdh-s=QRL=e{sl27p9rmMmoRDlM|V1!sP#CkMl$^BCNIT1G3 zIe|#>&{zsG%pB|8@Rq90>o0(Vw0Ko0enD>lX+XpghJh-B4?p5OBx`v06qE{dXgX%~ zTzyrL7S?dAxRnvVTp1&$Q#ot8Vu`b{vN2zDS$MtY@9y*D-o0mkNAyP+0*IJcXpJOQ zW^St(whCq;XY^3ky{nTQx=;%ejRKMlmAYi(RUU>8a22KtCfb~JR!ar&R8TTHc5}ON$hg(nZ|U@^One^M@Yk4==8-|F>GH*gL%N=={_8a$z1!{C{*^NCt8S&@*V| zb#+m=va+H#oR$O$ZuS?CYox*k%5Yk>Q@y$BHd_-Rf52C$Zz;w>nr-CRRk*7q>iWMp zw8dtm9QS^MaM-%2ytK*lP436oT~VN9gB#4T8=Mz_U6@~VS%``AecH2)*Bdu7XB-l^ ziRXELs=nH=n$7V}tFjCXV+pOM2I4CtR2g%FUID)uO6Mp4SG>M@JCyI$xA<&-YHq~+ zY?FvV+;Vp)G485v@Ir3|Y(yO8g1oE2yQOMU*0+wv!M338p!_zy zfFkN`rzK2SkPCj(iZ(GSi?e&x&=mJrLMZm+^bG=@zO3%E`P65%AUMa9B17gJ){B_0WF9i95yHVkbq&^+OqC5CJ;9Ozse{_zO^v@8X zL4bAY5GG{DZ{IFc)ecsy$n&1Mt%-41r0)|-XAh%_!ugjicS%y%X8P?Xmp#Q^2fRFs zBv&S>54|})MJ1lb7Scv}1!6;xcU>bF7hy%oz9IUa)=m*2LaxwTWmt-V#iX3&Pi%jv zLz9f)4YNH{ff&1l%OT;ed^M6Ez}2)N@JFDF;$>7aY{xArWtVfDSdtt!d1$bgz67i~ zwpBGa%Zr+N>m-@#xleE$-Tc?~_P_f2fzvfflg2&IEEe&-n<2t}p?Nw{ZAQGH*(A(D@YIuQ$R}O z*GPR}ILCEp-SkztL;m84tz5M_&fXb_wEN`ddU|S`344RTDfZ22%TNPGij5UI5J0AR z3diQ-dM~+qEEGgcu0hm;2UijM66}oaYCTuWi+`(M7j?*uS4q(TmGw=xiMwJLHyW(@ zUp0&&kQJ(hS@*D70(9I=UC$E}|B8w%l2QqXMH$-dSVO*jaC)$)fA;_Agc;mLK%L3|(hhJXW#{H%qyT0kvm zVr->85zU=Qd|$-du+er=xs)|JWq1d}L_QJjCn}q1lM()+xUI!ulHvX)c_vrp zv)>uw^CpI6Gya(+h@LFEJbVGDhqdvv*aE9OEsAuK@{r5GQ=dzZY9om5l!uz?=lW~bD z;fcGRsRO%qG1Fi%-$31KUCjM+f47KN2;U`i$cCH6@@9v4wp z?1wl5gZhP!0=wo5HW$}x%@@&#b>vqE%lp~SD10kUoqlbCejtiYBSp+(`;`{rKvb@F zfE)9GYg$ErY*BhG4kvmzy@ZPgtmyf=GDs1NjNUoiWVK2T;Fe#lI`9*|b}0Yd^5a@o z9+St1kT(I-2)>2S(K27kAo#^d)nL3NX%cS`CP@?b3+ukM@D}j{ov|16t3xds7vAai z2FotAK_5)80E%aZ0zWkEx)VY2x!=m9Y|0oFTiDtpmJosdH1uA;&!|x2)iZA9*}js6 zOJps==M|^DsAWu4h&0}<{>)#4SRdD~oKuM<2yNhwA%iHG=JQG8gX^(xP;B%O5RL~p7drFWQf zIiN9JsD4Gka2vOe&q1L3iWe^)BQe{=jMmGa>sEVBwW0Dc2V63M0Q%8=sn9nNC7 z!t1*6+EMOIPQ3*G8v1&DpWaj@6RY!uOjNB?2lDnd2Cs`^BEu*QRt*G5vKVi0R(VW7 z*zDJJl{bS<{10k2=(>Fso(;i`YAq};d^UI)EJS&L^9NUB!j9Q87G~|nZliEo0+Mxi zoMZNvt9^rTH}(}PlK>>R`5uTLsJ$UnJy|}tV1*aaFPnVY7R1-y-}i!q|JojN@BOw9 zZ(qHFWCX&rYE#qjO?=n=kjvH;>F4n)bPE8=sw3XZu|eI=a^*v3`JS@6;2q6Z(gC0PV=DL)SYmJRc$|^b-MKrI=K^S6S|qAi#Ahl zm%qQ-bG#~abm}_R7>V_>jnE0@nQX(_^EHKLsn*1S%<29bSb3OKrpQi4m{SWHu9slH zc8vaf6nAxLE!%T^qxc{nW-YHc#bG(%(b!Vkq}jfiJHQ)~|C&wymxWFQZbOB+|8pz9 zBw(eRznO@wW6`1SqmA0IMyxI^M)GcJxq)!5;tm;sp3*P4PaQ?3mKskrjO0THoN`Y~ zNs{AElUzLkpmcxlq9K%na=xJ+>w0U>oYn`9TLLd+G)qt7fZT}gV3(Dj_or1QQAPbz zgz^sQTJ2%Pww1qisL>!Jiz}HzV@>N~ncZA5nW|jQ0eR0^^nuxKqQ8$QGm0ko&=pM#kNyBLgiI5J$ zf-I+1lFQ-q5+?2Kn%JcN&5>W7PY$g4_8#T-fL*hMB~832ev5i&mwmT>_^q&~T|b<^ zAz{CiRiG9N3f}S1FzJx$uCh}RhH$0QgxJ6|2wXyAFGL--)^Lghx|Q( zz6H)*@8Gv2a|!r@%c$7eqO6e9?A{^M`zi@v-jJc40@34Qf z_Brps1XM;k*`{N7y5HqrQKYXiY2yTVqE4MTfI2JVM#1+1Cx5x$*^^Fn=*gse%jl)B z+sTcE+=#!7GIp(|q;RF>X|Xyzaos6sWQ1Is&Og%8V_JKY8;GNgpdwvfB1;ezvFvm3 zShG~$wuZWd7r5|A$m}nq^n^^_{2yJ12?c7=eMxMf0OxWBlRXPiQMdZsoMu}0+~G^y zn$$&)Wp!7{OH^TUHy&fqFfNOmsz);;#XHOwHT;?2IUu87y7{sd1?Vz6a*V;uX2^9H!Mm;L1kX} znQv;GerCVRk(IFR;9Eb2&dU|DkT6m438)+KM}k$+0qE6*TMgXrH0Z9B;;XmNhc7Op z6Hi)lkwU4XA1@)L`hF|n+E>@N)YBZ(7GxuQ>dXvnVUsRdJieC^!JF ztt7sLHjTR_u*fekSn@7%MOdkCCzLj6NMM~vRsLqc)ADLw9`~6&9kKgUNq{dQX`XlT z(PkFXg}d@$(QF%h%rd{f>c?$OKbl?YW_F;ly?-q|7 z%#8v^TmNw>Gf%L!S(oSg8cUGU+}N-F$yJ|33HKNb2HXgQm~>Z?^y?mG0?wkd5mQmw zxK;bpjQ?2v=m&b0i~8rhidYyanzeH=v0j+B+E=@rVPd~-mUG~BvkGyW^fpS>X& zopHoQTcU5>gbU>u-m#g}R79C20sfUG=Zz;?%Id#*s%yIHoA>5agQC|IE>XOOwLhE@ z1Nm;jiTmP4Y)m!7*EHTlB@3=?Yi;H97Ycq%mT^9t?6AzU(cmw&dXzPC-WM5s$TWZ3 zvZQ!(stCsN$lQE7gdZo`<7WLLX;@JGRaUd#)=6VY>X}!$f8*MG8IUtVZaBR7PJefe zo2A@xF2^kiEaP*Kd17>p6^*~9#h~gLzxkTpy8uf)S+*QBIW!%Pm!i(RT3*?7x0#{s zX*kvI|3-?3jNqGeRJk}LK(8OM_WvJ6XTi`^!-ipeQBhD)l#Yp@D5=C~uxJ4VMu*bj zM)w$sBGS^*QUaqS#^_0oMp`y{Fr-TcV`F~j`v*JQ*@@@5@9P3(DmF68mqK^i`q6sp zZ=85r+T7kQI3i2h@2Jl9DXPo${kh+artlSxLXGAQYg@#To!mGzAKs8yqZb=D)(^!a z+*ewL80(M~q`)gGPHBgaep9Mbm(t=Z^z%1#RyFyS-uPP~=e5FV{=;X4*q?so>&b3? zJU0r*#h39G4jnt*i7UC8J0wC>wJ)c|#{-;L$+mDI3w-PX`N{n=m2Bbgt9>%8sXDuo z8}nLR%K{!rO@*VqlCLb4?7|+8l<;K>iUR<6c zX^GCy2*&A499L^X9qkfC4ano`vG{`YL@m~$_YSY1Qc{?OLp!o}+@l58 ziR;_d(5IIK8)D6v1Oy{J`ApwkW*|~9dJk}JGF=b+|2wNlKqH?}(2!?!EQxf?g9_JL zOSNw!nIkM&Tt{a|q(?A5%|#z|d7>~9Un}_Zq;N%Oqlt98`lR7{KV09fFg0kdl*$x2 zLV#m)TZ6wU1Q(~N!sQ%t=&r1`fk;We^!_|eC}HDZQFvpQ2qtin+v_{u3C4<$j?3V zTHNpCR3H4LZUn4Yd`d@4WHmZD#kpqoIDT4oYG~Q|6Nz@YAftVQ2NcKJ+xIS=rF2f67 zu_F4~*d)QP_6a{;Kz>An^tV)8AZlY0=xHkrpwcIL#@Li01uD6xSB+!sYf%Y~=$QlQ z61)KsOk?%v^%vvG+rAhn;38;*%j9UA>tRa*-CxwlPLU5@g zZYw;+fh=!_^4ReFsr;bc%Tm`@C?|Gx%?sWq4gKL^^r69fsx&g_YR3Avh65l2YLQ)8 zPTIZw1kd1Zc%kg44qpkq)Jix~0P-?kdWn`zfyzkbP~cXLxWZr0k%EQM8n5XpOB}k^QZgC$6?I{Ozhn!d?F)ZZiVykmP`sD?>QWfUD+{7@Ij{C1`!S zadp3cn-6wp+7_fEj#G!?lP_#1y?DO2AnWfw|HwhN14j4rxTNyCGi|tjr+PPuW~N)~ z@g(U0z3=p+_!(newDiVsKOW&s`|~8}P~w?>!^e$;8gg&~1YQ)9B)~?F{hap;?hfSoG><-kS&b=aan8N8uGaN?zqy_Rzj^rda4Zpf~EhUR;dMJ;39p$=O6Yl9)Xy`06@0keKOkINxrh;g8IK6vJ~UOm>4T58Xb+mJ%;iE&o|R{^ z{>Cz(Ue@3tA=DMZD?-;SxyQSfQ2M;9wuT(v6S z8;pI34$i%4P8+64Ox*L&)IONx%=BF*JNJK}V~>}+{r5;D!zZ-1IQriBm+r#;UWy64 zJncsPXxdz_@9Q83w{4xi58_aksreFp?7v?Zy`clMdXaZI8G{-wmYz)_sk@# zYU0T5RfPcgcfs;VIE{P%uf)aX!u6(dNjvX(Gpxr9&)GrIyHij{8|17()h_qKN$6r6 zs?yodt#Hl)`n$eXbq4R9@JU_pT%6aV4>p!o7Jb*qjPOK>!P#QbU;?g1gvNMI;0Z-) zQwNlJT;OCQs#$aOq!YBrsTw?m23E#51e#JkV~W(qArAegmekRcXB160n+x!}%T|n2 zQ^ThtU7BJr&b&i$6PO32f!lLjW@mxk=geXWXz~%noVrK{xZi+?VBmw!c$MS9PUWp@ zf(H>I9E#N&?7yNGF}9&Iv_k^WJs9#+7DKt8s7(ZN1;2==)(SAj*!Cy>VL6!_Xh}0V!IcR&RCD-kT+0!S- zQ)S}fO2B<2k%i3EK!#*JWx1{3=^Oifz;c|Ws%t?JtLSbrpyHnp#=vo0nPIdo6;*J2 z&9#4c)5xVD{_U80_$T5V@mwzlZ|i2;$xX_0S)lrGuW`l2+-jOCNUB~R9|;!xOmg+k zI`6*gov8Y$Wk<15nk4HnR9!$uIO2w4SUxf@b%$K0fN1?y`<=`GZM0dM;O^$6;-c~0 zfU)W({Q*uVcWKr`a~my4Z(?SC-tc6YLei1VWdx$pgk`pG{cU{vY*|gPv|?SMFVhAQ zxM9}nrrY{gCt`muG9G|f;Q`Z1kfm&)pT;DXSqt<2*EOH|ZwjWdBx*+p9!OHT{$k>7 zt^&n$y-6;umYbDgpK@=iIk~f7Nx^b{EC^_S1090?_c;qpjsDi*@(}YPFSbj9DIkc@ z#V0*coO<32B4`Dk)a0c5VeOd&4P3%S^lHsoJ#@J{H}m#<w`KbHM*&aBN6w&I}xVV+^`s8<1><@<#2k>paR$oGur zq`&N`Yf9eJ{5kuC_e8F;&DtEw_1e|o6F6(LtX|K}8~3rt`?Qq@tvs3}uoQ_AnZ zhJ0GcTl6w&~S_RhY$mgi;%{N+zRBe99Lc3yLQtGxrydhAtM_-2AJYWU=X0gcZXa!^o#K zsZ=TJBTryZKXDT5#79ImLATi5Y%J9`H?tB|Qbyqbt0Bw^4&J|5w?AN4qQjh$9bcl4 z@*Zt}Dyil@QK2T%FuPOGoy9ko3i?MUXhVeWgQ%<#%PX>+Ha8c#=B*bJ<#IihdmXT? zcc-bWxr95ZhRdb?ehFf>u_mCMDxubpTn6fm%q8gQ;`*@`HyoJf-(>m(Q;g3gPvZ4Y z1Z+CyR9^0{Z{Pj$k1oy3U0l$N<4CCyTg*|V@LlmdW_4ypTyQB^mJvi220p;~f-^K+ zhoT)IVqCp%RfkUF(w&}JoG|-DPWc4}(f#*CRB9b9b5wCac58-hH&9S(x#vS2K}^(( zds_-l5u(fEQ0QE)y%`Q4XHhDcbu6>c*H~Z)0|0CtEsR5YMa$*!{k8qST^sr!9U7@u z|HK1Shp-5#IYe)p=p%7}?ai8!<|T~$khmt4`>k&v#O*Mb^k&a}`!0bwqIx~&!oFj~ z_Y-SkphG052F{KTHYWR7N22nX6Z)A=e(v5&m&)x>`&`ygr#PIYy$(`juK7gaBa&5$isdhq`ljzl2-jZ zFTD4+PpRxecuS^OZSL28WT#?n+@rXoQwNG`0E}XEmO-^_f=10-$s|d3&CLGv1>QNZ zPZo+0?ub52J*k+&|3_AVohqWr;mU#y5t-GiKj`FnyNjjP+MUfFSLrZ+PSN%sqdD=q z3g6V?3aw#|R(eC>q)p<|I(9i+9=WDAB>}68(+<0)OrFvKUcA}G$Eu$Ks%n8O6kfJd zwRWNN(o%gKuTB?NA?VLb;R3RxpSa{D9$D6dstyd}$p|Uytmy7ZS=kA&)6=SVNVHIt zU-4-;ymj6(VnyS9!k2S@y90`&FwVd{Q|9cu1l0_XV17c}1{h^6G^>>6PH)if6%AbB z1$BB3g7bVUt z#`|3Z>+#6Pzb0c)Z|NKdAX``U4#>}(2-nvx$46%HeJBNl@_Z3aA-*g6%Kfti_&q&@ z4}{PbNUHh;RW*$_LdQ9?ufQdDD3eP>p8kr$px@Szt5+{rb$jcPAvG4#&1fm8Rqnj2 z+Z%`lXlwd%vp@Ss)p^Kw^v=ra|6SQwm#yZMNJk33w7hKXb;uNr>-=p%#PstY-Gb3} z5d>%z8Va1v0;|iooxerPnx_Bg{-{jQoi*Fj_HCBFg9SicLpnS${hhl$WTbp8(O#B% zq2xb^O&TL6n3(sqTnvyIpBUP|twGP>&v5EC`pw5BbPj-x8j=w`}doP<`q1W zRKS?M&~3v`n+H~Vy`hd(d@gNFd+rgi78gQ=nLy5b$Nd#Ihw#X*m{EsFGB;yuqbQv` zL4^(2xtXclhpU{tFJ8y6wehMgHS@x(FmH*{Xby&xukp!}J7hrgac=0w&#BdBq0L8L zH7dZ_!;$BBQ88rq5auvv%#N7-Xk<)jHgTP1E=T-oyZH;w0Q&5!>#jcj7ADr+WiW4} z2IcAhnbO&OZdi`kl16$09O)Mq8&q0X)y+Q{j-UGq{yd)HytCjQ7gcL_3b;;cjv|g60*GLlvXpHLCl#Jym=#@W8nU#I)P@HZr!m(Bqa3 zVGDXFY`Uk&8eR30(YZu@xj&be+k*B$RCX5NR`g)>txV{rw%dC-DHVF97tRO@ovXD= zP78O6`ya#TPJJu*!^`9j)ts*tNpFq(;*Q3qdkml;nAVqPQ$N4EC`=YdDJi;@nCtTV zn(eA7c-}sm(s=&H?{VCd1E7@ZrM21bexV2}x#OT3e1@|hAj31)qVkp z6-Qs@9*8dnPA3TTnV9Rw5ZY^-+`2LF;E!L`F@~|I!tAVRa?~DwutT=sEi;#x*Nn<# zQgJ%Tt^%-1mmRk2EFA4aG6NiJEZ4{;+-FIo%t+2QGkdEAk+=9b#eFMux3f96i{%+t z2vMxD`rg)Q!jRXG4#cmY^}CONK&}6uV3P@~njI1OoLUC_1fwqKdC3M^MxSw|m_NIM9++d(drRxN&mOZ8r*<<4 z_UJTr?&Px>C6sND2auJD>Gbv#0k4azSm6<*hbsHq&n20UJO#kBFbA9Th>24pj}g`$ zqQ>l2yNUa*Y>4EesPwneh-~1`$Xx`m@SA26+2UM^VpBe5f0CLm0g1cq3@D#wBWI-( zIPk))hJ)C383(l3e&7dJaF-c#}bi?~7|UxSuxooD4Di zM;H0GDrrbHZX~ZAIE}7Uf5dv$-D%rhcHj=ZVwC8z*{DSZfSwkUktCVx2ee;#c6eFQ zxmS&Uw@vtC1>@J${X$Qj4pxGr4wl_{djcId)Gr_)1MpZ>YlD&r_8%R3tP2+&k;FVR zCGX&#jTl*bOAdI`Gp0|lc`a?rvEPV>;RY*O15UkdZX*_6o#h&iL&wwuU^ez8Y20S@ z*&`^>4@GYvp+CR$kM6iIz*5V-w0~^`?9W*5bvZ9;aWIp6b#6D@cO^JM-_at#&XhH! z&?+%sQ(V9{fcu$!3Dz*9jCohkF-&s_TEv=p#+j)^S4b_MrPZyAUtv5LSk>|vIFP#U zK;=|4S?6W$3w&j(JcJoIC@{7IF4r|2Gg15RVtWwTAujtJscww~%HS)rTE1m@ezSn# z0GSJM-_Y9C&jd6RMPR0!_q6`I@`WD$)2Tw=txX61_=h^iH}&4Zg4o0bgw$rtOSu6n z=Hk%Boa)(Gt%~O{2Qot~_s3Mk*&_n2fUFy*ywdbIQ_)$Do<$JY!VA3mbBh&YPEMm; zrj)C>2bO6rI6)VD7r+P7vEi3u8qc3=MxRWNC)sF7No4Ha`A1imm-6_SXPTIP2zcn7 zHsQ+tVUb+R3q;>Y2u(lb1^n84ZmhymdZsFP^%eR!IK}(VfKG#M@s9|i{!W?u+!npJ z5q}%_EzN1peFxmL_Jg4{;6QnZMQkn*V`qFQ3!`0ly)pN$eN7r49Dz`h2;8HZ2FxRaeR!91@Y?i%#D9)j(Se_KM;UjHc|6TeiJd*|GlI=U*` zW$ZU#=jjdGtq&Y~#Q0ZeSHdv6KzamVuNjP*&()pDpzb!j91#hGRj*`yf5IU5|0dDk!jesaBCc%#x)f{9TUFL_=e_1cKAq+JRse>;4=8so z8}SOR0LQt?l&w6S2xxA{MGe8GgJA#VG8%9;gSbhlClbt`{brx>B%v}2203xh+ui4+ zkr8W}!_K^_TfG^Q;~4Lu zq2ZwTSy;nbVaiwFzKR)Z!6aW^psjeN*nma1N4<03O{=GZ2LvyF4Pw>Mu*LX%aWhJ% zPwB4}vH@aR$O8S@1J2Q?P%FY)xpIlhUSvaMIIuJgf1h&3+P}$yoheHh)@RiJKx&o| zC6_WFvu(vh>!UA~YIacG3Z$LS+guUVuXYZ+n(buo3{(fQrhYOO@%IOHb40hVM^~)7 zOpV7=v%Goy%p9E+rS<0-4>7%{uU=jNoiqS}E;M~9ka&{hY&XhbtCW!r4OZoZw@{{AzY}4&C+ny){Ut4U|MZJdEUe}!MyUq7+IHP;SK@rm zJ6eih&_^$eZy9V3(6UAXOYjj093rK?zGKqjfQ3UH9UgUaYZAP{cFqS{a@c-vlPyO# zi_(uZ($RHq7ht@%WcAY@>hq4Q8Ko3a)XxW}d~KUZ@~R~CK$;eP{uZ@0uptX8N5p!j zu0R(!eiC*PwRUwa@+2{a>hf&9=>@S#E@TLYCX)UAm)WB&5pXx!?ZtSl`X=Q&Wv`yS z1h*h^<@n6SzRis(biQZmPdRH*hBD>x%4!n%bRvzNzaZ9bmS#>J^pwOlSI>W3ge+JLpWZ{opd6HB6^_3l!45ibxRapPfz4qUY$2qU6nK%uS-w-Q_ z_yb$r2Ia{fJ^eR^b7p0d;=4d~oWYAYN9dcKVfc{yggm9uJ@T1N6>z0rD=rBs^(g}z zH94Xw`ZIQ&wVK1Z@}hVRrKZ4XW70kuhkA;F6^hF6qFNpp=P)9Nxh+M-z@Mi_ zenjuTted6H2?J%BhiPI^? zna@0Lj22^-Cl|Iozx`2VsZx5N+=|VCCJ>{mVruDLVByRMb$8Ljr+b&Sh^@XL(o&fSs*-exNk?PL>w zkv$RXG2(^1gR7eD3}d9!W)Dh!rjM%tukiy(N&T0K6Tdp@(Tt3u!O2qOYO-jvy3Q`>L7#h(3FX1T zY@d)3H++(vDNQl*Zs2l;$xS~HiOnLw-UO0h8*5?PS{Brj&UrppkM2rG*-)vLuTS%L zTr-oj0j{9jVdehC~qrU;ov>spA`(qzyAbM(F%z;Y(3oikDXlfrGUB zBI8{CMqh~!5oMAnft|j()hwDK_fsteSQi|1$YLBwo#1r>S z`E6snCN0DWPprGUSGA}PDoX0+VO^$0SV)B9HiW;{fo-%;K(_z7j#97%aV^k(6N_>d z>pC_@#`VwZ?@pRHOaz9e-6r^fNd)dvIe=et+)GlhNw1$1Y<$`~{GGSC?Jm< zUl2RI?foe+hi>@-s8gZAf%BihZ?8C^xYA~JE5(d8SB-JVUD11UD=@3V ziz+JlRmlP(iqYIMu@kA)RODbuySS_f8#%pS_1hN1(o2ph&hP1trsj_=j=8t3(ue8y z4-y$RP%=wq6_pMafr8My`W9Q~6>*BuC;hLleW@Ed7XD4K_u|w7w(-F~lP0j>wldvkN=c%H0N&N{-q9Ot?JZpQ%;M(1OtzUNNl?P}OreHhIhY%N8smdveRJGCX zMjB6OmceYG0j_nJ=;P?}Dgz`hD6nc`khPp%G(_?xzp8xWIH&OBPH+Fs4+pZhoq#7X zx>Dk$w}??s0g0s8dAI;TiQBel6Tu*}$@O3Yf`3=U?VXw^9 z@EtYR>f&pGxOt~no<$>pciYy{*bc>(;A1+;E=gKls)F+5M1SrkFYQoGQkNSxa{Fcj zU8~#R-+y#?k#_d9FSt&Rz1Gv82_gBM(&VqhgyYZUe%A$*PLEh;+(0Z!QlL)1Y5OLp zv3l;J#^6Au^n&>ty!YNE#T*^+dPYr|DvbIin+@^!GVBfU@+cA;(zoX&WF-5`z*9hc zq~j5m*F#u6bFj%L#nxDjaj33m>$+2nXUuf&EMhE&p(Xr<%I!n3M62d<0((N8$2W08 z_L5g1KxAjN>j>p;5g=4pb6;ie0ym{}cLrLB%`7E8T~NGn<+t3cj`VOAx~uA!U-futBmfv}axq0TEze67!V`O?C5EwrNipz)w@eKzbnaoo!vY}1ZJ!ahK^So1w6b%ytfBVswyV!yTBONb zT}!UHGXS6{n=_R0o_(DXtv4>Si+Rjj-hsx%R=0eARA&#zo@?majVks<(o0JA^xY|D zTKS3>C(DWScur-?bXxT;bIi><*VpW@Urr?mD6K?=RFw1AKjFfn%&j8tP0huYeS{UB zGUlsGdx^$-{TZxrm^4dtcy(-YL7w3#e_+_zkK;sxZ16y~_5!D>hW$cX>$il7aJzS(}ps(;*hK%ah1>nDy%QopBlP_->Y@b{z6XI!DKXs$kp< zt2gC|H8{}z5abCx?13~YKACN~8I>1O8kqI`ppWr^AH@BUyxjQ*+_h1ARo6q?pQ^A0 z=y!94#~w$DZs&B9k`HzSGB1Bo$65xa^U6^-wS9^t!f%N9s)V7@^M&z8!O<|_2H$2L zZ(Wd)2Y7U&+6<7$**Cn#`pxlQvs4ZLR!N*_0DX04LTXE@3g12?Cr{9Iuv(@iwN|)z z5PPLS(7!Tid98=}8eC*_X+p^ciC;H|uH=dBR0>F`k3A$1V_2?TP<0X{n=@6ey~!V9 zLhKIWg^mNG{en-Oc#)^G>Z2{;el?8_X1BI~a`04zR(R$zQ9bkFroZf_s1hY=WiGB` zlCw|1t7I*`S8cCncrV>*1D`Z5*@Oov;o=%A))ma3cZZHuw)Jn<*>5w`s#}w}v{^9s zcT&*`J#X%Id>)4ff7%-qgk0`ZX)NE|w1}4id5awedW8ZDd*6m(kKquERr3SW80{awv(T4&8#$!VwF%EBY0^P37PIe)xXI$GC?&G-qd zU%)YB#@CU|+5Dd-LB@LX?Eb;_!P+hyALiwy(Q1_I5Y-c2bfp6AT8+aqc!X>O%K(`n zhcn__>k{zPxmNsNMZ$#FKe|dIiNeCa=p)Idvzm|*(uZ@n@#}69C*t3sXU^$#2-{%nr$&U1K7;}`MaJ1}D z>s{+a_^hvxKt>oRf6f`VQ!kQr(gH@9Sdn?Pzg(ZWWTm|!WV*w5@gUo@^ALnc@0ROs z6pTzwfc_Q35w;HBz_E^2&4MgKLq{t-kk8w+0iO5iW|^X8&5k=iy}RMQLfdKtT~%Wf zg*3bv!3Bbtbd7DeACM;cUQ;A1-giwpw9_cyba)8*ZECeG!hbGcu|X^BJ1_)>53A(2 zeNvLO>Xxg64>lBE=9C^+=}f`***oLFCSdrHEfA)v)(=jPH_K|kcv-<=APW($7#B`3N8#ZC5Wi_Nfk!(9RlleaN zF?-xxX(e};7>@mPCj3u2DZBhV8cPJPORXZ&^ILK-HGS!@!Eg6V(SVQb)sF%U47ES< zG1S$aeS`1L4~tfqT`$6w0-$I#ilFinQM-R+(f_5 zGs5^D%_vd0qd8hcRFu93F3TZo!ycB1h9 ztsi(e%&0QO`BLNj)L+%Qv^cJ*<*Cpcu4%9OoB1BViW0=n$=%0)jR{_ENJUvx*pluO zZ60MI>*p38tUM5U$50`uC2y=~p9lu|#%=is(ANiNoHh$|64Shnse)-!LA9>NNmefY zuU6SC0(0cS|L8_kzr=_uuV>U(`&U{Ej_ow~cQiL&I6SwdZ}?%pl$`72l#uHK%kx7I z^wQ|#*R=R#B}K{vDkt$&4f&aoKW@4&$PqQ4cQ_+q9mK4s>?{cfn6061S1E1Bc~2Q$ z2annx3qh*qHb8Z2v8Z4+b{wfTq|r=u40YMj`0A8ob9LSE(XP?os`wo6-q~L-m(!gp zDB~kvbkwPisomUg_l<_141X(C2iXp#U}XObv^B)XAj1=f-{2sVZ?99UtYu=T)g8zXkS8*xNu^^ps}61=4Jl?3 zgD>F!nG$&RM}!tw3EpxIvnmvUkZmlHgni-Innb(&kB+O4qVEDMw%}E6QZ-7p`ckh~ z8Basz-594xu9`(=lVE3uI2Qhd%k2%?GYZs5Z}>UHB-r% zw=Y92MQyhfMf=aM$qRs{8unG`WjlbBmMMwjAKkD1;(6n(Nk=x9CTcU%OhAj9-()pk zMicSsIHS$jr17uYpxx8f(8z!yO9}ln_r3AL{>t55BeAv(DHZPGy6<+!UU&G(}wA^4LNU|%d;L>S?7vAImW8Ctc89yN6_4{~qFb%7S#_PD4e zuS6&ElbyzNVef9?fkk&>LD}1XbYGxY%hP0@;4Bke1sTVxTMK!y+R6E6gg>oM*EuuT zbl1^tBB88~T1&jb8}@93V7F9Xn@-6#uu~p`q8Oj-G99Q?p#HS`F zoIzp1L2(+aD_q4?HvPrqM`WF4rh(va+luo|Z)uL|A-Cd~SzmTe!TO}+Aw{htMNleJ zQF~oTdYgVz`GW9-d2yHzRDJ2i6kAobc1<0B`upAS%HU}+iV|%y=i*sW9jCa`g9`Cd zk{@4CNS|0AFR#TFRpCu|2mnu5$_`r4J23nrDL_B z*7uyKB36tdMd{LbqXZQ~%_nz2be3N|zJ!WrY^j=~@ww%m815T(+HffexmN}R8(2LZ zUW)3PH&Z9HaWJkQhb)i~`{mzr4RyJiK%G(`%DM|a>_^F@zZAWJ#1L@VJHri$08lbX z&2OQ9Wcc=*xe?HXpsa-!9AaDM`ypqV-)`CtO3;Phs~rEdriO~T)47TU0qSs;2}Qq3 zrodcT(6%AjW@(Lfio7>{wejb;eKeVKw1fW{Nun}HRofa@xzS$hFI z>7D|p5f$ELwmEv>)BO7}bGHn@?60rVj#wp$4WP#tuA-$i_+-x=hHll>-7|WqDrKTv z>2JQ+>24nDQE|566MKv>w=I+WYlS&Ex>tU$T#kxWo&SEH+(1q{LF%U_d?g61&S^g5 z;xiKJuQ*P}d`i_+pI33TA(f8SuNt_p))%YFQjF+g4}oK6dKI6v3!fr)pyApSCQ#8s;32c! zJE;VtHZ?z`)d7{scGyD&cw2hqGt&G?V*%CmtVK!IZSP={#=^9%T!4-XzTf$bTlC|S zSzv+@+ue8$!nYv}AivTb#JoL9@d((|-GAo#>csC>s!`a~;g&nmo$2rbf1D(izIdP+ zFx-Pas_yBjhUeC(d|wM9p0hxTEU6yYKZpEA zOs6)v<0bC?+L4~2{%u0Xa;bAL+O6st#mzBTvRr@zl-BcM!?=Y9+cr+LxrM!#Ly9DcJ>Be;AlFU6wY-cgzsesga8Ytboc`RX z$3v}ktodrUwimKBhos=KA7eWaFMd{lSxgUN@7|4QvP4Ksp#~_b7tQ)e7N(WiVmt3H zyh~v}_i4NJ(vn+`>S83{jd);v%A>;XoEl3swP+Wb3H3$+c|?|oL=P!!)qstMHT7l0 zvc}e=-LgfA-S~pVxY~I4t+@RjGsT<3Qb$#Bn8nz%r|vk#Wup$=NUp)=8~(7tKk|0J zu6XV?eUH^rkP#5?o{WJ!Uk*y!P5_R4U>x9%#Hs*Jrbyp`3R(TVOa`6%6^j8x#-))g z$1C|#F|zamRdgo(m^}k#9B65+r;5cHaq+~v#04R|f3>niwk>tcN|67Y#@wW7Dk1M^ zJ?f0%giO(gEA5R$v;UmGv(G?6lvO@iy^HJ=jg@S~sn{D_)VGW8Z{s{`4zBCqXHX-kmnqunz*nO`5b9VnMlPVOrm^*Xa zerjCUe8hAWd`T!F(~o#bQhqHi>(J`$Ug|m!l<;e*BHcO(58SsSneA1gLj=+6CaK7= z;qB&Ok%L{Tr**Zo&>-bE{upf%Z=zjuq--AgAIn|tABf!(WA#Qt1$(FLWxfKWOH*ie zcCK?%99t5v2ge7)fR0mw&e$B(glJDT$6N!>m^`lHZl+LNK^MDuYg+>eEd?8+mIcCd zgp!U;>X!@$24$ar3O<(yQRMdu^Fll0rMw^6FqSRd6PRFnJ zk!D>;w0rx~qcEoOs)2*z-)p{a;*a$ih(O#YDo|HW^)sb3K!>g3D7TY#`IJC#kHIOg zMTtN6&u}Y~pWXI}9{&zZk9>wCy3M&=6bm!Gn^LXD1#|o^237h28Rlb8g4oj$Q?Ep; zXLn-D*NNDZ3+vljzWV~^)e+b0i>{qurfEmqNr{v+PhEeFG#z+=W~O0>XKt-d>elvulSYJF5ED(^u?`D=>p~Ui4Krdz4TVeVc*1PQcUy+ z{m`Y!I!WjhLR9F*p1;pKeVgE-^hIR2O==^yG$3l)u<6i!#RQ6kEOYdbFnwGYE>+vF(%Ehuhg3xX0c1W3w~$A@7yo``^8x5~FQlI^4f4qL7o-XRk%Gq%Y(lHav5)5;Z71yPjyP6i(l$2EO%bM z3ms5`_5>YOI(97OHE3~iJIz}y+&Pn5W8E}>wu1vvtc4?mG&)*W+cnh-D<`r0c3tMF zkxS8i_O)YMTmR_11CcK-(L3K?Xntv$umICzkQqTt0eQ;^1PfJqjK&|J*k!`C@DWwE z@8IU98)stS`)mc~H zEfz!_x=v&XTOV76Tlf`Z!l7Xy^Z%JKfIBu4uB2y#Klec5If4?r% zu7@>pNdtboZsVtw->2LnDNuE4uwzgoATfP=jqeCxT`5wvCt9Qy@tGki8_QU?kEuoz zg0X`1ybMnPwi7}nAWBj8J^V>%wLc8+D+t4Xdem?uN7=0xJ4Q;$jHJk3I<8;{QW*W^_&OK*C9rBYTKcehnclM3?q+WAnYIo%(9Eo|GLLyAa3(?~mXvovr zje^Bki#c19IpFql_8AgsJg*Vbvm^^%NC|RidxQV`|C?A|D#>djLnN~-Iz9DX^y-W! zw^X90vCUT~ea6YDYCPYaII!ta>ywnw)eP4}EV^;Af#Ikkm-!^~<-U5ZuWw+f%;1=v zn~rbW+ic{+nV-j1Hh1$0QL*Xdkw_ZXL|=_|!@9A-YJK$7LTQz+C#i%s%bkvREUzaNh_6yTjHFn^jMQ{&bLdW8ojrK?F1P1y5W>--$aj92bvy2{2%BobPViTI2b1XSRdMO$})`c1Uy#R zIoa@$64lq-z7zK*-+Thwh@p3)bfd#BA;Z{?SF#RmG*PRlw!#4ci*(uZulwyB<@(xr zLfj58U3@B2fOJ=uEp3`@-TMLB5!E6ZLnrESj-hfkcdwlFtdOej4r^D^LP|i$s0Z9I z{bMa!%6{OakdkGF)8FX`YmVt50Kc?qrlx(WYIw9=v1=|jcXL=LKE-h0YO_Dxf2iRN zF6EsfL1^(aQfi_>=It+74zH)AzuOvQmOEZ<$t^=oP^wPCAlsGvAq#u@Q=n@@PENL8)VyKimWcf@ zB3leW^x;V#L&M@!_*90^k$R$YqK2Zs3c^v@?+2->_xs7wvSK8!MOQ{a<@hm*Atg}x zk|43QfOPkSyxi)&{5>V#d^0Gy4=JY;ZQLT7s29< z`MNlYv=2v;cJ2PM?Ca%meO_7MS{t1NrbXV*MZds|pru?;vf$it5VaUHR%&ha>?YJW zCB^f2+MRwbD8sirUa)^S$5vbx+PSB{mSDJnkZ{`=mL+}MyNc;%{?ycy1fE7uY?}{< z&TF}D-sE@WpWgYg2{1+>Z~!@a-hE$|WD^Fr$e+_K>;uOK^0u7gPt>}X(D(G*V%FPX zs@;{A={c@iWnu>DSAh^-GPeP`eMrUlHYH_H$M!H?OrbMXG)AF)4(@?iz6A?Z^TgX6 zl6y`4u7vRCua|Qr!AxI56*k(j*>dU2cL%sLbIzv{2>w)7!)1og_0l+#_xX+E`3Gnl z^$H%ubFJ&E@R3Ke?+QU_eBVnDKaX`wWU? z2f)#Xi>YsnO})pF0d`bMHNaL)Oiy6;j4QlCSpqf}hsxQndXq{WvfJzvl?L}d=W7)R zI)tq$d(4F>5lG@EEWq#vW2gH0JCkYEN^Pse_wAO*6^rycv0v!6O0)!E+nx0O3>-?u z-Bs~7;nsWc?EzJY{x-oqQmI(hCZ(=1rem-3*0o50eJ)4&%|lt4n$4MlpMAi|l?fc3 zj+j!eCA_)Xwl+3rd`YSFO8k`@w+9{UX=3@a&ys8nx3wpP_vr=7NNyxxr9}i|1;lT>5@Zo)P%3-97NsTK z9J+m9%gr}c27gFfO>-XRIGfkk4%_KA{~twX8Q0X`#$jv`6cLdIl~Pi=;crkPARr?~ zh%|Gfq{pTxAT8ZYq;rx322ANjS{U6mV(1ub!{ozxc;h4?{18r;@tzohEtaF!qxV)0Ug_p%wNyYpX zFtG| zlsiLlNeR~frEKm9Pdk{XP)~ZVc64xY^R@g%qmXtuRzdXVW_|nBZud9!iQ77-(L&Bu zjv7uMr8~TShV2sgI^!cxi)@-2n|`_HMP%^&dLC25B5U{MYnz5Z)~Z<>QGxmp7oE|j zS*%$wXeZb;4oc`Ulwc=*Ncyg;+N&(AIyLHWVES@Pn1rX?xtI2l z#fymtk`se2q*U+bHyDv7&;p0z5^iA5QU882MckY!wlFCX0#^NjB*>3K{ zWdK0qP;>bTyM6K>v{#1Kr^<2HieomAeu5^i;-%ys)s3%Pwrp7oJ6?^)0o(x|9yU+J zKi9Q-+)J)xd$&E-P6U7PExD0xpm1&$Hpp2pE{`$1rCP{pw8sCvQHKrH;; zH4t5SI3J9HyfwcczvAs; zJ`{|Vn+v|)y8aCL2PM`|+=xrl(q2>^m#-Rj=5}4}DBT-V7W`!^_%ccR9WYD9vX@54 zT{D{F;Lp(Ix0R4TvIck|m^ZI^`j1{Gc0QZB@G|tCX#*G>jMdKG5LsEbuZpls?1oe8 zWPR%=&m06nqMBrs4HyQ5t>%#xFlA%2IdrweJ@MO!@dn zIhKjJ^Lhsa&_D^e`O^AB=Z;N>Jycc>DojBMlkB-jAuiVr%AK9{m!G|!<6i1+GFjJ2 z%N9QN1g2zYXP*_7!^_HemA~ z(Q|{$$(@34x^mC|-Xygt5>^2D(=4vh*VW%Rh%Xg(jw*V8@}%OgR$MP}X$@o0YFRm) zr0ApJheQKnzk-hR|4JlN`G#=KED|?gbF*MMHf~43rm8A=uR6VuE`4#&*YqT9*E>Wy z;6k05c#k}POr)$QCY!;|qPfZ=s%Bj>en{qYQme`z#y_+kkpEd!u=zu>#gN}_;>GtW zfeO#>H9*SbV%8(soWxmVo#v`Hl*Gc>i|hKAzc(jf((21_>p+)kxTnaA`@MIUiqYC- zArCIk^AgJ(srMeiI%6tq;s#t<;XS$WUtrL#I~(h&yi&31NnXDh{Ne|Buw7-W?Qdgz zs|)(1gay6>R+gB@LXGR&j6bIc*PCob=Jj#S-XDaM7NhO`&eV(s?={plI5~oop(6oR z$&?Lu#+LsqQ}psN4Vd8L>(_+V@YPG^ce@@_`WiQGcNN&7U_dR;Uno++Ol9I9-N;1! zb!O$hElR# zmb3jA-_UI}Q5DStpTf-LvTUuX)r9rgGPN=;WS#xmlS8Q)&nb>G&Kd|TVwQ(!^uGg-NqYUG(weHBxlpPC!eoO20h&4~#0%5}RIC375D5mx06&x7&-61x< zhaAPLpDMR1Gl%q&n4$heoYK(KdqbDB1;%W3YAl)!N`G>w4$fi*ewz_unUERf+k9BY zL@+JG(N>Mw8%Bn)xxbMzd1zkTwN}>*sTg*bkv_3ih!>s_pVD}6tzt-O@@v9`Q>>~; z&7K(HcG#VnJcdxjRpEbhk4sw}JbJn`XELLp#J0U_D$=AuFeW2t=eC7}gg`9o)#B>l zTvqLY|E~A2-i_q73lDmN<>{KX&XvOPN!^W=+V*E9rV^Iir4H*q3!LQP>O|LTk*>B% ztKE!6B2nzUD}~#q>s+>ks}AxBx^IUTWWWQ=D`Ng_y?7qTDiS{m0V8=`B9HG>&EhrX zI+&WkkjAS>!DnEvm=G?dZmyUh4kpUz$(eRshvgFIk!^-DItq1F7OF=I2(4}5UC?Wa zWg=WWYi|gss4SHF{4(E+vEzJmd=|)X*Kdiv*?SSk>~FL23X&}k>8VsL3lOeKH@^L( zlezjm2Z9_I(l=K&-mFOqzCyBX82eiWJ($^I4$f7@)oOJqGFP#5oG`3I_faj8#9^{9 zVKUb_pg6!7vDBOi0AShZZyasNk9#*TvJO)Q=UZHW!Jboz@JP;Wm*VB(;=i`J*h2=A z;em6z?WOvvQa832t*<;aNpW%x86bh|xXV)U4O!82&C3nAX}%xIVU5e(hwSy>VD)+W zNu~vco*7-Mj`Lsqmdy6|eyTL=fN}L39h4T64qtWNvDFm5>b(q~h)-`vhv3EVd^Ln^ zOV{N+HOMrAo_u+1X}^u8K6%=`OB7)4Bi1!wj^yvYG+hC7jfqo!E9R432JCu<1ebSq z-{0-nBmGD|$`zNFUB!K0M6La4z2j4oEZ8aL$qvlCo5!CX&oEb5x=Te|nChOgE4 zW4A#=;p`Sc4xReQ;n|4=+b!rBf0#kwjXK#W&q22sSouy3a__fpfA-f)ut2Zivi0Gz zv3F7_dc8dPnf=bteoA#IK9&w-KrWH2B|9`Y#qeMpvoZ9kS07zF=1_BMo?@QvN(A>z z5{3LUS=dc|4<2!?4Ofa(<_3!mW`3SFepI$z8>DcqS0!<(h0Z+V*31h*iyXN(nQs#J z&n0*jl?+=(4sq}k7kVQslJ;mDDI+Or9~QGr)W-=$Cmt{t3ts}Uv#rFt_ab~Y7MHE> z3=`5sN`o9`@%N!S(NL4Ru)rhDN|i5z#R4)iw=K9l=UUaG^WkM-h6g1QwYj8%BfFzJ z@|Ucuq)UvlK29l7-JaD%8OG0;M)C~S$vavA2rI7W#H~&?kkq_(BWYiAHnz{G6#>*u zJT*fHp5FM42a;o~7QQF?jc48ozBrCfrTT7<(GI-XKGc`EApBnY?SyTeu;F}-(E4m2 zkC*>N=0Wos3!A}ug}r08nP{%P(=x`tc@FYDt5xqH>B;x4)1esV6wpkISGpSHXosW$ zfY^}{d>CX0LDXpU-JG$Cg{6xs#nb;wm*6ZBaqQU(Q$x5{AU=Tg-GvT4g%giN`qvZ^ z4r9w#>a`0Hc2wyD+YUok#O%T?wjUXFVG*U>p0Z}g8FA^p^RH65)$Ozd>dgcggLju( z7=?dIKD{6b)Zva<(lKSp1x-%N`={|DaVB)zwbv;bq~S% zhjE>8w=MkJcAg~{eXkoM^iQv8jQ3EI`9!+!KTh#_2B)Uzc&xKpvLadUgv z{p(h-_-=uoH>KA;8l3+8QO~Nn*#+L@I+4^Yv-n|S_4V)~_!j0Tnn!_?bRhT~M03h=xOLh=3dwlTgurFT8LF=>w>;EFxWX+Np8nNShbtzq5`A3Gk4O{J^PyLivp_ zCy`h`9@=o2{b(xp?H504DMw$*GQK``GmV=!D}!vgK{_}bAC>C}EZ4nncTCGR`d!?8 z$rA(x1Pa6K{_XwMGcnuI1S$}EPE2ZSP1QTZcY}M%8JOvEgs-GV3x$C*qtry^XZuz6 zIp*Zg3DDp6F~Xp&CpxxS+I{Z#UYiX_eR_=bu6OcoSmR6P|K)?X$)x}s4p(H`d;_*F z_5rlHgv%%y(@pxE_V%Tjik8aFONfZb;-xSzGkh+!Kr1pwO6&P)h61XlI~4K2MY)vh zv|$W|7=G?wGxQ`SHC+%-^Qh9{t~zi3V_^Tcp%_I7aeLG6cg><-8V)6ih( zl9~xXE{{(9`Mqwakz`@L++bW5a4Vsx@7;<>kcaMHbP_Btpi)TKXJ8awj@wZk@_WR; z|Bz?Ub4{+aKSNF#8a$M>7xSRlAVIICUW_bf+}*`#GkxFo&u^A@<#rZVJv#1eO2rno z63Ix2r(nLg21YR4dp<$Y# zd2PQWzLzfqWcD)GK$pBfe2jxnWp>1Stzqo{py|olEZJkF2LuTa8mU3H|Dy(N?mQBJ z@vUoV%{F^nW>Rx)wb$jpYigZldUpLchnhe7y(G@vo!bVF&MXDz?OE@W%+vAC14`GV zLLR34qdRyR_qm?nVbCxNo`ucFKyLR71!q07HB4nE*a{W*%8(S6gxqR3!sh`?ChdHE z;_g9hH71qsP$qcxm@aO^Mv@Y&EqA=Tg4W~Rmvl)s_2_Fy%rz2z!XWFqIQKYSi%S1;N08% zde{)1(0py_Oq@!8sQqK%Ciu61nIYJrA#S)f-B1gjgQ_o&IA3H1PMK0XAgRiRp;Wa+%IbK2Vtc)jC9QOafmBfy z>d}0e|K4YT8=^XsDCHOFCZUz^UVd0y!0hi64c3h-tYcJuvSB6M_kcbdsuhj}JsVOnz&{7$vPXDFiM zsQw?F^t_x(t5y%)(JbdqQihqfxQeX_8n6sAEkm#T3=FGtuJng=GH;QCc7lbR6ZDMz zUw0mSy*DE>HPh_Zj^LV54Omu_d^{$e0rfU+0IQfkPavwVy$t`pxQh7(mosHrpAz`<4AzG6cw9|wnqb@6 zVZB)8*AQu(JRfE%V>#u%n|MvxbZ5;VaIaySMw`RHb3EN}fPYR-=^Q;Pir)fezciPGVG zghnNE%;h5{n64fvi3{^}&~AW1RgQB+8Ogr#0*mm#Kep2gCW*QeLJReZewUoyLf-`Z zpo$VR41sy`Xg5Hh`4mPKOLNli!+Q(qF#gBSvBGDNW$I3b;XZ%2(y8)KIGqENTh{PnJE|h>!zEe%9d&$0_Lb=&2+T5vF2=vqz|Ry#H51Y=Yb%`VW~A+ zwh@njgO+Zqn@igSgCaBU3~B)UjF40~2(raNwOi&Wq!cf_ zl_bUw`SC(JQ}m4fs_~J-8pEiE&V+W0>TcAM+qXW@lJC{leQdWTitQA#4SzN$_k@ZXntsL zcj0XZL@;Cr|=Pki>p&xiZ&i$hUA_PZ%q+s&7L)3Cy=SrVQcZ^K)a6-qS^_Lm@3oZUGixn|c=y5Z z7@yp2Rl;YvQ#bq@gbdNBT8Jrpl|lixeutzsrQX@a|M%l3r4*;Yv$Fv_@tx7{1W>f# z_k*7^aYAx9njyWcuQAYr?`D)$=aQ{qirgF_RU&TPt9V9RpTa`bunj|EQX`o@T5iGB zd>lr0_0KF(s<->4hA%pBug0{qZrNghe~QC$s>&f-lqB5ePVSNp8-XETAdxozo^|Ht z&7$JdoPbJxl4kRv!mcajjqW1fty;_VRDVjvzI=p4p3-ZDM=RUX!Iy%EDM;%A)NcGT zU(JcJRzL5ClM1VWAFsx}9Ca8Zrw$B?n%yqC;ie5_*M17_U7y zcxeS!`@Ie{oAzC69m=N;+VTLGN$vBxhbUhMj?pO(>nyH5t<+6T1l z11V3$jNSl{T(7$w&VYB$D0SQ93zK`g~8wC(?h7c3qjB~#RN!D+KQYaO?H8~<79Y+H*m_dArG89N@f}l$nWdJ|X1p*Q zl`_p7$isytQsD_i_z*fr9K!^P--`((obhE8YT5fk@t|0>Er)aVl)*aO;mn=?1{%%? zI`mz8$obp`7}r|9@MNkBWt`6Yz9+GCG;PWqxF?^>r}W2RiPZ6^tX0h1*Nd+MQB64C zl%){b%-d-2e(=IR^0auvZ}15E^=ihG!R!U!Mr2gRHF8v&ABZS`q4x-t7oKlt^rpeVNmJmE;m5KQMlI{zZq<3Sx6VAJ7m1kxY+2hd5U56@5ivGrHxKpSyh`% zs^0huk*7PaMyEite13!3_+WCyC5&&3_t9lHuW2C4ilt1{mMX{YcByYyYba~Ln8?ED z&$;C9IjUsysXOX2W)aH~LJt`eBsBczvlwsQxJsB(EdnChWFbQWGoUpy81ccy&5PHC zw*`u~&1&XP55$lPwfC=mHC-v=)mikBJN-xk;?~FDR@)ZL{+sk-D`^SfS?YboJCiPb z2@^g$UYL_dt1LN~75yG?kI4c8GH-Y05JB7YWX}&DY?aS`;;Q_jfSl$+^uo<%y|UiI ze{^sB<8dQzEEr~cIzKvw(Y;iDPk-u%MvFPH$iT6FaA3*;$x!u{}8^D$&PpUI-Vy5&xKQK0 zrXHDoHS)*4-2;YWr;|J#eS--Vv^iV=lKUO&pFips;RN^?i^|V&WWWg!GrQz=V1?i~ zO#MhGzZW?txfU$KPZR}jv%Oddz&KI|j{7}r?Lxl(U+)CZx&JL1@DCpQsfX0j5&*d(Q>P8zc%31y zzh3vR3M$fNq+)!);WJ-WpW%6Fg&Q~CbIOVZMhnh^c`mIs;6&T7rWv=p~ zmsan%V3Wj?e{>$_{_Kh_ef~?ILfZp51*PAvUw7Yp*c3WJ`pzl|liQm55C6yvIT z`QO^k>tfcr`^RGGH?Ncw#4dQ1LT8%c{ZxzNqHf`Yg@!md9)ld#JbnF#b;58q?%}QE zx#8wkMyeV>p6$RWYrI!=Ttd;4@m;Wr5;rqUr@MO3RioSbcLc1?{W(F!q2!kM4$AN( z!HlVnlzGJi?FhMNO^hk^Y+QSw7ptwqNugH0>&@~zoooQSAF>l_l#O+mu8sX6=~m_= z*h$)wEOh0_Tnol>@xDI=X_z%v_Mf)b#UCSgGl5T^_wY)Tx)>P0<9BL+%I|G--vFC0 z1x1IPlUR_K!3fI{oeAJW%j1=90`syy28s~$0!#4Ts11DWc`lS$L#<$Tt?vU>eAoFRY%{WNuP+^-_!SQ6O>NOlK;+OzH`$OJ)0oW zQm@N#J_slfVG}ud+c#1Aat*Y+#c%8}7vZmpOK0Z(@Ek z`Mi8&X!L8$o|aDK;)#wo{JJStgRB6Jy>Z;>9=QA;?{DW0juE{W6vdT>dOVV$bYGtLaq2@J2&Z)n4P2!E6p`PkAQ3t}%r3^NMNq zj*cX+kceZ>4Tps&ZlrXRtYOu&exWhk8VBQ*l0WF6@VzRXlS+v}skG>(SEa9#QZnS{ zhUrI~LON6Q`v(5e&G$(sJidF=^RL{WY*Yu+dAQSodSVfo@^Y&DZ;(bR0R;Nykf5OW zpg>nNbbB>usz2~8G}!;kbbztML2=a!E>E@h?o%0!LUpu{!HlE2q@ak~!Pz6xVsqcK zV+{*}yQHHpD?kaDjoS0I^<~ZSJ=h z88=`G+&MVO3k3oC=_t~k$#LKziq6%wHk0Mrf=sN4p^V&IGgl+tuZMDXaxhu<> z6DttT>p4{<)I*K2d;jRnhE~>;X`>e;R=T;$7VK#8XWUPns^Ttf_8!UTt^e-yX3S2y zA$?gnj?^@j4V>fD|3(EreKz4(7huG;FKZE|)_slnsV8dR7oA&KXzmW6wt;F>_RUOx!iH%d%xU%UhQ(bN_Sx+(PH+uhp>uzB7 z*IR)(`T`5p!|mxAuUnZ9`gCQk6FZBd6ngI-+`P0k#YZs9KN+e7riTc0~VJ$Tb~v}`v!pMw*_pnAKQ4_<}4hTqNY{4TGfFja<<=(GcL-D zk*(^jF;{t(yH>)f6-RyDFr zq0TPPLLVzBzE-#p_qC#Uu+2=%q&B4}0@06S*l%S$8$fUzELU$H1JhhP_xlmi(w1}j zl&wVXRSxNZyF|ZttiZdx%Xi@3$;bF^A%?R%imKvSV7?upY%V@7Js(`HJMT#R>VMSq zhL4+RZ{vd8>A7VNHsd;^py{OM3A5Dw%KaqI@tYcdL}G_J#X*Y3^8#1Dfz0!X__aUR z7fvTfI%H3<>CZFXo=Be2vmA6AAK305Rk|wg#R0yW-ZFhvJx@ljfDy5v+mB4Le`4Nk ztiiI(dUHf*QB?aSKD@~GLi-sPZsMK4PlLPqw6oi-d9^dE;qw8})&(zCu+HcT1jgl5 zzonq1YtvM=&gy^;Z!=-DPv|05R2Pwu| zo=i%$L%d<6QT_m8&BM5LgwB<{8pfmOiRpNPMLxbo3A%?(!}-+O2BD@^VA&QKyRq&Bj+v|LDs zX27H*+q0MB>Lrg(KY~R*$-?k3!QT~j-)(M+9xAQ)P95a1X)##c?`9S7j9_)ZQ(6{0 z({#`FZM;ney$vwpPw=LniBZx$J)vtzMoFig4C#s$T|6=kVu4g4gJny?G%tpJ6iRIwo<1Vcts(t zmmkUqcGKaJzG7YOb)CD-gU1=djnJ#yFrTfi-NE(ayCqr-RedNEZls8(!bPn|ECWL_5Hixo{dW(l*neEG=q%d z<~&`8gk?O7dZ#neS(Tc$u&&ha96h0{?&K;Iz8cSn#2Jkr9*?yun}OJPOc+dNOcXt* z;ZjMotbL*?ilj?+E`uwOjiGWXF155bJA(~PIvj*mBc-%v+>$Yu=7EJ9dzL`d(VQf3zjrYwBix z`9K7*#vpgXH=5WNurZSRYL&{0|-dX!s?6V+;SgIqB50 zdv*zOVS3XTZD+a^zXlVp$YRw|^GfqrwIR1LSEB47I_+~?#sBZ9xjbqDb zUQ_fWhAo-1Ddi+zs+VJvevbIscLnVhoZYfK2ej@)|5WkL&o= z>*##13LLJ(=T&Yj&>OnbEHxJrETfAJZ*N3F^4tANRJ{mC760ghTBiD!R8kD&6L(HP z11UAV#OL!b9uZDZY*HKhGHV9A_OSuH$(im93$E(Vh4AU}c_+qP&Kv7*o_g3*ni(eu zt)|UJs&1n?YsW*w47IUqTI(huxxOoLOM~~k^Q2&TlNGCJv~Owy)~XTeAZIV>USSo_ zu|hR9*|$zndR49$G#Nzp98kf{BcUg^zi5pX;7FF>&-Ohyry{cf z7VTUvB(s_B4_lTaO2B=cu{Wp{PM+PqwGT^43D0M3&PK+KY_At_5!#MWe@4 zmh$SPo{GXg%Mv70rDbCS+V2g`1|A+m47!x|#13(RT@}i-od0O*rb~@@3#qQtL|DTs zOoF^L!AE}gE4=LJ;ml(VON@-2iH77L#`}$auF_I!mUE69fQ&q{?DUb1) zQj9w*`08I^<*DWPuk*3h3KzmpJQt#W&GkiaX9T*X1ieYvdE3t~Q~So{H>MA30hp^x zigQIF)qH=#bil9)cbQOjuBSPlNcrX~HORW^zSx*LaN5vq55>jkzXbi}1)2NJqcwZi z@OejOl%-Qze#1KaVe6swa)wUw-4j2jCDp~rlzjyBX{<*pG&8} zJ$itWw2@dUi=ohbCc@O|h)oiIeF!*l=X!$PvJEt)$1g`zm}Z0MIoYhPm!6LgQFF7b z(w%jfNty}Hkq?O69&F^NJnrKn_ckl-Z za6D!tzhsQfC+r+KCuW=my&N0x2G@Qr6A&?)OX}KYRq*JO3ekVrFh;1m94cIYl&roZ z>*`UJ`g8Ha7pcjn?}|lFij=E*W82C#C7t%*0n39X%W_lgz9VwBH)bu&YryzwwdfSC z^jVF)SYLUKDAnNYW7M?!A{7{w!TAJ-Fp!%QlFXG+0YqJ(YHfMS{qwcQ5PzY6DC)1_FKe z94x*2u|Af#m;T0SrZU%$UsWO(VgKP5W$J!x_`8Df;1)mqK_6N>kSx=X#X_q?m1 zl#e;`?XiVO&RJK~wc2ma@~XU20kNCTamv3XIK}y;Hvgjw2-qUOGGpVKxW-}a@aCuK zr(X6=rs7iJj1`!;v1nnUx6t$pEJ#E2BQctFF{4HRX`kw$-`@uFnZ=qV_}w@uUjL$9 zd^I`}o+U93tq2`fgf$;_%5UFwB4&e>_>Ft8(a= zK(C_epF-MK@T{HvY$-O`G#WZgM^JrN*!w7Kupkj|!UPYsHeX0CnkhSxyq8|dZzWya zj_y-F{hQzIRk0%GEgQ9_&8ak7*=k~^J>RoCIc^6~~&5TeIz7pyA3iOyuEa+ykb)iE4@kLLv>08aeGIDxs4K)dhz@zL=v{+M#p^|Updf`A*0!)oVD^kWqZ8$Q7JgX9|Mz3xZ+QfF;|FK&#R&9hj=^ouH_ zMH7x!7@Iw_Vgn}~H^QO(nS(d?oL;vSn)0vDUto-dn1ej^C2}9kE+Ji+cx{1^YTRcz zfBuG`LHRztPt1-2U%E1@%fBAQ&)QE#o}ka@GY{Mi4l(cl?%yJpwJRIcDSY;E%0|}h z686=t!la?EUpRZh6t5KX;+*F#D>_`PO&v`6q#gOhyt8}O&GPr4b46y!@|gYa8rDnk16Lb* z=rPfZQ1*SRxTv%H+sNuvg6UVPUek!=U#9cq8bc5qgBj zzWt^DM{PZo-_U(=>V$8k`KV)`7a#ZHNAgG!S)#LIbZWOst-6{J(;_DeMnIhN`-1$eePlFQxVv?C$VV) z$&0+n$IkD4BzG5X6hzNM+shxPPkic^&A)V{ME7CVLsTEZH?3W)>&+TdQ9CN5zIjj2 zRtgneUHsBOB`0|MA05d$CL5QIbsxlT{IO9+7wEf{7Dib3O2|k3dgn_NbHS=Z@%3fU zBl*KDUJ-F{dp)nvh*Na~CUThzm0&I${q4n-fgdZhg)Sg>_N+M|=04^y`0roEy@&M} z%@lof9azP;ey-#A?r~*sa!j7^;2;}>_fjyh$lW-&ky|3(A&)ue7RmmlHlFh$dN|?n zlWWl)=ih5s!fJp^rVbeJ;NaLP5T-FkV0K|9#+$V}_h&m}Afj&H5|&FV;Xm;f8)o2H zco=$SbA_Vjw(w}6lF%wg!B_nf(!CVCNlH-vrfQenbxo>6&roJvU*n8^VNqu__TjF( zfWwKS!-POgCP(kN2CBw%v5zEK*zaR4moFBBX>JCaGO<|Ms$tUlhX;D!D{^NALpB?8 zIrCwi)5p}({-eK2D-Fw4s;-QQ{u-v{e(v%_sAi&bmd-ux!4Fv(n?*vaEiXK|t+R%* z@<7d5mVQ$`WT$N@T0T)lmQ<}0U;ylkXQfRa^Jf)PcgFwGIp88J6+Td*CFa|MtqWG4 z@fFMRo2K?_UKL@+2742$Q*0*M<;uViwY%9X8-*p#7)pAuixO9Pi(0fj3%VxD9zmia zcqYJuuXlu$VA?OtwrqM$^K-?^<2J%SCrRDN_rp>RixAwKXFOzc&3xO=dC=U-ASN07(8>A4Qp+m{P4{6wZEDK^}#g1!B%NSsyx`*8r*+WMf^~EaFyof(O~#yHgh6OflFj$)u>u* zQ(iQ9nG2#4Q-hyVpLDXj-_vkcn4Lf8@4hJTK?8}UH(g5uvZ9y%;cUKeSG_^<;7t|;l;Uj6=Gq`~0cB`ym&arJqRe{@(!u2wr?fensrDO;5e zB7DRZ_08We$G)08Vg5Xp&5g8^yX1>JFhJ4kLe}Lf+Mnavj*W%W4Ao*UU*bF1LtY7h zN+y=*V#P|2cq)G1eF%I_O9q1<=JpH>;4>l4YqNfjwtkITYpxBpFw}~4ug%!cVWMx$ zK~^0Vy#F+M=6H)A-l9w&-6)})CqLD*>V_0U&u&hQHZ9)x@8YW27sTj4x@xmHY&i0^7< zpJ0xixZti4fo2#50z6FgJ8Vz2Cw#=^mmD>=B@3con8i05C2{)>zB5DBhQ~-GSD;lN zm)dB1e0w+v?#4gjPjVarcCNP1im`KiOd@@!zA^uz|+L7w4I|>TCT$AWOX+GC0d?0onq{9KT5OzLjb8Ov>mO~cM;iu!v#HCd> zTff2hbyp7L`ve2Ut;n(8eaBA5<@HKL~ zT#l5vl&RgAGL1miy|`+=j2}ZQ?PFM1#n-LeKT8f{-7xdV7kC=?&6;JFTfje>nzlLB z3yQan|?rU?!Rim zJKdS2xI@Qw85@Xl(&UlQ^lNYl+t992gg}lOQhDXCYgnVFY-~LEB-(7vW^t7X*rx{A znZ${uV>>M7_yGn5`2nC3s4E=XLLnvTz7-72QvL!APZ@<^D)Z}_%&T`j%)FK+th#;u#YwB z{W-J;!Ny0{Ty{@JK+9Xg8_>qIOox;e^Yo?o{7^IJ0eq@ju#A=BmcB7mriP)@qE6S+ zbakpsl>p#w5&%|9hM_zk{Y+Us(&u(U=y8u^^dvNndW&o6tvvLtEJvmNEdJS%`kGk4 zPj-#DQ?sd_!D!^2?R)M(G9Ko3GF%Q?NF&*Gq$gP?yMo6T5m(QKl!brbnA-DQ>V50) zJfadV8imfz-Y`U@Z?yRBmPrr*Zr2>%Ad%nmdLs_2Q_62j!Dmz_WzDSyu$SvUKk^Y# z!I=R0g~i+qYalAA;eg}#Z8_5)AW(1jO($1c^^?vcIvb?K#OlJq^Xt4jkI5Pn~ae&T8A=bZNRnC!fEJZjKp?VTwA@bcR+&GdCm+(7!rn>Qx*V{sd-C;b%pv&kF{ zVCyUy{H^!Exy!O6O2weME_+5&!tcsc`ksr2A?kIf#N52OxHKfzqA5J&PjGM{B#JdY zA39KREFD}{8q1$>$Fp(JG9x){*79#5GOOESK*{W7*?eTHnUnsTq%j z5|DqWkWHw*|63ZHx@JrD%{?2AQA?(<-U7g_NSBD}$JI>+yb)L0*XPlrDe?B>_ zuY0p>|LCepSmS^tZeWzTz+dixb{Da-vk7IbTatr-xv6+s8<_q>aRhj6CaM1NJ}sp< z{wX|dt|{I^L47zqxpjXsFTuL}D{Wpx@rWB;vo`?=II>8YzHtnvUtNaRxDx}$q@tuZ|ei1k10Hqm2r%-dMQ zALC{UH{x2Fa>jtQu5Y73Z5`Vza=~`4;KWdPy)XbpK6cX@TGu#b)lus_(>SV6{Md%; z2Y`>i5ZlWMPbmYK`LiTC0yf!K26je}15d4+=3lRS1ytXEl;9hBD7AFBpbsych|^Di z3y){vtr0Go3-nQ&;oLTXt;g|~8zy5Adx37g*^hay~FKMk?|7;CtJGDs%a zRv%MYS2}sc$R$i62w{J%sb}MyOW#6>b2jsGGfLOjmF9+@G!Cty({PJ90M)Kp@Bl*s zURp6^CJaE`ig38!vG~i8un?9^znEiyDB{cZLe@?Z&J~@FFJM67MR18w_~Qby(-H0d zv3|_V%=?~h@&nQkS+bLXl%=pdgDn5eA6D|~G@PFK*v9o2_<+68WG zdayxv-r<@Eft?nM@P4eKaQtZV(HZ^lw`r;|5DiW9FS8yWfmPO)1&F`--MvQq@-&g0 zjk2V812)Oo@oCG`ittw{!M z1Odd3;sd5Ort?Lg;o8e+CNiSSMU~7;JXJ*eYWBV*H76{nb(M97(Ji67;+R}<2dUs~%MZVx z)G}jC7%y95mi<0&E8a7b$V9$(7GC79KzdJ3bu83o4MRDVU1SdE9J<)hwkPnVRB4AQ zhpH*q6CT&O-o^W34$XkO7Q4n`)lGjxQtcSxj=yueZ{TDR_n~Hq z)&D3u&u}*1HjL}kt*zQ4En2l}Z)vM`Q4}>(dqnKLQd*P}MNt%0wMS~kj=e+e5j#SS z7zvR`_`i9-`S2W$onPl`R}AWG z)2!O7eI5iaN{j%sf-Pp1RgM`!)ydkZ%b#vI6Sn~|D!WIp_$&A%IEtwBxu;c2vac( zJpTL^$tN_;{6D%lDK73)wPBN!^rSAn<-KTLY0HX#Np+9_l&nj(rz zmsChyD~sTsnM98@$m6l)b+wjQ5_k9Jj&TJwB!5w)Z%!H_>sky-#!ER0OO7SFp2h{# z_YF@Dc^PCc%AQE#muUpIhmE9&Rpzh?FOQ9~R~ahrB{a9SxSr|QDI-jKEHd?5@x4O` za3~si;jif|^uSELx|u|SN>(pIowX=CvG27$4*nikhYx;=4^4=t=?+Vc9-o%0PCkSx z9@zHvE;Ap8`Pm#^KG%ya{5NA@p*_nvAaleJAM=LkkBa4b638Kf7NiweA6hBIAZymM zypfohm*Q4hatAkrM_#8=Zp0}j^3w-=$DK_rE+?g+nf9Tzz+JC`Knvpo+~$YR1AAx2yMAq*z-y@23+x(l@3X;a+DlrHz2NBpprp)VADXMJ&ZFne zRuU<5)z=KpHzw;|7t(v(iwCy*;MOf7b-PS`Tns4effwyTPau?$*=}~>A5C3rZf8w} z?}#mKO>F5Vv>A)lWkVa&<$jGTh1clv}zSx5MBk15>$Z}!mEFWY436=+a}%ei2~`ADpoBLiQ$sAra@G2Q#s zk9HhE(xXboPn+4ptn*E2csc^FEp1&=EX*4J(c$zH4m~5KAj9Z)&6jC6^6Ar=8E%oY zC>0he^K>nUK5(YT{CKmw!hKSS*c3LdTHpdvxOCOBSolGk9N+y$Hvu+s^V(*o;&LSP zex2AI&^B}Mr>2n7a^epDHLE+Td-jb;MXt`$v`4ygjJuWrKm+8;7lb65%Gp*&qn-y< z-tMZ_#a2fp&~r4*-`SI#*#S9ec(BZ~lHB@VbfmdfjX2dd-kqkH09Qe4)caH zdiZ8l!{v`3F4>2xq!O*ly)1jH(F^9)o`XXYPxivD_X=SNtmwOQN8fKqb3K?;|0DUT z%44xcIottMC|@iqB>2gZY_ZReny6=Rn?!(|>KdNAm!n@r>_!@6I7&_V_=nHLbLrmnwg7Ku>0bus8_ zZIPit_*R0Oh*s}-)VW5E7Db7qttfDpkY~=?KHBW zOR(}UdM@BsG}{UsfhCw!cN@3u_EDY)1w$jc#M(V>Xh`+y0(8`~FP6RVAUei;MYFu8 zV@&)G%lA}vnNRP4-nO(>99li&IO#~uaI;l^)8+o)SENJ><4l{6Re74v(rdU2F`!12P#>h=q(Ur|#H zk%#Nc1ouUR`?RH32guw`moEwDH%Rm7uAY&UeN03vW`_LY-De974E05-k^5fB&>N-G z-ix|7%AqQ#QlwXtyIoR8`y$FT1GY;*&Px)z{{kI=H_)!!k836?Ybjqy<@ZJ8la|;l z6}>s*J%7-mifQK;-MNAbu$I1a>QFRom$(Gx6@sT=YnmefmlMTJ-B(9sos?zd%~(cXKh z5bAqX)Jq9HHhpUu1Wzlg4MtGVc{No_y&$oqtDAb^wj+k@_-hwJXzh# zD*id@?Uy0Pfya~UD-;tbPJ~uoUL`>((#xv(JNl)dokZY}jg1G_ZX6xp zJ9Uo(12}#%O-!4wZ0j zXqWE!G=NEkFYp&fnD%M!zxi32pQApHOI#M{&3<);GRs_+LInIE`$@nz~rx|*7r>W$5JkN^DqDv65y!Mr$7v_T>4QUm9v z=e|+-_*t%P$1^;f~=R*Yj3nB={C@)Z7rRm2v1fZBWnP(ZFHiS8m-}i9%U%UW9OC>_Azua80}`+rk2|YN zs~kbeuinVf3oW-POuWueUzauLWy`ZF9_(pzz@tCN%dPwvUr+jcoOWq^{7?XA-8F!jLQ7B7k(EpS`GR57tZkj~YjU4P94^ zCwbGrOgUEdV*{eoggjcatArq94b)v=JeyvNO;bPHn{$ks4PEB@j7GLnRWB8|YB{F= z?IkGb^)uaj?}VVGCEKpHSrX8EusZXQx5?_FgIkv! z+1#cFudB!mzz7p_1nR?SyPcLVuGXlt8K zt8JSr<=OM=Lwz6AgBkmN7S-qogJT+!3?l2NwU|VG$fI9iD4Q5M^|;i!{@F z>y-2s>ls&N;`|@onhR^fuY>^RFmhD-dkp`>yIN~mVNQGzkCIY3JPq-EjamF&L;MGr zf_F8}Gls^I(td8QmR|L54|j<)TCOv=x1};yc`%h}a6qE5=l&*6h|vD!Zk0W{t);Kp zvO@CFHwf;@4tq>Z@~Sq%WR~eEn*t9>VMg!K1{(TOS7_>;&Q%Y zuxnW**6OEjS?423H5rB$pSyi*yz}qmcAYKI+BhZUDHZVpLPHWShnP3#q(V$nQf8R) zVkOP1mqf-F1$%SMOM^Vz#=emksyHFks24>GqE%jA(i7yrodx#_;uXYw`o#dWSC}*E zBUo1^mUbYBL!<KPpv;--&ixWVcq}Q5T0z&81?K8Z;r7LJ1}q2cz!Iy>NIoIn(r%C`)aUUlt~L4(Z6E1^_)dStv1OmTUIHKDaTm6 zIycjVoSyLWP7$ScRFqAO`4#wgRGUN4p?5{=!84;IZiW^4LYJm$^Dft~Rh?(4T)}#P-5H8G^!hQ@12{~-@a*3WHTYu z<%;GA4eg%E#6N&vPU6T@2brD(<1zWw0G`ZXSkWmx0|P^2H1*5`pG)st(q(g+R)qSH>j!*DtDQg#vM zZ9}q!ze6B?jQpC-^XlJc=XI{8e6g9D?!0D6X^Nrnk>*s-XASlv-XW)Nrvrq*ZG4EP zcLpudbFrx}6T071*BLvM)=FNZoCun^PVdf5@iiPz4O05_LWsrdUq7=yM{T^$cmIzr z^_%#*JIFu_cFIyqyb1RFcp@Rn0}_0hz-HIjX37!l*XLMCzlP{dU|89!U?5hU%q^|) zj6w7JzYyAbbPp>hde^l6$-|$+Fe7yV;-ihWPA2%C!Cnh2r(Xvb7z;wf-+__$T%Ohk z+-*(F_DnZ9i8*_#$>Nm6-|xeh!C%S3^v|Io(4;a?ah5=M{q|ti$%Gl1v7<||3>5c! zY9lMc;ZliGs&IOY{r~V7{I2Z_NTW)&(3lkHzRUTOgO=ddgmqJ*=#r66VZW&9)Sqe^ zr`*mHo)rqBDE~8{GSy7mOhA0$cU2uOSK|_Jj_ub7z8oB$3*H)se&rr>v|W%HP8*c} z*d|}y0K<=L>etCKmnjMG%(bGU2#+%Fzs|631PE-!9Sb_tIxrvLmNsKm<>1$g*D4(0 zc}IZwHU*MSr|f;zpo*=k1&h*_KiA`B?`GVg!+-boT!{E#f{X|a`%T&&0hbA+tt~R* zI5K6`;~A1n))I5kH@I?{8Y68fp9$n z&c&=WkpO+y1B$@r(tDX1h#a)mxc9cHvCY09n}euS5GgMsQS#0?v6_sm9HQ|AyobS{Q2sI9l>71s-hv3s&zsuJtn>2^BKRbhWmt(Ez8)C?PQDG&caENZbhs; zMG>-CZ;T!wzZl#sJ}xo%6|*kdY_tIxWHWUhH9$*U$nx?PaePx&hXACu>9NFPc8vOp zvI-N2{SkPtlXUF)VJO_qpv1k!UVWiW`--v2ow(qXkEplNy=xqBh3lb>Y&zAwXs$1J zWmgW=xSkJ?G7dFfl0d6j*><3&v>B~G&j|~{P-hs|9+RF5QPSF$R`|m|Z4gelpVr_f zHccD?{i8Tkao^~)lp{)@D|zPN#qa?Y`5#@J!}Yg?_6Jpr9LH}Qo-}g{wf{$F2bfFm z$Ynv=kKWm4&y7BsgV#OI4VxsENX4r*WlSBmzUcgVVFi9^riMZLj?x6Oztb>z_LR^C zWml436T7+)n58!5cAUUG$CrysGYoCE106+$;qa5*ZCr_opLG>fj9KIQ%gI>wJJ1IU0M@s+E}QL z2b;YWS9jk0l~$W7hu~4dw>Mw@zF*d5LxB0?Dii$5bX9sP`5I$wYK(+RhaW*j82NBY z{_s&6;i7}~OQnVRtQ2H!eyk02(7#j5a=)&%OLOSjyUSxbU)8mB@R2W8zuRRVd!Qwj zF}5TiEmS~_n7|NegIM&s^1}-Sm9F{8C?Cpv!F%o!Jw#&)!-h}AaaE4ypL0{+9n2)= z!%kixtz0`boZH5*EsFLORDZ8FwQ)D>bPCB4YCaauL<-wKJ~QMJ9nla*u;?_&ILfsP zB{L`sZ30PrqUF;2bJJ_|A==F-iy(&c>q5udF0uJVqj`f_jBx1jkDdd0f2CajoZZ*KP>b?yis;U9fvguN&S>{Fgvwu?} zG0Pp*O*q;zv75+TlTI`C$lCDN&z9eQ!TCX;UZK`JvXpml$uZpd&-UEPds(3QP?q8G zo`bN1sc$mGX{6VIvKYftb>m|1sfSK)DN znJG-L|6(u7<01Gm$6o>!W%uDl=`@5x@*4!sgCpZ}{4ujI3Bjd0$ELypz8Dn2U1D>C zkS@GgB!9)!CxVXa=ViN-<^!PinM!J&me#V} zq3hDIDF@o<{;7*hNs>c`JG;I>eYDw)c)A-u;)BQEEh%h`TlAxRI94s}=(R5Tz=Haf z!T%OnR>V3-0f7w0t#x6J^SUyCWt7Nd{lDs;qk}4YVPQ~q^2FQm^$FuVLP16<2#~zj3b69bc=Mp;sOv8`qxQz0@ub&s_U-HmbTCC?d;tnl5aW7p-Zfgd)!mHlOe7 zh1_*QGL$!y$WSjF z5TYZqxmAUb^#2#Q*3wMGPhJLAkH+TL!%!!}Z`_?1xu0_~Ml!%HO=bg;E*vMXCck*O zQQaqhixj`cL&%nJdqUiOy7o;%@ol_@V6oM?(;Z`t%IBLC)6K|F&BCEy`K+ov2+7x1G=rRlYGL~TKTOHHsfoRMY>JzZ`~Fi ze;GF8yb_9(rDzBHfQ)gxY~DGXw)2ha)j_n)Teex2vha-ZJ2*~hRoJaYX4AxkqqWVj zfoW^`2GX8^k!nu^bFJOv(&@~!s-V`qOe}G|Z&90Lgh{=ou8)dj;Avb=fL@aJ_+ZUb zUpFOM8)hg}d~Y11+pv7|YCnGT@apAo3ti_TmMV$D=^|0eL5)qlSpRYdjpBPub(Q|E zA=97bO&hOn_!rcxuV0}cBhf$1WN(%V)w?!OF&dS7qb@OiNr+waYkmEMu<*V}-*=mY zH}QK8^sMxW=0#6Z=i)`Nb{Fj9)Mtkpm$7K7ZqBoiTfq}g?2}U02?6}H%*$r_%Xfj< zA%H}rO}2;XfynY_CE2yx96j~(U^isk$jce#{P^2>L7M^c|LRf?Vu+?w;ZFnoH!Yhc zYmp43;3ZH^Wq$E~l<1RxcGeP}!8tu%)78X-I@CFwRyKa0%W}(-RiCq35Z(2OBSK01 zyCG1QMG;^Kb^xs4VT`Wj0Z#F!X0+eI@gr>{T4%Z>OLSeyQue_)GIF$u3FsjIjB zo$yT47Z2CK_p;PW2$^%q?(W8(S8?Qcp6dZf0-noY=E< z_mmspGRbnw8vv>JKCt_3M9wGfK)Bx74?Bcau$}07Qxd~qY504E@Vc(}=`78?4uR5Q zqP#~7;+*D$tuZW*)STR-Oo1rC`%)q4&=Xk)q~H(pa;N~LnPvd$fM$m_f6-{&hY^@?-p$KJ&-6P8< zbtLHFioj)Gvi{Z9_&dxA+M!dTLEjf%ZH=b!&xA9aRVmS9;GgE<3AJ3_qi@H2iwjbx z1(FIKUk&Isa;{WrxTmfLfDSBjKQ)Et@%f-h`M$yi)Cw6fG1zLRdsrFaWEB+Yr~e6e zn4*2qgX{W7EQQzL0Agv$P4_!SPhPIaGa|TCkC0Rv1F%!&4k?==IFDL8V^MEGX0ELW zxyl>}^_TW3vQjqz;_~bMn5#`i5d|#1*%@7DdCG~6P$v+Yp2pe0>DoyzM^e?C${&}x zHN+a{XD+=MP}iVacWgq&L0P1bkt&yHwRgquvVyIx)_T#6uTH=I|Jv|b_ly3J0%g75FzSF{~AZs=wIkZ+I$^V{&1p$I8RI=eyVFE|BUlP zKVc{(SeqVpo!@{QOc28k7kd-nmOJ7gb1E#!1v{bA{gr_`b%XXh&tF@E7Qvi%kG^TNYmUckzT=N)+>{MTxeMgO?5 zZa*eqaO%)$*QtnlfmDa_z=_d`MMLW#)#V3fXE40@@{M+xYdd}Vt`s#X(k^bCHQkkm zCO;pqHF&+nT%VU!5EvM+`lyPnxkqFAEb48%GD5gwJT~>B;-@b5Pqt~jd& z1lDrnBNMGg1uW#(a5ZNjd8wR?+a+je2t8j{GfQ-#Sp#3+O+`qkUR>wMYdF|^qW%-l{orjg!$Cu*JwC9*Kitm^Ib|-sjd}S6f zvyXw2U4dT|oe|_z4Vnt;;CdaNDPR9v#eX?H;DDgtU#QbS9rXW?F6Wy8FU@duwomns zdzGs?@MLi|-+d1lo$k*844`q73lYN$)Vh&i&VgO|^m^J;Np=oNUnFH{e??Q4cM(JN z*|ive%=Y!Ks27Vc z94O1r$R%UB`c(hl^n1dyw2wIV)*3W)(sr!;U0sskUMT5KD^{6aBc3y)p`+)UT>{B5 zONBw<_DRW;x}K1kN5-WeQf=l-3lOFkD5@6Zr7KNVyXaqjpmgu`kBJAB*vgw>%d~XP zLF)Uz8;3NF+U+O#chZe>zPk)7{+W#0+LRjx-d{ASUT4uz+iVtMDvd%JM7v`z31vw& zH8)uBEwc+p(+B|=U@jCi!4S3l2h=q>C$_qm=d^-km~{y-6?eoObc1v*yI~vkJRM z!UN}{$kyP%cyRFy@87lj7=y9g@5nz^om3!gbNdyD(9Z-`pEZxhT}E?LS5(AjPvkaR z!)ROMl?!LhN6=YBXA`&!46Xpr|IRb)*znaYl7F1S2Y3$dL_+jQ{G*>+954b(kb`r) z2z}4JKiU4GqX=!4y$x1$qP2ciC18btdfx*>-^T#U1STMzfn4vv_1qlJSi}S*kB~zF z$fom32u2N%8yuA-%?U3n3IyC7e@=gnw>>{A8KJ3IKG9NZ<@Sr7 zngcr^4rs??+gXh1-^md@@Q9i6W2!+^;m6nBgPu-2lQ)2Q zO?q{7a0}2MxDXX zbYWCckL0dUOk()n@gWP&m}be}n{ES!k8@u?Wcuh*KM#u9w`&Qk%+#IGiT0?h{^AhSS_qR~ z)$yRiD`Ilmx@w`vxl~;R8RuQhGXMTF+0wIxNt-s0mWt+m(=Ucvs6j>U0>$FrCjx1nfr&-rb(C1N4-VI!o`_u;SOgT0PQLG#=alcKy%6UTjvpZp;z7@s>Wt9sy5 zZjVn*FH(YPKvu)~{$W1x)9#H2NWEw_R*P4ZZ>6{>nZBH0+g8m@c61WJPmD>R09pn| zo?oC6bk}YhKgndSZ%KB>mnS%h{u>FxIP)gvJ+KZW7)Hy`Cg`QU7SES)#%*6eZkOAi zMp}nz9mJ^D97g{>sTT(g&?G>%?AK7qfd2Bb{U{ZVrY6(I35fmsj+2(Bqj*mhn}JL9 z;Mt;B2arN+fS z7gZiy8sM!9;-^aNN1tCK)oAI4^ezDor{c#G>s*?AVOe(cK!tdK*kK3U^FV($YXupD zyf3E0=Zd`Ba_=VR0aQ|t6lI}jyKgkq^$YDd-q}1 ze1|3}MYQ8Q*qSx!$`Q)zBTU)WSz(4VZVjRgx>PU==C6_Kno zV3DOdr2?3zYMfOl1+C^@o7FD?znSHlmbudd@g=3l{J>yg(i|`NQyQNS-DQ|;dvd6r z$lvV|P1{zLp2F8+Tf~B^cN7vb+lI=JQq6sLFV|eY@?TRSXGy_F?6WkuY`wn8BK##4nf;rNb}Zy46eUesq#IQA#h%QVDvQ}pwb7mnqgb*&7Y%}*8ZcLmt0M!3P54(8;L%A>9IGj zyJ2(GlQs~(CVC8X{?bJLgtjaHkQ_i~2U2FM1hA#i!H= zmc=DZZ<-#MuB8ygUyYR5p7jS+K!)K)v8vCKVYci%E220-W*pLgD+A_DpZFLVZW-x~Yzb^^M5bt5! zXpww7_aqvcz>bAYDio~MLPe*W{M@*+|D!weJEaw?x6)VqtDKEA5Cp!_j3&8_#FQU& zro7`BP82@UlbMkaD8rTj?=z>sa*T1xU#9ngTve83jNC~oG3Pw>Ix{zD?M8wi5Y{x+ zMn=~AU0ZUPM-lrR5{q7Q;$6l=0}n4R??^WnnY_;x!64FM-ty-f(x-NQ6jl=8Z9_uA z*pc+BUJ{GGCfWKWL;BUK#IJ`Bm?_b%rIu1)EI;-2EWa-`PB5EJ+x}{BV;c3{NCd2G4!7F4JC>bfX*EW*2le+o!!=;p&dO>-l zEr@PeJwYt`NQQQe1j|i5NZ;+h zQUjQ`HAQHY3S=!aqGmYE>8;LZH1?hJb;w!cY!@&gJQlI*aImT4@>_*v!qCy*@l_Nb z!g7U21oIP0`P3sN>b{#Z7Tl#DME3{!NQXXYG%}dRvecytw(7!^IB=TR{ zjua5*&hz34A{f_cYf-}YI(XCH#}I+Ly(XrZ;CfhJZ0y^V;v3e#zR3pv+fM^fCdRzk z0s^B#^tagM z>P4Y`0u3Egs5Bg@new=5h5#>yu6_w;UjnCSv3xoLO9ePBUTKoBv767gyEMZ&W3&SJ z)W$(lp8?DU>!tr*u;S?vnnQmHaNu0|s(c2Pf2->jy2%(Am4bODnHSwfK?Q}!nDPqC zSWL0ashEI{;~SNZH#3LE?VZv70Vj*oamxC`FJoBa9p7hX%TLxHnp>a`H# z-!=9Kk0pufOLc+1{agD3LHMkwY70!N2q2UoKawPpj^FB-t?E&F;i?;Ya)ot>JdOR3Kfu0j$Xv8?LS?N`8ltw~Ty_vkr5f6Y*0N zXfCTrV5`holX)AnS5KVnRondFd6cYvSc4eio?bkOfBo}L%YmM2clzxh&+XXtuF<9L zthb?g_{N>-pAFHPINr#sE=)`T;e_DI>jR3X>{zVSBg9wfE?$`)2XgkzAzx~ddxoP! ztW18f<6^A5GJ_IKAOSE3Ibp0!$wX_H zg7>WB!0$bbo6wAUabryU*99k7s**p1kHJeUwXq5>6|R3ng>2I!UD17a*X*&MnWp_>;xGibkgIUA4({p)fg48Xea}*B~FU zR2@2cl7YEZ{=m~)enP{hT92w%*1)5* zHJJcV26bwd*7trfI5iZ@K0d8QKLqBsnwuGMH0H$1j~1A$x*Mse1DvDfrfCDT#?vOx zYO^HX{h&6Eavzc0;}#`a6hlYTLwC+=0{A!de!Q)(`i~C$JVQNY#DQS6UuM4p9Kb9^nA&J>&0IE z$M&=#3xb4jR=~BxA7vqvIhM~BH8=NU4|TYEAzx;^PXXrTQnFJO>y4%jcnrER-F^(i z@jWG>i}3r>ky+lPQopE$TaN3l7+Zop>w=ysOa*k_YCc(%jDJN|!87U8+S`3U2dp)i zl6XG5HFbv_RZrI6Xu=0VC|pNXXp97W`5 z({Uwl$zLT_{T(M)Sh4!NDf)FSCT$j=Maezk9U%_?uRJUrqeDl#&e4mIJd;I{>0b2t z*X9;fK3|%3p!Ag=c81RD;#N}Q+9g%?_eF1Fzqqf{MK)Op?eAgRU-8|l=|Uq% z1gz^U6Q*UZv&C*z9=|N9@XbYrVV@y9wMdmseYnc8$M+}(YZ9=q^eQ*-Ax3byP;m-S zRgsPP)%+moWtk3Jw7RgwT*th|67SExO>>%#-lQuOzVZ51@gSec`4c{vx*(tmRjjeW zAgDWMjDJGu8Ijl6&Ce^x@@ke{m*hZw!B%uC?A{hutWVoD3u@;QK-||V7Efh2W3h2? zoRgsDKE0JVa&6s?P-L+vozVTa#jF2-oLsrZy`;tAI7QFKO7AbZJpC(k8OL&W!LsQ4 z*A}R7RkX<*;h7^>&B9-UY&+L4oMSp0$o+1M`x*)BHwSJdL?Bdt0MauPyGl>kA^i;r z2%&QAeYU9IOM2eVd!HXw+$>&cLYSH~Ea0kAq2u!2dJKnj^lV3HlSd7xGFB^lYqK;O zfYr|k9C3_#`+A!RE;6oL&5GWuQQPQi4c;|q^y&*eHAog^|Iu}ie9>Z8sk}#vcq|{U%-IlGHi|JChJnGy5gk4GBCNB zs|D3}W+KXKyZls79eO&&bd*3`JeaSkg$<$}Ea@+h-%4opUSA~PeqJ!hZ*!Su27{sE z207vql7bL}+!mGq`H~Ei>8TsQjOM#C11csrho1Cpx(8x%gBu@b_DRfDmzFl=OO+nh zKsdfLTZ`wM38|d+x;$x!K*%PSR=I=3-!%@rhG}s9yD)JLzH98x=<&VB$d1**C%17c z{)YcQOoF{{s{g({MLRL;+^qOcwz}e!ke^8XATxI4>aQ-#L}PSi$}cy-p`(1I2|dLLJtKlvf+pcWep0{k3j2MiaHF8T1DWDBmScs zzk?f1v#BDrbA<0fiMR`avQu*vD zw#qOSrTC@Hzi!ytxU5EYDZZ0zS9=RS^w;lq6tb4xqgHgi-VoKQTKb9gk~iKvsI=aH zi$UYUFDvRAG)ov+CK?bk1Zgfre++xXEzR*p88cPy9>`)>b8ih7Ip z%qlRDD1MQANenfxkKQPkPkT4!oyE>hY`Z$w(P+>J)poZn%(Z zmsuPEe>{l-d$4L|Ye$782Ymr#OhRma*tI$>y4(aeJx80UiGGf^+rcM(J8;El507PB z{Wl{F7fdLd4ILWA=w@mbra7HaR3WMJ-y7a_-U%iQ$(0 zK39dQOm=G(x@>h;N^wA{**@uBK@G*w ztTPs?QE#uLpZ1;y5rl=|WzvGtN*!g@rczt37Pe@k}Co`xc6x#kXFd`NN96 z|9;#^o~kU0{rqd^?H8=SCVrX5zQ4LcDk*nm4(`%EJY;%FlHAR;3Gw>-dCAfJCW^3OOajZyGZPiHUd3a8AS z+Y(yra!a0H@DBBan?mB9xi7^HP=1@QJFSgPgZC4$WDTnwv{Yw@iMcHU@&&LpA9v6KxfR2?D= z6OroSK1sLH;vz+^7ZOgwrU!3&@pCe57HB|9TU#gH$8~B_u%djFe7Y4v{Pd>)om=A) zWX-aZ`VAHgmi}*CWs_#i8zY|Ppzl`0&CTxoLh~P#oQUU57KyVneOG5tlvn=SyCpT= zyGelIS?ax<{7P9)PTRKUXK_-Xgf>1BBiLc(%%kfR5VIcA9Af5Slj_bg>?5QJ``jL% zPIoDF@nal?o_L1PRV3;k8bmH;Y}7F0T0^mm!vC`RLEo>KQqx;~pa(h}A-Q+Xdz(0o z)Td8|M0z?B5Pb+=Je@H|1c&JOv#TL94(x{siXtOHYK@%0PT*`C!w2Bi&>(o=mv?sLrUxxK44lWy`)LbTQpV?^3!{AM@Q77%%^c(~cgWxh}QRo;^xz5VYb9dX_7 z_ZC`ac<6)Eg;`G7pX}*`-z;J&9@(W?yW+&<#`VMsU2hAm#}Kifg05NGA}$RirZJx zeZ5_03~_ja6oC(NBYVwFrUD13f=S>?`Fyu{=Mb^^I@kDOu3N-C*4*X$nyf=~;oo~` zRy-{(Zilnn{bXDyvKB0f0|~?T8r;fGK<}S1Sc8Y4U@O^fKn)OAQ9#v>9yM${Am)8* z4U}CB^2bFra4_x_TL&o}GZ`d%rw)9xs)U`K-@JVbu}n`DZL?~wc1=iiUN>17OS=R7 zNOwnLX^=8A0lnyFvj&Pe4O>sv@g6tR0FDCshx_Rs!e8W$w+WNThh{)`U2ta;f8?@B z(>M-}NjqP%@L})c_K%%JvfWF&5)j%K&rZo|KfOT$=+KfOL*X^(>e5}K8-L#9NBppp z9yMDM;MERj%#&euG<2A25MAQ3xRiWh-Bj@~r5hh8w(4G2Y}Q}qc-UjFH+bU9%T@Fb_5+-0)&W8`&;C-heu)!a0ER>3xD z8s}2C)Yr}!zHkmiO!@#~;TW}CoPk(>j)nJyE9wmNtn%EyvP1r_r;!pRH!#-88@gRS zWN{X&)@w;`*-sgJY4PWPOWX7DGhncv6IXXZvXD?=lz+qrf0^gPah~_<4EIOIK-I6 zY-_i5DEzwh%{@qYi~R*ucm}-sB*gNZxBTbfZRN(?jS!75?E0U8HLx!~TjIpT9_aWc zJ=5YC{yJzhWS4WnP(Q2zo^vde6jW@bUEa^)!#XI_DnHNM-b{?5_i=(aU9;rKkrd zhCqJO<&$lQSHqz+HCbp+!vUr~YTZD8`2d_tilw{{ME5M;@e^S&IlMA;p6lff9kYHvz-ENR zVjdo%nT{4{gfQS0a**?e3*)^~rSZ~dqe^9dC(1h`NHBa>_Qe6Hz195W73_Z$oo76o zZ5xO6(N;@UTSe^_rA6&MyR51zwS&~2Ns8LR(}CJWQ53Dc)riEqgOf6n^MDugrD zNZS7aZG3;PJ0gjUXRf3fe8=>-`MIr>nM2+3-e&NIh)e769rY{j<(;RG?*}ePCnyTu zcs@fGkkS8MH(p&xTF|k-Jl8I`$Crz?_oK4F8M9ZJV%rQVl~T{@#XdT+ce(}}ZYRt? zWvpjxAn8UhPoMqJU^xK4Z0ne!Jy}k8HvGesZn0)XbbvmVGSCRrLJ-XYLj*^5?;AAj zgs=h;5Q1eu1Yd}kmK2Z%7if$;%&B_2?RR%5exgHv`TdeldJWrIk=FU`i1W}YXQRh> z`~67jl}c5M%0nua>^9cJ^NTb4ex#I*o|);Dz+`{phR_ zS9O<%z;4ajtRdCV3i*!Caw6YlNlrE@_fUgn`?#iXv$jR&d?cOg>~kQkBGi=E$3{xJ z;Ijx3^91W6SGx2blwWo(cDv&$EuiIuU8!_`VPR1e;dZQ^q%H20^y7X*yz;D2Q*Vj^ zN8%n%x5qMo!|L3x)o;|Gk_DbeSzkSu9s@|*W zUM(Q`^b|`?y<>RP#`0dLHgC|vsq3V-BKpFl_XD@&s)hY%Y}-X{6($BCNPHIo%z33_ zB3uCiX1Meur%if!{(-Z{^n>sTl96ymS1FO)thf#q(Bh$40{71{F#eC+0L-yu=eX90 zE5qx?m79-2OpF0Rr9pQjFHy5;h993W2hVl12u9uhENb>zx>!IH556G;|v}vY4 zlC16~eXlCa?ZuyMH}BTcr*ft0k%^aR*5zS2>`)D2oM^Ddb-+V&$|@V-1?KJ(c+p-V zrv@)O-bk<%D-+JmkuwSt%n$!fztk}a|IhAn*P3AEU%S>da}kFITXg6Ab}0q=zEnJ6T;HoZ-NE-Vo$q9>6iDGRJos?vR3!I zEbfqABm!4@5P#?~(T=Sfd?E^L(-~Tb+MR>l!4f1idiB2MQbwU?61m0V-^|yN9_R7D z*$zkqPMy0+lsrLWY5+~|{ZqXI%TGhmERj=%I*!5g;|oueiKqi+QV(tK+V(JssOPmw zu7Nwt(6;|}&C)M}_5*Oe3aOnfZ&RcPhp4kP)GG5Mpm{FcWf8x-pTy_s44P5XLzRI7}V|N<>N0u zM7)uIec-QScY9cvzfk>aINCO;6F}onnSifXF`ElUkyQzZhDRnsk?b8Iw;8oc_;UKH z0@Sr^iQw!LukJDrgNAUEZ;l?8JtI|@e0$ojAMVj^wv33LeL*byj!R0uOSXTU{Ymqa z@HeOmpvT+K*cqjY&|FRu_UXMF-Kd*T1#LEU`KpgE>-1|=Cx`h~`GaeKLTjlY_n&FH zX!v0G?YglC*{0JEJ{w+0(X}_szsfA#!NPMmdUBT>=^w#LG!_-zNhEMFb^gNgGSx$r#_?8aaf}$PB3@J*dudb(T#{Am& z&XOy8GCLemYfNJ=(LF0_V{%&I_8+~zNk(so{6Rh$SgeWs^~>S!2-`3bTm)`(>jv&g zpTPCnaSAy~)73TA0H5XmPZ;H!iugsDkV9~8UVTKbaRR>n>iZ6kNji(?EKFen4GVo+ z|Gnu|%8SK+FKJbs1lH)We#*Fu(KtN`Dshg@tF5kD*_*>3W2QPdwqwq!eqc2!F09Xu zr$41u>#MG7egFHnrYU0S`&fhhZSOV99cc`mLad<&R z=~(bJ1&pRRiNLJmT)u^txOqNJm64e@2MfqaQJB=_+=>I?V}n@*BOV;kn=y|RPJ2LH z#T`O!e?GUD81?hFMO;~Ewn@odgM!hBrL6ythr41XoXpN}y^EC?tS^P;@qY;_xVz>P zoTTHI_l@z9Ewk?ccdiAnTsD&zRLiD> zTal^L!}Gb(BGTXo2Y`=@2jH9{7C!velG~5?2&A2#fNgS0{C_5e{PeY=ReY1H?UQIo zY|G_R`;rwmgP-{^IPna7)oC?whw4VXO~>K@yi+jDEC23kIob`1xo+|JkKFgS0~=x` zFC>n*mUj_ipEP*AMDW|!Ib47s4kgtyuS4XLVAp>Pyx|Li4gPt*NBM(v+T@*FlM4f& zJ@A2Rkj^WCN8FuDZ+9gAzUs13+f=jlM2Y7|&I8zyfZWV8(A?IK@EJwte($7=h>46h zc6jCesnGcNLWp?+s@0I3E$m}+m{L2YX{K9swoaGce(o(buS5jsJs=jcHFXkDrUf(( zPXQv}O!?-}@P--~VFw+tGxf9Iwj4O~8;fCSwd4%i;lt|#hY|JkQF1wVJpv_OFO&|! zOAjZtKW{>CgR=>Mu72iUVdQ5BhE#L%YSjtxo=5=^ihV>z9+%fpwU?hcFIJY~1O63u zrwx3Kq-1vNDZDyKxS6(i?>pO%jCBl6p@OCg&Wh3g1Q3Rjp8zq1(%$Z@M&|UbIp|8; zE+u1kTm+M8O!nY0mOkmQaa}@xpqVu%Jn(h-ie!D+k8$p&Se|7W@Rkf42wwyo@!)nq zb5nFj(ScJtTOEl2I=p~S3HfR+ExDGoQ=Bs)!A>*3T{UGlC_J*4nV#Jol1JT23%6II z;mOlV))#y3bhy%q|L`|S$a*IFA7}C+<4wPrR7Naf!*Mg-Se?- z5)I!CPPM-b9EmmI<0wuot)S5^)K%}lIl&5sF}atd8cx#E&ui-HOKKYP`937>0FN?_ z!>|{9V55DJX1jm78Infr9nehZm_}T=B-JM=V%lAvtL6Q-Cq#RG+Oay(z)|S07A0}y zewu+DhJIv|$dNFkNCCM5&c2O4Vg^uOIUHz5h0E&g7cAkTVJpUbb~-m}-cnp94V`nw zLn0RpU|%lZd>>Tp*NNIUsY&>c;h%6J_kcX^2XB=p0hps!u{^&eH=E@{^47UMqJe{J zhP-2fyC#peep@PE9ylvoLCdvQ0turr#U2{Rfpl6;@q>b1Uia&Lon6ZHJ-6aChlXS&ic z5L6HmlK#eez=yEgFM?u7;c8+$;O5@PN2B(w_F{6irWG)thLa=cLnj%F|ZWFbtmA9D8rKqOzMiz{>3Mubv3{&v{^nf^Zv z?D?aD)%}q$=jv{i#S{@|$QvU3X1%40NX1js zds7u>pBD#D)2AWa&Gd(n07E<)X2_r@kJ2K3pSQt2$#w*m4Bu{@vZx?Q6=4{vXMr>^%Rf{>>H zNCi*&JQA@fdfjr%)?Cn?fKFl};yCD*eTv(NlS@c^I{sx-6rnIO8=e=uGD^rZwn;Ug zs`l?OYiaT-OyV{1T}*m3DRA^^Bt@Tw0B5I}(?#iD@Ca5kB5;=ySP#G1gxcPL z%y6@`#5Gq;{o&F%46ZO{IN>*hXUBt=U}2XX)~;V#0J~e?>WgAQ5-d(bLnqVq(v@*| ziAH?to^!zYV{&oKJQvsRS+u-lU`ng}g+-Ly+VO=Jw!!aFB$pZC_7vBw70xT!a|1}G zFN_*&CNG1b6Yy3bf213ZkLEMEg88wS*KThKV>zU+wA}WDwGd{?TddMNWct>~cm;N_(yAjz03?d>!yR7Wa6Ca_=N)=EH z;#R#f+^iC?RuY)q4qnZY$48hK-HR7eD$jd?>&a4)u}_UL${FCP_e33 z@XcL1=KygS9tNPWkVt>Q`8}J=*$|w4A14sytlgIU{&8IbCVcNzlK0x|%)!D}rHsV^ zn)(}j6e~Q@iRK!1k?WazE+{HFn*|9&H)nYHV1#n~{0Vvl+7QaWQHoeHIa5&IVyHs* zr{t-J!?F|S6#h6bYIGyL!m#K=zs=ZXHPwb2IFCD!+P+r8{28(NSaYi(PXZRKfwZ7z zH~KF*7{9VyOa6gOc~gl#o4`wj_#}D}A~4D;>$TrcDvV-#Pq&8C3>#h=v|H;9Hkn4? zHfCC7tn^~a%Y>u(jO>7 z6WiR|lbPI#?WPOMJ~t>_DPkF0?=Fj9-s@AqpV-^qtxr_hQv^}dY>9YbOoPkF`niH% zBJbWClWGDqWX-pSlCm>ynKu565dM2nT{RQsk9-@41kixC&2;TUQ~6ZdBA30%X5CmlTBn`l-Wh7r$Fh;-%ep zY>7IE2$a{2qdosYeS1`*cg=OMaqq$7v%TN@USGFJPfeZBFVTq9vmA`Uc0V8-a1t5p zDK-bMnBxh#ACf{sx+Nd1*Zr=dN#Z4>!oQgY_gIo+TiMqwFs-m+eR9?1FW&mj6c9QU z?Qb_|-Y9oGaNaSS&x@zl&4omFbBjOb-ck{n@_lac)PG?MB|X@AyxO5Qr53rCBEhj( z_Xb_tNF06qX!{krs`n=Zs}kAx#-L_``PwQ;Kh^o(^7e! zh7n$Z^Q(-J>S@U9i^~SoMa!oi1F2#H(c=N9i0X`@ZjQDHSN&N6C}OcL@_2LjNtt`2 zmdNCUb;Dc-onk{0%u=+iS8={|p1R}|;8_wy^C&v$?vmMF(3!3-D^f63Lwm{D_Lj#q z|CCP&b*c)sjEY#w&t*Pf>KQ$G{5Q1f5uzf>OA}|<`*Xy(bNk!DFM%qG%4F(1ce7p@ zk+XxhF(GyE&}K#vOE{3z9SNta{aqbFhcTivoFyz3MDUUPj4wNxN@;Q{=WU$Nn;s7Dpy-mIaU$PA>xxhYdu zU+i7yC{(pFO%;(Zp)*BRzZE_$^wV6&xCQ++yV&5bMplYS&!qgo`q?tQR&Vd}h=F)m z1=}wzrAeB<7yo)f`NCEfDTw1?Tt@O`THkD(Jo1sqGL;;&}X{-w*iA28BPJLC)g?3Hg zJ#&ImW}%Dzs{Ca@#O2&l5CKm!`dwPoEH-IU7O~PPa8;~$m^TSq?c=b=J8%XXoGoo8me4YFr z1r#_sb;CenME>NsM<-a$0CsFO>j>PXuVklv%`H?G-h9X*3~o?>I+4;{@#`9HUeLYf zh$>JEZcLPYBR~>x$Z#?4qWEeiDxO?U(eE_+RBml<)jPivyqfeZv!1yEd7AD|n38}O zs9tGHes~qjw(un%5I%s&x%NB02CS30Q`0Xqc*)+W)ZshPd2POWgEAN0Ex>hkJ01lA zS1?o0D~&}CN5qS&fE7K^uDPy7T9%~2y8c?}pz>?g+h^h!_Sv$c3Wcn~#$5r6EN3p> z4ZHDS6f@A0IR^|hr92Kn?OpXkyE*|bF3y?G386b%T4^shJbpY(fCDt8s8^;q#@P{2t>4Y7=Yk(menE z>C63rwGH-rTqfL8KX{)+C$4p(`Kx~YDi2hWp_ow0T0`T)OdUEIiapyE9y6 zQcEc4;;h-EjrD^)A+tjZhc~T@@4K0<7U|*&a`WqH{s$nSwqlvVQ$c1{Yc6s#BTiK7HH^bHjp`<%9vZh=<2hQ>u$;?Jwe9S|KiBi;{?1KvI3ikb#U+S^wJW z$+wi-2{tpsnaPcNX0WtI-$xcZw@xj2m$erRf6)~>?6eK1IG|ALOj8ohkWEEzMENt< zUdXDZrbI)iY2y~g!lmhTV$ajqUnHPVj$)c9ep~)(BHz8-zii5~c=E3(@+*R>JJ>4v zu&VaCdR;io+g$UR3w;=r6Q80EkJE_Iw)-w$@|KiAzXQ0#htK*?`4r@IJakNBxLgmh+D6o*CN#nYFTXdSFpUrLmGY4sgHB85VH7{)!UG51+L2BFS#!3dew_#}tHF9B#y> z#Yq@*TZ=k=!_kL-HKx@!Iog`o14sX3 zkj!^X9L#CV3yDz<##t}cuzbqQl822EqV%}Q-&rM^+>!&IP>B_5a>7g&!t1ZEHw#45 z8OS65_f;cg1lV0J|oYmu9mFY$lDs#ZkTy!>}7kECi4dJDktiWTjLjwTfU7A zyORc3D2Y{^A_?zVzdQWY)5_Uue!kd~}f!!sG4cp#K;wa3C4Jx@$p29YO20pDVRM2A|RZ17G7ISy>G3mp4;7 zG@fc2Z7@FZxRPWmqias#@>@$rv|q63XrlUQl#Yvx6eYV^MxOBAbY`2)DhsM9eG=W| z!Jck6D8)tnp|XKj3^DwapZPSxSCN!Ihb`b^t=cn^h^hEuv4oWjAal}RCmh$KnGKMy z|L_Mh3ae_2m44pw*UcU=VJw$P<_Z*nKtlraL$AX`BthQ8pZFhtr3X-wYEP4nOOc7V zdthMZ9;nvZM~+ds+^oL(gSM60)Z1OB+w@tyKzXR$gcQV3!Jrm8i9sVXZCpt6R#4aY zl1nldEkC51%I(&tgppb*lzMERH<^%SXH_>}&JTU=AD18ojXQ=VkRxKE*ba+sOD+b5 z8#GwHM6w{)EL;pSALk661Ald!DfQTvOpowg#+v1qH?G-j+`4my`YS$}^fDKR-&tSv ztV0eX(Jr_Uw_+b$`u24UQO_-tG$v7+$t5UWyvBbPoPXOzkF~0Dlv%&S*CmtNUODO3 zOPO#}d0cYUPzEnI9HDy&GYcKNXgs7D=HA@Yj6`L>%?=->R+V?@B*AdEG)SSRliu(F zh2yRY{W;@yMB2BF^8#!f53QR#oSXVBQk_A{YB3yvN1X!Gf_nuCbF^_FlC6Mg;qrnU zt4-5akgepi)|@HY@RtQYgs&cV`D}uZ7cVW>5u-+2>~LHTdv-Wed{;kRbrm_Sfl~Lv z+y-aJ)RiB^3w~M40uc|&bK0*bnTg;uT`QU>UMZmmsQ z=Md>*=|n<9W`^6>R~~-x%S|I{<~NMjBO5)O7jgFCmJV{&bOzySnF!`Vul_xelzR(y zpKIU7fOZf54X9mXx50Y@`hjIPgUrmK%Gv9maGD?72`?^*{m{l$^Y-F-8esp_RaXVg zcw!m{kJkw|#fEFxy5;vfBQXnA>vm+s0e+|l4_EOvwrVA= zy5c+fFQyig+;bzos*3KS`!d81o&c-Q^cFVC1&KpkBe1C9L-w?lA4cVa?1AVEu<{Lv z*uQ~*)8C`YIdSq{E7B#y3jz(Y{jd;)j9qn%DCqOuvJNRAzQ`1gw@~NJm#J&Gr!io0 zGlKF*a5tn(wNoL3^$O4XhXIrUB*7S47qyn6=2$>wY1~T-6#C*CkzFGusan#9j=MqOobA+Vgds`Py*4Pz3Q5&I*d$0}OB&Kfx z#ob|qYF%Pg8pSuhwT0?f(3n}nQD}*)Ny?lJ#B2JhI~GQTRs@Tfx#uca(AVPrsA#Oz zlyc+lO+eb7lvD=BR@S?uxg`0LloIt|RoaFVOZ(V(r7AU1v3uay_rs2Vlnss9%sq7pw4xEe z=X_t{BXSQMFM9n(Bw@OjBU|N+R^k*EFzHsDdW)rOyw6A~yqlOa-K-p7H*0 zb@m%Fqj!q@o@=_c?3^^8%m(+y#Ric{h*Z^_0ZW^lgLP1{cH4^?q7{lYTqwwLB`Ot| zDPBE^)1CQYTXB}SB;VI?5z<}Cz@Y(17@O2jr%p@d9tAjqRAjv5l>(w@Tr`qT0Wie zfRG9*b{ty0ASx!gQFS>hJADOnzxIJl;v6x9B=mc%QzNeKCuy9%A$FeOp;&6xA5jDs zuZ?E;z{k0S)_@m5Obg9k;5Y&Hq(1O|Vno-IBIKuBVeR9<%sSop_&rlC`wwX&JAUyN ze|^L1IMR}n$r%=l{C;DvlRQUyBa0Hk$6Eu3hIbSG$mWWN#)0oz&+h4+?X`4yb3h_%742D7{bJrTpT*KDBi?kXe|d${j?ClkjsFUN`yQ${N1(o%lGh^m(X(X;A+*$RT6TvMk4V*>LRSl}*;R>9puId0Uah zQEJSEuKrsYDoo$r&C)NJv35?2CgH6)>g{qu|ecNyP@ZNuYkK5_PSyH3y`B;nm5pIg(O;RZ`2KqitV z*Rg~zgd|6m5w)52E8GD+S=+WhmC%A;$=4xqLyPtD$}Z4HeSqhvuS;#k&co*&vmWX} zqRE$4hI5mO`)<+e(yN*r9oB8za|_ZLL)Mqxl%4}}IgP?LmZ#JEp6M525LOUUHUU!b zjS+ZU>G!DG@_Rwrp1H+4v6YqYGE;ZYu~nz9UbxScQMCa{zlOMa*M!zX`0gf#}TVN_Wq);SW=E zt1HJJZg^Ov$eb)yUwi`DwqKex6uw7kOvlc*H}U&QbfRGQwd*6?@~#y=8%h)gr!@wD zRDrGh@w0JQ4bCqeuwm-M zpknGsteq)oYk@3l*x@1SYTs^~`Ylkg*YnfZHc}k5d0##q7uOyRElBR<-?|62(6xnE zku&_@Lm{u(Y)=2Cf&{gPChOE{&e6aJV%>I+&)PIAJ#9eX9|o^uw{)T&1~Yno2B!B% z3$K~pb%$ojTj?keoxC7 z+PHoFvwYtxb6V|&6O=flWlrWxs(RYl*z7is+)Y~fob>#y%6|;olhC!&`9CAGRwtV) z+Sd$(?6($*hDM4-E!)ECbXRwsN(eoEEy{_C##g)q7qVQA*3;k>2s--hSXjQ?862*6 zN&sb7dj|D2A_$#WROgp?v?aLzg7X#C(&Oh7M9S9Siu6$@k8uuPB2QpD16=;hMVIQQ+?oOJ`>`IxILU z?{UmF*25scR5UX2gNXSycL#Z(*&2mg4hs|S$n(U{zk%0EO;c-Y(wq2eC#tO*|Bx&L z)+tCSTuv|t$zMtHMALA8@uFS9`k&T7IF81%r|s6PQNwP;Ihq_E;A+>tJ<8FR9*_{I zg?Gi~&9n<2hk}CqS=O-~E6<^nSc+3^XN^2Zk!VPeC3Py)dAP+~;!yZ(;r;V^sk2Jd z?&Mn96Y&a(;&HvN+*T26SS(okzGvv;KAwtuuuStZDWOB{`TrO+?;rexps-lurqn@L z#yXg~RjlU8H#=5*N4oyR9Xak`P3~hZaN83ndJ^dB@VDdIZUDG4u)^wV;8YvgH(0JL z+j;xSlJhE~=8JK#f-;SZcUeQGV#@{`FG=fTxmjz~d$7ts`t_n;lTX%mL3D+Q{k@GZ z%Um9UE)QA-9#`Xc5iVW=EI((ml^ex(n&&WKUW1kY4;B+(IAH2j9~B7lJ!sP@nk(6J ztY2RJ{Q4^<99wyAL--_UI0)dZY-^&upp)9sG^4w1-sWj{60(Jc1l>sSPmWA2sZRP%O73DzQK-cFEq+E3G-nYMT9J)5J8p}!)w}-$FHi< z*}e}|TsCfraWgU1Do)WnPv*bF&z(estq5MT#dNzleixVQ7j1G?x%6*xO1Ni|n+iJZ zcdk3)?MRxpQxr_rJdh6v2B8egzl`NKRccJv977JG&vs_SI`iUfwEL16=e$~kpQR(m zFI(K7l1%Z}-K9Q(KcCT1FX?>HK9ZUi?3VH% z^%~VT+v;1GP8f?wgp}U!AsmIP4#uh*czXDc)vWDWoC9tk2vfZdm1$$z<+AOhY>C!0 zLLo)@9xMZ5V8X@gOeam5*6e*y##TItT9T_nVm)JxaXvH_n&CtJ#QTi$*IF|Iu+uK} zhs+po^L4T9YA0nQT>y5o`Q;c1`K_+>t4K^`BPaA zi0V8vc{Ri|&W)9K2)CP(Az>KTF=q?j_)y-)UFuY9Ng&mH^g-e;EFy>!fh(lq_jv+w zsb^W91MA9I?5rPj<%^QIFpr>|HW{?{ioUz94hqB-nFgF;8)C!3dx}Cj%rbao9Gxeo z045vJN}ql{#1Tvhd?mQ&EKQwa7*YBO{KDUpL-PP}j`n!CO|-kq#-4<^e%bZ1vkiKr zDO3{uw~#ezSmmD~{0?negmRfs4|D@jOXeGS4W?%m%l75j;jZt^Sz6uhUg`~XQ>l4G z$@ak@*Z*VasJGSbV+jCX1gj~J5;(!7946S1?-^a=ln1~F>EHyr6fuuHPCSVTUFCn) zZD2?0ywF1%IfU1}`Iy{Xr}E%kPQ~1;?7^$m=_Fzi)!(CLpA2LqDCF>)L#2gq^wnDDTCIbuONxQSXfb;4(1`UhS-Zx3&@(3Jn2(%p4Y*9mIZphB{ zNvibWRF~Y`YidwS`Cw$^-cINeQPh}qGoU56ssbFRLSHDVT3sF(Vcz)Mv_YNji#5$L zTb;wbH%Z7G2p`Mae;yGX!KJ~*5;W7h3W{LE^tN~|+8NhPzg%PezA8|__g9r;6}7LE z!`Z$3A4AV*9FJ56Oxz;`PJgODcQ$u}_^4M#CgI)OgRlg@Rftm`xIQ7VwW6yr!=^a- zc;4}O`C}W6C1=J_zyLkc0emvPm!4Y`OagOoLh6JyK8-Y6xE}iTzR*`$%FU$|J$v=G zDi2^N++bI-{wMRTpb*D8KZKB1XWy!rSD{9b$C z@&RvW%W+I`P{uN6+0xmKgg~xawz<0Dh-KjC#f9;9YhU?W^nRqvFtg@%j2H}imiADR zd3BQc5}!kbr+oY}k7-PTS5LF>-|R;R7f^8up<#~)R#IjN=VDeUDUY_3v$B1#Q8oN$ z|N0yF1BBJDi=Y}+j9~&EFH|K^4+Q^{cP#-~VZ*(#=CVHF2#$CML; z123bq5}H9d&ONKKa)E#W_epZr4f8p4yo~KrQQ^C{bXE5P8fPM1)=+^swJ@!=k&d@Y*=0b?9x)v>#M-B6Dvy8%keypS|9i9t&&GtMfh*H~TBF ziYrt8ZOqyrxnVPD#~mnf_m_WaqKw%r;cAh`Dww6diW~)hRMHSD`1aIpFgQDLywlz{ zhyk!A1N=J6qH;>gRR=_TGJC%CVaANB00blfB%wRv?#L$q^iHI{}N0=9@Rd^}Lh ziwT!>|Ll>sX)2a^qk$b}%Zk-*xvX+p!&K!!Q$9-w=MQ393d@M^kg`2_e`t0fEa#r} zBKggy!SauklzON4-L;JTzWR)VT5@*AuxilaVqwSY*Om2M+oC&eC#`|ic}q3#>38W1 zdDj%$MezV#JWf+*G?YZ92>$d?`j;@ucdl1P_3j&{kW+CvuPc?KzfPhhq8R1NK7MR& zw%;&0$UeTmFWrq|50ba4KM-w#v##hRS94lmf|(P2n_ntb1L4Phy=pblsM@?=K(#3o ztv7ZAi?ifXOBZ@Cnm94f%K%>^irl02k!n=VnmbfIBCad4T?yjqGL|@T`^8Coo#CUO z?H`9-GZ2>+by|Bb-2fFD`+wv7AmMn^WX1_qFq0zw;iMLhxwNWMHqg;^n|MI1s6Rw z`Q_Ki`@#2L#)alwPDKxG_y%DCrL}YP2vhZ_MDpk6j&eAq8LqURoW1VwZc?%6N-YQ{ zAs1FaMU&Zc@n<1_3pfiZRPI(L1)hMY!a*<4OW5e&Y_U8u&4rt%Rbw9vCcO)<55T|s zf)cv4(^_7yev6O&anODIq;Vfhjy%#nuSox~oW%2D=J?sp^(w+uh9~zapYAk^upN2( z1~bYpL-LX$yplc%2<{g(WMrhP*>EBwxz5-OqVLrR-_WuGJ}fnj8NV?fqZZg#qGH@u z_ZZ>#PyBquVijSGw!vIBUko=u_MTU1eb8&K%j+R>eE)Klbt?9m`o@jtjD56y783n` zpX0LNJDNlO38UG;Yz(4Cz|Q(1`EYZ*VBTtIvpwH#@T%%d`GJM`doP&K;OiRfKKrN@ z*V^yk=SVJ|2jd^2c#B{9R^NPkr6}THXZBBDoCe$e?DAgUHss0gtTiP5)(xC!o)Mx$ zx+tu$r|ur%j`F$pm3<%nZi3IzCoORzu!UDWmI4xyslSyi|FN9Egh09{YSf5ag`=dQ zyk&g3MsAT+((bz)_j`0V1xxVzdfX2zm!8Lt9tU&2+~%AYcAuZV`JK+6xfsL`+OPSk z$nr{I9wzM!Avd|KHa^+}$L3uOm-Dn2*jEUU!P+Yh`KHgM8q}jzZvPWT{b1Li-N4x_ z;$BmVh3Cl&8Hp=6`%~TlJgvrTYFr_~yfJ*dJDk%{23_WOhLV@;P-YCBbXd|NoTLh%O|@BYW|NDz2Ej=D%AUZGVJFf%IZaJZIu za#WLmg04q)NI#6FgLL0bwitBUAjJR~e|vUVh{)n+;8 z^sPWoZ;B56)vG98QLvGB!>%Hzz*Gi=$UF6pyD7NUQ|TGLlD6F94|o;$%ZS2yY@fM2 z%Oi2<_2A$wx%RWI$fM7bG?P+LeHneUMG4j7G{u*fR*Nqy9taij+yr!zo_$ zZa;dnSY>}RXEMks&(;<5n$l(`G;W$v?kz#j-Y4L zC5(1UcBAqd){8{8IcY9Gxi~Vy!m^Dv3jmt@<{wuXuN2-08-04tio<)w!eb7yv`FA{OnZAY;Rk%96MOoPv& znNdl7_^uM32VS{N?c~;2N(O)FJ1#tUH4hBKVfI4hU(D!Z8HCg79l_p85PiBsBEg#N zlRp9_y!TOpnIqf57&99$om)LySxYNJ3GOu8<9crC?*Y16<2=^bYo#Q7o0&w zn45Q<;eM~hCwdm=$$*AGgzkV>y302b{Va8wN!S(tgd9dmBWh!ka2YYrv!Zye|4;^x zXiN_~I2!}HsN@2t1A1KZKAy%|7O^tMo5Cf@BQYGIvJp?kA`=x;NU7#W^e8P`NUr)JcGW4;8dv$${-QEuPT>aSs5nM(^ zJ(t-9<@oa2VIsT5`_3m`;t$kl_4~GDdEbf3NPBrQxsUHY)v7&^FpcX{`|{GzzXY@R zY(*tUIcRS(vHOHFzjWPl9ASm|76w{PFH^| zi0AQ>Cx^=eF9&7Lt&vC3KuD{=HlF!!(q*_&dkVtSHRA`^*9z5PDjDuEdfZ6nWReMo(icDF#-UN8x6t*C@ z-KAY?I~k;T`TLri77JAu{t}=Ze*i@hb^psj@gE0NLtPs_ z%6*>k{mB(w!<%B-U09|^WVh}xR=}$TzU-ldOkhDp{jh{!!bczcW|EH5RvM%9QB@d= zT-3XG0+m{}f}&~HQ9ZK)q9=wc336^NpRRh*h0{C)7C+GAIBwR#KkTc-4Vo&E#IKkOKBYT-K30#rm*HE=MW$<-lna!F@M7oO2Q^Re4}UVNk}eF zNQ>&MTZINfzM?tsO}-jzE_^-?2DBD?(M zh#piHn%g+r15!opb;P3md(};@i5!a7ry=1x|1l`-9YIpUntHWQ{~|37!h{-!E1O+i zyXBqU9ZGu|qPt-VJ`LG9Q?1^xQrn7v;ze0=aLcEv);36=sb8=7zxtq|sT(&BK?FBf z>Sp9xhZ>#ZLCaHzSL>kS9VkXDWrBS`Md33hDhZvO7I=GM6!4TtzFGY)aONSBX>S&3 z8CoA)Ra=m$<^67#fxoQ8(S`SO#bwdMyLN+^th+Av28|ik0`e8X4Z)Gh&@jB*E;ex~ z(Z?dKZ9t=GLB#o$gm~i&rhkOZJF282ESD<)0|g53h}4q1XR_NbPTwaa>#jOByq{2Y z)_;vNcV?SRzpbnha`osy`}d`cRVJcrg@-Igi5NA_c`;>XeYx--YrCnOb`=d@Z8fT1 z??PHf_HyVZPtPdppj)3G27+#ebH5mN(w@1WS%n^H>TB5x7{PXrKD<{;9_YIn!&x~9+=;lq&v=Hki3g$nKG2_M_hOpE!-?xhYXQ zp;l*^aBGg5KJ=z{E^hQGD%a8-$->cQwJIcBr^_rare(E{yz;8sC0syd`qyi`R=9kig9f<;OV^SikTK+6(NzS|YkpF4yo-h2` zFH=bDBIq&k&u)Un!m(rA8g9jXJ}t^w!zCXG?045vjo*pt$$tFwR^xMpw6wV#|s0iuTuj1 zP(zqss`egqTR9^hRJJ_4qES+=!I;Pgtp2hKuc(oQ-8(N z6;fxLk3Q_98ILH7k@YUN-P)=S<7=OBurp%!yxzy>b;S=pN#R}f5D6ThfZ`L2EA0#j zILSC(qjgzGb+P6m#8z%!CgRw}Ff_O=VX{JT2$R!R%qAH2J&?gvf}7h^*}}yk%|I#m zo%XyIjmP3%$`%Z1;Qz*cbNZ$Z;){NK>ABn2``7&TOvLge-}ELAZTo%YHhqYBazp`P z%J?RCW>gjwQwOd2KDq_Sq>JooBxSrCDD`J4E1X=+e=xWxFL5zmzYeM%B+-AXn9&&- zN7WI&>x64<8j_l)yipI>du1;N>aB#(C*rf64$Z{%h0mXB5AjvY$~{$?cX}7-9nITT ze8KA8uP&sb#Vu^XTxmJ={Il`eghIif{czjEQG|Njn~pZBd0~`xPOHz;MY3%8k2bnuhe@6`x;A>FUAg9`mHN{&b`PS*mYDkZ`3uQ(2wSI zbM+Cs{HxPGgq**^>uHL$V?rNtg_S#a{1eZ>_AF7~!rdBbZ+&O+r(|`j^?NuzSSCnw z*eYox+7RT6*GT+_aszhA5$<|RldY`uNYpLCM!_8NBiw>S5gR-BEIt$hfGLj?&c|;H z1%sM0t(vJ{H8vosffAK(#7>FmW@plTZC66oyKj@CnH|>GI|3ZL-$p14-s8+k!OQYSYbU|dE6~LhIdO@ngD2)@u|Jr?x34deV;V5UIO37;Rhlv?m@n`8Q*2)V9 zX9uwUzP6YMyfvA{an@)rXiSd^03%}a4;m}=vA+eSz&#U2snGl-_>NjOs|Vp4qTKke`k?{T3G>8N2S9S zkyOGj%ERuE$%4-dxF-aP#hy1_-jAi!B>jBSmo@TctThBPVjkdvw5`dSOAddOBBwgy zd80=BfLcp{w}JvC{RVUWVi`te6dF@s28$$GSere?L3z=x>b1?G$;hnq3GMp%J?6n$ zN+QSC=WVp_0+ikRHY#lhnYyA;$-(#o>PfWb2_0Q5qODBJy~}?PX&P2O^`?){Lokz2?_fUUs@x6l3sf04bc2e23-urjTED=kXg)9)61l`V${%8`%J<~(f=lFAsZGnk zN2%#H3~3H_;|~L&u#7X;-Xw>(IDR6tml zokYF@zXFxIQjkV14?flXY|@dQ4Gd2^WFu~R`8buGgxuoJ2(`5plEiRi;&%=%UU}n( zIotY60+S1q#DGq)e+K%H?HZhQ90pwUshXZ6BU}8BdASjH4-dj8xS3K|t`EFK$z2WD zeKk`-N29JOUIHYUKUgOg=TE{%Kyg-gn+`RS`Sb+5Ul?ARkGgp-_Q+0(*O-ltu0^kv zYvyK%iy*IO2N#g?Z^s1iS4G`oD(3d;MY&i(+swUI@19}8^1E2r8tnTvK-IQrnXkQ1 zf+2~jBTBOfK0QQ#LP8>uiZku+ z^I{||y}lA^*%CgAx&&9ww|%mr$z?`0%Y7O@>Ms+9cNg(>{KdEiDS!z|&opaap!d~+ zHcxwo&q#Q^Qqb@*Q{C4A7+?JjISbp`bK!r)5}W&L6wWfBHE>3%j?wo`B-pdjdJp0f zYxvH4LXZ1RVa$sz76|6Ux5f*Akhja{W8>4M#h=r+Hw0tmsP9KdS`c12tquv#&X$Fi z0lndEw<6AMLVpu1(@a7-lT>pc_+?t%KTmIx7Q-7cN`TMn966;e#n!&bUlEiK?@eVn zl>Sx@n&qzr3x(D4|Hc4uyTJ*E5)l;u*7LXb{>~4lL;kePxjIS(`QiWJ&Q*mtS!4{m zcfHi6($3iiW8`4&d~x?$Wq*9^V3RI}+QF4djGxvo^N!5`IkdT>iB?up*e>&5+*&7! ze17VB?}Q;hj!Q&?Z;)pBJQ7yFXe1&&EbMKxJ-Dm7R^x5j_nLeIs!x9bf?aKYqq-fN z^6V!uO3#NJ?DE118pQXv$8eo9A@BkfA6$oNOfn~CrM`?L&Wk>s7rYL!*!dv#VJ<7$ z0A-Ld=uaZc*bPt{H&S!w%0JovE`CA?jtI7Xykl`g!Y#FvXimUFl%^@%v%WjPX4JdR zGO0WAFd#FMjOZsvKMk!GTVz}1Me4aK;!Dm(W64H+&_DkUUlltYT zd1R=Kg$%{5KiPzQRko>Yy#tt}yob<->DNzk_9I@l&3b!F7b9oZjz(N6`*wf_-b< zx|dPr;EcHnO@#Y6f)@pyKTlSjd>HO%oi06281B1sp#y30$Tec8wS0@G0(MBzfWQKD zIbVs=+~$af@Y6K+eNQc2^pv6lkjW5~Dkj#e8mAk`yK-%L;isR1=}`>e=mTHU?~wmM zP(^`u^k_@|>DY zsTBQkw~t!!y3r*+IA|+ux3I%eowl$iz;&KhWw|>;Fj>Y@E!O*O3XVT}tN5JE*SfUn z@ciFqxY`|MEvH@9=poQtz5Nudf)Kla{RjGWm^kQ8mifrJYw3J0=OBb$c^8JMXWcptab{6S-u0l#KW0xEf5)-#eX(Ho|U}O5dI7 zx;pszPni#!QxyMt!|A3IhefoyT!bTSJfCK|WchRGm9}t-gCR!cB-XfXZhyeXXX=l( zj!XJ)w2HLqb2lj0Wt!~b&P6X#TxwJR$Nlmv&&Jas5k&Eq16PZ-;?n58Z?Xz8{R*4^ zQXz$X;V|4~ShT0^JJ0y-7~eSEe560EuQU6?Zankq`8L~w-!%p83yd%}G>S*=dZfYk zgr~>T_!zJMA*MT!i8P&n+TDM~5ELXFwthv7*wZBb;Crk6;kDw$I)y+Jak$B6)hKa< zrYh;Xo!`!SPy0Eo)Y#3Nci zc_e>%bC=iTnQX^Zi(0m~8ZANqBfmRvDEDp+w^SI;#j_0XU+rVyUdeDHO{V5wh}3)` zX!llqbXahM_V(u6#hIQVr_$-8|}lY_G#73;tATMGuIDWWxRc zEquAcZ?Du}vRWqd+Rq=0Y2|n%d3((%d5B2~;%g8pz}w-}nZ4NR=!yFBX$co;CA%&` znW*LmB3`6H^1+fkztr@`-8{3ykIX!4nZ?-gdX9XyYa)2tqJq2(g-)7Hy2W>mUh_(Q z-QtHUv~+r!m=P`uB;%E4_Di-WfHKO1YKAsHG*%GmwzAN;C87D!kVBvrb@ z^w}5po$u2bPM&R<9w$?p&QuFtjp`7vOZkY%=%xoVn~0pjVlivz@RfxQ!19C38sP1P zoLGhDz(Ta*4t7rsj2%LRQud|n5hZ1n-h`Qo>t@e7In45r)7k1n^V1^O?vjqAUh7fV zw&H2syOi2Qt=}S1f10^>v!yja$nudDFDj+(-_2Y?d$Hz&QYq{x&SRkA4_D2Np3@lt zSUuO-4y#p#ZDQAne8lNF+*}-YpdltC;YVx(bl&~xU7`1blj*4}!LF{Sc62e@+Nm<( zBr0dx#+|addB$W<7{AgXp7!1*$EE`@M;HBmHzG#nH!&#JWzFsH@_gLE{2Z?4L-SGE z!HyiXKbEsYPap6(IytX)<6c8N;2Eew(aOO^#ie@L1;5?kwIo$}*(oOaA$PccA&^HU zjSu&f7SJnM2jiXJVir9|KxS$0pqw#ZHQ1<|lic|NFr_CHiv0O1AvvCa74;hK8T#ac zT1z-;i5h)iqNe|UIRlp>gh4DmN3<&l?zxAA-(#m%Ie>r3Pr)sAt=fejc7&onRL65$ zuUiSqHMff8KDc|Sx=7=KRc3sX{aSlYJTIPWi}|>K&{<_iOY*i7HlO|>UTl&l^rlt# z3?_``vXC+O76{nN`KTg)MGXMY7w%e5w42T#2EHq*T^E%WDI~%}sU^=7y}Fhv3hL2j zin}>m8tCAiHdVq({3oPvJKXnpRSN-^B<{`0=aw94MT=*b?s$QCb(Dm74216f105aa zf7`$kW^Hf3>ia0+&5`Hf7v}|@-dTvrxup9tVg%~&%Q7zP2i+fuk8EFX^=s;#kBbA5J`6Kh~1n++xor2cNxFZ=RPXWoum1! z23FP7*W$uH%85T~VSD|}H+Gu2IiqvRwr>|akNSWxS(I0uM%Y{?Oj#=-_Tf*C{|Q^m zZn`^xe~r*|+Z#O$iF&xF3M4bgDmV1p9L1>Ij%dQ>^Q+&A=3KPWj@n&qoOYJHQm_17 z0@1NII4@GXD{6_2+uoQ2jU0gHoQfYyj5S*Fvq_$^4jPB9;sK`n0}8UkZ7U@cdWaKpb{Mz}Hi+#i z)Dl4nq~RezB9gzD=w--RpCZ-Y)Df7|b4 z8G-l42tJyV{1EW9SLZ)A`WXY#T_@{#l+FP_19s}2tosA>svfo;bGt@hf>K8gPxF;V$7^AIAIKiAHI4PL%)SquTyxi?U!-(u9B=NXr1o2y z0SRG~A1yKp)!2uaRHc?a_7A}!gv|;{6q7s5*yP!v_TF(^I)<|cl#IpoLOOsPVy*}l z&)(V=KL7qANp6DGw%DCp(@_h0p_FK<(7L7_z1oz)I@dCw1|-iaKA7Z8y}13jizLY| zzI5Ur8S_rp15T67i33uwujr3?BdiXra&App zEF-Ula;-ZaV*s#jt0MClL!YS<1#S$tXnzh$6R-Z3uy?)mIUFC=6q zU#Q+xql$VV8lgLl$EwBG$e(){09lYOx^PL^(YgJNd{0fBsa|NP9Ham^O7D@K%{Pa1 z_&2hZ%>*EK$7`xOOWk~kjX#5*8mozWutofqjy?LwyuXNh4_jXs9 zaW{0coNL>+uPGy7q*|Air5KMbz=q;5>TqXj%|4Oaa<0;n9;CSRm%SO1bj4ykIj&cJ zX3}4mbymN`-jJaY>{c$Y;IMTZpWYg0CFJ`j2*gFZ9o5lSdt;P&KG)t}wPsOITI#WH zjo53hjDe^3HKU~N29*G|Hd*fAGpxQ)=wIW2R~1vrrFF*2M78GA$0SFiX_Q|%IQ^(? zyeHSy;MA^A$q(Cdjep;n8i#3rf+@Xzk8R-`YHtv3u8B}D9`_!}*XI++*){wMQwHK| zk~)1Hni+l21l65XfB3asZD5FV6g-R!mk{pASmCCXGA^+u2)ux;2VwO2_{wlVMk$JC z<7un=p;t`GUh}-Y>!g_wExQa*AZ*z8%7#fVd_^h(}`@}jx0lU6!Vlg^U*Kb8)1 zUhuJD5K-cU;sHVJ*{rUD-vC8cU+h!@pAurO-PC%*j2eUrZA==8D@*D-FLJygXMt!A z)F$U^@Pxwcb5kr)YKex#rJm1t;K-p3=e`;H@=Dc7;aT+#v(6C~g0-)}^>ZWf zjb-g|87V0*1X;G>I}Ik03RhI;mb};!c{tAfWbv>Zit=MWI3hRxV+%@`3c2_1R4(00 zz9B#crS#%Iwz=n1l)5+Ilw_nk5P8n}S8g}=ta3tpY4upMZEVFba>-m3(TJ+~TSOI) zcunWs0X@nys0<+?LAjnUDMzbx&zzS;5%yUx)W6?&IaFl9z}6YHQx1hY&;1Qt>|+Pa z;K_m8Qv*2-<^XLiOcuu&vq87UehfM-PsQ(~1Jkz7xh7N3#-2N$sNtwAF$D^*H2J=G z7}7gFS&;S;p7!-L(E`x!# zGy)F;Hj1_0UfZsEs*|Gg?C29fpUu95>;c>t8x5EER6HFTO-CBBX6L-$H#Yp_yWDl+ zWos9vCR`rv3G9)HN-+en%9ewZG$*%pL;(M+?yCh@YOnue}lydcWEIY%{xg3IO6z^9j0_kYWhGVJ2vAaxpT0 ziG!=X>gY$G0j2QeGOSj|Nm?j`*jB!%E^`+M+39^_FD-X8cV{Wki&UN^pIVoEh+}|5 z>x-8pQl&IjqGIX4{TKD4Pzw^fWdz$iv-7{4p9j!Ym-v zT|>hxZGveJl{G9uHP)orKLHAF-m+bTIuB&3@vno65~jD)d_@`K1r^B=59C&CC-{m- zZM`qIx0!v-{YG=|YYXMTra70%lAWy+vT!-=h!-x*Z4LT=P4*n=@f+5{)V{o9Jl9cFm;%_ zO(?2Pi5y#As;YRW)}AG|;qHokPNHHLf{>upMYE`X4p}krhnfL|2Ar1D;cLx+@;3cG zUn*+4!;O|m*R67$Ei0`?!yhw#P5gRpY$z&8+r0nj>4cm^W3jUh(YYkjo>N;op?Q}x z2O?+;OOP&Kh06=3#jDH(_pR*RY%%HMTr9!tOzxJ$)}ykNuoE6E>HzMi=zXx^gPEc| zFLxDsSswB^u$azTYNAY8%vnO`fKaN)tNkBxmtSlL;)UFNqyOe`GH>o8^BFwrj^~Gw zQr5v-jF87`A8vkhkQj?*mb`zhTGYu^WbYxAqXBHo-(FWdbp@&gyRoHDfaa&wPVCx( znWllzrF|wk&L4c!mbPgDvC$d#|2mF*1kT8L^3Q5w;br}oOZ&BD#)st=Gk@cwbE@Pc zbb!Ig!{J8FJu$<*@$tX8WR6156@h_gf*;+xPiVPh9t;HL>{{dq2YdVy5v2Jqm~m~` zs^)XP^TGvzU!)rfXe^&pcJ+V@h75`YIe}H}fMz9Ld9S;B-%V@c^N!P`^Bdx1ja8CV z|AQ(xJdL=*lpc=bzAZ7^b)ghny&+;FRlePg-aj;Jk3-gYm{cWMHX1mAlUE4n-UF>; z+2dAy#PhWd{c}K)wA2#TL`Sd~3V8L~q#{s3FxT~|z<~gNFaOd5-G|K=m&Qev?Qd4f5NeE1#U_Q?kl?~YpNKOtc7$+XBh>qf$5Y4(q z+mfR%{AHfsDr$qxn&f_}J<3K1``*ae5?1rWt`OZ*$m_p{jxqfoF0gX{L1RSgV?;7BfGy1j>? z{6~$ar0V5A`%kqyAJNW03Wv@ro1#Z1bq6egoD|_2Wr@-Vvwixb&ISlH`c%p>^tuTVV6P4cfZ5EPN#$5Gd&f;&F~EO zA-%gIXE8%k=CPn2xwYl1zL#_5UVc>UQ#trG(mN@*;=yP$wK)o1OAn9z)Wgw1>@KZ3 z_o+5qA#zQlK>7BB8pxUz=pNtac492Y+@`PtjGDWE{>8@OnXsfO2nMz~XTfFWmgM;Q{_Aa=9@PlXrg zKbc$&nPkkwlhlLmc3HHHM%=BeX{Z_~L%HTemAcPbMQ!o8JD{68&%f_k;=7%ly~J$_ zpUPP{_|=bDXgWP@X|mQ`^9XkLw8gp1?3#@sa&_!+T*}-maqj!FMI^BiHq(#qhysJr zA;`iyR;9Zc3v3KH!J$?|9#gm8%?lQ-#x1q|6I3Ek%V2Mn7ixXJ*YcOmm+XLli@XS2 zUD}PlfBrc%`Wf;LV)+jB!2J9mb_%-m(?^)#30L3$t1AYF#u7-{%~SK%xNyJ+&9^>? zY(tt^{f+W?^V&>JCEp>GOFQL=H z@rS9v&!^FlvmAE=cXQhRVgs9b_D#IHbCfHQyYJm8fn6(wCouz=uHi|0n)9Mjuka@a z@~y2sefs>}p=;LHdHR&S&j!AzwZCW=e^}uVm@yy5af9MxrjZb&XzxUI-4_43xoJy% znq?f&P7ZhhdgfNYbtC>ELdSwW3OD-S zkTH=@T^Xp+@m7*I&(_a}9F)pFoYszK2bRW;HE_3ZYmITYWOG0k{{ivXr#_a9AzX-u zeBry|5w9fllb;YQse$<+?onU+RD5P1Fy-JQCecBOLjz(rauwgyrPVoxcd0K$hv)1x zzcTqG0t&<)P5m*@T5Q|^JobNo=y+^%W%hwGL)kJS#p4v!m;x2Pn&Q|6NQlKF)h~=x zOUDxNAvob9U%;wM<7#JZm{~l0#aCpt#n9>&4pK~UMj0wyyd9q$fE$XPff;xNJ^#GjwhTJt^O8-Cjbb3ZM3@cPP^=Al19h@CV|)HU(X& zJ}j|ytPzKb60l_VGey9uAlX077utRR5$meJ_j;x^$F+cV{2C( z3}Sr`!`x@k5%7#YZ+S@!_{lk0S0HEHYP1Y?J#o>KRBrAs?Q&UeNHKUbI$$Mw&c8RUibk45Gk#$9-|394J0M>reKV~#8ucs-V zrC=c@kMSWY$dQ`c((MXj{;DPQmIr`7o}9^G$_hcisRW66N~Z2o!Jl#NT8ek{_>;i z221Mf*}8=C-jM3?EX?S{T9!;o=BO2i zro!rzF`9k;&Wo(sa|vgj@NS~Iyyls3I}BvQ&pE!T)_2gU-i7vAQgECdHtKn$xz9Y; zu1bWNl>)rN^s8>9$|u`y?WIaWY{%Bv0t%+-{tn8Xz7=Y`mWCp#-adD@*wf>9e47oC zmI-|lD|9QM@pBwk`?oTK92#z00HwN?c1f~jE@_8vMry}Du-NDfL9G+}ssJ>r!)P}% z@eH-V-W^^)Am)Rv2`c4Top0SnOoP*XzXnwG~Edq$iGN zB@nv~Vvdy7Jw$itIQ*B%NM|p6ZhlD^YAAPHN1|O9MPc%d96+tOGf% zHF}Qoufe;qW%#fX>RQs1bWe#I>*=({4*In34b?^8*0tARoXIM&_-WL5gQ1cf)%B=P zNnwd?FEa>`?tLnCO&st@T7h;-KofJql@0=(9v8ID z2ic*`59wg(Gij)??Gs6Hq|h-xN0d7OlbL#1`FGJ)ZNi<`iM(3x233qrvLOYHaoow{ zcQSs^LB=tkPoQ`JPDRr_-t82(m+i11Mri|ApU5}NwIw`5#gv@yp5%}18k~8tKFIch zIS#5h^Ov~xwG_SzPJZHDM?b9z;|^jx(8%GqqF|O3h9RBZZlc`dh}+qdy)`82iJahvD z`$4n*loQ=rV|&}R_3ja=2r2NY3+JK^Xr7s0HBx-4O^x?XC!*(pnCdUkW$6o0HtO$C zP$?g?p_>Y`rg{@9Pc5AGjoisG^(q^RuYM?=BRQQFNH49a#4BhxD%I!P=u8VqSSH(K zO5rX`_WSvTuASh%?kruv5Y0NTDXpreIx47VLlsKs+zLAQvFMtR{erw)5LjJWS4Y>E zo(15A1Pl-9M^czlsW=fEsi_BQ82w8Zi}Schw@?nADW5e~OS$W@ooKox02w+raaRMt z0*s;;u+lI_n@LILK9|OzQ6WV6v!S>fK3wVK{(o%a$vrcET>d~+M72^+Qzd4VluAXq zvBXjx3ulWQ^hI#KaAjzvb`&I;5;fS;n<g2E4))3o~vUenYwSkg(( zRs10xK5oqd0X{;A%o7PaBZ(UmB$#M79V9+Ow5zsmrZ2kg8HWN}pO4vZ*&;!JFCeU)_U%_`T)-ogvbnI3Ur2lx}L6C0trz|OoXpL)o3 zapR}qvgS@r;*3U{*iTL0H&dwCu%n3#cz6KZw<`3HEV@!mfI5{0xDyl`xEWO1!^+- z56MFAw?3wvV4?GbuCy{^ZI3>)MCTCqX!-xKo#k!=*Tj~-ch5>(kx1iQV@LhI8rU_` zoG&6+)mUdUGCMo#N<5)h-UVOsUVEEd_ye6^s`4{#K%(wJkF@QF<(ak5ZudCV3!kYp z3b~xZIGOhli!#@+MZTjaeSbV6+QC){L@R%h`Ms7Rt%M6i{HuPtn`N(>5U0MV5k5eP zK*U-)eHvtX(B7(}<0oZZsUV4rPtA-V2N_xSWC!k{^FYxL$nJ>nRz z?}vejt`V1#T^!I@xPqPUpk{+}bwPc~gl-BcsEVuUE9sNafshLjF230^s^1hykG5N- zH$_?pemiGd)A$KCAV3bhnc4@9&7AkZO5Ij~6gefQ1wUXIsr4#`2)QWJ%N-Y0;<(+P z`(cKOD~DQ(MTXRJF|!PJ-W6zLwn6K+^Hm0uDYRswv)uS>LzJZYQl`1k4YM>}f0Gmf zpW<>R+x<0e+uj9RmCFVV%ix5xK*gj^4#&j##}Lspii`{>Cvu)M?ds(Z)9L)Gx#dS) zLA&9zntL%LHmlnAoszr?&-M517jJ|({z%b`tcriB_mX;ww8}nnH~UOCH@JrwqCAW! zRyqy%s#}D{2n04q1l0Xz`i=d5x7+p0il@6u%5$`|taSBZRLr~2wa^A*5B7XSE-)*N zN?+`1ZN6>;Ex=j_cos&>mZRSuFBkx9Gj0ffy+RFLZ62z{y?Yv)m$CZNZ;DtI^g>b7 z@@9M_^i|r3@yiKiy{QI}YDt`rYTRi^@L(dRM1WY3Z?pKm?0A}s_0&&~emBuK*`!$H zD^@qE8X3>H%LLP6{V~=X0|90BAI)FXFdiEGu%f6Yckz3xa-9kRq6-oT=wBBGo2=eL z(bM(2VFFzhG)Uok&;ar}pk`g_f6;RW7u>fue(&T(UKagFtm9*M<3j&=@TXacaXg$W zW>(nYeEYv@9sc2+CC~9RelkV!so<&P*A^{Ts#U_)Vs+=USf}<}QJ#&v2aTilw@ETq zmx(jB2}2U5s%u4^(tjFuI9rk=XiyvSoR{Wxe1ya5YE`0hEG5R<_xx7mM(7&#|Q|}n8R!lHNxb$!8 z0w!{_t(g})icZU|!F}reh?qpIn(Jni10vXf_n}3IgZM;hJ=~;Z^lf$)oYfc7Y>ZnJ0)7-w2AH#gY&a z-ZB(`zpvR(y=5r} zmb`=Xsl|b%cepZE=r(>nI*rdi&x9yS8Sj&UhL`xgyT~GZuqcXu?P7E^MpkPus|L`a z!QZ40=nNM0tv={*_%>DuzQf7RN%Ef*0&&=}&Qcc4*k4i{jkrOqa`iK!kUmzQ6CA)l8PpWTyXn9=FdS##W zyGl6$J5ERp$?yxh{Eby}HSBt#-i2N?W&25?Y|AwfrA@snCyNbxc3g6~;{twsAF5k8 zQVDP{8n9KVC21kO>hq$BzlYz935m8fF^rGiAoz>);Q=?__8gWqmU18bLcS0>)-!+N zH*d`3Tbh>v8DRoZAl7YjzjkA^s6TyPwBb*mBxUm_tPHt)!2XSQR?}zXW{Tuyb0Gd> zyCU7I6ZJ>vSmxrcdC|`*-v&EP5j6nYImz0+pe6`Y7PQ*`ir5VC7c^k^k0NHzaK8MH zE%MZ^mTxhu4+ll>)2obcV8LVR*WS>q8p4Snj8{v8$mZ_7**-_1zG-G z;@)Ep1n3&X^LuFfUS>=$+NN$@*`4?!CLd)f8DW$5eM~OUz?6+{L+QNhqjM0#PR?Q6 zqFF6q0O?RM*fU)_t7-L5n`xE3c=U;Poi?dD&BTUD0`Cd0Z3f`95kPABE7la8Lmu$C zag>R8kceno5c~Kn)qaPA>A)on@z%=Q5KHCmu*o+v&9WWwq+=1M7{{0wlNKdo4=|Vd z@~0rN3txG+uxGyW7&pIO*y}wQG#jbcB}mT8cbeEbSpE9fnOJE}_?|pAtJed$oc*DM z^nfztG12S~;NEdHn8;?O`V6CSIrMUEiW%*oKH>6$9ivV4slgxrBf=lJF0g2qye2Rl z;G@TZJr~2Jqr$$LOy|O4ss{69xf7t-Ns-*d7xF^1jssH_-RV}gweDc{M z?$?pAMQugZ7#X1rStSz8B6+Qh7C!sOa38B%r}{hci+*trUN+e}LWTT3L*C}F9ytgj zi!A-FY;LSb_^L$bb)qOT2LmbAZ<2wF?W8 zmo-Z4Y$`doq4rI(;ijy_A*iBRxD9B8`)E=B)$w&4p zTxrV=ja-t9rdK0}W^Y7Jrx<^t>zKr?2iypG6UOPMzG=Ub^NYi*y`Fj)m+b57usn+v$!dWGyirD;uS}!`;6(86g*(h@Mg>I z{6f~LB@)i%frM#@mSLjq-2=0?x|Lk7RX*9E?b;lLq@qF7)l)bFzQ5Os`A#rHN52y# zZwA5E#`r(q%dUhoH2POV7^JGuE@h_8y zCuksLh*U6pn~DEEVj#bzY-+v7{*W0q_J8XcD$T_=XjSwi&5@L`<2|}ardidN9F2(v z=ziMX?vP9ajD_Tx=bA&DrGm5v$z@)Fhn0-qVXgRc%5zcaGJygJp2LZs3mZ}fNZF?VnyJ+8Y}1nbbiD1T zmP+0XBs602!|cSZ_UeS4933vY#Zm9`2|o zapQl#RG?cPzbI=6vXD!?;Ar0``WwyEl~?gC8rRXU=&{Iz_Xl^8*LJDDbaViroJsy4 z9>opZG$Lj1;2qeb?IS_Z zFVNSi`8VQ}2%Rqn1{Yq%0}Bm$Y2t~qk^w-zuS$T^o?=W0PnU|(IY)}F4&F6q+N{e_ z3J`iTO=wZ|?T%xLAHDi0<@@J(uR#SLyf`I}AO&LzbfK7cEGb$tLwciLEfPKXeBAa< zA7qt}upWBx?(vZB3qFC9wYKX&%Vw=3EVYTvVB3-X$sn^NMvVpfwoag@fVp|4PQcM? z*3}JB4&=E%=~f@S1-hQs)PREd-^plfX8JZvjx-r}1b#A^whR z;|g8h-zHM49+ui)h$ONGN2<_{Ah2?jUZ#`a^%1AQNP0b#Xp(gPyb_|Xffl}gG`0;? z+oVS^L29ht@sCx`Qpqzq8@qk=@oABQD-L6@8FWq>o{-OIuu1h`Y2SOlZ&bxqkDo1S z94KqWM`!ojeC0}RvKz^ux;&%eBVS)jTpzE*-yj2yn|YLG>$GOeLS|_rSN&YrQF^rc ze{3OCY{}3uF;rDu@xXP^)85jCl^@{y9s;?%h33aB>Jselfr6 zD-qS_oKUqYr?ZLT=13+c{l|tFvJl(v>d##T70v24)HT~?_?3?n`q50Vk&CEi5>t6w zeCt642Gv*!=x)3xMfXM*U31PN`8Vn}faJu&=>cDX%&nP(1~%W{oYFN3)=-Bzl@NKd zr;Eh*T`T*K*|#i=HHPz(u|K|l+&6nR^1-He(8+W|u4^^51y8$WMRs5qkbR+diH&{gdJ`rN^FU- zA79MU&Wj6^8B8@=aR9>$Icqx^i;&NEM77Bm+M_GS*$~Pk8u?CF;w4~ zjGn`>Gp`DE0zxCTVBK~RK89>oT%GTs-N&6JJ^MASSDgxD3Dk^{<|{|B0Db3MI@ebI zUQ!nU+mN@Bo;z!AFV1sl{(hg@)6gIO%jeARS=NtA{L39;LEqubQGu4E|M!>Fbkm%C zl3wrR`8v4ZYp{mq^Vs?0#|9VdF(*VlAuqivQX|*a*~v}7jS3n;xe2pB9R8berV+Hq z`>RJ_o#0h$J*9BVEzm-DrSO=(WRQ6@1r>qcwHy=;Hd}O0{)PZ@22&R@!mZAsJ%nPF z!%zdDb z8Sq?RAW632u!dKqkE%FHW!$+Ne(Z(k6yniOe5#XHe7WG}I{trW&wn@oQbbm{vNhjx zqK~#>Rx_XiFn2hRQ;4yLZ?*dbm`$g)2El!OeN{TMt~6HmH06nVpoX@)56e3ygCtkI zc30daxrYvKPnTBoHrxJ`rl{!lDe9H7hKOcW@j<#lEA%vcWFrNDfoi(i@ew*VOq3k< z++&@JxMwHGzRd=c-^As7Ghb=fts6dWN|@H?vM8(be2iO;V;SqFRB4&R#nWY4xp5`i z7~S|o8qH8LZG|>ySo?A^EW`p)qTSP?L;I~cs%67~AQYn7p}xRiCo-l-^%B1X*I1Zk z_4;pyfSGK^t?ALAzaH_yBfK?}a$=-aL;NaBq)EXVkYv^PncDyj(i@>yz&Kz6{;63v zSj~D;P7a`tUmLY?PhCmvCuB$KcsrNs??GCVLZY+9N8AIPGmv8+rbXU-V0Ll;9b267 zj?Y0SEy>MQrm~I?_Ws94la;9O4c~j#zWbHgpj}qs_71zu=kxxrqtza16D(T&XQ(u4 zmYJ)h8n}iNHTw7e@ashrwXU42jcS}pMUP8rN-A}ySwWUT+Fg8%TybP_&b<5-aRJlD z^*U7kla7oIE(A?$3n##0-NFx5_OHIkDtQ#4$Con0tEn#;{cr1(+qts_v>8(ouhRG9 zY5RGjXZfvraI`>17?)Wn<`5%c(l9QDN=7;~QC^$rE`c90-H$#xgFj|p!O>6fGjVL}B%VA13|%Bbs;|wW-vqbC!LqnV;5Y zF%+Q8(C*C9yf@c)VXJhAnJaWqR$%=-P3%pO)|4eFBG&NFX;fB#zvPaXh!wB9h(~JQ z09JJnczd>-x^jEpR^60@4@e>w^0*XA5$_d{pYwBv%crOhS6k2{EN|u-Z zC0X}fG0}Mr71H$jvl~gzb0DUro|{u!dK159)F1d=whkvnUV_{E#`*7ntv2T>*xNCY zNOkNkPu(Kw(!kP3Sr-bNOi=$@ll^F>=*p2t3SR0;X3p2OpY%^%BIg@uc6$J7(f041 z^vsk!Uw-y2g7W8gOig-c*hrzRV&H>hUSYFwFiqTHzkQcyae~({tNc?*%WpL2Jx$f0 z{PPD)O{=NYOC?+M!15ttcdpfGqZbfxC71*vc5p!~ZDw5&Vo=st zG!?a5F8K0qvCIMSJVs%uu1YUxpZ8UFTv?c3=#i(&`O>iP${v4+kT+hY`Nb=E?roL! zx?vev_=>n5PX*(=THDS1p5s``z02RX9J8oB1z7M z{B2TITF?}qZyp7PTK}wuS#mTNz;JQ$;Rsq@`C#vKQ;{8dyrcbzoaKyb{4Kt{wA1Qc z)Jl`^S+T3ddIK<|Q$%YozA@b}NXHctPof(&J5JDt{m?t@0UE_r9;=$fiJOU!pRHDY z3EuZZI_)nniS{;W9%5;_F1v%~!z$8tVX?YqdpFBa9#x3?b;eVrZ|w4!$r{>fcQ6VS zX;f%znz`Rxu-wewZdl#~Ews1n>TraYV!p12_8=Od)${N)b2Vr5!~cftReZVIW`FE; z`)bdL9HW17?v(Ej?7WUvK`)5<%=1l%VaAy@6|NH`!!_g{#wJ-3F8iJBM$G3272>|@ zU}M?Fz|WOWwzf(sN^<1d<;2HG&n#3^_Yvw^K4|{i$Thdi1|=CdRc<6at;z4Mh0L&$ zKQ0L0*FzQF7|%y{jAeXT;5J6!Rp&6ipl>hHHsb;}AJg#@C%vB?CMu1EKCMByFX!RZ8MH5{JS34Ag1pg(fBik3c zgUqyiF;m-Gd1=cs21vsfYM0`bR_vE_A_RPvtv39}zSM1no6qAfdS)vRZ5?n(ux25G z9nqG_U-gFRANbgpUq46|4-nq$D?>pCqX^WFb*=Lr;Q^`@oOu%*SF!)G)p?rtx<1J( zwg|mwf|z4mU=2@-a-in3o7MNOrV^cY8+j*r8kQB+GKbHMUOTv+XVKh821_D%hYoh8 zSxXCZ9p~%h_yd}34d-ow1|)9yrh$X_5ZKvpdZB)vn;fyFlp^qs2zw}IFV|wC z(QFsF-`7IuI)vfSA-7K#`{a5%^*-5=YiTtl_4+iz);o}|Xt^z{JAg+ieclc%8k~T* zkM`oV+*xZd^!eN}Lce#}sDj=7`GpsX6VLxh?rC!0jU$MbOkh0^LFsyKwQ0uCtS9na zC$7CZIGzbztF6~}2jBFiC?m7;{G(I&wa9IJlRZx!AK#uKURe=R8!3#u2s-OJLo;d2 zRr51dZz(qv&q}~KC3I3baQ*=GAI@1~=6HAUM}0j*^G>W<+C?&s#z6l>dwo%LeP^6`ue#d!KIMLVCqMf$XWX>}9v= zFx%qlAN>(4+g^$5sg=Ua%?B*holqV<_2Xx3u=k6HVlw^h+qk~kxX`%H4A=-s^6Rs$ z^=brKGOI3rvobGoVs;R%cKQ-hkNyq-ghjtl;>OKy_|{ImM3b4D1+#rMf&&gSNlCqji?#S@QIST4 zU6x)&bKSmst@SjI%#-1&+7rv&(1xJPVOCBq?*GPSEnti%u@!+Ug8sYe>)^`>*P1$7 z&R&(Jad9~}bYdY9TooC4pLhG2(-YRFSR#tB>4>#?7k2|ur4_Rztfee(yy!8F;$lMc znFhPs%~iQGArt;erkI+Az!=>x`48VDi>ry@jWV9QCb*{uSzAs_uY|bKRXg}**R&O4 zNsvxmK=dGD#`O;V*Qz#p$#it*B+mx!Yyek+&_kW4@UM?X8a(C-q|YBFf<+JyCTpZ2 zx6x#T(z3qSkhSA^Xi1ln&ZJhc!}J;-i5Lww2gV?Wyp`LRy8NBO>usCN0%<{e(nhp5 zt2XPYqTcCzKRouo*z2LC++M%ZzIs6@da~XVCK2dRTq{hxL#$|_n|aaktg~yrP?3zq zv$&8{waZjv267}Q6m`jyu2G&P5Y77jA$N*Cx^*h-OFhr zq^;RXb&Ch*(wP%8ouajxff~x`6?tyHDR?CWUM36+v*fCl1Vp-nwqDaso!?4CB%VJ_ zq}xPPBAtEo&UPqS$3aA821Nb@otne-KOXEiUD3&|$>&T@D7Ck%o;-g8mU7cc+)FgR zUeEsx{b{bxmvreF0>2pcT=b6btw)sqadhtSOuz3R*QW!8bP{q{p_F6JXDX$T7Udi& z=fk#~Ph&-qoI=QP$@v^(a~KObpUPolGv`BLY=p5xzxVg|{~nLMANS+Fulu^L`*l5E zPNb%sx@sZqg@ikJ6R+r}({gEXP{W-J&-kP3dH*=}Cu~u;i~EVx>T%3qSuM8VaW2=B z?ubt;^KCB5uO-Ca*b54Wx!Je0W2a9j8C5LTW~aKs($x;Qo6bBi=z>wiuTr=VavwiVptiK_lq826R_e z0(G5y$JXd-#-=Z&S$6>0tmnd(9p8)avcsh{6*w@p&_AaZtNjiqDuh+-qOW3c$Q2vA zzWEbI?TebKGQ9)=?f{>r{PZi(avFu``>f51UfaXkd1{ng@&|=3kaX}Zrnjw7a`KF> zw2aMLy7L#C_&=~Tv{2mG5o$b^wl;&@9JO~e*(*trw2YoN*@Vpo92jyscH}2+b3v1x z5NXzWKVG(=Y5QP+ax^}co$nRe4*J|5UrNdjjd^x?QPMBxZ#jOOk6h@(8W%>RDN{>J zmyqBrO$E_wF7YS`WPJ(cv?3)D_25@)N1a4Stg>i=ylCAj$CBSityA(3KjPE%DaT|< zS@(Ea{Dk4F9AX85T2Fs=UYQxV?Z|`rR{XHH%(y8 z5smUXc%5|5c1W&SUBYDtyUR4fXx8+{Y}Q%({mR-cP=qe&oBFv2OE14pWHaulx>w7s z1iY7#Hfr)^E=B!Z$g1OBLMWzRO^$G!^H3MbyAL<7_pu|fDK0LqvZQe>jLSicu4nUW zik?bSV~9Mu4ju7?frbtsOFT0R9Z|hS>ay}@Z3-Cu1v+U!k2g~^C&df! zJxwQ)SC5=;?evt0(&GKcaU;n`UvZA{WaS$Vx;AA&J>Ag7)jqj;UL3uc&Z!e0SRK|4 zl-Byx<_C*-7#_dPJP|3^HWIqbs^zg*)jUgdnn^Tx*7K+$&8-vDicgoAX}PK5$h1dXqF`_+HHpOCeaC-GL?DtM^T!p3j-FRd)Vn8v!RXlHDFJU8OgQ*V_YWm(M;$I`O$NZo+_N-G``v4^w zw{H;zY5zXo@|2JPhDB5c4q~s9Ke=!N^q#ERfLC&qi9$yuHOPm-wwEs9f!oKQrU=0a z036ZsaY6$|I;u|)>SO-F=^85f&r=j+y4@x-Ebq|+c7Uz6Vu(uOK+_X_N;Md$sb8Cu6rOAk!7oJCBm@5KBJIVo4ZZCMhmY?+K-g!@!4u z#+bG2$F^chUCevFxa?h+NXEvv+cY{gL>wL-No=f8wtHJ^BZO|Qb#XAu_;yt1sp+e4 z6seViy-oN1@LxI3fg_=1M|k)0A%&Hx&y3K5W|>ohC0yA_Gm9A8?J1o1$XkM%%pOeS zkDgQMbhM^fhVE@`#U2Ba>J-y8#mn(+#N{mhojl=_=*o&!@q~BTGUL@hr}k>z0%fuL&Cc>S=64^X!#ny}6(4 z%YSCiq|F*nR4QzYt%N{UjPPQU{X4tWR*zY=ZTxi0#r`ImZpA}XJr7m6S?2np^qkMf z=_GvH9lB!)a!P@H>K6OV=nPFqx!kV)&kGsjKit5HydRl$Q-WEyKz8{gKQySer9s`+p)12vE90dX!h}#o%rR>X^q-k#mIsM{z}P z^~I#r6>=L68WQi7ACy+CMC=ScOHPf9@DBG%FLV-c&%R?? zQP{X8-aIQU}r1 zSUj^D)umZ!dCwQAB9ky&(PY)M6qlB#k1n=vl$ZdrDc`~SHY1ZiS?vt{X z{!BNyB`B<>;U)YLmY2H6x?`ezV2-EF!pr$H(VlIv{3JIQ@lbtt=~khwViyreSgCF zm}pOmGHWxoAdIyc~IhqcPNfme7`2sFR(xIy%q@sd+fM842<^Cun~Nj)y6!>A8y!-~-V zIx0mSebWy<>5*3>i$e7NqA_vW-U%+mDyCdhu%IC4Olv`pBTvM6o5?lg)Yby8zGZ?9 zWTM#Ldi6Hu#x_M$J62TY2a&v(ViJ;Wc@{mQ?jHC&C#4dblRB~t=6j!Djjk4q*D0;f zESN_gT&kbU&F~NU$ZWy3o!Pv4dr@;esiSR++Wg*M*eZ2Pi+5HYKai8!Q@hf3j#}x9 zi>b2xjp|?6U9y<9W(Rt?+U#1_%>&Bz|QnZ>2thOrWaeX(k zcl1HQdo5s4{o+eRjNk!!vnwq1k2LA6`MpyW(D1tB%OeFrH9#^D`PL4LKt+_IIvXwp z+t^tA`X(%N%x5eRuoC-Q8e1XM&5PPTZ~2a7jZLD@`{ESH-o8aX!#?YGhJ2 zYycq2wC>n%wd3A|mh_CA^@JRsXp1ZH@N~nCS6?WqzpVE&yW29(F_uvou&l9CQ$c<0&x ztB28#>m)^n9sX=7bd=W5@Xf894MFc76{X=@73K*WMPjpoA zm0=5NnHBrlwX5Sng^32Q9>|st?OU|DdIQ3$Dmr6NqmjDR*|K#$IH)U7O!?dB z>b9yNg|ZxN5>9>~Qp!OY_StWlaD0nE@gfu8|IOT>1;vR|q1pcIdy!R0q9j&kJ3~UI zAs8AWS@Y0RkEkYRmbMXMolPSkFa<#?lf(MMYL;LF--Py5|&)Zr?X{o%38`V z7Ih$-T07k`F|2%GFu~Mo&mTKla~0cwSK;*>2fLIJtGgNO?n!M*(Bq+%YI1ukAyFI8%E4nSx5RZ&GOM2_ zAI68eMJ0bY2(igq@)$RsF5r>jf&gUC71F-(CS}~m0mD%F1I1*;FOxQg^UtqN`tbPMYujI<9}$O zDI4MXk}=^KQhAPGBBI|jl6VQRu}W?G$I;cCn>)d(iYD*vZNy2wNz|CWwWwK>3TSmB z7lKWz%uSNG=;az_Z9yi%OBSMiS32Uua*(5~fT19<2h2(cuvthb43YZ4`E>mf(Dy{{ za5Gy7$?SeDg?9lXQ`|;ua$<*xkV<;kyF3;9_BY3p6CZ`_*0>#wDba$DTIs+ouN8Xw z7LZhC>DO0Zw_T1HI?PC5YL=@0V;2)Nken$*;O`NRka-*%4K|je*>U02M)83 zxG!0oW;fG=*RLC)Q07KR+?@)Dc|?QVG)ZrOWcO}Lwc`0XUBR$KoH2#1&K@O7eb+xS z?L}Z)j0gG%*!eeq(3BTMaLjyn8xQF5UchM~=8$@vEsX%h%VUv`he&p3pQCXr5!=th zlWW80T!OFYJ?8**B^j^d<_aCZ4dw~cWlDqbvt16?CSd30p#Z84s?%$&7Ucc-1efS> zAACoLD&*&Sfy1NRsr{PovqYJPtgm{aQ}nn;=nQb;{81J2`7E8keIkAi>I_pvyM>M- zLz(`EsrZkBi;Y@PIHS-z;9N@UY5cF|O;haZ@mHt4xY;M|j{lggn~A&di;}ugUbhLU z>^ypmWjMBOedxH6I**%5S|GfKdo6&@PZio>kI3dAV9a_ebSQ4rH_XEXxQU*a& zJrJT|Iy`7H>{Av}@k}wK$0(#IZMFH^Ku3?TQy=KMtok|a{iU75+5BFpir^BgwSzSa zGaeAWqq3CqC|=jdSdUtP+{dUNbe(!%+0|x0v;|%r)K>?hyQ%A0;OV;ow^hEdqAt85 z8{gw3Kf495hn~Ol0D@E>Y9Yo838w>cm<;FynWHsdfQ)E3CSZ&7YJ==mLbke(2F#3o}f;XN$Vy+X_ub;F#L!N7Ih z6Qhb9tb`fg~Rl^}n z@{Ww9YZ5@4t*=ubXxy;H*70G%1GoCx%5ieS7zOP#M9V`Pb$`;%lfsXfe!F*UimU56 zi2ZjaZp$KYcY2mwhF88ep>4%J{xC(iqGzz;7Ow^L9WI7_SO`l)wJeiNR65*<6$E8Iey1-f+Yde)7%MzTVgj9=BSSA*Fwo+PqZm-GydDjR z^zrH7%+eznAaz3qE)*NI_Y>uXjMUnQYt~0iK3s3Ws4F%y4~77rEVU)TSsApL@fymO zfa~K%Dc7u>TcaNcWd>2EZ=SvZs5D<(4Q|}kzo9>ug!`ucM&DzX_Li+PW@Xp>t##1U zC!xFzI;xhGacrB5y>rB|U`Cvk3zwm~%~h>L&4=@u{`xz0**(*nvWT&KcE<19f8Zv` z{c11v$uS1c5QCo%`*DZy%--)Y?LsYj8TG(&M&;@^uGMt8yw^;uYirWN{@YEg#~i6j zj|jV3eWqqLFKr#)^Qg$~ug0GjpRNQo9RRGzV?HdTj{3q#;_L;eeC5Kp+~PsY}5W+R{NNcfp1`yavFl>N(Ho%b>w)Y;;s(mm-6CpJ* ztFg=y^8vLfb&-TZG2x`oerqzu!2mqR??Klb1)K&_4t_MeI1gf8sOW4i>e}vPRk(fTD+e1h6_yh*Ns`5QSG!vvcLzCGH_o82c)>r3z9 zNEPgpBc*T%MBSV^Q`s!_zCPH=&StJ5oWK(oukw1yc~e)fbtnX}0TgS;f`FY6&(?5f zE6`^bmI?Jpp8k|ckF$o9m4|PYGF%S=m*nS~$e1dKtjo27_{Esg`ri@nB1W1Ywu#aO z=5^IpR56XHQQ5iltL$?h#TTjF`g5w|>W3qXBtWA!gV(-0b*Wq$jw63{*q!g&QI}t> zHMQ~mq~j8ziiv?1pdlIZ?*JMLUu%RUdkTP{bl+or#To>-&6C5PjlwoFtCky{_z1(6 z__9A5K0Vq)ey-6Ku`qi_z6!`-lQTB)62VfBAcK4TTl*x|<^-DW!f$Y{BnwF0WwwQ#EnSM1zTmAN$+X=P<{iYl zjaA?7S$4!-)aR`a*N+(BN_K_}Z6}tb+RVsOc{9?-db}$d0u=_B^p#fWkRJzC{YkYM zu_Np^3kYCeP@|Z4V@jgo_a%zA4ua$>qIMwdn!l$ix1_pFLFsLxGy}3a72!7Uhak8} zts&q9nc8Dj@OyrIQSVNEX;@4G%8*-rf7KNq;}u&iTB zP)%NaO7p!5Rp14sy3ND78+R4B=y4`EyaW!@*gU)`I;-`YD4tLD#d)@lQz=TG$< zGXigxYoo*aLq}VaI{lcl41=2$@yli_Ve+}$hZu^_yc(T0pTOCnE*2CSA%YDotG-*5 zZJl{0*4c87YdbKWM{PQht2(M3fzr#t)o(Lzx6+EU{pMR3Ba~}tTLmd=3tJ(u%aTr; zDNohmQ2w3V)pigEQ<$b6GZ)o^q-Iz@o908eAG<~xi1&?n+O6BCy2TczBd9gsBV?QD z$qGM2)n?m6Ll4lQrz&Ipe6(Iy2wYY)C-3wv7Mt>4H(E=QAj;SyuSZOSb$cjji?K^4 zz>Myax6O--1Ir&zZ5%DVyrgcfeQM`{(?w;u&TH%b&wB@3FlQ&vAL28*!0%I-cJ#gl zg>y5~4Z~HzqvF+e14;DrQbHXR(7npir=I5Gk4QmqoHmrG{PW0Y>jxj7NK-L?q)PVv zZxO?X=?S##1(!(XeVWw!4V|k+Z4|UGcXWK>U7x#*1I7l!8ej?(?ClYUs`@#f5UW~H@B*4h|>e*b3KffO}E5t2y-riAKP)ll*fhW}`0C}?!9ssUW&Ruo<}qMm5o4opPdxjwyB6&2#who|$c#Xn z$6P$*%@dDf=YS<+^dIpAN}^PHE2t+aDNmASk0nq_X359CnG8ze+`wt)Jy%7Jvm2gX zCe__G_ax=jP(cfpwLrDWabOv=&wWY0D^j++`lLp`->eic5?xDgtqGAYUZ71OV(~^A z&;ltWzO5XH_Qp)PU+~)uomnHFl0P*8dqoy$5=2VVi6@9}OvI_fEYKT0kc}j{cxuD3 zdB*x60?7*9R#Z)?ko?8y;if0Q8K~>GwwZ6rvTaq>mz86ydaAvmq%7=8Ah2bU6(ZSS zPO%AjByGeZA>t>7U_A6`x{~n??3buj!`5~zQ)Hf{9`?QchH6ZD=aNpAbj{kTkIsT#~^7@!cg^A2fVvgvei7b5u}fv<-GB}dPm zneD+aFe74H4sR{Ud%c)!4|UMw{@LlKz>8G%0|XuTtnK8}xr2Y!I~;1)nB zJOgTIYyL%nJhv`xsLS5>Grio&hx8K?u0gNp`Z?MpeQFAM(K@m+cw7TBB=z;rN^l0n zl$JtR4C>;B81|ET$NaMuJzOrV?>k9tDIQxfTps~{3OGhM$#ZR6|0W9JdSHPIZWJqF zOaNPP3@(?yZW$=X-I%^M>pv1M*Lfi<(CSoeQkvz%*F6&Yw#x>BHbKnFxb4k@P@dJq zU2;ra5kJ3E)VZbgCZifNj3a*o_$XPoD80z%Wi4jlnE3^GHTT87rL4i!Jv5ES*V{gn z<>Vq}TQyeT)^^ipC|r(ll_@$FArlN`L!kXKyOw8Vp4oN<@OVzXJiQqN`f2se15u|C zRh)o!*YeipM{C*jpsG3hJ4-2!IV-+sX*hXgefanyw%~Zm<4()`AxX?n`ZX|dz_Bf6 zSZk#^TNs!YGETOCK>4KcXZY}eksCp+d_UdU@w|iO~u@GeEUZ39cu*CzyPtZ36<@f@h5Zo~4fjW(BApR-0XvYT9 zDJD5`E9}TLTXhRT?bYLMOyLLfx%ZvAVnKGhFtnpbSxRn9&N&?{d@m4mI^yha$CCw( z80sbxR?I5eAK42$b1*4<`*|qRdy!adA%190ZH!8+^LB82!e_wiVdVaIZ18s>Hp@fI z>kV2JmNE2r`pDXi7fvBQO?JL~8K*kSmQwgs7|{=$w-*`xfVs!OuHL7Kr;V@~@$!&2MWk>gl|M~Wz|@67R#%V%!QHhhcb6AuW;ylXih zr~&mo<&@XrRi{cUOwnAvFjLYFBpl|voOf9OM93L%g=0!nEA`!gcvgOg0FLPJic6AH z$8Ic&y4;hJ5F~Q&ujtpiQI5~?U5prF^HVRziea;2-d1gVjnrJ+o^Q-lUY&09y?;&v zv~>lLuj6QA?fb|E1t$Ob_AIMCy(;y$a0!^l-oX~cL0j}!ru?$}q)bDf^>?;-Bgcos z>_xYY+Wa*~o&bw)V-(x9wGKdf7^X3mZnXXN∾j#lD>2G`}oju8Xjm^P;mUgOg6| zT;SX&nYXEm_)f@zW}$=1Tk!6iwekJnV|5hW^%XvnC*OuX(2M8@n?r8{%uX)RNm9jy zjF&?8*6aRoo8{_OPl7If@N~Z$RE*Qk1@*X;JL* znXNC5^Ql0zKWY=1F({rTyB|v2YJp?6my#uw`j^zqtfVHx2X`y|%^{aqQCloEO{koW zXxa;O?DK8xh+^>ij_;4K)hv|PP4G-PN`_fpu@kVEPkE}6tsN{&2`>+_ z-Ths4!fye5ln|uMk6$pE?F|4uw|tcIONnYCsryq+wNQqa`g4u1E<5}t^1mn0C^gWl zBe7zQWk+^^;nUt({m-K}?T0=E5|u~1eN4CU>z+!_LZB@cwz_?Q_GK0ZA<%9TO~nzj<3Fjz{r8JL4tjlNuX*wC1*X zQ4=O9IMq)XGF^p%ay}GO%yQX%KYq=0Ohy`*6-As8ae77Bx*NDIn)N*eYWW7ZL*|!8w=6&8T3i6i``N#1Ce9;uRf#!$Hs%&Me_B4dPGL$8g zRzNA2^WQHH21u?ZW#3ijrnA?sXI|74rJYfD{pQmiFi%gTWtWuRq7KVX`QU#=7I9XNFFgZRVC7d$qqy2SpHzZUfrrk>PYsD{4a0 z`@cg^jGG(WH!n9Z?v!Tg-MW_QRmvzL-_~5Kl=+=!i6FO;DOL^BG zX^W*B=e(*lp9P?q36-!b77=kf)tlB74yC;=gR7m>N`|w6H%FQj#ml2!UkK>Z(m0mf z`$f7^ZUwcS@cQNjx2RNbTfAX~M9I*lchdtHcaS=;3v73){KnHG?+blcQz4z}!N7V+ zYOAU3>qC}+I%+^|X-80cvtJ2yc(%RFB7y)Ddjh4ZLl5vuJsP`z9>y*}ZddC;%66oo z`ZpK_9EZEbxgFQ5RFJfrkn+CeGHv_2aUfx{53f4Wl3xYzPv;37WN zb-7UyM=%ki$~lJ?UVpAIEGJT(YI-XgyDJin{+2x)HEWHXNVDtn5K3!fugqkJ zW~}B+gbhT!s!aY0Gdwkz0wD_ScKYOE7pml%yd0J8T4g?kxH`5p?((!v*g%}IJ1P9G z4)zvLwaWCbOSF0X82&=v(iw=(3UE|Xm5rY=99Apqoy)4nqzHb7l104!amYEHgA&!9 z`Byb}%kj0jrKK&&cB>XIT9$-{@w>Y3l+96zYR}he9ZwB5C1m^bMQHT$7bst|D^9$i z3@`03@4JvaCb{WGoQ_IVG#d(bbGZwN9~>>0jn*Y49{m_Rd|YeC)Oy}VZPVssfBbq& z4acVFACw{kl+CRyEx&RQ#rhRLx2?I#f7y8`kUFic5Otm^1UcR=# zLCQ^wuzI}KB>ed>QW{)aV5{R8z_uV(p#o1Vyb2!qR!(u-i>;PQ77n&wi&#{I9_d{y zx>jwQ7N^)L=~MTke{;=l+1nRvE=&!pQ~cs1Nul>as|+R6q2T7**?XB|An!Y3V)$RawflUP+HR`wI#C@ z69xF+A+yGYZ1Zm^(+?_B@1EF{bj(>=)rtDxkba3JkX_?o0f)u zb=B-+i!0-cp94{e|z=KmPG&;-q6a`B3Y>dulBK)Bh1+% zR+aB>NlF0Y&gOK>CphT|C^+nJytnjqvl_m#d_Wm>78BUhL7SZ|f_E|y)`dRwfa)tB zT*AI)yI`)@8NPRUwNpcWmiB$?fbeS%@#j*Cw@q%gaCVHNIbRX{07(9h|AMYG{KTss zY-YKimD^5I9vHu=bGAV{Xs^cZ>b{RzD11alYbDr7GH^zySsht7gsq#F39q=z&>oP( z5v`P#a!L0;-z+i&Lt4GM^j(nrMsu#TYx$5~MJ5@jb(=)&Mh&YI% zFE5zte^(CncHdI+w8XhY1~sHfLUjsX^}Q3Dq6~$CH#(_etL!tm#=5qG)m6KeAFf4O z?3@FmoL`e(S@GC$mXRC^5q>Ab3@c|1e(YEDpU#?)7}nuld^e%vvS31X0Q_g=t8A}2 z(sy^z@GcHPhn5(fpep@ILYJk3Fg@8{Ds>?BaiomJ4q*jI>9GaArzfAJCd$;&dN!g8 ze}|fmXL*OF+8dpZpapQS-A+6az9+sYG$&TFyyXzakf5v0_Bfsu3v2O;3!})KZ`Zni zHM>tD11xVpEAdkA^^x83GRuUADhD6~Eq^Zq0WeX%WNK8Fz&U&%iu6;ei?QI{H`Iy` z9b3%Q*_we5t~Xc+!%k^Er{PnTWL%y?C2i3gr1nr$3S)b2>)d~#vjj( z>#b^bY-xyq+Ldr7rrATW0|CJ{xj~|XvrZ7M`QamCfLH;j+5^1|4{bFQ{nnr;pB2sTHxO09sHMQwXBEI z-7TN_uup2Fh(*}ivwcFm+cg9GK{9SB8f^cGqya;&e;mrS#EKor$n7CfgZvoU6U&%; zbe9F8O`YOsV#nf;jor&$F{Kuvv8zv`BFPw6oZ3H*m$^=h`cXRi3wS!bnFlEF$6buZ z20pAU%$SLbT=z~l&o>NV%lc)pZqTy}y27cmKh8eW>uMaU{zC4ckdK!3>WG0u4>;K; zkIrMV=WF8Rr2_1tX(H&&q|+*8 zk0km-9auR3{`(*#pzIlsCx(6$?Cv6*;|T5m9A`B6ceXbEQ0;((P(V*3c*l}j5@*+; zZb^LKkgHQyb~(jJ-MIuLKbZ9MZ_SuYk`jJ`nHFnvW&`r|o;mBiPBKeo2fX(Jcu7=e zXt77d^jao1c8eSETSAp>U4q*$rk}kh4Sw%*Tb3v(@)By2*}Z0F7J6>&483OWHmh7m z-DfdYmU$;n3Q^lts@2*-N=ICOAWD6V%#ccvaINuS72#f>Szp@}gTsC(d0j+M6N%ry zJ+o6x|sxu?)ykSYRbWr52S> z^d&3CL#u1{KF~`R_@+4bQmKgdV!BVBQWf6I6@1vcAvhhLle9}KFZn{ctizXG^Tcus zqJB+VB!gl@<+EYM?!rzoZ&9Ng0=yt4Yc~tgZBG9<3Q#!*o|T$bkNf+Bju1w1x8d9X zq|!u3p=j+mzr*&7OhTUZ0eqbIowLa6)5-^g_SuH}-9fA-$)DI8b5-gN5V4tUwQ(B( zU%T{OiaBY)|iq=)}Cy&`V-K?v0zYriPvZy-n9&+D)sBAWW z!c--~p4a29|tS+kk1y#fkWs= zyKIY=m#gZC1t{ZKFCVQ+O?_#u$vNO1)~exgBk&XdV5OO5r<7p}E5rdk?_>c{E7AC- zQ~L>Yg7wu}z$EcQu#s7kDlep_IdlFod&WU^Y|qXP82Z`!bv-sP#8=j9mh1M`*5gU` zq=R&`W1Xn&yo4oJZ@k3L8^)}{Bf~A2=f1`N{)R3OQiN8))Jlc#V!#d7DL*!oJiHTc z28&JPE{;sm*&LD69R^&(18zMHRX#2J3>$Qc($7 zm+IMrRtD|W)e#dulFNa*ohtu0lqlQ#sqq(f9U4gRqqO1-;J7V_d)mgUZ`%}}laM_n z=_1L0+$So@VY2#S_pmAF<3_alsWH1p1KanPHcy=@vw%75l9*>x?~Ji88#pa|va{D) zxFP3YBf!?R6Mp+XD{??oJuo&=ewP~{>4gMKiDiAiFCj52@NwvANZ#EsGEZwJtOV>iC8Q0CN;&Z(imcauC zV~Zc;pnviomScMVarjY({nm$!ivN7`y0rT)cmGpu!w>hhLCC&*V9puE6ol;|%#;y=Hq*R-GOH{)4_4~{mO-d&58O)M6afu zfFw%GVz$QU4CwrtSv6%=!u#Hc6bE2sW$TSZ?=KJXP zj{{#L%c{jWgHAB@=>k>L9=1G|L8P;nbCrF6rTE(0nm?FR^BZfpu+}x?TLo6uSYV4* zMV38E;5I5wkM-ZyJ4LsrWn0jFyed5cTU>s@ZKSI<&fXF8;JhO)l|S+E;-$4d}@8yBT4;7}X72n;O>K)PX zBerG{d?!G!OAG%_wlW^VCGa{fRQ>jd%T%?vfGUrw;x1R3^$kSbAU3r@sgpA>{1nER z$U^IZrfnmJ5T~Exs}@piYe&1VJEV;iL+ALLBn1b>H(M>^1XZfnJhCh4Bvbkq_BOS~ zZbIkY{MNa97@N9p&DJE7&pAq>8;UtMq~d=uY=cJ$M%28R`QXfIsK31ikqpTmbYFGC z&aDa^+Zmym7bCU4mBXd_iO+__<@Z@6pyWx))(;a!W&L4`Fz?}YPGImCFQs}MMl>vU zAsTRa!VQ7gL8Ou#o^9@tzDlX+@7Z zFH55rFxLz-NaIp;@{=I_4nDZLErHM`KxU62Q8RJsZ{_6z_Z1eR-$yj(~K? zcM*t0wL#dW9T9tSl0mlVLxtEZ0#g!KTk~3C+(CPw5G7r{-bzipKePKER%Q-b>oY(5 z-mIZ@;1=PGVAfMeRW3V9l*4;58Q&VS_o2BS;Jf2a(r?SlZK~P}JW7!AvN_s4_}k=p z;#{85TBxNX^L&lT82km}w*9?|Kj=$EHG3Y&{>B*JiV#{C*6BESWZbf@xo|VUrLlCL z_IJJYsVzjb0Z9?6vNl*oczc46%1@B|Y0Zm?hT*y%POQQP-M%&;Bk)`f(p|)4{>eEz z+O~>er zAC_^BV3_>yPL>I`+SUVPJJBEU)mm!;CQNSjr>&lnXQKv;+v~|2x62)wL&KzKi}gQw zUR!{$!4-F6$n%@YeE129^Fe0O*y8L+L3yOigx-Jb0ljnB^tF(`CY&kDXsK)-U+JXh z-xrHqo}9@SZk(nREL;OixzFPyc8(z2hdih3(+~gb!~59D(g#k(!Jb7@6oDH1XRPVtGKlyU|cUX&;b zn)gY}J#D=i%wdBoI#dT8*`XCZ5qV>(TH@;<)%_aE5Ovmu{*Iwak9qWy zf~arcE=3pNKA#`#(K&aEQ&-uM1AcY_=c)f@k9Xcw_`4RQwOoZ7wZ}A8)wV1HIe(6?D(!)77QDqy; zDj|zz^%B$Wi>_|W^PtCZrmW1r;r}>7Dm%d~D=y!M5m)Tn3aa5!tcH4Bua1N=Yx)OW zKtwru@nk#^IielM6@ZII9Q#XF{;@X%DZLNnUx2l8O$xl|anO!( zlx6}Rn{1tk9{qZJ)gmm)GLS7v-Fp9QMEBDUjM4KpxbAJ5TYs7)vl7fdIPIdgG9eI+w@nK?&|#KOF~%nn zB)x0yS062PMo53tR~j>mQ;OPAn}76=BR#$)u;Pj2KaP7AY=!+&dE&Diq?{vTz~XI! zQW>eqvS`{FGO};iAfb>dHLzXr*p=K}UOXK=UBy~61Y85#tyXNkKL}^QjJ=Gu(Zpk# zY0c38Ndsjb4D}cm%f2g^*0Ta4QdTK^5JJY#vvR-JiXdB-(RKeg&K>@Gn4EXd)gDKc zmJTWTIe2&j?XRzF!D~(!j)4vK&#KybaIrrs!+G+GXH2MmI^rNb;nT!=XNHMdEd?6)(x8TKV+9P9Hx4hWc-u~&|z zskEJ>8DT9kV?zOY-b%9G#{) zJORFO3^;tz!BKlNw3xUWNesr3XR<{;E5TK6Q>WnCg|^d1B#a)TLjQ%Hm3pn&CurJ8 z<%(lACdnnsDc@33#Q=Q^#eCTU)#5u^9)b*7 zcHA$svGa1;{Au0YQF|rRqC&lEu=cl7I;64+xXkJir+)2ltEr(UDgnZ{;ppTRUjwj! z0ba(A=fsO^-3AgMdX^47u*2S2Rps7X(4DUse* zZepL^UgW~giEOSrivFp*sB#t_KYNcf`(N9D!iT+6t0OPjy1d6Hicy))CV={sMDlW@ zYp&7?CmOtF&nO%|B&AtHEEvDuO!-+{a<`p-ETPliVv!aU0QgI=JY1zb1sH2B5&QjZ z-%l&sr<*u^yyqz8Sss$KAEXUq>L2c2m`Ystht6J8N1Pt}t?RS?q&l#orZ?s2{x@9z zSE7LURpRvKB+g%KO4pRb5koU9f(c7MBne@l_k>$-o?KPs&0WH$KA=fusLS9opkYVX zw=AwDhdy85*eZjPGca7||E?ky%(HkK!fGGhmGY9JIljp;EkQ|#YxD|3m zzx!_Fr#&^iaQSlTgz{Lz#4bPw(uOCs0A3wiKmxJ5zN84`(5ZTHd`wB@v{e?eWgj8? zMB<6i%+QWHl}bW@Y-=Gxjjm=*2qGB+XihGL?f$NJs-xm`b_rMS-XvQuRwkZ zWHR%zFX9qlG{m-OrZ;$rfT7>Y6^4;A&XI%v0i4HmM( zN#p`1$_cZmS zM8Zs3Ik9tb5T=@UZMsTfxZ+KGP5`Wxn2)haT+O% z!-l1_cG-ZHWK5U$Rgmg~`Ghfzb>wZUp`Seva3${fgv?xaTAW`9)Mo$2z4&h&&fDrA zm1M}o1=DyCY)gO6F-dg29rt|i;*3z!e~>Cay_Gl*hYLq~b^Bz)E67`deLg5Ce$`Kj z!em&jXpW+#@2^h**T~D5FRC=lr)0Eg!P0#5{^f0rk_V&T9=AAIvGwA6O2o@ZlkXaz z53px8g<3Vm>m^{CpE#eF&UWr7U>v;qbqlxhB{NQqNkEtF=$~qCQ)UWU(rkhtu*{gD z{fxvWmDpFcy*~>eumv(@rjS@kvRfqqy|{lI(wfy^)%qJM{W$f^9V4dxOyByD>7{qc zJ(;buD;5swfyef~YWyHPbT%CrxDjx=VprGGkc2r~LuRj^_(OTR;U@GfUp?A80AeOz z?Y*&*qDrhA;c|V+`7G(t%&tnP?5jUMBwJL-%`bO7Ci_})QU)VnTfT_HiCCK5LUbAx zF~5>u8WGgD!TE4+L)SETGaJZ-4e3^8rZ3Ti!}|A>OOG(Nh$(csrb6Sn z#-qi`xeaC|>Xk;HzV7Ri?opX~pytoF{*R-x3}~`_+c+jFB8t+&R6vxJPMPsgA|m2w zn9{Y495psY0cimNX_3xJZS?#908Az4Ck!^U zeXl*gVMy0{@p zLIA4##y`etvP@)7gp#$jHVcaav`*z!*T0SFjj$`C5=@T;A1nagv5_ps1|vzI)vZE* zcF&Gf$9U&W@cb&S12#0iG7a#D=Q$!dD(z}BeCJ}zWNXt6#-8{#KlW{hNG=Xhru6rO12mTLKajYY44TU%z`^0HxELF!Jw^# zJ?ycCOm)3%2Up+Dc2YC-gYvwR`sfI8rPzM(bLwH#;kXZ}Ygw5gc=B4ukJhodeBdzp zk9Z>5SKrXO68o~w6q?i*JZZi}7##h;y%1m%9^{gX1z|}=J9f0Zjn;{`-&tYxo^`V6 zCC2a>+{OX^<=1Xr`&d)8b`V2{XKp{koOM`~WF#T<3fc=EMz3=% zwME2__(#4qb`gYLT5H^)RAYAhukwE79oK~9BS-Cke$PF8&k6o2oFxhuS3#D6c&yDu z+K;WLhXqFcN=rHpzSu{Thj3XA?sL&9!#pWOOGavqOtD`$&o6aXThMD06-Yi8Mzij6BC3Tc;g26E2bUL3?OpkLsN_qxm znd8MxP0Ic#o#R)g))t*zPfftV>ziz_IjI52bEKSbo2$^W)D->r#a6dQO*ZR5Q5JJx zWlI+ybaAS0l71uY>|=LBnd(j%^!KpO)Bl)&68&dx53LGlupRxEJtpXPqjX4QbAuQTM?D zs{bw8J%bV8W2JQTG22(2q`VJ#>N=RK>t!X$pObV~b8t8CPp8svmK0@svPAX6ng_d< z=Jj%3HT3>I>tM*Zr>yHKX$d*)el%J@dC{L03mOgW>*4X`?^?rqT5%s0&XPH-#8uR* zVSab)9l{?1{UU=67HiJOr!BatS5G

    V$cO)!O`b!FD>AZ}I$Bw&(GtBMp{0)uNf= z3G?>#Kb1_(@f}MHo3alK)G02#U*PRD8ty^R;^tWCV7+ymkBx> zX;bEe+2w(%{UG1_MIwAEd9U@9EHu1-X-ub~5C#9mlzPvys3=>NNzJ=x=wUQT=|CL1 z&TybSSc|VOnA!gCNpD6zfbO?N47=aCnc*J*ibx+5MXr`O`*ipCz1K8HU(6cGcM`;E`DRbo zV|((w0{YMN9NznIe>bClyD!z0!v~^2OLDu$M<{*P%ehoOhC%+$xA@Jp&ijvg6s_g9-a`wu9wLqQm@md8J+C9)TW7eZL~H)*_fT(S6^UQc{<;DA zHGf+DCL4`5)97CyQFh#`5cNJDoy>&lOUasx-?x1S37_pqt?+$zaX)Irg2%%sZl|rj zzUhi04CP1Kxlb?3OH1%dgz9FXk3-+|wY0Zf#!sQ#qAyludWH(@tP4MQD0jGI@hDB$ zj%~^>486C}HeUptl4d@fp^T-v+%xZ35j`1tL=}!a`Hg7DN|<~F+_jOY#$JHLU9?iS zS2fRQEGkI0kL~PbY0$DCn^^7hpU;2MZ>Om!p(j+DM*vCJ=7 zwqwveCQ{{x1?#5S*!U&V`r=?Ze2>pK_ElAsN#|9GM)NE9wn&1XNVFC(>g+dH(-7j_ zy2R&KsBQ%yd$1HkK;rS3_ErJo9{5w1clvQdtQat(elp@VwoiKa>V>DLnc}M1TvrL@ zjfmEI&)e}KD|>r6aet-ag(&sbm6Bv4HTkz;bozz2|0Q%+>t?&VyMZQc>`AFe?|!$- ztOK*puyKf*(FD^_B2}&ZY4@G&v4n|dUC?I<(?Ue7|E&M*Xf1ib!6&U6K>Ga_wp1jg zQ#?@ff{x7?aXt!U6J|S$gvEZ3kMmGE9?q&sIOwpkchDoGUX|&D84OVIy0R=QH?kr1 z9%QNBCFn|X!TT%NtLp^w^!iGkcWJgaI+@3cgt`#$9kwbvPCM7rj_JOeOt<9$A`@ee zQj?qXsY`t-Y0E<;gu-A%hacEel(mQ7#9Ks=RH)-F+}PW-F~E09!KqV7x!`_PM1iOwB@WzNHlAHX=CwwYNDhD|{$hWMENT@Fl1d59+cM%Pl&-(!As2#Ah%?LH`cu9A~sjrbIKv71}o zxGh6@Ycph15K}iMS7V8^jO&tEXklQQaL9z>Su(qmm1KE{i)vTdO;mg%T%D5b=@E); zv{CWUO?G{2cMZ~Q7nL3So{I7l%@)OUxbFC>fjF>EIex%kbx8iAy~N&Lv7z2Vu}n#6 zb@USGT4~LUn_vIKv7HD%{!oU`212XyQF#q9Qws`hnBcuK$Z_#OwC-;h}GF`ogX{c-KD&;oA zf*BV$YZV3Kb}YW88ki#W$n~x_yY^NLI&h8+G+mLdaHPHAu0XiV!^6ZTFQl`WVp3*; z`C{kG>yE?C<-3Bt_cxOktuwv+y?&0J-LDHvd`xJ_X*uZu{P^qM?@9U*edOmF*HSbs zD6Urz_Y-t6be(s!jlMtKEy=ZP*^v1?swLmfD7I(AJO1a^YOT`R*oS*H)_qyVE@*sp z(<^-@hx`}OriuFX*afaMaOvM4mMxHGg=d5%Cz!m%< z-(&5)H9fJ95^WHfD!V2vgPYLSGWP-Il(sGM$Mq92cX#1PIGpAF=CoOdM7*SrVi(gJ zooSs7(V=Ah- zDH^22EEpgCijBiPkJQ$+x7e%ANFSy0u=PzEEq^$}(X|RV=M@nVY+nto)QXA_m$vvB ztcrR6Z9CIqcfjn=R%RO`RpklRuL^wKNu>(@SJ=Lyj#&NVe2~hy_yHWpry}GynAMBs zgUReL(@Sr!$;Sv6P;77M9Y_!(>= z-F@LwC-CKH%ynNb{q5ko=K%tTp&qBhe1+~+GtrNsN0;yYzg4Z_3%5-iU81&(Eti!2TrD9H@<|6)+i&S+a0bQs0l?meCPEQA7z^$TtiUv`czv z7|S1(w>>Tmm=V}cw2za=stUW+JC~OuIn3KPdTZGgs0p?=?<03_WVq>rUj#W}PMR@_ zd@538uH}hSwjOPZD%)!yTYJMgd52&VTz6Q452BHcLFPWr zm3Y_4*1krPw@vaGb{;mJs0y;9<&^D<_Qrnm($oB5 zzM6W&NFJOaABH*o1pY69(VxE8ayEvGvp#Ej4L{E5;1$sV{$`^B^K# zlIz{V38oQ<-ksxX8YXe_b-_B|WWFNIM#hKTu`KKR4$nyDVi%2QQNIWH>qcW5FB?HB zAOKm(4XRo=^)kSn@3ND(aK=z3@k(zEx=B;RH|FHlGi5a6%o=qX+PyAwu37}lEs0p7|ydSKhjwmx5U-U&jQGl@;Nm8QBchPe5v&tY1~ zQ+En`dypDV$UCXe$8#F0{ET)U4&cu*w909pnwJF&iK z;EM&xvLxDz)xRYM8{f)pE$hF`#AYlviJJUl8Vo9ctQ=y|_tAGCpE^Uszo!u^vTz`6Psvk--1~t>}(A12vFAyA9PIJ${9o}MoN0ybqCwV z&7VTa^|5~nRv)iT17}jWv8TEB+ZeP0rHYC!P>ok7UCob~X}o{OBA6OfxzP*NARPM6 zHAOKx)8-XuinKd7OnTv$Xz@+f9jWh;`f9gbEutISJ;%ZiUUh14_+{^F>BQL$zc{?03?F{(jo9%-qN$neGsJ#s0OHZmfUxiAnl_76q>jNvbL|QXe z?94Da3k^EW*k)~8J6xdO2Z?RC;M-BG8F{RSVj+0OX^J#2b3GD zFcq(9}@<3!eOp;`W1Pf?TVGJ|IYS7%MK}b z!8w+ixxP=;vT|{jTLkU2%@- zmYmB8k*XE+$ct>`7Q8KG@w7OeBkSubz5Xv1RbPKpD2Vk2ANZiiAcl*7 zogq)TU^YZoL})i{DMsuC#9Z`^^?6)m)pfJKLlz*S{!TSoH73{esFHCUbePUU|6_za zKkAjL8o^iGRWfd*ODVmKJmW3Mbk_LJ?RlItVKpIjQM=vxVN?EigtH>lgl=E3dDlMX zTK%Eow&X^_|NF_VGG?(zW}+{t(R%bPUWk^2tcFW!}C4>=T8(VzW*iwsDx!~-ujN%s{X|C!PZtN zrF8aU;~z6~)nbrISxMRVz`U`SwjuiiueG?>KD9f5nT^!9y|(3+)&ry@#y!w9dC`vE zTGJ+w<>-0HVtv`>TyZ!pyV(*)F=kKbPZqnObJygEn%o5LiDhKpU_DVBQtV>C=$y2X zhUeo)g^}9xd_I9h9O>YA*p_M@?v<(L%6!P^5!JthCEA`*H~P`Xw*(SqKs*kemGAB< z#Gc5la5)#!$d7X3fRdW6flL3GnjFvEc+nZp_--8SrzYuugM!^SqOm6wL>tjjSnOd8 zf6 zZ)*0G*D>1ghHixKfQ@v#o&{Dv*&L|2{klZmpdPxJbh^s>Oa6U*XCFCWF~_o`?-_+a zzm+B{E#iXm&sj7D`;c<@FBVZFz7h(11-Qg<0h^FqkN}uS#f66{aw89hpM2C3)jwnm zdSOXR>bj_Hx$yS)*5>e4eQ8iCP>TNe$(0Ex@6Xuq&Wzq&sqMFgJ>@KG^nFF>T+NS* zWeUZNktZ9GRt-qnSyn}wrNB}*5u?1A#ou%QW6;XVq$Sd0{J)WFqt#=YtC-Yp^7V?= zC7pxIqa3I&>&lE+660TZ9xJwix`u#*vC-(5Er59nAjM>T!Opk`{hT~i1Z2O}#QYb@ zKmj&OFy>oq!HiHeMx@D!o%g(+hpwrVWHMzCLR_kul5r~!%FamcKpI#qH}iWO9#Bs) zYM||#Eh_4TE;AAj6Sxc-s(lgb8eetPY`>DF-uH`*FoYtZz>3UINNL9m@ezb+&g7bZ zZrM-aurl%1D(6>jy?4|&iM>q7E%YC9B>2({BYh+NO>e7$g1=rJp-SgM$%EL=Z-m(E zXOK1RfeNzxuM(hdtKsA2vj#0MN>y>PJM{HmEP;8xq!AnPClf^8KZ9+I41| zaT+=vmi?EwJDHi~drtgMs|W`@r-coy1zNL~4$qs)aV9?k#!xb|W~gr*znMOq%;N<4 z#img+p=4$+ip^Y7+tR2jWpknOTeDO~d*U-;!dImZCTJtlBKjMuSznF!0EjVeHHWAW zoBC7YP6(Ke92Nfbz;D|}$77>K2B0YybLfqHgO)XyOiTJWsysimN!6DXT}@_N@z34Q zNEhOS1pvNFv}P?Ubu};C=u!*cLLc3MegcFdAlsTfQ>u*kFK=wvov4F?$gCNxL6{hY z5r8-jvDresNgQ8HuA;;iOOfm&uN=YXm&_64fLl#MmQbVQ4L1BCBVhUl-4D%`TxV!J zw48N*)C7Y}9H{iP{$8A3wfV>r3RD=g(XN0np105Gu9dBsYHo3j_FzZ-Bt~jmacey8 zH-eOLi4 zRu>6Z8Z^b~!tQMd=Bv#EC6G_h>)G3_dK2-!eC;KD1kerZn&}!5p^Lyw=lmjMFOYBE z@q~Q#s8C|5_g?WuKd#!})=&74&sdF$U*ieP-F28AVU)v%{#rMVviAhr0F1aH@J-(! zC$Z$u)}u2$Fh;(rclXeSc4gmyf4|?!a-=FDfvNZ#>|Zx6N<@2_I8yWlhCR>?Nd$~riD@Q3Bt{ZmPfKaPxh{(BVuQjV& z6$48{wG=wfq7>-MiM2iBQ#6yOh_q$is!AA^H&>+!yrHcxkxH(;Jy+up9?|lTsRG@a z`59LUjhKT8Xcf93?`x!9+eY`U9TQQiWCdlWTH9m6L@wS8d!|fhb3b5VC$M_i1 z<{>DfvDCrkZuP>UOwWs4X_YmL;zPXtHHs9`DRQn8NUjksVORC*!+A_Y1g~71o{8oN z@dRtVS`Bx~406ACHjzuFFeGo|CnaF>r{HP6`k5(T=Jx+-Ha_b?)m!J*fC~MW7j}6$ znVopL_&l-k9X_6x=yu@5wbmK7^(551gn65S`u%O=4cwqt>d%8I$Jh=*RV{{U!8YUa zX7sE4lUq98m(gl$bEhi0EGXvATPe_(v*<|@S$HCkX@RzII_+*6@6441CbI+D<5Jt%2ZmV2(Gh9@2CdBB zN-y_lWsHRd9`E(1tN(grd}6-`8#K8HSGh2y-=QCFgau#shL{bs99+41$_YueIUmc; z+<)_S_IMSN2)@40#*7U*F`W5^E#I<=xMkFIy9R5C<*XFYk%;>*nTHu$ezBph zT7)8=OnfEnCgB49#dv!F7mnguXU9s>zL?$4H{xIjt}@;(D!p|_qSBlTG&F-xIvyK;`y=$&)K zrq#fDnv3$XqFL2})6C7XF607zBw}XYr|qaCPP3XMEfC0~l{plzWoD&T5s9NRqF0+! z)tmbMu9(RU$XcyJP_kkpr6IW*-f` z>ut)-tAG)zq1krer;*D-2YF?+?@Q!jOHYHu#TC(0H%tTO&+oYGSivHAKcjY!2#`c^J&ME+aC6t&CB*0~Cj(=TZQc&6zmX~#XHcZ_ zenTYwcsDEUp(AimeNkB0m~3gAG2ah+J55ax&s0O6hwpp}bq)~8np z0n0WrCh)FD#zuPn?aPu_F7_8b^%xQtvtT(oKuFKpfQk+m0F-1uNR*n|H7#W!*=X=? z?80S2tfDsb%iOrak8gMZFCYX5y;OO;>iKP~#(vt43Yh;ab--Pd$s|n~4>fQOn%ed% z_LtTwKBT_#U+_VjoThu1vdog(?vJZ^XA_;B})BzmCS1{{8Izs!Z72hm4On{w)|$clsMYuqnC8j>7c-#(nF+` z=g#3C+VT{e4bh#`$S7ygb-&igPJGI@Ro)tT?$@3&S|E-AYB1t4^ywpb6tBf+98ruv z7K&)R(Bz&nFbU-YyrH+L-@}G7{&Wi_Q>ww(Fw;*|m#8+(tEblf{-Wc9W-qOe+Y|0% zlarRE#XtGr|9pMrNdYI4gpT3^X9)GauA97l+D$GZ>E%uD)6#2~0bf=?f~Pt1#VhH# zW7YTdB8wRdLT18BSJ%nfY^7tZwe8@kMzcESSm(lsyL(Y~Us>#Nsq5G3mi%<~y7$SZ z7#t>0bb1VFSu%W?Q+v*)3DlX?`NqUed43HX&qC95fhY`6%sZkLSa--e*pE@mOB4br zzw-2lyi>O8YQ=i|;ycQGG*`?(C0Q4MOi{jK+$8C>k6B6@x!^aVI8+xDrO6(NZkMHWCl#uu~5xy zJXAD#%+`0xmV}xqF&n{vE5Kjgh3I}UT6`Y_(!3gXc~OJf>cM2$NvD?SA2=PcWF4g* zNNnlU54uXBQ#F$e8cg5wR6zTyDnhpw&dvmbv#F zfyA_GtQ>GAnSN*FM0Hzijx!wFb9_H$Y1>!73y4zldA=&9eK>?UKd(y(ZTYxwXv* zv!u3|h!^9Byc*aro1ihU_&xf8UXN+o=FZ?Vfy}n-iNJtuo0$-XQRzHGX&e-A)Lpek zvwYrW^`Ig~w_(ICSupc;;tWMeN9jh6#@0pitN65CE7loCc_5wJiaEJ?F#p>}%H3~H zx2vqI3~Sc)znPewup|;p?6}T$=%!p&n_excF3HI=T52>2xc;(++kpOS zK4kYEk9;nT2RW9=fT%IDz`*QayvUTuR&jNku4tl8#b-hX&0i{=pcXZ{0ANCj`T`l8 zF}8L9mv6QO&8H0))?#Op9MmoM>hhEhx5<=)b^EIwjwdr$`qPvh;Oe&XHmkTJK}f_T zy{p1fJk!xU3hH~$KC)9*lbs8KALfhcQH3}kf5!{APshup#(t-0z9zLYLIL#|cQEm& z-9e<8U#eNk`<6-&NnfJjwO+X`iK>dd)}z!--{d$vpZK@p{@5vlLqMis?X0M`ZAi7! zEMyPGoU)SV?(dg1>oY8e0!P8AZnx)Cs{VYp4S75$O1VNX$(CM=^vch^EXm!ytNC5S zo{IHR3ojN5dB5DrND3(%eMk6sptfz{q2lMND;Jz&3?kr;(%~Dx&>x%siN|ZCN8+*0 zCt0JIt&9GHLK!xqNtTSvGcky(SM$YSEML+xp`N9>Y4i3z$33B_pHp2urRC2Mr7PV` zylA(slKe%Z_(f>p66a&p=mc52phS2hD&vtvc7H-Q)tgHiLNm4rD=C}5Q zSKx)ElGp;e#GsrW4W};%i7y?b}yg1!&fH|3QPb|Q?!xZQH(t`3H+Ul z!HKsD%L<6-jLe_n_y&brHswUdI2U}BOv%kM3j1k~N@56c2l80OWmRF!$wIIMpId|s z>5Oj^BQ4k45C6B11c+cug&XdZsOemb_OyE3N9L@}w`Zqap6iFqxkP;>JX?luW^P1Y z(|XK6s75CBZpY8(VIVMGUGobnuwGhwG>fg&gG+9xF<39E8f=a*8lBxDe}-*HA_@%d z#O6BK@KXNsQQPB}PNAwEfaCS6N2@Kh+B~I_iWu?hG#~V4j*i2V?tU|&j!jK;PS?uR z&7$$=i$~#T*(i>+LxFnQg`*Xlt%T)Jjzq3%_evY?DQWk+9`*WHp8x{3R;;`We7QhJ zh1;u3%b=l6imMTQW7aN_J?-k#^Exta$k+MN%=k~nKwBW6>0cBNdLDzRq4$kit#xVN zr@bMR#I09HGE-|_U0(GU5SySYBYX$d*;>9YXS?hiO zQoB=lgEZ72xVXt;0QtJca<)GorKs!ZYQ#Wpv1bI9gNQ+y1|7iW4QuiVz zGA(xZCfLarO446f_1zdhjQxEFQpuxMYr>4QNK~u$%uoq1?gE@qXIleuH3^!pW{3tu zAf<~R%QC!uC$WIX!_r$ie409)czj^g{c>-_@b&P6?p=su>z7tHCc6dW)HJ0j>Ba@@ zW7iZJ=Qq_qNnc!L1Jf;S^re#|%FTQ2n4?d4VV|h83hUa%HOm>N zqAbP1HP~l2T^Nz*<{KMIw*?vuq4L6}Y8Y_J{1P<@Iy8MvLk2cYbuY%W+3YIt8$149 zUekIMqyTho!3?A>Pv^L$%T6qe_$S01%El8f_%D#b`jBW*Aj( zyE(GOFb*7;>GI{8Tc9^4x9P2j&cam{!(VJzY)$#FkB+-s(GM}nO=&^$U$%lZ1Bnq& z8HZjYP;8S$9;x+HyTq=JJG7_%KoDkcH(ea_4bfWth9)Kl1tHBH2nmpr2Lt1!OePVK z^r4onCJT?UF}nvx2Ju~M-J1sHMJ;GCF~LA`IzvcuvXHQxE1w<5hf+>%=;#=wmE_hg z2#{aEQtx0UKK!@iVae6<~O(L-M4v0m8p(KAT6E5Cyum+oI3zcK{X zuwY9@!crN-{&th~X?Xs$D-I!`0xxD{owD3( z>FS!KCb=N8nHJzbE+1?Vg`qQey9CX(?foQ(uww zaNscXM^U9za)GN6^&&s~gyz1p%uF>T97;bVRue6gU|sm=TgTSPev4Z77~|~`F{tJA z$L?uW`%q*Sd&yYTX|=TRq;h)y; zmc@Yx3ms=&HK}gdfcAme7g*Muj{a_TY9#WICRnD`sIKahGHM^2qA^v_+nR6L7R{jH z7)-;g#e&7Ie5y8gG@5Ex*-i1De(3JN(#w{_e(h<7H zUJv>vE2{Xudxl>9W~eQ&zRxd3?>k|KGR-U!+x}`-RFFP{YIM1<{K!!J;?s)&a6O zifQsET4N`mS@3mJAVCT(XKoZA%^udU7ZtD*MaA$BJ*NF3HEgCqB3q%45Vb9>m%Br8gtt zzae;_KIbhW&(Jq>V-0dBu9A+P+q`Lk4Nuvb?>8AWV<|$0*)|Egcy+x$uGQURLr;_y(<_{s7pE&B%|{t2VBgUc@jE zzmNfm->uj7Mvp_%FMPCJ1N24ad+d~yOxrL|{YY_essU+g(l>3+T^9~<%uY6{4ZTuc@t!VjW$74^!4EO zhJ6f&St&;Hx{Hox_j+*~g|5Yto9?7khJi5$xs63`()}MG8?O9#q~;WO+lpoMUNT6* zbXr!FPDw^oe7xu@v%A@|*vkI7h11Bw zL3tDGkI>#q^^I?)--&{%CDG2WhP8z^-|@Ir>^<$vAUiG{uCpn&>+-X;Ma)p;Qk9lQ zg{l)axm+VuzM3k($>#TXBA6FotjDA3_}*+xk23 zBU;A^s%Uf(g9UF#mXR7CGFtQKRtjJq))5mHw_4|2I@IbbF=PB)lu$Krf4_A*ktN}= z7POiIJd3lngag9H1=O}XvN#UIB}=9{;3j<$mprjyhK176KdxS5EW7bE)f3@utw^9# zOqdb!`Zlz1mLiEinH&{Tl#ph>!F1;zLsLf z&)P#2I^QM&)bUHPLmak`dZH(ljRB8@W}x#Qt=4ED1lP7mht!l!i@|_RA*$sZ#D&-L z1=h+#)41>3qN456vuq{wm2J*iG?FpBsZNZhi`#Esh&m}3ZYovZuZ>m^M2>!C!Zk?d z^MF%7O)!=K^AQgb|AW=7A4|-w9On|z2`=8=JghEaJF-=`XZ-Ce3Ilfev_Lj)Jb95@aXq zPlNtfjsG6D(jp#vw!$eci-9Rhf{wfo6(vU_IcARc2WX&R$Q#$XK!aj$*lpK1F@<*8 zB%}1LK3;7Qqa{VZrF9;es88>bQ@qP;Dk1m^yVrmtg-^W!yfgHNzB`94R_Dg{FAbLQ z_Kz8B?40zQfADCSIhS^@X0deS|EAEuFq$&4S-LQRX2-+oVbjwbbeoSm)fz4$6Fzqx z6HtxE-nWgH_s1!PbALB-B3+F2V351v5(FXYla<}8^V>Nw2XosNq9s%9OMj8ZlZ!=# zdzXAqfmhHr5(A?JM+V7Cg`OSw`^eDKL~pOJQpvZKjA2bh%px1KF>o|y)rw~%+h+$( zNFYT<_u|Spz6>z$92@`U#9^5utBUodW?&xRFmXZpY zraq|S_mkZIYv=rC zNEDI5Rvd8KXd`diw(wfvw=)O8T))~^qPbQ+24q8={O_UcOCDlQg`O?t^}g|XEfAkt zOWZ@foL``3i+wasjVr&p^YgoB84ht-D6b|TCjYVkdNp-9PzZDIkEsTApMedk{#m22 zo^{bj(v1!O*O?V~khcx}EQtNoW|mNq2QMP31$>X|6gII<$B&o#A$0NgOOTnfK<2T2 z8_-akMV&M9t3swb>>fI)vfH5k2(z3v8*FO+=-zG)fiG}rI#>NL-}z()HdWbSRQ`*X zR8g-E!TZ9|(2E|TCFJVRFp!OBnTuraA!_cuAU#r_=K!5>-~qJ$$MofS)Fdckul88q zJ9ir5#5-jfu`5;;5LV}(NSW{=fHCG&ele;!yK8-C8=oqIO=oP zUsbB(`3%Yy#YO*P_DSEt2KCeN;NT5O0qgB@ z&xB54xhE!&J8;|KDCUU^zB)<)!t%yfGALQlI&u)vov^^sFSaspBm!=aa@LPFCh;X1 z)xfSz|MhuOT}0GQ++P1ZbF;GkS{ih&0Wklcv=fef|B?-8=VggOE7VmyG*4*-D_^bB z|Hdh8|K~T?*uFw_==`oAW0i0@68sSQaYErVD>8h=MzbJvGGXUO?l@xhGzlhw^_i27v6`y`hLCT{!_IWeDe#tdWah20@;Vzl-6 zDj%9@CF9|CXE@)JKi;))^U}{^?y_Q6ix=zOg>*5UlBy|FY#)Da0oS9@&KZ|SlG=^@ z+Zf>$3TR|hA;)p}f_3UgrI|fPJ_@pv z5*mE+)ZsKdNc9xh?*tdEZV^-5iWIxO9R3H}R8`aDICYG-RNqOCQ)gB_|5X~CFoxpY zXF0EJU1zUNSOh=Hw7Mh|Z!~)}=q-nmZ|`JmFIB|JqVe6oZNRGHYUpgBTg+#@QfWZw z$<2My`PZQuwz2t@w%&Z{OHr}kGPFfK#~MXu*xDq{b~t6Hz8Rt{q)OGIvk9Fed+kUC zON4EMX(n$@`G$T{k@w-s%b0nN#q<_6$)!inkrswV|CCVZ_NSowYE5HpEuEy^~8?%^Je~CqcVlV963-bC0 zW%;8Bnw~HF+I%)bdz%rB)-db}vvo|ltiCBIl|=o*T&7-q{6C`}=k@~N8p;m9Zk3uC zva@>k{Efiu-rWd+6yl*vg#4ew1u` z-5@4>TJq+k(ptOs5euF1pPSF06B}bF?bMkE>0-zMq{P-(sr(51@UT*->A9chGm~pi zC>>-p-YVGHnXA10ven?@?0M`u{|qjMTxB1&%}^t=JJpSa6n!uSRRb&n-!W zzE4|-%C1HT)8Hq3BM1Z98wM-t+MW*)9A>NmL-fG)vPDa0@1*9vwr)fDmAdo z^oe=t?<>Eee0ANI{m|8R8er_JWfEiSh-rUCVy zUx93P`W>Ml8BckHNo9x96)s9==3i`5JdH=lzTX1SuQ<)?0a`1qOjrCPUWTzF3d$oQ z3*ISro$-5ou-q7!Ogl5Jl|%1Q7l_-i+nFD>aY6;#oK66Hs}Y_wp}!(?4EaTU`}mX# z6;l_W-#8j^|7A^=&B(m_Z~DI9PW&sB?4Rhtec;so6b;5;ZH!j4kfDaF)Auz1ASNodg@kW?y0zqx;7P}M7IbWqjMJ8 zGQRyIp9?>jEB#z{ust{_{L6UP@X`}C3WT@4icAhW+s|3#qB(e1k}SOTk7ZEL}BwAFu^XDyF(xw-+Aav28{}k6k zCgs$@(qC;Rph6;oJCd(#keV_jZpG>BD5+x5MCS+R{&EnP-kq*`zHeGXRqskM8hysF zM!mJ+Bh+M>DgO{)6j%R7E@I~+-E-_G{6acP zSRc`{kai65nr}`pd^vz2&FL(dR(uFc$qj{0pAs7=KbSE*HI`NQ+Nfws=^F(V)I6^J zrEBE_K>P0N^EQY09Y!1fqhSXr-x+1&Xa_+yz^QifBt0|$c?ok+?ReRR(UC(sI63z4HRRkPK;f~E?Re>l=2l;Z+}8S(hu%VC z&n+U>qwp~sNA;38e0@k(iZP`KuAx5fAd4}!a-)WcSnJ3)gPF4Q4&c_S?>O7Xp6zCb zCql=G)djvqvt=S!-+5gZH!%Fx1L9FUC3^oO?KLAW%KQLx)XebF0KZ7e@v&Zh@CoB%7fw0|&9s|{mQSizO|Cj<6&Bj3do1PCk%exWJwz#)_f}mc7 z^G>B@kdt5#)pxQA37QA|0hP^45Ixy8`D}EC@iZ$ zsmE-9XZH%`qIfDy4HQxQy2WCqydD~jx)CxE5X%ll{w!wm8*5EoM^7KY7(V@{i1Xz? zri2oMXL#-uPD6&c4`j3zohs5l*0b76-&9^}Hv=;Yd(7K*M9qlQ>HgDPW%){J2?Wb~ z7oq4_iqoxP6z3+r+IH27t!mi5Cfy+3pJNK=9qfJfdHrcAt{qezbF}SbiOF&HK~*0a zMwi|fm~uDI6h=JR%E+i&h+~0A+uKjCiS#ws^Dd6Jz`=H3?g^`+={8fD(}N|#RoB}j0C#)3FEQBylf7emNx6WW!r&n*pb*$H0B=@PlKWj zi^f%7syaC33G={*M@r;qzv4P*#0($?eECE*N1@SWhEc$->MqKb7KxHBzCz9|1Sz_` zdV0K+&Zujc8eWHXHWvKtsM~n)3Kj8G4lJUEutyjGCzpc-y61X(BT%BuG?j{5_7S4^ zjBNG&{Rx#Wqy!0_ zw%Ns-R}Pcrj+J%~36lym{}GE4l$b6wlc+(!-oEXhqJ1DH*rBLWMkGW)I+d0iy&jt0 z6a!fK`pm|Bpvxm}4tfzD2k31%eDNxrbO`wJtaORqPWbh>!_CJ%=u*V|^2yx{(QPS) z&}*!&V$EMF7@D}&#@q1H2$1&G`pc&vzjxZV5l#C$BS?i23T5gN)IJo}+i317=|2OP z=S-RtOXt+|u1QdwwQSnN8T9LUoPv}+D>Y0DCTO7tZASswC;oNAUKH7R&QAn1n?Clm8BCEvxl$;+`4Nlk-5&2hVUr&p0qe}i)Ei7_LnBVj=6sqEV$ z5ibg$KM8D?;rx5jKC!V56%d*{$mnAmnP0wn&u>~k}Sgcb}4Hq)JT7;(M;W-KI!W@ z**v&-WsM`iELpi}AlJNgVMD|2v!H1FpWEKcXhU5z;?|#i33*+DS=ShDHKBB#cxffF zX!m&B(#4rl8yQ*ucEie_ZSBqJPvICxy;OB0!VYbD&4Sfi%hl7>7PUA}8xY4HvCbaU zp6*Abw_td(6K};nQhon%smc1ZssWhqtJOJWSr(PQQWuz}P|pLgnJB&MW4)+M{q@$? zb7!1@H7eJt4XP_b_u+STSKUX(+sGJODUq1c6ky7&H+}fEhWShj<3C&fN6~rsCDpfa z*y?GQW~I5UT;(jyy|PlXQq$ZcDpwA`2~Kz#YB_VDxihzjTXAA)Zqag)Afn<{oQWXH z^PcxFIDU|G_?`Q{zSnmh`uQ0XAv<_ixzdD3k`~b1xEL(lQ8%Zgq)Sy#YK~i6Rr_C#-L8&Zq-%5IvGFhNmOi2k0EYg>K)rUf?626yo z>GN5XuVQbDEsIWa(S3fgZv>jK0Zr)Wy0Seg(SR)1X!vmpy?f`z=kELSh{D!{HYdv2 zRRHDL)cY;2|GIv9%{1Eccy*)e8%zn$aTU zdIGMtL#2mIibo+{n%W&wR6w*Bd%9k|eqJuJ7u8-Ak6;ag9_a#*^GEQ!S0GexhpZx% z;UpB38;|dE_&eiPrx(T&4%Bf>csT1QTsURR|60&#nEwW@g)@76&Cf`jaBg^~hz0r? zA`qIyhqEw%B`q=$kgPs>g?vxdQER-tW$N_sjj^^jImZnW>W0JrrsaevY5;{Z3Ro7U(gZ372hms-StC>6 z4dTG7o>tldW(H|9|6;@tMLIHS-4l`3XtP>YeS2XP-jZL?uYAFZiFIq-v@CR2*)rKzW8~{I(N}50#D&j5uFW;)PWCJV~VHvlW-7FQJ>;^6RX^Ae#n+D~ zivj>jyB)ADISeJ}2!v|>x|e0n_QbnDp;GqN4H46-$Qu2{>aASg9qyy?AhgzH^R0Is zXy=grosi<<3`6}+g%0m-^yn76U45D${>&U#v?RLT#Zq6Z4n=OebvizMJeChYuP@kSeW0Bj@f^OPSM&cU`OBDULlV$q-J!ZJfLYv6m9*s8a(cOBY`>uXk;3(67n9oy0u%Uh%ythEo_X*%PD#Qxjxc|`i z>OF`xhtP)BhvCWkYNG&8h>N9_#pAR$;8u;Tw@o0$?acB$ON*(s-8*J+c^D%fA!ARE zsIvWQ{8k3f`?5_>tFO=;c9N2sRbqlHKZC&ntLj;)ugP_)3#x9TqbJ&CjmN&*+Xs9R zQ|V%IOvY@`sF+UKF6u2jJk!AXNxri^{F}Dv__7huy#cIer6cJf`1~KIB4x}%j@(THtLbSc z#lvP;jMM39^t655Jj52|XzfOp*$B3Lbmm4R&8+99V*M~#5$!e=Bk-yLTzYLDMqbUR z`N5~XddoS>@_eBR+KY*x@2+Z68_}*a#~WQ8*AbTBwQ#-@r>Be03`Tn@K4w|oV3n<5 z|J62ZRh)Ba8dJ?l<9Seu9mHYYtK)V1F5CB9?yK=TlL6fr;LP`ooRI zP7Nk99#DP~%oL~ccSUbFhq&vwU6OSYRnW`oky`vwQM@OoBiK7(1g5z<8(B$Y-<2eH zx}DAxnG_oJca&7%{8PreTv<4~qaWLLYvse{%ld1g8vfcbJT1eLIMBJeqZT%mn!_6? zzc!=VGvHP~x{)_RbG(Ul2hRsO**NLd;PrNSlNy)g(tj}UnANsRI4O_xa9S3XG}+pU zYO0P#VKpzqqYJ57hd?;LQ+fY{JDnIg>?5*HIR^~E|dv*IlhO;5m&YI;0DX8UK71nyqeJB@vpp&xy6oB z=5Dj{XP?dvj~f0f9$VDtkbIK*N08o@{@j?R-5A$mMwl#8h>k zSsO`mPgECoED@(@)Z8`zI?U2B;^1>FaU_sm=>}+HOVQBRGh9aGU*@cm{bnpm*k|9~ z>6Q?O-duWR4_!BBQ$`x>GKq!CC2EZR)r8x_RJmH=p{4k?w-cA!V<(D7Xd3-ckz=_S|aLKuYM|M zV7)o44*Fb0MmTPlZ(N0}Mdb;7hMw<^-8Uk$hBFrSPM3RvY$iQJdv#pAn$Ys(+(3S@ zxH@CN=H~VLXyJUs^R;YD(!_^*a+$X|Qz5yb&7bdJ+V1>eEUbU^5(L@qqR_#S z3OF^fWpsAx*Wp0DGB}TcdMcvG1@%ZMBMR@-cRlaibX8#*obu~=nS50|D$zlH>8KyE z@A;Z=?v5gt+TUXEn>fM3FRH!k*EV@(d;_(dh*>`TEI)Mp@^g9Gs-|y{aLx0{DISo# zp$pb)W94Q!b!;iq31GPIpAV?lXY!0=!7i!uUf9sMKUbT;9i2)>Qe+FcRzh&M&axIP zzv0gYX6X@ne_sZ?_JcL91)H1R{(fAp`i_+=(|&<}xKPRRva`f|JSRm0m1{ukviCjA z(>n1d{aaNJPtTOgRC}8Bjp`op1FHE|;WZ*1nh2O2G!(1utar+4qQZ>L&6;2Qz8MDMB$>XL=Sf{L9i<5q#eOKIC4 zp22Zkshz*@DAj+cTD8CbCVS0oQ^e3iBT_H%p2(Zxu=rYVY)0jLrpUM_%f3Hy0D4=i zn^-z&nl^M=EXoKVNq$pp#cla7(X5`c;5je9Sv)5WTK)imtaGX+w z0HfQy&4$h_rd^DmT(^>d9qnH1k8OqD9e()dTpeUUXkel5N}m7?_LvTlN{R`F7uIz; zDAnd5Q$Ta`TW4;jx9MpH$n*s|yV}^k;CFTHSMsa19%{qp_gF-Bg6SZQr=Fk5!eGbw zFZr(@y{0Y%*Sv~*Lin9z*W1T0de3N|u5v^Q_6}Q(%grOM#@6;+X@O!F`gPVX`{YbC zZ3UnNN(;(;sFfAmdZQbm1JG^Oiw4FCx7iFZ=k{nndmsdD#j=3gA9H^%c|u>R-0#p) z!wOh_leQ34(=A9n;X?g2yMktjWm6zLDDCx*`sCs*_VQApafnvVMOuZNmHi42mAni7 zC>9jIJaCY`hjz>Daj8Y^-i&p$hDl6m99x@ccKP~t%xXzOs|ZM@v?dx3h+bf;I)>if z=EZu>$=DC1L=T2&M#R$6@8>j{af8T7*u_0zUk`=wgHsjM%~;-P`RtB4u(E=V{XqEB zuk;SiOLsIoPhd0s>T#J#9l?+s*obzF{XEm&Bf{Ypd(G#$JMKgkwjs_Fd0TubSQhc5 zuOTte;lgOpdmnch2fT~oQtVPqW6i}MiPIB&BzR^nEDvHO>lY*9arotoO0tVJa(2q> zh~q?|bkpR$YwB z<-_{Q>YJrOlT*c{Ag!=bnq_`wjp`)gpnlPkDY!7h^}u7$thG~XqfL6D`AMna@ige? zG;=AduufPv(^@!Cd+lN7)9+4LA91<;2M`zXXj1R6@;|WR36ITY-=pdHW;oWa=3Jj7 z{c>nO3GSPT)qOS=oNFKM)Vv648Eo_aD->^6{4T@CbLUPh4%)hd9c+!fXt~tD>nA2d z+xZhZ*sS`>f7qn%+h{Ey8^t+*Ns$f;pwRRvHR7s@CTyLU!P6R~e$lSrl{zI#;NwoH zIw1i9o(qzdvS3*t{J|`&>uL9k!_VkzAW3AqL_l$>;dUm>K81I@0QH7>&{uQpLx9?{ z=Q`$TXVsdh%2D%Gw2TY?Qz0j@n7Qghv8@eKXK>OKN&e@QV*;%c4eQ?E^rIwM^FBi1 zjr9uZ!uyMou(A~S9_qi^XO)==EM>$mUfmivO^@0eK$d#hXph&&WTjA+u$P|9ms~I1 z(7ny4rY*Cl;BEV*v$+qHkY*oTazdQPiJ;u=2|Dc`&+T#9Si7|$(Ilx$bTUU4uJU*$ zY1P;B@zZ1zRUIkD5ys;`4y;s{>DjROhXg>J%gJ!Eh|MZbhG03(txulqn=1a7+pdid zahK6aw>T=k2Z%U5cn@%STl86rm-%MBTPtYY19c9~@XHW>hb_3%FT!N!EF{$}NN9^l z>X`Vk4wci~em~GhAMzN&%sQ%e1z$+PUh49JlpzCT-F-N(!mUJF{!;5+6w^H)1bKzt zWjO%Zx}#dLkwf)aV|n&Lm(FmAPw|xdrohV1zkXM$BS2KvWIMU%3CoF&#EM*FIOQ)B zbUfvA+)g&hVAB@D^|}M4MzhBsb|O#xjlY0re{gei6PS~FYV%WiYU4&KpZWnpnLu3j zA+Znm#>JB&z|Hnat7N* z|8P>j`)-W?_3;U;*q~-TGe}oOT;xN7v8|{lH97uV=~t!?;YQPhu}woiUX$4Ko)Jwy zyCvRKOHlaUPjLrVT%LOJne&uU{~e)hLm?{GlPUg6ZGZ)7=BFV{ycu&c9Xq6ED>Qyd4diQej0E5ufBZ%07+idjMKN7O|M1CIPR z-_oeozSz}8cUAf9xJ6PpA52PnC0pevJXCBZmUGR#?zezohFX4>l&wT;?kz=8b!k1Z zYz^fwg$o@ekVZ?|k%*ke@nW57SxE_b)NIm4n|7dV^`t6fZs9(K7Km@gUa zD|Y+1Ld}ztFjD^P-%Og2!o>m7Gxk&aC)OdwX%=B~a0PLZ$$5B}Kaj#k-1f{lPjnp# zkU={)1i0GdbEY}9OEbkUsq^61%(4`I5YOS04el%{ml3wUoF|Z_J0oDnnXO!L+1=`j{Yww4 zO`ogA|2&azaB8GiOp6KM$A<|QA%3=T1q|0JFMX{2^U{@whu*6+;+#{o`5{|olj~e1yASIEOXL-8vV`8X@aG#=Q{L4w zZPL9zBRjzJ-clkWBf9Nje}(QFP^1r9Un;_X!f<$a{%e-u{fF|}>Hv}?#Rw8vezQf3 zOvQR^#tcT?U*+^WAT;!r5=?achjQSaJYHNCe5K!2u?zI_DFw0&Av>?QB5AQk_YuJD z)>vR@3;S)mTHv-f$Yb5Ty0bhZlsB>65^@dMrUQ~lOdysv%aUVwcC^)y7Yhnj>`Zck zoV1YIWeU)Mx;|l?tys_WKTBHgCUC^gK9QfG49Eh6Kj_GFDTi@e^4o#vIyHccsMW9m z5rdQV5f0Rf!*lhW1N)zre){k_nPT2k^K>tnGrQP1z?-DS{(8lC+T~u5> z-zq)5xFd6~B=J^0D-8EBT#M$w^6?gUPH+Vct8N4(l77BBPI zF)i}NShjwcRtd$A>SDL=R)pwia7^Lc5x{oN^u z`t;jisgo}$b!uh?*x8oZ$~&t@EB01R8+5&UiT?1#Vy{~x{t4iXEF@H5$~RQ<$}Q7$ zHno8+r-|*N{*9QRa`P*E$}Uw6Zz^L)p&93Q-Q&*?) z`&GYU5OpBa?ShSXB@KrGI*gfqCc{l`>dKI|XTmQqS=gjn`vg6lp^6E;h#fV_EqzNQ zuA;@;-d464B`QXKd93-aN9|@4g&{c<&-DqXjz>F0&RD1HYUHy2OfW zP22NCRCA~F&tLdmhzkWPbXjRMY9GXq7(~En++l8M&bzf!h&3lg8pzZDJZR$GjS$fQd6*lfs z5}bejGN-l-rmn88X7u%0p;DMj{etSe^7SJ*9@?Y!6+Sn=%{(f!sa5VQH?&(&g8POkPG4nBb39#x@CTNiY46>;I%*#0+ zWucw}#gI5Cby*h`JiNYnu?68<<|8{C3A5$Gue56+cov;11i*PUr_<*aETznj)=9|8 z%}#H8ldv=%0ZI!^W=6gqRbyLR`PE}mAww8h4q37LZ$N%Fnc#J{Wl-|5$X-0S#HS)G6ZFsP(8E%d~ zwvz+w+rrG5d5Lfti;W?>#N-?$ohJZkQivF0s~&x85u7E7o+jB(wT6$@t+u>ZNmLQy zk=vPZN*E&)u!sNSI6XIt5MHU*D2VFuaf1q@PqKyc`1$5q%fS`bH0??NLlo23<;o@! zzQIOKn)uN@ZfBYoR>0zig#FlO*QgcYqF4j;+$Pr_`pICbalO=oja;!yvt8l3E| zT;Yk$GyKxQ{XP-4ct`QH2lBzcUp*j5^JjvgSYpR$=gKgZxG`11Tga53ecyeak4bPux z{vMX?pkpI?GmQBDOb;GtPTofpVr0TIPWrU{$03~G^lxvO6VtxHH%l;~{u*QxmBFw} z?nb5n2k|5hV($ z##{r9AQ)x8YV9$m=IuAV<~}fW3DgX#C9D@*t(($^JKHgGVQ{@xxmqN)T6KGwc^D z--<|)Gt|?U@wmW67F8kI%!A7uVSvv5T>Yv(3n*Yf@<>-~DpK~x#qR!@Qe$EEOVxGU zb%_N#a2+_rl1&pcuxwdn* zvG=Nt7r|^^JIv68AP&k}Oi_kp;5<(I8VSNd%??G~GR*^^V-%ztMH!IyDt2icE!ztT z!Mg$k4e>xE*;BMD{eoRY`Z{e_8U;$mYPY?twbkyDvy6|{1xk$S45JXTjM1KH{_W}3 z5|5_(_}e!5Ee(c&KcUzYnKQ3z-Vx$o_aWPXen2Rf(4oXpzShO9%^x~9Q=g92-FC{R zpW)%pe>YWnB9qp~>FbTy;FS5u(8M?(h5$(3D$GhIN1kB3EsHIEmp|yf-kUVVB?s$CkwDp}h{b#uP|(A}fdeaY zCYK`8=BgWWAR3O7ogy-#I;~PSyCA$?seC^hVuUzbagfCp&Dl-b#nbD+_xGeEBQ;DR zA|Qu%S}N-*Z}5}IgvJMcNk5LOh|j#+MMA7&X&Vw^e+aI{(9t)tAJ9Lsw18vtZY8LEIx4V+dp6vn@dq@e9YFzrx$cD zhu(;%-^MZYi@Q81%eOByrJ~L~N_0q-?Sz|U&KwUU5#rRn85)QoqYb(=P8#CTGtpM3 z+HFci|3GrLn9a#a{XBpq&4j4P6?XYRFPFh)Rh1fdNI9)pJu5FAS@+lzqV-&~*l%P| zps7P;hVcl5ciO&hwjRrR$enmKx$~q@wyp+Cm)`5Ty}#~>nYJa-jIAGEJKN?Q%lEc@ zNmPb=Wa~pW`Vx*+`h$$9Zp?P;?f0rYmvlV=dc2-d6U53P5Mi!S10k&op zxH}U?p5NL1b@|jWIyzQ;_;KOTpvv)jNr&W{^M?s*vro!(BT79db{yQn0*C#paC!2S z^@kPUt8W4Qh+SDw!T1R3SWf0mRlcKq7%63}vCp|}4L{mi;|r)u$dMLwcbp1wX7l_u zJ#DwT?PmNeNwl_jV8cy`dfp=br}dLh{n?%hgUzt)y)-u;cGQxmk^&htJM3khnnQAG zS0$L61dxZ7t`R3TcQ(|84S`-|j4r)w>%;?6%R@-UcVJZO={6ceUG-d{o*r;olJ;i1 zAZG?Pbd}p?unA3v4qJoqbbn7&25fMh8F=g=j9R=2;)Mj=@I^cVwUDr?!i^P}wiyiQ zaxEwZbhVbRR@+X_QZD&s3wIx@T6N)0f4)%WsX+Ubt)A6>&AC-LhxQ+QH`uK^;*( z7mB<|vxKoqj)v13{|*Nm58)GIGLXRGXkyb2bg4y2v@_>(_Vq1dFG2Awd}mU#mc*uh zxpSX`ZJ8<_&Dn#>@T{~1tp7`K6b#J32%T9S{Y+~y*5YOuAg*vFVM%MIfaSLt7hu|g zjyQM)6p5xWd|1+l>RSpwF6#DxE@hY#6k7B{=-QeFqvb8(HJ{ZL2T2LhDuTJ){P+Kv zkGn#z1lFH9;V_)Ywr-@r9O2>i&1-cv*+%jrqFr%8v_xa4y-&M48LYEvyJCILKYc?7 zD*>pC1^|<~1y7;U^^+=Ie<%w2E-mAiQcIu^t5d~p^{V|WAmL!j{gT-b6uDO7>^b6VHjPs5G!IGI~iF2hT;V?-cXIyv{RiR1*h-u|7L{VGT^Z?ON~1mw|V{9)){!Jl6ON}klD#B`*^Iq)|@Um zS7tYu^U$(eRq}bd^;^_yCN^w>)oh8|Z#Y$eixGdTQW_M!gC#=|9(-cl9U~A_HgtA2 zRSR+b&8G?b5>B=8cPuYX04Ny_G-^`l9FAGtl42MDlKljulGmA zovqZvtE^cRy#SK*(!&hXk!kWP@>!hvNvufZ zEkiHdnF*buwmn(a5k2Jib*RVUTfz8%3(MdKXI!)ACd6akJXY22eDdv{Q_PY&GbGdM zuX~YTO?DY3mqq}IXbEz?gKC*_wtD(~Bj(5LbKeEsxjy(!=GBt$=@-p$bql}=cNI_cAQSLsaWsh}l2^Bh7OLCv9tZ_ct znSv%Qt?f#e*(*-D`4U>$Kif|FbMYd2>#a2+P=#dUdBrttN^M+o^OQZ$^%RZY&{p2tDnQ}$`9xJ773zGB?0Uh|e4+_0! zCcO5``>F_43UdEm&Xx)C<2HLDhZ`pmYPKEv+tXV0Ah)^(+k{oU_5Hp?stClVUOORo z_?V5)kNmBwx&r~0D>Zi?-k}>ceT~tYPj+M=?P|s_m?D7J>~#vtKO8w|DPlW^(>ve8yb>fS-qgophXKD>h2DtI0kuD0cCQw-EZ|4t;(2 zIv1+yi{~bqRfKYqIYdg+n6~d@{FMjngsMlKJbZnv-t93c}(w;hA)QdCE$%GWU$;$PdGs7_VH=&cqn7ZB@NTfD8!Ddc5`F5_S@T+ z5j)1^Q6u8u8esb^H;nWMo^~}lM|1fzNJ6~4Pvo%LG^(2qx5YWfV!d3n8A5S;S111C z(0tm6+tOcN2^adir2g&ehDof@-JWFN)7-c8p^d65cQI<_=&@VV%-7?a{Gm&C6gHlg z&#CU2d{odPSk#Y9Ar@`xduk8+NvQZ2?G;f7c~4?|7bVUvCF>P^yFU7gLh|oEkKMa! zOR(pCAKGV}T7!ciS4cy{PI&xXidFc?c+EQUEaQD=PkLAvJHzK{%9+xrmFra1{6 z_4C6cd4v}Cyg(7pq|#NZUff?u@au$hbz%5GIC)<{YbR)Bq|EW&uH(HV$ptEG9mqEC6$L>ihNVME zzi1ZF=4|zg_xbk|<&pob+!5f$8Rw{gtQq?PgQ|N3*##A}RyQ9NkvgUjvVPgiOF824^`8&j(dxJM%Qw;`y6*&HM%!>-l zi1O=2B_n|dAVwh;y2MY7ikNn@%z)6!np0t-n<7U{9=W}_@*Jh^sIs-4YNK7Bj*W{X z?OVrEM;=0|ioqJ4UU+%fTxzs1zI8!7jzwUCO3Wh4SX(}+wK8ZFeSj3~)yzSeR1 zL%H5J?B!bcF7_8lb02>wyB(igCAG%q9KL~z-YU#y2a*-}Y*WtDyM(wny^rt@eJop0+8^_@r3125`eu)3=vPyT|O_iyvw_jwA zKlnQjC}bYvi;YrT!>=up*u8(XYo0$QDI~`?FUUTj_`$bDJJPL>tIdnL@4%S}-(v@3 zf$@x3JI%Zs?FW@g%(h3LCSqy^<$W?m?wqu=$JA&T3jYYYy6JAc@P>THP_4^8!^Rym zagP`)$b(1}JIVKAEoStOv4j1vyz-lEv_=V-1XKKSM_m+S8P8qoxu54Hh2M?S@mj(d z3+3Q${I)eS9IOU=758bHdi}mxTB|F$G>qus5LGeo$qz-i^sNAP$Cj zhc%7ys_aC6E^x85V2haHKo3VT#-f{ba=+2CKL2rCJLsB$iKTlHE-tkAgf?4yWxwD` zZF^`r_{;b26`uy2&47|(1rYsNR`k~Qo0i$DaO=!|3)7%}LO23brz4J(z>-ns4^cgq#<|%m0n{Q*wIq&1FgJF3;q< z@92r=sC6GI`bqdTbKTDy>7X8k)2o;IVuRa-DvwBm;OU3IPFnFvO*Ek$)5A+0Pg~Vn z$uvVKccjd#b9-La?L>akbz1|w0Ug-QMN?A_#upP%3v~^umj=a*|5$uE^`ha9_9|gL zV_W9MSZ&*-<;vD^{9brzwf$tT)uKM~Zh?Q)i^|@w4phXS-rKs}PSxPd!x zX7|;rQrB5R*8Oc4*_T$4m$h7w@VRJVb8`NGcxpn1tGjT=d*M6hWy5^BgBQ`ECm9LF zfx1-vg_su(#zmB;-cj+@E(vd@6E0aVT2cSwc(7Ntx{xprQ5=W33lX1uH;>!sA>1K- zpOy!#=7;tO)26#UPIwz=y31$6AQRc#*f77-`lFP$Mx#`b*(N5fin@MKd8~#pUQrj8 zm7fGz`U6*7)UjdPb_KTJH$pP&ue&DjpzMS3yP*vM10vatT@S;G^*se<1w*~yUj5i- z9LK1-6ZtMOt})j_YM_A2min%D({cvqX~b`@0vgn)TJud!Cw)vE5104gaOT#$Z9OehG*LYy$zS)|g+bOG7v*d_w zXH8T!0M4#-dwl;Z`D9QI@=u6&Vv|t{dGQoTuYIxn*)Pp|l|hfEZd*bnGTtuhQN<@h zQ}E|Xkm>i3t=Q@Vr|F_yF-4$hUiJJ={obCIh@XX#a93$}S#@c5RE9OoxDXr8`_=Yxoj+gYRYSj} zNU@@RezEi+Hk&eTrPPIOXUwU7V2eynX{km>M>M+L?e6fW?4F|DFf=1!{AIQ2e5T~A1M z6ZN01nZ`*2dn^k^`RY7={g1ZCKd(w0i(PNf&X!I;uJ?GsQTmn z0H(9LE*Hd>+Dy~*HoDTLWU*#1DD~q{K_9pTF|5n_2EW8a;0#5ul z_oB1>X5t#*aA=T3Yd2Qb%(Qu5`s$6)_Xy@t;F3spqbRZ2rj3DTIW6NZHYUMxzzadV zRSK!tKqhuR(fRe*-yRd`u+&!9zYiBf^42yZ+W1?pZTldGzcC^@*mKGkWzC+6znz?) zd|!0IkgR?pcAU@yr3U3qh=AFb_c$VWMTSHZ_?g7DZ^5YrdKKG|?sNv1`> z=Y0EBTcDX>_PqGhx`;)WKYvb06$y<(zP<`la#Gu19Zk40>gE4GXy>D=#?$moB+X1gQ{%q3+O zW>EZGYX>h-#yG|q8(W9qyz*hh$1Bga#oeJ5ru4vaZl`3LbrS6?pV_c($c4lBC+lr) zZIP9s&$lIdNEJ7093?#6Sk z%h}nLX=boVCFOkG(d{j=BZpShL+`2+Gd=`)G5Fh;_$t0Do4#kCVEmpDwnAQ5fgk8b z-4ld01mxW9?xJLMowYqR1}>`K=)8&Zem^w{axmbAbKH;Z-G_DcT@71z>JD z!_bRrd4V}j?W-nPCYEDxV)oOB;lV5Ck2XxDrgOxzT{qL}H^_Ae$3|+*wh8X{h8$cg zWmonsMKdVm{f3&T;t~KUKYF@k*ZaoG#gg2}_Za;rV80@9UI$;A%6PzkvRR3Tsk2if zKjGl5F7&2FfqhQjhi89%08vxEX!Pc-E-aDeb&x57c-@UaZSrn)4=nJ1pC-Y@dc|CN z#KWO>Tc(WL6QA!Mr9;7KIOo^l(ji-l| z&Z!14i{6xB+9Kw;jg}w|C}P4P2_C%N6|DM$GD(NV5Cq70Hu@<3``aA3jqlq`3}jN` z!F4fjv2s(>;1R|s>#hw$b2h9fE>vc&a9btv;$&rus1r*VUxsfezmi$5vSTC$F9>_) zsc$D0xn3YwuT=o~KufUplRhL_L-jtyjM|2`cE09G1@trvVuiZr=>G?{x_RpnLcjMw zf`J{Bj@XKy*pw}aHX^TD=J7I{thPJq+L4I8_QOyH7X~qeQ)T}g#~NQqIFGjP>Lz`{ zqBtAGFHjS*rKxsull-i+`VR9gZKwo_ZwoMXNCMP5NUuPcOq1LuJ>vg|EQt0ibZ35sKCDK0^ zIARJ5+(JZ?g3dyd`y*dj#R%ueow?W@RDOl-!cYhT)@Ptmt=pbEJ(4c18H490wsJc) zmSPr?ff-ClZrM@36=qrWY>5q3XMi5vZ9v+Y#es4Xm3n>=ez$Esoy=y@!^b4zw3Bo) z;x}j)uM2jopU@HjMyW*28LgZeN|*4%2jLs}^)*cH@-(eU^!320=y+&Y1M zjgBsU8sG-Lpz#(uJr$PqwKfkW{_bA`LG8)Fvb&ef^QT}Mm8&M-qgoH+#}+0fKSP>H z41^^#^<7+KcAXqrxy84;48tClX%t!u4HSslmFC3|+oARMb_)aS=pA<;4o z`l(6H>Ada|L z3dY+>EEuM_rKa^DYf5w~Br|$wc4zdkrWwAEPOo9K&dNPFnWbep%jCvEndj^`K%Fp; z)I){M(~cg3V%yNjD+5DT_RDz=oHL2XDzcI#v&w?EbM5})IKhhR(3crzYa1t+Obi1T z|ADob*p(QMGQNhQ*QrCxE^j>JPJS!7Uo`2XLn89VH=vTCKd% zH{;@lf2y9|c;pmA70dPk$r%D$)Us{I@>Du2{-fQ%@`!3W_KR}ogQ|6MXC((ak7pIR zWm~~HT#V?gc?xBh3o;zXEnF-jg-tY3n}5r%(e)YcX7F5e?KmX2N4oKjyWQg;Fygm> zR@4;{8>{OnJTkXFVeHy7wGA7DFFRC_0s|kl!HQU>22_5!$MEgQblJOg? z751V)-&rB5diNdc)43Hnhk$|Pr0X{Pla_w5-WFwctm&tQREGA#Sn0l0pShlFf|}lY z9rLrjFC&$=H#@c849`{o^U!Ew{nu10BG)GgZaZ|9$+O&Ua)#lF_osiw_<%fsV}{rv zmpeN2nDHa~`}pFg5}i-6o_#Dly1DU(koB|T(MTLMH?=;w);=qB{XB5}m!oZ-P#%w$ zz_Bl2D>drgpN|;N#!30S(-)|4X+083cN!mdY`d9ikgx@vrO{hUG%zh^2FpfnqK)2L z_!>IEDl&m;`m|u=$NwWVjH=lq2-Vb+uIn*!v+gYP{kuS!AUOzlNk;%!IJUJmS8z|ehkg+_&PD38 zoIUNPz8k^{ZoJax9mS~Oi57cEK`zdk{xemISbYL;(w)yQ=>1ar0LR`xOyETdSV-oxiVHGy zJIxHG4&ETIDB$n&+Rfm_L|Lo3Eu=alAaOh{Q@=PwX|;4t0(YwbugqJ&{_%Ax0i_}A zZsRG^7{U<|aC=;A&j$ zO?&uu7|}m820}U_dMq>o@(=g^LExc9cBCkCsNI1eTc3j-V0keq!29E-x$35%1j4a4 zBT@eq14xi;otD1pq02rn(oXe z98b%3Q6yV3^kMe&EmuMvPtE5<#b`c@Dc=x5O_OVdww6S+_~Na1-bNsE+LC?EAnHS<4? zz}di#-LWy`mL2qy-L>%0kQowKdQnr`!}EP<%6dYXNBsN8WdPQnnrn zg7`uo5tO^Ou~98L=~D&S7uEB^ZA3R`T&m$BZIR_m?WTY+^ zKXv+vSwG%Vzl2Syg#Ux;2%j?1*z49rv^_LZEg9aki(RSOYNLe*%!v~1>Ddg&8Sv$a zTLGHdk`q>`17Ua{Z$yw|x6ft1@%R&OUo!CiId#M9Al4&>^$+7Y1>wMH!cRNNa9Ljx zsk1f3spZ1qoHE~qNpW6a1>L5v>(a&$9}3?RrAJR7q*n#T7whJPU2orv8=^X=Ox&o< zb6uFaE8qlqEciA430;90O%Kr(0&L(S0#TZQ&g0kLax+MRcYcUp>O4{L?7$B%otFQ? zEQ+gC^QB=g;u>R8HLh(YS@lX-lNBI!NLy#S%84T!0=X;ANNRk;f~F1xK$3BaU5aPP ztcJtEVEuGS7S8p)9OcUy%w{-p%h*2Wqi&53c56rUGHBI!?w_R4O##(Ocp;x8kK(Z< zaW`yhaND{d>*6H4OZOb$Azj~FJ2Kl8ntHa+{r%LJfA5s$Ettj4C&DiWl?(jo)$nzk zTsHg899<5@0&~4S?d> z>Vc>8cH~b{k-g!|?i%2pPvE_QM(A~N(0pB4=o_u(aPh<+$A$+IH3{pT3Tfv{0EVnI z|3J9zXWydaAA(#BBWTl6&B0>XG@Vx`IGeiVLqH%KVve-xc( zT$1hk#(i3*S++Dcm6qkqow*uM&dkc3sAR4baqj_{KQ(u1?$pYaB9a49QE~54xl%;j z<^bG4jOTyZTP7KyB4jgoWERV9dz@6#kY``nZ_b0FH`#k?-i_RWn*OoCN^+5gO*aMb)#z>@~ z$mYAu)Si%N)zDZ+bD`y-5tx>{6F-OdMr355FMtrb@@CxO(PHb1iH&AY!QDl9i&MwG zaZ5`2N>4Ub7aei$N=L&*{%omDqB>bm+H5|5Z*2r1S2NUqU-F!m5**#GJNM|$=-JmS zCw95^jlkux6Lhn#czIxhNBpDh2eAC+oB~(-^sn6ubqb!=fmZz_a|GP+f>)LtN|%O^ z_UZyQF5{?0eih^BYuCA))+EIZsts;7_;~QDYg_L@`{HM_>BCGWEX@{pzx#`mloLR^jYMU+;!Vm7iJH>UNZ~d$v3j9E>n=_+|qV>Y1 zvCA(5^!VwrOMUI2vvl}bu+dI0pt6S65zWq#?kr*jU#_H|GvlVPZ_!torf(o;SSrB3 zfICF8TgBsw!zKIa=HX|F0q#cfwO9Q!23M9^ntxVqhF7lJIe+vV3jtcj$PJG6kBGC2 zFzy%F9rW9UH>E8m8nIf)aY6f`Pl5xQCxXzUr1uUIZ9CL%Q?Gdn5#=S-n)?&9?&Yk# zk`n2kz`Sw+8F(@WUMH7C==k++IG_T zkmDyRclw0?`rD7Oq(ruBS*~zU2-g+_8&^^#9sxx-g>p%xckuTl6xMeBtD`{sq%tVCY z+FVx_3XM4WctZ^TyJo=(@xH$&^GsDAi$HD&Wcv>Eaz`|TtgnqkBr~1dg8-1ROUv`G zRhIoO*7=m`Wvrx_+x6Drl;Xb=o^a?=oXGPLzfi}DU#r1SIdK`Ns_bbV823lAB>&Rk zT~NHv$;b|GrVc4Y+GIyBCg7~Xur)!|wyi19r$=PT`Tm{Xqfd2e_Rz-kXu}q!&Ymfs zR>PfH^uA(~p7EjC|M23Nv(mj;Uzax7sz-s)Qj@+JsRy*CYw?VHfy2;3!O{?BO5gsx zc|r`2g9rI=+k%bJ*6=N70rnOihZ{A`Aq#Z`p~s#28W#_?dsbA$) zDwiMA5>~tS>(dkPe_RPy+W4`1WNInaYOeoVkJQ0N4^SJwo17v#+1qXkIrR-rpF^ho z2qg5CMk)cu`Wv;o266L8OQTaqX4(9-F=(? zHTRh99Y|*=3tUb9y{wzbSaT1I&tw)&YhUOKb>Nr$5{-;)`Eogb9HO#c46ugOavWa= zCLX$fWDP{hdEi=u?g$-K@RR?kA}Y`(z3{EFYF)K=?h5yYpnt&3k6d<2G=^*by2jA$JT?r&qy=UZft z+}PC^>O0auun3?r%6BMlzOB9#U;dSlA=wiiMP4>C66MGw02|b zb_xN5yLA0`cl5XkZr|aQp?%4Nmj2Gy$ada)m$2pkuNdfyzc@4YKaSk<8_{;)t?NOV zHou_pHy)%geHveJLDub3w@r5Ny`+n}*CLGR6-%Zvq(=Z{>FYc=+)$m7^fj3GVa3o% z!wh$+cZ8;eso?GLWh2Bw5gr&$DTB^BlvacwEDFODwUDxr)I0HmE00-M#Yy4J$}oTP z+wU`u*Uv8e z=$n`KD^aahVhvh{TM#aIH{vYIk@)~VGh5zk@AN49!4A24%U+tCMTM&EZ7+0|TzujJ z4v6z;SmX6O4GInY1@2E_=DB*eVySK^r>pIrWTn}k%ab+97`O^fqPoCJ+bjvAciUB| z8bdCFz(XiAh*cC2L>tjq1tadccmw{nMcO~(mu)*;^VCOwPp>kpRc?(w{fBMpmw#dN zqG6k_6`RIGga6s|F?eL*gxO;?keZ0Pk$8=HZRT3_oT1>7YxLk88Ru6`oY~Y5U#d_g zc{B&j;E-%mrlAnmh55G%g!$xeF}Ve`!0_kYKX+BZ8(U(dwSXxGW@$0|+rdm1NDan( zd5z1D0^~iawp(5uEaE2QRzzhYEt`~n=gqO0p30fQZlsEGYU{pC&DQv*<*Bk1(lF^d zc76zENt}-ApuU{l6Gc5AhV<=g!3fh)V^1cEX3z4a7;ne;;guHzJ^ZcyV1fW(xYCegB!i|VTUN-|!> zJWI;qZU3}qAg~UqMQrbv(Tm%IMG9NJ_Q9rb*lRNt|IqWF;{T=Z27ZQmY5V)rVHnon*p(Yt-!&y6js+DV zsIBFT3{l@BJ;@CqFw4QN`0QJ_H@HmbBGjCD)v_KZ@{DlP?M&-qK$?9Xz>1MlMh1C*6Fp05lSvNiHWf(=xan$qkZu63o8?$YT zzqZL}-63DsX&#TCa)!y7E~i`4Q9md|2#AieE;@>(6TKtd%7{0T<1$apEX#aA0qdZA zSNP0@F-UJ)`>(Y~>8^&LeXsD3*pwTj{oSN=vufE?&CHDs_wWE6yL3T+-&XVl2J1B= z>M?SC+me}_?ibl?Zn>b=w(jC$Ifvs=wa;Z1`TEPR$e2VV^h{chid0VoB8E( zPAfaI4BWS9NKr}gE$aPJi?wGaC5?>j!tBnSdO&@WLK?_3rE)r48DV0dmPuZ>M6Is3 zj9ZzoM;fM*?O*R@D{_v4{r^rv->;;5N!*w%g}dGwwx*E*+mnh~XXyK1r$Fkfb12+I zs)zF(xp1k}mDtA$$Szs`dOnFaH;{Y`GR$YVdT1Z$1EeRV{`zWaYnlABEhMe8woNo> z-p6X0Ut_Kmzo<~ecp+x=vgRx4ysoVxf{f=T7~2z%o~}@ z0U47vm10aznVZlryDhl1kI@*06ymI zZ0%zxf`ID2fxx$%T3M}v8s%+I#YS>o#ZgZq*7Ec)t__lNZ^1X!&b2&NF!uw0w%3KA zhWSs0{2nJH^&w`i_9VT*;UPTW_L@HR)sAAPK=^ncXK6Z!YhqSK%JfV&C4Yz8_lrW| zR9~lY-JG&il7n0lsPW?ry+i#2@o-mQeteZEV_2lPtD;B? z)zNZAcA~v2ytVR#n6h5PlrRb3ymXTRHJ+TVRk`H<5gUsYo|=g(-M`RD@?idJEDC+4 zVPID?&>LFeoYWy|BvKi<_So{^?t%nyV`_&nm#P>mtJFvGD&qp=?iJP@k>6 z@uL8G->jG*0duChcW%z-j!2s$yG1Icm-L`Hgr?ToU0GGNgOkzkj_DhG3c)k)JKbz6 zH+(u}kDCNTwQj+=#=M|wMTE}L&A;M;TB4fhD{BUOLRyQ_xYv@?Q3GPj-_T~#nKdSB zp*FwTE<&bX264C(&Y)+$j*_gg35H<9J#mOu@cC`y7Plb(Y0^{+@(45$o4EVv8P+Y! z@bHYK&D8CaovS6hEfNp<<_9*mtO47rr~)Q6W``c6brQ@(M#itoWudc|PnVo@1x#GJ zuGQrWMV$o(iw03@W9K2(D#XYF^ac2+_|)BJ)Y}^xmD+WPmXZN?fQ66N(s}}cYBWl3YRQ@%E`TBJd(WsKuk~6FL>DpE9n=;{A}xrEm#o$0EBlV3vCh{SLQ#$V2@Fl{YEACI z$dfy6N9gG8+0xkbSshe8z<6$(HQolwtK5@OKm4ts+%JkA4$)y+ z_HBgQ_Fg|;f2-qf#Ei8cV9D=Q);JXG5YKrW{$gNF*EDjfnArh{5XIwZ^WTQk4Me+< zYp@O%<~#s-sIN8&y4L(MWzlL4mIE{}VPn$2^I!)`j8NDhGj4bgObtheWeG*}5U^0A zeX`}ENw~zph_L|HS*dL;;yN!&sCz2Ucu#){kZN;kU8q;;gj!#l{F-o{s|BRE`-!xxlet3Kd;{`ET zr9QmzzR;%>f5=H7b{9T|gin$LZ@d$Yzm~ptS3tYzM6k*Tl1@ zYyMUMq4FQjV4D;@bN69auiiz9Jj7x=qTsunqvHbQ++LZk^O(@`Dj?Hz;NS3{*&;Qp zVUYB4YcLclYU5eIVXLCnlA~+22<@1;)1SVA2I~j*&u>iJtTM6=zj4Cmb<|DbNmC>wdiHNd6cAv z{1dX%Fv10qFv}0*&eLzJ9oXKi#7YS5{!+fbYg8kZ;TVuS_25G=H&3D8P;>$ldGs-r zbAc4oCUvK>|L4Z9N)ufeXHR_DM`%nte7XmLrM7G7&5(LXXIX)Z5Z<1%S&5YfP+#w3 zxy6kH=8o{o?9tpSc}%w@>G;xVpmX#e*Ln5HT(qiishQ%ft+jS*7v~l6a_%7yDy$hnwmQ|H5 zoa=NeKDve94nQ4^1R{0}4oyIDVYPDvcHxq^Ed?@9P2RJ+dV~N1rhRv>exSlidnLvxE5l+=IL)Z)@uXxZ#-*g?2JceC^yf>i+jkWfXCbDZMzK zDgjKVLP2#sBDFxzOo2}NQ2Eb^w1Q%ke{0oUhrfB+^=~ZN)`AWK*UL9-;M(+L#i$7W z%FPBmuCeBQZ2+uMXcer9()`%_v(dDFhR_rYJD!51KD9q5+xuocb=0i6fAGeWz^lOEbo0?K3dqVE|FsD zV=L~}!a~;_f7TQg+}BQNQlrk_V@F3^seoFk%+e92b$R;p$xx}ZGJBe`suWq<=kA~R zi2?j;#S>LOqZjROD5Eg;<%v`ul~_X2Lj#b!!kZ&K-|}8NC6VXe{3r~~scE0xNA6h4 zPqd8HyR>O_ZaC=cNGseN6QUbkCaYn_{?2-S)GfbsrUE?jdsnTuXZ9a5M-yF|ehdO&=_{7DeXT*vTgI7hvE;Eh=7iCA8Oz1A`BHn;oV8|MrOk8V;x z&D;!kN+fc0s8~(Ym{2g2Y1n%qnx0LpD2RmW{kCt(3@z^LCZy}fKH9(XQ1e6}H%1*a z3+ zkz_p=2(P^jvTw0f!O(RWE!W^{hXjHq8z^jO|B}tEQTd`O`h&t%1`KdOf=fpUmV3Ht zST;%xcHxKZmThK>cJ&_xsnk{RgmsXbB@ob5GU+AxVs^fQ*+96Y)@M--Ww=pBz z3jCXm*%fNBbvdS}%?wY*OP$4xV7&CNCUi0cBsJY4?#mbUKkU!? z%?|q#mlyilBUMi$bu<6Ukm}50((_nAb{CBlaP zR(2t12mfC2HD`LSct4i3>}oU0)!W^^~^jeJEu2QYoS>s}_)41t`j zAUIu>e3SV=*P2{4fn7K-9@bweQCvnOT?^S{#PrvoV&^5Z8{HsupP@~yw= zI%l}Pwvlke&;2JDR0rBFT0-;E^DTGSYc)%R-vtL-;O@q7>x}5PP252}QXFyUY*xA+ zPYkN8FFE2$<9GTh645EUTqJG>pvmr?{00A+oBsI3g^PCvdzCumqX1Pd7Mgm16+`mqPqQFJw@B#6S1?76GZfBx7 zllE%vWtXxW$3Dsjv8sjfvxGggm@nC$zY8H|vM^$^Ej8hV3b40Xwm0Y>PN)=Rzj`oz zy!w>yucj^E)|a)F#TrC_85Jo@0DK#W|4Ce8e`(QL!XNhto`uA<_y^RG=#UrqoUSv5 z74fhk=Ud!j>#6y7+to-f-Yl0xH^cd6&lW`ke=7dM`=2eICGt7WmKR!2VP{%kJrcIs$((43QaZs*0dw?0NIDa_W&^|vg*@y`d| zG3m*3dyh$$Hs6(gFa2+%mT8O0dr8Bw!OcPVE4b@evC~v7TmbNp+*bqI#35V%j$^>d zY7sg|^ou|bq;82lck17{V2zQ^zasn6`o*|-BKa!HUys8Z>C+t7Lr7dMBN1fDu8mnb ziIV&ub5eH|)Bymo(vIb$QhKG))qQ9CFQsp=*uirTuDVI89h9>!k1fYwdrd=C=@|K& zz)V67<6tXMP4s1bNH5DzWndlcv8K21u{k0vuFurpv@K=cIj{4s1b5Ptt;GR7TZna$OQUX|l$C^}@b=6)^b_fw&^ zR_=+>OmsgNY%9rXvW)*AMSbdN;#c4i^IB>aC{{VNW!sCU%pOe`X?r@uoR;pVr#@Vx z)V<{5a9hF6e;K$p%Db#&71i-BuVd2>pJ%(n${jm|&;j{6AIFN_&1Hrdwm^@ zj*fx#QV)11p8F6H4dDua@NbQIvyqO_%ls>D&Mwc6{Uf!$HQ&l>9dG_+=u%fjT(a@} zFM}k`Z%D0oEK8EfLoa&rv)-_3`d>`S-pPd5=#Od2tEuM6-G5mVB>Htu4Iim?SiLQH z_GXRy^~}k(4I4XV;3#wpAxIY->MInORE2h1VJ1+sQ}#nmLErm~S!3gf*G03Cqg(X& z>b{-5t*++j=)lC@Ky34ex;-A7W6LzRT$-TJ<(74lEEp8IC2s_UlH0h8ZJ zDG46>P*sG+uY=O2H2IY`YPY21HS(UfC*4%fSc6ggwA>Qt*mi`dHVha+E|i%HB*o}z z?7FPS3k`*St5otGy8o5<32?t$w$>D<9_H75qa^eM_yUB~4P>X>~5fOh?~;40ECPVG;_)Eu-=c z^MjQGT#6wq_+*PX)5IfBA!FB=G@=72bry=+ZnBHuS3~MUYDG_bQWc7`M!{#|a-BP_Kgl{n@V<-2eZdH- zx4neO`8vL6+?RXlG0}4FlQ_>qi5-U1Y~O7bL{0gzuEP}y@)UsGFI4XNsJ;eieZnZ7 zJ5KSYU{RsF_eu>8hQ=J&CAmVR^W$`}$ ztllK%#D`(D@`COpVBeqoHld0Lw7|DMYY_E?q#^V5*xr`*M>-smy5=X}Q zXN=X&Pc;+*OO~Yy&hYy9*cAwRH#icfn&{xc@s7|YdhIH{7GH8Bmo+GlHHfOq~K9|W6aVugy&dtlr zk@-g07fJQWNTan;X7f`&Px(uJQy^*3+<;kw8*v34|@sOK|~xrzT%E=(Gi0EvWelNN6mvO z(5FGPNiLn6K`tN}GK5xfg_aLwYaIKJ>+mI1hzPKqO7&mOA^163_b;jzsW<_cERINg z?xKPLk#n;gc}kPe)OL7wUm+NAWbvFUCTT7UI5q3ckFqTOf!oIWj(ZcU(C-VSGP>YA zlM2Oi=(8;;`S2qP9w7l^+K*Aox+dQ*?ut^pgYyo;*;I3~wQ7<8ZD4ehr_yh8_wc_5)l)KeOco9YH#G9lnR0)>I)%#?7bGnECcosC zYj>l(4N>a~K`)p0nf<=96dbcgk6G3+>9Ms$`CWpo9+16Lm5y`SkE)lAcl2BsTFYFO z)otH($4S9!4Wx5#0)0`q_Y!hQ*`QWMhT^@*p)Nr8ksMwi`Re5BDb{f);QQc!yaD`P%WF_gHM6Vtmz# zjeH=|+AG6*2l?3(uD}6zT!+^ujczoby*hjKNJb`(`F>e6{zT;HDZTi3 z8hsEJ##uHE2--V3oXJ{XYb_@*6**^OlpqNXps42-!3AV&xa?b&f=;kML@=@fW_8I3 zL$|Pe)sjXY^@Z4H0Rj(5D}{4SzIEJvG40B#9hzoi;Mj)^Q$XKnPX5@^W(&+Qtp3M! z^D{V#9|!{~I%?b47|>yk>rSqzUmyx2l4}XAr_3Oz;7_J0dq2TLX_+=Jf#&W-G(8V7 zTWaxw0E9r=MUsE(PJ(izT)QHMik662-FkMZ^FgZjAd-gAvpsbrkLY~<4NQo^!~BsN7e=cH9=Zte^`vV^wYYHfL8WJpG4nX0h*H$8k@5(kd)mY=lL zu8Wv2oUgxWyf2UHI(& z7Y&^Qg1s|SH^V@vD>&Ier$c@Y&vDgh#A%1q;2|~>e&|<)`s4p;Cj^Z}%UjquS?+59 z34GxkwOuUh;;~Eoom$^`8-7ctWz+IA{gdFKPJM9bwo#d+lg1!^9-ZBb5H36tHMRt) zRmA?x%(MuxV8A!DCty6*K5$niN!}WA5Nk>(F$DYl0&=_7378Tm444jm2QIiUBRmcM z5;g439EoF3vbL5Ggs*S#i@M`4Vc__$G9&es{ol+MKYe1$lDF0bcN?bmjx3fjVDG2paeLNIRxHq9$k{765C0oI9oVek}?boTcJYURBycqZuOyK2a4 z_-Lx}O<&B-waC2SLkRP`mr+>%dsYS0OCmW@@4$%rFXS7Q9W4q9f`h!w!qk2(L;~f~ z35I3!4!n|f_Tro>4(`HiUpVACBD{SnJ1?B+I$)LycR>S1#6l5M6>(xSX}4;ymSR8r zd?x>`*^hIwq>@uEMrQr!J&wa6qs^CdsB)N;$Q~^EJY(UUYfYizcBrNCNOMKO1; zR}Z)6rMLL3OJne@q$XmCNkIIayt<#(aBA*LA`E!o7_Z6oPpgW8E_pmBnw?San@<|T z1fM%;y`LqlYdN17%V=$^N==3cszRbTXB(#uL$7T6un5;bNRIS_u6n6tIPe1{_xR$r zpVSBN=7{JWOAG8QxzL&-b-T~g@@L|kLGwT1)95LAt^}Xy) z9X-qaQmehS0<%Iw$_CFu;6X*31k2%vuH2j3h+>j_Pkp@T5DxTbyB$vc9wMo!)=A$# z+M|2#toK|IF(tAmC#DE#^P{BEIKPz>bB1G*pPa)d_2mPkpOzy-5S>AA;T`PESHpC1 zQkTR?2Y@pvdao-o3!VB=H8?IeSo!lF#g2Q9dt7^pzXLy8*MXOi_j3F}aj~gV5`CaZ zanA8P(Tw!DFWmsG+09OpYvEtaPli0t69tF7R%DVg3R~e($$$o4`~&~_ci$pXXqzl- zlPgSsdNFbixc29(DWQUQC%-akM<&5LWV`h){&*3yp47ObFiz@G9A+Z3C}30Lw$<(L zuL|#|6dpF$dKo?!D6!yNW;8@iqt&A6$qV=XNatdyRUu~is~ZCy4-rX(1~NyY>)6*{ z7BJWJyVKqy`|3+ozqdM;QDz>yBcdjlHpmii<6B81!Yqc6kyG|_@POZx zJe@r~pe{^ZgdZtP$L&Pyg&+n2Pz2%LHrT%wERsMv&iy z(ne4E!eAkgS_n#OZ)fz8)5R-=-i8dkf5*St3+_{Y&y z&ZIU}txKi3jy2r0tSL5$8{;Ny<$0}I@kH9hQj^{pU}Hs?Rz|*?-Mp>f`q9%O zP0BKDZ1D8xcGQ^hmYP=oHsd8j!*Hx7p*H5Yd&j2##LJ2Glnma8h87#~)@C~uVRbSj z-{TwOT@oDrG0*e%noKouP7-mYY3q5H2y8AHkOrHGLD=KI>r+KiUxNB8=fN<0YD!h4 zfzHX-ur(90A--u|P(W%?K1JP{x%=x26hf>YCCRu!HRi|e8(mHqtkpEi{Fy@ugfZVP z_=Ns_fs{&IeWWow+~#aoe8<5^a~Z{Db~e$@w%VqRZa)-f$*b%?CpK}G$3{X8qC|X% z9jOV{kdEFkC)x{QQiz0s{p*7iNG8@l-2j2Iw40OjgUt{3U^Pao;D5$^9~c{X+%pX7 z?|l3_HOtaFt>%aSui`xQOENL9zZazy1p5@H8`6+Ci()s>J<4ol?w^8w-NUDp$FAv8 zu9lV;)Yon|Vuulm9L$^7EAwR@15(o$s;44{uXvMIK7CpT+^NsOb4tyGGpyk~m0Pf) zkVQXHLMhC>rr7A3o~&V<(>>Nm;VDD5to-}*-C|J7o;8^mN5qnox$omvb$P-2)h@ML5?p`wE-_1mC!gb^nZg zbz+@|#?ZiAh}VQa_igSBsUPGtxFuz%$x6G>0Hcrn$7$vwds5Fob71)k`PsbwPkmr} zht?8ok|HwRs*GPI-5HV64Fep^!K&f8K>;g4H!GJsdJ+)|^Coe?85?5(lDzdGs$*HW zT=B1N#=he4@Pz_^Ot{uAiETCVb$xVuZbZ~k)FY1O#lLDkW6i3nsh;%y=*iG@`mN#3 z8H_p)9#I>Ydrq0J0p-?QXU)9|-k2&7TN7$17@BM|TRhX=u2VM^ixt!u{fW+AsbJ*# zk|)B)J#E?sc#Vf@AZy--1)4gVYKB%fEy0g1otY?15G%iCV5?7O6UA;y7%{Z)t_L;& zt|4RWM7Tx4i(TisC(`|BOppeVIK8S-!Pt5%z>vhr4ZmY zeuSfVfpEU#|7KsPtrVQw9m3I`SbS7;5S^ItAtZ`+zsk3;(n8=;AL@+ArLilp54Wot z=kI2C`)RHh*~&ZG)nfTic$$68C%6(zh0V;z6Z&?!V_|CjE1~0lZ9$ZzdwsYReuqpi zqr#_GsMjg3G_QLgj}BlM1*O>jy-T4yQ~+o1MQBaX7`&rI$ZPh^fUiitmU46SmU=BLH0Xbl;JE zGYY4jTqAB3rali|d)_|w0$Mxn8fW`=xql8nq%V22ZQFqH@|Vt548_;i0|JQKB7t3 zH^;;OvXFJRMpDcg+$)zoj8XeC0c^_PlVm8<8gFn$L?`?d%4^o#E881gYJZ1p^-4rmwv;yhAcLHk37W&!Ypip+`Fn zqp*jjhJ9Yy4iTwMj^dEF!O~i-Tj<#uYAV$0c~NGYXCXIttI9Ui+c$GIX%M_N42uC} z`9FDl`anpr*m{OAWHEz{zjUVW>N|g%S^gMU1jzeFL0%=8I*Sx^w2NHcJ3uk5ZBnL~ zL&=0}zXnZhR45`|&$B4b;nMC6PVP5)Jggc99?X29kt>gqRzGo53sJia`?uDt9KZI{}GpEYj>N=)s4 zn}g$89ywMLh4Nm4LnVZz#PPwmUKom{rIva}+^1Ina>@VNK%9wPd6q4#sA%P}{IFNV z+G+5sy)Ks&p@R+FuS6r<#mA*|GqW8B)cVGE6w)Xr>u$ArwSZo8pK$4vwgzekY06Jm0;>`MonUS|a3*7C}((iaU zfq$-Cxy_gGAD1iu_#4Lk^$UfBjZ{ce1un{lyqFA9fw?@xg+l!Mo?>oc_a*z~Mtau* zIkd*o^oM}wsKsUeHvzl0HNc!ZsF0`1udsjB8%gUa-WvHGxU5eW7OqC!zzf( zqn^<&fw`;{n$|2E(LiOH(%x=ApnbJDh8`xVlLt|M<{iTBUbBUSB zQ#BpJ(LdhXAD~shW?+(!Bzj1hFnm{$lhJC9x2PY5Sd{HGwchYp-L%dKxAxeMg-3YZ z^PkRRyx)$jgnnil8?Gedqimvp<(FC-u?2{AcVeX2pIqk(ozv#@e`@IqfBc_j$AQk) zAFX&kxguGZcPj=PaHM;>`8e_=Ytk`w*9qdsXG@I^54whfo2I|8c!fssZsZ zCG6#) zWI^jGRCB1V!z8<(fTf-bU7mQsxM@?IX8$>aw7QoMRiG?iCTRu0u2bf6<_2-0py8K0 z&B|Yhb7@WdRpTD^};QwK=Z7@!p#<|n~L-&8((Dm*+!V!z2#Kd#_Ir_ zWE7Q>Q)cQVsHTJ+!a*ZQ8u(LHf2wG@5;kiLFa;S&nfsI=Nl>nG!3VRcZEa15KwFCZ zud|ZD8ClPl8QwJGz0ghBX&`Zgpr>F|EgYoNYklD2INK8Xj*%*{#-R-r3;1`LR17J zk6~X3Ex&QHC+)~1P2Kiy08YUPnvIJENSVEf@$LhMaES3iC`Hu_cJqv!$&fxIl<2?g#_O^x;Ni&&HaeFX-fypxU-Hqnn%s{Ctmc~85&YvdiOO!^9VFC^KEuXE&C)HeDRIrRxlyX&b zvz#MMA&rF6UFP!(@H51QHv1odo>hG1IcH7;-AOhxuEBh-aeY~UW&BbQ!W< zL?P)mAo|f7$YrKHkT$$L+%E*eIrGmhXaU=clIM~LtCf();5}&NLIdP~ocP4mfzyKRFc81O94^YlcNXHqDJ=X{Y_|sk zHi)tOUV5#C;;Au=?=c|42w>`qEaG>Cu@?6$Yw^JfQ{GFT739*-16P(^i#LSf+}bL5hNR*l&&*Ndbf@_N+_yy4L}4Ydh2|=Ia7Ua|YePwBbGq z08L=23dg$(=RV7tt3o7BmA(nW>dC4^Ot3o~AJHsyw-kq-%z-jkka_zFu1|`*czM3k z+y-(d=Bx;%pAj5UpAch{P0yzM_$OfgHG3GS!UErvcuB&@d)07{TgQn65V6F9(YEDP zt{U0p4WYepSw$oU0(b`BA0i80%&I}u9_l*f&19|xB9UFG&tAU6#A|Gs4u}CXqLTbS zcVzdh}KO2?zNXqL$v!N#mOw<#LSHmU| zW9(V3D@d4!-c;o6GhQx?hFVrVHMfllTvY_Po|M90sZ*-?kCG-3H5?(2>F4CMWlZKI zc+K+KU9rE@00=&CY!`9X7cVaNcslCvA8eQbR92aMq~r1RP$g@agN`Zjl-X ziR9D;1NTMr$E39v;_Zx-^D^(AM%F@q;ujJTJP~TU=0_#;j*2b8ps;9b($M9LV_xDP zb-JSKHSV|T`T?wLU&yxx{27+s0)l6xmrT#@t-Q<+azqfa{ zj&yc3$QRV&ST{K0-={N7{B~}1;-sA4o#VRdpU3*me#dgg1JO?a6TEu>d9u#lEA(qT zb?rBy_HlVu+1!f z)AwXI`mlegO&fTJ)(F3!oVyWTKj3^UAWqLJQS@c3>^Heg3DKa@e;wQz!7J6vX{#|l zedlDq1HT@N=y=%TxBz+|8MRj!?)yh? z$B_D4uLD%)9k;w27awS<(G9wcS<4C^d9n5K3dqI%4*9YiAym>g$nQzgaPWn?b285p zkxESKQRCB0y#?=gh(${l&rWvSu~1mah7b6j7ZH=C)aWLyOhJUimEsOg$c6ew}RvEeb_+k=pnl zsUS+W6oB#&dwN8O&mf`W)H_qoeGu6&Kh*4{{xmgTs=MMxw*D9v1GEQ8 z0fNh$O5XjS`qx6pZK`bKZ29TQ!Zf>}6i9Zi$jWpTPhfp_))=^Oz51(R;d{qV1f1+H6B^@R7hDw}kP{@c-N)k9WdCULD`2^>^@>-!dv?zU8i6@pfxzyNp!ovo8+Sx=Z zE^8s>)#}k3KRS<4!iN908Gn%X8aM82tg!=H`!*v~sovX@GD>G164u5m7n35qN*y=~ z?_m8ruuAXXL$g4LM3b0M8zepxD3oKc3bF4B=WJ71t(Y$Jtl@Dq-mx$Jgm|1*FM!+Y z=iQ(;8+zL152gg_N3%WGK>&HG;!PF1Voo5NAUBRRjmvcYI3Ax!0{N|oKG>+=43WoX zaZQoEnt#F32%*vtEpuB~lf@ORsnI8et^wPE7x@*3Z)*?EJEpHPF)yaCY>WgW)tnx0 zwbdz?l)_~PuZLYTAYBY>VO5j|_CF07o(Hu?gd5gDQ3sc`Ds5k+VNQm7+qs_fd&uZ( zqyOe6z_m_2ewh}XcmH~dkn{$6b#c9729F>jaK+HoQEX;YgFB7igoY;|M<#N0Bp4T&9@t)0{11-p&*Z;h#Y#mOu<$Q0n*$iJ+Rh z??3lS9#g`LZvzkpeXS6y0!y^RFpT`d-RQHLaju_lChr3qR1WnEk@3LQHjN~zosLKw z{cX5-Kn(65&)coI9ktT(w133|_X=8a$$QDB1&Wao$SN+Utw;90cbx-F$TO*yau zz!Co3(}BlNpN$fZ7w|Vj0R3jmT32`ZkK}+lRgTwswY7(->Xg&%;Qx4k30?$6B3*J^ z+W+ld%u%oeR!=(Q-iCXk(os&dR8_cJA80;A}G8N-y)V*{-fmaG`!wo@fiBrg5o4WdokBh$iF^72Vs-7r&4A$IG zdwp%v$5hWsr)dmoru((sOaE>>SU1Qno%xaAGzm3AC=0cH! zxV|+lSJ%yc9GJ?0s812dOLqE3L7;G^mVQ1qoRG&g{S!Qej4e>qWL0}Ei#wyHL;1Oe z_)|ZR|6Of)XmSNTV28*TqamX|^ZYj4KY&Twp`GhXssQRH2ri#!qR0g z^`=R=uWMkur?eTFu*S?va8?*aK?PLI>j^)1Vx7M4e&SDGm>9ZebO=|@H=nr~^5q&y zp*E(g#4e*6Uo{Y+UEZhk(91Ks{yo;Nb063(R+io_;^{VqfA~t4Zc_OiTl@V`k+XlN z!gSu4qQ>ENtugQKg>_1;g4yV%h?^^$)tVnd;p;)AI*l-0U=urCu=jj_WZ0WwXTLeE z$;Dr|RaPb>75{m+WC%Ltt&4N)KsRCPRlAo|3&t1j@Bh;In0!T~zj@yXh^Sh=(G>Qf zM(U`<+l&RRNj23Q8lR*!Dg5M7kIwTlx2U4%Cn`r4i8x@yLYL`0_(XN!d@?yZCgY05Ek6vcpd~JGg@VyCI={haHj97m(060@~*|pejYFiDOwgg^3Z8y zkP52Bx#ASjmHNCBti?!HJRWxj#<}~QnLKf7TznDc53WvFWzN#hA-ng*qV_vm=k`|~ zDujkAzQ)~KTNQLz5VQQ!y=0@m1Ng%Zzo^ead5Cc_`25IuO4(P#EX4a8qz4DG$72y! z*vsSnb^m|41J)c&iwCSswZ6`xRQoJ9W+58CFt;)qxjc1G%Q?srCmtasF zas4eDG;dT|NHGn}XSO^)G7buU6T}T?apA2TzO(Ub5ic%-e(lBR1pn<+=BMTGOWi3iA_PL z`oEtQtGs>QwnZTF{0|>|wK-rhYf;=eN@kf36~>qiNmm1Ap3#Pg_Jbi84`LrDTl{=) zs8!q_BEoXo5P1dAN~FiPgKCC(YA^E{D~EjG=+Ku{*XG%RA&cJ>Uhg###Ci9|noi7- z*}PDIoWu}Q&V`53$3nJUizv_P9|US=LnkJPo_7Njlf>y zXz|X}Eu&@=5tnpY@$ictR)!P!N2`)KZ5}tx!fO>TStqZ>eL;o#MRbHfcxNKZHB=^O zZ6N&>s4d|~JOCv=9$a;(=_Z*&sn<`no*T0b>ZnsHr)kpAK0xWR z=vj+jX%O7K|M;}1$4hr3wwCQRH*nL69lJhmZXEwrW2`EOy`w5$zQFAxh9?i7om9Rs zww#mdfHI_FOKxSlsmhnA&ZaBj=vE{Np~Xj-Qb)KM-e#>v3dU_(*T;KqR3&~0*n#{A z?36c5DFfqIa8TG&3VI)B|FisAa*dk&Ibb2f!`sy?AyX(BsrQUwlT)Qz;euiGsH}hn zvyxx41Z$3EfaHkgm%1%pZzP~JUG4FEXxz*<`H!D`*H1)W=_Ug*E0z3lx8E*)IjzG= zaFT89*5ytKz46!T+@q2>srw8yA1Xd*j*=V39Z95$X>y*Rthr>u?xE?pV>K=sSA3LE zLsEwBj^*Qz0UV&wbs7kRP}z9mNMz@1#5!}Om{@GC=bRzrI-=BdGs<`Hb01iOs;~-= zod(?X??AIiTuJk=gC_c!QfmzY({SeaS;?{?VZN~OZb)@`)mI=V!^$h~RU)id#nAdc zGC#?>XY2}|EUeoLw)yqD*3omIWSZ2!IQn(rf_cLlsFE40RK73SpHERNM!A4L5wAZ> zF4OOo2w5H*C&YWNw(}M z`q$ zQK4@W_Zbmifla(hN-xmF;X@_=J(;|+(~k(8LH+xp(VUSR7&(IR-j2}Rw|2ME1kjT> z+{)Y6^}U;~bh#(TCoBIXdRemuTs$1UCyobc6~8?HyW*dZtnvq3`$SJqm!YnJcXQJ? zDZ9*}{`}3+$;uuwzM-W{|4n4yuM)rvdp!_R-)9Um_Yy@?PsV4tS^=Uw@6QD1_73AA z1)oB~(ScsK)wjuSX&N(<8v^4@%?4}E`G}=mpW~{b63eh%c}{Ob(}GxK3+|lu@`xql zvYA|JgGEMkUztUN?uW(r)H`$L+V(+Pc0p^DmEG!>+UJ*V2{fX2yE>2|yWp-4#Ng~d zZy7@sdnsjJ+*GLtHE#E74oj%s5FZuJs5tkWsAI5;yW;k=DIzR0(MNi6;WZHnv=6w? z(%vrLI;}KJ(H!Ks*E^Nr8#e)}`FC%+L$_8GRZ5d(1>bRt?)?-h?srwn6E^wYaQYAG zU6B$=ZrSF-)}FTOl?pndq7j^0c}*?h{?Ebh-Iq@Fy@R<^>}+0sth9)~y<39oKdU8h z91r)FQY#<6G^}wquHN0Q^=r>62AwWQq)LSTD2B~#x=+zm z%Y)_X##-aExufCV6jU3yXn#5+Ye6!9rNdlSE7T)^Tp3RR%Vme{Ydn@YL-I|Hv%mRk z?I_T1{U_{+bUn0-&Ouro4#EwNf9YC0UsCM^lDWevzU%`lmZi3@9}s9MjGEJSO)`pC zuMbot=WkBdedN10FS#QltWpq{|D@5H^QOG>aAiKVUt-|sHx>+j^ z9D>d%itfT+qJx7UnrrB&Lwk6Ar8tl2g@ioTmt)KV&&zic?Qj*n_%)z~SI8@uq@>lw zP0}mjwT$|1&W{T}HhnEodd=NadlGlG_Vp|6^D7q1t7(0N=jA()CK}p;c}s-ASok4k zWmTt4OHb^c*@%hikA1L#mxsZK6mNi?aJAY=J^k43IQ_(wmE+Dzzu7`r`ono<$(oy^ z0)irxvJrFqx%%@N?WwNVG_xKtx}Ko1_Y*s7jmHbA`TNX4@=xxNiMLDB0Lu;1*!1nE zZdhQk*r_gzlx9aOUOhb3__5y=>3BqU&55lN2A8b4nA|c~Y#@$Sp;98hf1yneElO!6_bFhTdcB*?vH!hU4YVf5ccs|Z0KtXJhERl7#^;c)~ zi>n{6QaW(Rz*W>~VQozQp1DNFaItyf)KU+7VdF%HnF|YMt%);C4-h!gjah#y`shDC zO;f+gd7RfSYJw&Dlr2+8QmyG1zr*it6PanYF!73V+JxRjW3h%|7#?VLNlRWm9ipqz z5d6d7YM|R{m1SXGgs1^AE)wWi33>uNQMZ|=H>I({r(e9yAc*BScJYNGU4 z;=H6=e6}nj#K$3|BFDHw-Uym+_4H?EOsbs+F3w2{QRqbYk56f2-|B1(!67s}P5n99ioklvFF>(= zO!>a*t{lxObZBPCcB;zvZUz5X@a@{gXb${7nN+QS5@McNSPEUlfZR4+KLJHeJevHf zJ73`TfM;TBe@IqF-8T`s6E##X#`o--d9$QVVasHfQi0W*LUM1X^Rc*7xTzCsCa3Dk zhvJf6YKwau#5g;KD%ASG)pRrTk>(OQ^pcj7(E7V&Ju#^F6%PSZf#(_RGmcI^3I0BA zMqJGK#FsY)jJ3bdd(=mF8F7T)$QSjKoa1QN6EA;NzvV$|))*9ixkNLE1X-(t65PuE zhT9aAncseb^2{$OKGMHF2gh+G(tQ@5$E7iM4ia_s_`kHxC$O&+wVQz-<0?nJ=R>Vd z17q2V^rV{w!lXXSotygJ<4dWXocu)0XwIbFs14J<(`apnlU(MhuRcPAGbO;U%VFDl zcUp+yL|2o`1+QEr$U(z{PEBKMGaok_gMvLg;*1A?c>+f2+$-zXe(VgJ|Gj`a$ zG=$9tXigSAmmul&%d0UeZKJ1B>2uQbyCpF~X? zC*HT8>>)VrI-F5F@bCa7Y@1VTjnmS4T-=+t0rakquH($vr%*Gfv+RcwS_Y$+M)F@X z7_Pd?XP?HcUk7gv$5A|pn23cL@-lYt zdr4`MvKxUV-_S0=pQrJm43~PNkKOcl8A5V=JbX0$Mg>++#cPZJikFK>f+_Zj^px1n z2w-wY2j3_A8XIchWgB6`*I?ywyTQr}+nt8CRao2q_(q9+8E)jLWio(KG4LW?h6!v| zQ7HLWoOON28bI;67n|3aZ4&nT!wezmYcP(>G&!tlK6_koCrIbzNREACkp#JF%+U;Q z9cX1crKi~N$q*Mux>Ud1Z=Y_iR$X(iSaPPUe^@chHQZ+LVIJ2y1kHUms?qN>I_|}& zSHa&T_Tc@wIyJfZ}{DtYbgR(#rrwPaXI-n*Ec7~eFuebpYC1R_+e`6KpM+lTT-(!v0)Y@d#39&xg{Y%pMMN(2#0fhe z`>X4{gWeT#3*x9azw2FO+fu~Pb#65bo>gVdD&0So@Th(a!w9H_10^ga#sI7Ae48rk z?*=4)c~!3rb>&Z$UiBz#=VsF2EadIJ{ENR>V$?P_PR0J$MXq61!JxX9>8`crX>smB z^Ucdm%BG=;KINxF_DTLeomZd3HX2j7lM+V4-&cHM$^Ru>DeHAF7tNNhgw^Ahxc`t*Mfk(yKbYa-cL^gRPY-Z6}LCaY!dS9-EV8(7{h(T z8mi3~5&agbJszcU>}^i4JrB5d_;&F4_cCEfW!sRq9bxoh-!E+QyDyWQv-RCN+RONl z+6o^!?DrCtV-FOJU-8sG#K*h` z!&ho-r_hA;PycZ~wVu(8Z5%7}R>Z&-ZNF{WlX`WD;C6!Y^^6B|G%xeon9oz1@? zPYuY*fH&!4I#~U>NN3ZK0bfy{=zM=#1=i|968wpL%8-q5qVXkMh7s6?%Lb z&dFTe{ejXAsM$Ey?BU-z((Uy>D!F4Tg!w-5Cy}?WZvUQNUUBxp6G9dYk5<(B?Ef1& zNQXMi(modc418Ayd;EuFJd%3@Yc3_zls&_H#rqK^2`#ag{dfsV%}v};W7!M^04EM) zJ(sQGJc4zQ&|EIl5ObJlGZTO1BN!=c^iyZC#zP})oaMe=5v6~I9p0X+F}4HM#f0kr zlFTVmzjrC}ugAqYptY*9!fRYl#U+2Aw5x>zifP#onpAf&ffc$&>;3L+C!%prh0^1) zH?OnD&A5+3;IrdVJh53_rts2k<~u)6&1IJE)sIR(rRQ~99v=l5M1y4};YE3?^SuE8 zkMSPj)Gz@kaqZZau)xOgTjS#YD4>;uN2>q5tw7%7QWb`XGwJ#&HS6Y`dv-o+7{=pp zX_`V;&bbE(grHRI#bQ>OIazn6Jbk@<%WOnXCTJ@9HNqS!%=qY6o1hWDEe<>eAwDM` z>iAg1Y|&oh-tM2idie#SGYQ;SnI5wB>EYQkxZ_RR5-VO)zr0twHraDE$8EjhdmfIj zB8QhyXPT}D=C{6W&pfXDtJ!`-i6)oL@VUNX0^iVW9Se4LY@ANZ+II`CPw;Sby(ayf zs8YD$Qyq0a@2#a%38r1uXOo;C+4(X&sMvL6C-#h*8LX^LJg%Ae>vzHnao3kRT$_O# zv|{cmLh*-R>2uHwGS>?vq6ZczdqZ;^a#p3O83vy1CCw)~SFIbf;@71mCBjYg9A>j@ z;@N`|^{B7bBd#`<|G!AUGYP3AZ zh<2&W{WJHex8ijmT6NP==X=?2m~orlNr^o?Pl&v;SD`Pu>|bl6f9+RdY8}&|!1dW5 zA>ZvHF9?>@cE!coT?QJX=?uV97~s1jROqtP7bB>pj9*Fg#^quDVjjX4cP)0FSpU z;fpsXhKyW;wx(#y&LOShTg#MX1EiGQM4)KEh}Gh)tUt)TSgnAlqIEKGy6M^y#^cS1 z|5LsHS*0`& zekQeWgQWvAC9#6dz_eyP_8XUlP=HG*G%~1lddcV_P!F0bK1JF9SQr}frHcd{(MdVT z{ASj`R=z4h2d|#)$gt4z6cm`2q{FURX#d<`qm-vs|v9_ zEZFDhe|#Qwm#X|LRb6RnE6+vu=`J?)BJhh>~ok*C& zV_bYtbP!XqazG8D@t)O0*x0^i0XbGP9s;zgEELt8!_6;Pk$A^5b_*T}zeNd)JX(u1 zUiT@Ndhub=w|SU`IYOmYZuM5 zurP7}T41e!xO@!X?y{KwGo;f+#gP*uQ#oyy(K+}u^UK7WBIKhBB zDbZ0u6BWxHJ^2xXm!~NR5UF3PdVR=s1xbA$uL16v*B0t8C?ghtD)RbqDQrrgxm#** zTa!UW?|x5UKJ{_;(h_#xm)XB?Z`1A`2dbuuL_Qi7M=Lzlng-x#Yrl3OF~%@j3zo1( zcWHbjDn9MnX8`AT_I%;d*lT~DmnwdyZVpu)$21_VzZ^~^tb>E$8&B+?_G7gorc9(y z%a>0j&@Dcd;E6G>WD;X4Kw(t~i`faD(=2yS2l~Oqlr8-_SN8ay^QSs*i@RfGdnJ)D zT1R85H<^pKL&an^2H!$3xMzX4RRcGMWm{>guA|FPBoGK->&vXbV>3b_AmInkQf`?4*ItoW3TN! zwD(xU?%yQ*R(+~KZM-occjlqo$h8bN8zADe{KUSqU%u9dsM3c=4*=}AZK#i1RB#$iH^V0M-C%VKS9X%Uw}|M-bc=<8wB%-i5c zH23*An>gvH2O6#2s`6de6B_FWi?l0-g>p5w#MUY{tlnPemmQ)tK{C9M4Nk`CS$CwO zqcuhzI?RIFYS|9!G{bdXuz&_3)=eN&_lk9L??>59e$gAm4 zgiHUD5VU3k*zm%DCQT1NrvrATS9MV=`#1CV>tOv0<%`@hV%WFDJ2moqRGO0XTe=mO z#<1+sQdUg~cu)kL6;t?-%B#nzR7~6F&zT=@_5OXGbSCt@r82EKhRVgiiXbj#=Fgo- zknNZxhIK`zm7J;(OPQi@%x#CB{oLulKP3x$PkvIq;45o*Vu4eX-_L1IGdQj>gn{ zKq|Zls@kXDuq+U>3A@6#$p6P-tV&M{+y;*W9YcV>vJ)P|1Q*+g^5#Mm@0|9-hvZ8C zy=hkp-9K?XP(Am?`s&G&>dSQ`iq*Ju5}&yE?tH}%0gP>G#8q3_6`F`5fxt08Hp2ag zyruA9dZ$Te-i{VYXv&~vD}>ylBlk|xr(hlRI;eJY+NEzqw$;Bz?p3fy&@tWmLkF=< zDiQ1XZNzgGge!l-%8Oah2%N=>prDQY%}1{--QIV)E{Y5JL!=y9&pm)yyY=uIXn-+T zeWkY>`@S8%DIY;oQyAtXFRwURw2}OC#)7J9HlTAFgPri$zoZX4M-j1@JHeBuufc0t z_5Yl1I?eAGTy{(f+Og;*OF{Yi{xNo(`=l~C87!q+gTmJ$Bf^JM-*lD7^yAnzobb#g z`|~R!fBk>d5stD8*Ne=41`1fuw*~8%!nfwIW=Z^=tJ!|q-OSvF&;oWU*MuEByPA7u zUE~cDj8$rq^Oaa_EGTU*Kx?$9L_P}Gs;UPE_weK4b)^X$LNPW3-w*_Tvqfv;V>oFd-Q1`;d!3P@6Az?BNUgO zM)dI1%D)z5`KW1T=jK*sK?#hPB#gkKGQ?a7Xw@T4>1Oe6Jp zBj>9Xg`Cy5M3MXrtS4U05eQXmSYhY~?&nOiKiu@+RtjD7MMnsZz!yUQ2V7r>Qju0x zw~1EEhfxlQ>KDl?tbT{(SGl`6qbC33TN&?nkto5VZ@=rXijz6J>R-iEsC4N5Rv&dW zquyyFa&s?K!b|~iqw)o>LCVJH$!6`dhz$oG?NKV}ZopN#O*b7F)c*fS1QP<}Kd{5_s^X;>4L3>`@$yDD_=5&3 zKDTpzw08V@*el z;3+DDxJBJ8!gch1c<2S={QW#r|UmOWR-^BO{jh_A1pqKW%n*_fxZd0enUD!~-0Tcc& z95G2O!$#89ZGw#27<;O)r8g-PlZr=UUA4=V(~f6f9f2Cwc$@&OZsoU0Dfe1~@c-T& zt7=r%mR>OVjkYhATOFQ_4Uaxiu&moa15b8xMC0dP8awU^FFCuYJtM53YWBQ{84UnH z8K}_11xfBK!W&jmu=&4MDBuuM8(bs0(@ykzeS-@vd9Tn_o2-3F>O)|@nk)SA!1Dzi zYfOkn32rl^b#%#gc9T<>_HWjkmyT_@@c-jaZiaH)frK+nZhC4u_4#3uQ?vT>&m7qH z$)4UGANs2Tm$~v-F=t>3$^d7a8;!Hd2%*rzSF8%2NzT}@s(~oM@`I_~fKyq)T*x%9 z#Ht>MLQk9F(--(Zq0&4Zx5NW}auW8Bf0)TJ?L^na?R-o3V6CJD=6rQ5HK~mM{3mqz z4|Zz5op6G%J`PweKJO^ldAo0FzaCLAI?D|oFNaPkN=nz5hMqw@BkY1S1;Z{>c@%v^ zyH~cyypOF)4;uTu7_(etlb7-(ltf}iK{r4@a4h9q*Yuy~!A+&a@`z^WJQ(;9=5g203kk`}_WwI3EEVjRhmCCVmkzfZ4}jJ%VY|zg`!D7_u9TG# z<#wx)xg%Bko7PS}WL26j{v3CY^dI!-?k8Nyfvehbp9|vy(yr{`yKBF+5nB{z|fLz3rj` z-m9FpR_9QDrSY?IZRskEMwMXCBw(zGiTU-Yn(|Ta8U!s^Tu|UTEckAp7~NP`r{WKeFdu>Mm%C8q6*-v5L4W46ahgic3t!y{%mBPNu zU@B4ut1?VgHrA*STw*Tm<@`NnigdqUYnSS`CH9x)4Y%Z z57uaG`WShp-wAJuCLCSVvx)@?wn0zVTrNYYF&tGjj~oeK)cEskW4O?Cg2dEoGCC*> z4fh1_Blaphd172_aM5IMC`>FP>B^;$QM>f+M`gqgo`J;5&vK&MO?{Y!N@VjW7T<%Z z>6@bvg*TER;2-~|4UZ>^c;C~S3civS{K`+hXR=h@7}U=* z+d8t`J@fM)k#nl1-=3DNCi~FgO_a56sd#y?l2lv*)5$J~<>rm8CJjKBPW!)avVSvLbA_cw-8gcZbn!J69=y5yyz!swL^>g#D^BC@JO^}@oen3WyB8JyI8=JYh7Xu7my)h$M2 zZ@&0Bxz30B<2*RWs!Xm}?9N85+CQ8uCQ5P+`ABW#$(jnGvm?v9j0Oaaw0i#tdG8jP ziR*i$Z0t=wq%VlR0lWjdh2iI!(o;P{sywvn+OGCZ|64JB-kE1@V3<$f27H5LswVn` zdeVInf8fZG4EFyaDy&hSDQjh}V;vMhR4JAGeDl?JmnQ;@_7`R4W#piR8{!8Bo1e%C zG&b%J)w?IGm4aB~3wvIkO6%Xh0}*PYDKemvUo*VpN)9NM9kJkI-JR!?j)4Y>JWsyt z6kDWi!nj;h@%c^W;}>1ZmlA7tNIf6Pb{Roxr^8%*hYCFt3=KIo`$HQ)#H~8wMb&HL zT&)s9-7H=3iLZ`=?|=Up>kyf|;A);ue~u2W;)VY-0T4pnk?x!0UL}?AM(y+JUGtjj zUm{ASP(sv|fty!{9I`4hgwgb)E4y{c-M@o&^IWVmCTgy@?M;sf^-3NQ!t$xQ1zCav z39LonNdM?-5`kZR7{oz0ar?JkHrFryGo;vkyoN_qfbBCM@?*6#My<^I@X^ywWktom zA03bi4L*uo8$E_~2u=e8-bZGlnTL&>vZ{NU@~^nW=LiWajh0h41$xNgL3(f5}zzXa5T)pbI-M_6)UvMh5S7jJlCoj0g5t~P5xHf(N z@!^nYU)j8`6phGXgA?XDJ$1~wb1qdcpMb9)h&Ml9QB;=&#Ld%xJCSkxR+N`FS5(@a zC2Gb~-4%cJ!?&b5$@)uD=k@;ecM8!nt|}hzov&PL2D>L@1fb*XD|qtO>-3B~fWjuZ zdAIx*(A8+XpcsB2_Ej4|9ojmz>;zf$Ung3w>-3|-Pu}1CSJBxLm>L^MeI|nZPeu-P zgsUO6evY+vnqX1^Zy(k_e;7^v3-z?Ewr;g+Xm*{ zqCS6gikqF{xAV};Kb29n1rWkd^v~vK8VE5jWq)IBSZXLJU|YWbwv%$K=8Li6wkjZ^9t%+*c-Fn@$ozQ%{DarTk0twJH1)=AK$ZAq5Ut7)KcV zR#eosdM!a5Ct-NEudK`z!NsZcHX|XZuqfU4^YHWl-E_b2Jr%tq1IkE}v)1RThr+4r z_&Nss$(yV96%k_~_%lWC9x>-#LxlTp=%Ilrt3n?D1B}fdI}buxT#H)vwR(bb#J85OcobX1nS7vB_(=WbLUj z`15=wcj&M~cgnpiL?^k2v3pZ@T(>Ob9Qn}*0E?jezC|Ay=-td{CtSFH^f&amW>2}{7#WLOv?X1d<|J8Ec5Az<^3 znz9RpUvK{7S}7}DdegywmdKVDS^XvVZX3iOQq!vAUE@U%8@(Ju^-k&j{k^Z}!9`G3 z|M7fr1Z4+^8NOkU0xH}b|GOOla9OTEwh_xd~XjNG~{cSI0Toj(s)V}z-&EuaS64$B>inse> zIW)o1njPew<+qCh=`d%F3PTcmtBUTq+4TNSEJI2FFAQ^`vx=gC*f(-rpSDwJZcdm3ft}}lcbZHco=M&I zA)q54WH@B!BdQU-TgXFiZF}!5cNg_FN*V-m&$9Vwju4Q*GAvN77Q=eaYk$7T_v~KF zpzqF#T{W^Dd9Bz!Lru&$f;9((n~=? zVLP-*aJ!_$`oo42FP+i8M-(&uiLd6@m~p;aIc3)ep9|Sngn(CRfS ziXWaWD$p{Qr#PgZWYkO0t5I_ki|6aw`QG--O2!TKxyrW4+Hqi9oyYGcS+#MnRrmcU zZ0Hf@bfud&;tLG1D7_7ej4&$#8a0JdVRT@&x4F%|ukMFwb9g_k^)Ta5l<4v&Lqyv; zL59G7o!?_s5HH#aBR5-Kp#r^sL7t7_ns2>|#iSHZG+5#MjLZdAAPOBq(+PRI6oHTJ zkBY!FWzWeI^I`twVN*>U+^?LaIW&Uu4EST5&dWT1m1)k3=b{ zt5Q|bJ1HzJxU-b@VL?6zZ$|*I!#8i1nAb#Qh$8>v1BbJH*Ay1AEq2l5^GptVpA|Zd zUN>)R3{br|RK|D`3a2;}=s(jteTz?=PKW?@R9QT+bygNvuW$_g4C>(ze_48{u*tWY z7k`iP#mzhq5F7}-TzNB}E-t$FCEkV(agH7t?*p$}n#s)WWn0e&I6F13zOeXQs=Of^ zvSdu{hen%DNuf_=xyYDx^ppGR5W?K+JlS;!2_A{Oyq>d<@hC(*tVx+(O26>&jhNln z2iM>0zce{e^Ft~q^kB2g9R;q!e(&Gi*E>{?dt(|ZXPiaLpH+Xlmv-yj!E5tOqq|-v zJMMqSNyvaSt++sUntOfJBW~gyjw_-dY-S8I9-H+j@gD|vS--5rcw~I^e%y|}mG#i- zU*pGnAJsuI=l(hq*XKKOB`SXgD%d7lS2xvfmIq8$eYjr?(tJq?`x_4x0}4dw33Dcx z0EZJDjkxvxvU63Ap^?J@w~7_^yZOJbI3IE=r!EJZWfa;53zPAF-&cO{uXh)WG~N3< zS~o_$VAK|DHnIKJy(C9hP1|bGS}o5-{1T$W?u^3bcGu!c42w3Y)w2H&yJ`j`5@HS^ z3;@IwdNk6jTq5GBBjI31ut>E?@JhGaY{Wqv= z#c0GSwosE^C{p#;vp7Vyx7`fR>UD64P7uqqZL3bC+~8E@`eu5gPHyjMZn=7%^=(T? zlAVsD%;-Zcf*nW~@bJV+(X0iybAC*c;c35~9@;dwcW{W{Y*Dq1a;_LNlFk*Vsmh5< zxo+RoXR4~)-_e+Rv1?JeP1?8b0(nWVAC&~fdnsHPd|PEMmGOB zUW@EuA@5IzRxw~S1;$?+!JAXb9zOi1>_*t}-AM6e;*=yR-KUJU-JyjHDM>=e4BzdJ z4M$}RFsdSFa*c(@ok-l_{eD9r_}f`9T(Q08)9f^ z{T-a6ZbeKb^zO|IWpPIe%FBFv`nS{;iR`O3tMe7eA%JY%lqnMBqvSG@G~+03bNX!j z(;F8*6)cL?ad*n0ET6r^z?&*8mxLB)rKpyv>F%;3>vv{iYI6K1k6uDLQy2`0MZXXL zMNK8nn3;OG|El?iW5dPpti~TU%?tnI*OTo^1}hR>iEJ5EyUJuRYY27Tk!tG{5~P_a zvzZm%b^fFFqqE9JtAY_im@qj;KcKYrZdAP2SGVIiu(dI^FZSh)?cj=QRdBIu4?;`G zwwkNY@}IpO3A0(UoVq{QOTsS*7>=Rox8v}d^Ij!?ZEVKn8@ANW&nz4I4M_>Zp= z)d{!LdV+P_$|Hv5lH9=ES+o#8JzG}`^X{XRemim@C~zx!a26_2!rFfE5QT{wif zx#Sg|DULhR?SJ{ZQbUM4Pa&@6i__b%`86Ld#(c^llv0SZeB$E}DMm2M-#`4=;QeGJ z9(aERv=2xb(lrmkI7oYV1{d4n?)HCG3iAj{VhWqW?2|4dS`AR-GATmaV@UoKSU+9lfhaB6nHn;h?)&7wo_joD>V^9v=vs;q%Rd3YB4yL67Lol-FB z0&d0R@&|2r`d;SS)G2<2et|~Au6-3=&?{;8seUZdnoC^$_23i3u?EH=z%v0IdT?h5 z#|2O4!#8}saY)?Keb%3QzsW>8C-^wsPxtH2i6s2KI~9v$81I)|0fiEy(0aOdzCbGF zoBX@QHQw}&lC4ZVCZ`D~h~FyUWT7*HBbdwgH=ord%zj(5I(cUe-h3~~ti|RKoyuFX zrZj-mEKM&Z`f14nVx;WXEP5jZ4InWxji|E5)B6mK4Bx?C9Gz24)XJ#W0`MCwxLT0) zt0NirOCo7FP}qm_3@1EJYx>(^D@T=GPnVuLelg?@pPW2Rg^RgeFQD1RgD9Qs)FM%* zNP8vlj0PNxg8$A3(vm?jOBVO9hLkW{^-mB9ujg#AuNOG`%$|4g*>jC2(YprzyQN9& zg>Op0Zi#u$iQsUH+O-mi`3j71dD^cz~tDuqL^A>ch0jOgE6)p zNuUVBt1QCS8$k&l1x>B#ayP@}& z&Y@crqEAZ&Rd#xf|b7INZGCge3j_M5GSC~R6Q=|)?s8BgKfsz26$IalFNsf7); z7RQkk&`H&5*akBqxhRD5-dC_UlWhS$gq2xmVCp8Y5pFJ9%F;^bgBA=v=O=)#Th#B} zD2I|D!i1Zs7H#B}kY~JS^Du|b=`$ncQl_Or$-TI(u9LF|^bSOkvk&Tg*A@ow1pl~Y zf<;j+w+S*U&@p3N*A;UFrm`pgw4mTNB z+MYzPA8%50NOI4?`q20yCD~$`!uXhg1)09wqAt+7MFLx%KbCNw5+Vj1daeCnt^r9O ze9r^d1W|s$XzRIrs^r>JlTYQgZw{_$(1TEQBvQh};Cyh@DnWTAZVr0WI%I0&A`aXj z7?fi0PN0T9b23=mAM%tv&w{i4*Z<>d|Ce{aem$qT6E~A}h$Z*tI^let;Ge{+9LvSE z#4e66C0lq)rh0M3qtZ$(uXJ>Do z4G`yiN%r1rU*C-d&#JFC=N7#0m1zARMQ7s3^#8|kefyRU(S_UpY z!bF_|L}HF4QvRL$eB}mSPpnoHdoC{dgSeuJXU+^IAInVm2effGVU2E&}s{uDTL6$CUu5#Up z=Q*ZVKQH#w(*EFk&QdrW+4%BG5J&P)k{s0~*k&I4;4+T}II@UGgV5@jatx>*Z*O(JgwN!MpI@KfZ>Kt~k|0>K&gpP&w$MNT zMAu-b-e&#`bfzS49XQ1kbkU@kvzNuARpO1Etw$ZNb?ZqS`{KB2(efze*^s@2?$Q!W zA>BT$2fT@3ORPPvtz*T=XR2b!Ua}QBX`0r*QKE!P4BbZUdo;J`{DBF7PsW%CJw&j8yxt+|4+xiLcl>G*A7fkHGZd+Z!rD}wIx3&y`;izke z9$_R)AXfxWj2Xg&-Jnrs!LK>TIsJhIRk~GFKBKC2`Z8_{?N5qHAWt+kM^4@}MwA*5 zrp`T=s80I@x$H50Y?!S8Y~Eca86<%s=fo7fWXa`YQKD(>c4yF&6{%NmrKFd7Z+Yx% zii>>Ax2NN%uzCvlfHfdKk$XQW_zR$vUfQI#Gpr|ZX}^f?kf#U=&)L`0e$j&>&1yAAxcwX7*=L3c10rGhtA7y1cuOZP@dg!CJFUE;<%4OaC&UGK z9gH>W&>l+wSq(IaCb=Kz)xf@l%^3fS$) z*<~ltyPM!=!&wehMj{&}s+&dgqt(dSupn90cnZsQ%pVn;NU*%yuTf!V@_d!k-VRxJ z*;n}%ceEX~fxO2k-`mPqHH{jjVr&$Cv%84?#G->^tzm9H^q8ia;z1B2(x`3{p9UF} zEutm`_1AdL^G!Cljb>}ncdJv=%!&7w+S*%v-)!jVKp*QE|~*Y0|>e zp(q=gIw*gO&2iFJLxyq%6uSPyKSc=u%8yN_GLJr#XqvTQ&R(bFF>rfb`41`DMhvaJ zF@!gMT7nf`S1e1Jb})8LJFj~I6(AMzhSP05IohWGp_Dy#=1ocvUS+AzHPL2%3w~y; zA#nGPiK(Zga((2+HXvluwWm<^{&JnbEXPzc*vge9xgr>`wW|FeZ?^Vk+$84hZr>78 zy$(x@qcjhF%~&r0PYx|__;ke-SfqtYybN#jH3*<>07OC{eHf1|&Ai{K4lI36?H^C@ zLqrpmm`eosVKm#(Etes_I&E_m>zS_mK)zHEE}^bfNVE5BJq|d=0uu zbtdG(J8;I*+F`N5db)skF74^(mmI@}gsL=m?agU>jLZbPI{-3;?d4o*b!naJ)pidI z!!;QOCSzPBntb}TF`))y)ubrZ{zCVk#q6#)?~fz{solMD`8|R2#4VlLuWco#^HM6ua9OCi`kL=|F6tlfOx6`uP_f ztk>bITdCs3(|k)8ba8qus8*m*+beuj(_6Hyf!z<&YBf>`r`wgt%O&91miIbw^Vjj# zz-awtaB&>&>tLGh`@?Sp)#u^;Iy^84AC$&7+spOz%v5ktDro6P3XEtvT4xRe+Eh;Md?|%+_nY$cT)-BPVd{$z(uX(xrzN zmcw_v1G7&88HAm41dYQaj)I2-Z@3WK3qP3ehQ(lUp2$ijOte)>+akw%>N>l9w84UN zQilc@ZDzqA5!S_qSljj}nGEu^U^QyoM^|piA8vQK8NujldV1Lhu38V8F8_*QQSd{fU!9+Mc{w4KYuWk(edl~woDufG?p z#6a$a(&0cV?BtpyJub7|^BZTkrhKFI*H%~9$ZRFDqg?wi)_>$MPY1{zB1n%V$+0{= zM~ywLFiD1vCpJ)5e7(6&CwKO3q$uYJZfZpb2<;;qDU(i(NFnr6g5juw>u@3gWEF25 zoO=09)Z{#?^^IggO5J?+A=(u)1Xm=lQ&dM-c?~+J*xN&j7iJ{b7n7TX15t}0+co#| zxCNB1HxmDH<(q7=3qRTupv!MsRZUaf%uAz7 zMLfbbw2Gm&SaXpgP)}1?i>_L%L9X;69a!1au>R%JGw1&+N?`-Pl zoV736pGXd*)R*AniI3!Y$;WjIBdnBFpo#I6S+8s^wufrj7(W07z^G?(}GA3Mvc2p5n>L9OX4(ilALC=c45W8{o=+b;ySc&hQD5s={B*f=w zmQcaE52$Jr~%hkauY4aTJqVZi& ztuZcIa=Lztx51YkaJW=&jb2x?)QI$Mp6 zTYh`vt$eo4_T$o0l~1GxN8f6-hVd7SS7%NKJ}13!vFg$g&JKGDfV0l-pDi+!ZDQolhv7E4oAIl$@M)U6L=3!(_t3!&XN|SI`Te3%YBuz0_X| z7FQyKetcAcxtu;c#OoWe*J7!{1L*p=lYqEc@zeTGiE0#pcQU@iJy_h) z3eDu{mpDZPUSrwAyGe!{>0mgJ@}nveA+#zh7h{#^9pBSOfqO$*wx>}K0wlMkYN49s zQW9L5I%TTfvBQsivXyE2No_L=%g@9@=efdUMQ%!`hljxgp8o+}0oq~|+ zG6Uy_cZyX@*I>f$U4tc{BM?&5U2g9DW47Z~wN%}ndiypt7tS6fz3LaMx>xm2PhVa- z3DvNzbd-x{I|G0EwxIiBWoc-1IZfq-(@}bHz>EdwBpz*yaJC?i|d3LDG~4D+T+g`QvE(cCS38QGbbGU61kIze=| zn*ZvvX%ui&S8)ss>^#%qa&E~T-%c$$n6yB)g#xLr6L_D_OPc<I;(HSt;iOPiKxW#!Wre*uk`Wp_BnM4%4rYcQ)NnI~z1wUu zq)kfN$uI}Q#_tozp}S!v)quvu^3B3dVS4r&0#EAJKOFR4#S`tE8n{ecn}nqFm_lh} z8)MP1d**hAkX-Anef^UC5xDI9n~vP1OB+|*&v61_v#|90Gd$wMWFvEOhH}XST&ZKq zH^lqZKX*yWFO)jE*_zwKH1|o%Mwfs@OCb>t$ji875_kOPk=V|?0Mb4n9NSb3Gt5mg z-25?RlU~On-rN1P*84a*O1{`u^(9fxZ4*)2fIE10-j?ZoNFFGTa3K-jm|{sh@{dui zKOr!jVA+HHf@(P_S(}jy@0o-r^(geYlL9CYQcDccZHftkJ3M(%yhm@S_TsOp#M0QM zbt~&0Ryfvw>aJ5UDd02>qZv1`q8j<%HO4g~%n{4TF0Nl|s~&HTqc4RbDrJjns69F9 zfi!KGwdCgndHPb~j9V4NaYJFYR(D&k(j@2j(p{m_RO7kAYUyI6ng=qO;y&OK<=Y1~(TGqoWW?fuVGnUgF--5enZ% z>VjkJ&Ysv%hz;4xT7t%(v}AW68a6v8o4Ml}wi(vXabML0=wy&`1KuTNpmyh&O;Gt4 zsE*q>CgBab%-w7?4lSLkH1~GeF<9in>zk!{KlO)V7ZBqsRzNyl%+M<$AKNx9?xLT2 zAynXElAdQ+R5k7gqE=b-t2n;4{E?0Q9f2A0kmmRj=2=op9;xuewnjIW*65;L93}Aa%?>Rc-jS_@CNX|( zS%N>^HJlNQHZXIzr?O_em^9rB_S(1|@G>@u^4N?s4jaY}U!gw4THKoo)jMxk{k-ms|(ddjAT-Q9jP z!M1O4+&R|K%8d!X#UyP0T!5F{B9-VDX9h|O2L5J!=JhsE?|pFF#nqC$wE;+@sO{fY zG7>L=CVyt`%Xgg%a361~fnebZY=V@?ZM7X;4gPM;G8TEUuaU z70|I?9J09En~WE>Eq_ zXddGY&@fYu`?Emh=RGKntRN?k7|(0nMpf~N3%e^|5#ZCLIak1JEk@dWf5hbCLUF2~ z{@&>zgd}#^h)>Ip8kY4Tc zG)}l)4Vw5cYWKshv*Qj;hN?bW0rV`B^Rro_5uOSdlEVXm?|@Y%7qBz6q_kfJs6^8^ zNHf@`*$>Qq`VQt4)@^<7QXh^J8V$HIHR5c@-4bOAsJ! z&5kYZ6JK9X7VE^m>|(?Jx93!Rs6tJa_RTk%v0Ul$2bM( z=N|;)^$w?ZlNT))?;Y&*-PrSKy;f|DQ>av>?7m^b>_ijL&$l>zKkLtfssMhPkL%>X za>OxH&An1`oK_Zi@hW(ya4b~Wi-jjZzaDAz{mUhiVaj+GQl-!`y2+!5)r(R)wi+Sw zRs@*7h2TyqUB#r=uf>3Xus_7;_>@oV&YE2T^@ztdLW7V373|DVxfyfd_>^fcqmHwvJie)wG$U-L;O%9fK<>7rO)8&<& zXQta&tmw)T*yQt_%iBW@CNq?iE8(*Amy;g27F*tICL9+;*>@Jbe);Iw*rna_;U9{& z?%kdeaa~)5gVRfo$Mok+mG4l5!$!yrX+K4`qr>W_?NO&I;E>5n<)_!f)+UMWn{N)> zfYyzNVdbg1oxCogHCW_=<2ueQIVMNSpR$g9SZXN%&a!z}0_82iC!Nq7%5k{k)PG)X zc3I!9>K@2;* zAwtV{9t^+sD!DqgaO^?2)p%F`R(!pGInEz-;ki*h30fOXuGot5MoU~e8vAYye5Hlh zl8|%2cfzdbo`tu`+Hay%dk6hHGT)@Ar#OC*1)n}Z_7b}Otbo+`fGYxg)`J^Pwh8n{7Wa6tm0sC7> zN>BAE_g6PyQ>qTMpb0GX)tnDJ9{3`~Qf!?*Ue!ta6m(Z+u>7N_8LsNLzX+=GS{~|v`q1H|$j|$iGH*fUb}XCBQW**rTQSJ4*CO^{n@D7A|0XQ}QQd^Ga@UB$zu%?2J$b7O}Z)P1fN z=|@>-k(IxFjo#nn92ygh`(()VB7U4BJ9y{9z&Tmv=(@#hM`k+6V@nX$ z3n0fvTD*Ypm3$%OM62|uOOjw%w?r3Fb<Gs?Obj ztmmGavVYY1iT~qeF24CE=9S9tL2jQmdC-_qgM>xcoTW~rN1~9>=d6ly*&1eF#_dyx@_RiVK;VY`n;);bpR9nkm-iLt;J~ zOY#>@EECT%u(61SFeQp6l@2U%MafRo(^Y|^%WG8I^S0~~RGKH0h3EUWU@ZcpuQk>L z?scmY^ELxXTlNMrX?@3iAGC)6+uzgprn8tvap~Vn&nc%W?9Twg)FWQ51cyg|4)Q+F zgV{Kw-@TJRK%nz48 z@;#J$n6^>7EuU)Z0=D2`Uj30-ts_axt&_G@T{inBwb%D9JMk~i%`KX=N)ow0&;Kw} zdjj^;{)GF~K@45YpX}&8Dbea+p+>Ev;ih|q>fLiX)Wo`~paJ5wZ6=_1d*cjasZb|+ zb{w8nqPh=d{_6Ljx#;^0wpagrj`w^7_F0j~BPRlx*k{%kG&Y)5bjTi&&4jB%^^m;$ zygUb6%J`Jy_ta^}tJpbZ*)cM2`%-BDNHjodWNsvV8&LQ0?G=pbID_Am%-PF!O>b=( z_g8Wb0%jEuN_Rm+Ko)*3h1W`B@w$1Ba#m1ZHW3MrlD` zd-(Kq3Y2Np;w;~~CMSTdxyEoZ+IT0q*q+dGoX5x}x9mbAeS zdMgi$DLpPxPAAY;yQ>l&%ld8F8grj0bNT&c&gI6dK%4}de{Bx?OD9H{FOs9ic+?~& z=#Z^-kdjpwK^^IAzHDw~I82*Qx))1F0n%rlwNZzg04^aO;>r$zfOlwTP9K~*Z6FoH_jmG@$q!wN!F-~lI@W7>PV_k{?% z22xk=PV{7^6R5%1y5ClrPMt};fF*m;G(jF7Hp0RvlS+Y^I8EsoG#6)tCgwlTCuy^NpIo$%Jk){>C*=yJZze(CknERG4pqRGrl~Yp{Hd)%I zFjCP~zTeebtx2PQ1lR_{dBrXoi$jI&zP!$1ou#>Q_PLUC;;XgDI zG7=asG@%}T+ItpHwuheqq}+$E@;kR^pheiC-c{4UFGaxH{xSQ(sH0wDoU zp!f4Sz0;IYog`C%0(sjj93dB(EzsbB3pt9qnX zgh(e>Go_x7SVI^8a%ruel;Y{>BJTIPx@zlWqVU*7W>J-X$<>80N+vxQoFQu@;-5*_ zzH{W8Qg1CZH?C{L9ADHe6ad>8sK(NvG7D>s;dtRZQ2uMf{ogct`}&Iql7Hk%o0r^C469dLT{9II^_{Yx$#dc^ z`^=*>IbwQ&lCs;vCj0E#UKnsN`=ccImxg!jl`L7u0cm+K5B!YK_M^8sk^ef@afL0F z4-*+yAy3}X4tK;9+eVvOU%G64dm8iAS6{AE=Yf({)q+prFKX=Q+MjS&)YSB7meAsBYE`NNAdztn4_Mh32>!{DDpW1o( zoL(f&(ljbuWKp3TV%8b>1E20N{9qp2>s^_<`i@+$8MWmR1rvf zhRt05k_5`>DmuovVk#Osrog%ZToPyfbw21^P(XOj6VG{0tI&Cq<-*>S?;gGFQ}*kE z>{Gr^8~BKks4K-rP8V?L56r8`Lb?y0nPPbZjH97f^Of5hwdIr?1l zlj&07VAGV~a^Bp!{DlPbdk^kIc1wrc_l=J-eQ!SoUY9FZiQ<5Qwg3M)0EZUyY9H_D z@apDM{$xZfq={U^-H`dxes|VTQbv0OK-T5QOw19X^E7HPwJEH1YJyo;jH^jI_EoWy$I+56FXW=% zJ!;ALK~WGY!PwTDg<_)Kr%@`DT4ATx1kc*PszJiA0a3|R-Tn7pk3WvL7J1?+`SkEh z_;vk((rIy$h=vk7>}tN2-|u(SWN=aV^>mDh#~3XP8?>v3>x{t zswLHh1xeWM->}NG4rGc4fCVZjd{qg+8Sh~m9F}N{tx?XfZQOW?j)$3uzg)hOH<34; zHp`mybsXBcfhnxOvfgimO)^zq&N#Strv9GWT-~UPX1Jq;&>c6K14+TXy+PBs+e9A3!=a7v?wo18!z{NK zH9!Uhza0wr1Ll9B96UirgHWW)UoM7BICd_lP!Bf87X|;cGFrIm5E^PdU3p9@z(piM zX0#4989KidNrye9wZExX%J0o%s5QYwzGsKU`FOY9G?ln65wxX}+R3lOzIb$=?;Szj zUHjFnbD^Q%`%E!QqlCMYYrmJ=l8Vb+#x8=I6mo+Dq|im%BUz|qXz{Y=A&}8T z(;iX!>Xa_7KY=~`hIjA&IPzTf$Keued(CX>hWlrT>ol+ocXf!=q&s}b6wRm_(s2V( zPunuyzzTz!COLn(9$*~L7guN7#n!%5^BE4<>eF8z8$e>XCkc`s*+=Mn?+}Fu6%X2q zu-;o>))(95L*)D$)Tz_lA2O$@R1zctR0@YmO~SqNLC|eIqS`roP@6>HZ0x5Wj1L=p zTs5IDt2sBqhr}<^8UUF)TVbYsMDcd{iGISoS$(V$>Dmk}OP^17XsKN09QO^e;Z2CC zGlr2)W6dJlJt0aKRrXG88IR2-v>R&W+EsWypCW(Q6H?b|MVPXzgRbs3qN-6*Il~w} zs&OXsNuG~4>EJQ^->HSJp>XfD>{gi2RNP85b1-Z_=( zE;)>JyBm<@*Gw;am%o}3QU6K+T-oNj^?d%t%OJpkq$T%z*YpHqvK4DQyLnNrqkZ!R zX=}b5Xdi_4fos|!(T#7N<>zYVurx<|(p!C_jZ5g)S|Y=G+?Y1k#WD@bjR;3Tt)8+a z(7{1CR70T7%UQ}<&X3mxANFocNTeM^B*gAujHGFlkLRQyg%me={Oi8ET0VVRa!=YH z(D(N|D8@6yvqn6bh$8bbU-sdxw?+p}2_A>HO^=RGjJNZ6RN$7OhJ*b!z8yU=kLz5EM!teCa#mw)cW*pLU!uhZt<_8A*j57}v1%h27Lm_5A{~@bnhXCoj(TruiTF+Z zZ(J}bckgQL+yX|AXC@|^XYE}l`9H9%UU&O<;LW|%Mc=9Ex52G8R zwNd((cC!_cbEpd*RzA$9d2?T8HJ9TYdplY$+R62K*wWs>W<#0l*Zkfh@ z1;~`pC308st3CKf#g$z}$^E+EJVEfW9d#*elEx*;q`T>AQr9!FVl7{J>ozUDI07qc zV$DdmaiiO@6qP2Cp35&Tw8K2M53AP0VC?^T8cH$Hvi>bWGX)EHW-Bwk3?N&Uw8VR*JU^g9KpmZL@wKcLU}SQ{M-@*Z7{~D30$G!{7l$HO51XTlA9sq$!$?-{5x)XM?ug@|DO2Y5% zf-&3Cr|;aRk93wgRFEQ(!2LOhc>U! zVIOx&U}rb5o=3#To#WLcU&v_kIQztIlotYEOmRTbbv?Z2-e}BsTg(!=*!Z8T(34C0 zmB*o`Pq-cA(1&pdZa9sy=T1wFE1X0Va`IQYFBVU@PHi?s$q+T?6Q0PGW$9g#gZX7w z+vWKqSai=l3!wjU-W-=`#RVpxX_<`M%dlEqi&BJLgFg&$I(6}8I~Q-rF3>B@r0t(2 zhqvG35s0el&YoR%cD8ysh^P|_-=&Jz??aQ5Db_@E6#zdkvSDltS=w)a;B;O;s}!_{Tj2W{e+}jKUS^fI~QPxb^`o>_1?c)V!k@LYTYtWwiUjMPa%33 zYfJ$D3W+n{q7+lg>m#EOz0G{y&!|T^>G6Kx@1=OBI7z)Yh4K5vMCHNv+%-&2qj4kQRlMb5B?$E2U6k-=a^tm zzD!tWzf|;Mxzu_h=Jx0!C?HiLZE=bsTSg_pB|>7lom~?-EJO)@ajl*I(OlmwrYP4& z3{6_HB-cIjzl7GXGg9SUeCEjHL%$$btHv)>bSaR0*~FF-_FYknA1<{JqDc=?b$#0; zW5lV}67rV|9!Ms+D{SpCO@41O;Yze+t#*X@Ph;N`-RMy&KFuA7!C4I|-cPN(GaQS? zgzvLzFO~SJR8yok6~bZlI(#8UQr50|aVbF@1$4yPr?6FT$HiqMe*_+30fliWym{JB67zPPJmDhw|z@J>zPmnCq2;?oRpj!>=6Pl`-(?rF#1Dw3yC<+Ek@Gy7JLQi@K8Mww=XVc;+`20{C}q9?u%^ zsdsK5vVET9J^t^8p1u8&E7*@U7HVEpX7nPy$Y-MXWzNedxiAJa~it;Bv7;U<@svTT56Sj_x{FJ zm9n1lv~0o4fGCL3-jWfHq2uSTRTCWn|B*XlBxUw`$)zh-uY7j9?0bamxxOZL+dc5c ztE$@roftJh33GzG&(y)k;feR$kAE|uljFOU+EDkJQrvk`%jjNlC8BKHO22EPT`Ixj zWlqwTx{VP0aKvTz!14oD+ZE&|cN4sCw2&QEl$I=ibE~JMTai-V{_W0er$=aEs!)uy z_O=R?nFjw^ygv{Vm2n@xhoxb=TEh|=?)7uD%=XnN3bkbvJmqSV{?=^&wA(LOns0?> zMk4cbJ`PAf8dhutq`LtGsL{^c4=kpZ5HDzgho=T0>nCRX_llrc15Y1Ca@ob25m?&N zjCYuTd4Q9AKDd^y-xJ%ZfG5_ugn}IJ-OJ>T?dm}MLs!cTj?a|V1V?50C z;<&3wWn4q%qU(Y0D@$0WPKfD7*-|%Bmh1brfTg8r`sd0G`_k6hc2UXy9nyLS-a21eyP4!T&czxwfktAPh zf zV&>vhX1Jvlc_@2VVUf6bR+@~)fEa4LxfYH#YPX|fN#SPO$L#=-+S`cmZ`9wf;zm`O z;aeY=zOi`;Q2eJ_+ncA*X4Ut^V&*)^wT%WpqHbqe=(|BBJ0Q-=b{(_)AiyuMu-10N8AEdWGGM*L#3D$6 z@!oo-i&R&C2~{%567T=#Rnj74R!^yF=?L*1G+1)wzTesLD!XEK-=9*!s^SH=HS^mF zQW{vNZsbhU;iePS6oY%flc`#%)Q#^ZcZ;X<+viRd12QT|_ZDDY0{sJbF76fWZ%FfS z+cd!7oP;iZRW3Z-=*|>EEP$Nh6`SkX_ zs#z}H$M5Q5&tUDxt?oA+Vro91J){sqFPP?_bfO?~vVVP#PGYX3MW~_`5>2}Bev@8% zw?;5vVtST5%gOT$8r{QvKznM6)K^?3Rkys?NKO?AiTA0ia3FoY;kOOf41Q=i6?`Gk z9zAf0__HCZHnT-pq59Ekg*KxyMtqCn@2`I3iPqiSGNeIOnA%>AyNJK9Vo|^r(~;kz z+y7x{7ToP?{0-ExfbxroWAxM_5C6>W63cDC1uxPQd4q7>#r{_ozJ{O?&xi2;%XK_l z*uz1YQ6UpmetUQ5r47H;^@&;7EiR?YR(){s`rYrou}-pSgKcLE)O{cJ-rfk)3+dep z4Y+|xw342j_MoX>-tF@+k$bGZ>at3xw{l$cSytr_=2#en??NS|`sE{f|)`B(-J5W+11WY(?2 z=_CJIC^#y}B(YMI1(%wYM3dJ>^TAWaA6zEUm=xsZkFf^50O*#o7X-ae#8K4lc4aP){uw#E|i_6{+UAkBCK3|3FjiR>!}lPiAm zrDNv5NP~u`)JtBfi;y2j8^Y74l4#AnE=>oTmS1-b2yM<78SwZmS7H6Xv7^d>aFx z!ZuPtwGU4SY5QL1sZYknV-92hV*UzJNLy?=$Ol8Ly4}T3Xbli1>kf=V)OXB-R@!{P zg22^bj&wuvdzvu}S~wzu<*?my9(x0UZjrNdS(4lpc>YNr;KG=wN|OzX*(>s|WOq8~yE&StsK)jqaI+Dl?u0AL?Z_m>l7RWo~Rv>_aC*^XX(EQIUbp(o0| zZ(Z!w09rWN+K4*E9!}m%8kXPfj*@s@9|x8Pyl=?QJEFkNTxwoU)hn^DRz^a|8fra7 z3ZuKR9E88c8W;{N)|cOJDE%NJ&-|gh(w}UF4C>tEUFYt45;}4MNRC7uTRVRfN2`gH za(pOvC)Q*A2)X+*_vNiKIrbPD!XOI>IW?+KQKx@DyqGMz(cT>dN*;S_ z)L0S%Ymd6KmW$<#;`Hm0SFAvhmMqqJ>AXLE zl3Ubmur47MeAFKXM2n9EoEDQXuBxwjlM5y?!viq@}fHd*?!iab0t!&$K1z zn0bn(c4dtHy&ntX3!X*77E3k#o1E>y<6Ir;nnPGU5d%4$zFSO$u>qR8@3czO3x6LBkkOzMEwSdCh?z`677mp>-(@tPjh?FtkPS^ z;)gkrLjQ3`tL@xpX3c7*pWkwO82U1Lhi>=4D#X$hBo3qfP!P zm$h@>dwXLbbE9iP?ux;ln8AKY2fXvNN?W&R%s%qnn_uE7{qG98P1A-+VrEY~%+{l) zuVO(|h2h}B-$f~ieDdP@rK1&Vf4N4>9LDDIi%v|$wA&M>)9#9+<{gq}G>}wN@mH$@ zJzdEWQ(Zzoqwo^fH$2xj&#>i&U|x_UiT#PzFt>2x`4z>QXxZijvib8Pql$_76 z1)i~<;wWgs7$y4BHBVsiAi>~XI&5z_bVPKdQp}T#KX5KBT3J$G{|Zm(KtSn)Jmjn( z>sd$&q5U*rPUxI7lQ-0f$k70o*hV&GDMGb(LLZhsE|OIo7)t5W5oWq^P9@Hy0Q>+q zmZRI5de3DhY*Dp0@7)al24D9O4NcpLye4_VU!XxL5 zBohxK*eZ~m)oCeu>(qdD!tC={tHSOjrOCV}C+=!q*U7a0f`BsK_{}E>*gKG+?qvnr z_F05itg~Ew+$#?KvkIR2G}!v>jB5l;0ofxN+#e7MS%M@@9lv&g%MX7#zILi^k6B_y z2zxZU;pEC%1i{%=)o4o0ec7=O8I{AY zvBG4Ro{kl{wn}X!n16lq6<(S`;$68qDKuOq3mBq;E-#NZWC9r+#AZrNHuq@#xw$M0 z6I%JlG8s^>5(q%wZ{iz25-lCHQFkEfWDhq}zX`T|uDdF+qJEHl3x^v)h+N}PEvROA z2VMD(>X&KUQ;nj5yXd%wV~q}CjH5FRf^&8LVSjw-}L4^DU`_D59!Jxc7Fyc%R{br~G;1o7hSD8|Xa+dW z#(5f4MR%K35@T^iW>{HkjW??&bz1xHEIv`PsFXPey!AzCWp&>f&BjDrB1}`K$hP!A zZ2feNPSvMNSK8G{joh@k`X772w2i!?ApFzXimHsYb#F-8`d_Z_n}4|iIH-b#kWFeP z{hc8l`=MTKHcNJE-h9YkOl|$A{fQ=3>jkIIKi;{{$Pf&1CgI?}M7BTu-;=zofS*w^ ze^@`4g}4i~DyFd|0g)Bt)Oqcq_zzb*x2mmiw6vH!EXijUdBGT3DCQETZO!v79)7G% zW%FRDlznRs4GpW|2-1&@wBk}NK{i4u4;L2BCAL4=J#h4ysgD$&$w-)C2_?YDmDWP3L5#mPxvhv=|G+q=&Fy{Az;L6bh!LGTvujcdOI ze7_fJuXC~E90oYN?8k(vPqqxTHn2ZV(^ji(so%V;q<_+F== z7&o`f@dntQ3vIO%7JMnr35$IZRijn^LU<7!`&m%gcq!0~{?Z~4V2%Q#M~Q?uTI8HF z#9eCo41G9BdeItXoD~zo?%`fDn??vSQlxlvW{=a;#wXr(ZRYk31V`pSInh4Pu-@1m zi||rRN043#Wislk$;`Pg(-IYNh$_ehz~N9fu(MQO=XM_HB8H@&FMwQ^LI8u#e~TE_ zbHoTFmjkIabM#Z>WNyt8TQJ=!qvpgB81SJJwDPDO{Vlf1j0i}}b{Z5!UV4?h`S119|6D4XXJPgz?2DkiAUYq_h9trUO^Xbmj?_$CU>7{)A>70wy@y>W`2^jG<^ zL?L$Fn*>kk5US)(IgC60{q@4CmX;Tb=6U@+eB(0nmi?{$q(w}F`Fvl}+LLrQ)|0(g z`|FQV+U-|TfLgb-XtMnxQJw+@=d>Ae?|s5?K(6= z@Wt@nzg(FArseP>{#v?vE=j6YF4;!fZXL}xCx69%Lyh8Lq)pCA>p9bpC;>n{6-D7e z=)z`+=Rqy!XS1@L$jNEP;QSqk7dIpneO4wcgdX`WG}QNbJiqq|Zh%ELJ|sfku_PEW z1|yK2-BFB!xo?b1-9YYB-WC2xA-kf+RW+ZfP#NIZ%^N2~fw_0GLO6HP<(OBgE8py> z@9%aT)!dQw1mqD-M4Blw4$xb2xAgP%(owC(#jip{^XIPbEKOIbb)0f8KGFQ|!c5|} zPv@Njm02QB^Q@ToWZ$Tc^z@~XbApS{e_i6Tj*Nbm`kBn`w~fsotM@dJ)bGL9l<#Nc zq{P76_pQ>s(W)b4Hi$UQ_6RiJMxazj$}afcP|OgrGzCxyh~X6}@fU!525;70=REa) z{HuCFnG>0<(^7r@t)|*(U^|O!ig=OpnnkMEI=r3$&%*!Z63fXN)tCGcHo{r?mP2|3 z6kQGON&4`cI%Hsgo1y=y6c)kEs@W*S2FLc|m*y0%(I zIB4WsF$1yWB5A$KQyr90*mSNJM4co3mn+!4lmv<+6_RRe!o3i~q?2b}86)`t348lA zX`cX2{g}4oRYRssbA+W>_;6Pe8*KYul;l-*Bf*}cM2Gy3qjPa&djJ1;=c~KQ>4GGj zqLgbP&yt~)Fnn) z-Xd9Eyw5#BbZinG*Ci*PU(q~&sG2kk}Td&Zn zjukZirfUHatpt2X^rvEBYW*8o@*N%owK4b!Yk)fx{Y}E;-3&GoqqD?z;OF@)EmC>l zv@akF#t0jKKiL^>-cHxOw&&U>9pG=~jaJ_-hGW{AE_YdD;fn&g=J|yW9u>qJ2P<&^ zW@ePX>j2!(`Vx*RN?PCO>JNy`CL$(5bB_&hSvBi{X%W50ezUR#O9TKfNx~ZE#ciMB z2uj9gxtO`fCFPz)x2_Veyus~t_K*}7K`T+uq}k{jexl-@ins42CgmP4R=Nrx8=@Wh z{-DP52|x7c8mxY(VCAI)0FDKhE9tHr?YMpgsBaN8=G}XrMFFO;ilu#ulbSfTHV++O zi_2pJ8h;?I;!@60@JyrH9D&TQ7_e$T`-oYw>WDrWj3)^YN_m#*t+7DCmehO7|7r!UFnr*O|CSm06VUks z{Bb|33;!4Mctd^u)vH<)-483d9M_(6Em@uB#shR^=3f0{!4oM5h%4$pjYnsA^Y=3p zx^*ISy90=Y`9-EU!4&%x?Noj0$UBQ_RrS`oO|GG7Dn5j3elRTD$v@~xc>K#rZ^hOT zOE>Nn{)_Uix0@@ECq9R6oL}Vz?Bsl^Wt$wG_x6QVp-1r@o+-$sjbS6ZnZo%eRq0Z{ z?IdTOMr;;YQu-dA&gg@}n*@L@@t|~)rug-fx@~A05bzJ?|Z3fLabugyKI^qt$n55)HY)u=_03H~D6T&P(@j z)}hfUJxsvpm)QFXQk~RWbK2cU^)I%xts@d)-{k`hW=1A=*RGfNn;$emRy6!Mr+v~^ z61zLmke1DXhi;#)rP_?{pP?$NfVsiNMPSeiwVJuVA`hsH%g>?HxWAU71Eb4}ZE-Zy z;r`zHp&539`*v$_Ukl?KVhn&i`}sd*Uu^d}!xB=DQM-9xl~d7~4;SXl6T`SJ-s>Z+ zXA`wZ(7N`7PiG5T4jT3aJ%_frm3HEl9B%8*kY_d2q)|8JORK&7F^7W8`uj=2Y9%1^ z*G^~OFDL|L`HW4<5f3n8fK$-k(skPBxx#p(S6oJRca1rPV=;wp95uTF_dajqUVR0I zE|A8iI5PqYq%qsk1hQb#;`-iX4$Da}>HkhI5MW!$a>`%3k8stk%kTGe>U^w0`|tyQ zDp4|QT1h6b$9fNlPs>l<6+G5%jBAYjzQch&3UIVMYek4=Xb{EMh65F48aA{(O&#?; zd5?njfmO!;3SRZtIbu@;aDqU}`nI2u=4*jKT6;$h_ z*#@CSrt-d7pr1qmbmdy;2czsRW8?Dn8HdXT7fG{4QQ}km;7)!UVfoq)>Wv$#njUo*0+p&S7DX2q?xDw_+^v&2XlG z5G^3Y%V3YH5Svivg#_9!HAFtB12zb3H2zoPSe3fA8myy>gL^A2nPp0EjWSfC3CJom zdjk}o$5R`k>&DWv@wa|fBGREbqr}Z`vNEO|s~$O|HW9c+4faE&!4e`8C6mW=fOMX_ z&DU>;8Ro#LcgN+l^qHF!rRd%7A!q9LlFy!b`zB``*-OQ;LmlbpU8@N+Q#y5!fJ)hS z2X+V>pHQi*i4h&V%+CK@9P?*~_P^TTtk*Q;2mL2{l z0}ZI;(@O~}a`*nOfb3Y>IW9Z!g3g23i-D?>4EM!+{pIXEUtTG&`cD8>8en4isf+u?Jy`h?<#UwRw$Wq!N^M1Eb3lJ)FYG0vji9a-an@nQ;WQ+wlz2w8C|3G+ zkH_7SZ~be@94%MO%pc*xm7^oyD$KssmDyHq3OH=bD2G1e7yQ=`CV>L3rsnA#?)i zoQPD;G<&716#t<;%{$AqUagrrXjHeF23)vxqldbBX;pvcAo;g|{QIW48ou08&)~2! zA2dxE!na9)P5R#S1E6UPyXu%xZP@*Wx_EZYsZ5_H|go zmM^-Z9%B`siEk#C%w@_Mz+l5z#_S#*uQb>tXx7 zhbwjUq9YdIBz0D({eWCfCK^_r4Hj?w*IRFo2ye3>#*7fU*!EU5_p}NY<(#I7+Vk{) zTaNSz_1+^g*X1%*Lh}haU+hz6x0w%m37(?P1|1wGntiM^;fpf#I@Y>Lxs!#+E>%6v zw8Ppzt$HF_&_^TiM9g+e`K8*x!!rYn(!4f1wlJB4&eYugndf+wolFU-7d$m`WF*%V zSrK8do(|~znxR>yvxBDOA5Q$7w#~fe)Q!rPz;9W*s{^?v+Uv}kf|4yLj0J2lNIeS?ZmdF<;7CRYC?UdXU^z zn=+l)qGl1Dhkj`G9@x=>{br4IbfxAgo3$VGNFakT%n2+_tb`ePe(i}B&$X8*5A&A| z+zQ`jy8`itz}F@%Ij&T@Vce6=;8bERL4}g$mD9l+tfHgdADbZBfKuj4FXIqHm3_l0 z2lgkf7&1c)9tUdg66Vd2dTN-)5>{#O+_@P|HPtK}?M|sBM2$Ct`Jd+=BmXU+- z;nrIX(bcgVwY5cx6VL})Q_^qa0k!%(u<~MB&HC_0rdg{Ei>Vl1hXs6kYgj&aE+;{> z23y9a91zDjLA5gGVfWT`MC)b=J@0w%^>Xk@L3eD~tQM03ksCPu(ReRbIo|bg z#*vZf8IG0+zp6Qx37g^7^g-EhLEq`G)u4Cn5$4f_IoSx!t%~U4Hms8c*b2DR6!$QR zsp`wplIg!9#(|7Ip?$`O-@LVOdikE;?cj3trfhZ$A=NF5M1=`^W^3^`n;G)4J0=qi zw_2Ux576vE9Hao9dBLxr;b+o(0TS{U6)XC*d1F+M0&yWWEE_9aR~FXI&|8 z&BW?2@|_g-7?$?QWzm9co4#W&&9y)gcB?n?TC&qb#rqsREeI$Us}KKRqOoOL{ggF~ zbSF73W)lUwgxdNYNZSV4~Rc@h$F^wpZwQ%+)U>Z5gg_c8LCPRWVXlCAsVUNpQRQ+`F)Fmjw-R*B0<0*aTbe@6Ip!JND$SWHUBK&iFzExlqk<^;=wI4Y55X&j|*Q#zeUbYTIT z3*u(YJkIXVujOZ~+z>SVp5*(~K~OfLg;z@TxpPmS&UKdROx-AB7H={DnoSIWx;n6G z%~j2;?nyyh^~6%}T!5G~GdBnphK4v`)#%08Gw7gp?!RCgyIa;oV9}O$CvMIV#eg|>Zo0T;;_#Lt}8^1gBOT2 z>71!}k808Pfv-iGK$s5f^Pozuxjy^)?t|Yh{F8po!h%MKL>++Ul?&U(wDu+qaNrIU zP{Q_)r~boPpjm=GbBGcfvAXp+EmvXe1?RYVJQ|%Ziu$(qs632(xZxt^75vA6vW4mk z-Fc5vbcP0}p=|APv&L0D*%O9onT{+GGYLQN6=3gS)sLyzwU;8+MeLi#^Nqi5fzOK; zCj{qh*=IxmvgG;h?%~?VA~GfrXpBk3Y`x$&R|W}+{mgQz1C1R^doy~@CXK0X#1P~D zshCpBwQV;(iRMx^v4bsV*Zqz^G}Qzu2V7B|bX3U8*#qNvU}O5VsP|iULWeJ%OyQf_ zT{DRm_QG(;n5y<#&4JIG^guX2$63TGRdOG{cess_fE^sFspw+}dZIQ8t9`A1P)t4V zL_=P1^!2y=V_)t+_$#t{dRh;b0wTnt*%As;Q7Na95VpK44<=svGsEJaM}P%YO4iPA zC}Bzx5&vKl4tk)Q5?PZ)yOW~#!s1J*d`vTihfmh=)`cO#-k=#iXCn5p*|&PDbU3xi zCiX|vy1Me8T4o>)8YE`1vyl-?rzXA9^)sTdL&r0-*}t(&1(UIXPS|nS7(fT!6y|tL zb4w|F&8I_9UdWtth*&iZB%@gTQ}k0^67KACsMQQ^RB+U#4l7W=sbGMm5MJ+>G8K~q zg!gbLgHayA%`0xer*8ruXbHQxefGqvkgV=lrnirMnJ@Dg1dl(yvF!)N9 zktfYOh7X)SopsUvd`$Q8H~0|U0E^#k{6@ovx;VkMuTX>xz{W(Dy`D2#RAYQ)d|2I0+x&J?=bMrxCSr~*T?$@Z+3QsQr5yLkkzGwHX2{J@^!s{}}HepT##$1Ks^>;{L{BE4aRUoa_cUjmwZ~lX4rje@u?zvf8rRgK^#!2va zO4)DW5z^TU+DFJc%_H)Gl@OG`_<%*hm9;AT;rGFD{nwlV4DbHRQLofp2h+ggl#vwU zzqxf`Uf2xYV{v7YZ|Yra@PeEcjOTvKBxq2-!ScKiFSWiPS4$35dS(R5vs3}Ay*~W+ z@iTf6la`M@c{yU{3c><4J3z_R6`ZC=sq!{w3l8>5#W>fV9Z;<>6ju~r%}-Vf?{`|H zQ-=K&&|Y^;fBPAnZgF{tC3t74);At{QxF@W5^@#Vd{kh%6X4%I(3rQsb#^GF`J=3> z(q9&aKg0VO`N8W-UA#A+@uZBB;XuS@ZC>d=lwj8HCr4vQg=C`lag*~aqupcJs}x*b z;LqkwUZtqumZJQ#P^^3?-Ega1!>cU^OX-RcyS+Z)@*yp+{yh{Y{7m)gwe=O|rZ1xk6ZJzjA zlO%KnJes1O+MJ(Iy|g)RIzn~OXsP6>r8wTUDQktaoGWk4tdFT|CV3>tr+sx#qZ`(e z6H}iX$=h-h^CS=D8qiPTD`vjLY`8dx zzNNspe$6_h`?%0#>K88_Ei>(>dwHBWU)Msm&z<504UV?_Wn2@L(12Law*9`Xg0E}% zQb$+{D-TFBmc4FLrVu@48Wj58-QK=vkQJ_j`83^o3%!w1Aruz8SDci3M_R9Ob*VwK ziA+0xxgvhYZY(={{j}NJ0wn$2#VxR!z!_y%9qH@jG2=X9licCkUx$U3w(x3^qWquG zHMx(+Y8N}$cwW7cbA0UEzVizRahz}!SP;I($1lE8De%=;6Cj!J&K5w3>NGtfwIOw% zEFUbWz*opAyYTcOivi(X(x9%Gyykl5M<@+|QsYD`{I1#aLF$*q9ES#t)Gsl(fa_Ro zfC)yx-?swgA?f*bH}+<&szj(&%+@THk*+y`)OqMtN6OVKRYq|r>>pU;zQHm7^!|0#nO)RqMMaVFU69E zShj6LWcvX$@LT6oEK>cbys{^o`hb<$oO;Ug3|27Ab9=24(QE$t|NE@pqxN7Q>!osF z6kdQ6QTH+#2Vuj@o;(0#cquOCuq4j65Q1s z7`W`AkLD;4zCosa;z*luseR&owksEkJckbB{tS?3Jd_W&#G#R+(S+ACc>&cn!s~}=TQ)5glsd}G$p>2l=cJTq{0`ot z-2=I|q7{{g6lA3nKh^fzFr^Tf{ztvF(BJs(N8S8cyFTve17PVZZyvT^o^n3ZP?ys& zNC-!P{@r8DKxAewnj=4_#l;i{!lBuM$&*j?N7#9%e)~O}G2jC#?c-Q?!GQtIZ>3s2 ztGLBew3s!iY!vN-1Q7&>gaGq0z{wf6NT#zUpnog^mF^1@+iy-!>;q`~b{}-CC`dY& zFjHZ65tK4aXZ0r_C(ABA0*b#@NWkH+4wKCQ86$V+n@Za*hVX)7%ByYk3jS!9J<4#` zC`GdK{4bW(9q(f(2~j(NWg7?LwqZ6d?U@?z6Ba(+G@SEzoQwUAg;?(Df6@Cq2H26p zpZacJeavIDuv#vZ+;dqI{k_TH-#rDb6-=r0X^)}FZ^J)C)~@<4?wakdTXWEeE`?Al zf)u++(zQl&4W37|9d5lFwop`^8G%xrCWfWJyfQ+s0CuJ>9Lx?Omwrd_9d#RU2z60y z9>gb5?xwaidafU<{M=8AZLAWi)z|zSU{sPVi}&4+O+h%gEVOLS@jcM^qozK;Q<&zu zFaf;_VuXFR?XT&cC>fsysH*r1JfSNV@}MaRvdlZ7Po?WH157Je+P+%7w=YrBFt1QF z!DO*w2Iu@fIsh{T;SD;CiY-3O*qlx1xw6XVI8(mvHfL2$fel`Zra)AA40NQFqMmG@ z?RkvbZKV$v5IWT$vHSY1mHF7qFaq^j6y3Tb2X!I;s|A4SqE_ZA=7sD3dQz7;^R9zg z8Wu7C%Jo1)(9foWws|nXq};cJu(v+iMOm*Rp!fpkKdbz(QB7l%rhL*iAK7S*>IfAD z95Oqz@_Q$x8lFRuN7gJd%E7PSml2Eps^1@UqJ{}BQqs|<*45GwtIirRl9*t|-DaJ( z(qSIvFuG{YX1OFqJutcybE#ugJD{%-WqQag^Wm7(EpuP9zM~tE`QF6!+AiLiW^A~0 za&;Svst%(r?__)nzs7lsS$9f3YO5^oA<=y_U~>)9hdrbiI+c+Wh2qwl07+r|sv8Mk z6QSB!cde(XdU4s6H)pbT%(8aS4lOdC!bNbnb|=xp+$e==e47U8E-ADTvpJdZ+s5c0 zGRh_xBX(kvL(pO-E1dR+sKUhfbBtX3#>YnNE<7uNcL-kO;q_$y=)31>K*guFG=dv0 z`p^g^8+W0|1$oV6`Tg=^m`sxXoDEm*(LYgBeddZC$08~LAlED5pG5&~l@B3QU3Zw( z-KPrsdHsD4pD8xo5+B0Nua3r>seFf(wq=Hy%R>I{0TjvM9?Jr#5~x!>L__gs<1hBksvCChee?_44^ zmG2b6$TVqCy-j(0zpyDaz})0$@s6Dx>F@D-!zBf!vzSA`N7+dVA0`KFRp#^TS)%dg zzBiojc7_tQOJn%MLnc{kLxrl6JI+h0ahOGAGC2PSNjz59^w=2VdnF>|d3UR1{Aqqm z5BiP2*t@51<^Y|-!5mu)iLJ~#=@$@gkNc(k7^TF;RMTefF!M8kO)CKcqgB0z$7|U432{fc}0!qwV8mbCeM$8GT{s>B+>pgeO0 zj*87u2yjk;= z7fa|Kp8+DPg?ZwA&BbkX6!?%_W}ZA6+C6^B>nrky76Zy^X5#zHe)^<(ssrF&)K05m z`MG$OyuTO7o4Sb&y`42rhm)vS0l~nGp1j90ILn#b;g$3?2OCTK=ZI6*+81VgrXyTd zKx1U}o`YAmf;=E>OxQ6@{vEy1Yh6~(f%>umH8lJV_rqITMP-12(EwlMH#4$itaIMQ zRJ3|i+5hyY5>l*N@@ERNhDmo!8oOD2 zHozvfmme%Nth_R?WV=~IXKT|y5}$QqtmQw%c0ghV30<>{XG)9v-I=q*)Hwlu*m<$W zq{()$5+|6&Vg}=3b-FUsYXtS^LUEJ6KX}l#Cdo42!^*; zFlv9aQ3Sm}E?yfbN8#>&Ka)QE(;I|ouVjBa z@inteZH>D-akY;ddD>v8I+Yu>X=~LicJeC+I3uxN*0Fl2`l`Z@4vlXGyKEf%Wl=_KxEkRVC**N`H~c z(Vh?SkMC*mOZp~Sywk~~@^Be(TdmUIY(tw zpq}Un7p05saoj^YXMV=U}kw^>?A)V($wfdg;#v08Eg=QilH>zI0B_1rYrIF zd}>o3R$9V?|8y}ED8T{L$d*c(I^u6mKC{Cdte+ zFqV?m;pEY}+_!YE$+Jx-Q3#PmY@n3)Kkq)HgR_aHQqU~c0ToB|NCgh1%LYs$6HBK* zw}D+x3oF`ds5ppf?SegIm;nqUsaftq>c)gq|Cov_IEbz~gom($g2MVfJ7dRzOEcr0 zoMWKhizscWR)2X^$BbD;&>sBSqL32n?@ZhryQ;bYbUQta%1w`N!iIxUKCwH{Jce+^ z#p^f@u($kjUPM4Wnbv0pF5qHt0RMS-vwmrr_VG&Nn}*&hfiA~j7^{#RYP$#^Y#%`PKT&n zlKa&5)U_EH|FOfCR&SiN`Y7E`*)*f}sW(bR)vC~*;B@L6G3qcr-(ddatCJLdbYRl6=4UG`mN!;B2S>UJe zxATe0az6G87`RlS1D{`BnJpb6W(#QT#~RbsBhTezO1~2=^6P=;i^Fh0OpglyZY}4) zLG=H^38WX{f27ZWE&9oWJp|l8r$?8-F7b^D8);Q(NKsxaWCe5jPhFvmN`0EYN8 zX(Jc5d2KlHbUui}OWYJKd=E~*UZEU;D@9?CHsQ*a;)WlD)PrAioyGiB`OJ0aq12%9*dA{xFSU&Oac-~= zF!x**20+--t7{R+ptV zBd?n%MP2wK>7Xzx6Dc(hob#uY3#iMQ3!X|@m8}qV40ZHjQ;{fz2v1`Vq8M1K~31`WJ*%?tKb=%zUWIgz8H?S+gU zYk0l?Rq=9WAq!YkSXEQgU}w#ru9MD0j$HN*8gBQ*()3cw#dfkJ^C3vq57zhLENAOO zo{p_4dQ#rzJa&lk)_~Y|L+3Ig(`1OncfDJ?5lb%`K3`rBIwY_5F&}6UnI6|F_Uju) zs9}yVlD1cqQgj_JI{9xa`07NW9kt)pU-D>=wR3lVDZD9aH&cpG6s@teYqZYDUb&mK z-tntHww21eZwAj1w1?NwxfL7AJL=rv4VhNyF32oproKlFb0h`1kYYLb^k~e2;JEO& zZ{l+?N)1!jAO~w%*IxU!043zeuNjY$D*rmjQjZF@_Q+hq-*G@{T^~i^Zm~s z!8=pKXi3q#aP~|gw}!-8qr${Ws}BZb-_9gY3h_k6AsF9#_RmpjPW zZXH1)VeRU`7tDO@u=l`IuRAXIDaw9ZnAEN%k$M^0W*4&$1Kz(YhU^q{=BB0a)ZnhE z=UnZJ@Pk@s81jjqfrbT&{0r~1oWGiegg!g@{(#91^~~h5G*_gVB@ME9mHcza``$fB zvm@Xf(Duptv2E4>h#t(e^}gPR%CU+Hkwp{vTu6^;?ZDHn!^+?lo0FMqXhgtP-agm} zU2D<eP{oh`G+?f8J8%GOTmH((c zP=n49B@6vyH*C1k>#Pc9c&sWn=(vqaM(jsB-ADa!>ji~aebO~$?=aYXO`P)gEQRXU z4vr9*y-lUrzO?Y5xm7R`*(hUNc=->{)@s7yya_y!)yDb}Q%Xv{c^w9q_DU`WV*bVI z*t5U6$1LY74$~idLiJ^0DbPqjJ}gy`!dp>d7NK~oq=+8MjJqFSK%-7FYc5)$!C^^l zy;lq0rM#s;oc#+2ATMX>UpciV3kPzqr#&3*c)s|K!U8;6xa_I2{xbGOj)vo9-a8=` z$(10z%2{X&_ak3607j2ju_njbL#?ZqQDkhKK~BRb73b6bc%`rOsGY9!aWfv&+O{WC!VU4pp$ynr%#$4?i;-_0aBqrhEi) z*US1*b4x4#ulkR`oc9-9+!hKMEb>gJIc1;#zuEoL<%9z7S!p@5IM1}q5a}G0%o?R( zEf7$yyjx2G6WEKL; z=3%rLBXmdih(TgnkHR~n5Rg{XS-=hgUu`QCy6~sMbq>a~%4)afF-mQN7l#)!`OZ7| z)g`;9fwvg?3e6S5iS*y=)kI8smuSURwC8gRZ5+i42?Ne!qEUghhhL!*)Q2CmT?1$6Wz&ACZZ{3!RdXz1>2BK-1}lE8vZ0 zIRz24?1qI-X&#cV^(#c9!U(4fEoSjf)~AEu$BMIBlRo@9>m{j1uUY}bzr$sguC7I& zD~$}~C=3DPHY)Sa9OFxOfG_-9i>xN&lVZ3o0LrxlRmO)eNzkr8Gy_o{+@twkKn0a( z2Xv$> zBZdeDf@=<>U%-?iwAxNte{z(HnG-XQOCImy@c@I_PK68n#2vxV$_$J?_HInt8}MSQ zW+hc`u8CLe&+~(hQ=8Y;mI1XdE3i&CcIEZ6oaWU0Y!_3EYPNyqve?B^t1@X<`Dly`IjCMq^A(T4u9`fl()Pc8xpB4@9e2OQTvvOe63(wU z1i{dtxp}$@d~IC#-gLb@m9OM#(TbO*fU!^P(R8MUWyaASz8&Iq#T2upwkHctSgSt# z4^zB-bI3?WtX9Z=Dg`X&82vYibr4(7ZXI%VvKq+6Bvu(DeH< zWT_P19UYrH9@BS#hyhh$1&R|-iHEH(UKLFO(pe)TE#UpV%ylwkRz3c;vj7)(OQ2|6 z#?w(}iZ>^wj;J^R?XG0;nUH?w7agFWc_Os`;jpyI7})klXYrz#DYNSpT=Q!IjNvey zRR-K&Qk!$DWb~C8B^7#>4R)bwn>6XXK;Qs`)gCl+ba40gztC1`*$QPK=BYa%1{Ofx zs3py^O63eN$0of?nV%Ggm9@+db`pow2CG}q_V-fnG-GrAeyM`wqqGdJRL8%msE_Ak z@DB!*h<$_fZeZY)3e%eB`i*2*Hu||Lm|?iijFP^9#PjiYQUOK;0uj}^2;B0%qKZ3! zNxU&;xVaFU9df~1N77b?OvRwi+6ZkoN#Tra35|r4J`6sxhR)flE`ilQQV-*o!P2-%rxZ(2oN$81$m&a`OOt5$9#wsNc2 z;(Mdgt7h4$zso&gk1}w4wC5G8SB9*oM#oB@sV~{>T;{Do%Fy2wWg90O{|3XH@4O{S z*x=KwSs*k|!SD~o8@1WOKR0mP^hvY5rClBdb0y`$m6|QztJ&Vk-<6Xy26XaA(~+!4 zc1mFjNlG8ONXY@m69ZOT=bl{IjQ3T+8Wrwb@?}2$0Wc7`raLb>j@yu$$Hp$n)l}c< zVCeMz=5YTh6stJj?%P8@wzNLFc5)rpM+UvO37_NX+$AbbJ@U@eZaMxOhfsZE+7_jq zX#OLYc4^1_zpPcqI=(u;=ifc4we0ilZ3#z=-S2waro9Z>BW*ZZv$AXOqjn8d9-y>t zN0sVQ)cumx=KwSEtEnnH5$TolKbC~Dp_-L+?Ues_H(k~E_v5~u<_+4fH8FmOoy(;! zw?L-;mfC-QGU9hNyOyT_nZ zxgfu#CrbSJ2VD-x(VJm{sy%zeGV8>M!rPNoMCucra+TWj9m1euzcTny_!k#IvECz4B)U*CV*zf>g$u@C;ot6-@yzTBqvOm~o0>wus+m(Nq@739d#lLR0J%fGU zC9x+*<+`jN0?>muI3QSOTQiBCSX<0sLZ3`4~1B>b9@!R8&wMGbUZvuSiL_sY(q-dmo@?zF0O#9HKq?w5W~rM=+# zLh3S6uh7?C=q|+J?eMncGaZEnGcz6Gd`fXF+wMadLW3li?HN8=KvrxZnAbcJ)piJ5Q63& z1ftCm$omhyurOyzM`jH?I8k&vT@EqrS){MVU z*wIe< z!R-bX3*sm*rdToW&K^6xM44}uoAJh&#FS@~eoV}GzS#SC4ISUqQho4=t4HA%*PZ~mu(g60??&9?Sr%PP7b{u>8Zu%L58r}TQ#7MyN$c%=vkGY@CVV2=Y6 z!?V0a0Pm0l^$qGqXEW_Jb7cSbJqqs8Hx)#WhC6a#_Z z;kefI($DYzch6dMZtK2p8Gafw-eMVkNCcaC<7k^b&_N~`^Ug!jey#^JrmGEP@|yuq zMj#TXV%xd)a~isRiOyO#{Aik}T<*;ep4z$b^ZmEIiKkscP&zo6@PG=3{J{@Bs zeE=MV@$}8g6CQ`ELAT&Ax)u#HDy`7ndB+nM2v|w5|9jTd-%iL;m|`2etD4?DTt6h; zjMM7vWKwW`3bDHr=h9Dq&jB?r7-z%RP{I{__b}tKUv3SYn*&qOOa+<_33gFwc_JOto&vplaPh`UL|N{-b-9t69@^&UC@+dbNx(k+&JUOa zWm)jE1>HPu=@+az)ono8s4_BW2QH6L9m_eo$!tL$VG7N=a1s)Q)&H|rNki!xv1f6? zScy`CTgryFznkHwnX`#ad93y8rhbfL4mQ^%)kgl^qs30c9BZ8UeTYEwg;isB8UTs9 zq!CVPUawRS@)#Q4+?;&WdoC3XY!C6mTi-lSg`OO=Z*lZBZfjn}`~Z1W;VU}7=%_pg zR@%DU%4IhyB|<*uv}kfm0y{A_-KF~OyCv|M!pgeHpWhl~YM)%gh9{@ee1M1xN;Lzl z(w;THu(mjfpIZD`c+37{md}x)Dqt&bes%e4`QsNF!&yGS|DPSUygTWBUu4<%T~zrf zoG!%+<#_InyICz}FsK(7m7;fW3n|-s?->{YPI5pvkgatK7*bBN@?bVLGjWk-?>KFq-a zT~EKv?`E+;Rh9zl3yE3E_6RCdEq&ht*=^ zyTU#iho!l;x3eA*)X}POmN!;3kd+Eue^_|OXfe8A?4*e_|K--d09YVfpM|fpk(Y7( zGFVe7UJWHz_7`Q!0qG+MiuOqd(|9^&j)#U3v}ymGJ~fjGmVQ82e++>;r{K%K&s)6# z1j|PR+C!tIj(}^fUbOSDiWV@xdA*PJO!cLA;L8*j;V==)Vm*wkc+h)nlMwDw4;(f| z_AshGx43r1;+hNdSXiubLITbFqK`3F8wkd>D2bx>q}!=cv%JWKxmyaRN3C&T8bn_6 z3mB236=|xbPgQ|`Zf_3KCaz8-oza}pTsMI6?`8$ns{Du!`)~l#yn36;D-`@EB%kiF zsOCm^S@4nNd}qoksqj22o=X_a0R(X(;GMUq;@rxH;x++AJZ<#uo}hrb&MJZyJ%b^Z zUWt@e34$vdQnCKfyrWY|WqmUw3naX9K-${fb~+}y zr~#bZ-n*C`h?a z7!Bt-1K<03$lx#sCh;s{yZp`kfDg0~JvsgF9;#sGtW$U03OV=K*L&Hz`UZX`I<`lS1#WRg5q~&0lfA{3vZS+owQu1_lD*Mo+mu#R~H2kYW zx^3fB(wB?NhBSJt=WL`%{ktB0hH(&nu7F{uOB72ZvP+E4thFos2!tLPq1^^#p2KvY zi2zlTx;FPAXet$=p!!K})&A>dWj|-w^GD75jXs4&GdtUwj;@3-=xf@%buN!?=`BX08=YFNACVwX4U|O!Vf< zht$_SB;1AA#T&)s73WI(O_}%b8a%23a8Ch?*YKTgO#1^_M)9h&tbNdLO^exfqm1#*#pqNB< zBlc1nO6?h4f91d5fPXK0ONKtzkr9qaOpM6STckFI2?GM5ubO4dTd`Od5?Eu1(Brn6 zwS*8%nzlc8HjgB{OobWXlp5lj&8`8P=C3i=8^(Z+4)c=%GU{C4rh=(q(8$cG!BYzg zQYMN8O#r%U@9TBgt0aP#xs+a8Z2Oz`13piO)6Na3HlH>SaiC!FSm8cqhgpo&hC#e{ zvTGCGDB5ZEE6B^s_`cO2zkjt-abCo%SqhwEZU7$#$0nGaj$qG?Ce&(%W6|4o@YbUgGk4DRuRxAA*HV-{%2fDao$_>eWtnc$lrriKhq6k?x_2)LcSH?_S!FA)SCSC6HnP+`RI5pylKWxdToA6ztr@u8Ocp~0V)#%jF4We zaxK>j|GM_KTVJ<$-$b4jJ^`#AQh6lrWW@D9n1-ug!F{J|O92mB;WWm50~;s&ZJ{up zY}!uKSZB7Y2Yc^*?$vVqua#9sdR5Hu>&yS9~IzXAqV zJiPwb9_KK%+sSX_O`mPm3{F>sBzf=8Aszu5e73f!$ zP%WXy&eDA9&ZX36VbFcQ3M8jYOh3<>AZo7d5_Z|`IuYkh;N*j%cYeol z-S^ISCa9VjMsZ=zzkY{PE9=#XG+fT*=$?(@nk3Mb8zkbIY#ORt)~l1g@k1cD`LUE7 zi?!6K6zIXeYhyYp5KQ9YQ3&FxNt3Y|QzhDqjD`bd#10h2F0f#!;dOrC4_sh$q)8FH zQg!(JC&1qm6J7?3Q7^qUHbS)%g-Q+wxv(A(aY%ByA;5GPyyX4wp1ulEWBM$5SWedL z(73kN@x?FL+}nUSU>u?rSbLb_Ze=pP;4PL0a6fmyCC9 zn9oTz!YH1$g{%ZCAao4L8){DQMYKP>3W4#Q+v>;klBx??lXn}Lfv;4YZ^@YdZ+Try zxe1$$iI1skj$el*^bUTxP3WdyqVh>(EUkFtNH+#qN*N)wy!V{$gC3o}N!L)vi^02~ zz|;dX*XH|``QMS3y{i-d9w8Yw1A4G+D#IO46*@&*qhuRwAad0ox=BpAl*{J$)?4sW zf3a*+Bi5z;U50>giErsfSj>@6Wji#pcaAX|EgG}d&@7TJr3;A+MI?|e0DCGg$BW-! zP5Y^)P3-_ilzO@v+@1G-99?@n)BFE-x}GlTR0l=1Q$z?MTOCC=w@R*?+)|0$wnf=e zV_l9eB%xuJB-f3R%Qh@qC6rmYjI!C5YOB;XP0ZTm`+N6$Jo+ctmx!BGCyCMupMib|3jUDnbbIxQ99zAhyn# z2>k}Ihl)vwjP1!kXmh1a!v?8_CGK`aEQ&8yjr@DYIi;*ig$+LIe1v-)QLn&6zF6lq zj;IXXU94K9#^S_!%E@RUUR0hD8$~+j@UzP9Ro-Ul&f+_?^|vzuR2Ov$=KgWp2=5G) zuUPo;cA(F+Ekq-|Dfb^mAbN$h;Ylewh3#+W5`3HnTXKm67Fy0QTAsg-2yGY@jMmjI z4Q^b>N-$a84oQt~;vcq1+UQpn4;LOe#(lEw3gf)q<}xI8S^A7CyMv95tJy(19pTP7 zB!2Q$>n;m)#sOo(8R^4C^4PqaXhKHV`E&N){{|{o@x_V~UurLhMjtfKP`HcK*!1|i zsDOChdF-N?Q*H{Oc59OFiUIMI!v|e_USmP$o@0R&z3iTr=X&1o-zCl)D76AJ><|23 zkNke7_6oz!lcJNhk2h*3nVy5=?yBQ=U*wT6nBlh)1fa9!RUHBA)67EOLO@Ii5wQhs zr@9AKFyWg|yPWilQ4y?20aQv--V7uX{7i2DfLVi*vYKnrLM>RljQVy4$ps7YQ^aVE-O_Wu90yaIA{r`Q~LN1E${5&5tS-#A8vh zUG~=J7F$~+7$1>oSgq5RlGv>R2C~+4uSKBSEWelAnzCUy0Q7+;#5Thl(T?qroy7PJA(EwRtgfVg0C5+# zB`$vc4~A4fL^MDtvN$W1s#+RiQXA0@$sM;;b(??*@X7C#v-6X!4b@TuV zNJsohIYZG{A$j!RF{S&BQ6l0oJ(<}6JgVYLbCj6>UV>RyR-Kl^gy;yC3bE%h8|oj) z{Rd>rrU5dbn=}vbu@D`Sdyb1mVM)#~&VTBX%a3RL%^+#<%^N7+vQWz07c9^hr}KS4+MSBgu&AwrsF$u*Gq6cs0`8&oR|L$tt>* z>l;dB7^{i+v1(i4Qf}*e7f-P>5^@RT`;fyEJee%y$kN7A^Z6>omGf(xO6$FZQJqJl zL{0=v9RMza2%*uZxYG_(^6DNYs1(vGhPMj~tgxD>?!fx%9-o0nV#wxpt$>*_Fvfoo zka#5|Z1^LuUT7v&XT->kiHxRJkg6t^okfP=@RPtUdTI0<3jJXmWG+-AZTgn!z7Mpn z%v;n{)m0baNWfZ&1lrKr(Gh#|xOFD4Vgz&N$qkm!ANeK<9J6zBkGo@|TbZ4Gw5!p1 z{8IjfG-5deeiYL%$gtwKxV)J^mPjhi178-2W_F(+iYc0}2t-B-{Q9`SuW?doUmf+I z)+GLsaNFH3i9Cu_qgY9%zB1`=;~p^8E6lN~c$`e^Fx9A{ta8j^U8{u0zW%;Y9rqCv ziWgRftnsddzNm>nPOrT~@KD05J3;Q!=3*(1;bK1_wa>s*JC*jaFJXW9ucz~J zGQQbDrLjU^(0(G?5J;M>XPC!xop_=)^xASrk@R6=`)X^{GE^kZP)eHR7~jNEX5xcw zcWQuc=8zaVV3PXVRGZu`!LN2(+6^sp;Z`QQ^fgSpRYW&-rXgq*!uajY!Z41RbNa0M z!eYiKi`+q5gR7A?xPMrD`Q#78gHe^E`XBwU8E6CF1O*{f?yPrXKky0Fs=xmsYvju7-BYbPT3y)bnO>|uW;!UP!f$HKOGJ! zz`pLUD`oo4hfpv6pe|zUjt?loIHFoCZnI@Lw!O$eb~K0d*9&&)-{2wM8(&5i%t z{fyInyH72~2+t@2HYV*`Ku_c5ChMkfUBhQlW9XM@uG7=NiLnq&cVK_#n~zyV{!==h z?RsUH&?~7H@;OL+<)y-lep7d!xvn6rFs{E*snmpQ_;-E@?UM|?i2%<~XpVh$vH1$? z_%E5-+2XTe=#9Nlu>a@$@!`rA0&>=4Id$_%vpIUfs~x&WUk=yU->jQPccn|!SlCp4 zitjFBEXmC6gn+J-U&Pzspe9(8s58djTWoHq?=^~cLUPx2yZz7L@RQ-CYI<`|KZt-R zrRE+Gm9;KB8X16y2_m>VIdGNu6^mSXj$Iuv&qy*O5s4-(rbZ&6Uy&lj_27fZdi`<9 z(@&px*{3!o$q3pvrQwQHAbB=ct?+usiR;JP+HNaL%ZMU9nAwpPGi~9)uVuc~bUNPW zG5V%nQYFpXPB#WC#Dy%z)nS64%W^cSj3!;OA>u*B>srGtaK5W)(TYiQFek7YYupR_7N7Less*lMn zLL!-kPJ-MZuh!hNv&e)#)2io>-+@>fkRBc>d=qx{aHCV|X|P6uqb%(Ys~JaIc+a-% zC{{n|6r2M9Tg`afblBuF+q4F%3eW%Uu7gK8?*S57ny^TcgnxSZ{kg!j)sz;)`k|9R zLJXwBrS+(7@+V|F2?D_vGpz?s&wlmj$xUAP;P|e9GHGOAc;hfX6D3LEJhFb?v+pd{ z7X3OzE`P(Ixw)oup4ZuYmS~twPb*vQMxvJ9o*X+Jqh??hkJfuZ`nsg=sEm#}qe=X~ zJLKyd$q4VlRZNcPma;)Xs@bKTH0wN|Tb~J_O_bu?n*(nS@mj#QzrA3bnhDyHk1nO@ zHE*`m-#HnZn=u*_DY&&0Qnmi+2d^{cG7*&)ibd%i_Q^uRzNFt@6h*?SF!HCfl$hFta0sO&sf^DTY@LpKT@4UymClBVT>4L#O2NWJpjxY_s* zKjf`hG-Y+PQhg;9NCLudxled4XLbQV2s@>-iE8N^h6a>|&s~)xdJU38o5Npolh@z| zTbb}8>4cwOL!5Z8q$%;W-SR|cg5@eKj!DT_+G z{YNp?Z+*)CNhnmRw~VY)|0G|G12V0I@G%C6(XrJ@-4B&-Uepnz$-3Mq(!7(+@k;)4 z3KMibH+R?AFa_pUh99(!=#-D~F4&3Ca7FT~_XF{qls}{4@2)V+A*2+2y3MYN@Y=H> zQiOh1@)_V_f#8rv1;4BpfYiEkg`YC+aa=>~P4_a1^df}dYtK&o`86+ptvMi}GL1m* znWzz6J^|bX&)33P=fQ-BJ-dGRyvBLQwnK*mW+?HKcN;r@jS#8w^R3hK97>&55;9^V zrthTJO1)W#o-nXt{H?_A33pO_sGhSeBieox5#5Gb-uA_svtx9E^d0bhn~?p?5UV@m zYqC0_#Q?zw-7n9{K=7F(>AN=mT(fpESUD04_8JQthPAf6RF`P}3+-S}9W5LG=k6J! z*wNR1bf-VZ2*W5Llm4J4>-vw_g2VZ%l&=^lZdIC9jTS_=Epu>2epVgjkZ|%;{O~4^S zbq1Pw<>>WpyJ-Fz9l!J*G6p@ja;9+wYjY6xOq1t-<`1v#Y0?SVFi};3E9)ChES&ij zRQdeJPk}E`$sZrgr?qjlMNx2L~6W7bW! z?|H8Zw9WBiTg&`u_318u>)zO{Nzo_mDSkaZEIhu?)TDNV~cY<6eTwm;@$> zpij5ACpidf`Zaf6CEbn;e{Sq%nNv7vmPVR`e>9|%q9-olzt1#XN=-Z;$(HN()Say8 zqK8N|txYvWFVSp}pjNexm3fGBJ|#eFG=z*5qmk%kKwlet9zs3e)HQoy7I=_V32FAm zyNLK(A#>!jp%?gl;)`X@mx$e4nm5A{sUT~T@#7MYgewGVM7F!hC+~QA3yL&tk?d~2 zSmj75D`DTN=-k8__X3|kZ_hK}@VXd9l(iOcY1hsb|>#h_<*ZD7bf z^&2|%v|UKfbG>`m>23RZ)nUF}8DST z#msVvC;XWFQHW*8LZqNbKi@~vdKW2VApc#fLcIYxby;BDqMWN%<6))q%S~mWXSvM& z8fP1BsaTie|LLOd(<9x{^Z|FYr|eucQ?>VKhbkzgW2FVzOpEyY*b ziwqfZsv{ozOr4RiK*l44I5{KL_-w|G7j0fqS}fAB*thclj@_+>yRMfw<#?FSoXa>H{Y0x4?0D;v zx*YzdST(~z)0&$zDNa33G+*5>z{=F{c#e}TbXGvazkC=`Znpis7I@%m(#}ZKBl>72 z66zv!0;281$<8xyK7|=}^=dr*X%$8WUbyrioP?D4`&Im-wp#b0v7f?z4hTG2eC0Mu zjeZ{I>ps}J9_?=@bU)4L)0K(wNWe%}kmd;NtP-(P6CexOS(Lr+gx{mz2!pHp z+3i7t?bW~rBT!X%3VpW@N2k{1t~^($qc-P zwk_|L1^NRL(D93kzp_rfW&{7nqeuBp^%dwou`FQU?%tNF-r_c4$1P~D6;MM zKZ)sG65%%$c{;*43DQx=)Rla6_4ydU*i?l6VYjch-xZ}!c=GlIeX$VT8Q5j{?yVGf zzb}J)9i8Ia{>CDw1|jEAo8G<3^KF3F`NwKfWKl}v(B<{9ww4>&$`fgbQ!w~v8fGoQtyvxzqAdt z&E_UT6{IS!PqyA5NF-xs4{FhG%;FeQpmhg<1TkAqVlm*%WM6;OR>a|F%qj}+zuttx zzmNLPGg-Z4-MMx`hFr`HbV|f%#_IfQb2HJMI>iL#adR_615X(vR0io3g%pdI7P)#g zW!l>a3loNQD9zoL;l$rZ4%c>hYeE$GkF8%O#0PH*;ZB1l1w|g>8L`^1W`*;R3cPZK~{rp2*v3|b(i^9Lx@@qJxE306xNmV;Gfft9n*12YblhwXdVjp|#FsG%)Wc|@UScIqt? z5DdY_#Xw~vhCiya*k9dIvE_;LnPeDA(%t!(eLl!)DyM#UQyd(4L_g5o-bg55vf&$r zxfde^euBdlkj>xE_)NScT_&t|Gip(%WHCeL?jasWHrs<2FK4;<((f>4heZ4O;-ReV zkEW;v5oqP9Kq?b6K>ZaQB3fnoUsk?nJqbJvqB~*^k%W>&efTxh^Wqf~-#2o6^uVXw z;8Py&FZn{dE3Uglec;!rc~G|{EwL$fk33_ADzB)pNoQqCuq#HcW<@FBmqM|B4qp9o ziu3-RDH0?{X*o>Z#o&srvoMZR8b?3s7RD>3_f*>J#NF^0tD&Q=SUe^-(e2~et6$D| zO>i!RC!MW7Std!s2HTROnfBI@-|Z#@|v6{lcGNk&3$>=(U)(@`Vv zYY(VcIPke%ySOIQ>3d5SG>Vi`D;uUk(F^#(gm7-_A<8q>m&kX&LiP@}a?2*db|PMm zQ)S9QnPmL<>pi!r2PX8STF;xK&_;+TCaw#A$b2e2r?f0@VQWD32eD1&r_mmTON%N* zKB#YAZycovnjMmF>~Sc6b71PTpRip<9U*FkedXb~VKognhv8H-JE@U&%|Wwsm$r_2 zMjgC?>U%`iBPNydM&f^-x^MyGBzO)LkGUPW3+~JuE1@y*y(avE;I9{CCPv75K%~-d zw_fm5u|=xtF4kep!VDG14=~<=kvki1*t3`a1b&%CC9ZJ!W_LiMes?voOWX0jc_h!q^ z7dj`dR-j2!Un6aLCCcz~Fjahgc?WfMqg$igv|>fCOX^gkcgN{7^r#{UP&!p7LYB66 zhWl!E)6YhDG0zIM78&r-#;KF+n>^pLd+Cz#ME82%q<0ce!=w}pdqolzDRMkxQb<`N z&n?u40-*l zGiY;sTCjERXlu}fzG&l}!smP|KFK6S{&mKvQ_||{hY5?20gW%48bT+J55Ma^zf)*3 zfg)A+S_+O8U{xWK z5zb+V_NTU;dP+Gf(=bC*9PfJlGdwXDUhQ>e{XAiq(Q_@QowQMxNY?yI`J4(-zJWZa z9T(N4bmq7WNW~MPQuIGcyHi5O91u27mM#7HP3m)+&KT#=81`aG*4K(&{&p2XB$1uz@kM2Z=he{MmT;y_z)&C?9=V*N zmXWa2wc&Qdl9-BbYrgb;fB$R!2koBbV?*YNYgRJHiXexYYP8P7+djr*8F>IZZ%(}% zVZcfL2{*C^*TBSQ0l|daA$moR;peVW>qg_)rdy>M-_nKbqL~_p%Rgtwa}te5foNMo zo#DWQLcPoC-louf=s64}WR%$j*11i5pLhq_oy@co1J!~HcL6`4YF8Y|ow!rN$o?l2 zUa*Z6A}!b(1-0u8vZR=}`Yjde9;TU|NNq_SdK(JgXCz^`EZ)b)3Q<}}O? z!?IL(#vws;t78-?G1&K?ybHeK?}M`HjvGzaz61~A+~ccW%Kml)ikFc9#?(*h!j@wU zq&k$900NitRQRk14A7+j-a^d^D+=iBn@ucVkar9E7-%AE$ITLrHSCLEZKWt0)L|Z8 z+3T8t6ol)_gY1^xPBH`iQe|HFHlUrG8m{a@%?F|zLz@P@8;0EEfeBzN%uooc?I!@f zPpAvpD!9wZRRr6v{XM8YT-3uPxndginSnCb6+J@z8x{E=-byH#4kE?bgv^EL7ly5V zu{Y$b`^8F8U%MR$;t;#1Q9KH;A~ndC3VatZ4zr6pB0g&hfKz^v7o!$vD$^<+@v>6od0>N z8gwb-aL4{Oy-l>0LY4agU2=JI9N&+aF)NoThbyB&GkXccPmXMchJ&lKLfm=O6SDR1 zlJ)@f!yT?{e$=;s{~6Rp{H+eF%%k_T>1VtwP94U)0UnP1h$S#yJzal3_n!jLNHFFS zJWe&`fOHJjDOuV zYFx>_G#9tEz=s1e%aB~19B&HZXYbP`VK@A8PSRq8y{=*PJ8YVv5NX2FJ0E~bR@Yca zWc0@dvcJn~ko^Anfjbf*R&%vWP^;vTpYSU=-pS0YCe#0taP_S{{@h-VhxvCxG!Co1qTJ>RtI|mPXBPvOiLmtUC=r5!lb_7NiDr z58^^X#l~2etP<`T3O-?J+vrJ)1bAm?(Om7F1JY!zExfwe^WCy`cBl6E&spWiJin=X zX0^*A2*eD~`dl9Iepd(kfkt;C{xa-yQ$-a%io>V0Mb@cmt?nfygyb?ya$swxWK1d9 z)MJ`tMnqJ^*mY)nJIh-!YHxCA5b(ie-+CDl=FFK}!b{^G+sE_uhCaU5_5 z{OzBfEwco3UTqY!^_7PGp|Zqx*sJ|_l36cVgN25is*Al!`vTofp#zf$Q_pqtBlsJu z!==@a`&A@);*P+f5aFXpkgxv1Wn@twy-L8CDaSd z(dm;59N^FNE13skfC$!fd@IIm9RmmG>86*a5!J$4w(#M?*cb`jUQv{~r&3)EA)!V5 z)*LILev9x3F{>*R$%b+Fu7pnmBoA&aU`5U1pI3~V)d-_B5;7IwW%L#omrGy3zhfY| z+bnvHH4Tr4rE#ZmY~Won^kZ_=ZUEz1sevzpj+_cVGdG~%ZTNLN)-{=NE-1_s0a7}_ zBz3V&iVRk(TsGI1K<6u*&v_pRJH>YTe#Y>B2DqU*qbMRPHo*gNeF7Z0y@-UoXhe=T zlDpRs;S^y*Ko@4EJ}*Q>a>0yheQEEW46^_RLp^}ovtHX zv0IY89 zZ*cu9D?-OFF?+-*1ol9aejVXDd?n+2}EMF|F8I`7tZ31UW z{4z%MWS*n3;saPsqq}&eI4uFN_QyUt=-+5|yxLa(AR0*WqFgNc52uTtw2r8YK%&vS zDhM;`NnI;QNARELwem;04hR7#q_g1Tz`^}@&J%!d3J!QbI~#)G8{m@M_MeUvck8*f z&Cba2KF%FPMQk9LHvMwkFH|~+^fLya*r3)?))nV5HDWASg%IeBj5T8*^>!>;B*S;} zJw6!9X|(vCkbM~^pCLIukiPy3NmQq*Gp<+$* zMF{8>Lf|XRJT(-p*y31NE@_zta9(O8UDnId55p7FpmZ3XspH?X=8K=GG1D`(hd#YH z=P2ycQhk^SP(-dHyR+j_>=xEEDgo1MAHD{ushRV&J;{pvMkkuV`VQ$PBOmQ6R5S1& zTR%2A0`-0}C~~nt7xeF{-2XSp)ptpwRh?f21Q5ipR}OFJtGiQ!G<9l*Y(yM{(+Y&(sE^(=zcO=lOV`sQzoU3)?c?&_AXxXbizo7@LXDuXk_>O@` z`I4lz0u%3sP#0c*Q}_;Da%ImAhJv0;AjHE}w}+$o{Z%02A}gxUed1yMF7p_5#_VL^ zGW%s9fPQ$S1YNA{W2;82irT{=P6G>Ys^i90Iez^sg|)=nxsUOkfeSR10L}sxJhlKc z?;x6#0N#19QD_fTH+ga5g1dc!^I6t8FD5`jE-3<~e-zlfq?Qr#^VU*Xis`JK?w?cb zm)R76w|&GQ@A2)%DTRhfJ{{E549B{x>akd>-%{h$0+vk&;Il5TNsb$Kw{_rnuk`|& zfNux?Q{My&WUUXCjyF?-OhZh^P}#r&AFx^G@Ao5}zltdr=v7tV#oef3sZgRg^0)Pl5WX}A)EE*6{mwmS3Ab+B8eCVci(}tyWi-0Zf&yb z{r%gKb<50Fu%QYqruYW~PpF-@@K3Jlx5FxGmPmg4my9Hrix0Q95<%()(g2od*l!eI z0H4@alGl>1V1t8r$!TYwcRJz7Zd(;==770FVR;C+^|Zh)eWL{3 zdDJz3wL@Q3xI`ELdp+K)Wn(o@f}{nKS9(Yh(lG-Ke7|Q0D3!hf|me!X|nYMhA<2%9c3Iug` zOnpPBCO`A*KY&E&2?uV5O;NftVylsA(j1XI%Z$lMRt|wZ_sf)cnyPlmJhBidA8Bpl zVh2#D1GnWc=PMv{M%%^^r`%Nf|Kk3<9cyhiFGJ>7e1x3I2mW-%I-_YNWiU|#_DR(# z2Ljd~212b_{QF>}NNhC)R^3UEb-5jN-qa350sVglUv{j!NeOccWw`iA${aED(du5+ z+3*zVze%X5iKq_`7fp;^(1%^&$TMytNB zmT#5|iqs{=?wQ#*ZqWYn5O<+QKpHI>T00i5uvc`@4ragMOydLz&czrllNhe%eS2}~ zYPw>g{EAW;A|E(xUf_0Slw=0k<)bc=4{B{P&?ULV5q4&Xl$=+&-}{+}NkVH})@;&L zL4Ut!DRuc&{UjCYIfLW|`gfyxB?(EF2qCUSObPx6J}q2QOY|CWGIyxU;?PZXH8c_MrxEyom2{g5E!` z1&Ys>4}+A!Nbx1Tx{`Rr=U!t!8#<1EN_Io^gez$Ox+uqPhy+7~%c#)!eCK3%uc$JQ z5Q=}&>ig&P&gyfYPs0G{Y_M;8i6_KKR{hGfxdmj^eLad6zU;SNcNBEVA#>?*%ObM2 z3!(Bz@x@AkL>9#aFi!oolzgs0R}wW-p{WCw`+1{=qUa`f*pz<$*TYO5RScV=?RbvZ z@~7C&{D|lju64~nr`7jzi;zxf^BR3e%&j9|;Dpxs=?d`fetWnXj-))P9u;=)3Qu_N zAk?%LIP{mp+5Bo5@YwU0wr}p0ysXghR?a+W^#Oh{ zzUWx)31pvG6a`#z=TOU;?Ch_;1u5LiZ0Ml2*79KB$w~;Qj{}sI+j>#YSV4jI(gIg( z5?BN0<*8=S7Ubd2!bEV5NJti8gk1`ke?RQVW1!S+VY&S}=`celY&Bg@eDYF&?qjmw z2cKJxY-gY}%(y%yFn_7Z76o>#0PIirGb!=NsM2}~6DtxPMIiDHSC4}C%hr<>i;+jo z)<&e2!TQ<4gasxDCSzxMsT-I&OtaRfy;HMd+)I5n>%S?|N5@-x#_e0Qt{w*N3U45I z%F3yZUw2DQaKE9A=U8O34Koq^`uNyWeS!?t4;=gAWm8JnZexC9;11D|ODxSf?Ve08 znj73u*(efz^P7n7RpFTkVYbw$!Pr9xB>pV{+*{cB(;t;Rh;g zF}Kx_iD&xeJ2CgE*&=#f{sW)^67}{;49Xc6~RI&OYa>kgY6lDoF6@ncm!ppAxsNT`eFU)b8ng-k%H z#a>POlkW*)7y-ttj!#2K7%(HVh;*qT;|%9;mrdgjK*w;GRD>X2`cn7$H(LWnf3xHw zOsL@;6(}cI--5sLT)sg4MD`yvAx4{PM7`QY#pTD+M^6AoIW{o9ZpOLn!(S7zr^I$X z67{tds;AhgZV_PeZtZ?$cB%mwVd+Gotu^u~C@!4aEi(5m9UpDmD=g25dFL^D8};ze9>uTxjUh2KVcfQJc{XpBI8w zBYci*(FWNLpcPdDoBu>uDO3Me!hb`YyuAYnbXumjP!V*M*572VNqcbS_2NFB=d%zO4{v`#fQ+%jNyF}W;nwgLKG)PwJ zf%71?B9wjMSw;-#omsU?Z4crMl8r^WM5~Lvl+=0K(ynnL@IS)I(>|)BVq(I=XojYL z#Mv{n$UQZDu5;^#1{W5b>nT9QZWFMXbHn2EwY5F=Sl0?{TN{7iX>-HH z+wRLn;_tjaIm<6)qlBsuepT#-h1(&F2PTqglpzy61&Z8q5!+=~rCHE28lD;S&*t%O z=E#o{%{aCu{Kep-CM0!#kEz$VAe5wORhy|2+gUNc@s8?w{}zt-Vl@H^$h?I|l~nff z*ZHUsk4o9NDv~6M5P#XTyo7*zW$_AhJi|~D23-V1tG$%C*wwPY*L8bArb%Ew``60O zU6|Ii>K#4n{;I=KeaF|CEv3}$UG1|r^Iju3p+vR2>9RhW8%)>t7+sVsINaLwN<%vm z9}x``+S2gXE82>+wIOFLHEly$gg-REfD6iEd-MOgNA0llm}nn1!%X$7?l8g};$OyRRN zv^6WOk1YZ;6{6tvYM(A#PJk;???7OM{ZY5F>tYb$YIB()_~cbapQucC@$~H>5XuOi z?XJDqOM5)}7ywNr76F2`l7G=izkxS*^b-fyYS43{Y`cc58J!Y;YbrD-*Pq}9mp}=N5=ir1M->38u4R2u=M)#tz=JV0x z_jQWdT6jnl0T?b4pqZJVIVo*j*kHc>7!M4=iXV=(ZyyzCLuc4&#=lM?~vi})mbR$gdjtd*p^Af*Y+K@j7sb!w#89^B#*8>DG1A=KxYH<0-5w z#h^-px!2%S57#nW;!%YzIRet}XAz(v*|~H=fn7uT@F-$&q%bV+7&fvW;Lk^MZun_2 zdBlTh?wBjqmL8j%3w!%GhhDrgy{?X*2FV8*GB4*vId|a)*VaF~0KulZUPl+rC9G@* zVAKzC`H8wWQ@nett?zzD!cbB^kQ&tNNKkGE?|!_AE*jslwaqZb$*T?AkGX-S?=f%s z+tkGP$&AzU^}niH4BJ5<(}^`GDGCbGjIH4ZeXk1WLp|L@Z#W!7`9-*&jmx(ew*GOl zVjNHq1Mv?+E=c$G|t?l7$c&r3;0M$#fWSfW#Tx*iqHODo{s&MrH8wOUHRlQ@f02~U_ z@F>iXGTqYb@jHR^s$}!Mnh;4sY*Bl;gq;nh@8+%gJ@r)WjuCTiCD^$d=XS0aw zCn|%qcDl(^hBZKnW*oCvqQ(oWKc!_IPM7LULoFiTY2K-8|HwZXRShr(78#ZlJ70pH z?X*4};|dC%36Rk+;A(be$z}7r!%#`&{|rQx<6e+dL}d~s8r{e4_NFolBY+w6ivN79 zjY0@eynWTpIb@|A@ZYG4HOLc!5FLNl_%$FNdFUHK0LXXa6exC?&{NHx|JjfJ{(%vH zqL~zu7AKqr9Ob_YAGbJ=)^Tvu0A!TIbs?*=pv?gQ9l02}TNG&yqvJ1GRS`X)>)~^J zr;ScO)6`7|5sSSkZj-cq$%I%`tI?`&nR&TFVZb;F4aNiE;WnsL&7LdCAwjzLdS^0h zkq8Y{uLy&ol5#uPm%f1_b_+=OmYKd9mJfKBVbAJq&iP1s%ZlQwcW|$dGci!{bCSh1 zPGr3RkVTTc%b-F^9RQ{?b1urq0nczpT0TvZnoBR5xAFVMX`vV`&omIXM&!vU{Q~KI)TW-0j8p@R-662WB&1Iz^{$Jm_RGR8fZM7Sf8;{+pV} zu}|US;_jo<^d7Oj6b$ScGOJ}~kSArLYM-@vyCONiul3#~=IiX+0!1y zJap(IX3|DCvVz-Dq;Pgn2W4f&!@#(m=+F-um`5l2DjEMX_`9{@FT|GvC?=SG#=wzM zTSa7e_pza1zQDCVDzaYOs;e+mh29Y}y^5I83pHYU{#7%qldUZX)>PGPt2Tb6Hxe-C z60=-ehCU4kP^i-zfa}nHR5_Myi#Iff6|%dh@fc7vKhIIFKe{^#M~LY_Fz)ntX&g4 zth(M**_5)OAc>mhs7@QNYtKlyRu}>K@Vh;=Jh<_&liXd!wP`{C<@`Pk&8dr-q8ov$ z9~xGL~8cazR;~&qV&>CrN`>M2MVD=>&PdwpDz)5kjc(Cx>?;XiVM`uwbSAU}gdZ0hgs;S;i{0m}2; zl$S9p)?!NPL+WhhVNgRvcMeBP`>THy!{G-U?>y(lrI)TR6DGtTqgnB2%Q>dg(>8Q> ze)TIy_;V1%bt!d!-`f8fG>cs<3JmJNr1>TI8S~m1j(`c~t0QPaiWvJV__o-7aD>hD z7j8w}78Ks2TZaGH7CUaH|5ZzGe$}THu(R&}Z5?Qh(E;TaRYi_RdQ{OCAwVKgZAAUy zcJM`M-c&Oj3;nwF)mnApb+C;29Ikbw!!Z1zOdpNMR7k?jrM|qp*Yy-51~|?PZRhnT zt1@OBvs=C2=`Gc9(+loA)lDJ-o6oYH!2EZ;ZM@wa%o$-58%0-$krdx|F=i}O{G#A= zS!-HMyME@6#3h&O%ZqT?g=z%JBJ-k_8Ynv^_4G{0uD^Xq_K>(Tc6b0I+Mk{uzH3o*Y$3 zIns-n%s0D2yBSH{hm2^eKctg&0Ytp=0@m{dR9r%-??PoHldkD0v%U?xD z_PxLxE@efZ(+%rqR`no^fm}gv1NLxiBY=x_^$}cn>u*#9ZC8t=)`mMBU=i!t2l^GC zf~}CxB?&?wbj?O&_f95evcpg+Bi3G4K~foe$H5s_|JR)bu1^BFjjS0fZR?|__QQ;_4xabBq+C_}N)DJPFojS} zC8*58hsopcJfQXj_eR!q0dh%4$t#*;&3ITuV?Ke{{AqvJv3zG+R4;I3^E}IotmM=k z>EH2~GE*7Ad^Ehp+s_V815cL%Hv$nB0I-p6CbfGjA94`ILTvpl<(~Dgzhh)zIwvq> zu>crRQvdZ_wsAsh_giW`mhGeG;8%9eGwj1$6|iR$5HbAj5NT{}IK)OLq}ebE``Ds~ zi(8D~i@{Ur*2+{N7Xtj8D>_B_pTR;0Zmyg*Z}M0SJP!lJ3;{1I$~8QhpxrE#yen3? zw~@TK(AdM0XmRFTbRoG?r~HiVV`GXhaOy)9|GnWiBvxww8`u+1H8toV~@Ju zYEhA+gBWN{u=dq;yf6#gzh$%J zW8cp&s#NMDatrf!p0hFp;kO?*g*LnNnEX8g;xDg(dqIXrwt?a1Rx|?Bg%f|Kg=~$a z_WEpkBZ|?>>_5^-(kLD2Z#&kkMyw;O-XHqAAW_=A3))7%l@alxM{(NXcRBTJ>~z(! zG5D3(m?}c<7!PpFras56IxtPIX@i>@Bta@N!rfWA2M*remZKMDe=xx%GR3qfpH7zZ zpS7cz^qVJb&DN;!|KW`w+ftm`;e6U=ZGC$b0kj;LntQC1bxY!uraAR>cUi4cWDCBz zl}a=-moqqCThFa}!Hib3vn4`5B?r0;m#tz1%8yCk{pPU@*H4!{zvC}8XG9VGQQ#e_ z(ZGs9jA+7jCtS}sU}`Gbj3>qRprvv-)!<=~5pmo778z?e=YBE&gYS?n3RpIUm5A~2 ze}7|*cNd9{Pdl#6u-)%IICwMY!?!)?i zxb zfCJ}=c~1cc&pdpu;k4@?gd2bdqB=`LodLZ~GvBE`5SZ|+tzhLuSdM}6hxUL16_%1u z-jog)ah){@k9{Mm^uOK3IpOvV9Il>CV1bB$tPl5eo0aiinY63JfY2VEt6z9D*6yi* z77wygx^RNHB+WF1IlmU{_LW>y8Y}dpCHs z-1}{zhBtF!{8u{v4{y|1l!VRHsU3dkm#(^zD zOk!maQyz4>?Q?u2`#DcKaRJE;2So2u15;=LCj66dh$LP6UP7b~=_*p1`0QVX2X>S} zR{&UcEY6^~P%xeGcV2T^)*;|VovBWFl1oZGybNtu2sA_k3sP{y&grsFYa>EM1XLQ9 z|8e_I(5Ha{pQ+T#=AoYVoLZmn|UnmKaMCKb6u2t|i`jvO;g zTXNs!wwbw=Y=+p@j^FS3{@?N0XV0GJ{k%@}(-FlEi*|H(vG>K3eY!eOG{}4O%3jEg z?6DucuZKempQ(h9WGPG#X2RcIn?=n2yQ^J#_`ZDn4P*nm1Tp()6Ydo}mh?`9Y4b`0 z^L$fx8r~0`h&W8Je-EfwqEr&RHE5~~t2`ub6G?2py_wRR!V)u|I$nMgy-F|e(WpnQ ztv}8^Q}^x&4$;rwk{{BjGB|>cd3M%+wRjQAA-0>JNRq;%h13gDq_c;YOki1vt)g<& z(@QFwN+6D9EXu2O;rhEi{3fD`zR@zWFa-Vd=Oeph z%c;ttUQP#i_wz%kpEp&dy@ADOMynPr$TM8|XQlYrxRZ|K5dOlhr~goyC2^cH>Vc*# z_e^H`ju1s2Debo6EDmtr;V)xDP6z9*!#^pTCF4>;dde_78W?7iEfVlv^`!91QE-JW zQjWQty@}^h!%Gj{C`_`MwetmW$QICZ?$RN0$Wf{81%QE%qTo~D=Pmd&U@s`xhH-wE z1?^8tS2-RU<)VXCajz8-Sn>e?AjGfuLPW(tleNJd_6;4MbyW(3 z%m3PlatKuG?PRxW+jUJLF+f#h5_i$j3o9ewkxtLxD_3aSDTf{;JF1wL1=plxdj@U- zmO1O;u>0i@O;98w!T~egA_|O&=KBfVKa};Kyfzl?+L5^ zm((N-*6Xq5d1ZVfU)(D$yD0_;h2ffgWFU-9jajlP@5#9CyO0oBvZhsPyq2`tD4HDruucLvu7Xqp>m$2MP*0i^mZw6sxIY)J_Jgj&4Q6<)kq zB82P_R&X*bX{SF|kq>ovdq!9sp@CG_ziR)=*lRARy zCFKn5fz6R`(AdU{?6ObRw5du zS-iN>bl2xaGBY0hu;SXF3#+8#c%xcW=jyE0;Eg_;l86;1 z(z@N7=$euL2{blDF8V}L9g0kUOE3BvI*-~1H0J}gV4j({juRIsUxI9xO3pp*0je+4 zBegozX6zZA3G$+I1G}{RGh&+UNFSQCvzSIoN>MXu!! z5K3Yf?Qhi71oGEzaRFQrT^t&-Y{&be2B+wf?SGGD`uV=p`97gKAei_rW?7%VlaT(B zp|x&Dbb~tEu?dQuqu(EXtx$OKG@>IHOw&(CigGnQ!kzpo$Kb2bg278RC!dc<#R8*! zbTjO0JKpY>PVi6M+gf({hQrgGf&ZWZ@_J>hY!xNGWmP31+@ zcG%yo5+FmJ`7-WMINa(#`^OGG+KO7aUWGf6p7|&FIfGdhMZTNf9b{|jO!$MADAh;V zeHvJ?o1ehr%6vI3^_laAb%ozUrIC9~64hy3lU3qs80UsL#|)|4Ft%75KbaPgAnI1% zng1rutXr-kJhCk}JC2Q6Okv4Ui0K@?6;Zi0T*FA=1Sgn2@v7j+stMmP`?2xwfA_ zG!~MTcXT9YLq^qqPY3IEgj3YS?!=RVf3*S<-qJ7I1#U4Gek)lp z7p$F1-=G#==;4lEdp&l6#IC!MD*Cn|D;#`QN9Pe`uV2cReh;lT{L?Fv!}uwFKq@gfFDpUIA}0l7u+#uuBmgxpIv9Z(56gb6eKvY6&qDx~3l6z$&yf8rS>~v5|7Jj47kL0Qf7q}+ zG!lJ#kLqUE?O_9~?w*-C2tXBQdrHP{GE3znD^kIQk8-W_1WweLsz{$AqbdKOpd-SM zy2`EV>e>_|F!|9%#XYopJW@&amc&}n6xrr;8e~cx(L5@LEH5)$@@ z=#E_$xG18E&A9%xeKAibt9%z6BOF~l-7*NPUZ3UP1q-NS%0Kr)*}>pPFmzefP~y+) zbCfKHpnkmCI&vKV+zuti8>ZPkKcA>6&=wgeX`5{RsZg}0}n2iheGL}nT8J%t3Ybv|b zH0Sjk>9jwo&)OqL4J8ZDpIaDwlNoW(?04Wl{q*gBEWPcd>d<9lC>UuA47z0Y|L&J3 zGVWGAXRL*+k45L!5S1XkDNbq&O6-0_yi`*AI~STTCzC|f8Ed(`-y?T!bgN_jV3KS< zE+iZ8@#|XmQr5o;i=fARN(rSrcZAOb zI^Cq!7k^LD1ncv~ym5>v7dv^STiR6C(<;{U;C`iO$k+QlZyH^IJ=T70f|pg1 ze@p7e567o|eAJC#30B;Ycf-LgbLpdp^c+L>Nog*CLuP%6Rd zGcV^mD|OwZmAZ$kr29(W64~UN>eW*-&;#=f#D<=Dm;M8q5(^R45=lIHpmu#<4EF5k z(}-2JRauSh?$U$hJFNE86@z!dyu;8602>YdoPCGZ4mQN#chxT&d;sYV@(S6F!ka3> z&xD@z+K_QUN9KcdK~AqF6vTm&ZPI)B=RjT2`bxUTsxh?9EwmxM!J^+^`BFj)28T;NHHA2HT$}$uMT$46cLwt+6Q|NRG zkUiGa@JK2C=`8SVhk2aa-s1)(Z~86=>0BC^qB~arblCe$uK$G>NMaBWjNx*%@EV|b*3u**fq}dDny~EFE4*=-dwq0!e`bMby)Xr+7jbNd|k4jvvoS!^a%wm}BWro=kboxqzb<6^a_LASWQ z0HwLA^T#v8a`vuP>p-_t4R5J*0j3@Xn=Pv`rs_B@A!a`ee4y$DszW)A{}Bq(m7^|= z1cw-(^B@?TJHm3;xL!~>2E{r7vDnQ~%Uokz@t+SU+VD{guN$P=cR4?=x20h|x{o8S+B$Z&| z?hYi0FH`b~jah3d>aL_7fEnGb;PfStbJy>lbB95ijVr!Z9gzdGj z_jsS5zU80&{6W;@xa(aIg*aX40|ysXud|8Wax!eb3|3iD%zsmr`q?T%pt_UO4{DA1 zTgE?V>G}B_a0R;rL~P^#?xQ9fYf3>_i%suCY{y0oFiqkppNx1*=DtuchbWrK3rP6c0<2LB8&|!CGSqHjiii_OB{l48-ix5%fTI!vH?*t zOM8@eaRCgnzgMmbFu^4YZtf4I0c}`F*}Mp){AZ}ravHe(1+xKm;Wg{juD(!MMnM1H zGC%sRe9od*B-!4NssuvHjJ_`>t1}4>2_YbQl(%`;%zu$4NCga)13G(yu1GG~p(>f9 zkAWAp%EwpWSwzy-M--C@;v}RM{3(D-xZrca=T`3`10beq^Edk!U+QJs{!ifgr< z5bbMPFL8%K(&tZ^SZT+*=_;GL+r$@yS5`jiO!Aa15cyw%>N@21@m)5#W&gPWHG3vcZXA>CD{4DXO-X&ZHgCZiro+ zLI*DKW$8n0#Ry@j_aVJx?-$8By{g-=re5>R)Hi$J<#^&PpKNz3Gbh!3Q}P+7m1R@7 z8zs?C78K5Z>|^x@>4uGuS$l#3 za$$A?ts?>iy8KaPIDT#YzoI>rg~O<@p6IJFaW-llmIc?& z1(~2`g8E9F4w56EU7~vK$Vt?^?(_$#FWaO(N~vUX_Zz?zQ$A=CEwflq&*}!}8E$zm z*LuJ4eefOmrFTK9hfe(ZdMqSI4d6Y`%k0l6>k> z?_erU7}uyjWM7>&X$VuvmsO*7Qff^+^%P(0xaO0D0l4@sl;ASyjXn0+YmJ{1bjJ@JrM=Gko7#Yy&4#%b) zmlt(xTS$*`F!?qR=`94Fpvp^D0PQmm@q2y$lDq1tUrK*dE)LJd-O5=0;f6dee~YTdz@t7`rB@2j>fJ6 z?cW}KhFZLe@8kOFkt&tP%?RxNpP%z?AkGJ9`0cRqoyJZcYgG2@d9eOZf^!=+c2bI$ zg_LzG4^5iBv?Wwk{jCg-gJi<;-ly+s)H4c$GPz>jvwX~)g^1Zto6Wn8W89?NkAh#a z)uUQNWNgRRRK45KGlU^$dwwrLthpx4!Q3ERFUI3yS>*v5o71Da(~LnWXY-2_0R|P-#DdVNm9|93mv2vWq~JiIc6wo-X7k& zEw`a9=~7>9oKY6%3gt%s33vyrh9{zc6Jvl!tKIHkP-#0j`m8&DZZ>Re!IjzwK26U5 zUNqW$j%&?;Dx9wQkZ)NC<)!@1XL%2@E-bfM+-S>^^^N^b3*WY}s&2GA)paWVqV%b9 z7xcc5MV4Bt;gNOKboVjH`W26=MdxSk<}VbTyQN9j(M^_ulafo=M3(@| z#z#Diz5+*u-I#etYer;fc1FO93bs|v7LEI zIMKJm*s>7yoU1*qPn_)h9x|2|=EXlz*W}zM`2{ZOl>Q^%;k)(NFEYvFA#xwDN?(>^ z`M^8)?f?0|x#BbJrMs9f*w#F_UP2FHTMTfg4>-3FH#67I8M=cPB{ z+tnC$$FHs4RXOA&@%+AByTEoh^NOI`ypGJ5l1~N4MQ52q`{E~^-(Yfzu8>5 zOY;JZOZq#(p~@9U%yMP-5Y&-!grD=#WAk?-683tie23pxMm_lPeCf>f_I(&#nF}3> zJ|~B4Ar>fQq|*<>-K;zCkhZ25Hd5Ay&TNAA*2HV4&Pytr3WL%{{2)tNr1k9<^jRGx zaP_G3{!?E=hqNAsiNyHKB%5H7Ti|1qvwo@;`ZH3#J)(c)SXaZQeOxUsnxCqXUtXHp z_tx0(USos7*ZKLZRg>A=wMkv;Vfd<8mdTI4e^1NE=aNlNO{e(^%)eQ#k_jyzmCr1C z_j@%`lR=!*Nm&nUz57Q>dywR#dQ9sMu}!3e=8&^+&cc8n9Q(wWugF61_Y19G|I;bE z2kH4~+DWCA6=4f~W@E8hZ7G}oPiKq9^oIqm^yW(EtJiL1aPSc}zB-RUF)Y}R4Xeu0 zEzX9@4%0AL*QZVEnx;*A$)W>clGpWSkROix-L3*+TzHE#st0mdMSmH`F^OF}iq2jr zN9`87 ztgtml0FYC(+pqa{7~{5V{CWr9DJNs>Qz|5DNh40>w97_i;HKuogZa5pmSSlBej>xS zcTVCv>_}+xzkv&tkUB!IltGgQx$fQzpPdKx>7UrrA4`@PNp_*-PiAc|F)V5JRbCFh zuV~)r;`S4m-F@-Q9WC-@%L*Qxi4!(ev;!PysN=SGwPRBFAJ;S!g3?pxjoX^ZdyV%- zj4xY8J(Y$%2R)MZa9z`%?);wWCNnY7F?HX35ATrN9=VsThrT^^6MHhR^Rq^jD~CjNXQja7vC2R^Nbd#b&~ z+b14+B+FVkYjn%~NA60*LPGs*1es6M^hLq(Kvq7_45Q>AQ|VFf$qqFRImWhhCpyAaF|3*hYEMEb%5`3u%%e@9X{34)Gtc?TdLw0fZDK1#jj84MGkIzR#&~PyaAuwR9z{_xNUaar0%*P38Ou}4Igg7-q6kYqNlby>dtkB>B+6pum~L)DnqRD$-MP*a~7iF zmhP2`H+?_~X_SklbkVsD42(Aq1hIRz@mwH#kCl^T1NA>yCjqCe_x zlPtEm6R-G^o#i|2|NQ=+4Xr%YG1)*9ey*NkUBrFi({8&Ux;K);N{}6CI_3E4V+HxjRT4uuU2gk{6e6RDz^#F%~;Yc~&&80D`xE~+r zPhS7r4Z7~iWen+SS-zKPH}7|+T>tc!mNSeyyd#Sjx6G5)u|>Wf0?O${c-xkKkZ}2<_$LXclComTg`6+*kjVV zbSvbjp)6JF3N@DUFmvpJVZZ#hg#+S#8s!=vp0_HN&;~5O!C1MVGeTog!=!^eLsta8=^zf-03bydI4M)W#jv=JA!=lf!;cKP@nx+cIgP+F{F zslIGgTP+r@?fOYtX^Nlh!T7nDM?cOUJ*56l%gY2@7|S%q+KueJ!kDYM;7J!42-*>j zF6)W?=&G9XmU;gb-FNcC9YeBfTwpjjaU#Wwvo=F~HplX3wBBMY99gaZNt?$$50rqH zL>;nxuqO<`J*xVs1l3O1mA+)jN+l^N@U)JcM+6SaGnG5Oj_8mE3f^z2YM6NhK#mhM zJcv7y@}vP`(6-+0JiXwc6m;LRAmr!+#2l#bwQZrsUJ-Iyd7z3TJi$pEah!DQ_Ltk~ zcmEXJMyB;hio<3VOS$j0Gk9I6ljiL!9X6<|_!_*siLyFtuh=|{VOcd%+zOL~Jbtg~ zIQrDv!0OL~p{0m8UlnfmM~$7qrMvtle~Cc*k9^82x5Bur>hK7Lhs_vRRC^3HBzwRI{e;L; zTyDic4i-4v$)A&dxrnQ^y_pPqy9hOfPL+0@08y~Z+MlBxBztNhw^1rcF9x&4@(_>^ zgeKfI7ZQJ1&bJTlzO-xCyEJPNCZ_c-nx$mhqEvNQ_zb5_rO-*j&8$l9eBzGIk8%bH zQ6erdRnSpvMmW{FuD9L9kc~qA>8^N`CKP$=eAPSU=!LKkG@BJnhv_^vgvz*UIbqwf z4Xa5c5poMjTE=cGL&_AN8a4Ws%7eX{P24 z_Zm*Xr3Vi9*mfH3V>L#utMT{a{2ys0ghkF8jMelsQV!aTyO#7mQRu$V^=Cp5pk&cL z{O<%QRwF})+HR;aR1vg>b28t4+WbEO)1*f>@_PgxSuXxDsf`!$7{qbyIT1)@R><7q zPi^86BbQQxs1YlLm*jvW_>$uTI(ZG1a;-#$tw{8PGwW}z7<6DtJ=V@HWO@fh9P~c9 zD7pKE`@@Qfd6|KI+KhY}oUyDG|R0EZF>%JL1fW(ICXo($_YYJY0G=S?0f^QdF$kRA_$Wq zKN@%6Gye%{5RL7OLVFF0OnE&xG_FD~s*TLbJVbCFO>m8p2?(D*6>Th4O}NY_$%>$# zTv0Y-71{u_}f*lNXW+o&XGVAM?eV6+TzAh0DJh zulJKz|K#|k(bP|!E64VoAIn;;awpa+aF6Yp+l!flt64OEsZFiewnQu`yg$J?mNdEh zrDZW?t|sGH>Vq*8GIa-f=A-N(h^Ly2lg9&@v21Pgr^!%UGft=9uTt~P6v{_7Ya}mf zyio@V-)YdHaTyGW!8{e5Y_r!PUZ*LegcY;rdU>+z z#ISQ-g(&-o^yB#dKFvo)8(m!It;FB{Fvu9j=`6`kw`&-Q>g?;q0pnDu;PwwWI60pc za!(*&BOVQ#&5kPFuW=Y>_Q zoJP^t)@-sO53F1rQub;YUn-L7km)m3SQlT&iCeXFEqslj8wbYva`e92B7-mnawfSCPTTxk;|$KnI- zC&}LS4H-b?Vxnsv=uol_pdg2$BnDJ;GkePOTTPE)^f11_0va;4+F_XqnJb2$beP2f zJ^6>d{R-(KkdP{Ha(&(ugC19DVh9IHQ1)|cB)_NcF-cCXUTNir8UU7Wesq7}rYq*+v) z6XaGHwfnuyhQ1+y*qA?-8%!nSNIbs&a4*)g_i0jN22Nq!>Tvg$a;n-fG3QATsy$m8 z9H%Sj(;2dh%h%dr^9PaMt2%}NiD|}-DL@<9Q?+hAe#>R%K5{VIx^fu?;)caemy=x| zlWo1$?+o^)@@Uu-JxIDO{~x=|bit|_gT`)sNOirxSP6;7OzC02N8u$v=~;Y%r>^Sk zZOUR9GM}b479}mG+uvxo+=nkSA`Pv%lN2wj3SpK5fJ*_DA@5Ijhs^=KXz1Ei;iP)4 zZ1BHY|7XqSdJtE+lSS;au8-JQ<)lRnTCfU?y;;W&>BZ16UqJ452zbLU*x7LimasAK zYY1=52VJ()s5f*T*^N8vCMzH7wWf!@;;M{Xg5jy0k!EEtk!ec1S{5!K1$2~r72bIS z(c)Zj>t|WVD-2d*kxk4vB^OXRI7iu3D-^iexGABB(*Ol$A{ZS>{(O zUjq{gxhWfjzx5)C^VXIs*fZ{mjY5r%9HQ>ABn7&o(k6~l`uTO)`Uait=>W-9Sd!&= z?Zv+V5zM+8pwN%$b(1Xj5Z!y_X$Ag0QSEQBadrJ_F(BE>XPll{Yh{x`0D@NcaW24s ziFnJTXj&_9oO>m^gVZ0d0@FdY#pOkIsm}XE!+*6P|DY{_t8z0{v{`rEI%;Z9x0r>zv z{DN|MIr!Mq;CV7% zEqO{D#0TSgEs_i$Kw{GSe2`Ra#Eo!N3?BxyP@ z5MKYEfV8F>Wr|3H9>5<}H5};Qpd-HGNgwSU+$eb7C66y&MeCs}w0B zCwDFKx2_y*bQEd?tqJ#k-eD;g@50#7jy4;kvpn@HUo^RRL1k(yU z^N!8pw4vqD^4o#QhRkqeda&$&W+Hn@lnomfN!|8x5BMo3_Fop<4%gRJK)=T-0kX|O zzQJt-)uOJFhB0dEm=^ad@53-dY}{QPim>pHI+JP%-`~^8-6G|CdmG?y1g?4 z92a*-o6^kAEh2JPF+x>XBcGlDG4KA_$>Y=1h4XIZ_gW@!^R6>#boDQRpTuXWX zf(;x@sR?R=cpTvC1x(Au>=W+QmB&j1Qr&6H6b!z==O{xQpS0d zk;!9~Lx;xr%2pN%>4N~t4vsd_`7LScMB_6lMKnr-80RlOp^6#evRFDBRXGN0riKCE z_8yCNM=wyF{DxOfMuE~j`cSuEdH*SPF8yai%~F&|RzNf-yB64gQL~c-z$_Z!d2-4` zHD}^S<4!2_~n`OR4!@pP#NecwD~(Dsst|ntf#`*_ai;} z*UGdMsZF-Ym!(5aEbmI5PgWGZ!QT&xj7q$YTAnNnd(sF+mef`UCyMUc)xBbJd;FK| zpI}&|G$&;cGSb&g6JzEdEcd`jit4^2hS{T_^9q|2q$!l z3|!Lr)4IXGreZoyF>)?UC2C*2lHol6fbh0-@zZs&#kN<8c!wjkDr<=g!8DV9l&mcT z{VXHcy>1Z}Mn^MD-r87B2D7tqzGJEd6QG%W_9Wz5D$KSbr-P~iYHcVR^VrbXRW-&w zz9ez>eaCB@21RAGlPr_Zvio#;SF!B5F#c8qY&(tOhetV8fCQt*rya$vd#P*VE8vDbV&Jxs>+aZ+2depSm!bjMQ);lN%jxjIwDzl=m)+Wf zrJ~Y2rJqnh)Izh%_6jfGm*@qHx|09QWkgl0Wb0#1*zj<@@qyEh-Y$($+5@jNLUF-1 zL>oPmO{`7=dFMtmRMF6(`L>*a6l7DnCmud)I@_c!Ltl9Ij{EC#NaRux4}?19H+8Nq z&ql~f$arl!U~AuyYMMT=PrvIHw~q;2^1C{}Sv5qR$lbQ8;iUsDdgQ*ApQgC`o_v=n zXXOZ~72C*uxe(<@Glj8FygK3&O^z}0$VjvL!9PM&I9bnFx?AZKoMpgJcZ_h0JQQ|6 z*bt1>(K$$mCKf=Hch9qo=KPyHvGD7o2=RmcGR=8L{k5khFFkBMktYO$?R$z5nb2u>7W@JmZW7X!x#mg})x(c(5K=4$#Uq&iG2^7E=xf>&>la)isvT$J37 zW3K16PrWuX2>rd?+44Vuy|^g80yHfzkk>%=U%5D={S5sr10{Hje4TYU@us( z^4cT$!swa8X+s9T=#O{UQ&Le5!CQFaRu;tL_DOSz6z>qu=xUWTyTqmpI z>)JS4=v_$CC1H%t+`MBdtM&4WA9@sbN0Ws5na{XQx!)#Rm&H}K+#Q-T|GkMaxwBnIY zBI2tW=Nb=Q@V2oxmK-r#~MQ+g@&s zbTq;7l8^>v7G;h=#s3?1GDZQR=~Z{v;nd{|?~Y2j(teW~L4C{i1>ih~xQR3Flm_`R zt0!;Ntf)@-&o|)?N}Bmc)eckSO%*(NV)wFkFlrI!)Sn9kc7m zOXi_NV-NNZh&WkaN%i*MAjItB9!@c-uO+a4YG;g-kEqQ?3w3=AeUv77a7g}{E1MBO zjd(2<*$t-V-R2Fo&AiWsmu@_IA{K4X7V>P!OeWib_Mn&x)=VmC0pRPJX>HsyiPzMOu`Q_mbf9q_OHS!jI)P| z+`%g%oC)3L+^uawNKQN5`EpGXinTwxX}Y`8_|EhWh|^DSl@dwnz>=|CDv0yF8IK{gJO;{alWAoCntlXipGlj0EP|)_2iwpog$ON?Kx#mI=RX= z;qX-(zZ6ZE?i1hQ-bER@JX<=_v2nQ{^$PiTvfu#=1IANY3BZa9yoJ6QLR^CG<62VlF_$mezLHjUGVof2WQayN`RWo-tp{Y5^H>b zpv-&5*I^B}pc!%AvWJTajK0LN&9+*@4xHR^k~;f|m}-H;9&zB=+dKaYF$?U-{}VW@ z>hAa=?T<}-Kl9PO%>Df9Wmg_vi4F(|3EoLG3KC&48=UbOBUQ5x%sG<$zAGWC`3&RM zR)@ef4`7?$sC)Fl*w=ny#x3s8KmP|<4PL3(UMiFLZ!5_xVydIw(~jH7d$#(Q`U1kR zM<+F@jF3V|syXzPmW;wMNSLyU{I%TUyU^D!D@A$#A+jz=BvdrZagK4X=BzuqjisJ3 z;t(|hFYhtl=c{4)s6Q-(26Udg*S@mw>!i+3{-IHXzQJ5jjkxX6c6B>%!kPa6WsHDo1AmkPq;-%H^5pqDqPN@TrL=GT?T7) zId?Xnbyl`r$gEP#rv`=Y~_rAU>siot_!{@2E{ROKbq|cxy4fxWba0!!Yes|9IX&8%@cJ$Qc*I5Hg z%69LVz5>U^2EbarjCRpmn;4$q{ZAlPTL!@iH?Odo+rEITl`3mIzQw8TQJ) zDop#P)V;{2{)+SWwXGJe-FKO?86X@fGDl=7_+sZQS?4?A*5j~if8pTN)t5xMC#)`s z-;N6Gp3>wgBFNw*Uf1oYI>ADBJUB!|h=dMaYuMzI#i5luQ|sI!N>nx9&Atg}Y*G9< zQPN&v3_cFL*{#SUzxoiS2*w>hd5RD{MzNZaQ`)&In{03WX<2r4`~$j0fwq9yhaB?S8Dn zX4djUzZ($&mj;ynLcSA@)HCipKa}f{+KKRa2DKIZY9Jth+F4tA&!KBb*P-^-dd@fq zDl8dua|7LE>nq8d%%7?-{w@owZSrk(=XhXff(}6cD(qIA58wj3?8V>~XAD;>k?g{@ z4W@$IH6{*Bqj4Wd5J9O1b~2?L^wMM{OMdm_JFGrLtxXr&F*Ue&+`W-*dRM_?;`G!A zpeDn-%v82(o^Mpx+T&Dr)~dknrKwHdXWBGYC5~0E$R67AsI-CAI@w$9F3(pot~y$Z zZoLc?OXD{Ux5xO3J*mKzx799%TsNYxa`wni`^Ti}c`V9|^jHpa|T=?IUTg>(U2|N!YoT4W} z63bQPQV%UTYRaZjt{)EQoSMS`!Ai?l*pX%)mGRcouY;)h*`YZ-a9r}Z+|)A%bop_4 z{+SC44Y?~RYGAijqnH59V~-5OKTme5|4GE5B^TMW;GH5T(t;m~Y-9eNY-kek_Wj6I z`~XU?@-o=E9Kaj3NF!}I>ip4@((8rHS1Lh5&MNkV!R>%Fc7L`GTkY8L+!wzBr5ixpyT9!^;?3%%-({c|AiroxFO`b^Hrz zh*~2XgVIE5uJ5VG74a~UFQ^(NqN;7mI}L>{$h$0F{=3wy#uvN+wzP>+6a;BKggVbP z7=2 zZkYo!j-48@J>5}a)zp0_;FYgPUES^3vW%-$QlZcJM@3HjO2?z!w9BoU%#Yi0Zd&b^ z&HET9u{NPEUU1uFilwWg5BwfJ_0N`jbZuLy zhWCc6fc%J_gJUeV6PSz5-S$TucW;<<5tCQ`gXM4WvbaVZE2PlyU$sLPkA(YUO29Sj z_pQ|$c+&90Q-?L=T{itQ9vE4S>%2UV_X?siETHwUiLBYxOne4i>+SojK5AWR+KzwY z4Q8h(X&^1EN|E={@aRhZPPALTAnU$UL_{v_(BSIE;LZ%Q{R%}_FLlZ&jkvqH0XG~9 zT3XWk3z-0(qp~^-@>tmBW@N&XlF4b!uv}f^n!~MAv*cuhzzz{}@V>WHk-coTN#K+7d|40^JH$T}ag%B2Xhz((FMuge^;jXkGx&}paUASGy!c&jYX+{XQ5 z>3SCTNQ`+z3Q2Bm9cwX0dO5dp&wL4i&POf!$b3E+_-&u^OLD1R+buKGO+u(^!?U>3|+^yf^hc8%+ z&0YVwc75;U#jqB+AERod)@|i=M28w#?i>1Wo#T6*j`8ofTQ!*LhCk1wZoW1>wchaP zU+|XHl`^J6)(yZZ`y?d5{+q~b45e2j?oK&O{;?7Na(1{Jeqy-biN{%9O4hSz!BWYp zYV^zpUD8v?mz3m_VT3_MSYi1Q)tQ=Zr8ftp=%+-Ts%D!SV65|&s}la4d!f2UqxyP* zh|jF~R^2btp18G>OLwz{Wq&Liwp(wvBY)4WO+vQcv9@NvDt#wtuOCW37YDzT?D&$p z9Yb0uuMjo<825W*IYfWc^1bhk=Y&{cMzD0sUhtR-T*t@|sjeI#ki~~+rRuMLXA332 z&^-|z|8I@Ie;yI2w(2;G50i`h+5D^W=cj?cUP1W zCcX~Ff-6p>p)-UpSiNp_F=@#GyVOn!(P)0v+x;h{Q?J$rGLyzPtYs|IX4mCRMjlu< zj6x#zZcp@|aniR+^t(d4bjdJ#>FeMOV%21x8Uw*GUm41IHD#ukhN2zfX-7V#88>WD zI@2U&`~)jUXXY2X{=|3iiXk&^QK~SKplp2p9AkzapO9sWhqOL#@o+wn(aluzVnfeop7sPz=PmYGpnb6Zz~ zUiALu`QnDj(-eI0BE@V8?jyokDwuV#ats&^`^eh{>0oqH0o@$?SKdt#bHi|SfL7O= z)Gu^&QxQ2T*o9nuN!j4neao}l^3Kl<7&Y&3!}*}sEv!gWDE2E(!UlI#$;aKLc8PrT zh%r%7hN!7_D|KE`EFp3gV@2-JeF99RfEW_i@O%*&qNf?TvUB{j4fT@VQAhGB}W20jd*``4+ z@}<;+?kI?EFSE2r@72ESjr=V5siZqI62WV8g=z3=RY<~;mluw5k82%wRIwQyM7;Gh z)NYdrCB||_`u0+|iWjDz^py4E7Af^nGCdozbgYs~A7YNm)jnz}7P?)y`TX_*AOt{o zrhT0$(>>C^etO?@eUuO6-9m>oeZy-2VNjmemB-8fo+dh*uJ~e5nmCvMExsLmkrM9?L z<_hLEPMM@6P*yM|Ld`r{S!QaeNM_{8A+>wYqM>=X-y9xp_gV0IKBFuRbcQ-p-K| zLxl+hGy-BDG?X5s*l)O_?3Dg?J)aB&Rxs{$fhw8n^?FNDE z!jSyU_{Xor;aCSju_lIqWkxu?`rJ27b781DN&kH2fOGU!}JevIXi?;?t7U1c@GvYN!T)%Am%zXLZ6J#LW0Fa|y8B7a5{lS*H{G@Zc!mVuiUrAMtrgp2&tUHNGl zG?;brmKFLNoQrQ4?x`;|IB|N=&Bj&*t!%<)M8Y!PQ^ewwPjQOox)-J~t}!KAuA%FU zASaO~#l5MkNppg)t(fuVot4d1Y-k$`bs={#L$rYLDUlh>3|}0;E6wM6g?_sG4Q-!a z=t<>vF%bfQocDY+d=;`<%SwhP8XTHYIk?LTf7`@Z^Ey;=3qRL8;T2 zX!aR@tznUW)4f>jkJbGzrlGrh(`L1oBL}7uoyB$cm0yun@fZ|fU{+h6!mXjTv|VQ< zrfPW+m=)=k(qwVeOG4>Kt}8RkE2=QD&_nd+JQiuYc~OBbvG<>v-6#3?;qmoF1XE3W zaNYT3=l`28n@HfkcGM;A|J5b|<~%~Is858}37p-DZ)%@qeV=s6byjk&=FKmoCMAT= zQ3ozq6hZCPl%0PP^KmTvRo%z!r4Z%bKNRB{CX$m=uWOr*ZH2^`u%E; z2Z%68T33&`Zs%q^9fA(hbpDxfE054NuVpf9iVd8>D2ipXwvBh`>i`dfnh&6jlO|Nk za3B1}zAb$Y_M+xG;ks$@wttNdze0#Y-x)L-^e=`~&wq`Uzk`vbMVy%(ww6@j0JDmN zdR@yQ87Fi25`qej(h*%8HC1(Zd(g4gkO|utcP-ru%I|ZjJ;1B2dmhuwF6@u<3tnq+}`j(^W(`v4xqz>FDN0+d8862SvdL6n#i(A zkAy2$;(qWbI8K>yA^WJB`scyE62p?fN!-`Eg@G=tVFU?s=h3$83pbnuwD%VKQd#hY z-{SUAPU(CnZ!aCR=w|L4YUo7Ys;Jyt&zsd%D8{6{L9c)Y&Okhd=ZF3y+5SKEo5a*W zG45Sxjww=8B10!_g9TsSdB;CVU10@1$VY^t^*?v`Ysd|L^&fc7+IF<(%1*qzrnUIJ zDsn+VQz<8b0Q&-}NNc-QbZL$lrM*Zk&_%uGBXVYpVyHfTq%YCeF{oZ*o9u|?Z$yba z(wrloXj>2oIVVrAH_Ex^?y}iIFMks<=gu-u|9s>|BKR-%+$$HsFl&m@VI7Rn0#$Ih z!Xm%O%4uR`I@>Z;C`!$<1T_a5v?SzhW0#MqZtT-dpTkcrJ{`xBA~E9kKFQ(=N*uu5 ze18|@8a3IZv=Hm+B#M#gRP)1Zh-NPskOeW>FJ-k@%fqH3!^?9^tB-E(b$Sk%a=BM( z$iN)10^a{?Gz9fptSdx5aAj{uQ;x$=gHR-e*swtnHj2f8~@(fKV-TfigCmLnwG~byxdv)AD^u`;H zIXUvb=q06^OBzxb*ZDK@&+ul;twpKEFr%4PP+R=hSOPms+`cK_B_pA&C%7Oc6oj7# zDa~Hn07MzeWw{5Nlh}%9KXH=-y5eCTOK$s73VS+WC)DKE_Ar7OY4)G` zz8f!3AyfVU#=d3{9ZWr-2cDMz@(Z~P5CE@n9Z&3zkTD9k{<|cJ4wIhIGjGY(@|K9kW z@!9eDsK9~Ldd6QdkS$KPPH6erlKlEWP;*W`MZE7)aWASpAkR&`mz*gTAj%JtA2Qk6 z_T%Wg_mVZ_i~6#i1@`beE^iM$^@_Pgxg%@lkHdR012CDHfgXJ!+rG}E^MEuDq9)6- z&t47w%U{@TU#XQdMFXnk1-*K1NZy7=fbg>7hedx=8EjE^ZrNi37J zJe`Nn>nrCuW##Y8d(>cG52xh3nS3{3wSoNl<~QymuIS3{xz1&m&AbzA6~;Lu$g%NP z4jT`we0_ew#@iK5yT3f4R`=BcXwEH3p+q7b0#cmf0HI9<^D2u2?0h$FLB+|$w)Sod4~7&V-Fi& zB#5{a|A+lgJKlEdhXsI5aE-krnitjvrXnq*RuuCS3LjRk$1K2Ud6dk zCB&=S5S}bk*X84e*3O+)MV5HCs$n0IL|sO5I@g?P_3~ylX`|k|S?Jni%WAbzUc60H zgch(G86*Gp-=df^SiPw{E?&ZF*mZ-*CnZ2NkmQo%kLzLj^#^LVSo}ORj zqEc{yei&iNAq`M^ySUzUs%%5ARuJy$+5c0wU2xKOoQvS#m%A^`D=}zvf3I5qdqF%d zVYD#l7<*jj|EI_L{(9zo9cDv&oc|LE(>r^6*%I$Kdp2fMOP@7SV(3a3v_3{0f*$Ob z<%A#|5ke1*tTA$RoYEt3Q%*rM6qU8|lp|punH+=WYh8>f>m9mj^7ev~Rdm#ZV5q@6 z{c*jCII;WCHUIHKPI1}u;v$)bl-TY606m3DBZ^ASdSV`W{KRtBM#+1VOcQB}(bI0G zeiE<5;w$H0TxD!(dG4i{gGe{AcpslIJ~U)$L+hLrJ^slzrX)<@{~Gy zCEP&1%pekY9d52FgiY5foE?YlWvu?486MPNu}aG=t~MH9SdW|4Lr@o^M;4cj&_t&o znQKGT=M$-D+f(a#x0<3BSYwhQ1a7jbBfAC_smdVRN4~{TO653({L9@`-_sp#_P*L* z|1r8^Rr0(Csbw10vv|;0C~GyY zTw))IDteNrV8FO(i0Xb{znt6K^~c>lS{f0qF+c7vbU@$EddZj#nmyP76stP+^+2~I z8Gv1#%tl)+m$FY<>Z|YGE)d+u?rE(|k{UMOy%v`ncWc}REeibXEZB=h45D!R3j^SB z@eBelDfI^CiR3Hu(m$INdwA`vY_ML+s#C^U9|67F&MNjZg(x7LV+WgG&;4Y#!_1>+ z1}3)ex353#PD}%k0$udy4ve;8RxkAb*C-IzC1~$~WIzjD3&d!a%!T}SLU11Pd+i#w zA5(3}Z4^sjiAbCPHdJ}X^-AWlvSY%vcwsi{T@w$ovqwdH8chVMs9zI#kjT3~y4mMx zM-P4sAU=$BYMfS*>8_~`8efwq(8Fu`OV%TzT<1R08RGNDrGJfne~=}EB92wUGlzfA zeL5BNVlGXgp?_u#^C7ajUtaLIk989h9uk_s&D-Ixy2zVlNy>8c!X`l{&@wX6cb%fM zg78HuvPnYE=zCk^F>3T&s`kohRg!kpZQEN&lxYY@-n%zN>A{7T75ck65r}P0;JssT z-{t0p@Y7J@jasD-G2y6L8L&ay`fgHs6NAX2? zStPj9YVIZe(yU>V+XJmK=eXmBRUtxd26?bD9SEUF%X^-3bjjcl_$V8NIXkUr1U|$s zl{Z_kd7Y4U%V^I#awN~Z&~ph%t*V<&;1D8T+7C>kgV&-YZ%{}4ihIGyrET9_!RHcy z_}m#=8SE9l;z}orZSeLpqeiDs(a`PwZtf$l`M|(#aG&)W;*;8ZLKq^IULNMxD~N zWPNNU?=PrYJ*Xn`1qY9%|G05B&ai0D;}(+=xIxv3gZL7N<+c06GW+5wyV0_avQ7g2 z)k}yMA+Lv82EkrgtF=j~yn4tf;!&C{!q={S%Qwn#@hp3?4)b{h z(J7|q%PuMc@@9KEFUpV>$jy0&T!G^T&Frn$*`btZr5%h;1k~I7O8W8(HklZ?^y7gJ z2cnL75Ja&Ka3E&N>WY6G-+~8(Wx2}DMS}-l=N{>Xci%;Ck>M1hS2i`i)KDOOysc1< zC6GTyG2Mu@bL5;l=Hav=hmsKXX&5A@R~DUi(Y8mRwBBB7lFB0#`*4b2MMd6VtzkI^ z^x}QK0=cAZG#kDUeM6gK4PD4d9Y8CD5{P=Vz884Z*QV|2lle{SEV}*C)%sik?D4I# zCHZ`@nois6s+i!4(GhEMf*_L>e9|QM{-gC3a$?)xM~Bz~jef>9QkL8^qZe*kwI#=e zZP|mUZOwZAh4FP5o1cHH1_iJ*fzHF<1mU|?9KyzNDViRIa;i4a_65?C6njO%lJh0g zem|!7rE^%3$be*_mzO{lu~+5gILjjU7hC3p0ILpSSBxGfB@fJV7dF&ptIC&6q7rz9 zC*EU+QJBUb#GIUMpPR3tdczK0s5y*v^?|VT3(`hFy&>QZ%vR^Z)#+T7Ca%1~o_y{P ze@s1}q-3k)~kiIN2UcQ0tU*F^wF%CxJ$=*ZSH9E|eV z*d1U12tFy`ytRjflFI?_e@X0;sK@@}8YIY>U*uU6;io)K_0gWZic>Uw*q81)z{V@} zw9hpI?bK4e^1~i}66z`M)>hjWwpS^jcu+C`v4#TB?DbaHd-f`_BtCNNkHHE`G^8pf zhZP)lM-NC7fRNSos;baWK+&WQ=5sg%!K|*`lK9dxbcpU3X(93a3Lj#ySOqEb^-PtA zJq9xb!qj0WW%ul}6tA~P6mA;g@~p4sfJ<=2Bw?9!eEtM&%kACFCZA1NU{2l7{(Pn; z$D8J;rms<839!Vc+X|RijKm9m(y009k0%e~^J#?75sh*9m^kdVmLSvlTa;pW?{XdV z(4mxG{HX9?>ozgl_gq077OsdrXiKHDffwj#rRCz!U;pPJP}ChDQt*Ia8SM{EJhGUs4!hnQ0_XKG}>^-#N2 z6VN*$W_t7Ke~s=$#v~vEfcLzK_5MdIFDTJ&4ViWt?3&)0BSr(Bg!NLa`0NGLQSN{*Bj6S~(4l2|OkwLKF zVrd;o6XCXmV z6H#wBp&vurx3TEWj(zm}sL~&ly#(65k^k_?9J8cfqzJ8%>xH#bqAxh8a zX1*m1-RRhLyGA87^_gzi#p=_Bv3+~%7+hy7rx$lh0c@9CEv0#rVgs&cJy+Mc|96Uz zG{-Hso(Ag1af4vLw&k&iLLh&m=aq9vUzVqX+I6t_6=OGM<4iJVh>l?uFcjq zgauU6wM@VCSHwch42Ml@U))0EgQQ(tQxMA2d84Zbcy6n>aE2IRQ`at2H0*t6<*a|9 zAw-tISyik_eJ&S1&`IQB$zLxzT-p3mO;a@Nzo*DEz@F#mx$ddLfOs`_A| zM>FG2*ndpM6;pB8V)jbAR*+itXhg?~1{IN~CdJ;}FP8d|s2J0)GH+B+ELM6z&jNY?Gft!03$rEk2P_HzJ zG{Bk#jU%-%foJM})}8hFPAGR?=b~JATo&3@rGo<2<)(8ewLEhqi7LxGpjT^Ri%wod zQ{df>+)^5s?aj@GMuApv?e1tR2zG6U-T(fDZyK{qj1;%iNh)7;$+wZ@ycocu zi9(B{U_Dm?wWt}g{|UOK zO?nkHL~bRPaD6>OaLq|VAH+1q<(|kCnBw$jdt#3-Q%t8nTf}xR#6pFpX4oe12jIq9 zmDc8c1p_ip7X2rDp}EQD`F8?+-XQ?ec*OI3`D-D0Cz))#M7l5C4dZ*Z10_DFDn3vz zPmb2W6NILZ+lG-pL@fNT+tp#gjUBXM)phh9V@bj zOR&OVapjb1-4YzN2W|)FCU)*rBtl|wT9G9lZ-5AKZNoozIM?F7^TCW`9t(8teSB9J z5MFW9H6fSOMO^{$a6Y4}^Umk}ActK3P3L~lAUzkI_LOkCa&yfumhz)zNNrn~wOCeQ zv5U?=2a?tvfhD<3^2vhyQ)eP=j?QHBU^cF5fEjAx%*!W6~5wj{)iwlpRwkA(E zM7mx!Ctt*A5wQUdaC^k8K0)`~{qVFwu%7sUCHb0i(z0My9vk>Srw0w3UnY2a4&3qj zjlUDtBED=Glhy*Sj<`x_7GRZ$36xT+B7Ec~zuBN12cgF(_uP{^ZUy%C2#g;ihN8|A z=BM}HcY36SktjxW%R=*#)4%ybU~VX9lS!8-RJSyTinWP{GqLf86mftk;^wp(sn}z3J*S;lXvyGXqfzimT9%jw6G z)Pc3S<+P1sSQ1Y0-1N*r%B$y{(~sv*SA2O}8+tFcZtR-45)H@CuGFNzZ-=2)wzK4k z72l$+^N~B)-r{6kj^QZ-UM5qCWQL zekr*-^vQUrx(<2v_-~U5`!}295qo?TGwB1elm7>_4-Xi?Y3&0=#jYngG<`9neW-oF zA!#0N=s_iTN;NxP~?BAo?poqIhm^ zUZTIX7T!OpUib-`b>c5~e_F*o+hK5?(r?x5qY*H-ADbio003_>;@-bTZeFtt%cFb$ ziy44qE?v}D{kzSuayY@W0Uh~@3S~r^$~^Fs<3ib5UI;Uv>f7B_H9Nq^%Mlv#WKI8L z=AW}ohV0N3-P513A|PDbvZ;h^z8U0hbt-=n6{mnVVkP35+r~b}PIi=tO1-8m3jiKp z&r#Nc!A^5ld+_f=%|Hq8gsjS;^CEi7ade)jJLKe_@$aUjEI00bCl%P@BwZ6 zzedU2@-6(|?bSUP-o9XmJ(F={f?jy+YHRQx61igl-7WaY#&=f|kr z%wv8&G>X1cNG5#J&`&bRpd5GVk*Hk0VAsB7Gs)kBxlKEq_~nGUN3B;KLayY1H{f8J907>RT|QsQoZb7H8$lj3QPT%3 zS)-?#lLWzApo%*WGohESi@BTTOO`@L>(AoZVXWqGmdv+L=U#Z^cE1t=4b%4}aN?E& z^usl28eXDr?2Fku{T8|-sj>gI5I5_zWK~Ky657W(5Xnni$);gb9Si}ERBDbr)^gQ?rG&9u$?S+!Q+Lhu z@b8+~a@~pW5=Z+&I7PDR*4l4mBq4ksrMJ1Z?giiF1N=x5s_3L|Z-lOJPs98TOhl3| ze0%I*gIT0P{t(391hKD@VN*oB8fy4+vZ%)kU@*(f{`Xz<90B(0k`wirl$bi`M^Q=p z&Gyv41`zD`t5Z!%tJk9SFKPx1P2N3UY|ukht&s6ZkJ$AnAEG@MSh`{2i41Ng#-kML zfQTU}#dNbHvQsK7oJ+JblkpX&)7zH>hy(YYS~E1{19M#Tr2G@DdJx2)G3*Z~2|E+o zJs$ZS^G3j^^6l~+D++N=$;%;wRark$dDZT1y9QX&za0^8b3`8IXmlb zC(jvsyS5B*`#8OGq7y#!T#ksN0Fd+hXz%R?yOpM0-;tEQPBZ9!;uB=~!vTwQO}% zlgH_A9}W~9yeOLhmb4WAZ1u#k2SKORB)CKL2J9PlF*uQwynWPUgjJuKem6jPfh3c+ zExzp8nof%HC42}MEFGIaAtGOR93l`UbMio&TS-~UF779b#SNpxUl9Eg!)At4%WtsW zQRVB0s$sly<*pmS9r<%B7qw)rYGDQ%o?#@;yzqqJE=jhAjX~ezy17EW?7{)r1lQi{ z(=*$8Hy+}cB?*XZHZGJ2#zgIBFL4cP+;%{n`Wc5rZ19mUTx+)wzRLmhc1ziSctYa1 z1BHXDz*t?}nZm7NXoP;hR#ucxDN#l-LW_IB6Fym&gemkko8Zlkl*saeAE3zjr>W(&2`F7Ige~?CEfe)%D*ys$p6KCDi<%7Y%KD8^r8Zuc8 z2v^%ZStA|oD=KB~E%tV-AC(bV&(CxABG#4>Y3PKdBV|Kkq?yb zg-zdBmL$}jXg*TlMc{WPcB|>+7XiHI$g*Rz1&{YA=2;i5;VkoXOZ^Pc65uE;bS}|l zMuSAVDqG0M>l%V71_iV>%Qv;OF4Yu$8_qyCP%!gtGP~yFcwJk)$PyT`ucO|E&C_Ul z(A&89PVKz9Z{!-hu+`;T*RNj5I2w-M=O{kusLrfh4?R|E6FZ`T#zr&dN zTOnmjF~elDnY2PHmryan@F8;ipxt>2l#7yc%)#y&l;bS&l2XuMerZ7CTZxq2O9(14p{NIXM4Var$`mp9Cy|=C8h=;YF`V_zLp^u zw-dZRjji_LiQWDqg4^frIw}cELfxGr5IG={?h0O!zv;E^2~%Bme*MVOivZE+nH_H3 zn(wHx8+93we%ws3C!3tJHCEZfCgCOU@2B*Cen|p|)H#||0p_G3?x*#UY6#Y10=#q+ zz06a~i{u}q6g5_jPCV|t+Owv{xyPxS51y*1b1Lwbocnp#EmbMIBO5= zHQ)MWjc@kL7~2(Ii&-PUWb9Wu*2tYuj+9pNw4@nH5H9W+Le zmH>;Y{|@RujSnOldC_6tS9-Us1&-)#H!RP20z8gY4m?W$*q*hkD?GTep_340bn90o z4J)4)W$;vE^2T>U?(~5U>;uiYMj`xXyuDlVX5J6W(*mo~aKngExcvR~pv|@ze>sYmTwvlu;7WD%8SlggiPC&F30XBL`<2D|(x_L~?iX)F?f0bp+IwZhZ0H8Xp< zUtOPy$q{pCr#;s6<*PA}i0{8NeM0^87c&SYsCL7Zv*(bv<8mf=;JAR+Ty1?eDGUGz z|L9KeGH;Fbr7mnG|L7$M=YE^80#602D&Nh`{uJvj&91|qbAkwdt6^{RoT)8Hup%o) zGgjqu+G8u0FUh;1pUF>6PWHt&-Cmh699W>T&r(jk51sO4Noe1~xx7Rrk%P8sTX#;! zX$EBG9jBM0#lc=pmL!~Z=5DfHv}}T_jFN~4K8;3f73aL0qyLQT`QK_Hcjhag3I9<} zYHsTIX#emXZ!rihml9-)1C2!(Yu%XrpY~Ewk+nV6QB63B{%?&(vI$fa*Xa|?F@{IN zeTz3=G2)OSbx}I^q1hj2{*#1m#f3nd1M$Dd zL!gI!8g|31X9<0;D87X)zM?wmGo$0Ade)&LgW~Ny*MjH)S5s4XLNVeZv#vau=U{E{ zCdKhY%I~`Op1L8t4v=}rXGL>xF15#*+B;tA6qSn*$f|yMuL8*AN9o3Fg18pr>u^yo zZU}VQ+56Jo;;t*>-ra!NH&WJU9P9Bb@B;jw55rU3_P^~dFFwG$xndNrf%6rAQ&eS` zZP>lYoV_@a0&ie!-Ny~zvzMe5*AD!*peNBVbO!|XM2J~F;jv28EK+&6JSr%4=KBJ$ zHGb#M3gb?icFfM|Mxn$mH=7mWW~2qHocJ~~zSvB)mhkCw7(C|9P?^U7 zxZc-mZw9@y*)`45F>bfcKFT{j07<=JMTyfh%!^mQN*H}liS<|{ORlpy%Itpu{Q~)d z6N@qIRFS&p%fSZe<0>bim-7%_KFNL5cB$8jbbf=ni^$v0?Ald1N3SJ33FLD#Qe*yL zl#8P0*kKD*7ILlR#d8>3N6=p zI_zO3{zYu&At3kg*!nV~Lz)RnnZmY3?A=H5&kzy7KU@wM zD@PZ-O&Mj^%jI#Tu?4hU282OwX1to7!0{rE{TM(vrHW`8;)3C`vYb|< zybn9UZI2B@t#$wu?V==22vlxZO&Lw*P6MCXBM9n0ngw6Q(myFVAF;^OU;)@0{FDzc zJt1?`^|tzcUyd3&e{HKdt2I}7<(z2k=#?#G?Ypxs_n3uVSgk0wbn@ca#hS&14w>m9 zkjk>NQpwVqP>^d)U8qR^Epzl}!c!3Y^1D?hQx+z0I<364?zDYZCB3Z6Yn(&s8z63{ zK_WROePOFF# zf}UahKX;4@D^fWcZyJQNvF<0eX{GCqd>9EDmEYaoqn-rj0|`}NBL1*n;!r`5L5CfG zVNo(+^#_i)?%Ezs3|U;sGcIZ;;gsR(z%@n^XZ2OfR`QN}#Y00}H_xYCJ^u)}PE)$X zCk3&IUCW^TYE%~Be_b)HOBMCRXG6{DEM^o46#?7yy`TT$&;7^J zIF%8kVFFpGZRA6U{9psXWDk5S2;!#l$!I6p3LZY;lDhMC0fs53@^v(@QSCi}ZEY`u6ST zb7(TiHuW>Msqg{~O_R!f2wUI@feZGB?tKE5zm?l@Wdxhg_wC%n4U3)$v>M_SLvT^sNHOBbP}8Ro z>i=#w%0xQ)Rgr0cl7n~_WLuhnVWV5grv5(=+r-^e5-pWa?2FfNKR)Y0y+|yPR)qzh z{rbC%T5@hcg-N{sYJ*+ll{c03IA@%Lw@)%M@&3x#{Igxn+R5XeM$`9pmcT-8^)n+r z-QfYi5*!7+%?I~$j<}1qBC#jUYpCtcpFzOg9J~8^$4+@T8~gOWB-SRpl_zfJcC+rX zBdS?!z91r~SA9|Gsv8TpJ(zv}5j9`(>oyy$=px9ZC$dbxa7)dLa4VMUM*l{w=m0+{ zx~{+`Vc2cu5coNl3)VXfX#Yaix9EmUCeJl&<|;k2ULeG(sK<3zY(z2pi2^mc(phM> z2f?<_nxWxeeF8r{y?bJFMhF*E@+IH$OuxnB2Nks&4GESM5@*{HN$OeWF zKDO`$&N0TkgokkCXu#A%-SiROf(DnQf@5hqK1e_dw}`)9w!v`i8pYhnx^W*xIIGbI zeFi=2eu3?zd=u;BD)Ip%<2w5F|FoK$UiiNRrn|w*iqtQ5afeFy%Y(Hb@ny4r464%- zeAV4sFa3aY3*fpca8&dU$MS-cQAkl_TS~JW{EqS0bw! zulxKPCN@z@PiWv`64jJ)oR_5 z`)<8vN?D7rqKH6s3rIkI0|Z}u_EG*{+_|!;8)@gB7iJpUl;`Rt-KwaNPAd3)tiZQ> zq|>S|Na8uI21#*xZ1bwdI1n#-=usI3YytQ%f*ylhN1;ETN;1e(7asE(T*0^v6rBne zgjl^64x9{hDz)fnj;NC~JDm0R=<=GN{$4Njjx6D2w);(M*J;J*6yC|_19`gL66L8$ z;54kVvpHcanFCVYPKlUhDHTTq^`QSXYUAQ*d~_vzV(UJF&558Q%mS{E!4MroIWRfW ziLnzrF?=!0bsR?3^Zp64iROLWkDEdyr*V96@=Xx?p7Me>n(ZVqZX871=~q_F#R>li z3_01{V~jD(%!`OvAKcXRTz6{4(H{?TDCF+Q!F3%de+|MHeAhbUk0z_+kF=GJga{w!=Zdo}(S zrh#=6?|xv9^~M)Z#2ju8<>W9qgUku`G>5n0GN89oA;b`RLkpa2e>wT%%COjp?`wp3 zCi!oKP3uzR)A?d?&vS4()M^EOYkj`TAw9tx&ZZC6(=uD8uu(Pt68r8}Qa5@989IfwF`!hVw+r&3?VL-v@PV{$2M8N96-u_>K+}+eG#Q$3id*Q;28C|fY6l5A6t8${%>5yd3)TQ!Tz+YnM&sNTkvz>Xn zw-%Zg2926f=>eW{P+)UCteg;NRNnloAPM)i_>T*;AKv$lYL&DX=ki#nnp zw+ElSBsWCyuv&@u_TobSnC+Tza3WCl#s_w^$oDs`NRD#^xn0Dq4zbV)K$D$I+5BCz z{-ZB1n0?&Tc7(l5hNxjK5-c%p!#qw9=x554?HH#xIN&V%J$TI6_M!MK5YZr&5i72E z1AfNGo_0)fdzc^_X|N++kq&Usx*?164xc-3M7dfycB1YM!B;3c|A-KL%!q|~f zz>6vBZe$uuMqdkc{YSErd?pfAPzGBK>L$OL^%ckM7Zx8d@36NW(~yN<++|Ymw= zMjHRMD@!8X-^{4cm(|_*lw49#f}MA9e0c7bag|TV0tOE`_IiK72wNFuy{ghlF7G}|#7gg}m#pPDyYBj%}y97a%*25%pR@UsHkrR^aKpszovbJz6Hbm5e z&@%U7-bzU`?8(|TQS_F%;!;T_0ahpe{Ad9jXc9hy>-w+JndclCXp=QrlRgT`tX&XE z`EK^vA~2SK13-9!SkcQxkGzzeAb)x9brzb`Ge)T4W*t-AgHC5t*>j}Wv|2UIoSQ@2 zq`$k<8j~<;B+L7CCr+#)jyBf?2uR>>-`c!j)+Bb zr_p>faS+Rw*fl>Qv*$6VbhFvL!^ki0FAE|hj-6EQcr6jYT4()jvRM^MFG1IN+28wx zcY9BC?B&dn#p;^43GbzNO*F=OPpi`d2?TVqstU!}pJxBe$b`iid;Xs6Y9O|X%RA5s zox<7C#N&|`kN!3C)fo?0X%f#IL9A8Cap>=Flx_IIvkCA(EwPtbQ_--81H_cxpmLH-p?^D0tZykIuL#wTAlU@lEog)h@n#6F~ z|77?~v!DI!_wv+3KR&cfx#}mWao*9EF=drggazsh`p&;bJ(XWmoLqV;OI%n%+8g~h z2CaYA=ILj`M1)l!3^yFG8X~{;J@?0OvxU>EPYo)^|K7m7Gb}k^bA;ymkQdyMCXADz zmz`*i4Y_a9HD;6U`dQ76B08kO;h%R*IKCWwvYI;MnEV*8px2F(sj3bw*y|c+j^FIm zSi)0IMQ^`>L9O}rM(*FYE7Bn>k7E%eL~Z7#>@rW$b*>w+ zeL;lhw#568SUX&sShf=*?kd5K0YEC?H8Lf<271a)U{ax1PTV`mi9YMEj+Q3y<+JTS zKc3;uwzNi3M;%(fw+ZuslO`N+m$Q#ILif2XLeCEM^ND)>@91z`!d zf=?ECmELRZIeJEEqv?5c(w?2=f3e2a?EMi-rGJ!ggub~{V%BZ8Q%-ZwcRj6=czm=jn>#S|g79rFAFX8|;i7JKBL0F7>ga+^Z`MJH+RiYpUJaumq3ii|=J4qGu%MYBdPcrDCvF zMzUpwFZOo#b0sj?(b{=>mNnDhHN;=2z`YT_k7&EdKf;lUISRcnH)S{k-1H{=wgr}Z zb{2zDhA)yKA_4lQ{}K|jlX6Ps2|Tv4s_cEVwRo9UU|9M`rR7zW@t}s-KkssR;EtJ9 zfb$1(ue*49@2Jzky11_mX4b`z(yEXA1+yWBC|OZjhLF*qiz@m#C2FY%jvuyu@1s_-)Y&u?EW{Wa_xE&xOY=xl^gT}qVq_{p>`u^b3 zz)k!oy{GNw4FP%D#}j(-7|5xSOK{v-Ho9!u4E<=ZGnB`k>#UNGE}untK2+GNIUa%U zJQY^x?gJYw#O5U@6uyrBDs1w~2>G+`lf=@N*0Z3<9atA*eQaeXS6F>h8r})3-YX#H?0&puJ~@iYPgW`EBbVdy)Mfi=mcsQJG)Q?ZeupVuq(Ij zJoGjy2t(0Uc_9{;L?sjT9L6s%pCkxWX@F3)6*KQO8F*2PD#e}Yyv~ba?ZjxheaI;_ z!EPF--A=bT$`FxMM8?>f!#5J~OfD(aJL_&^+8$uzAh;^k*+ zp=G*83$uJx8ZbDvs!#hb-1Uy*K3I8V{1ZN=lz*+Ovbj($^%_Rp6GZSAs7?_2C` zRsv~*$ElZdWKJlqoG^d!v)Dmf#FyNw%m0))YtSJa>6vkWlLggxd|A|-5@hV48_ zw@nsNqztQ{gFDFWk=qXc_zaoo@;kJV@XWT%stJjr=|xS2nv5|fF zP=_WOD~%^g`a+EubzmsyW))h^&Ed{6E=_g3FBP~JG_OJyd#3zrbOok-e~gMG{}7kX zBD(~ymz+6MqkNX${m&MZtLq!u@21hd8O6*4*7A5yv80!S@n1QhY~gkKPSOc8d$|$u zmu(VD&f4IAa$5IJ2^nfWyZGQqdMXu`iVV*$sIa_M8y=8 z@1|mLdk?O-c)hZPq$V4K6D)3yt1L4r6`xJulwfS9 zU0)O7x8C$hgK6`WOU?n0I*r)i7yCw6*C|#JG%2Zz3+>oR&NI(JJ>1bWNf+6-$3%arD%`6|X0;NTe*aMzTWLo*1WYgX?k@u+PmSkI ze(H5!vkh`1>m$bo#8qj&8trHy7B%6MICZCi2Oeld%4U;n_7*Wr27f+U7-T>~cDOu} zphzQf#kJUtzdql+*E9cy$^AAMm|WR&qs8gfSGkavH~LB>g8-VIy7h$h&l@FQ2@wn( z|4-S3WT%$Wn$83iDJlR4pvRj^-!ugXkZix-l_yc;0% zgpbBQw@NanrpMq_>QvkRVGs#z_vDx3=3*&TD>r&MNoyQ;nB?ud>4p(SH1&KRvb^|5xC`BzozF~t`Y8L zwA9`pupB#r!cEn>vZA%nqjlfbz8g|M+C|*{-^6p9XPRter5+NsNC#2 zWDi&6Y{;!8^Lew+%$mKoQc~+De|-i-bwsTu=aA3Lh>fUyH}rt8x2X&7AtOWx|A3bv zki865LP*A<;DUpyYjTP6Qz$*~e*~9d#uq8KR^|I7T4iv%MkSrjjWP1Y?Ilh zFV!k4D<@e)KVL``v51gM`bhF{8_%SW;e{3HWm=s*?qIv2 ze0;CnPC2kf!`|qV&~roByw_5etRbP%wUbXjjW!E9OP3?`Z%ch)axCENce?IjJN*k# zPaB*CV+2f}|5vh8yh0ptuwteLv9fS_dAiv;dj3ODzT zwl=po00o}nwOWL+i{|2IGQMj2fKyx{*FLgrH*|(wb?v`;qNpq)RG1n@DytP^VE^qoaF6{3jVSpXl;H-XMu=Zzy^S|OOD7O1f3T=VSS9gBtF zuc(z9+Y-VSy*QT92^QSrf{kOo`n=_LeQ0sIZPtlzCP0hLKYP2{>@V8#2Xf)qrfKac z?`#0dD)ac{|KsS~874%+9=*u|S)??Oyw> z^AFwy_lk~(^Q$BB9vhNpBb`T0ok?m|s&y0uYOs{CeHVDVoN!BVuPhJA^utYdK(+zr zLbZxvZ!9!zTv{uX_*o3ZcKT-Yz<5nJ=g78Lx1PO7xY>^7Hfgmi3pe8un^Z!(@Tz*e z%4~h!oRK2q!i-Z9%>+l!nyz|`uLVJEae5ps^u7xhx5ZXJI|z5;P@0RYnu%rQ@EgLQ z{zPLGg=wm4#k#nhln)4~&#R;sHpTQdzDPYvh;(gr0@I|Q)a$3Lkmb3L39vbI>B}#b zs{3%B*?E{`$r$f+m_DKTJ2a+|dx@JS6uCoxK<{hj<$2l$sm zyl=}c7U_06`a5iMK?>AOVuDp11R11ji+|bX%_KvhcH4TOZCY5!nnx9A5r1s5&1>RD=BYk&I~qEn*AOJ^B3j%)vH&r znYl`IZlW0j!Ai^QsZg`Dc}9;?MwV>c@nmKZSt8PkUkOPI*szK^6cX#e^3k9s*#Owm%r+Pt?_Ak`W>TXSO{LotAZka$XiZM3IaGgx97AnVL z8>68YBV!XC1Z@#T!0j=8F`DllQjAm<#k6imd%s#rj{W9MLAYEaOi?gA@-RT zys>u*l})Dd#SpcOHcQxiS29hRAk-a>va!WQ6yLWyvGY|B=?h+GdX6)uE|4;a^AGsd z;i=EBV_XacsseazYa1S#0tpLyXX<#wG=}gN`(z#7BpwFroTmExzv86p9>Bz)&5&41 zHA5gje^Jtc#R?OcnXZTU0DhZ#kaZDE+0m@52uL(VD;9{ z09!2ix#gTxJDJR6J)=o6(J+;aAF)5X z?McEE!J4QQXS&LIvnzL=I_)ru0nn-!W`kR*3WhN|E0f}1y{i{e7eF2Nz13kiO=AUV z^_vCiT=g5G-beTyK6x%G;rY^-oidzSLT_s!*MR^9O-b6mb|&U>%m6vz(T$LbDIS8{{`C3Fu8 zgEc`wi;Cql&eNGBF5~M6;yPqrvmC}Ax)1jAPfA8@mb$;;oPv75`1X*8(h;wMTzeav zyk&`|8kP)IIAV_7S_D@07|*}WpB@`*wETL0E(FW%TJ3mc;|dVD za9=7Dy;0HHarIymKWRD1$gC{@DShR12hzyb9Qt5<1|YhDVI5+B zF3iSsbKBqS6nQxEr|dF5@w;ZTI$eTW{fwMSrq#@t(t|!ExRku>7*4V92=mhk%6^AuKd7iC3y}7=fF<7fhU`_0RIViPY6Y{KaQ8X(uS?nLd)5! z$6!jNf+=KcmCBPwLx^;yFD z=||*0ywL7|>x`A-@FX1JZK)^_9O!?WDK643Jh3sO+u~L&DgX?o#D9+Svq8C^E0&L< zg3hUt7WN^PKl0@Y_qzbBxX-fx*--Y=BQ=V6$Syt%KcjnD;r6a@<}5-SS{d-eoq)ER zT6yzsu{+-hh6G2;QMQhoWR11J#$)=QeE7o*vRe~4_MF?Qp|MP9nx;9G1GMZw<=8sO z)r6BntLOJyX1LsScopWv>O9KeJhy~#bstg8tJCs+L5P7+WhcX}yc%<2J0%9Kf^}JA zKwV_`qO7c|hQ3!i%3olm<;3PV5P>~hb!NQS{dK{Lu4tWUHSKZNF{>92H0^A}!E!W` zSQdq#5(epT8fRPQ#Fs3rJ+aORy@;-&>ECs&g}epz$bv3X;Vg=nu3?=G+Y_?wW7l{MRJ_-(wp6HNRhe35##c?9V+j7OWhWLm|E z7cymmbQpbP@;|+QP6Rx0S{~Qp1;~NO_QTT?)I?N1`(kKZFNxAbM?p96tTFN1lyr{wVuaf>{T`S$70_p|t{+9KNPcmt^~M((kBX=S zu+SW#jjL+p?sbNSR|*HWGAQ|F_bkrb?#a6&;jo?yNt<#&De|1|$s%1K3xp z?*v-aM#!Vog=Bl(2A(GCO5qcg^*PaL@R%QD%?RASIQcH?c=&>hd-zlExD&+6t2;kX z|2)iQi3vrl+Z8X1ww26RFJYa-ylWY)9wmLlw&LDzHZ!w}F9ZIe5d;rTB1Ar&N51iF zAuAV#D_<5qZM3z?8oU1-9Q77*3D#lrq#Ix)HT#wrtm;UvrGFjn5NAI*LD=FFF1$oD zc?rsYy+56}_ zeC2Aq(UBPsYmlEUnl_jxqzDV*96vLrLh%ltgW~MhFw0NF7X94LbB5hV)@PDTRst!; z-_6K23g<+Qcvcp&PNaGwA09)R!?ttD?gmg1x4hOpAr@m9XD6^1GqO2lB(6>d#IgP! zTzG)&f=;qCqF`IrTfXjc1xEhWQRf5)65Hz=%rC@OD+rCG)K zFKjpy1og+UTjfHqVJ0^vj4uZjfDQ(Pmv`Lx)Bh>#eyTOmKTfl+|4O&Qghrq=&vEm_@m|EArB;G*A5>zxT>sh2Ln z^4@U@0)>ol@pv_>+hhHdKLYzIb{utvY05_xr&8J3RB?1@kRxkfN#;ax$Pn_+jB|x_ZnI$S)C^s zMvL6jYE<|ngwYk{!*Djoy@GgME>*+8j!+ot63&E+3@+}W7HNExcVz+ zE~b~{<(FqNTv^XY^h8dj(QBJe?hjhaAaLeZao?2`hzLy8>(s1RGljigaBOn((?yrB z*QLoel&Z$Syw##P|IgRbEG|+TVzdv zLTSx6lk}saH_H}k$ZQ3JdqkgywDE!?jtS_fGv#L(V!Ah>#Rd73?;ZM8 z;5k@UwpWc>hL5YF{2dtpW{Im}!EtkzO-V@kF`Q7 z+_=^3d_FKQ@`5X^Q|f?k<~H{y`? zK>;n8J*Yg>VfRcEk|{_5P{lhxDnqM{|2NQ9U?HbTL!C*~0eiGUAW|p`NNRpHTGa?Y6xrT53#FaG_!JP>el13=@>PM*Pi{K|Ujxi%7fqJXrpr#?gVeNUb7~Z31sUwF)Tf!q^n@Y18*F}a5&2`l z?{E7tXnF2A4xe>%h-$l|b&_T8@gyqRePT3d0gJR~i8O1ert6FShppJn0W$lOr4FwU z36GSqV=a~T+4sR5GGbbbyRm2&x^(r5?_Tb!iwP^vt(DiA-?m|0f>VM>ZE_t)no)#- z;?w*>D?uOFHJ7q{nF$0ZhHJ{T)y!sAI}>%Z{u=hZw2p@-IvRXQEmx*!H*SBcFMi`}jF0V#{pw$TRzw zu)qVP+J-3VI1B{e=pbZA!>pbTlD0@qx!r~Ukip(YTXVBISUn2V)~2x;V}@DVpu|Vl zj24InN;+X;|IfSU@#|l(1hk>B)Mf?pCcrLx0(QId82POTvJ!MFHYHPr1;p4t-DBQ} zz}vyc66VsMEkdf6(3b8yvl?-qb)`(MsXW6Dw8Kz)5X{nU4d zy4!#%t>(ufkdA_sMI#UM8z3)!wt8EhhHPwfkf^C7?gw7gz16FY^#6h`iIR5DJ*x0= zNi(|V>IE|@CL1xK1+`$HR|c-`Jjtiq>te zGQ;Jr)_60;4<6h(k(ON$2U62Dle^GMP(@v#`;{AZJYPGQspaikHres=;1)ya$c27q zFEfWxp1}vtZo+3+%!>=#qE1-~m2sRaF<0sx_U5jBDL_@v_;YidL+^OpnIa`O8)Mn) zVYrz>mV7@63o7*{917l!qWMNVuzTRZwJ;Dvg^kV&HXkJ6Kuy$Foj;vGjpws%1Je~y zG7_uje^*B8mgPU_0w2ULjsdr9cG4B6zqCB$p&gyNd^A_?8*=wfslZucVKXDbJwOG? zP)WaTZ@_1ENk>6OI83USB1mdvxBJj{mcgl$OrmCLq&GsCsQi&oAd096Wac=%FlT)> zRL>SMMeq5dDiGIF#i5y%GrLIk-&(e3=87hX(m;Y*T(nug3)TBcGa^&rQX}%ZuqX!7 z(m#Ei+pAuqcA_b~V|YLI%>>j7CNzgX`anf4e`=$`)m+)E5#K3>K>-ilXyO^tBZk=1FF{QO6gmV9I)Rv)K=4H_C9(*r3p{ zJ20mmB#V{j=KtM)q`+4f`Mm6WgEMnC01&bFT|8R1M-aL#bVj)X{mrdS;0_k>J=rZ@ zhV39tNiHdBY=dv+cIENrGbo?M>&oB$7lh2hJmYpNG+jX3%!hGV&(Rf+GZ{o=I$?3z zopW6)VG&b z3D5UJIklAJ#SURycp(n3k}g|}5ba`XyaRSe9S(HmkTjELYPjnQYsu#Xel$sDhz^aV zvM-O4qj?jcIoSRE1}8u9ek6FaKonY@phIuxC zjL3^ch@qqVPw&%+plVY2#5N^)d6e6!*&RL07E-`^G4_U&eVqVoMoILyFyLTKlpY#z#NV|7a4*-( zJSzL~Vb~I1jPG2kktvI6jB%VnXWYojqU{Mu|LK9-ptv%NC=FZd6?+5UJBoUEaNBgt zBQ6|L-!)u*CzprA^x-y5X{{>Q3XUv}aOh#0tpcCI1v;W`+Y_VBS)?y1@YG_j-}+C_ zd?B3G<2e{|8At6xRcikkp$P4~)Mp}O_Igglze_1AVc*GaYgKnp)*5FRWr=*|i~nHR znb*NYK4xQ7UB(%*#KC?t3tU3^JPq5$ zQKt)-ze@9wFSIjj`61-lA;PLfbe}S2=HS1oAk{05r4eBoH?qNFdn6vTq5^(Rm@Vb$ zmDj5n1q>07W#;c)_`*fctKKnDPPec<$L(MUAWQZ#H4d&su695Fgl$91C{_=xX68ZR z)t;+Ov>XEi;g<(2;_VD31yYu44C1Yym>t<1nTr7#P(*%?>tvgn>)W>#(04Ns=q>f( z3^uKO!XlB>D8oX7>&g%^rp94kb|K8gtPAUT%TLl%-Bplz@L;W#>j#I@LS`^Mj zE2yTzeXu&k$fpCEyNFfYZKQ8hSx|QwAr@<8ozu^yA4Q8N1qoi=>B`<`!3ud}3a?)H z(OD{Kwok`pvXfc%fuyCu(+BkXc_T?w%u^L9c~rmeYvAQIY(>g!{O!mrWKy1s=lIft z>%_o{q)hdAy_N(~!YRKmI$SJoe_&9pdsHaYlM@vtxE55U_`CiHt z6FiE>=d-L!7QFQk43C^oEI~w_11Mqy8Y6K{*y0QoKH1H}PTzqoxqGNORh=F{krJ}n zg~U`C%PoN$vy9Nel}j+HFkb3iP!TdrHBEZ50?|ulO~XO#8HB1$yooE(0Syk zGnC3uIxW@mHrvoaJ~aH#xed?b+MUS}Uucs2MVGK=vA+3&ArL%l^*9ELxWu@!vkx_J zaPk#~N}A7{*)x1-Jg%)UZ<6iF2?KTMZm%@k?|y=>Me@nuovwNJOyY)G)^o7gg{-;I zp#7IXRnTnj)&BlQ9KGyZ^TDFxljLyWr?37;AG)Fsvntk9bm4?OM_e6(z7KW~PJ?#0 z$%@lKxr(241)I;9Dwa0*q*|w6`XC7ZDIl64fJgz)HvCdev;Npvw!5kr32ow9z1`Dg zFND*Y*lqut3N~ZlLt^#Ax3*|uP>4Re^$39p7Ao;IGwpn&5=BY-qn2(&X*@|aI`7vU zu?BRWzfQU2V2&wuN+1|rGhmw;QLd8MJ`UpJB362Wq{^+CbP!Oru@?A4TmXSgm#%vA z{UA3L*6jGIhWz-v=!uer?`z(l0-bg=_*{=P+SIQ5x3BH-MaPS>n-_F>#Ll z+EqZ=!Hx6>Tc35tfYL+{`AIUL1t*m(uutV?>Tbl3bNgjjr%b; zuI>@o_#XX$N^nemmhY;#e`D{UkeD54qZRPuj@fi@lJkL#tPwxV9_+hU6P01}SZ7jQ z`CIQe&`dz0;cTd2VsP7vF>1|S4vsL3dQQgX28Fm zWZ;H=grO~f$&&V*ix$YWVpW%N2B^{aB**{3N;a8)xyrpOn#ESWL7>y_Hb_)q>e21c zcU(*62kBO*MmOxrWupxzp;xaN4sE*Y>ZW9Q-oZ5-Yl8hVrSk-?-3b+xGGsON^@^|8 ztp~TznAOVA2Qiu+-$gw)l$Kh~qyr@A>@lYy@S<*9>2BMBScD$g4b(mx0LFX;;S>sf&OcWUY7wx+iZC;p+?#N}xX-mHJ*S5kTAxq}R6179l zs7c}?>*mkUrmGN3kXj(F>Rprlh4KHZL7W1?MkdNqX7Al##t;_tgI2LG3eDhFE+BF0 z9i1qR8he{1^A~D!4(etuF5d6i_k&~>M!l%uUYOrgFIf&F_N!~hBRY?tco*d#eNWV) z;fK(EjDqNalKk>)|E-%!+Uwf7a7>zssyt;elSF~~uIC{-U;@SJ^sF^VkWAKj?0L#~ za?E4|qoVW{5zgn>#OEdqVc*?}HZz2I=GTC&11Q68KWVI$qk%x7Z>AM`1@iN#L}BMi z(Q%XBQ83wVwzVrnLG@}~h(DVtXDB;k=M(iYPF-?I>BId@-Yn9kpB&blXZ0wHI%^soU*^Cxfmst^vaB->WEw;Q?O+0VVKr+xh8<(+!Hy-Y!#N>8wfGs_9nZ(!j^(~?x-P!-Chwq z29Cd5;ZXCwypmj=ka;H(D(P}`bm}@{y^QIb#0OB(RT%8mj%PdL_z9!N`C)N3*|HYe zq-ok@2nE6}S0$dZ(cJh>^6CUOIP3+C3}|LQ`V`z?Tup{v z?Mv@~iKisG^t+iXcIGV=RV{q>Fza9xdKG_u*b$#~+oRt3y_)4Ps=KI1O&0g5QHL6m zoZQty5-u>)Q*xeV1!ABpRsZRof^Y;(sNQB9_I)+wZ#(?C_h)s|;s#t6vIls4{dW~g z24&{qwXF`0Fn45ix)m_N^3P)W99L{jU|GQM>=`uqw><7zp2;-=d*(^S$`>njH$0zY zQDLf4TO}I&q9kJ<)|)=TRpg<@k{V+WY6)eK|-7md|@R1_7^at*O3_k2$Q8?94v zn%wz?l-1C5+)mGE651|e;#~)~9cC%HUbnJstnLq}@=F}0b>nM6@i~e%{1>e_W`qQq!&ZMT+Iw2OWe!} zB3izR)p=yY=O=V4fFh%$<*T)_0`2|gp9Vy|*C@gWL3MqQWKDUpI{*5mErXnzk~|2K z&0;^FfYnnIa1PTYOW^vT9%FJyI?SrLIJu0t%5fejI6z>WRR_2ObV|i z2N9Sp*XOqG?7=%i4b|*lo0{j2x&&3XJ=BA6lRqdBEmm)(XZv>jl0FP7!Q1_<=yKGK zWt90qk*etDTyg11!O_FRDf0jd+%GYa^b}yFI*AP?jEFv`qTW6orJI*PWngyEWTsxo z^oAj!C**IX@J>^eR8LuW(->HqD7QVo30343AV5Ph=Q_MOI#OdFaT;}+yag%-{+5Ie6zKg4kjr)ok%y(_4?rBF5Il6;gzAUo!ezx=EU$}8;+odyab z|eLHIE<-QaLAongk%@`583MnM8lzg$n+kd#`Gr6J}V zNhr1Adim3PCBmu7+Ej*t3Ps6VzQJ`W!j$vUD23O!Ta|2>Ut^k=eNt*5tqbGn7m!|n zWq(A^K|FpeIUOEt*R5pbl)8*p)RuqvK^IzQ(Y*W7;0Djuc0h$loE#ouwpD1f>TofSzgh7_WY+ey6c%!^-$-eP;Yu%T?7HGXlqADAe4FrYh ze=jOOi=2wC$;;44P!ZFmzglzRS904+!|gkIHaK%xB*K@o^_zo7;m~Ma&)L&Y$p7^r zlstXVWZHOaKAG8^*8)jSJ|PaD$(YczSt}cF@Ql3I^48Ydz5q3as=&-uEFVuBtTR4e zG<^>F{&UqtEyj5(pCl+Xw|U|H`U#GmmduZ7|`t5WE z;~Sy)zR?PZ&H^IWJ+>11MsLg{_$Xy+afuN=cL_^SiCa^ z%rCE1X34AHfI9(DEkaUEmHpF0DPj@Hcgg$BysfR3?i}(N20@p4lBXXGxmKMX-FD}Q zV}t@cPw!52h=KT0#5{JZ?QV&Sx)ykJ*tq_Xyz&Wo8c0G^Zd@H3b$qGMWS2;%uVP$z zeK9FRLV*4$G!C-^CYZJqee+z$oQeq8)A@d9_gBnGF zv|{ULp#^3I_3E#Dx4}WMBUyZAJwJ%OGbSi1Fth^EE@oEn0ON||KT(oDk}r9jI_ZcI zNnynJfw>S{w{tX{4h-#zQ?^#09|_7^wR~W|@@4q4dz<2q@>`$|j`XXZWI4JbExe7$ zs=&2;+K*HYj`h45{rJ)jbM=)J*?f(I6lnzm#|HuBsgZDeDr-W5u=NtC2We4ev){3Z zBpmuv^Y&~Bx{os=+ebgQ5L$xRkNin1RL}lCX?&X!W3X09q=6VG;J4IrUJ&Fa!l)<5 zC0Lov45@M40lPF2KhV9FUx1g42>PTY1%%J9?}j-6e(R?|RTv0j>NmFvs^ZR||D-w0 zETRPsiC%^sO?5x~0*h?*Y{nKxIlY_#I9 zfiiV(e>gy#cyEig(OUkVgsB;M&MA1O=<4rN-q(Sw4q!N1s)UmJlIJ z{8>%Xo<|JZ82@h0{XeEUlPiLih9(DJ{nti0~*NH0+3#Re&_`UoxL!{w@=6>x)A=KVIY zA(Z=pz9c^P? zIJI!UPQTJ&j6emeL6i9GV7ItDT44a#MwtHHhGz5J0?q7qp1qphiREN#W^0|Ed_i3A($^=n~GY!|4w}U7}#3B5$*|=s0t7) z9^E;#{u#Y_DXg-&6rOuXkq2~?B(=SbU8NUWKHY`mAUPda;k-qHIpO%WtZ2BUzu`nqM= ziK0y>+I~H^Y=JURQ9S9f?b`r0GC@-*{`lTAJKnS@`oYpBdn&XdlO0>_RA0ak|9*S!DbOh zMO_j-^Pw|&=>)#Zu?uqgGy|ui;x=vMT%|h}wjyn$s@SN2-Csa3ZGHy&#>Syr|D*30 zC>-Lr`R{98L=vrC1tQNpz)oKYmRu9Pp|DbWOus;El<&qI(7zY)b} z6|n^6r=*n?r<;4dt>H8uh1^Q&4oX^i(GA*km&h2@S_XnD`rfmfGf1kM&Gu^l$Kf1+ z`ui956?9(#63M$X446B=zK*l0cOn&aNCi5(d3e_Qq`=GQ&5gkmCEhIQ>rab|hwxkU zUu&{SS?x_@sx$9r;huMQN~Spz=3{eKWCz=Pt#hb7fi}v%ng5sb{4`TkerF?-gS@n8 zm;@ueAY!^aWDUEIt(&vkeYvoovwm+ z4Cg^-B{gm0C$sX%vVZAoI5a*LE=rONQ_Z#YzL2U4AP6eY`MP9i8ju{W!fIh#?h66K z%rB|S^9c<7f@^l6v+pkI?q5}#IA!s+wuRUE)gFvr!E1JM4aisJ-`{?EfGNTQ`*8S< zXkgs^;#{;pd^l4)$dDbUTP{mxeHz~U_p>@V9vY*pz%(~rA)Hv9I=d5zhkNAt&PO5Y zLJ78om0achuFxk&5IC*Ec9dK_Z)gRB{e;Z4CMx5M^PHPas=4Rz*wMjmDHu9}#HX5< z-^ujhaD-Q(5NPz_?a4)a_(N0CrPR)OzLsJPNutt}m78oR>tqm0Ta*XAeHh4v`YEKH zuiNkE3yNb;xm$#g0Ip#=xjaj}Xdjsw-T6Y@?qA2$LXN~$G2L!^U5m?0NPevsUd{)V z&0J-zvlo6D#Q+AxclN@mP%vZuEHy`nbsmf8 z)Y$3eSWV2AbbRV9i(Mz_micq7{$Qu7Zjkd3w#S%oslT0n_-6H~oFCbiN?7WA9O_7A z+~o-KTnB?sJAiL8w&sgYk`U8;Yhv}bv_(jATAp$6n-wHzr>3xHrI<(!65<{%W!>cI zKK|?x@n-=JHuwFc94ML+~SFVh)S>FNeh2~0TgV*3RF!o+8*}-W%Wwsf10l3iI zw{pCaXK4RZ<;shfX^@psA;US8b(G@Eke zEkR?YcWZ}FYgj!;mOep0MX9KloWGou%nFq+1=WllvgWS%fP0cj8jXHr9ivE`TKGt9 zzq_BtVS&ZSBWuq|Y01KzeK7tkOF6onH)C0Dn-m{*nu-{^ z^V=s!wvFvFdBaHNF0j`(Xh0PgY)-kF2#@g*$e^H%QD&N4T~48L;~>&JkN?+brwSDP#>ZxgZvh_%(In(r??CoJch`tlhd@O9tPVbixybvBQV2cmM!&x zzFiY|?T53E8`tMorTG-d@B&o+0p{Jte;3DlahK#XGcp{~>hr7R*^lK4?U)lSI2adC zc}nZ}p?6$e=dX$%tRf18SALE1vAYU`dtw>G_el-X$=-Q7$DOR?GT{ipJ`@AQY(OVj z@;!%-F(R>*EJ4MoywlDY%5;@$SvBlBzW5oL<|8k$ZsL~gLfhlmOoGU7V4e8A7{^4H zXNl2$P$w>_$T`AH;8S>|Ife(ick87$FXl|FAFF)H5lSdTx>T_h%zzb&L-{%-L`19a zh)soR&?9nGu!N2o&Og@H*zNea4i#_nH-oG4UDl<9dB?o{wzIKCUGu^ZC;1wu#S^WM zb}1{NexnRrdTWZ(WK38#{^@B>ah!q@PUhDNw-~3b(h-*V51$XjZ1(_HZP)!(sz30P ztV^t~bIau?3RxeF!!H4x~NuJI{1;{s~W{7<@znwU&i1crsZ$Ry9p zm;wC{h%+)uvnFuKUQJWHh7YKN;1STeq6_O7v8!NfGnHpr{fqPbtlpug>I4Y%b<4+- zWl9?JK#0KtBk;j(4eL^v%6GZ?4QPM`r4ZeL-4_i3Zg9W=8=_^1^;KVQ6_>Gs@^@HG zPA|8aQ4foR+CJ=c1tlrA>ojOZop`u>$nOb^L?G4dDpbRH&r`G zE9rzWmk*(&u?Cq`W0WfzfZtfN+V05{g?>l~$=ur8$L(4M_xL z4Seu)x&!6r=W@kro5$*x$|73SQkz=`;cG1*)fpY-&>S@I6x|uBm$VAn0B)#rl&*#c zXrpi5(+qwZAni_VyYu6-hOBlz%d^#3VRVW%vR2t8gR&BnR=cc2*a*rZ^~i_4acR>q zdJmKtZ8S@s)QaHpFAG?Mbw=AA|8CKsrphniAmAPl+W!(A{joVOKSz*(D*>Q((CNLX zosr+WaX8O4FeGyCBdpehgRQH|CiR`IM|9Be{INR0HgCK zk8d$-0vcY(80@<+KjXrBVFA)g0D)-U2U5x>*dUH#em7=mCUuDd1DWs0XC3A}- zPoHN&Jc{4Wtp}Xr9jB^nchqUcJ$j&(Uo>X_{#cm9hv5rFuwBE)9t?_)=QHr)YsTkP zq|E}xLXG}!4f_clbXfYJ3Q~s85NTQnRSv7lp_i24DL19BmdylCzJow>mc3(aEMhJ2 z=lO;()^o@`Uz$vRF{>BR0bJXf;QGW(PV~SkPK}zGZckzQm z2iM9Os<(Mz%D857boC6wdk{E~3zXCvwHp9J>vR_&pj|S^1n0bbG^x<+f)b1StL&6k zhov0=%d?S{ymZ@Ru|Op8>4Y4GII`#_QQcJgR}oC+FSIfIM1MrJz;~g)blVU!H|CT0e?Zj_O%g^3Ok&5Okf! zMZu>U@ZrsSC+7QW^&8j>@mxjjhNFLL*cxPL>@E5|$x&^IIQ&zvcJ?~z`;ePc5uMDh zfv@+Y*jMY}ea=_^xfw#Iobsruq2&Y4BStu8P~1%1qbckaj)4;+nHC$rN#)lFSQcWl zF;{H6mSyH^bI@4uI1g6`N+y3Pf3WLSUDkZt!$Y)BNQc4WFY_z9;2xh2ZTaL~@A*nI z2mWq;zzeYpo>QF+8iQ<~U} zo=V@Ba2D5u?hL}x9)0om*>biIFXqD^Ro)-C=Z-!yjB_H{K=Np=66^DMl-L?}Db@i` zXlDkERiF-Q8I(pZi!*Y|f5zt)L)5uHoA36qavDXEm7hnLT^|;GbGDo{ZENLHcnFhf ze0-~I4z4eR5P~cDZa)HLP#J^4+;M?&huKng%C*%{+A{mlzqJw4x{|pQ=%V+w?ld+d z5l?tlF8^kXCv*g2wO0=bj}~Ywn0R5g%6I$2etyUu0l&Dk$Rpd=3>xTe&HgXFnCN3l z%B`ZBy40c|qL`4!nyASx_f?rVU54h)-^@JwJ#qA`(85wcgXmROY8R9avOwY-%{V03 zI-EsXU<7PK9u7GMOOf~iBig*qO8Sb48!7i_4uK5xk4L@_6F9lvK^0(#(tqbF(AxJe zSXYZ(&xoTW;VdwO+zuixQdyE(UM(wU|Ma7peqSi@w@HKbEYu;Y;pr&gz+H@k#d~$} zKX%k*DMH2VC1zOU9o7_p^DTBix#P+!xe8g}jxm_iVXL5Ko8$-PtA@pz4~}QsPc^RT zQ)bf|7>2gV^Z<`bO#EVDs-@M5^(RFPvjf$fG*@}Ac+n<()}K+wN z34C&~4X`uKgs42)b4NkxvH{iQMM<48$GjBKj|_dlH%MnM<|I)st5~|o0807K7p4q{R*$&M8tAbskv|bkSy%C59m?pDg);0?5RgDJ zNa%t+kCP5{_Ca`2?~jXc)@^Yf%?-$#vOxb|wmK_063vO9*P-_k<&I~lFxvR4SYzzg+Wg{cuker@+w;^tHPg_Azm>r(ElHE``&$qVvzuSU?si zU6yTWk?d|ToPH^&s{bcQ1e26YtlQ=CA0T$0vB@j&Nfv5wClJf{307OEK4r z{wE2-za-WtHlK2|(DG0z6@`ypuq>9aQ(UdNEOXXX-PaoD*YlUpgMRa)cMEM5W$wxEFYN+m_*%#wBuRt z+nhd`g|pK&ZXdhlAtrnhzNXK^KU|?zPQuT%=Rsl77738cs&5+ZQ`5CP=kUoEQR%lD zmWjh29X3H!#v_ON9CA7n0O}lnj}}Z2VPUPFC(Y=ln%}i(414tDAdb)CsjypZSORhJ zM0VcMdSU00jYzJcVN!8fwwGz`e|na)7vC(2>h~#7H*fS1n~KP4-{l*YT^eQJKIjG> z+Vh(Xr|G7*huq2N2+dXf9SyfEsbZDS=jIsjS37KimE?#!1oFUX4vuwuy)(QZ5nTBx z{=LkH{=_T@B(z7NUCcBkyl3J{FgePU9^5-9@7cf9PWKEQ#bpK-?`Oa9E2#;u!**AQx zWEA1r(m#<>r}5U<{pk^m>T(4a#80#5GJ_Ir@G8pJIg5^-IuvBb{_1M$-sasuGGp?= z!Hkl9WMd(w=qKEE=EF6}Ah32jE6xErNL!tjg8yPj8uB0zIq zcR_4P{OW69XpNy_z_QEra6rc|O7e)g7w{_qd0F_)kuVWO!CmUvZLouc#}I(jx4}I9 za=F6@pyGRq$pU(tGpv0d*O3AFT>vtH1=Cv!?y3rFRTN^d{tN3n&)n__GitjJK zWw&)L^vUxV<#Ggqbvx(a_hFf}uooq5(0&ogCLMJ4D9AzCdX=(%=18b$&Y!DnN!4wO zjJ_<;y@6}JESq(?45n1X0uJAVa*eXSb2+bD7Zc($rGhQ!pNVs*Nyw^e0=S~(qID|t zP~SfW#MxCQA>WAh#O}hqkTh!ZRM>riX}yj%BV%$WC+XtTj7*KEDRiUWcKp2aDE-Bb zWg{wSk9?+YklEGrtcMx{waC|ilTSl20+_}YNTt>9LWq4&TIPhhO#{Z0C7-RpqwuHG zuk>f|G+@)DOC7lg{GuN9po!CC)AM{FU|UH69}wdz`A@GGV((J%NfDFSm zj5AqFhiymCk+$Fw$eBwkNKCFGLWsxpiNooB+;%ruX1QhzK%oowU#!KO7pY_vSilNo z0r@T}5X@SsPx+eET89v6RnRUqDr+PRyt7mWb0)_rBk;@CSvN9_t6uP9zPGLanA!~@ zExWTPmjW7xPopNKJLq>Qm7TO_lS$aWK!BsiZp%0iQXGkg_?y(DEizdOw&FQ^uRwH+ z+_VscW8!r`>5<^S`N!_#<+07vUMx~SD{IYe zIc=CnN#~`V&WVJs5^Hj|1%%u1Fk# zN;0anX0yTJm4mcq{b!O>G)a|RYOCSZuYtBd@|Dy}%QJ%69xs(-sr28T-^{F?3UG%f zW{OsW!gtQRz^_p!36tS)Q%(9?Cc{Dw-RFdmmFyGmw-&pa!Egd`yaDjmC}$k2+w%<~ z`-0*X=m2aZ_ZxQ0M>s;qehytpx;naliy2@T(Os_`s(E!<-Zy!D{jBHuVFU=d2LTK< zNHu)+E^;MknDTGIq#&vI8us~X2?NDHT2hc%rwA}0mv0&cjhCK`^Y5RywYq#}C1%U*9i;)G*GLAH=MpMM$lt%565o5U=3j zh=YWg0E`@;%(Ul6S@tJL#>Eaiw#Jj~uPVy^IT|PIMzKVdWOU`gu8>W(I23l{-aKE+;lB@>F|zgSG(ook^x*?t~Hj+T-Pp`Ze@8oW@Q zAVsQkoBx&hL}M3m#9U(bok?l&45@$71Ar|u&N7vtC-cJ4qu<dc?iyZW{}K(AT9ns zy$#y2h>nr189Zb33ivnnsM$W#mwh^Q!^BGaXDTX+MA_*337JX}U@gvzTK|z2h?nT1 zA6(cyT|!a|i4Ti^HfFaGKZOJO$17a~Bo)@JnC2V#&*{qZYh8AKlg*k?k8a?qd(H|; z(mHb!*U1z6(F1(IXZp$CW1W)0DA#i9fsNH_g#?Vk5Tg$KyD!Qb`Ys&jr6!Clg>0YK zYwK4*;V-nXe*oIL1leM>_3;M_7PuT_{vNydtr|XDwMW)Ofiel6xg#7S74h?^@f%lX z6bT3B$l|&SyHL{%$IqbU)(e(8p883u@`GmX3YDE)CbJS~V!7K~>*Nxs1aIHL%`6IK zpHgnqjz0+ec7{W3)XCW1m<^VH^NG!7?%BOJ77BFB>puGOCciniu4M1O<@eJ@*@z6M zg5d=ks#X4Gfk@F0$~pby9qh*Jga=f~5ObwU9sG$hHwe;$>VVZoKl%Xt{B3#h(V-OK z=e~;F;sgEaAeb0Fed52TTIPgpgdlX<{>s(6mkLvAIDeJ#7PDnieRC8q22=Sm?d&Sg z9_>`(k7$(}+o!czp^pj!0z8G4bL3yB6Oa(0O5pM2(T1R>F@l~#_9lc{*~OQ0ewx&dokf{Xz&|rcyY>L9*uBy z_BVL1vl=WhlHQC3Gg)YTZ4f7%$v{>4cB^T0jkB(KX7jSuz~tv{LsB_111BhyN98(z^LmwLv0f!*D3l=>{V%nIBqS{HwS6#U@()Yh|oa zq1*0V!0~=9$t*hB2$No7kzMbbSamH|873~}{CQ#|>sO)e+Gc;TH~)@=PnHkYNv5Vl z7?29<#Uhp}R<%e6nIX_aU>^p09C}K-3D%6cpAI_Gcd20{QQ7pXca^LG#QI4%<9Pj1 zlHW#;wXM&urZ>`w1)85K0M(yDXZ#~nU7 za+*Y_Tp8G`dr(n#kB*x$#eJ|Hn3~>D38e`3npt#94T$cWy;=up?`2W}zze(`xvy(V zV))&U43(oR`p)Qk;op-6$AM~f{KrhNi!&&5H2tD?@iz4`VEC2ixcbvrJ(>tXsSoBS zk7c&bvsqbt4gkt%Hhu_)yH3KZ!J<-U`9a@628+BU^BzCu5av-t&4{%M%yBpHDspH@ zfilAx4eYY!tvq@f22MD_l{FLF6O;Z(n^d!I)qGTVl`{H;ma-1IU*D={^n46BZe|RZ zq=ezNZG3Rnqa)8cfAUf02CIREj``dY5LRb3?}MLTF5%1T z+@Sam&_rA*9I}zDaE_1#Q3qe5Ey8{ta*#Tv?0=#e>;~-!3FpfF0W@a(h1kLF0gOQR zQW;ucwvRYe*Z0NW?hJMByGrw44?j(&fqDa@E_E2K7<_uiRTa1`lN=3w8n9m~Ep|T= zfG1i>+i$$4>YYF?eb94l>}-Rj0U%t_7<>aZ&o&dOQ%N3QOv%g)6Fkr?AxojPX=SOYc|bBV&)}gw^0C zBloNb$1>+ztS^zmvfg)jGH2A?6#=RY21KMQBjOH;u=48s?ZYlg&YW>MA-M>KDcJPU z&-E&^u@8{*h%C!@ZrIq-MSEHAzy|q!AC&Szh8mpc1zv+h+&hq|N`m3~R>8zoSQcD2xjc)k|zq9L=kN0Rvua`jhutkbGSbL;WacLn$qN(;6CxSrBI zj}5;ur$&MZT2^|Gndj(WP3+~{2}tb$KXnVYO)fgEf|35H&&{SD_@d^`3k~=SU7wv2 zoDw|VCyq|<(qX^}=7O?Ff7~l#fI|2dc5>9+u8^dv%3srbj#g}J+)e-A2jbP+JI7fU zjjg53Qs-BP!;U`$uG^$z?EzDjNywp&e5mq;GON7XKW6ng6@pIk_e}zChp@^~MwT3vL(XO;{*msSM z+uB1-P09z7ulm+JRHEQaUSSMfx|(ERXAS(xo2>^)C`bSxrTDoyJD@66QD7=mRf|mK zXU>maemKa7Hjh@~vO9WN8q}DaA901dunJ>s3Tgjty5TRDqBg#;Hn>?|e1q>1S9sFc zFF87(bPbj=fmi58W~8zpH#FkU+8v4rAFKK(p$Sb$LCB!WJFTuB3!5pQ65Y=qFN+BQ zb+qsN0=>9W0}j*3hZTkJSy4sKTmOGD;QaSMP8pH{WdH= z3Rvhh1%ypI@+FCDMwi zGa5~(F8n{UYH}g+Hw1{d+m2;73<_aX$H_8VR#dQlt|*cTO$1ZrgEYxMx(+*(MU1QV}AAUobQ7 zJE#xPQy1J}UBSRxVe*UQg6jy}kv;~xgnmDGCl>bQ7*|Wsx!Tjqj#Xs798qpa>;=W& zeBP3l^9DNsi{7vyYe1+bN4=~={NX|v*%_oVQ2T}KxK)2NCiA|whO@sdA2)7mQl^St zAeMb!j$E{Dl4N_UXMY^Q5Hg<&>0|B-lB(71#(Qm}u`(fbaVu}<^(4AHNcyOayaTkP zf>Xo0e#r4aYeBBGBjUtLnoYP(mPvW4CV-vnNsg_v^_Iiirvdtd@&pWjVYFLD%;5$u zm%k4OX2L=J3RT3lae)ua7RdNhJhvl{05lRaU58rNQ-V>E7)Am?ChFF)RtyB1py(q( z)MBmtfXnE0hgH#u-LqeA{K(sS&@&3A1gZ)9(Jj5 z@N%TzL=05-+yP{#v~JnO_)XdQ7%9Y^{rEh|XD%tczK}_`>=2zxiMWLq%D_a03bM>e?upIW7LWQP|wz4_AFs-*B zUJC!JYsdLKd#E6)#A|giTQ@Z7tW8cIqy}6#!IkJmoPsNtCiI_g$#c#cZ*GGafAP0H z%G8@m%uNGj`49F&0gUh0Ro9W}Qa&&tY{TppU5nXb(SfAK&W4IHg9W;^kfuyP`#-tu zA|E7JB_#ksY& z1eldMt=evBTX?JMd80+FlN7xH!WW6IMS!0Xp#kLP$tO6#)}gjWkAyT3?mYQ;HA z!Z{$u6^{rytuPf);~N?S;w6ZRNe0oz^P&8P6*HymBKJH7U;wd3w|Vws^M_e?bu31f zR~``=*l04pAlUpphypGqBAjGi2EoWAQq4-$gkcY+2586au>bY9kZpJS+u=m&`iwh9 z!QbJEoXtGL_uMlw69;#vl8pc@!n;=G&8=Gos%`(QZnLUh4@E)P@}}MU7T0soZeJ;|&=HrujYjdkgFmykVD35Buq` z{ZdwDW~r=k)%|Bh#%-xmQJg&3{a#WzoaWpoy~;RRz})~!i*$ct)SbrQ-7(R_u1S}; z4KTQxYO>fkSPllt2;W{6(Fpqa?cst$0y&;xe0Kc?K@8*X`1G-Bew{t9rny_Kx6B@X zCgU&ljX|Js2e=}?pNL~xNaj*d{T$H(+)1O5`)wCdfe4(5`A22qM(sy{=Hh!qP7 z&q|8c^6FpFCnXVErD_=%AM3u}`BK%%Hs72+A)2AqE?s~ibTE~b@?7(($wX=U}yyw7f{1Qr49Lef_J!_j8f5DCt1=4DH?MC^V>8{E5Eq>7)>Idj_>IG?%pJg`K zqeZhQap`!au@PuLBbRB&VQ>gq8iv36RIs=tU6nB6{F8Q;HV#2(KYs)nZ?jN92iQJm znp?@t@JaR(elNZxWS}NYlzggrV~5`3eeKkZrfS%1ge-y>dN!b;u02@wX`@BYe$$W< z>=w-k@vVC|4knFo>!$;_>RdcXKU2W?o>2kp1NJ<1mp~It}+pw$@7;I*l6;lucDH*zc^;tdSBy6Z}?>-KDg{q#huvlg26cvA} jX__)?pLw&IO~)#vUVgTh0M5Pi>2yn6ZNGTvzvur4-EGwh diff --git a/simulator/ms-tpm-20-ref/Samples/TPMCmd-DeviceID/Platform/src/EPS.c b/simulator/ms-tpm-20-ref/Samples/TPMCmd-DeviceID/Platform/src/EPS.c deleted file mode 100644 index 889d01d61..000000000 --- a/simulator/ms-tpm-20-ref/Samples/TPMCmd-DeviceID/Platform/src/EPS.c +++ /dev/null @@ -1,285 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#if !defined(_MSC_VER) && defined(USE_PLATFORM_EPS) -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "Tpm.h" -#include "Platform_fp.h" - -#define DEVICEID_SIZE 48 - -// This extension is needed as TPM2B_STRING only define TPM2B variable when #GLOBAL_C is defined. -#define TPM2B_STRING_EXTENSION(name, value) \ -TPM2B_STRING(name, value); \ -const TPM2B_##name##_ name##_ = STRING_INITIALIZER(value); \ -const TPM2B *name = &name##_.b - -TPM2B_STRING_EXTENSION(EPS_CREATION, "EPS Creation"); - -// Definition for Device ID value. -TPM2B_TYPE(DEVICEID, DEVICEID_SIZE); -const unsigned int MAC_ADDRESS_MAXIMUM_SIZE = 6; - -// This value is used to store device id derived from hardware parameters. -static TPM2B_DEVICEID deviceID = {0}; -static BOOL isDeviceIDSet = FALSE; - -// Read mac address of the device and copy over to the given buffer. -// Returns 0 for success and -1 for error. - -static int GetMacAddress() -{ - struct ifreq interfaceRequest = {0}; - struct ifconf interfaceConfiguration = {0}; - char interfaceConfigurationBuffer[1024] = {0}; - - int inetSocket = socket(AF_INET, SOCK_DGRAM, IPPROTO_IP); - if (inetSocket == -1) - { - return -1; - } - - interfaceConfiguration.ifc_len = sizeof(interfaceConfigurationBuffer); - interfaceConfiguration.ifc_buf = interfaceConfigurationBuffer; - if((ioctl(inetSocket, SIOCGIFCONF, &interfaceConfiguration)) == -1) - { - close(inetSocket); - return -1; - } - - struct ifreq* intefaceRequestStart = interfaceConfiguration.ifc_req; - const struct ifreq* const interfaceRequestEnd = intefaceRequestStart + (interfaceConfiguration.ifc_len / sizeof(struct ifreq)); - - int32_t result = -1; - - for (; intefaceRequestStart != interfaceRequestEnd; ++intefaceRequestStart) - { - strcpy(interfaceRequest.ifr_name, intefaceRequestStart->ifr_name); - if (ioctl(inetSocket, SIOCGIFFLAGS, &interfaceRequest) == 0) - { - // don't count loopback - if ((interfaceRequest.ifr_flags & IFF_LOOPBACK) == 0) - { - if (ioctl(inetSocket, SIOCGIFHWADDR, &interfaceRequest) == 0) - { - result = 0; - break; - } - } - } - else - { - break; - } - } - - if (result == 0) - { - unsigned int size = deviceID.t.size <= MAC_ADDRESS_MAXIMUM_SIZE ? deviceID.t.size : MAC_ADDRESS_MAXIMUM_SIZE; - memcpy(deviceID.t.buffer, interfaceRequest.ifr_hwaddr.sa_data, size); - } - - close(inetSocket); - return result; -} - -// Read primary harddisk/emmc disk serial id from device and copy over to the given buffer. -// Returns 0 for success and -1 for error. - -static int GetDiskSerialNumber() -{ - struct udev *ud = NULL; - struct stat statbuf; - struct udev_device *device = NULL; - struct udev_list_entry *entry = NULL; - int result = -1; - - ud = udev_new(); - if (NULL == ud) - { - return result; - } - else - { - - const unsigned int diskDeviceNamesSize = 2; - const char *diskDeviceNames[] = { - "/dev/sda", // primary hard disk. - "/dev/mmcblk0" // primary eMMC disk. - }; - - unsigned int i = 0; - while (i < diskDeviceNamesSize) - { - if (0 == stat(diskDeviceNames[i], &statbuf)) - { - break; - } - i++; - } - - if (i == diskDeviceNamesSize) - { - goto Cleanup; - } - - const char blockDeviceType = 'b'; - device = udev_device_new_from_devnum(ud, blockDeviceType, statbuf.st_rdev); - if (NULL == device) - { - goto Cleanup; - } - else - { - entry = udev_device_get_properties_list_entry(device); - while (NULL != entry) - { - if (0 == strcmp(udev_list_entry_get_name(entry), - "ID_SERIAL")) - { - break; - } - - entry = udev_list_entry_get_next(entry); - } - - if(entry == NULL) - { - goto Cleanup; - } - - const char* serialNumber = udev_list_entry_get_value(entry); - size_t serialNumberLength = strlen(serialNumber); - - size_t dataCopyLength = deviceID.t.size - MAC_ADDRESS_MAXIMUM_SIZE; - if (serialNumberLength < dataCopyLength) - { - dataCopyLength = serialNumberLength; - } - - memcpy(deviceID.t.buffer, serialNumber, dataCopyLength); - - result = 0; - } - -Cleanup: - if(device) - { - udev_device_unref(device); - } - - (void)udev_unref(ud); - return result; - } -} - -#if defined(SIMULATION) && (SIMULATION == YES) -// Get device id from hardware parameters. -// CAUTION: Primary seeds derived from device unique IDs are guaranteed to remain the same as long as the reference -// implementation manufactures its NV state on the same device. Since this implementation of GetDeviceID() relies -// solely on publicly accessible values (storage device serial numbers and networking card MAC address), it can -// only be used for the simulation purposes, as it cannot be used to produce a secret value. -// pre-requisites - assumes that MAC address or disk device (i.e. /dev/sda or /dev/mmcblk0) present on the device. -TPM_RC GetDeviceID() -{ - if(isDeviceIDSet == FALSE) - { - if(GetMacAddress() == 0) - { - isDeviceIDSet = TRUE; - } - - if(GetDiskSerialNumber() == 0) - { - isDeviceIDSet = TRUE; - } - - if(isDeviceIDSet == FALSE) - { - return TPM_RC_FAILURE; - } - } - - return TPM_RC_SUCCESS; -} -#endif - -void GetSeed(UINT16 size, uint8_t *seed, const TPM2B *purpose) -{ - RAND_STATE rand; - - TPM_RC result = GetDeviceID(); - if(result != TPM_RC_SUCCESS) - { - LOG_FAILURE(FATAL_ERROR_INTERNAL); - return; - } - - result = DRBG_InstantiateSeeded(&rand.drbg, &deviceID.b, purpose, NULL, NULL); - if(result != TPM_RC_SUCCESS) - { - LOG_FAILURE(FATAL_ERROR_INTERNAL); - return; - } - - if(DRBG_Generate(&rand, seed, size) == 0) - { - LOG_FAILURE(FATAL_ERROR_INTERNAL); - } - return; -} - -void -_plat__GetEPS( - UINT16 size, - uint8_t *seed - ) -{ - // Ignore GCC warning. - (void)EPS_CREATION_; - GetSeed(size, seed, EPS_CREATION); -} - -#endif \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/Samples/TPMCmd-DeviceID/build-tpmsimulator-deviceid b/simulator/ms-tpm-20-ref/Samples/TPMCmd-DeviceID/build-tpmsimulator-deviceid deleted file mode 100755 index 56f21c536..000000000 --- a/simulator/ms-tpm-20-ref/Samples/TPMCmd-DeviceID/build-tpmsimulator-deviceid +++ /dev/null @@ -1,52 +0,0 @@ -#!/usr/bin/env sh -# The copyright in this software is being made available under the BSD License, -# included below. This software may be subject to other third party and -# contributor rights, including patent rights, and no such rights are granted -# under this license. -# -# Copyright (c) Intel Corporation -# -# All rights reserved. -# -# BSD License -# -# Redistribution and use in source and binary forms, with or without modification, -# are permitted provided that the following conditions are met: -# -# Redistributions of source code must retain the above copyright notice, this list -# of conditions and the following disclaimer. -# -# Redistributions in binary form must reproduce the above copyright notice, this -# list of conditions and the following disclaimer in the documentation and/or -# other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -# Script will build tpm2-simulator by using DeviceID. -# CAUTION: Endorsement seed derived from device unique IDs are guaranteed to remain the same as long as the reference -# implementation manufactures its NV state on the same device. It relies on publicly accessible values -# storage device serial numbers and networking card MAC address), it can only be used for the simulation purposes, -# as it cannot be used to produce a secret value. - -basedir=$1 - -# Copy needed tpm simulator reference implementation source code files. -cp -r -n -v $basedir/TPMCmd/* $basedir/Samples/TPMCmd-DeviceID - -cd $basedir/Samples/TPMCmd-DeviceID - -./bootstrap -./configure --enable-usedeviceid=yes -make -j2 - -cd $basedir - diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/include/Platform.h b/simulator/ms-tpm-20-ref/TPMCmd/Platform/include/Platform.h deleted file mode 100644 index a81e3c93b..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/include/Platform.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _PLATFORM_H_ -#define _PLATFORM_H_ - -#include "TpmBuildSwitches.h" -#include "BaseTypes.h" -#include "TPMB.h" -#include "MinMax.h" - -#include "TpmProfile.h" - -#include "PlatformData.h" -#include "Platform_fp.h" - - -#endif // _PLATFORM_H_ diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/include/PlatformData.h b/simulator/ms-tpm-20-ref/TPMCmd/Platform/include/PlatformData.h deleted file mode 100644 index e76da528c..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/include/PlatformData.h +++ /dev/null @@ -1,143 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -// This file contains the instance data for the Platform module. It is collected -// in this file so that the state of the module is easier to manage. - -#ifndef _PLATFORM_DATA_H_ -#define _PLATFORM_DATA_H_ - -// From Cancel.c -// Cancel flag. It is initialized as FALSE, which indicate the command is not -// being canceled -extern int s_isCanceled; - -#ifdef _MSC_VER -#include -#include -#else -#include -#include -#endif - - -#ifndef HARDWARE_CLOCK -typedef uint64_t clock64_t; -// This is the value returned the last time that the system clock was read. This -// is only relevant for a simulator or virtual TPM. -extern clock64_t s_realTimePrevious; - -// These values are used to try to synthesize a long lived version of clock(). -extern clock64_t s_lastSystemTime; -extern clock64_t s_lastReportedTime; - -// This is the rate adjusted value that is the equivalent of what would be read from -// a hardware register that produced rate adjusted time. -extern clock64_t s_tpmTime; -#endif // HARDWARE_CLOCK - -// This value indicates that the timer was reset -extern BOOL s_timerReset; -// This value indicates that the timer was stopped. It causes a clock discontinuity. -extern BOOL s_timerStopped; - -// CLOCK_NOMINAL is the number of hardware ticks per mS. A value of 300000 means -// that the nominal clock rate used to drive the hardware clock is 30 MHz. The -// adjustment rates are used to determine the conversion of the hardware ticks to -// internal hardware clock value. In practice, we would expect that there woudl be -// a hardware register will accumulated mS. It would be incremented by the output -// of a pre-scaler. The pre-scaler would divide the ticks from the clock by some -// value that would compensate for the difference between clock time and real time. -// The code in Clock does the emulation of this function. -#define CLOCK_NOMINAL 30000 -// A 1% change in rate is 300 counts -#define CLOCK_ADJUST_COARSE 300 -// A 0.1% change in rate is 30 counts -#define CLOCK_ADJUST_MEDIUM 30 -// A minimum change in rate is 1 count -#define CLOCK_ADJUST_FINE 1 -// The clock tolerance is +/-15% (4500 counts) -// Allow some guard band (16.7%) -#define CLOCK_ADJUST_LIMIT 5000 - -// This variable records the time when _plat__TimerReset is called. This mechanism -// allow us to subtract the time when TPM is power off from the total -// time reported by clock() function -extern uint64_t s_initClock; - -// This variable records the timer adjustment factor. -extern unsigned int s_adjustRate; - -// For LocalityPlat.c -// Locality of current command -extern unsigned char s_locality; - -// For NVMem.c -// Choose if the NV memory should be backed by RAM or by file. -// If this macro is defined, then a file is used as NV. If it is not defined, -// then RAM is used to back NV memory. Comment out to use RAM. - -#if (!defined VTPM) || ((VTPM != NO) && (VTPM != YES)) -# undef VTPM -# define VTPM YES // Default: Either YES or NO -#endif - -// For a simulation, use a file to back up the NV -#if (!defined FILE_BACKED_NV) || ((FILE_BACKED_NV != NO) && (FILE_BACKED_NV != YES)) -# undef FILE_BACKED_NV -# define FILE_BACKED_NV (VTPM && YES) // Default: Either YES or NO -#endif - -#if SIMULATION -# undef FILE_BACKED_NV -# define FILE_BACKED_NV YES -#endif // SIMULATION - -extern unsigned char s_NV[NV_MEMORY_SIZE]; -extern BOOL s_NvIsAvailable; -extern BOOL s_NV_unrecoverable; -extern BOOL s_NV_recoverable; - - -// For PPPlat.c -// Physical presence. It is initialized to FALSE -extern BOOL s_physicalPresence; - -// From Power -extern BOOL s_powerLost; - -// For Entropy.c -extern uint32_t lastEntropy; - -#endif // _PLATFORM_DATA_H_ diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/include/prototypes/DebugHelpers_fp.h b/simulator/ms-tpm-20-ref/TPMCmd/Platform/include/prototypes/DebugHelpers_fp.h deleted file mode 100644 index 87b8f3d04..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/include/prototypes/DebugHelpers_fp.h +++ /dev/null @@ -1,65 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*(Auto-generated) - * Created by TpmPrototypes; Version 3.0 July 18, 2017 - * Date: Oct 29, 2018 Time: 04:20:07PM - */ - -#ifndef _DEBUGHELPERS_FP_H_ -#define _DEBUGHELPERS_FP_H_ - -//*** DebugFileOpen() -// This function opens the file used to hold the debug data. -// Return Type: int -// 0 success -// != 0 error -int -DebugFileOpen( - void -); - -void -DebugFileClose( - void -); - -void -DebugDumpBuffer( - int size, - unsigned char *buf, - unsigned char *identifier -); - -#endif // _DEBUGHELPERS_FP_H_ diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/include/prototypes/Platform_fp.h b/simulator/ms-tpm-20-ref/TPMCmd/Platform/include/prototypes/Platform_fp.h deleted file mode 100644 index 8e981372b..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/include/prototypes/Platform_fp.h +++ /dev/null @@ -1,467 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*(Auto-generated) - * Created by TpmPrototypes; Version 3.0 July 18, 2017 - * Date: Apr 2, 2019 Time: 04:26:21PM - */ - -#ifndef _PLATFORM_FP_H_ -#define _PLATFORM_FP_H_ - -//** From Cancel.c - -//***_plat__IsCanceled() -// Check if the cancel flag is set -// Return Type: int -// TRUE(1) if cancel flag is set -// FALSE(0) if cancel flag is not set -LIB_EXPORT int -_plat__IsCanceled( - void - ); - -// Set cancel flag. -LIB_EXPORT void -_plat__SetCancel( - void - ); - -//***_plat__ClearCancel() -// Clear cancel flag -LIB_EXPORT void -_plat__ClearCancel( - void - ); - - -//** From Clock.c - -//***_plat__TimerReset() -// This function sets current system clock time as t0 for counting TPM time. -// This function is called at a power on event to reset the clock. When the clock -// is reset, the indication that the clock was stopped is also set. -LIB_EXPORT void -_plat__TimerReset( - void - ); - -//*** _plat__TimerRestart() -// This function should be called in order to simulate the restart of the timer -// should it be stopped while power is still applied. -LIB_EXPORT void -_plat__TimerRestart( - void - ); - -//*** _plat__RealTime() -// This is another, probably futile, attempt to define a portable function -// that will return a 64-bit clock value that has mSec resolution. -uint64_t -_plat__RealTime( - void -); - -//***_plat__TimerRead() -// This function provides access to the tick timer of the platform. The TPM code -// uses this value to drive the TPM Clock. -// -// The tick timer is supposed to run when power is applied to the device. This timer -// should not be reset by time events including _TPM_Init. It should only be reset -// when TPM power is re-applied. -// -// If the TPM is run in a protected environment, that environment may provide the -// tick time to the TPM as long as the time provided by the environment is not -// allowed to go backwards. If the time provided by the system can go backwards -// during a power discontinuity, then the _plat__Signal_PowerOn should call -// _plat__TimerReset(). -LIB_EXPORT uint64_t -_plat__TimerRead( - void - ); - -//*** _plat__TimerWasReset() -// This function is used to interrogate the flag indicating if the tick timer has -// been reset. -// -// If the resetFlag parameter is SET, then the flag will be CLEAR before the -// function returns. -LIB_EXPORT BOOL -_plat__TimerWasReset( - void - ); - -//*** _plat__TimerWasStopped() -// This function is used to interrogate the flag indicating if the tick timer has -// been stopped. If so, this is typically a reason to roll the nonce. -// -// This function will CLEAR the s_timerStopped flag before returning. This provides -// functionality that is similar to status register that is cleared when read. This -// is the model used here because it is the one that has the most impact on the TPM -// code as the flag can only be accessed by one entity in the TPM. Any other -// implementation of the hardware can be made to look like a read-once register. -LIB_EXPORT BOOL -_plat__TimerWasStopped( - void - ); - -//***_plat__ClockAdjustRate() -// Adjust the clock rate -LIB_EXPORT void -_plat__ClockAdjustRate( - int adjust // IN: the adjust number. It could be positive - // or negative - ); - - -//** From DebugHelpers.c - -//*** DebugFileOpen() -// This function opens the file used to hold the debug data. -// Return Type: int -// 0 success -// != 0 error -int -DebugFileOpen( - void -); - -void -DebugFileClose( - void -); - -void -DebugDumpBuffer( - int size, - unsigned char *buf, - unsigned char *identifier -); - - -//** From Entropy.c - -//*** _plat__GetEntropy() -// This function is used to get available hardware entropy. In a hardware -// implementation of this function, there would be no call to the system -// to get entropy. -// Return Type: int32_t -// < 0 hardware failure of the entropy generator, this is sticky -// >= 0 the returned amount of entropy (bytes) -// -LIB_EXPORT int32_t -_plat__GetEntropy( - unsigned char *entropy, // output buffer - uint32_t amount // amount requested -); - - -//** From LocalityPlat.c - -//***_plat__LocalityGet() -// Get the most recent command locality in locality value form. -// This is an integer value for locality and not a locality structure -// The locality can be 0-4 or 32-255. 5-31 is not allowed. -LIB_EXPORT unsigned char -_plat__LocalityGet( - void - ); - -//***_plat__LocalitySet() -// Set the most recent command locality in locality value form -LIB_EXPORT void -_plat__LocalitySet( - unsigned char locality - ); - - -//** From NVMem.c - -//*** _plat__NvErrors() -// This function is used by the simulator to set the error flags in the NV -// subsystem to simulate an error in the NV loading process -LIB_EXPORT void -_plat__NvErrors( - int recoverable, - int unrecoverable - ); - -//***_plat__NVEnable() -// Enable NV memory. -// -// This version just pulls in data from a file. In a real TPM, with NV on chip, -// this function would verify the integrity of the saved context. If the NV -// memory was not on chip but was in something like RPMB, the NV state would be -// read in, decrypted and integrity checked. -// -// The recovery from an integrity failure depends on where the error occurred. It -// it was in the state that is discarded by TPM Reset, then the error is -// recoverable if the TPM is reset. Otherwise, the TPM must go into failure mode. -// Return Type: int -// 0 if success -// > 0 if receive recoverable error -// <0 if unrecoverable error -LIB_EXPORT int -_plat__NVEnable( - void *platParameter // IN: platform specific parameters - ); - -//***_plat__NVDisable() -// Disable NV memory -LIB_EXPORT void -_plat__NVDisable( - void - ); - -//***_plat__IsNvAvailable() -// Check if NV is available -// Return Type: int -// 0 NV is available -// 1 NV is not available due to write failure -// 2 NV is not available due to rate limit -LIB_EXPORT int -_plat__IsNvAvailable( - void - ); - -//***_plat__NvMemoryRead() -// Function: Read a chunk of NV memory -LIB_EXPORT void -_plat__NvMemoryRead( - unsigned int startOffset, // IN: read start - unsigned int size, // IN: size of bytes to read - void *data // OUT: data buffer - ); - -//*** _plat__NvIsDifferent() -// This function checks to see if the NV is different from the test value. This is -// so that NV will not be written if it has not changed. -// Return Type: int -// TRUE(1) the NV location is different from the test value -// FALSE(0) the NV location is the same as the test value -LIB_EXPORT int -_plat__NvIsDifferent( - unsigned int startOffset, // IN: read start - unsigned int size, // IN: size of bytes to read - void *data // IN: data buffer - ); - -//***_plat__NvMemoryWrite() -// This function is used to update NV memory. The "write" is to a memory copy of -// NV. At the end of the current command, any changes are written to -// the actual NV memory. -// NOTE: A useful optimization would be for this code to compare the current -// contents of NV with the local copy and note the blocks that have changed. Then -// only write those blocks when _plat__NvCommit() is called. -LIB_EXPORT BOOL -_plat__NvMemoryWrite( - unsigned int startOffset, // IN: write start - unsigned int size, // IN: size of bytes to write - void *data // OUT: data buffer - ); - -//***_plat__NvMemoryClear() -// Function is used to set a range of NV memory bytes to an implementation-dependent -// value. The value represents the erase state of the memory. -LIB_EXPORT void -_plat__NvMemoryClear( - unsigned int start, // IN: clear start - unsigned int size // IN: number of bytes to clear - ); - -//***_plat__NvMemoryMove() -// Function: Move a chunk of NV memory from source to destination -// This function should ensure that if there overlap, the original data is -// copied before it is written -LIB_EXPORT void -_plat__NvMemoryMove( - unsigned int sourceOffset, // IN: source offset - unsigned int destOffset, // IN: destination offset - unsigned int size // IN: size of data being moved - ); - -//***_plat__NvCommit() -// This function writes the local copy of NV to NV for permanent store. It will write -// NV_MEMORY_SIZE bytes to NV. If a file is use, the entire file is written. -// Return Type: int -// 0 NV write success -// non-0 NV write fail -LIB_EXPORT int -_plat__NvCommit( - void - ); - -//***_plat__SetNvAvail() -// Set the current NV state to available. This function is for testing purpose -// only. It is not part of the platform NV logic -LIB_EXPORT void -_plat__SetNvAvail( - void - ); - -//***_plat__ClearNvAvail() -// Set the current NV state to unavailable. This function is for testing purpose -// only. It is not part of the platform NV logic -LIB_EXPORT void -_plat__ClearNvAvail( - void - ); - -//*** _plat__NVNeedsManufacture() -// This function is used by the simulator to determine when the TPM's NV state -// needs to be manufactured. -LIB_EXPORT BOOL -_plat__NVNeedsManufacture( - void - ); - -//** From PowerPlat.c - -//***_plat__Signal_PowerOn() -// Signal platform power on -LIB_EXPORT int -_plat__Signal_PowerOn( - void - ); - -//*** _plat__WasPowerLost() -// Test whether power was lost before a _TPM_Init. -// -// This function will clear the "hardware" indication of power loss before return. -// This means that there can only be one spot in the TPM code where this value -// gets read. This method is used here as it is the most difficult to manage in the -// TPM code and, if the hardware actually works this way, it is hard to make it -// look like anything else. So, the burden is placed on the TPM code rather than the -// platform code -// Return Type: int -// TRUE(1) power was lost -// FALSE(0) power was not lost -LIB_EXPORT int -_plat__WasPowerLost( - void - ); - -//*** _plat_Signal_Reset() -// This a TPM reset without a power loss. -LIB_EXPORT int -_plat__Signal_Reset( - void - ); - -//***_plat__Signal_PowerOff() -// Signal platform power off -LIB_EXPORT void -_plat__Signal_PowerOff( - void - ); - - -//** From PPPlat.c - -//***_plat__PhysicalPresenceAsserted() -// Check if physical presence is signaled -// Return Type: int -// TRUE(1) if physical presence is signaled -// FALSE(0) if physical presence is not signaled -LIB_EXPORT int -_plat__PhysicalPresenceAsserted( - void - ); - -//***_plat__Signal_PhysicalPresenceOn() -// Signal physical presence on -LIB_EXPORT void -_plat__Signal_PhysicalPresenceOn( - void - ); - -//***_plat__Signal_PhysicalPresenceOff() -// Signal physical presence off -LIB_EXPORT void -_plat__Signal_PhysicalPresenceOff( - void - ); - - -//** From RunCommand.c - -//***_plat__RunCommand() -// This version of RunCommand will set up a jum_buf and call ExecuteCommand(). If -// the command executes without failing, it will return and RunCommand will return. -// If there is a failure in the command, then _plat__Fail() is called and it will -// longjump back to RunCommand which will call ExecuteCommand again. However, this -// time, the TPM will be in failure mode so ExecuteCommand will simply build -// a failure response and return. -LIB_EXPORT void -_plat__RunCommand( - uint32_t requestSize, // IN: command buffer size - unsigned char *request, // IN: command buffer - uint32_t *responseSize, // IN/OUT: response buffer size - unsigned char **response // IN/OUT: response buffer - ); - -//***_plat__Fail() -// This is the platform depended failure exit for the TPM. -LIB_EXPORT NORETURN void -_plat__Fail( - void - ); - - -//** From Unique.c - -//** _plat__GetUnique() -// This function is used to access the platform-specific unique value. -// This function places the unique value in the provided buffer ('b') -// and returns the number of bytes transferred. The function will not -// copy more data than 'bSize'. -// NOTE: If a platform unique value has unequal distribution of uniqueness -// and 'bSize' is smaller than the size of the unique value, the 'bSize' -// portion with the most uniqueness should be returned. -LIB_EXPORT uint32_t -_plat__GetUnique( - uint32_t which, // authorities (0) or details - uint32_t bSize, // size of the buffer - unsigned char *b // output buffer - ); - -//** From EPS.c - -#if (defined USE_PLATFORM_EPS) && (USE_PLATFORM_EPS != NO) -//** _plat__GetEPS() -// This function is used to access the platform provided EPS value. -void _plat__GetEPS(UINT16, BYTE*); -#endif - -#endif // _PLATFORM_FP_H_ diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/platform.vcxproj b/simulator/ms-tpm-20-ref/TPMCmd/Platform/platform.vcxproj deleted file mode 100644 index 0b5811b71..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/platform.vcxproj +++ /dev/null @@ -1,506 +0,0 @@ - - - - - Debug - Win32 - - - Debug - x64 - - - Release - Win32 - - - Release - x64 - - - Static - Win32 - - - Static - x64 - - - WolfDebug - Win32 - - - WolfDebug - x64 - - - WolfRelease - Win32 - - - WolfRelease - x64 - - - - - - - - - - - - - - - - - - - - - {A9249F05-0DF5-4D06-9873-FBBE61B6768B} - platform - Win32Proj - Platform - 8.1 - - - - StaticLibrary - Unicode - true - v140 - - - StaticLibrary - Unicode - true - v140 - - - StaticLibrary - Unicode - false - v140 - - - StaticLibrary - Unicode - false - v140 - - - StaticLibrary - Unicode - v140 - - - StaticLibrary - Unicode - v140 - - - StaticLibrary - Unicode - v140 - - - StaticLibrary - Unicode - v140 - - - StaticLibrary - Unicode - v140 - - - StaticLibrary - Unicode - v140 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - <_ProjectFileVersion>10.0.30319.1 - $(SolutionDir)\$(Configuration)\ - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\$(Configuration)\ - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - AllRules.ruleset - AllRules.ruleset - AllRules.ruleset - AllRules.ruleset - AllRules.ruleset - AllRules.ruleset - - - - - - - - - - - - - AllRules.ruleset - AllRules.ruleset - AllRules.ruleset - AllRules.ruleset - - - - - - - - - .lib - .lib - .lib - .lib - .lib - .lib - - - true - - - true - - - true - - - false - .lib - - - false - .lib - - - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - - - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - - - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - - - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - - - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - - - - Disabled - $(ProjectDir)\include;$(ProjectDir)\include\prototypes;$(SolutionDir)\tpm\include;$(SolutionDir)\tpm\include\prototypes - WIN32;DEBUG;_LIB;%(PreprocessorDefinitions) - false - EnableFastChecks - MultiThreadedDebugDLL - NotUsing - EnableAllWarnings - ProgramDatabase - CompileAsC - 4668;4710;4711;4820 - Default - true - true - - - - - true - $(OutDir)$(TargetName)$(TargetExt) - %(AdditionalDependencies) - false - true - $(OutDir)Platform.map - - - $(OutDir)$(TargetName)$(TargetExt) - - - true - - - - - - - - Disabled - $(ProjectDir)\include;$(ProjectDir)\include\prototypes;$(SolutionDir)\tpm\include;$(SolutionDir)\tpm\include\prototypes - WIN32;DEBUG;_LIB;%(PreprocessorDefinitions) - false - EnableFastChecks - MultiThreadedDebugDLL - NotUsing - EnableAllWarnings - ProgramDatabase - CompileAsC - 4668;4710;4711;4820 - Default - true - true - - - - - true - $(OutDir)$(TargetName)$(TargetExt) - %(AdditionalDependencies) - false - true - $(OutDir)Platform.map - - - $(OutDir)$(TargetName)$(TargetExt) - - - true - - - - - - - - - Disabled - $(ProjectDir)\include;$(ProjectDir)\include\prototypes;$(SolutionDir)\tpm\include;$(SolutionDir)\tpm\include\prototypes - WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) - false - EnableFastChecks - MultiThreadedDebugDLL - NotUsing - EnableAllWarnings - ProgramDatabase - CompileAsC - 4668;4710;4711;4820 - Default - true - - - - - true - $(OutDir)$(TargetName)$(TargetExt) - %(AdditionalDependencies) - - - $(OutDir)$(TargetName)$(TargetExt) - - - - - Disabled - $(ProjectDir)\include;$(ProjectDir)\include\prototypes;$(SolutionDir)\tpm\include;$(SolutionDir)\tpm\include\prototypes - WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) - EnableFastChecks - MultiThreadedDebugDLL - - - EnableAllWarnings - ProgramDatabase - CompileAsC - 4668;4710;4711;4820 - Default - true - - - - - true - - - $(OutDir)$(TargetName)$(TargetExt) - - - - - Disabled - $(ProjectDir)\include;$(ProjectDir)\include\prototypes;$(SolutionDir)\tpm\include;$(SolutionDir)\tpm\include\prototypes - WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) - EnableFastChecks - MultiThreadedDebugDLL - - - EnableAllWarnings - ProgramDatabase - CompileAsC - 4668;4710;4711;4820 - Default - true - - - true - - - $(OutDir)$(TargetName)$(TargetExt) - - - - - Disabled - $(ProjectDir)\include;$(ProjectDir)\include\prototypes;$(SolutionDir)\tpm\include;$(SolutionDir)\tpm\include\prototypes - WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) - EnableFastChecks - MultiThreadedDebugDLL - - - EnableAllWarnings - ProgramDatabase - CompileAsC - 4668;4710;4711;4820 - Default - true - - - - - true - - - $(OutDir)$(TargetName)$(TargetExt) - - - - - MaxSpeed - true - WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) - MultiThreadedDLL - true - NotUsing - EnableAllWarnings - ProgramDatabase - $(ProjectDir)\include;$(ProjectDir)\include\prototypes;$(SolutionDir)\tpm\include;$(SolutionDir)\tpm\include\prototypes - true - 4668;4710;4711;4820 - - - - - $(OutDir)$(TargetName)$(TargetExt) - tpm.lib;kernel32.lib;user32.lib;gdi32.lib;winspool.lib;comdlg32.lib;advapi32.lib;shell32.lib;ole32.lib;oleaut32.lib;uuid.lib;odbc32.lib;odbccp32.lib;%(AdditionalDependencies) - - - - - MaxSpeed - true - WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) - MultiThreadedDLL - true - NotUsing - EnableAllWarnings - ProgramDatabase - $(ProjectDir)\include;$(ProjectDir)\include\prototypes;$(SolutionDir)\tpm\include;$(SolutionDir)\tpm\include\prototypes - true - 4668;4710;4711;4820 - - - - - $(OutDir)$(TargetName)$(TargetExt) - tpm.lib;kernel32.lib;user32.lib;gdi32.lib;winspool.lib;comdlg32.lib;advapi32.lib;shell32.lib;ole32.lib;oleaut32.lib;uuid.lib;odbc32.lib;odbccp32.lib;%(AdditionalDependencies) - - - - - MaxSpeed - true - WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) - MultiThreadedDLL - true - - - EnableAllWarnings - ProgramDatabase - $(ProjectDir)\include;$(ProjectDir)\include\prototypes;$(SolutionDir)\tpm\include;$(SolutionDir)\tpm\include\prototypes - true - 4668;4710;4711;4820 - - - - - kernel32.lib;user32.lib;gdi32.lib;winspool.lib;comdlg32.lib;advapi32.lib;shell32.lib;ole32.lib;oleaut32.lib;uuid.lib;odbc32.lib;odbccp32.lib - - - - - MaxSpeed - true - WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) - MultiThreadedDLL - true - - - EnableAllWarnings - ProgramDatabase - $(ProjectDir)\include;$(ProjectDir)\include\prototypes;$(SolutionDir)\tpm\include;$(SolutionDir)\tpm\include\prototypes - true - 4668;4710;4711;4820 - - - - - kernel32.lib;user32.lib;gdi32.lib;winspool.lib;comdlg32.lib;advapi32.lib;shell32.lib;ole32.lib;oleaut32.lib;uuid.lib;odbc32.lib;odbccp32.lib - - - - - - \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/platform.vcxproj.filters b/simulator/ms-tpm-20-ref/TPMCmd/Platform/platform.vcxproj.filters deleted file mode 100644 index 45cf28bbb..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/platform.vcxproj.filters +++ /dev/null @@ -1,55 +0,0 @@ - - - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - - - - {4303d7e7-8154-4a7c-9c6b-0df9b7e6447f} - - - {c7765704-4071-4d43-b451-b1dc177da099} - - - {356cc198-cb6e-4dbb-bf4f-b203b6e3fdb0} - - - - - Headers - - - Headers\prototypes - - - \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/Cancel.c b/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/Cancel.c deleted file mode 100644 index c05a7f9d1..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/Cancel.c +++ /dev/null @@ -1,79 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Description -// -// This module simulates the cancel pins on the TPM. -// -//** Includes, Typedefs, Structures, and Defines -#include "Platform.h" - -//** Functions - -//***_plat__IsCanceled() -// Check if the cancel flag is set -// Return Type: int -// TRUE(1) if cancel flag is set -// FALSE(0) if cancel flag is not set -LIB_EXPORT int -_plat__IsCanceled( - void - ) -{ - // return cancel flag - return s_isCanceled; -} - -//***_plat__SetCancel() - -// Set cancel flag. -LIB_EXPORT void -_plat__SetCancel( - void - ) -{ - s_isCanceled = TRUE; - return; -} - -//***_plat__ClearCancel() -// Clear cancel flag -LIB_EXPORT void -_plat__ClearCancel( - void - ) -{ - s_isCanceled = FALSE; - return; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/Clock.c b/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/Clock.c deleted file mode 100644 index 4ce56f747..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/Clock.c +++ /dev/null @@ -1,282 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Description -// -// This file contains the routines that are used by the simulator to mimic -// a hardware clock on a TPM. -// -// In this implementation, all the time values are measured in millisecond. -// However, the precision of the clock functions may be implementation dependent. - -//** Includes and Data Definitions -#include -#include "Platform.h" -#include "TpmFail_fp.h" - - -//** Simulator Functions -//*** Introduction -// This set of functions is intended to be called by the simulator environment in -// order to simulate hardware events. - -//***_plat__TimerReset() -// This function sets current system clock time as t0 for counting TPM time. -// This function is called at a power on event to reset the clock. When the clock -// is reset, the indication that the clock was stopped is also set. -LIB_EXPORT void -_plat__TimerReset( - void - ) -{ - s_lastSystemTime = 0; - s_tpmTime = 0; - s_adjustRate = CLOCK_NOMINAL; - s_timerReset = TRUE; - s_timerStopped = TRUE; - return; -} - -//*** _plat__TimerRestart() -// This function should be called in order to simulate the restart of the timer -// should it be stopped while power is still applied. -LIB_EXPORT void -_plat__TimerRestart( - void - ) -{ - s_timerStopped = TRUE; - return; -} - -//** Functions Used by TPM -//*** Introduction -// These functions are called by the TPM code. They should be replaced by -// appropriated hardware functions. - -#include -clock_t debugTime; - -//*** _plat__RealTime() -// This is another, probably futile, attempt to define a portable function -// that will return a 64-bit clock value that has mSec resolution. -uint64_t -_plat__RealTime( - void -) -{ - clock64_t time; -#ifdef _MSC_VER - struct _timeb sysTime; -// - _ftime_s(&sysTime); - time = (clock64_t)(sysTime.time) * 1000 + sysTime.millitm; - // set the time back by one hour if daylight savings - if(sysTime.dstflag) - time -= 1000 * 60 * 60; // mSec/sec * sec/min * min/hour = ms/hour -#else - // hopefully, this will work with most UNIX systems - struct timespec systime; -// - clock_gettime(CLOCK_MONOTONIC, &systime); - time = (clock64_t)systime.tv_sec * 1000 + (systime.tv_nsec / 1000000); -#endif - return time; -} - -//***_plat__TimerRead() -// This function provides access to the tick timer of the platform. The TPM code -// uses this value to drive the TPM Clock. -// -// The tick timer is supposed to run when power is applied to the device. This timer -// should not be reset by time events including _TPM_Init. It should only be reset -// when TPM power is re-applied. -// -// If the TPM is run in a protected environment, that environment may provide the -// tick time to the TPM as long as the time provided by the environment is not -// allowed to go backwards. If the time provided by the system can go backwards -// during a power discontinuity, then the _plat__Signal_PowerOn should call -// _plat__TimerReset(). -LIB_EXPORT uint64_t -_plat__TimerRead( - void - ) -{ -#ifdef HARDWARE_CLOCK -#error "need a defintion for reading the hardware clock" - return HARDWARE_CLOCK -#else - clock64_t timeDiff; - clock64_t adjustedTimeDiff; - clock64_t timeNow; - clock64_t readjustedTimeDiff; - - // This produces a timeNow that is basically locked to the system clock. - timeNow = _plat__RealTime(); - - // if this hasn't been initialized, initialize it - if(s_lastSystemTime == 0) - { - s_lastSystemTime = timeNow; - debugTime = clock(); - s_lastReportedTime = 0; - s_realTimePrevious = 0; - } - // The system time can bounce around and that's OK as long as we don't allow - // time to go backwards. When the time does appear to go backwards, set - // lastSystemTime to be the new value and then update the reported time. - if(timeNow < s_lastReportedTime) - s_lastSystemTime = timeNow; - s_lastReportedTime = s_lastReportedTime + timeNow - s_lastSystemTime; - s_lastSystemTime = timeNow; - timeNow = s_lastReportedTime; - - // The code above produces a timeNow that is similar to the value returned - // by Clock(). The difference is that timeNow does not max out, and it is - // at a ms. rate rather than at a CLOCKS_PER_SEC rate. The code below - // uses that value and does the rate adjustment on the time value. - // If there is no difference in time, then skip all the computations - if(s_realTimePrevious >= timeNow) - return s_tpmTime; - // Compute the amount of time since the last update of the system clock - timeDiff = timeNow - s_realTimePrevious; - - // Do the time rate adjustment and conversion from CLOCKS_PER_SEC to mSec - adjustedTimeDiff = (timeDiff * CLOCK_NOMINAL) / ((uint64_t)s_adjustRate); - - // update the TPM time with the adjusted timeDiff - s_tpmTime += (clock64_t)adjustedTimeDiff; - - // Might have some rounding error that would loose CLOCKS. See what is not - // being used. As mentioned above, this could result in putting back more than - // is taken out. Here, we are trying to recreate timeDiff. - readjustedTimeDiff = (adjustedTimeDiff * (uint64_t)s_adjustRate ) - / CLOCK_NOMINAL; - - // adjusted is now converted back to being the amount we should advance the - // previous sampled time. It should always be less than or equal to timeDiff. - // That is, we could not have use more time than we started with. - s_realTimePrevious = s_realTimePrevious + readjustedTimeDiff; - -#ifdef DEBUGGING_TIME - // Put this in so that TPM time will pass much faster than real time when - // doing debug. - // A value of 1000 for DEBUG_TIME_MULTIPLER will make each ms into a second - // A good value might be 100 - return (s_tpmTime * DEBUG_TIME_MULTIPLIER); -#endif - return s_tpmTime; -#endif -} - - - -//*** _plat__TimerWasReset() -// This function is used to interrogate the flag indicating if the tick timer has -// been reset. -// -// If the resetFlag parameter is SET, then the flag will be CLEAR before the -// function returns. -LIB_EXPORT BOOL -_plat__TimerWasReset( - void - ) -{ - BOOL retVal = s_timerReset; - s_timerReset = FALSE; - return retVal; -} - -//*** _plat__TimerWasStopped() -// This function is used to interrogate the flag indicating if the tick timer has -// been stopped. If so, this is typically a reason to roll the nonce. -// -// This function will CLEAR the s_timerStopped flag before returning. This provides -// functionality that is similar to status register that is cleared when read. This -// is the model used here because it is the one that has the most impact on the TPM -// code as the flag can only be accessed by one entity in the TPM. Any other -// implementation of the hardware can be made to look like a read-once register. -LIB_EXPORT BOOL -_plat__TimerWasStopped( - void - ) -{ - BOOL retVal = s_timerStopped; - s_timerStopped = FALSE; - return retVal; -} - -//***_plat__ClockAdjustRate() -// Adjust the clock rate -LIB_EXPORT void -_plat__ClockAdjustRate( - int adjust // IN: the adjust number. It could be positive - // or negative - ) -{ - // We expect the caller should only use a fixed set of constant values to - // adjust the rate - switch(adjust) - { - case CLOCK_ADJUST_COARSE: - s_adjustRate += CLOCK_ADJUST_COARSE; - break; - case -CLOCK_ADJUST_COARSE: - s_adjustRate -= CLOCK_ADJUST_COARSE; - break; - case CLOCK_ADJUST_MEDIUM: - s_adjustRate += CLOCK_ADJUST_MEDIUM; - break; - case -CLOCK_ADJUST_MEDIUM: - s_adjustRate -= CLOCK_ADJUST_MEDIUM; - break; - case CLOCK_ADJUST_FINE: - s_adjustRate += CLOCK_ADJUST_FINE; - break; - case -CLOCK_ADJUST_FINE: - s_adjustRate -= CLOCK_ADJUST_FINE; - break; - default: - // ignore any other values; - break; - } - - if(s_adjustRate > (CLOCK_NOMINAL + CLOCK_ADJUST_LIMIT)) - s_adjustRate = CLOCK_NOMINAL + CLOCK_ADJUST_LIMIT; - if(s_adjustRate < (CLOCK_NOMINAL - CLOCK_ADJUST_LIMIT)) - s_adjustRate = CLOCK_NOMINAL - CLOCK_ADJUST_LIMIT; - - return; -} - diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/DebugHelpers.c b/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/DebugHelpers.c deleted file mode 100644 index 65dba0e17..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/DebugHelpers.c +++ /dev/null @@ -1,134 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Description -// -// This file contains the NV read and write access methods. This implementation -// uses RAM/file and does not manage the RAM/file as NV blocks. -// The implementation may become more sophisticated over time. -// - -//** Includes and Local -#include -#include - -FILE *fDebug = NULL; -const char *fn = "DebugFile.txt"; - -static FILE* -fileOpen( - const char *fname, - const char *mode -) -{ - FILE *f; -#if defined _MSC_VER - if(fopen_s(&f, fname, mode) != 0) - f = NULL; -#else - f = fopen(fn, "w"); -#endif - return f; -} - -//*** DebugFileOpen() -// This function opens the file used to hold the debug data. -// Return Type: int -// 0 success -// != 0 error -int -DebugFileOpen( - void -) -{ -#if defined _MSC_VER - char timeString[100]; -#else - char *timeString; -#endif - time_t t = time(NULL); -// - // Get current date and time. -#if defined _MSC_VER - ctime_s(timeString, sizeof(timeString), &t); -#else - timeString = ctime(&t); -#endif - // Try to open the debug file - fDebug = fileOpen(fn, "w"); - if(fDebug) - { - fprintf(fDebug, "%s\n", timeString); - fclose(fDebug); - return 0; - } - return -1; -} - -void -DebugFileClose( - void -) -{ - if(fDebug) - fclose(fDebug); -} - -void -DebugDumpBuffer( - int size, - unsigned char *buf, - unsigned char *identifier -) -{ - int i; -// - FILE *f = fileOpen(fn, "a"); - if(!f) - return; - if(identifier) - fprintf(fDebug, "%s\n", identifier); - if(buf) - { - for(i = 0; i < size; i++) - { - if(((i % 16) == 0) && (i)) - fprintf(fDebug, "\n"); - fprintf(fDebug, " %02X", buf[i]); - } - if((size % 16) != 0) - fprintf(fDebug, "\n"); - } - fclose(f); -} diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/Entropy.c b/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/Entropy.c deleted file mode 100644 index 63ea079be..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/Entropy.c +++ /dev/null @@ -1,155 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Includes and Local Values - -#define _CRT_RAND_S -#include -#include -#include -#include "Platform.h" - -#ifdef _MSC_VER -#include -#else -#include -#endif - -// This is the last 32-bits of hardware entropy produced. We have to check to -// see that two consecutive 32-bit values are not the same because -// (according to FIPS 140-2, annex C -// -// "If each call to a RNG produces blocks of n bits (where n > 15), the first -// n-bit block generated after power-up, initialization, or reset shall not be -// used, but shall be saved for comparison with the next n-bit block to be -// generated. Each subsequent generation of an n-bit block shall be compared with -// the previously generated block. The test shall fail if any two compared n-bit -// blocks are equal." -extern uint32_t lastEntropy; - -//** Functions - -//*** rand32() -// Local function to get a 32-bit random number -static uint32_t -rand32( - void -) -{ - uint32_t rndNum = rand(); -#if RAND_MAX < UINT16_MAX - // If the maximum value of the random number is a 15-bit number, then shift it up - // 15 bits, get 15 more bits, shift that up 2 and then XOR in another value to get - // a full 32 bits. - rndNum = (rndNum << 15) ^ rand(); - rndNum = (rndNum << 2) ^ rand(); -#elif RAND_MAX == UINT16_MAX - // If the maximum size is 16-bits, shift it and add another 16 bits - rndNum = (rndNum << 16) ^ rand(); -#elif RAND_MAX < UINT32_MAX - // If 31 bits, then shift 1 and include another random value to get the extra bit - rndNum = (rndNum << 1) ^ rand(); -#endif - return rndNum; -} - - -//*** _plat__GetEntropy() -// This function is used to get available hardware entropy. In a hardware -// implementation of this function, there would be no call to the system -// to get entropy. -// Return Type: int32_t -// < 0 hardware failure of the entropy generator, this is sticky -// >= 0 the returned amount of entropy (bytes) -// -LIB_EXPORT int32_t -_plat__GetEntropy( - unsigned char *entropy, // output buffer - uint32_t amount // amount requested -) -{ - uint32_t rndNum; - int32_t ret; -// - if(amount == 0) - { - // Seed the platform entropy source if the entropy source is software. There - // is no reason to put a guard macro (#if or #ifdef) around this code because - // this code would not be here if someone was changing it for a system with - // actual hardware. - // - // NOTE 1: The following command does not provide proper cryptographic - // entropy. Its primary purpose to make sure that different instances of the - // simulator, possibly started by a script on the same machine, are seeded - // differently. Vendors of the actual TPMs need to ensure availability of - // proper entropy using their platform-specific means. - // - // NOTE 2: In debug builds by default the reference implementation will seed - // its RNG deterministically (without using any platform provided randomness). - // See the USE_DEBUG_RNG macro and DRBG_GetEntropy() function. -#ifdef _MSC_VER - srand((unsigned)_plat__RealTime() ^ _getpid()); -#else - srand((unsigned)_plat__RealTime() ^ getpid()); -#endif - lastEntropy = rand32(); - ret = 0; - } - else - { - rndNum = rand32(); - if(rndNum == lastEntropy) - { - ret = -1; - } - else - { - lastEntropy = rndNum; - // Each process will have its random number generator initialized - // according to the process id and the initialization time. This is not a - // lot of entropy so, to add a bit more, XOR the current time value into - // the returned entropy value. - // NOTE: the reason for including the time here rather than have it in - // in the value assigned to lastEntropy is that rand() could be broken and - // using the time would in the lastEntropy value would hide this. - rndNum ^= (uint32_t)_plat__RealTime(); - - // Only provide entropy 32 bits at a time to test the ability - // of the caller to deal with partial results. - ret = MIN(amount, sizeof(rndNum)); - memcpy(entropy, &rndNum, ret); - } - } - return ret; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/LocalityPlat.c b/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/LocalityPlat.c deleted file mode 100644 index 32bccd77b..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/LocalityPlat.c +++ /dev/null @@ -1,63 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Includes -#include "Platform.h" - -//** Functions - -//***_plat__LocalityGet() -// Get the most recent command locality in locality value form. -// This is an integer value for locality and not a locality structure -// The locality can be 0-4 or 32-255. 5-31 is not allowed. -LIB_EXPORT unsigned char -_plat__LocalityGet( - void - ) -{ - return s_locality; -} - -//***_plat__LocalitySet() -// Set the most recent command locality in locality value form -LIB_EXPORT void -_plat__LocalitySet( - unsigned char locality - ) -{ - if(locality > 4 && locality < 32) - locality = 0; - s_locality = locality; - return; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/NVMem.c b/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/NVMem.c deleted file mode 100644 index 6014b27fa..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/NVMem.c +++ /dev/null @@ -1,394 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Description -// -// This file contains the NV read and write access methods. This implementation -// uses RAM/file and does not manage the RAM/file as NV blocks. -// The implementation may become more sophisticated over time. -// - -//** Includes and Local -#include -#include -#include -#include "Platform.h" -#if FILE_BACKED_NV -# include -FILE *s_NvFile = NULL; -BOOL s_NeedsManufacture = FALSE; -#endif - -//**Functions - -#if FILE_BACKED_NV -//*** NvFileOpen() -// This function opens the file used to hold the NV image. -// Return Type: int -// >= 0 success -// -1 error -static int -NvFileOpen( - const char *mode -) -{ -#if defined(NV_FILE_PATH) -# define TO_STRING(s) TO_STRING_IMPL(s) -# define TO_STRING_IMPL(s) #s - const char* s_NvFilePath = TO_STRING(NV_FILE_PATH); -# undef TO_STRING -# undef TO_STRING_IMPL -#else - const char* s_NvFilePath = "NVChip"; -#endif - - // Try to open an exist NVChip file for read/write -# if defined _MSC_VER && 1 - if(fopen_s(&s_NvFile, s_NvFilePath, mode) != 0) - s_NvFile = NULL; -# else - s_NvFile = fopen(s_NvFilePath, mode); -# endif - return (s_NvFile == NULL) ? -1 : 0; -} - -//*** NvFileCommit() -// Write all of the contents of the NV image to a file. -// Return Type: int -// TRUE(1) success -// FALSE(0) failure -static int -NvFileCommit( - void -) -{ - int OK; - // If NV file is not available, return failure - if(s_NvFile == NULL) - return 1; - // Write RAM data to NV - fseek(s_NvFile, 0, SEEK_SET); - OK = (NV_MEMORY_SIZE == fwrite(s_NV, 1, NV_MEMORY_SIZE, s_NvFile)); - OK = OK && (0 == fflush(s_NvFile)); - assert(OK); - return OK; -} - -//*** NvFileSize() -// This function gets the size of the NV file and puts the file pointer were desired -// using the seek method values. SEEK_SET => beginning; SEEK_CUR => current position -// and SEEK_END => to the end of the file. -static long -NvFileSize( - int leaveAt -) -{ - long fileSize; - long filePos = ftell(s_NvFile); -// - assert(NULL != s_NvFile); - - fseek(s_NvFile, 0, SEEK_END); - fileSize = ftell(s_NvFile); - switch(leaveAt) - { - case SEEK_SET: - filePos = 0; - case SEEK_CUR: - fseek(s_NvFile, filePos, SEEK_SET); - break; - case SEEK_END: - break; - default: - assert(FALSE); - break; - } - return fileSize; -} -#endif - -//*** _plat__NvErrors() -// This function is used by the simulator to set the error flags in the NV -// subsystem to simulate an error in the NV loading process -LIB_EXPORT void -_plat__NvErrors( - int recoverable, - int unrecoverable - ) -{ - s_NV_unrecoverable = unrecoverable; - s_NV_recoverable = recoverable; -} - -//***_plat__NVEnable() -// Enable NV memory. -// -// This version just pulls in data from a file. In a real TPM, with NV on chip, -// this function would verify the integrity of the saved context. If the NV -// memory was not on chip but was in something like RPMB, the NV state would be -// read in, decrypted and integrity checked. -// -// The recovery from an integrity failure depends on where the error occurred. It -// it was in the state that is discarded by TPM Reset, then the error is -// recoverable if the TPM is reset. Otherwise, the TPM must go into failure mode. -// Return Type: int -// 0 if success -// > 0 if receive recoverable error -// <0 if unrecoverable error -LIB_EXPORT int -_plat__NVEnable( - void *platParameter // IN: platform specific parameters - ) -{ - NOT_REFERENCED(platParameter); // to keep compiler quiet -// - // Start assuming everything is OK - s_NV_unrecoverable = FALSE; - s_NV_recoverable = FALSE; -#if FILE_BACKED_NV - if(s_NvFile != NULL) - return 0; - // Initialize all the bytes in the ram copy of the NV - _plat__NvMemoryClear(0, NV_MEMORY_SIZE); - - // If the file exists - if(NvFileOpen("r+b") >= 0) - { - long fileSize = NvFileSize(SEEK_SET); // get the file size and leave the - // file pointer at the start -// - // If the size is right, read the data - if (NV_MEMORY_SIZE == fileSize) - { - s_NeedsManufacture = - fread(s_NV, 1, NV_MEMORY_SIZE, s_NvFile) != NV_MEMORY_SIZE; - } - else - { - NvFileCommit(); // for any other size, initialize it - s_NeedsManufacture = TRUE; - } - } - // If NVChip file does not exist, try to create it for read/write. - else if(NvFileOpen("w+b") >= 0) - { - NvFileCommit(); // Initialize the file - s_NeedsManufacture = TRUE; - } - assert(NULL != s_NvFile); // Just in case we are broken for some reason. -#endif - // NV contents have been initialized and the error checks have been performed. For - // simulation purposes, use the signaling interface to indicate if an error is - // to be simulated and the type of the error. - if(s_NV_unrecoverable) - return -1; - return s_NV_recoverable; -} - -//***_plat__NVDisable() -// Disable NV memory -LIB_EXPORT void -_plat__NVDisable( - void - ) -{ -#if FILE_BACKED_NV - if(NULL != s_NvFile) - fclose(s_NvFile); // Close NV file - s_NvFile = NULL; // Set file handle to NULL -#endif - return; -} - -//***_plat__IsNvAvailable() -// Check if NV is available -// Return Type: int -// 0 NV is available -// 1 NV is not available due to write failure -// 2 NV is not available due to rate limit -LIB_EXPORT int -_plat__IsNvAvailable( - void - ) -{ - int retVal = 0; - // NV is not available if the TPM is in failure mode - if(!s_NvIsAvailable) - retVal = 1; -#if FILE_BACKED_NV - else - retVal = (s_NvFile == NULL); -#endif - return retVal; -} - -//***_plat__NvMemoryRead() -// Function: Read a chunk of NV memory -LIB_EXPORT void -_plat__NvMemoryRead( - unsigned int startOffset, // IN: read start - unsigned int size, // IN: size of bytes to read - void *data // OUT: data buffer - ) -{ - assert(startOffset + size <= NV_MEMORY_SIZE); - memcpy(data, &s_NV[startOffset], size); // Copy data from RAM - return; -} - -//*** _plat__NvIsDifferent() -// This function checks to see if the NV is different from the test value. This is -// so that NV will not be written if it has not changed. -// Return Type: int -// TRUE(1) the NV location is different from the test value -// FALSE(0) the NV location is the same as the test value -LIB_EXPORT int -_plat__NvIsDifferent( - unsigned int startOffset, // IN: read start - unsigned int size, // IN: size of bytes to read - void *data // IN: data buffer - ) -{ - return (memcmp(&s_NV[startOffset], data, size) != 0); -} - -//***_plat__NvMemoryWrite() -// This function is used to update NV memory. The "write" is to a memory copy of -// NV. At the end of the current command, any changes are written to -// the actual NV memory. -// NOTE: A useful optimization would be for this code to compare the current -// contents of NV with the local copy and note the blocks that have changed. Then -// only write those blocks when _plat__NvCommit() is called. -LIB_EXPORT BOOL -_plat__NvMemoryWrite( - unsigned int startOffset, // IN: write start - unsigned int size, // IN: size of bytes to write - void *data // OUT: data buffer - ) -{ - if(startOffset + size <= NV_MEMORY_SIZE) - { - memcpy(&s_NV[startOffset], data, size); // Copy the data to the NV image - return TRUE; - } - return FALSE; -} - -//***_plat__NvMemoryClear() -// Function is used to set a range of NV memory bytes to an implementation-dependent -// value. The value represents the erase state of the memory. -LIB_EXPORT void -_plat__NvMemoryClear( - unsigned int start, // IN: clear start - unsigned int size // IN: number of bytes to clear - ) -{ - assert(start + size <= NV_MEMORY_SIZE); - // In this implementation, assume that the erase value for NV is all 1s - memset(&s_NV[start], 0xff, size); -} - -//***_plat__NvMemoryMove() -// Function: Move a chunk of NV memory from source to destination -// This function should ensure that if there overlap, the original data is -// copied before it is written -LIB_EXPORT void -_plat__NvMemoryMove( - unsigned int sourceOffset, // IN: source offset - unsigned int destOffset, // IN: destination offset - unsigned int size // IN: size of data being moved - ) -{ - assert(sourceOffset + size <= NV_MEMORY_SIZE); - assert(destOffset + size <= NV_MEMORY_SIZE); - memmove(&s_NV[destOffset], &s_NV[sourceOffset], size); // Move data in RAM - return; -} - -//***_plat__NvCommit() -// This function writes the local copy of NV to NV for permanent store. It will write -// NV_MEMORY_SIZE bytes to NV. If a file is use, the entire file is written. -// Return Type: int -// 0 NV write success -// non-0 NV write fail -LIB_EXPORT int -_plat__NvCommit( - void - ) -{ -#if FILE_BACKED_NV - return (NvFileCommit() ? 0 : 1); -#else - return 0; -#endif -} - -//***_plat__SetNvAvail() -// Set the current NV state to available. This function is for testing purpose -// only. It is not part of the platform NV logic -LIB_EXPORT void -_plat__SetNvAvail( - void - ) -{ - s_NvIsAvailable = TRUE; - return; -} - -//***_plat__ClearNvAvail() -// Set the current NV state to unavailable. This function is for testing purpose -// only. It is not part of the platform NV logic -LIB_EXPORT void -_plat__ClearNvAvail( - void - ) -{ - s_NvIsAvailable = FALSE; - return; -} - -//*** _plat__NVNeedsManufacture() -// This function is used by the simulator to determine when the TPM's NV state -// needs to be manufactured. -LIB_EXPORT BOOL -_plat__NVNeedsManufacture( - void - ) -{ -#if FILE_BACKED_NV - return s_NeedsManufacture; -#else - return FALSE; -#endif -} diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/PPPlat.c b/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/PPPlat.c deleted file mode 100644 index 5b8433c78..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/PPPlat.c +++ /dev/null @@ -1,79 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Description - -// This module simulates the physical presence interface pins on the TPM. - -//** Includes -#include "Platform.h" - -//** Functions - -//***_plat__PhysicalPresenceAsserted() -// Check if physical presence is signaled -// Return Type: int -// TRUE(1) if physical presence is signaled -// FALSE(0) if physical presence is not signaled -LIB_EXPORT int -_plat__PhysicalPresenceAsserted( - void - ) -{ - // Do not know how to check physical presence without real hardware. - // so always return TRUE; - return s_physicalPresence; -} - -//***_plat__Signal_PhysicalPresenceOn() -// Signal physical presence on -LIB_EXPORT void -_plat__Signal_PhysicalPresenceOn( - void - ) -{ - s_physicalPresence = TRUE; - return; -} - -//***_plat__Signal_PhysicalPresenceOff() -// Signal physical presence off -LIB_EXPORT void -_plat__Signal_PhysicalPresenceOff( - void - ) -{ - s_physicalPresence = FALSE; - return; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/PlatformData.c b/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/PlatformData.c deleted file mode 100644 index a1d60e1e5..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/PlatformData.c +++ /dev/null @@ -1,81 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Description -// This file will instance the TPM variables that are not stack allocated. The -// descriptions for these variables are in Global.h for this project. - -//** Includes -#include "Platform.h" - -// From Cancel.c -BOOL s_isCanceled; - -// From Clock.c -unsigned int s_adjustRate; -BOOL s_timerReset; -BOOL s_timerStopped; - -#ifndef HARDWARE_CLOCK -clock64_t s_realTimePrevious; -clock64_t s_tpmTime; - -clock64_t s_lastSystemTime; -clock64_t s_lastReportedTime; - - -#endif - - -// From LocalityPlat.c -unsigned char s_locality; - -// From Power.c -BOOL s_powerLost; - -// From Entropy.c -// This values is used to determine if the entropy generator is broken. If two -// consecutive values are the same, then the entropy generator is considered to be -// broken. -uint32_t lastEntropy; - - -// For NVMem.c -unsigned char s_NV[NV_MEMORY_SIZE]; -BOOL s_NvIsAvailable; -BOOL s_NV_unrecoverable; -BOOL s_NV_recoverable; - -// From PPPlat.c -BOOL s_physicalPresence; \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/PowerPlat.c b/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/PowerPlat.c deleted file mode 100644 index c8b689687..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/PowerPlat.c +++ /dev/null @@ -1,112 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Includes and Function Prototypes - -#include "Platform.h" -#include "_TPM_Init_fp.h" - -//** Functions - -//***_plat__Signal_PowerOn() -// Signal platform power on -LIB_EXPORT int -_plat__Signal_PowerOn( - void - ) -{ - // Reset the timer - _plat__TimerReset(); - - // Need to indicate that we lost power - s_powerLost = TRUE; - - return 0; -} - -//*** _plat__WasPowerLost() -// Test whether power was lost before a _TPM_Init. -// -// This function will clear the "hardware" indication of power loss before return. -// This means that there can only be one spot in the TPM code where this value -// gets read. This method is used here as it is the most difficult to manage in the -// TPM code and, if the hardware actually works this way, it is hard to make it -// look like anything else. So, the burden is placed on the TPM code rather than the -// platform code -// Return Type: int -// TRUE(1) power was lost -// FALSE(0) power was not lost -LIB_EXPORT int -_plat__WasPowerLost( - void - ) -{ - BOOL retVal = s_powerLost; - s_powerLost = FALSE; - return retVal; -} - -//*** _plat_Signal_Reset() -// This a TPM reset without a power loss. -LIB_EXPORT int -_plat__Signal_Reset( - void - ) -{ - // Initialize locality - s_locality = 0; - - // Command cancel - s_isCanceled = FALSE; - - _TPM_Init(); - - // if we are doing reset but did not have a power failure, then we should - // not need to reload NV ... - - return 0; -} - -//***_plat__Signal_PowerOff() -// Signal platform power off -LIB_EXPORT void -_plat__Signal_PowerOff( - void - ) -{ - // Prepare NV memory for power off - _plat__NVDisable(); - - return; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/RunCommand.c b/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/RunCommand.c deleted file mode 100644 index 8d4c4df8f..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/RunCommand.c +++ /dev/null @@ -1,86 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//**Introduction -// This module provides the platform specific entry and fail processing. The -// _plat__RunCommand() function is used to call to ExecuteCommand() in the TPM code. -// This function does whatever processing is necessary to set up the platform -// in anticipation of the call to the TPM including settup for error processing. -// -// The _plat__Fail() function is called when there is a failure in the TPM. The TPM -// code will have set the flag to indicate that the TPM is in failure mode. -// This call will then recursively call ExecuteCommand in order to build the -// failure mode response. When ExecuteCommand() returns to _plat__Fail(), the -// platform will do some platform specif operation to return to the environment in -// which the TPM is executing. For a simulator, setjmp/longjmp is used. For an OS, -// a system exit to the OS would be appropriate. - -//** Includes and locals -#include "Platform.h" -#include -#include "ExecCommand_fp.h" - -jmp_buf s_jumpBuffer; - -//** Functions - -//***_plat__RunCommand() -// This version of RunCommand will set up a jum_buf and call ExecuteCommand(). If -// the command executes without failing, it will return and RunCommand will return. -// If there is a failure in the command, then _plat__Fail() is called and it will -// longjump back to RunCommand which will call ExecuteCommand again. However, this -// time, the TPM will be in failure mode so ExecuteCommand will simply build -// a failure response and return. -LIB_EXPORT void -_plat__RunCommand( - uint32_t requestSize, // IN: command buffer size - unsigned char *request, // IN: command buffer - uint32_t *responseSize, // IN/OUT: response buffer size - unsigned char **response // IN/OUT: response buffer - ) -{ - setjmp(s_jumpBuffer); - ExecuteCommand(requestSize, request, responseSize, response); -} - - -//***_plat__Fail() -// This is the platform depended failure exit for the TPM. -LIB_EXPORT NORETURN void -_plat__Fail( - void - ) -{ - longjmp(&s_jumpBuffer[0], 1); -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/Unique.c b/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/Unique.c deleted file mode 100644 index 7c935c856..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Platform/src/Unique.c +++ /dev/null @@ -1,88 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Introduction -// In some implementations of the TPM, the hardware can provide a secret -// value to the TPM. This secret value is statistically unique to the -// instance of the TPM. Typical uses of this value are to provide -// personalization to the random number generation and as a shared secret -// between the TPM and the manufacturer. - -//** Includes -#include "Platform.h" - -const char notReallyUnique[] = -"This is not really a unique value. A real unique value should" -" be generated by the platform."; - -//** _plat__GetUnique() -// This function is used to access the platform-specific unique value. -// This function places the unique value in the provided buffer ('b') -// and returns the number of bytes transferred. The function will not -// copy more data than 'bSize'. -// NOTE: If a platform unique value has unequal distribution of uniqueness -// and 'bSize' is smaller than the size of the unique value, the 'bSize' -// portion with the most uniqueness should be returned. -LIB_EXPORT uint32_t -_plat__GetUnique( - uint32_t which, // authorities (0) or details - uint32_t bSize, // size of the buffer - unsigned char *b // output buffer - ) -{ - const char *from = notReallyUnique; - uint32_t retVal = 0; - - if(which == 0) // the authorities value - { - for(retVal = 0; - *from != 0 && retVal < bSize; - retVal++) - { - *b++ = *from++; - } - } - else - { -#define uSize sizeof(notReallyUnique) - b = &b[((bSize < uSize) ? bSize : uSize) - 1]; - for(retVal = 0; - *from != 0 && retVal < bSize; - retVal++) - { - *b-- = *from++; - } - } - return retVal; -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Simulator/include/TpmTcpProtocol.h b/simulator/ms-tpm-20-ref/TPMCmd/Simulator/include/TpmTcpProtocol.h deleted file mode 100644 index 9113dbea8..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Simulator/include/TpmTcpProtocol.h +++ /dev/null @@ -1,125 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Introduction - -// TPM commands are communicated as BYTE streams on a TCP connection. The TPM -// command protocol is enveloped with the interface protocol described in this -// file. The command is indicated by a UINT32 with one of the values below. Most -// commands take no parameters return no TPM errors. In these cases the TPM -// interface protocol acknowledges that command processing is completed by returning -// a UINT32=0. The command TPM_SIGNAL_HASH_DATA takes a UINT32-prepended variable -// length BYTE array and the interface protocol acknowledges command completion -// with a UINT32=0. Most TPM commands are enveloped using the TPM_SEND_COMMAND -// interface command. The parameters are as indicated below. The interface layer -// also appends a UIN32=0 to the TPM response for regularity. - - -//** Typedefs and Defines -#ifndef TCP_TPM_PROTOCOL_H -#define TCP_TPM_PROTOCOL_H - -//** TPM Commands. -// All commands acknowledge processing by returning a UINT32 == 0 except where noted -#define TPM_SIGNAL_POWER_ON 1 -#define TPM_SIGNAL_POWER_OFF 2 -#define TPM_SIGNAL_PHYS_PRES_ON 3 -#define TPM_SIGNAL_PHYS_PRES_OFF 4 -#define TPM_SIGNAL_HASH_START 5 -#define TPM_SIGNAL_HASH_DATA 6 - // {UINT32 BufferSize, BYTE[BufferSize] Buffer} -#define TPM_SIGNAL_HASH_END 7 -#define TPM_SEND_COMMAND 8 - // {BYTE Locality, UINT32 InBufferSize, BYTE[InBufferSize] InBuffer} -> - // {UINT32 OutBufferSize, BYTE[OutBufferSize] OutBuffer} - -#define TPM_SIGNAL_CANCEL_ON 9 -#define TPM_SIGNAL_CANCEL_OFF 10 -#define TPM_SIGNAL_NV_ON 11 -#define TPM_SIGNAL_NV_OFF 12 -#define TPM_SIGNAL_KEY_CACHE_ON 13 -#define TPM_SIGNAL_KEY_CACHE_OFF 14 - -#define TPM_REMOTE_HANDSHAKE 15 -#define TPM_SET_ALTERNATIVE_RESULT 16 - -#define TPM_SIGNAL_RESET 17 -#define TPM_SIGNAL_RESTART 18 - -#define TPM_SESSION_END 20 -#define TPM_STOP 21 - -#define TPM_GET_COMMAND_RESPONSE_SIZES 25 - -#define TPM_TEST_FAILURE_MODE 30 - -//** Enumerations and Structures -enum TpmEndPointInfo -{ - tpmPlatformAvailable = 0x01, - tpmUsesTbs = 0x02, - tpmInRawMode = 0x04, - tpmSupportsPP = 0x08 -}; - -#ifdef _MSC_VER -# pragma warning(push, 3) -#endif - -// Existing RPC interface type definitions retained so that the implementation -// can be re-used -typedef struct in_buffer -{ - unsigned long BufferSize; - unsigned char *Buffer; -} _IN_BUFFER; - -typedef unsigned char *_OUTPUT_BUFFER; - -typedef struct out_buffer -{ - uint32_t BufferSize; - _OUTPUT_BUFFER Buffer; -} _OUT_BUFFER; - -#ifdef _MSC_VER -# pragma warning(pop) -#endif - -#ifndef WIN32 -typedef unsigned long DWORD; -typedef void *LPVOID; -#endif - -#endif diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Simulator/include/prototypes/Simulator_fp.h b/simulator/ms-tpm-20-ref/TPMCmd/Simulator/include/prototypes/Simulator_fp.h deleted file mode 100644 index a75938a01..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Simulator/include/prototypes/Simulator_fp.h +++ /dev/null @@ -1,287 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*(Auto-generated) - * Created by TpmPrototypes; Version 3.0 July 18, 2017 - * Date: Nov 2, 2018 Time: 11:14:29AM - */ - -#ifndef _SIMULATOR_FP_H_ -#define _SIMULATOR_FP_H_ - -//** From TcpServer.c - -//*** PlatformServer() -// This function processes incoming platform requests. -BOOL -PlatformServer( - SOCKET s - ); - -//*** PlatformSvcRoutine() -// This function is called to set up the socket interfaces to listen for -// commands. -DWORD WINAPI -PlatformSvcRoutine( - LPVOID port - ); - -//*** PlatformSignalService() -// This function starts a new thread waiting for platform signals. -// Platform signals are processed one at a time in the order in which they are -// received. -int -PlatformSignalService( - int PortNumber - ); - -//*** RegularCommandService() -// This function services regular commands. -int -RegularCommandService( - int PortNumber - ); - -//*** StartTcpServer() -// This is the main entry-point to the TCP server. The server listens on port -// specified. -// -// Note that there is no way to specify the network interface in this implementation. -int -StartTcpServer( - int PortNumber - ); - -//*** ReadBytes() -// This function reads the indicated number of bytes ('NumBytes') into buffer -// from the indicated socket. -BOOL -ReadBytes( - SOCKET s, - char *buffer, - int NumBytes - ); - -//*** WriteBytes() -// This function will send the indicated number of bytes ('NumBytes') to the -// indicated socket -BOOL -WriteBytes( - SOCKET s, - char *buffer, - int NumBytes - ); - -//*** WriteUINT32() -// Send 4 bytes containing hton(1) -BOOL -WriteUINT32( - SOCKET s, - uint32_t val - ); - -//*** ReadVarBytes() -// Get a UINT32-length-prepended binary array. Note that the 4-byte length is -// in network byte order (big-endian). -BOOL -ReadVarBytes( - SOCKET s, - char *buffer, - uint32_t *BytesReceived, - int MaxLen - ); - -//*** WriteVarBytes() -// Send a UINT32-length-prepended binary array. Note that the 4-byte length is -// in network byte order (big-endian). -BOOL -WriteVarBytes( - SOCKET s, - char *buffer, - int BytesToSend - ); - -//*** TpmServer() -// Processing incoming TPM command requests using the protocol / interface -// defined above. -BOOL -TpmServer( - SOCKET s - ); - - -//** From TPMCmdp.c - -//*** Signal_PowerOn() -// This function processes a power-on indication. Among other things, it -// calls the _TPM_Init() handler. -void -_rpc__Signal_PowerOn( - BOOL isReset - ); - -//*** Signal_Restart() -// This function processes the clock restart indication. All it does is call -// the platform function. -void -_rpc__Signal_Restart( - void - ); - -//***Signal_PowerOff() -// This function processes the power off indication. Its primary function is -// to set a flag indicating that the next power on indication should cause -// _TPM_Init() to be called. -void -_rpc__Signal_PowerOff( - void - ); - -//*** _rpc__ForceFailureMode() -// This function is used to debug the Failure Mode logic of the TPM. It will set -// a flag in the TPM code such that the next call to TPM2_SelfTest() will result -// in a failure, putting the TPM into Failure Mode. -void -_rpc__ForceFailureMode( - void - ); - -//*** _rpc__Signal_PhysicalPresenceOn() -// This function is called to simulate activation of the physical presence "pin". -void -_rpc__Signal_PhysicalPresenceOn( - void - ); - -//*** _rpc__Signal_PhysicalPresenceOff() -// This function is called to simulate deactivation of the physical presence "pin". -void -_rpc__Signal_PhysicalPresenceOff( - void - ); - -//*** _rpc__Signal_Hash_Start() -// This function is called to simulate a _TPM_Hash_Start event. It will call -// -void -_rpc__Signal_Hash_Start( - void - ); - -//*** _rpc__Signal_Hash_Data() -// This function is called to simulate a _TPM_Hash_Data event. -void -_rpc__Signal_Hash_Data( - _IN_BUFFER input - ); - -//*** _rpc__Signal_HashEnd() -// This function is called to simulate a _TPM_Hash_End event. -void -_rpc__Signal_HashEnd( - void - ); - -//*** _rpc__Send_Command() -// This is the interface to the TPM code. -// Return Type: void -void -_rpc__Send_Command( - unsigned char locality, - _IN_BUFFER request, - _OUT_BUFFER *response - ); - -//*** _rpc__Signal_CancelOn() -// This function is used to turn on the indication to cancel a command in process. -// An executing command is not interrupted. The command code may periodically check -// this indication to see if it should abort the current command processing and -// returned TPM_RC_CANCELLED. -void -_rpc__Signal_CancelOn( - void - ); - -//*** _rpc__Signal_CancelOff() -// This function is used to turn off the indication to cancel a command in process. -void -_rpc__Signal_CancelOff( - void - ); - -//*** _rpc__Signal_NvOn() -// In a system where the NV memory used by the TPM is not within the TPM, the -// NV may not always be available. This function turns on the indicator that -// indicates that NV is available. -void -_rpc__Signal_NvOn( - void - ); - -//*** _rpc__Signal_NvOff() -// This function is used to set the indication that NV memory is no -// longer available. -void -_rpc__Signal_NvOff( - void - ); - -//*** _rpc__RsaKeyCacheControl() -// This function is used to enable/disable the use of the RSA key cache during -// simulation. -void -_rpc__RsaKeyCacheControl( - int state - ); - -//*** _rpc__Shutdown() -// This function is used to stop the TPM simulator. -void -_rpc__Shutdown( - void - ); - - -//** From TPMCmds.c - -//*** main() -// This is the main entry point for the simulator. -// It registers the interface and starts listening for clients -int -main( - int argc, - char *argv[] - ); - -#endif // _SIMULATOR_FP_H_ diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Simulator/simulator.vcxproj b/simulator/ms-tpm-20-ref/TPMCmd/Simulator/simulator.vcxproj deleted file mode 100644 index 42baba54e..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Simulator/simulator.vcxproj +++ /dev/null @@ -1,484 +0,0 @@ - - - - - Debug - Win32 - - - Debug - x64 - - - Release - Win32 - - - Release - x64 - - - Static - Win32 - - - Static - x64 - - - WolfDebug - Win32 - - - WolfDebug - x64 - - - WolfRelease - Win32 - - - WolfRelease - x64 - - - - {AAB9FA21-8671-4792-B000-B40A526058AD} - simulator - Win32Proj - Simulator - 8.1 - - - - Application - Unicode - false - v140 - - - Application - Unicode - false - v140 - - - Application - Unicode - false - v140 - - - Application - Unicode - false - v140 - - - Application - Unicode - v140 - - - Application - Unicode - v140 - - - Application - Unicode - v140 - - - Application - Unicode - v140 - - - Application - Unicode - v140 - - - Application - Unicode - v140 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - <_ProjectFileVersion>10.0.30319.1 - $(SolutionDir)\$(Configuration)\ - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - true - true - true - true - true - true - $(SolutionDir)\$(Configuration)\ - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - false - false - false - false - AllRules.ruleset - AllRules.ruleset - AllRules.ruleset - AllRules.ruleset - AllRules.ruleset - AllRules.ruleset - - - - - - - - - - - - - AllRules.ruleset - AllRules.ruleset - AllRules.ruleset - AllRules.ruleset - - - - - - - - - - - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - - - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - - - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - - - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - - - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - - - false - - - false - - - - Disabled - $(ProjectDir)include\;$(ProjectDir)include\prototypes;$(SolutionDir)tpm\include\;$(SolutionDir)tpm\include\prototypes;$(SolutionDir)platform\include\;$(SolutionDir)platform\include\prototypes - WIN32;DEBUG;_CONSOLE;%(PreprocessorDefinitions);_DIAGNOSTICS - true - EnableFastChecks - MultiThreadedDebugDLL - NotUsing - EnableAllWarnings - ProgramDatabase - CompileAsC - true - true - 4668; 4710; 4711;4820 - - - tpm.lib;platform.lib;Ws2_32.lib;Rpcrt4.lib;%(AdditionalDependencies) - $(OutDir);%(AdditionalLibraryDirectories) - true - Console - MachineX86 - $(OutDir)$(TargetName)$(TargetExt) - false - $(OutDir)Simulator.map - false - - - true - - - - - Disabled - $(ProjectDir)include\;$(ProjectDir)include\prototypes;$(SolutionDir)tpm\include\;$(SolutionDir)tpm\include\prototypes;$(SolutionDir)platform\include\;$(SolutionDir)platform\include\prototypes - WIN32;DEBUG;_CONSOLE;%(PreprocessorDefinitions);_DIAGNOSTICS - true - EnableFastChecks - MultiThreadedDebugDLL - NotUsing - EnableAllWarnings - ProgramDatabase - CompileAsC - true - true - 4668; 4710; 4711;4820 - - - tpm.lib;platform.lib;Ws2_32.lib;Rpcrt4.lib;%(AdditionalDependencies) - $(OutDir);%(AdditionalLibraryDirectories) - true - Console - MachineX86 - $(OutDir)$(TargetName)$(TargetExt) - false - $(OutDir)Simulator.map - false - - - true - - - - - Disabled - $(ProjectDir)include\;$(ProjectDir)include\prototypes;$(SolutionDir)tpm\include\;$(SolutionDir)tpm\include\prototypes;$(SolutionDir)platform\include\;$(SolutionDir)platform\include\prototypes - WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_DIAGNOSTICS - true - EnableFastChecks - MultiThreadedDebugDLL - NotUsing - EnableAllWarnings - ProgramDatabase - CompileAsC - true - 4668; 4710; 4711;4820 - - - libeay32.lib;tpm.lib;platform.lib;Ws2_32.lib;Rpcrt4.lib;%(AdditionalDependencies) - $(SolutionDir)\lib;$(OutDir);%(AdditionalLibraryDirectories) - true - Console - MachineX86 - $(OutDir)$(TargetName)$(TargetExt) - - - - - Disabled - $(ProjectDir)include\;$(ProjectDir)include\prototypes;$(SolutionDir)tpm\include\;$(SolutionDir)tpm\include\prototypes;$(SolutionDir)platform\include\;$(SolutionDir)platform\include\prototypes - WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_DIAGNOSTICS - EnableFastChecks - MultiThreadedDebugDLL - - - EnableAllWarnings - ProgramDatabase - true - 4668; 4710; 4711;4820 - - - tpm.lib;platform.lib;Ws2_32.lib;Rpcrt4.lib;%(AdditionalDependencies) - $(OutDir);%(AdditionalLibraryDirectories) - true - Console - - - - - Disabled - $(ProjectDir)include\;$(ProjectDir)include\prototypes;$(SolutionDir)tpm\include\;$(SolutionDir)tpm\include\prototypes;$(SolutionDir)platform\include\;$(SolutionDir)platform\include\prototypes - WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_DIAGNOSTICS - EnableFastChecks - MultiThreadedDebugDLL - - - EnableAllWarnings - ProgramDatabase - true - 4668; 4710; 4711;4820 - - - tpm.lib;platform.lib;Ws2_32.lib;Rpcrt4.lib;%(AdditionalDependencies) - $(OutDir);%(AdditionalLibraryDirectories) - true - Console - - - - - Disabled - $(ProjectDir)include\;$(ProjectDir)include\prototypes;$(SolutionDir)tpm\include\;$(SolutionDir)tpm\include\prototypes;$(SolutionDir)platform\include\;$(SolutionDir)platform\include\prototypes - WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_DIAGNOSTICS - EnableFastChecks - MultiThreadedDebugDLL - - - EnableAllWarnings - ProgramDatabase - true - 4668; 4710; 4711;4820 - - - libeay32.lib;tpm.lib;platform.lib;Ws2_32.lib;Rpcrt4.lib;%(AdditionalDependencies) - $(SolutionDir)\lib\x64;$(OutDir);%(AdditionalLibraryDirectories) - true - Console - - - - - MaxSpeed - true - WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - MultiThreadedDLL - true - NotUsing - EnableAllWarnings - ProgramDatabase - $(ProjectDir)include\;$(ProjectDir)include\prototypes;$(SolutionDir)tpm\include\;$(SolutionDir)tpm\include\prototypes;$(SolutionDir)platform\include\;$(SolutionDir)platform\include\prototypes - true - 4668; 4710; 4711;4820 - - - true - Console - true - true - MachineX86 - tpm.lib;platform.lib;Ws2_32.lib;Rpcrt4.lib;%(AdditionalDependencies) - $(OutDir);%(AdditionalLibraryDirectories) - $(OutDir)$(TargetName)$(TargetExt) - - - - - MaxSpeed - true - WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - MultiThreadedDLL - true - NotUsing - EnableAllWarnings - ProgramDatabase - $(ProjectDir)include\;$(ProjectDir)include\prototypes;$(SolutionDir)tpm\include\;$(SolutionDir)tpm\include\prototypes;$(SolutionDir)platform\include\;$(SolutionDir)platform\include\prototypes - true - 4668; 4710; 4711;4820 - - - true - Console - true - true - MachineX86 - tpm.lib;platform.lib;Ws2_32.lib;Rpcrt4.lib;%(AdditionalDependencies) - $(OutDir);%(AdditionalLibraryDirectories) - $(OutDir)$(TargetName)$(TargetExt) - - - - - MaxSpeed - true - WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - MultiThreadedDLL - true - - - EnableAllWarnings - ProgramDatabase - $(ProjectDir)include\;$(ProjectDir)include\prototypes;$(SolutionDir)tpm\include\;$(SolutionDir)tpm\include\prototypes;$(SolutionDir)platform\include\;$(SolutionDir)platform\include\prototypes - true - 4668; 4710; 4711;4820 - - - true - Console - true - true - tpm.lib;platform.lib;Ws2_32.lib;Rpcrt4.lib - $(OutDir);%(AdditionalLibraryDirectories) - - - false - - - - - MaxSpeed - true - WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - MultiThreadedDLL - true - - - EnableAllWarnings - ProgramDatabase - $(ProjectDir)include\;$(ProjectDir)include\prototypes;$(SolutionDir)tpm\include\;$(SolutionDir)tpm\include\prototypes;$(SolutionDir)platform\include\;$(SolutionDir)platform\include\prototypes - true - 4668; 4710; 4711;4820 - - - true - Console - true - true - tpm.lib;platform.lib;Ws2_32.lib;Rpcrt4.lib - $(ProjectDir)\lib;$(OutDir);%(AdditionalLibraryDirectories) - - - false - - - - - - - - - - - - - - \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Simulator/simulator.vcxproj.filters b/simulator/ms-tpm-20-ref/TPMCmd/Simulator/simulator.vcxproj.filters deleted file mode 100644 index 17b4626cc..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Simulator/simulator.vcxproj.filters +++ /dev/null @@ -1,27 +0,0 @@ - - - - - Source Files - - - Source Files - - - Source Files - - - - - {58589a8e-94bb-4128-b2fb-eaba000b1905} - - - {2786f12f-9161-45a4-ad11-8ef2615451be} - - - - - Headers - - - \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Simulator/src/TPMCmdp.c b/simulator/ms-tpm-20-ref/TPMCmd/Simulator/src/TPMCmdp.c deleted file mode 100644 index 58202da67..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Simulator/src/TPMCmdp.c +++ /dev/null @@ -1,336 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Description -// This file contains the functions that process the commands received on the -// control port or the command port of the simulator. The control port is used -// to allow simulation of hardware events (such as, _TPM_Hash_Start) to test -// the simulated TPM's reaction to those events. This improves code coverage -// of the testing. - -//** Includes and Data Definitions -#include -#include -#include -#include "TpmBuildSwitches.h" -#include "BaseTypes.h" - -#ifdef _MSC_VER -# pragma warning(push, 3) -# include -# include -# pragma warning(pop) -#elif defined(__unix__) - typedef int SOCKET; -#else -# error "Unsupported platform." -#endif - -#ifndef TRUE -# define TRUE 1 -#endif -#ifndef FALSE -# define FALSE 0 -#endif - -#include "Platform_fp.h" -#include "ExecCommand_fp.h" -#include "Manufacture_fp.h" -#include "_TPM_Init_fp.h" -#include "_TPM_Hash_Start_fp.h" -#include "_TPM_Hash_Data_fp.h" -#include "_TPM_Hash_End_fp.h" -#include "TpmFail_fp.h" - -#include "TpmTcpProtocol.h" -#include "Simulator_fp.h" - -static BOOL s_isPowerOn = FALSE; - -//** Functions - -//*** Signal_PowerOn() -// This function processes a power-on indication. Among other things, it -// calls the _TPM_Init() handler. -void -_rpc__Signal_PowerOn( - BOOL isReset - ) -{ - // if power is on and this is not a call to do TPM reset then return - if(s_isPowerOn && !isReset) - return; - - // If this is a reset but power is not on, then return - if(isReset && !s_isPowerOn) - return; - - // Unless this is just a reset, pass power on signal to platform - if(!isReset) - _plat__Signal_PowerOn(); - - // Power on and reset both lead to _TPM_Init() - _plat__Signal_Reset(); - - - // Set state as power on - s_isPowerOn = TRUE; -} - -//*** Signal_Restart() -// This function processes the clock restart indication. All it does is call -// the platform function. -void -_rpc__Signal_Restart( - void - ) -{ - _plat__TimerRestart(); -} - -//***Signal_PowerOff() -// This function processes the power off indication. Its primary function is -// to set a flag indicating that the next power on indication should cause -// _TPM_Init() to be called. -void -_rpc__Signal_PowerOff( - void - ) -{ - if(!s_isPowerOn) return; - - // Pass power off signal to platform - _plat__Signal_PowerOff(); - - s_isPowerOn = FALSE; - - return; -} - -//*** _rpc__ForceFailureMode() -// This function is used to debug the Failure Mode logic of the TPM. It will set -// a flag in the TPM code such that the next call to TPM2_SelfTest() will result -// in a failure, putting the TPM into Failure Mode. -void -_rpc__ForceFailureMode( - void - ) -{ - SetForceFailureMode(); -} - -//*** _rpc__Signal_PhysicalPresenceOn() -// This function is called to simulate activation of the physical presence "pin". -void -_rpc__Signal_PhysicalPresenceOn( - void - ) -{ - // If TPM is power off, reject this signal - if(!s_isPowerOn) return; - - // Pass physical presence on to platform - _plat__Signal_PhysicalPresenceOn(); - - return; -} - -//*** _rpc__Signal_PhysicalPresenceOff() -// This function is called to simulate deactivation of the physical presence "pin". -void -_rpc__Signal_PhysicalPresenceOff( - void - ) -{ - // If TPM is power off, reject this signal - if(!s_isPowerOn) return; - - // Pass physical presence off to platform - _plat__Signal_PhysicalPresenceOff(); - - return; -} - -//*** _rpc__Signal_Hash_Start() -// This function is called to simulate a _TPM_Hash_Start event. It will call -// -void -_rpc__Signal_Hash_Start( - void - ) -{ - // If TPM is power off, reject this signal - if(!s_isPowerOn) return; - - // Pass _TPM_Hash_Start signal to TPM - _TPM_Hash_Start(); - return; -} - -//*** _rpc__Signal_Hash_Data() -// This function is called to simulate a _TPM_Hash_Data event. -void -_rpc__Signal_Hash_Data( - _IN_BUFFER input - ) -{ - // If TPM is power off, reject this signal - if(!s_isPowerOn) return; - - // Pass _TPM_Hash_Data signal to TPM - _TPM_Hash_Data(input.BufferSize, input.Buffer); - return; -} - -//*** _rpc__Signal_HashEnd() -// This function is called to simulate a _TPM_Hash_End event. -void -_rpc__Signal_HashEnd( - void - ) -{ - // If TPM is power off, reject this signal - if(!s_isPowerOn) return; - - // Pass _TPM_HashEnd signal to TPM - _TPM_Hash_End(); - return; -} - -//*** _rpc__Send_Command() -// This is the interface to the TPM code. -// Return Type: void -void -_rpc__Send_Command( - unsigned char locality, - _IN_BUFFER request, - _OUT_BUFFER *response - ) -{ - // If TPM is power off, reject any commands. - if(!s_isPowerOn) - { - response->BufferSize = 0; - return; - } - // Set the locality of the command so that it doesn't change during the command - _plat__LocalitySet(locality); - // Do implementation-specific command dispatch - _plat__RunCommand(request.BufferSize, request.Buffer, - &response->BufferSize, &response->Buffer); - return; -} - -//*** _rpc__Signal_CancelOn() -// This function is used to turn on the indication to cancel a command in process. -// An executing command is not interrupted. The command code may periodically check -// this indication to see if it should abort the current command processing and -// returned TPM_RC_CANCELLED. -void -_rpc__Signal_CancelOn( - void - ) -{ - // If TPM is power off, reject this signal - if(!s_isPowerOn) return; - - // Set the platform canceling flag. - _plat__SetCancel(); - - return; -} - -//*** _rpc__Signal_CancelOff() -// This function is used to turn off the indication to cancel a command in process. -void -_rpc__Signal_CancelOff( - void - ) -{ - // If TPM is power off, reject this signal - if(!s_isPowerOn) return; - - // Set the platform canceling flag. - _plat__ClearCancel(); - - return; -} - -//*** _rpc__Signal_NvOn() -// In a system where the NV memory used by the TPM is not within the TPM, the -// NV may not always be available. This function turns on the indicator that -// indicates that NV is available. -void -_rpc__Signal_NvOn( - void - ) -{ - // If TPM is power off, reject this signal - if(!s_isPowerOn) return; - - _plat__SetNvAvail(); - return; -} - -//*** _rpc__Signal_NvOff() -// This function is used to set the indication that NV memory is no -// longer available. -void -_rpc__Signal_NvOff( - void - ) -{ - // If TPM is power off, reject this signal - if(!s_isPowerOn) return; - - _plat__ClearNvAvail(); - return; -} - -void RsaKeyCacheControl(int state); - -//*** _rpc__RsaKeyCacheControl() -// This function is used to enable/disable the use of the RSA key cache during -// simulation. -void -_rpc__RsaKeyCacheControl( - int state - ) -{ -#if USE_RSA_KEY_CACHE - RsaKeyCacheControl(state); -#else - NOT_REFERENCED(state); -#endif -} diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Simulator/src/TPMCmds.c b/simulator/ms-tpm-20-ref/TPMCmd/Simulator/src/TPMCmds.c deleted file mode 100644 index 74ad047ee..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Simulator/src/TPMCmds.c +++ /dev/null @@ -1,311 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Description -// This file contains the entry point for the simulator. - -//** Includes, Defines, Data Definitions, and Function Prototypes -#include "TpmBuildSwitches.h" - -#include -#include -#include -#include -#include -#include "BaseTypes.h" - -#ifdef _MSC_VER -# pragma warning(push, 3) -# include -# include -# pragma warning(pop) -#elif defined(__unix__) -# define _strcmpi strcasecmp - typedef int SOCKET; -#else -# error "Unsupported platform." -#endif - -#ifndef TRUE -# define TRUE 1 -#endif -#ifndef FALSE -# define FALSE 0 -#endif - -#include "TpmTcpProtocol.h" -#include "Manufacture_fp.h" -#include "Platform_fp.h" -#include "Simulator_fp.h" - -#define PURPOSE \ -"TPM 2.0 Reference Simulator.\n" \ -"Copyright (c) Microsoft Corporation. All rights reserved." - -#define DEFAULT_TPM_PORT 2321 - -// Information about command line arguments (does not include program name) -static uint32_t s_ArgsMask = 0; // Bit mask of unmatched command line args -static int s_Argc = 0; -static const char **s_Argv = NULL; - - -//** Functions - -#if DEBUG -//*** Assert() -// This function implements a run-time assertion. -// Computation of its parameters must not result in any side effects, as these -// computations will be stripped from the release builds. -static void Assert (BOOL cond, const char* msg) -{ - if (cond) - return; - fputs(msg, stderr); - exit(2); -} -#else -#define Assert(cond, msg) -#endif - -//*** Usage() -// This function prints the proper calling sequence for the simulator. -static void -Usage( - const char *programName -) -{ - fprintf(stderr, "%s\n\n", PURPOSE); - fprintf(stderr, "Usage: %s [PortNum] [opts]\n\n" - "Starts the TPM server listening on TCP port PortNum (by default %d).\n\n" - "An option can be in the short form (one letter preceded with '-' or '/')\n" - "or in the full form (preceded with '--' or no option marker at all).\n" - "Possible options are:\n" - " -h (--help) or ? - print this message\n" - " -m (--manufacture) - forces NV state of the TPM simulator to be " - "(re)manufactured\n", - programName, DEFAULT_TPM_PORT); - exit(1); -} - -//*** CmdLineParser_Init() -// This function initializes command line option parser. -static BOOL -CmdLineParser_Init( - int argc, - char *argv[], - int maxOpts - ) -{ - if (argc == 1) - return FALSE; - - if (maxOpts && (argc - 1) > maxOpts) - { - fprintf(stderr, "No more than %d options can be specified\n\n", maxOpts); - Usage(argv[0]); - } - - s_Argc = argc - 1; - s_Argv = (const char**)(argv + 1); - s_ArgsMask = (1 << s_Argc) - 1; - return TRUE; -} - -//*** CmdLineParser_More() -// Returns true if there are unparsed options still. -static BOOL -CmdLineParser_More( - void -) -{ - return s_ArgsMask != 0; -} - -//*** CmdLineParser_IsOpt() -// This function determines if the given command line parameter represents a valid -// option. -static BOOL -CmdLineParser_IsOpt( - const char* opt, // Command line parameter to check - const char* optFull, // Expected full name - const char* optShort, // Expected short (single letter) name - BOOL dashed // The parameter is preceded by a single dash - ) -{ - return 0 == strcmp(opt, optFull) - || (optShort && opt[0] == optShort[0] && opt[1] == 0) - || (dashed && opt[0] == '-' && 0 == strcmp(opt + 1, optFull)); -} - -//*** CmdLineParser_IsOptPresent() -// This function determines if the given command line parameter represents a valid -// option. -static BOOL -CmdLineParser_IsOptPresent( - const char* optFull, - const char* optShort - ) -{ - Assert(s_Argv != NULL, - "InitCmdLineOptParser(argc, argv) has not been invoked\n"); - Assert(optFull && optFull[0], - "Full form of a command line option must be present.\n" - "If only a short (single letter) form is supported, it must be" - "specified as the full one.\n"); - Assert(!optShort || (optShort[0] && !optShort[1]), - "If a short form of an option is specified, it must consist " - "of a single letter only.\n"); - - if (!CmdLineParser_More()) - return FALSE; - - for (int i = 0, curArgBit = 1; i < s_Argc; ++i, curArgBit <<= 1) - { - const char* opt = s_Argv[i]; - if ( (s_ArgsMask & curArgBit) && opt - && ( 0 == strcmp(opt, optFull) - || ( (opt[0] == '/' || opt[0] == '-') - && CmdLineParser_IsOpt(opt + 1, optFull, optShort, opt[0] == '-')))) - { - s_ArgsMask ^= curArgBit; - return TRUE; - } - } - return FALSE; -} - -//*** CmdLineParser_IsOptPresent() -// This function notifies the parser that no more options are needed. -static void -CmdLineParser_Done( - const char *programName -) -{ - char delim = ':'; - - if (!CmdLineParser_More()) - return; - - fprintf(stderr, "Command line contains unknown option%s", s_ArgsMask & (s_ArgsMask - 1) ? "s" : ""); - for (int i = 0, curArgBit = 1; i < s_Argc; ++i, curArgBit <<= 1) - { - if (s_ArgsMask & curArgBit) - { - fprintf(stderr, "%c %s", delim, s_Argv[i]); - delim = ','; - } - } - fprintf(stderr, "\n\n"); - Usage(programName); -} - -//*** main() -// This is the main entry point for the simulator. -// It registers the interface and starts listening for clients -int -main( - int argc, - char *argv[] - ) -{ - BOOL manufacture = FALSE; - int PortNum = DEFAULT_TPM_PORT; - - // Parse command line options - - if (CmdLineParser_Init(argc, argv, 2)) - { - if ( CmdLineParser_IsOptPresent("?", "?") - || CmdLineParser_IsOptPresent("help", "h")) - { - Usage(argv[0]); - } - if (CmdLineParser_IsOptPresent("manufacture", "m")) - { - manufacture = TRUE; - } - if (CmdLineParser_More()) - { - for (int i = 0; i < s_Argc; ++i) - { - char *nptr = NULL; - int portNum = (int)strtol(s_Argv[i], &nptr, 0); - if (s_Argv[i] != nptr) - { - // A numeric option is found - if(!*nptr && portNum > 0 && portNum < 65535) - { - PortNum = portNum; - s_ArgsMask ^= 1 << i; - break; - } - fprintf(stderr, "Invalid numeric option %s\n\n", s_Argv[i]); - Usage(argv[0]); - } - } - } - CmdLineParser_Done(argv[0]); - } - - // Enable NV memory - _plat__NVEnable(NULL); - - if (manufacture || _plat__NVNeedsManufacture()) - { - printf("Manufacturing NV state...\n"); - if(TPM_Manufacture(1) != 0) - { - exit(1); - } - // Coverage test - repeated manufacturing attempt - if(TPM_Manufacture(0) != 1) - { - exit(2); - } - // Coverage test - re-manufacturing - TPM_TearDown(); - if(TPM_Manufacture(1) != 0) - { - exit(3); - } - } - - // Disable NV memory - _plat__NVDisable(); - - StartTcpServer(PortNum); - return EXIT_SUCCESS; -} - diff --git a/simulator/ms-tpm-20-ref/TPMCmd/Simulator/src/TcpServer.c b/simulator/ms-tpm-20-ref/TPMCmd/Simulator/src/TcpServer.c deleted file mode 100644 index d620d4081..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/Simulator/src/TcpServer.c +++ /dev/null @@ -1,649 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -//** Description -// -// This file contains the socket interface to a TPM simulator. -// -//** Includes, Locals, Defines and Function Prototypes -#include "TpmBuildSwitches.h" -#include "BaseTypes.h" - -#include - -#ifdef _MSC_VER -# pragma warning(push, 3) -# include -# include -# pragma warning(pop) -typedef int socklen_t; -#elif defined(__unix__) -# include -# include -# include -# include -# include -# include -# define ZeroMemory(ptr, sz) (memset((ptr), 0, (sz))) -# define closesocket(x) close(x) -# define INVALID_SOCKET (-1) -# define SOCKET_ERROR (-1) -# define WSAGetLastError() (errno) -# define INT_PTR intptr_t - typedef int SOCKET; -#endif // __unix__ - -#ifndef TRUE -# define TRUE 1 -#endif -#ifndef FALSE -# define FALSE 0 -#endif - - -#include -#include -#include - -#include "TpmTcpProtocol.h" -#include "Manufacture_fp.h" - -#include "Simulator_fp.h" - -// To access key cache control in TPM -void RsaKeyCacheControl(int state); - -#ifndef __IGNORE_STATE__ - -static uint32_t ServerVersion = 1; - -#define MAX_BUFFER 1048576 -char InputBuffer[MAX_BUFFER]; //The input data buffer for the simulator. -char OutputBuffer[MAX_BUFFER]; //The output data buffer for the simulator. - -struct -{ - uint32_t largestCommandSize; - uint32_t largestCommand; - uint32_t largestResponseSize; - uint32_t largestResponse; -} CommandResponseSizes = {0}; - -#endif // __IGNORE_STATE___ - -//** Functions - -//*** CreateSocket() -// This function creates a socket listening on 'PortNumber'. -static int -CreateSocket( - int PortNumber, - SOCKET *listenSocket - ) -{ - struct sockaddr_in MyAddress; - int res; -// - // Initialize Winsock -#ifdef _MSC_VER - WSADATA wsaData; - res = WSAStartup(MAKEWORD(2, 2), &wsaData); - if(res != 0) - { - printf("WSAStartup failed with error: %d\n", res); - return -1; - } -#endif - // create listening socket - *listenSocket = socket(PF_INET, SOCK_STREAM, 0); - if(INVALID_SOCKET == *listenSocket) - { - printf("Cannot create server listen socket. Error is 0x%x\n", - WSAGetLastError()); - return -1; - } - // bind the listening socket to the specified port - ZeroMemory(&MyAddress, sizeof(MyAddress)); - MyAddress.sin_port = htons((short)PortNumber); - MyAddress.sin_family = AF_INET; - - res = bind(*listenSocket, (struct sockaddr*) &MyAddress, sizeof(MyAddress)); - if(res == SOCKET_ERROR) - { - printf("Bind error. Error is 0x%x\n", WSAGetLastError()); - return -1; - } - // listen/wait for server connections - res = listen(*listenSocket, 3); - if(res == SOCKET_ERROR) - { - printf("Listen error. Error is 0x%x\n", WSAGetLastError()); - return -1; - } - return 0; -} - -//*** PlatformServer() -// This function processes incoming platform requests. -BOOL -PlatformServer( - SOCKET s - ) -{ - BOOL OK = TRUE; - uint32_t Command; -// - for(;;) - { - OK = ReadBytes(s, (char*)&Command, 4); - // client disconnected (or other error). We stop processing this client - // and return to our caller who can stop the server or listen for another - // connection. - if(!OK) - return TRUE; - Command = ntohl(Command); - switch(Command) - { - case TPM_SIGNAL_POWER_ON: - _rpc__Signal_PowerOn(FALSE); - break; - case TPM_SIGNAL_POWER_OFF: - _rpc__Signal_PowerOff(); - break; - case TPM_SIGNAL_RESET: - _rpc__Signal_PowerOn(TRUE); - break; - case TPM_SIGNAL_RESTART: - _rpc__Signal_Restart(); - break; - case TPM_SIGNAL_PHYS_PRES_ON: - _rpc__Signal_PhysicalPresenceOn(); - break; - case TPM_SIGNAL_PHYS_PRES_OFF: - _rpc__Signal_PhysicalPresenceOff(); - break; - case TPM_SIGNAL_CANCEL_ON: - _rpc__Signal_CancelOn(); - break; - case TPM_SIGNAL_CANCEL_OFF: - _rpc__Signal_CancelOff(); - break; - case TPM_SIGNAL_NV_ON: - _rpc__Signal_NvOn(); - break; - case TPM_SIGNAL_NV_OFF: - _rpc__Signal_NvOff(); - break; - case TPM_SIGNAL_KEY_CACHE_ON: - _rpc__RsaKeyCacheControl(TRUE); - break; - case TPM_SIGNAL_KEY_CACHE_OFF: - _rpc__RsaKeyCacheControl(FALSE); - break; - case TPM_SESSION_END: - // Client signaled end-of-session - TpmEndSimulation(); - return TRUE; - case TPM_STOP: - // Client requested the simulator to exit - return FALSE; - case TPM_TEST_FAILURE_MODE: - _rpc__ForceFailureMode(); - break; - case TPM_GET_COMMAND_RESPONSE_SIZES: - OK = WriteVarBytes(s, (char *)&CommandResponseSizes, - sizeof(CommandResponseSizes)); - memset(&CommandResponseSizes, 0, sizeof(CommandResponseSizes)); - if(!OK) - return TRUE; - break; - default: - printf("Unrecognized platform interface command %d\n", - (int)Command); - WriteUINT32(s, 1); - return TRUE; - } - WriteUINT32(s, 0); - } -} - -//*** PlatformSvcRoutine() -// This function is called to set up the socket interfaces to listen for -// commands. -DWORD WINAPI -PlatformSvcRoutine( - LPVOID port - ) -{ - int PortNumber = (int)(INT_PTR)port; - SOCKET listenSocket, serverSocket; - struct sockaddr_in HerAddress; - int res; - socklen_t length; - BOOL continueServing; -// - res = CreateSocket(PortNumber, &listenSocket); - if(res != 0) - { - printf("Create platform service socket fail\n"); - return res; - } - // Loop accepting connections one-by-one until we are killed or asked to stop - // Note the platform service is single-threaded so we don't listen for a new - // connection until the prior connection drops. - do - { - printf("Platform server listening on port %d\n", PortNumber); - - // blocking accept - length = sizeof(HerAddress); - serverSocket = accept(listenSocket, - (struct sockaddr*) &HerAddress, - &length); - if(serverSocket == SOCKET_ERROR) - { - printf("Accept error. Error is 0x%x\n", WSAGetLastError()); - return (DWORD)-1; - } - printf("Client accepted\n"); - - // normal behavior on client disconnection is to wait for a new client - // to connect - continueServing = PlatformServer(serverSocket); - closesocket(serverSocket); - } while(continueServing); - - return 0; -} - -//*** PlatformSignalService() -// This function starts a new thread waiting for platform signals. -// Platform signals are processed one at a time in the order in which they are -// received. -#if defined(_MSC_VER) -int -PlatformSignalService( - int PortNumber - ) -{ - HANDLE hPlatformSvc; - int ThreadId; - int port = PortNumber; -// - // Create service thread for platform signals - hPlatformSvc = CreateThread(NULL, 0, - (LPTHREAD_START_ROUTINE)PlatformSvcRoutine, - (LPVOID)(INT_PTR)port, 0, (LPDWORD)&ThreadId); - if(hPlatformSvc == NULL) - { - printf("Thread Creation failed\n"); - return -1; - } - return 0; -} -#elif defined(__unix__) -#include -int -PlatformSignalService( - int PortNumber - ) -{ - pthread_t thread_id; - int ret; - int port = PortNumber; - - ret = pthread_create(&thread_id, NULL, (void*)PlatformSvcRoutine, (LPVOID)(INT_PTR)port); - if (ret == -1) - { - printf("pthread_create failed: %s", strerror(ret)); - } - - return ret; -} -#else -#error "Unsupported platform." -#endif // _MSC_VER -//*** RegularCommandService() -// This function services regular commands. -int -RegularCommandService( - int PortNumber - ) -{ - SOCKET listenSocket; - SOCKET serverSocket; - struct sockaddr_in HerAddress; - int res; - socklen_t length; - BOOL continueServing; -// - res = CreateSocket(PortNumber, &listenSocket); - if(res != 0) - { - printf("Create platform service socket fail\n"); - return res; - } - // Loop accepting connections one-by-one until we are killed or asked to stop - // Note the TPM command service is single-threaded so we don't listen for - // a new connection until the prior connection drops. - do - { - printf("TPM command server listening on port %d\n", PortNumber); - - // blocking accept - length = sizeof(HerAddress); - serverSocket = accept(listenSocket, - (struct sockaddr*) &HerAddress, - &length); - if(serverSocket == SOCKET_ERROR) - { - printf("Accept error. Error is 0x%x\n", WSAGetLastError()); - return -1; - } - printf("Client accepted\n"); - - // normal behavior on client disconnection is to wait for a new client - // to connect - continueServing = TpmServer(serverSocket); - closesocket(serverSocket); - } while(continueServing); - return 0; -} - -//*** StartTcpServer() -// This is the main entry-point to the TCP server. The server listens on port -// specified. -// -// Note that there is no way to specify the network interface in this implementation. -int -StartTcpServer( - int PortNumber - ) -{ - int res; -// - // Start Platform Signal Processing Service - res = PlatformSignalService(PortNumber + 1); - if(res != 0) - { - printf("PlatformSignalService failed\n"); - return res; - } - // Start Regular/DRTM TPM command service - res = RegularCommandService(PortNumber); - if(res != 0) - { - printf("RegularCommandService failed\n"); - return res; - } - return 0; -} - -//*** ReadBytes() -// This function reads the indicated number of bytes ('NumBytes') into buffer -// from the indicated socket. -BOOL -ReadBytes( - SOCKET s, - char *buffer, - int NumBytes - ) -{ - int res; - int numGot = 0; -// - while(numGot < NumBytes) - { - res = recv(s, buffer + numGot, NumBytes - numGot, 0); - if(res == -1) - { - printf("Receive error. Error is 0x%x\n", WSAGetLastError()); - return FALSE; - } - if(res == 0) - { - return FALSE; - } - numGot += res; - } - return TRUE; -} - -//*** WriteBytes() -// This function will send the indicated number of bytes ('NumBytes') to the -// indicated socket -BOOL -WriteBytes( - SOCKET s, - char *buffer, - int NumBytes - ) -{ - int res; - int numSent = 0; -// - while(numSent < NumBytes) - { - res = send(s, buffer + numSent, NumBytes - numSent, 0); - if(res == -1) - { - if(WSAGetLastError() == 0x2745) - { - printf("Client disconnected\n"); - } - else - { - printf("Send error. Error is 0x%x\n", WSAGetLastError()); - } - return FALSE; - } - numSent += res; - } - return TRUE; -} - -//*** WriteUINT32() -// Send 4 bytes containing hton(1) -BOOL -WriteUINT32( - SOCKET s, - uint32_t val - ) -{ - UINT32 netVal = htonl(val); -// - return WriteBytes(s, (char*)&netVal, 4); -} - -//*** ReadVarBytes() -// Get a UINT32-length-prepended binary array. Note that the 4-byte length is -// in network byte order (big-endian). -BOOL -ReadVarBytes( - SOCKET s, - char *buffer, - uint32_t *BytesReceived, - int MaxLen - ) -{ - int length; - BOOL res; -// - res = ReadBytes(s, (char*)&length, 4); - if(!res) return res; - length = ntohl(length); - *BytesReceived = length; - if(length > MaxLen) - { - printf("Buffer too big. Client says %d\n", length); - return FALSE; - } - if(length == 0) return TRUE; - res = ReadBytes(s, buffer, length); - if(!res) return res; - return TRUE; -} - -//*** WriteVarBytes() -// Send a UINT32-length-prepended binary array. Note that the 4-byte length is -// in network byte order (big-endian). -BOOL -WriteVarBytes( - SOCKET s, - char *buffer, - int BytesToSend - ) -{ - uint32_t netLength = htonl(BytesToSend); - BOOL res; -// - res = WriteBytes(s, (char*)&netLength, 4); - if(!res) - return res; - res = WriteBytes(s, buffer, BytesToSend); - if(!res) - return res; - return TRUE; -} - -//*** TpmServer() -// Processing incoming TPM command requests using the protocol / interface -// defined above. -BOOL -TpmServer( - SOCKET s - ) -{ - uint32_t length; - uint32_t Command; - BYTE locality; - BOOL OK; - int result; - int clientVersion; - _IN_BUFFER InBuffer; - _OUT_BUFFER OutBuffer; -// - for(;;) - { - OK = ReadBytes(s, (char*)&Command, 4); - // client disconnected (or other error). We stop processing this client - // and return to our caller who can stop the server or listen for another - // connection. - if(!OK) - return TRUE; - Command = ntohl(Command); - switch(Command) - { - case TPM_SIGNAL_HASH_START: - _rpc__Signal_Hash_Start(); - break; - case TPM_SIGNAL_HASH_END: - _rpc__Signal_HashEnd(); - break; - case TPM_SIGNAL_HASH_DATA: - OK = ReadVarBytes(s, InputBuffer, &length, MAX_BUFFER); - if(!OK) return TRUE; - InBuffer.Buffer = (BYTE*)InputBuffer; - InBuffer.BufferSize = length; - _rpc__Signal_Hash_Data(InBuffer); - break; - case TPM_SEND_COMMAND: - OK = ReadBytes(s, (char*)&locality, 1); - if(!OK) - return TRUE; - OK = ReadVarBytes(s, InputBuffer, &length, MAX_BUFFER); - if(!OK) - return TRUE; - InBuffer.Buffer = (BYTE*)InputBuffer; - InBuffer.BufferSize = length; - OutBuffer.BufferSize = MAX_BUFFER; - OutBuffer.Buffer = (_OUTPUT_BUFFER)OutputBuffer; - // record the number of bytes in the command if it is the largest - // we have seen so far. - if(InBuffer.BufferSize > CommandResponseSizes.largestCommandSize) - { - CommandResponseSizes.largestCommandSize = InBuffer.BufferSize; - memcpy(&CommandResponseSizes.largestCommand, - &InputBuffer[6], sizeof(UINT32)); - } - _rpc__Send_Command(locality, InBuffer, &OutBuffer); - // record the number of bytes in the response if it is the largest - // we have seen so far. - if(OutBuffer.BufferSize > CommandResponseSizes.largestResponseSize) - { - CommandResponseSizes.largestResponseSize - = OutBuffer.BufferSize; - memcpy(&CommandResponseSizes.largestResponse, - &OutputBuffer[6], sizeof(UINT32)); - } - OK = WriteVarBytes(s, - (char*)OutBuffer.Buffer, - OutBuffer.BufferSize); - if(!OK) - return TRUE; - break; - case TPM_REMOTE_HANDSHAKE: - OK = ReadBytes(s, (char*)&clientVersion, 4); - if(!OK) - return TRUE; - if(clientVersion == 0) - { - printf("Unsupported client version (0).\n"); - return TRUE; - } - OK &= WriteUINT32(s, ServerVersion); - OK &= WriteUINT32(s, tpmInRawMode - | tpmPlatformAvailable | tpmSupportsPP); - break; - case TPM_SET_ALTERNATIVE_RESULT: - OK = ReadBytes(s, (char*)&result, 4); - if(!OK) - return TRUE; - // Alternative result is not applicable to the simulator. - break; - case TPM_SESSION_END: - // Client signaled end-of-session - return TRUE; - case TPM_STOP: - // Client requested the simulator to exit - return FALSE; - default: - printf("Unrecognized TPM interface command %d\n", (int)Command); - return TRUE; - } - OK = WriteUINT32(s, 0); - if(!OK) - return TRUE; - } -} \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/bootstrap b/simulator/ms-tpm-20-ref/TPMCmd/bootstrap deleted file mode 100755 index a368cd7c5..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/bootstrap +++ /dev/null @@ -1,66 +0,0 @@ -#!/usr/bin/env sh -# The copyright in this software is being made available under the BSD License, -# included below. This software may be subject to other third party and -# contributor rights, including patent rights, and no such rights are granted -# under this license. -# -# Copyright (c) Intel Corporation -# -# All rights reserved. -# -# BSD License -# -# Redistribution and use in source and binary forms, with or without modification, -# are permitted provided that the following conditions are met: -# -# Redistributions of source code must retain the above copyright notice, this list -# of conditions and the following disclaimer. -# -# Redistributions in binary form must reproduce the above copyright notice, this -# list of conditions and the following disclaimer in the documentation and/or -# other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -AUTORECONF=${AUTORECONF:-autoreconf} - -# generate list of source files for use in Makefile.am -# if you add new source files, you must run ./bootstrap again -src_listvar () { - basedir=$1 - suffix=$2 - var=$3 - - find "${basedir}" -name "${suffix}" | LC_ALL=C sort | tr '\n' ' ' | (printf "${var} = " && cat) - echo "" -} - -echo "Generating file lists: src.mk" -( - src_listvar "Platform" "*.c" "PLATFORM_C" - src_listvar "Platform" "*.h" "PLATFORM_H" - src_listvar "Simulator" "*.c" "SIMULATOR_C" - src_listvar "Simulator" "*.h" "SIMULATOR_H" - src_listvar "tpm" "*.c" "TPM_C" - src_listvar "tpm" "*.h" "TPM_H" -) > src.mk - -echo "Setting up build" -${AUTORECONF} --install --sym - -# A freshly checked out source tree will not build. VendorString.h must have -# these symbols defined to build. -echo "Setting default vendor strings" -sed -i 's&^\/\/\(#define[[:space:]]\+FIRMWARE_V1.*\)&\1&; - s&^\/\/\(#define[[:space:]]\+MANUFACTURER.*\)&\1&; - s&^\/\/\(#define[[:space:]]\+VENDOR_STRING_1.*\)&\1&' \ - tpm/include/VendorString.h diff --git a/simulator/ms-tpm-20-ref/TPMCmd/simulator.sln b/simulator/ms-tpm-20-ref/TPMCmd/simulator.sln deleted file mode 100644 index 89ea5c196..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/simulator.sln +++ /dev/null @@ -1,128 +0,0 @@ - -Microsoft Visual Studio Solution File, Format Version 12.00 -# Visual Studio 14 -VisualStudioVersion = 14.0.25420.1 -MinimumVisualStudioVersion = 10.0.40219.1 -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Simulator", "simulator\simulator.vcxproj", "{AAB9FA21-8671-4792-B000-B40A526058AD}" - ProjectSection(ProjectDependencies) = postProject - {A9249F05-0DF5-4D06-9873-FBBE61B6768B} = {A9249F05-0DF5-4D06-9873-FBBE61B6768B} - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B} = {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B} - EndProjectSection -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Platform", "Platform\platform.vcxproj", "{A9249F05-0DF5-4D06-9873-FBBE61B6768B}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Tpm", "tpm\TPM.vcxproj", "{B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}" - ProjectSection(ProjectDependencies) = postProject - {A9249F05-0DF5-4D06-9873-FBBE61B6768B} = {A9249F05-0DF5-4D06-9873-FBBE61B6768B} - {73973223-5EE8-41CA-8E88-1D60E89A237B} = {73973223-5EE8-41CA-8E88-1D60E89A237B} - EndProjectSection -EndProject -Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Crypt", "Crypt", "{26AD7978-27E2-46E7-9F8C-36CDB1B5AB01}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "wolfssl", "tpm\src\crypt\wolf\wolfssl.vcxproj", "{73973223-5EE8-41CA-8E88-1D60E89A237B}" -EndProject -Global - GlobalSection(SolutionConfigurationPlatforms) = preSolution - Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - Static|Win32 = Static|Win32 - Static|x64 = Static|x64 - WolfDebug|Win32 = WolfDebug|Win32 - WolfDebug|x64 = WolfDebug|x64 - WolfRelease|Win32 = WolfRelease|Win32 - WolfRelease|x64 = WolfRelease|x64 - EndGlobalSection - GlobalSection(ProjectConfigurationPlatforms) = postSolution - {AAB9FA21-8671-4792-B000-B40A526058AD}.Debug|Win32.ActiveCfg = Debug|Win32 - {AAB9FA21-8671-4792-B000-B40A526058AD}.Debug|Win32.Build.0 = Debug|Win32 - {AAB9FA21-8671-4792-B000-B40A526058AD}.Debug|x64.ActiveCfg = Debug|x64 - {AAB9FA21-8671-4792-B000-B40A526058AD}.Debug|x64.Build.0 = Debug|x64 - {AAB9FA21-8671-4792-B000-B40A526058AD}.Release|Win32.ActiveCfg = Release|Win32 - {AAB9FA21-8671-4792-B000-B40A526058AD}.Release|Win32.Build.0 = Release|Win32 - {AAB9FA21-8671-4792-B000-B40A526058AD}.Release|x64.ActiveCfg = Release|x64 - {AAB9FA21-8671-4792-B000-B40A526058AD}.Release|x64.Build.0 = Release|x64 - {AAB9FA21-8671-4792-B000-B40A526058AD}.Static|Win32.ActiveCfg = Static|Win32 - {AAB9FA21-8671-4792-B000-B40A526058AD}.Static|Win32.Build.0 = Static|Win32 - {AAB9FA21-8671-4792-B000-B40A526058AD}.Static|x64.ActiveCfg = Static|x64 - {AAB9FA21-8671-4792-B000-B40A526058AD}.Static|x64.Build.0 = Static|x64 - {AAB9FA21-8671-4792-B000-B40A526058AD}.WolfDebug|Win32.ActiveCfg = WolfDebug|Win32 - {AAB9FA21-8671-4792-B000-B40A526058AD}.WolfDebug|Win32.Build.0 = WolfDebug|Win32 - {AAB9FA21-8671-4792-B000-B40A526058AD}.WolfDebug|x64.ActiveCfg = WolfDebug|x64 - {AAB9FA21-8671-4792-B000-B40A526058AD}.WolfDebug|x64.Build.0 = WolfDebug|x64 - {AAB9FA21-8671-4792-B000-B40A526058AD}.WolfRelease|Win32.ActiveCfg = WolfRelease|Win32 - {AAB9FA21-8671-4792-B000-B40A526058AD}.WolfRelease|Win32.Build.0 = WolfRelease|Win32 - {AAB9FA21-8671-4792-B000-B40A526058AD}.WolfRelease|x64.ActiveCfg = WolfRelease|x64 - {AAB9FA21-8671-4792-B000-B40A526058AD}.WolfRelease|x64.Build.0 = WolfRelease|x64 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.Debug|Win32.ActiveCfg = Debug|Win32 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.Debug|Win32.Build.0 = Debug|Win32 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.Debug|x64.ActiveCfg = Debug|x64 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.Debug|x64.Build.0 = Debug|x64 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.Release|Win32.ActiveCfg = Release|Win32 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.Release|Win32.Build.0 = Release|Win32 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.Release|x64.ActiveCfg = Release|x64 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.Release|x64.Build.0 = Release|x64 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.Static|Win32.ActiveCfg = Static|Win32 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.Static|Win32.Build.0 = Static|Win32 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.Static|x64.ActiveCfg = Static|x64 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.Static|x64.Build.0 = Static|x64 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.WolfDebug|Win32.ActiveCfg = WolfDebug|Win32 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.WolfDebug|Win32.Build.0 = WolfDebug|Win32 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.WolfDebug|x64.ActiveCfg = WolfDebug|x64 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.WolfDebug|x64.Build.0 = WolfDebug|x64 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.WolfDebug|x64.Deploy.0 = WolfDebug|x64 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.WolfRelease|Win32.ActiveCfg = WolfRelease|Win32 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.WolfRelease|Win32.Build.0 = WolfRelease|Win32 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.WolfRelease|x64.ActiveCfg = WolfRelease|x64 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.WolfRelease|x64.Build.0 = WolfRelease|x64 - {A9249F05-0DF5-4D06-9873-FBBE61B6768B}.WolfRelease|x64.Deploy.0 = WolfRelease|x64 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.Debug|Win32.ActiveCfg = Debug|Win32 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.Debug|Win32.Build.0 = Debug|Win32 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.Debug|x64.ActiveCfg = Debug|x64 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.Debug|x64.Build.0 = Debug|x64 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.Release|Win32.ActiveCfg = Release|Win32 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.Release|Win32.Build.0 = Release|Win32 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.Release|x64.ActiveCfg = Release|x64 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.Release|x64.Build.0 = Release|x64 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.Static|Win32.ActiveCfg = Static|Win32 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.Static|Win32.Build.0 = Static|Win32 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.Static|x64.ActiveCfg = Static|x64 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.Static|x64.Build.0 = Static|x64 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.WolfDebug|Win32.ActiveCfg = WolfDebug|Win32 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.WolfDebug|Win32.Build.0 = WolfDebug|Win32 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.WolfDebug|x64.ActiveCfg = WolfDebug|x64 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.WolfDebug|x64.Build.0 = WolfDebug|x64 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.WolfRelease|Win32.ActiveCfg = WolfRelease|Win32 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.WolfRelease|Win32.Build.0 = WolfRelease|Win32 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.WolfRelease|x64.ActiveCfg = WolfRelease|x64 - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B}.WolfRelease|x64.Build.0 = WolfRelease|x64 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.Debug|Win32.ActiveCfg = WolfDebug|Win32 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.Debug|x64.ActiveCfg = WolfDebug|x64 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.Release|Win32.ActiveCfg = WolfRelease|Win32 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.Release|x64.ActiveCfg = WolfRelease|x64 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.Static|Win32.ActiveCfg = WolfRelease|Win32 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.Static|Win32.Deploy.0 = WolfRelease|Win32 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.Static|x64.ActiveCfg = WolfRelease|x64 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.Static|x64.Deploy.0 = WolfRelease|x64 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.WolfDebug|Win32.ActiveCfg = WolfDebug|Win32 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.WolfDebug|Win32.Build.0 = WolfDebug|Win32 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.WolfDebug|x64.ActiveCfg = WolfDebug|x64 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.WolfDebug|x64.Build.0 = WolfDebug|x64 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.WolfRelease|Win32.ActiveCfg = WolfRelease|Win32 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.WolfRelease|Win32.Build.0 = WolfRelease|Win32 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.WolfRelease|Win32.Deploy.0 = WolfRelease|Win32 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.WolfRelease|x64.ActiveCfg = WolfRelease|x64 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.WolfRelease|x64.Build.0 = WolfRelease|x64 - {73973223-5EE8-41CA-8E88-1D60E89A237B}.WolfRelease|x64.Deploy.0 = WolfRelease|x64 - EndGlobalSection - GlobalSection(SolutionProperties) = preSolution - HideSolutionNode = FALSE - EndGlobalSection - GlobalSection(NestedProjects) = preSolution - {73973223-5EE8-41CA-8E88-1D60E89A237B} = {26AD7978-27E2-46E7-9F8C-36CDB1B5AB01} - EndGlobalSection - GlobalSection(ExtensibilityGlobals) = postSolution - SolutionGuid = {C15EF5ED-F2C1-4785-A9C2-A2D213A367F7} - EndGlobalSection -EndGlobal diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/Tpm.vcxproj b/simulator/ms-tpm-20-ref/TPMCmd/tpm/Tpm.vcxproj deleted file mode 100644 index d586036a4..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/Tpm.vcxproj +++ /dev/null @@ -1,1042 +0,0 @@ - - - - - Debug - Win32 - - - Debug - x64 - - - Release - Win32 - - - Release - x64 - - - Static - Win32 - - - Static - x64 - - - WolfDebug - Win32 - - - WolfDebug - x64 - - - WolfRelease - Win32 - - - WolfRelease - x64 - - - - Tpm - {B7456491-A2ED-4B1C-B59E-41C7B32B7E3B} - TPMCmd - Win32Proj - 8.1 - - - - DynamicLibrary - Unicode - false - v140 - - - DynamicLibrary - Unicode - false - v140 - - - DynamicLibrary - Unicode - v140 - - - DynamicLibrary - Unicode - v140 - - - StaticLibrary - Unicode - v140 - - - DynamicLibrary - Unicode - false - v140 - - - DynamicLibrary - Unicode - false - v140 - - - DynamicLibrary - Unicode - v140 - - - DynamicLibrary - Unicode - v140 - - - StaticLibrary - Unicode - v140 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .\Debug;$(ReferencePath) - .\Debug;$(ReferencePath) - .\Debug;$(ReferencePath) - $(SolutionDir)\$(Configuration)\ - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - true - true - true - .\Debug;$(ReferencePath) - .\Debug;$(ReferencePath) - .\Debug;$(ReferencePath) - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - true - true - true - .\Debug;$(ReferencePath) - .\Debug;$(ReferencePath) - $(SolutionDir)\$(Configuration)\ - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - false - false - .\Debug;$(ReferencePath) - .\Debug;$(ReferencePath) - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - $(SolutionDir)\bin\$(ProjectName)\$(PlatformTarget)\$(Configuration)\ - false - false - AllRules.ruleset - AllRules.ruleset - AllRules.ruleset - - - - - - - AllRules.ruleset - AllRules.ruleset - AllRules.ruleset - - - - - - - AllRules.ruleset - AllRules.ruleset - - - - - AllRules.ruleset - AllRules.ruleset - - - - - .dll - .dll - .lib - BuildLink - - - false - - - false - - - - $(ProjectDir)include\;$(ProjectDir)include\prototypes\;$(SolutionDir)Platform\include\;$(SolutionDir)Platform\include\prototypes\;$(SolutionDir)LtcInclude\;$(SolutionDIr)OsslInclude\;$(SolutionDir)MsBnInclude\ - - - - - - Disabled - $(ProjectDir)include\;$(ProjectDir)include\prototypes\;$(SolutionDir)Platform\include\;$(SolutionDir)Platform\include\prototypes\;$(SolutionDir)LtcInclude\;$(SolutionDIr)OsslInclude\;$(SolutionDir)MsBnInclude\ - HASH_LIB=Ossl;SYM_LIB=Ossl;MATH_LIB=Ossl;%(PreprocessorDefinitions); - false - MultiThreadedDebugDLL - NotUsing - $(IntDir)Server.pdb - EnableAllWarnings - Cdecl - CompileAsC - Default - 4668; 4710;4711; 4820 - true - Default - EnableFastChecks - true - - - true - true - - - platform.lib;libeay32.lib;%(AdditionalDependencies) - $(SolutionDir)\lib;$(OutDir);%(AdditionalLibraryDirectories) - - - true - NotSet - MachineX86 - $(OutDir)$(TargetName)$(TargetExt) - false - false - $(OutDir)Tpm.map - - - $(OutDir)$(TargetName)$(TargetExt) - - - $(ProjectDir)\lib;$(OutDir); - - - $(ProjectDir)\tpm\TPM.def - CryptoEngine.dll;platform.lib - - - true - - - - - Disabled - $(ProjectDir)include\wolf;$(SolutionDir)..\external\wolfssl;$(SolutionDir)\wolfcrypt\include;%(AdditionalIncludeDirectories) - LIBRARY_COMPATIBILITY_CHECK;HASH_LIB=Wolf;SYM_LIB=Wolf;MATH_LIB=Wolf;WOLFSSL_USER_SETTINGS;%(PreprocessorDefinitions) - false - MultiThreadedDebugDLL - NotUsing - $(IntDir)Server.pdb - EnableAllWarnings - Cdecl - CompileAsC - Default - 4255;4668; 4710;4711; 4820 - true - Default - EnableFastChecks - true - - - true - true - - - wolfssl.lib;platform.lib;%(AdditionalDependencies) - $(SolutionDir)\$(Configuration);$(OutDir);%(AdditionalLibraryDirectories) - - - true - NotSet - MachineX86 - $(OutDir)$(TargetName)$(TargetExt) - false - false - $(OutDir)Tpm.map - - - $(OutDir)$(TargetName)$(TargetExt) - - - $(ProjectDir)\lib;$(OutDir); - - - $(ProjectDir)\tpm\TPM.def - CryptoEngine.dll;platform.lib - - - true - - - - - Disabled - $(ProjectDir)include\;$(ProjectDir)include\prototypes\;$(SolutionDir)Platform\include\;$(SolutionDir)Platform\include\prototypes\;$(SolutionDir)LtcInclude\;$(SolutionDIr)OsslInclude\;$(SolutionDir)MsBnInclude\ - HASH_LIB=Ossl;SYM_LIB=Ossl;MATH_LIB=Ossl;CRYPTO_ALIGN_4;_DEBUG;%(PreprocessorDefinitions) - false - EnableFastChecks - MultiThreadedDebugDLL - NotUsing - $(IntDir)Server.pdb - EnableAllWarnings - EditAndContinue - Cdecl - CompileAsC - Default - 4668; 4710;4711; 4820 - false - true - - - true - true - - - cryptoengine.lib;platform.lib;%(AdditionalDependencies) - $(ProjectDir)\lib;$(OutDir);%(AdditionalLibraryDirectories) - - - true - Console - MachineX86 - $(OutDir)$(TargetName)$(TargetExt) - - - $(OutDir)$(TargetName)$(TargetExt) - - - - - - - - - - - - - - - X64 - - - Disabled - $(ProjectDir)include\;$(ProjectDir)include\prototypes\;$(SolutionDir)Platform\include\;$(SolutionDir)Platform\include\prototypes\;$(SolutionDir)LtcInclude\;$(SolutionDIr)OsslInclude\;$(SolutionDir)MsBnInclude\ - HASH_LIB=Ossl;SYM_LIB=Ossl;MATH_LIB=Ossl;CRYPTO_ALIGN_16;_DEBUG;%(PreprocessorDefinitions) - true - EnableFastChecks - MultiThreadedDebugDLL - - - EnableAllWarnings - ProgramDatabase - 4668; 4710;4711; 4820 - true - - - platform.lib;libeay32.lib;%(AdditionalDependencies) - true - Console - MachineX64 - $(SolutionDir)\lib\x64;$(OutDir);%(AdditionalLibraryDirectories) - - - - - - - X64 - - - Disabled - $(ProjectDir)include\wolf;$(SolutionDir)..\external\wolfssl;$(SolutionDir)\wolfcrypt\include;%(AdditionalIncludeDirectories) - LIBRARY_COMPATIBILITY_CHECK;HASH_LIB=Wolf;SYM_LIB=Wolf;MATH_LIB=Wolf;WOLFSSL_USER_SETTINGS;_DEBUG;%(PreprocessorDefinitions) - true - EnableFastChecks - MultiThreadedDebugDLL - - - EnableAllWarnings - ProgramDatabase - 4255;4668; 4710;4711; 4820 - true - - - wolfssl.lib;platform.lib;%(AdditionalDependencies) - true - Console - MachineX64 - $(OutDir);%(AdditionalLibraryDirectories) - - - - - - - X64 - - - Disabled - $(ProjectDir)include\;$(ProjectDir)include\prototypes\;$(SolutionDir)Platform\include\;$(SolutionDir)Platform\include\prototypes\;$(SolutionDir)LtcInclude\;$(SolutionDIr)OsslInclude\;$(SolutionDir)MsBnInclude\ - HASH_LIB=Ossl;SYM_LIB=Ossl;MATH_LIB=Ossl;CRYPTO_ALIGN_16;_DEBUG;%(PreprocessorDefinitions) - true - EnableFastChecks - MultiThreadedDebugDLL - - - EnableAllWarnings - ProgramDatabase - 4668; 4710;4711; 4820 - true - - - cryptoengine.lib;platform.lib;%(AdditionalDependencies) - true - Console - MachineX64 - $(SolutionDir)\lib\x64;$(OutDir);%(AdditionalLibraryDirectories) - - - - - - - MaxSpeed - $(ProjectDir)include\;$(ProjectDir)include\prototypes\;$(SolutionDir)Platform\include\;$(SolutionDir)Platform\include\prototypes\;$(SolutionDir)LtcInclude\;$(SolutionDIr)OsslInclude\;$(SolutionDir)MsBnInclude\ - true - HASH_LIB=Ossl;SYM_LIB=Ossl;MATH_LIB=Ossl;CRYPTO_ALIGN_4;NDEBUG;%(PreprocessorDefinitions) - MultiThreadedDLL - true - NotUsing - EnableAllWarnings - ProgramDatabase - CompileAsC - true - 4668; 4710;4711; 4820 - - - platform.lib;libeay32.lib;%(AdditionalDependencies) - true - Console - true - true - MachineX86 - $(SolutionDir)\lib;$(OutDir);%(AdditionalLibraryDirectories) - - - $(OutDir)$(TargetName)$(TargetExt) - - - - - MaxSpeed - $(ProjectDir)include\wolf;$(SolutionDir)..\external\wolfssl;$(SolutionDir)\wolfcrypt\include;%(AdditionalIncludeDirectories) - true - HASH_LIB=Wolf;SYM_LIB=Wolf;MATH_LIB=Wolf;WOLFSSL_USER_SETTINGS;CRYPTO_ALIGN_4;NDEBUG;%(PreprocessorDefinitions) - MultiThreadedDLL - true - NotUsing - EnableAllWarnings - ProgramDatabase - CompileAsC - 4255;4668; 4710;4711; 4820 - true - - - wolfssl.lib;platform.lib;%(AdditionalDependencies) - true - Console - true - true - MachineX86 - $(SolutionDir)\lib;$(OutDir);%(AdditionalLibraryDirectories) - - - $(OutDir)$(TargetName)$(TargetExt) - - - - - X64 - - - MaxSpeed - $(ProjectDir)include\;$(ProjectDir)include\prototypes\;$(SolutionDir)Platform\include\;$(SolutionDir)Platform\include\prototypes\;$(SolutionDir)LtcInclude\;$(SolutionDIr)OsslInclude\;$(SolutionDir)MsBnInclude\ - true - HASH_LIB=Ossl;SYM_LIB=Ossl;MATH_LIB=Ossl;CRYPTO_ALIGN_16;NDEBUG;%(PreprocessorDefinitions); - MultiThreadedDLL - true - - - EnableAllWarnings - ProgramDatabase - 16Bytes - true - 4668; 4710;4711; 4820 - - - true - Console - true - true - MachineX64 - $(SolutionDir)\lib\x64;$(OutDir);%(AdditionalLibraryDirectories) - platform.lib;libeay32.lib;Advapi32.lib;User32.lib;Gdi32.lib - - - - - false - true - - - - - X64 - - - MaxSpeed - $(ProjectDir)include\wolf;$(SolutionDir)..\external\wolfssl;$(SolutionDir)\wolfcrypt\include;%(AdditionalIncludeDirectories) - true - HASH_LIB=Wolf;SYM_LIB=Wolf;MATH_LIB=Wolf;WOLFSSL_USER_SETTINGS;NDEBUG;%(PreprocessorDefinitions) - MultiThreadedDLL - true - - - EnableAllWarnings - ProgramDatabase - 16Bytes - true - 4255;4668; 4710;4711; 4820 - - - true - Console - true - true - MachineX64 - $(OutDir);%(AdditionalLibraryDirectories) - wolfssl.lib;platform.lib;Advapi32.lib - - - - - false - false - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - false - false - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - false - false - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/Tpm.vcxproj.filters b/simulator/ms-tpm-20-ref/TPMCmd/tpm/Tpm.vcxproj.filters deleted file mode 100644 index f9ffe0e73..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/Tpm.vcxproj.filters +++ /dev/null @@ -1,1380 +0,0 @@ - - - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files\Crypt\ossl - - - Source Files\Crypt\ossl - - - Source Files\Crypt\ltc - - - Source Files\Crypt\ltc - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files - - - Source Files\Crypt - - - Source Files - - - Source Files\Crypt - - - Source Files\Crypt\ossl - - - Source Files\Crypt\ltc - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files\AttachedComponent - - - Source Files\AttachedComponent - - - Source Files\AttachedComponent - - - Source Files\AttachedComponent - - - Source Files - - - Source Files\Crypt - - - Source Files - - - Source Files\Crypt - - - Source Files\Crypt - - - Source Files\Crypt\wolf - - - Source Files\Crypt\wolf - - - Source Files\Crypt\wolf - - - Source Files - - - Source Files\X509 - - - Source Files\X509 - - - Source Files\X509 - - - Source Files\X509 - - - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers - - - Headers\prototypes - - - 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Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\Crypt - - - Source Files\X509 - - - Source Files\X509 - - - Source Files\X509 - - - Headers\Crypt - - - Headers\Crypt - - - Headers\Crypt - - - Headers\Crypt - - - Headers\Crypt - - - Headers\Crypt - - - Headers\Crypt - - - Headers\Crypt - - - Headers\Crypt - - - Headers - - - Headers\prototypes - - - Headers\Crypt - - - Headers\Crypt - - - Headers\Crypt - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\Crypt - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers\Crypt\ltc - - - Headers\Crypt\ltc - - - Headers\Crypt\ltc - - - Headers\Crypt\ltc - - - Headers\Crypt\ossl - - - Headers\Crypt\ossl - - - Headers\Crypt\ossl - - - Headers\Crypt\wolf - - - Headers\Crypt\wolf - - - Headers\Crypt\wolf - - - Headers\prototypes - - - Headers\prototypes - - - Headers\prototypes - - - Headers - - - Headers - - - Headers\Crypt\wolf - - - - - {0860d8a3-a60e-4ead-918e-79534b3c000d} - - - {0ac750c7-149f-40fc-9820-47287d744b3b} - - - {be59b71d-f8f7-4132-80f5-e5f6f311614f} - - - {cdeea2ca-7d66-43fc-9431-4bb51e70e78e} - - - {ef67ef8f-3c7e-492b-b8de-0fd83194ad1d} - - - {46a498d0-be4d-4034-b163-014a2ebcf2e1} - - - {6170bedc-9916-44b4-a24b-340b04313b20} - - - {c1608ff8-dc12-4101-8859-6d763377b840} - - - {eb07d621-fe5c-415a-84f0-d0e4c68039ed} - - - {1a979e04-0e58-4286-b6b0-52cb2b86d037} - - - {17d101a1-3063-43f5-960b-b0df7b0950cc} - - - {19c87ebb-c1f3-4521-a442-d9120957d238} - - - {c0101f08-45d5-48bf-bc4d-a64e300da76d} - - - \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/CryptHash.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/CryptHash.h index fe74f266b..de6eb5148 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/CryptHash.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/CryptHash.h @@ -239,10 +239,10 @@ typedef const struct HASH_DEF (HASH_STATE_EXPORT_METHOD *)&tpmHashStateExport_##HASH, \ (HASH_STATE_IMPORT_METHOD *)&tpmHashStateImport_##HASH, \ }, \ - HASH##_BLOCK_SIZE, /* block size */ \ - HASH##_DIGEST_SIZE, /* data size */ \ - sizeof(tpmHashState##HASH##_t), \ - TPM_ALG_##HASH, OID_##HASH \ + HASH##_BLOCK_SIZE, /*block size */ \ + HASH##_DIGEST_SIZE, /*data size */ \ + sizeof(tpmHashState##HASH##_t), \ + TPM_ALG_##HASH, OID_##HASH \ PKCS1_OID(HASH) ECDSA_OID(HASH)}; // These definitions are for the types that can be in a hash state structure. @@ -292,8 +292,7 @@ typedef struct hmacState } HMAC_STATE, *PHMAC_STATE; // This is for the external hash state. This implementation assumes that the size -// of the exported hash state is no larger than the internal hash state. There -// is a run time check that makes sure that this i. +// of the exported hash state is no larger than the internal hash state. typedef struct { BYTE buffer[sizeof(HASH_STATE)]; diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/CryptSym.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/CryptSym.h index 6f19e43dd..efbd24195 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/CryptSym.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/CryptSym.h @@ -75,10 +75,10 @@ typedef union tpmCryptKeySchedule_t { // or decrypt with the algorithm chosen by setting a function pointer to select // the algorithm that is used. -# define ENCRYPT(keySchedule, in, out) \ +# define ENCRYPT(keySchedule, in, out) \ encrypt(SWIZZLE(keySchedule, in, out)) -# define DECRYPT(keySchedule, in, out) \ +# define DECRYPT(keySchedule, in, out) \ decrypt(SWIZZLE(keySchedule, in, out)) diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Global.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Global.h index a121edba6..09bf6fc41 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Global.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Global.h @@ -63,7 +63,7 @@ #define INITIALIZER(_value_) = _value_ #else #define EXTERN extern -#define INITIALIZER(_name_) +#define INITIALIZER(_value_) #endif _REDUCE_WARNING_LEVEL_(2) @@ -679,6 +679,7 @@ EXTERN BOOL g_nvOk; // so that its value remains consistent during the command execution EXTERN TPM_RC g_NvStatus; +#ifdef VENDOR_PERMANENT //*** g_platformUnique // This location contains the unique value(s) used to identify the TPM. It is // loaded on every _TPM2_Startup() @@ -693,6 +694,7 @@ EXTERN TPM_RC g_NvStatus; EXTERN TPM2B_AUTH g_platformUniqueAuthorities; // Reserved for RNG EXTERN TPM2B_AUTH g_platformUniqueDetails; // referenced by VENDOR_PERMANENT +#endif //********************************************************************************* //********************************************************************************* @@ -916,9 +918,9 @@ EXTERN ORDERLY_DATA go; //*** STATE_CLEAR_DATA //********************************************************************************* //********************************************************************************* -// This structure contains the data that is saved on Shutdown(STATE). +// This structure contains the data that is saved on Shutdown(STATE) // and restored on Startup(STATE). The values are set to their default -// settings on any Startup(Clear). In other words the data is only persistent +// settings on any Startup(Clear). In other words, the data is only persistent // across TPM Resume. // // If the comments associated with a parameter indicate a default reset value, the diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/GpMacros.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/GpMacros.h index 47818c0f0..22f1b5a7e 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/GpMacros.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/GpMacros.h @@ -53,9 +53,9 @@ // Use of TPM_ALG_NULL is reserved for RSAEP/RSADP testing. If someone is wanting // to test a hash with that value, don't do it. -# define TEST_HASH(alg) \ - if(TEST_BIT(alg, g_toTest) \ - && (alg != ALG_NULL_VALUE)) \ +# define TEST_HASH(alg) \ + if(TEST_BIT(alg, g_toTest) \ + && (alg != ALG_NULL_VALUE)) \ CryptTestAlgorithm(alg, NULL) #else # define TEST(alg) @@ -93,16 +93,16 @@ // if it is not. If longjmp is being used, then the FAIL(FATAL_ERROR_) macro makes // a call from which there is no return. Otherwise, it returns and the function // will exit with the appropriate return code. -#define REQUIRE(condition, errorCode, returnCode) \ - { \ - if(!!(condition)) \ - { \ - FAIL(FATAL_ERROR_errorCode); \ - FAIL_RETURN(returnCode); \ - } \ +#define REQUIRE(condition, errorCode, returnCode) \ + { \ + if(!!(condition)) \ + { \ + FAIL(FATAL_ERROR_errorCode); \ + FAIL_RETURN(returnCode); \ + } \ } -#define PARAMETER_CHECK(condition, returnCode) \ +#define PARAMETER_CHECK(condition, returnCode) \ REQUIRE((condition), PARAMETER, returnCode) #if (defined EMPTY_ASSERT) && (EMPTY_ASSERT != NO) @@ -112,14 +112,10 @@ #endif //** Derived from Vendor-specific values -// Values derived from vendor specific settings in Implementation.h +// Values derived from vendor specific settings in TpmProfile.h #define PCR_SELECT_MIN ((PLATFORM_PCR+7)/8) #define PCR_SELECT_MAX ((IMPLEMENTATION_PCR+7)/8) #define MAX_ORDERLY_COUNT ((1 << ORDERLY_BITS) - 1) -#ifndef PRIVATE_VENDOR_SPECIFIC_BYTES -# define PRIVATE_VENDOR_SPECIFIC_BYTES \ - ((MAX_RSA_KEY_BYTES/2) * (3 + CRT_FORMAT_RSA * 2)) -#endif //** Compile-time Checks // In some cases, the relationship between two values may be dependent @@ -141,10 +137,10 @@ // This is used commonly in the "Crypt" code as a way to keep listings from // getting too long. This is not to save paper but to allow one to see more // useful stuff on the screen at any given time. -#define ERROR_RETURN(returnCode) \ - { \ - retVal = returnCode; \ - goto Exit; \ +#define ERROR_RETURN(returnCode) \ + { \ + retVal = returnCode; \ + goto Exit; \ } #ifndef MAX @@ -183,10 +179,10 @@ #define STD_RESPONSE_HEADER (sizeof(TPM_ST) + sizeof(UINT32) + sizeof(TPM_RC)) -#define JOIN(x,y) x##y +#define JOIN(x, y) x##y #define JOIN3(x, y, z) x##y##z -#define CONCAT(x,y) JOIN(x, y) -#define CONCAT3(x,y,z) JOIN3(x,y,z) +#define CONCAT(x, y) JOIN(x, y) +#define CONCAT3(x, y, z) JOIN3(x,y,z) // If CONTEXT_INTEGRITY_HASH_ALG is defined, then the vendor is using the old style // table. Otherwise, pick the "strongest" implemented hash algorithm as the context @@ -209,25 +205,25 @@ #ifndef CONTEXT_INTEGRITY_HASH_SIZE #define CONTEXT_INTEGRITY_HASH_SIZE CONCAT(CONTEXT_HASH_ALGORITHM, _DIGEST_SIZE) #endif -#if ALG_RSA -#define RSA_SECURITY_STRENGTH (MAX_RSA_KEY_BITS >= 15360 ? 256 : \ - (MAX_RSA_KEY_BITS >= 7680 ? 192 : \ - (MAX_RSA_KEY_BITS >= 3072 ? 128 : \ - (MAX_RSA_KEY_BITS >= 2048 ? 112 : \ +#if ALG_RSA +#define RSA_SECURITY_STRENGTH (MAX_RSA_KEY_BITS >= 15360 ? 256 : \ + (MAX_RSA_KEY_BITS >= 7680 ? 192 : \ + (MAX_RSA_KEY_BITS >= 3072 ? 128 : \ + (MAX_RSA_KEY_BITS >= 2048 ? 112 : \ (MAX_RSA_KEY_BITS >= 1024 ? 80 : 0))))) #else #define RSA_SECURITY_STRENGTH 0 #endif // ALG_RSA -#if ALG_ECC -#define ECC_SECURITY_STRENGTH (MAX_ECC_KEY_BITS >= 521 ? 256 : \ - (MAX_ECC_KEY_BITS >= 384 ? 192 : \ +#if ALG_ECC +#define ECC_SECURITY_STRENGTH (MAX_ECC_KEY_BITS >= 521 ? 256 : \ + (MAX_ECC_KEY_BITS >= 384 ? 192 : \ (MAX_ECC_KEY_BITS >= 256 ? 128 : 0))) #else #define ECC_SECURITY_STRENGTH 0 #endif // ALG_ECC -#define MAX_ASYM_SECURITY_STRENGTH \ +#define MAX_ASYM_SECURITY_STRENGTH \ MAX(RSA_SECURITY_STRENGTH, ECC_SECURITY_STRENGTH) #define MAX_HASH_SECURITY_STRENGTH ((CONTEXT_INTEGRITY_HASH_SIZE * 8) / 2) @@ -235,9 +231,9 @@ // Unless some algorithm is broken... #define MAX_SYM_SECURITY_STRENGTH MAX_SYM_KEY_BITS -#define MAX_SECURITY_STRENGTH_BITS \ - MAX(MAX_ASYM_SECURITY_STRENGTH, \ - MAX(MAX_SYM_SECURITY_STRENGTH, \ +#define MAX_SECURITY_STRENGTH_BITS \ + MAX(MAX_ASYM_SECURITY_STRENGTH, \ + MAX(MAX_SYM_SECURITY_STRENGTH, \ MAX_HASH_SECURITY_STRENGTH)) // This is the size that was used before the 1.38 errata requiring that P1.14.4 be @@ -245,11 +241,11 @@ #define PROOF_SIZE CONTEXT_INTEGRITY_HASH_SIZE // As required by P1.14.4 -#define COMPLIANT_PROOF_SIZE \ +#define COMPLIANT_PROOF_SIZE \ (MAX(CONTEXT_INTEGRITY_HASH_SIZE, (2 * MAX_SYM_KEY_BYTES))) - + // As required by P1.14.3.1 -#define COMPLIANT_PRIMARY_SEED_SIZE \ +#define COMPLIANT_PRIMARY_SEED_SIZE \ BITS_TO_BYTES(MAX_SECURITY_STRENGTH_BITS * 2) // This is the pre-errata version @@ -269,7 +265,7 @@ # error "PROOF_SIZE is not compliant with TPM specification" # endif # if PRIMARY_SEED_SIZE < COMPLIANT_PRIMARY_SEED_SIZE -# error "Implementation.h specifies a non-compliant PRIMARY_SEED_SIZE" +# error Non-compliant PRIMARY_SEED_SIZE # endif #endif // !SKIP_PROOF_ERRORS @@ -291,16 +287,10 @@ # define CONTEXT_ENCRYPT_ALG \ CONCAT3(ALG_, CONTEXT_ENCRYPT_ALGORITHM, _VALUE) #endif // CONTEXT_ENCRYPT_ALG -#define CONTEXT_ENCRYPT_KEY_BITS \ +#define CONTEXT_ENCRYPT_KEY_BITS \ CONCAT(CONTEXT_ENCRYPT_ALGORITHM, _MAX_KEY_SIZE_BITS) #define CONTEXT_ENCRYPT_KEY_BYTES ((CONTEXT_ENCRYPT_KEY_BITS+7)/8) - -#if (CONTEXT_ENCRYPT_ALG != ALG_AES_VALUE) && (CONTEXT_ENCRYPT_ALG != ALG_SM4_VALUE)\ - && (CONTEXT_ENCRYPT_ALG != ALG_CAMELLIA_VALUE) -# error Encryption algorithm selection broken -#endif - // This is updated to follow the requirement of P2 that the label not be larger // than 32 bytes. #ifndef LABEL_MAX_BUFFER @@ -312,7 +302,7 @@ // and TPM2_PolicySecret() and used by TPM2_PolicyTicket(). The timeout value is // relative to Time (g_time). Time is reset whenever the TPM loses power and cannot // be moved forward by the user (as can Clock). 'g_time' is a 64-bit value expressing -// time in ms. Sealing the MSb for a flag means that the TPM needs to be reset +// time in ms. Stealing the MSb for a flag means that the TPM needs to be reset // at least once every 292,471,208 years rather than once every 584,942,417 years. #define EXPIRATION_BIT ((UINT64)1 << 63) @@ -323,9 +313,9 @@ // These macros are used to handle the variation in handling of bit fields. If #if USE_BIT_FIELD_STRUCTURES // The default, old version, with bit fields -# define IS_ATTRIBUTE(a, type, b) (a.b != 0) -# define SET_ATTRIBUTE(a, type, b) (a.b = SET) -# define CLEAR_ATTRIBUTE(a, type, b) (a.b = CLEAR) +# define IS_ATTRIBUTE(a, type, b) ((a.b) != 0) +# define SET_ATTRIBUTE(a, type, b) (a.b = SET) +# define CLEAR_ATTRIBUTE(a, type, b) (a.b = CLEAR) # define GET_ATTRIBUTE(a, type, b) (a.b) # define TPMA_ZERO_INITIALIZER() {0} #else @@ -334,9 +324,9 @@ # define CLEAR_ATTRIBUTE(a, type, b) (a &= ~type##_##b) # define GET_ATTRIBUTE(a, type, b) \ (type)((a & type##_##b) >> type##_##b##_SHIFT) -# define TPMA_ZERO_INITIALIZER() 0 +# define TPMA_ZERO_INITIALIZER() (0) #endif #define VERIFY(_X) if(!(_X)) goto Error -#endif // GP_MACROS_H +#endif // GP_MACROS_H \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Implementation.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Implementation.h deleted file mode 100644 index 39a9d4acd..000000000 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Implementation.h +++ /dev/null @@ -1,1224 +0,0 @@ -/* Microsoft Reference Implementation for TPM 2.0 - * - * The copyright in this software is being made available under the BSD License, - * included below. This software may be subject to other third party and - * contributor rights, including patent rights, and no such rights are granted - * under this license. - * - * Copyright (c) Microsoft Corporation - * - * All rights reserved. - * - * BSD License - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ""AS IS"" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*(Auto-generated) - * Created by TpmStructures; Version 4.1 Dec 8, 2018 - * Date: Jan 28, 2019 Time: 12:36:23AM - */ -#ifndef _IMPLEMENTATION_H_ -#define _IMPLEMENTATION_H_ - - -#include "TpmBuildSwitches.h" -#include "BaseTypes.h" -#include "TPMB.h" - -#undef TRUE -#undef FALSE - -#ifndef MAX -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#define MAX3(a, b, c) MAX((a), MAX((b), (c))) -#define MAX4(a, b, c, d) MAX((a), MAX3((b), (c), (d))) -#define MAX5(a, b, c, d, e) MAX((a), MAX4((b), (c), (d), (e))) -#endif - -#ifndef MIN -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#endif -// Table 2:3 - Definition of Base Types -// Base Types are in BaseTypes.h - -// Table 2:4 - Defines for Logic Values -#define TRUE 1 -#define FALSE 0 -#define YES 1 -#define NO 0 -#define SET 1 -#define CLEAR 0 - -// Table 0:1 - Defines for Processor Values -#ifndef BIG_ENDIAN_TPM -#define BIG_ENDIAN_TPM NO -#endif // BIG_ENDIAN_TPM -#define LITTLE_ENDIAN_TPM !BIG_ENDIAN_TPM -#ifndef MOST_SIGNIFICANT_BIT_0 -#define MOST_SIGNIFICANT_BIT_0 NO -#endif // MOST_SIGNIFICANT_BIT_0 -#define LEAST_SIGNIFICANT_BIT_0 !MOST_SIGNIFICANT_BIT_0 -#ifndef AUTO_ALIGN -#define AUTO_ALIGN NO -#endif // AUTO_ALIGN - -// Table 0:3 - Defines for Key Size Constants -#define RSA_KEY_SIZE_BITS_1024 RSA_ALLOWED_KEY_SIZE_1024 -#define RSA_KEY_SIZE_BITS_2048 RSA_ALLOWED_KEY_SIZE_2048 -#define MAX_RSA_KEY_BITS 2048 -#define MAX_RSA_KEY_BYTES 256 - -// Table 0:4 - Defines for Implemented Curves -#define ECC_NIST_P192 NO -#define ECC_NIST_P224 NO -#define ECC_NIST_P256 YES -#define ECC_NIST_P384 YES -#define ECC_NIST_P521 NO -#ifdef USE_WOLFCRYPT -#define ECC_BN_P256 NO -#define ECC_SM2_P256 NO -#define ECC_BN_P638 NO -#else -#define ECC_BN_P256 YES -#define ECC_BN_P638 NO -#define ECC_SM2_P256 NO -#endif -#define ECC_CURVES \ - {TPM_ECC_BN_P256, TPM_ECC_BN_P638, TPM_ECC_NIST_P192, \ - TPM_ECC_NIST_P224, TPM_ECC_NIST_P256, TPM_ECC_NIST_P384, \ - TPM_ECC_NIST_P521, TPM_ECC_SM2_P256} -#define ECC_CURVE_COUNT \ - (ECC_BN_P256 + ECC_BN_P638 + ECC_NIST_P192 + ECC_NIST_P224 + \ - ECC_NIST_P256 + ECC_NIST_P384 + ECC_NIST_P521 + ECC_SM2_P256) -#define MAX_ECC_KEY_BITS \ - MAX(ECC_BN_P256 * 256, MAX(ECC_BN_P638 * 638, \ - MAX(ECC_NIST_P192 * 192, MAX(ECC_NIST_P224 * 224, \ - MAX(ECC_NIST_P256 * 256, MAX(ECC_NIST_P384 * 384, \ - MAX(ECC_NIST_P521 * 521, MAX(ECC_SM2_P256 * 256, \ - 0)))))))) -#define MAX_ECC_KEY_BYTES BITS_TO_BYTES(MAX_ECC_KEY_BITS) - -// Table 0:6 - Defines for PLATFORM Values -#define PLATFORM_FAMILY TPM_SPEC_FAMILY -#define PLATFORM_LEVEL TPM_SPEC_LEVEL -#define PLATFORM_VERSION TPM_SPEC_VERSION -#define PLATFORM_YEAR TPM_SPEC_YEAR -#define PLATFORM_DAY_OF_YEAR TPM_SPEC_DAY_OF_YEAR - -// Table 0:7 - Defines for Implementation Values -#define FIELD_UPGRADE_IMPLEMENTED NO -#if defined(__x86_64__) || defined(__x86_64) || defined(__amd64__) || defined(__amd64) || defined(_WIN64) || defined(_M_X64) || defined(_M_ARM64) || defined(__aarch64__) -#define RADIX_BITS 64 -#elif defined(__i386__) || defined(__i386) || defined(i386) || defined(_WIN32) || defined(_M_IX86) || defined(_M_ARM) || defined(__arm__) || defined(__thumb__) -#define RADIX_BITS 32 -#else -#error "Unable to determine RADIX_BITS from compiler environment." -#endif -#define HASH_ALIGNMENT 4 -#define SYMMETRIC_ALIGNMENT 4 -#ifdef USE_WOLFCRYPT -#define HASH_LIB WOLF -#define SYM_LIB WOLF -#define MATH_LIB WOLF -#else -#define HASH_LIB OSSL -#define SYM_LIB OSSL -#define MATH_LIB OSSL -#endif -#define BSIZE UINT16 -#define PLATFORM_PCR 24 -#define PCR_SELECT_MIN ((PLATFORM_PCR+7)/8) -#define IMPLEMENTATION_PCR 24 -#define PCR_SELECT_MAX ((IMPLEMENTATION_PCR+7)/8) -#define DRTM_PCR 17 -#define HCRTM_PCR 0 -#define NUM_LOCALITIES 5 -#define MAX_HANDLE_NUM 3 -#define MAX_ACTIVE_SESSIONS 64 -#define CONTEXT_SLOT UINT16 -#define CONTEXT_COUNTER UINT64 -#define MAX_LOADED_SESSIONS 3 -#define MAX_SESSION_NUM 3 -#define MAX_LOADED_OBJECTS 3 -#define MIN_EVICT_OBJECTS 2 -#define NUM_POLICY_PCR_GROUP 1 -#define NUM_AUTHVALUE_PCR_GROUP 1 -#define MAX_CONTEXT_SIZE 1264 -#define MAX_DIGEST_BUFFER 1024 -#define MAX_NV_INDEX_SIZE 2048 -#define MAX_NV_BUFFER_SIZE 1024 -#define MAX_CAP_BUFFER 1024 -#define NV_MEMORY_SIZE 16384 -#define MIN_COUNTER_INDICES 8 -#define NUM_STATIC_PCR 16 -#define MAX_ALG_LIST_SIZE 64 -#define PRIMARY_SEED_SIZE 32 -#define CONTEXT_ENCRYPT_ALG ALG_AES_VALUE -#define NV_CLOCK_UPDATE_INTERVAL 12 -#define NUM_POLICY_PCR 1 -#define MAX_COMMAND_SIZE 4096 -#define MAX_RESPONSE_SIZE 4096 -#define ORDERLY_BITS 8 -#define MAX_SYM_DATA 128 -#define MAX_RNG_ENTROPY_SIZE 64 -#define RAM_INDEX_SPACE 512 -#define RSA_DEFAULT_PUBLIC_EXPONENT 0x00010001 -#define ENABLE_PCR_NO_INCREMENT YES -#define CRT_FORMAT_RSA YES -#define VENDOR_COMMAND_COUNT 0 -#define MAX_VENDOR_BUFFER_SIZE 1024 -#define TPM_MAX_DERIVATION_BITS 8192 -#define SIZE_OF_X509_SERIAL_NUMBER 20 -#define PRIMES 5 -#define MAX_RSA_PRIME_SIZE MAX_RSA_KEY_BYTES/2 -#define RSA_PRIVATE_SIZE (PRIMES*MAX_RSA_PRIME_SIZE) -#define PRIVATE_VENDOR_SPECIFIC_BYTES RSA_PRIVATE_SIZE - -// Table 0:2 - Defines for Implemented Algorithms -#define ALG_AES ALG_YES -#define ALG_CAMELLIA ALG_NO /* Not specified by vendor */ -#define ALG_CBC ALG_YES -#define ALG_CFB ALG_YES -#define ALG_CMAC ALG_YES -#define ALG_CTR ALG_YES -#define ALG_ECB ALG_YES -#define ALG_ECC ALG_YES -#define ALG_ECDAA (ALG_YES && ALG_ECC) -#define ALG_ECDH (ALG_YES && ALG_ECC) -#define ALG_ECDSA (ALG_YES && ALG_ECC) -#define ALG_ECMQV (ALG_NO && ALG_ECC) -#define ALG_ECSCHNORR (ALG_YES && ALG_ECC) -#define ALG_HMAC ALG_YES -#define ALG_KDF1_SP800_108 ALG_YES -#define ALG_KDF1_SP800_56A (ALG_YES && ALG_ECC) -#define ALG_KDF2 ALG_NO -#define ALG_KEYEDHASH ALG_YES -#define ALG_MGF1 ALG_YES -#define ALG_OAEP (ALG_YES && ALG_RSA) -#define ALG_OFB ALG_YES -#define ALG_RSA ALG_YES -#define ALG_RSAES (ALG_YES && ALG_RSA) -#define ALG_RSAPSS (ALG_YES && ALG_RSA) -#define ALG_RSASSA (ALG_YES && ALG_RSA) -#define ALG_SHA ALG_NO /* Not specified by vendor */ -#define ALG_SHA1 ALG_YES -#define ALG_SHA256 ALG_YES -#define ALG_SHA384 ALG_YES -#define ALG_SHA512 ALG_NO -#define ALG_SM2 (ALG_NO && ALG_ECC) -#define ALG_SM3_256 ALG_NO -#define ALG_SM4 ALG_NO -#define ALG_SYMCIPHER ALG_YES -#define ALG_TDES ALG_NO -#define ALG_XOR ALG_YES - -// Table 1:2 - Definition of TPM_ALG_ID Constants -typedef UINT16 TPM_ALG_ID; -#define TYPE_OF_TPM_ALG_ID UINT16 -#define ALG_ERROR_VALUE 0x0000 -#define TPM_ALG_ERROR (TPM_ALG_ID)(ALG_ERROR_VALUE) -#define ALG_RSA_VALUE 0x0001 -#if ALG_RSA -#define TPM_ALG_RSA (TPM_ALG_ID)(ALG_RSA_VALUE) -#endif // ALG_RSA -#define ALG_TDES_VALUE 0x0003 -#if ALG_TDES -#define TPM_ALG_TDES (TPM_ALG_ID)(ALG_TDES_VALUE) -#endif // ALG_TDES -#define ALG_SHA_VALUE 0x0004 -#if ALG_SHA -#define TPM_ALG_SHA (TPM_ALG_ID)(ALG_SHA_VALUE) -#endif // ALG_SHA -#define ALG_SHA1_VALUE 0x0004 -#if ALG_SHA1 -#define TPM_ALG_SHA1 (TPM_ALG_ID)(ALG_SHA1_VALUE) -#endif // ALG_SHA1 -#define ALG_HMAC_VALUE 0x0005 -#if ALG_HMAC -#define TPM_ALG_HMAC (TPM_ALG_ID)(ALG_HMAC_VALUE) -#endif // ALG_HMAC -#define ALG_AES_VALUE 0x0006 -#if ALG_AES -#define TPM_ALG_AES (TPM_ALG_ID)(ALG_AES_VALUE) -#endif // ALG_AES -#define ALG_MGF1_VALUE 0x0007 -#if ALG_MGF1 -#define TPM_ALG_MGF1 (TPM_ALG_ID)(ALG_MGF1_VALUE) -#endif // ALG_MGF1 -#define ALG_KEYEDHASH_VALUE 0x0008 -#if ALG_KEYEDHASH -#define TPM_ALG_KEYEDHASH (TPM_ALG_ID)(ALG_KEYEDHASH_VALUE) -#endif // ALG_KEYEDHASH -#define ALG_XOR_VALUE 0x000A -#if ALG_XOR -#define TPM_ALG_XOR (TPM_ALG_ID)(ALG_XOR_VALUE) -#endif // ALG_XOR -#define ALG_SHA256_VALUE 0x000B -#if ALG_SHA256 -#define TPM_ALG_SHA256 (TPM_ALG_ID)(ALG_SHA256_VALUE) -#endif // ALG_SHA256 -#define ALG_SHA384_VALUE 0x000C -#if ALG_SHA384 -#define TPM_ALG_SHA384 (TPM_ALG_ID)(ALG_SHA384_VALUE) -#endif // ALG_SHA384 -#define ALG_SHA512_VALUE 0x000D -#if ALG_SHA512 -#define TPM_ALG_SHA512 (TPM_ALG_ID)(ALG_SHA512_VALUE) -#endif // ALG_SHA512 -#define ALG_NULL_VALUE 0x0010 -#define TPM_ALG_NULL (TPM_ALG_ID)(ALG_NULL_VALUE) -#define ALG_SM3_256_VALUE 0x0012 -#if ALG_SM3_256 -#define TPM_ALG_SM3_256 (TPM_ALG_ID)(ALG_SM3_256_VALUE) -#endif // ALG_SM3_256 -#define ALG_SM4_VALUE 0x0013 -#if ALG_SM4 -#define TPM_ALG_SM4 (TPM_ALG_ID)(ALG_SM4_VALUE) -#endif // ALG_SM4 -#define ALG_RSASSA_VALUE 0x0014 -#if ALG_RSASSA -#define TPM_ALG_RSASSA (TPM_ALG_ID)(ALG_RSASSA_VALUE) -#endif // ALG_RSASSA -#define ALG_RSAES_VALUE 0x0015 -#if ALG_RSAES -#define TPM_ALG_RSAES (TPM_ALG_ID)(ALG_RSAES_VALUE) -#endif // ALG_RSAES -#define ALG_RSAPSS_VALUE 0x0016 -#if ALG_RSAPSS -#define TPM_ALG_RSAPSS (TPM_ALG_ID)(ALG_RSAPSS_VALUE) -#endif // ALG_RSAPSS -#define ALG_OAEP_VALUE 0x0017 -#if ALG_OAEP -#define TPM_ALG_OAEP (TPM_ALG_ID)(ALG_OAEP_VALUE) -#endif // ALG_OAEP -#define ALG_ECDSA_VALUE 0x0018 -#if ALG_ECDSA -#define TPM_ALG_ECDSA (TPM_ALG_ID)(ALG_ECDSA_VALUE) -#endif // ALG_ECDSA -#define ALG_ECDH_VALUE 0x0019 -#if ALG_ECDH -#define TPM_ALG_ECDH (TPM_ALG_ID)(ALG_ECDH_VALUE) -#endif // ALG_ECDH -#define ALG_ECDAA_VALUE 0x001A -#if ALG_ECDAA -#define TPM_ALG_ECDAA (TPM_ALG_ID)(ALG_ECDAA_VALUE) -#endif // ALG_ECDAA -#define ALG_SM2_VALUE 0x001B -#if ALG_SM2 -#define TPM_ALG_SM2 (TPM_ALG_ID)(ALG_SM2_VALUE) -#endif // ALG_SM2 -#define ALG_ECSCHNORR_VALUE 0x001C -#if ALG_ECSCHNORR -#define TPM_ALG_ECSCHNORR (TPM_ALG_ID)(ALG_ECSCHNORR_VALUE) -#endif // ALG_ECSCHNORR -#define ALG_ECMQV_VALUE 0x001D -#if ALG_ECMQV -#define TPM_ALG_ECMQV (TPM_ALG_ID)(ALG_ECMQV_VALUE) -#endif // ALG_ECMQV -#define ALG_KDF1_SP800_56A_VALUE 0x0020 -#if ALG_KDF1_SP800_56A -#define TPM_ALG_KDF1_SP800_56A (TPM_ALG_ID)(ALG_KDF1_SP800_56A_VALUE) -#endif // ALG_KDF1_SP800_56A -#define ALG_KDF2_VALUE 0x0021 -#if ALG_KDF2 -#define TPM_ALG_KDF2 (TPM_ALG_ID)(ALG_KDF2_VALUE) -#endif // ALG_KDF2 -#define ALG_KDF1_SP800_108_VALUE 0x0022 -#if ALG_KDF1_SP800_108 -#define TPM_ALG_KDF1_SP800_108 (TPM_ALG_ID)(ALG_KDF1_SP800_108_VALUE) -#endif // ALG_KDF1_SP800_108 -#define ALG_ECC_VALUE 0x0023 -#if ALG_ECC -#define TPM_ALG_ECC (TPM_ALG_ID)(ALG_ECC_VALUE) -#endif // ALG_ECC -#define ALG_SYMCIPHER_VALUE 0x0025 -#if ALG_SYMCIPHER -#define TPM_ALG_SYMCIPHER (TPM_ALG_ID)(ALG_SYMCIPHER_VALUE) -#endif // ALG_SYMCIPHER -#define ALG_CAMELLIA_VALUE 0x0026 -#if ALG_CAMELLIA -#define TPM_ALG_CAMELLIA (TPM_ALG_ID)(ALG_CAMELLIA_VALUE) -#endif // ALG_CAMELLIA -#define ALG_CMAC_VALUE 0x003F -#if ALG_CMAC -#define TPM_ALG_CMAC (TPM_ALG_ID)(ALG_CMAC_VALUE) -#endif // ALG_CMAC -#define ALG_CTR_VALUE 0x0040 -#if ALG_CTR -#define TPM_ALG_CTR (TPM_ALG_ID)(ALG_CTR_VALUE) -#endif // ALG_CTR -#define ALG_OFB_VALUE 0x0041 -#if ALG_OFB -#define TPM_ALG_OFB (TPM_ALG_ID)(ALG_OFB_VALUE) -#endif // ALG_OFB -#define ALG_CBC_VALUE 0x0042 -#if ALG_CBC -#define TPM_ALG_CBC (TPM_ALG_ID)(ALG_CBC_VALUE) -#endif // ALG_CBC -#define ALG_CFB_VALUE 0x0043 -#if ALG_CFB -#define TPM_ALG_CFB (TPM_ALG_ID)(ALG_CFB_VALUE) -#endif // ALG_CFB -#define ALG_ECB_VALUE 0x0044 -#if ALG_ECB -#define TPM_ALG_ECB (TPM_ALG_ID)(ALG_ECB_VALUE) -#endif // ALG_ECB -// Values derived from Table 1:2 -#define ALG_FIRST_VALUE 0x0001 -#define TPM_ALG_FIRST (TPM_ALG_ID)(ALG_FIRST_VALUE) -#define ALG_LAST_VALUE 0x0044 -#define TPM_ALG_LAST (TPM_ALG_ID)(ALG_LAST_VALUE) - -// Table 1:3 - Definition of TPM_ECC_CURVE Constants -typedef UINT16 TPM_ECC_CURVE; -#define TYPE_OF_TPM_ECC_CURVE UINT16 -#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000) -#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001) -#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002) -#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003) -#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004) -#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005) -#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010) -#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011) -#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020) - -// Table 1:12 - Defines for SHA1 Hash Values -#define SHA1_DIGEST_SIZE 20 -#define SHA1_BLOCK_SIZE 64 -#define SHA1_DER_SIZE 15 -#define SHA1_DER \ - 0x30, 0x21, 0x30, 0x09, 0x06, 0x05, 0x2B, 0x0E, \ - 0x03, 0x02, 0x1A, 0x05, 0x00, 0x04, 0x14 - -// Table 1:13 - Defines for SHA256 Hash Values -#define SHA256_DIGEST_SIZE 32 -#define SHA256_BLOCK_SIZE 64 -#define SHA256_DER_SIZE 19 -#define SHA256_DER \ - 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, \ - 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, \ - 0x00, 0x04, 0x20 - -// Table 1:14 - Defines for SHA384 Hash Values -#define SHA384_DIGEST_SIZE 48 -#define SHA384_BLOCK_SIZE 128 -#define SHA384_DER_SIZE 19 -#define SHA384_DER \ - 0x30, 0x41, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, \ - 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x02, 0x05, \ - 0x00, 0x04, 0x30 - -// Table 1:15 - Defines for SHA512 Hash Values -#define SHA512_DIGEST_SIZE 64 -#define SHA512_BLOCK_SIZE 128 -#define SHA512_DER_SIZE 19 -#define SHA512_DER \ - 0x30, 0x51, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, \ - 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x03, 0x05, \ - 0x00, 0x04, 0x40 - -// Table 1:16 - Defines for SM3_256 Hash Values -#define SM3_256_DIGEST_SIZE 32 -#define SM3_256_BLOCK_SIZE 64 -#define SM3_256_DER_SIZE 18 -#define SM3_256_DER \ - 0x30, 0x30, 0x30, 0x0C, 0x06, 0x08, 0x2A, 0x81, \ - 0x1C, 0x81, 0x45, 0x01, 0x83, 0x11, 0x05, 0x00, \ - 0x04, 0x20 - -// Table 1:17 - Defines for AES Symmetric Cipher Algorithm Constants -#define AES_128 (ALG_AES & YES) -#define AES_192 (ALG_AES & NO) -#define AES_256 (ALG_AES & YES) -#define AES_KEY_SIZES_BITS \ - (128 * AES_128), (192 * AES_192), (256 * AES_256) -#if AES_256 -# define AES_MAX_KEY_SIZE_BITS 256 -#elif AES_192 -# define AES_MAX_KEY_SIZE_BITS 192 -#elif AES_128 -# define AES_MAX_KEY_SIZE_BITS 128 -#else -# define AES_MAX_KEY_SIZE_BITS 0 -#endif -#define MAX_AES_KEY_BITS AES_MAX_KEY_SIZE_BITS -#define AES_MAX_KEY_SIZE ((AES_MAX_KEY_SIZE_BITS + 7) / 8) -#define AES_128_BLOCK_SIZE_BYTES (AES_128 * 16) -#define AES_192_BLOCK_SIZE_BYTES (AES_192 * 16) -#define AES_256_BLOCK_SIZE_BYTES (AES_256 * 16) -#define AES_BLOCK_SIZES \ - AES_128_BLOCK_SIZE_BYTES, AES_192_BLOCK_SIZE_BYTES, \ - AES_256_BLOCK_SIZE_BYTES -#if ALG_AES -# define AES_MAX_BLOCK_SIZE 16 -#else -# define AES_MAX_BLOCK_SIZE 0 -#endif -#define MAX_AES_BLOCK_SIZE_BYTES AES_MAX_BLOCK_SIZE - -// Table 1:18 - Defines for SM4 Symmetric Cipher Algorithm Constants -#define SM4_128 (ALG_SM4 & YES) -#define SM4_KEY_SIZES_BITS (128 * SM4_128) -#if SM4_128 -# define SM4_MAX_KEY_SIZE_BITS 128 -#else -# define SM4_MAX_KEY_SIZE_BITS 0 -#endif -#define MAX_SM4_KEY_BITS SM4_MAX_KEY_SIZE_BITS -#define SM4_MAX_KEY_SIZE ((SM4_MAX_KEY_SIZE_BITS + 7) / 8) -#define SM4_128_BLOCK_SIZE_BYTES (SM4_128 * 16) -#define SM4_BLOCK_SIZES SM4_128_BLOCK_SIZE_BYTES -#if ALG_SM4 -# define SM4_MAX_BLOCK_SIZE 16 -#else -# define SM4_MAX_BLOCK_SIZE 0 -#endif -#define MAX_SM4_BLOCK_SIZE_BYTES SM4_MAX_BLOCK_SIZE - -// Table 1:19 - Defines for CAMELLIA Symmetric Cipher Algorithm Constants -#define CAMELLIA_128 (ALG_CAMELLIA & YES) -#define CAMELLIA_192 (ALG_CAMELLIA & NO) -#define CAMELLIA_256 (ALG_CAMELLIA & NO) -#define CAMELLIA_KEY_SIZES_BITS \ - (128 * CAMELLIA_128), (192 * CAMELLIA_192), (256 * CAMELLIA_256) -#if CAMELLIA_256 -# define CAMELLIA_MAX_KEY_SIZE_BITS 256 -#elif CAMELLIA_192 -# define CAMELLIA_MAX_KEY_SIZE_BITS 192 -#elif CAMELLIA_128 -# define CAMELLIA_MAX_KEY_SIZE_BITS 128 -#else -# define CAMELLIA_MAX_KEY_SIZE_BITS 0 -#endif -#define MAX_CAMELLIA_KEY_BITS CAMELLIA_MAX_KEY_SIZE_BITS -#define CAMELLIA_MAX_KEY_SIZE ((CAMELLIA_MAX_KEY_SIZE_BITS + 7) / 8) -#define CAMELLIA_128_BLOCK_SIZE_BYTES (CAMELLIA_128 * 16) -#define CAMELLIA_192_BLOCK_SIZE_BYTES (CAMELLIA_192 * 16) -#define CAMELLIA_256_BLOCK_SIZE_BYTES (CAMELLIA_256 * 16) -#define CAMELLIA_BLOCK_SIZES \ - CAMELLIA_128_BLOCK_SIZE_BYTES, CAMELLIA_192_BLOCK_SIZE_BYTES, \ - CAMELLIA_256_BLOCK_SIZE_BYTES -#if ALG_CAMELLIA -# define CAMELLIA_MAX_BLOCK_SIZE 16 -#else -# define CAMELLIA_MAX_BLOCK_SIZE 0 -#endif -#define MAX_CAMELLIA_BLOCK_SIZE_BYTES CAMELLIA_MAX_BLOCK_SIZE - -// Table 1:17 - Defines for TDES Symmetric Cipher Algorithm Constants -#define TDES_128 (ALG_TDES & YES) -#define TDES_192 (ALG_TDES & YES) -#define TDES_KEY_SIZES_BITS (128 * TDES_128), (192 * TDES_192) -#if TDES_192 -# define TDES_MAX_KEY_SIZE_BITS 192 -#elif TDES_128 -# define TDES_MAX_KEY_SIZE_BITS 128 -#else -# define TDES_MAX_KEY_SIZE_BITS 0 -#endif -#define MAX_TDES_KEY_BITS TDES_MAX_KEY_SIZE_BITS -#define TDES_MAX_KEY_SIZE ((TDES_MAX_KEY_SIZE_BITS + 7) / 8) -#define TDES_128_BLOCK_SIZE_BYTES (TDES_128 * 8) -#define TDES_192_BLOCK_SIZE_BYTES (TDES_192 * 8) -#define TDES_BLOCK_SIZES \ - TDES_128_BLOCK_SIZE_BYTES, TDES_192_BLOCK_SIZE_BYTES -#if ALG_TDES -# define TDES_MAX_BLOCK_SIZE 8 -#else -# define TDES_MAX_BLOCK_SIZE 0 -#endif -#define MAX_TDES_BLOCK_SIZE_BYTES TDES_MAX_BLOCK_SIZE - -// Table 0:5 - Defines for Implemented Commands -#define CC_AC_GetCapability CC_YES -#define CC_AC_Send CC_YES -#define CC_ActivateCredential CC_YES -#define CC_Certify CC_YES -#define CC_CertifyCreation CC_YES -#define CC_CertifyX509 CC_YES -#define CC_ChangeEPS CC_YES -#define CC_ChangePPS CC_YES -#define CC_Clear CC_YES -#define CC_ClearControl CC_YES -#define CC_ClockRateAdjust CC_YES -#define CC_ClockSet CC_YES -#define CC_Commit (CC_YES && ALG_ECC) -#define CC_ContextLoad CC_YES -#define CC_ContextSave CC_YES -#define CC_Create CC_YES -#define CC_CreateLoaded CC_YES -#define CC_CreatePrimary CC_YES -#define CC_DictionaryAttackLockReset CC_YES -#define CC_DictionaryAttackParameters CC_YES -#define CC_Duplicate CC_YES -#define CC_ECC_Parameters (CC_YES && ALG_ECC) -#define CC_ECDH_KeyGen (CC_YES && ALG_ECC) -#define CC_ECDH_ZGen (CC_YES && ALG_ECC) -#define CC_EC_Ephemeral (CC_YES && ALG_ECC) -#define CC_EncryptDecrypt CC_YES -#define CC_EncryptDecrypt2 CC_YES -#define CC_EventSequenceComplete CC_YES -#define CC_EvictControl CC_YES -#define CC_FieldUpgradeData CC_NO -#define CC_FieldUpgradeStart CC_NO -#define CC_FirmwareRead CC_NO -#define CC_FlushContext CC_YES -#define CC_GetCapability CC_YES -#define CC_GetCommandAuditDigest CC_YES -#define CC_GetRandom CC_YES -#define CC_GetSessionAuditDigest CC_YES -#define CC_GetTestResult CC_YES -#define CC_GetTime CC_YES -#define CC_HMAC (CC_YES && !ALG_CMAC) -#define CC_HMAC_Start (CC_YES && !ALG_CMAC) -#define CC_Hash CC_YES -#define CC_HashSequenceStart CC_YES -#define CC_HierarchyChangeAuth CC_YES -#define CC_HierarchyControl CC_YES -#define CC_Import CC_YES -#define CC_IncrementalSelfTest CC_YES -#define CC_Load CC_YES -#define CC_LoadExternal CC_YES -#define CC_MAC (CC_YES && ALG_CMAC) -#define CC_MAC_Start (CC_YES && ALG_CMAC) -#define CC_MakeCredential CC_YES -#define CC_NV_Certify CC_YES -#define CC_NV_ChangeAuth CC_YES -#define CC_NV_DefineSpace CC_YES -#define CC_NV_Extend CC_YES -#define CC_NV_GlobalWriteLock CC_YES -#define CC_NV_Increment CC_YES -#define CC_NV_Read CC_YES -#define CC_NV_ReadLock CC_YES -#define CC_NV_ReadPublic CC_YES -#define CC_NV_SetBits CC_YES -#define CC_NV_UndefineSpace CC_YES -#define CC_NV_UndefineSpaceSpecial CC_YES -#define CC_NV_Write CC_YES -#define CC_NV_WriteLock CC_YES -#define CC_ObjectChangeAuth CC_YES -#define CC_PCR_Allocate CC_YES -#define CC_PCR_Event CC_YES -#define CC_PCR_Extend CC_YES -#define CC_PCR_Read CC_YES -#define CC_PCR_Reset CC_YES -#define CC_PCR_SetAuthPolicy CC_YES -#define CC_PCR_SetAuthValue CC_YES -#define CC_PP_Commands CC_YES -#define CC_PolicyAuthValue CC_YES -#define CC_PolicyAuthorize CC_YES -#define CC_PolicyAuthorizeNV CC_YES -#define CC_PolicyCommandCode CC_YES -#define CC_PolicyCounterTimer CC_YES -#define CC_PolicyCpHash CC_YES -#define CC_PolicyDuplicationSelect CC_YES -#define CC_PolicyGetDigest CC_YES -#define CC_PolicyLocality CC_YES -#define CC_PolicyNV CC_YES -#define CC_PolicyNameHash CC_YES -#define CC_PolicyNvWritten CC_YES -#define CC_PolicyOR CC_YES -#define CC_PolicyPCR CC_YES -#define CC_PolicyPassword CC_YES -#define CC_PolicyPhysicalPresence CC_YES -#define CC_PolicyRestart CC_YES -#define CC_PolicySecret CC_YES -#define CC_PolicySigned CC_YES -#define CC_PolicyTemplate CC_YES -#define CC_PolicyTicket CC_YES -#define CC_Policy_AC_SendSelect CC_YES -#define CC_Quote CC_YES -#define CC_RSA_Decrypt (CC_YES && ALG_RSA) -#define CC_RSA_Encrypt (CC_YES && ALG_RSA) -#define CC_ReadClock CC_YES -#define CC_ReadPublic CC_YES -#define CC_Rewrap CC_YES -#define CC_SelfTest CC_YES -#define CC_SequenceComplete CC_YES -#define CC_SequenceUpdate CC_YES -#define CC_SetAlgorithmSet CC_YES -#define CC_SetCommandCodeAuditStatus CC_YES -#define CC_SetPrimaryPolicy CC_YES -#define CC_Shutdown CC_YES -#define CC_Sign CC_YES -#define CC_StartAuthSession CC_YES -#define CC_Startup CC_YES -#define CC_StirRandom CC_YES -#define CC_TestParms CC_YES -#define CC_Unseal CC_YES -#define CC_Vendor_TCG_Test CC_YES -#define CC_VerifySignature CC_YES -#define CC_ZGen_2Phase (CC_YES && ALG_ECC) - -// Table 2:12 - Definition of TPM_CC Constants -typedef UINT32 TPM_CC; -#define TYPE_OF_TPM_CC UINT32 -#if CC_NV_UndefineSpaceSpecial -#define TPM_CC_NV_UndefineSpaceSpecial (TPM_CC)(0x0000011F) -#endif -#if CC_EvictControl -#define TPM_CC_EvictControl (TPM_CC)(0x00000120) -#endif -#if CC_HierarchyControl -#define TPM_CC_HierarchyControl (TPM_CC)(0x00000121) -#endif -#if CC_NV_UndefineSpace -#define TPM_CC_NV_UndefineSpace (TPM_CC)(0x00000122) -#endif -#if CC_ChangeEPS -#define TPM_CC_ChangeEPS (TPM_CC)(0x00000124) -#endif -#if CC_ChangePPS -#define TPM_CC_ChangePPS (TPM_CC)(0x00000125) -#endif -#if CC_Clear -#define TPM_CC_Clear (TPM_CC)(0x00000126) -#endif -#if CC_ClearControl -#define TPM_CC_ClearControl (TPM_CC)(0x00000127) -#endif -#if CC_ClockSet -#define TPM_CC_ClockSet (TPM_CC)(0x00000128) -#endif -#if CC_HierarchyChangeAuth -#define TPM_CC_HierarchyChangeAuth (TPM_CC)(0x00000129) -#endif -#if CC_NV_DefineSpace -#define TPM_CC_NV_DefineSpace (TPM_CC)(0x0000012A) -#endif -#if CC_PCR_Allocate -#define TPM_CC_PCR_Allocate (TPM_CC)(0x0000012B) -#endif -#if CC_PCR_SetAuthPolicy -#define TPM_CC_PCR_SetAuthPolicy (TPM_CC)(0x0000012C) -#endif -#if CC_PP_Commands -#define TPM_CC_PP_Commands (TPM_CC)(0x0000012D) -#endif -#if CC_SetPrimaryPolicy -#define TPM_CC_SetPrimaryPolicy (TPM_CC)(0x0000012E) -#endif -#if CC_FieldUpgradeStart -#define TPM_CC_FieldUpgradeStart (TPM_CC)(0x0000012F) -#endif -#if CC_ClockRateAdjust -#define TPM_CC_ClockRateAdjust (TPM_CC)(0x00000130) -#endif -#if CC_CreatePrimary -#define TPM_CC_CreatePrimary (TPM_CC)(0x00000131) -#endif -#if CC_NV_GlobalWriteLock -#define TPM_CC_NV_GlobalWriteLock (TPM_CC)(0x00000132) -#endif -#if CC_GetCommandAuditDigest -#define TPM_CC_GetCommandAuditDigest (TPM_CC)(0x00000133) -#endif -#if CC_NV_Increment -#define TPM_CC_NV_Increment (TPM_CC)(0x00000134) -#endif -#if CC_NV_SetBits -#define TPM_CC_NV_SetBits (TPM_CC)(0x00000135) -#endif -#if CC_NV_Extend -#define TPM_CC_NV_Extend (TPM_CC)(0x00000136) -#endif -#if CC_NV_Write -#define TPM_CC_NV_Write (TPM_CC)(0x00000137) -#endif -#if CC_NV_WriteLock -#define TPM_CC_NV_WriteLock (TPM_CC)(0x00000138) -#endif -#if CC_DictionaryAttackLockReset -#define TPM_CC_DictionaryAttackLockReset (TPM_CC)(0x00000139) -#endif -#if CC_DictionaryAttackParameters -#define TPM_CC_DictionaryAttackParameters (TPM_CC)(0x0000013A) -#endif -#if CC_NV_ChangeAuth -#define TPM_CC_NV_ChangeAuth (TPM_CC)(0x0000013B) -#endif -#if CC_PCR_Event -#define TPM_CC_PCR_Event (TPM_CC)(0x0000013C) -#endif -#if CC_PCR_Reset -#define TPM_CC_PCR_Reset (TPM_CC)(0x0000013D) -#endif -#if CC_SequenceComplete -#define TPM_CC_SequenceComplete (TPM_CC)(0x0000013E) -#endif -#if CC_SetAlgorithmSet -#define TPM_CC_SetAlgorithmSet (TPM_CC)(0x0000013F) -#endif -#if CC_SetCommandCodeAuditStatus -#define TPM_CC_SetCommandCodeAuditStatus (TPM_CC)(0x00000140) -#endif -#if CC_FieldUpgradeData -#define TPM_CC_FieldUpgradeData (TPM_CC)(0x00000141) -#endif -#if CC_IncrementalSelfTest -#define TPM_CC_IncrementalSelfTest (TPM_CC)(0x00000142) -#endif -#if CC_SelfTest -#define TPM_CC_SelfTest (TPM_CC)(0x00000143) -#endif -#if CC_Startup -#define TPM_CC_Startup (TPM_CC)(0x00000144) -#endif -#if CC_Shutdown -#define TPM_CC_Shutdown (TPM_CC)(0x00000145) -#endif -#if CC_StirRandom -#define TPM_CC_StirRandom (TPM_CC)(0x00000146) -#endif -#if CC_ActivateCredential -#define TPM_CC_ActivateCredential (TPM_CC)(0x00000147) -#endif -#if CC_Certify -#define TPM_CC_Certify (TPM_CC)(0x00000148) -#endif -#if CC_PolicyNV -#define TPM_CC_PolicyNV (TPM_CC)(0x00000149) -#endif -#if CC_CertifyCreation -#define TPM_CC_CertifyCreation (TPM_CC)(0x0000014A) -#endif -#if CC_Duplicate -#define TPM_CC_Duplicate (TPM_CC)(0x0000014B) -#endif -#if CC_GetTime -#define TPM_CC_GetTime (TPM_CC)(0x0000014C) -#endif -#if CC_GetSessionAuditDigest -#define TPM_CC_GetSessionAuditDigest (TPM_CC)(0x0000014D) -#endif -#if CC_NV_Read -#define TPM_CC_NV_Read (TPM_CC)(0x0000014E) -#endif -#if CC_NV_ReadLock -#define TPM_CC_NV_ReadLock (TPM_CC)(0x0000014F) -#endif -#if CC_ObjectChangeAuth -#define TPM_CC_ObjectChangeAuth (TPM_CC)(0x00000150) -#endif -#if CC_PolicySecret -#define TPM_CC_PolicySecret (TPM_CC)(0x00000151) -#endif -#if CC_Rewrap -#define TPM_CC_Rewrap (TPM_CC)(0x00000152) -#endif -#if CC_Create -#define TPM_CC_Create (TPM_CC)(0x00000153) -#endif -#if CC_ECDH_ZGen -#define TPM_CC_ECDH_ZGen (TPM_CC)(0x00000154) -#endif -#if CC_HMAC -#define TPM_CC_HMAC (TPM_CC)(0x00000155) -#endif -#if CC_MAC -#define TPM_CC_MAC (TPM_CC)(0x00000155) -#endif -#if CC_Import -#define TPM_CC_Import (TPM_CC)(0x00000156) -#endif -#if CC_Load -#define TPM_CC_Load (TPM_CC)(0x00000157) -#endif -#if CC_Quote -#define TPM_CC_Quote (TPM_CC)(0x00000158) -#endif -#if CC_RSA_Decrypt -#define TPM_CC_RSA_Decrypt (TPM_CC)(0x00000159) -#endif -#if CC_HMAC_Start -#define TPM_CC_HMAC_Start (TPM_CC)(0x0000015B) -#endif -#if CC_MAC_Start -#define TPM_CC_MAC_Start (TPM_CC)(0x0000015B) -#endif -#if CC_SequenceUpdate -#define TPM_CC_SequenceUpdate (TPM_CC)(0x0000015C) -#endif -#if CC_Sign -#define TPM_CC_Sign (TPM_CC)(0x0000015D) -#endif -#if CC_Unseal -#define TPM_CC_Unseal (TPM_CC)(0x0000015E) -#endif -#if CC_PolicySigned -#define TPM_CC_PolicySigned (TPM_CC)(0x00000160) -#endif -#if CC_ContextLoad -#define TPM_CC_ContextLoad (TPM_CC)(0x00000161) -#endif -#if CC_ContextSave -#define TPM_CC_ContextSave (TPM_CC)(0x00000162) -#endif -#if CC_ECDH_KeyGen -#define TPM_CC_ECDH_KeyGen (TPM_CC)(0x00000163) -#endif -#if CC_EncryptDecrypt -#define TPM_CC_EncryptDecrypt (TPM_CC)(0x00000164) -#endif -#if CC_FlushContext -#define TPM_CC_FlushContext (TPM_CC)(0x00000165) -#endif -#if CC_LoadExternal -#define TPM_CC_LoadExternal (TPM_CC)(0x00000167) -#endif -#if CC_MakeCredential -#define TPM_CC_MakeCredential (TPM_CC)(0x00000168) -#endif -#if CC_NV_ReadPublic -#define TPM_CC_NV_ReadPublic (TPM_CC)(0x00000169) -#endif -#if CC_PolicyAuthorize -#define TPM_CC_PolicyAuthorize (TPM_CC)(0x0000016A) -#endif -#if CC_PolicyAuthValue -#define TPM_CC_PolicyAuthValue (TPM_CC)(0x0000016B) -#endif -#if CC_PolicyCommandCode -#define TPM_CC_PolicyCommandCode (TPM_CC)(0x0000016C) -#endif -#if CC_PolicyCounterTimer -#define TPM_CC_PolicyCounterTimer (TPM_CC)(0x0000016D) -#endif -#if CC_PolicyCpHash -#define TPM_CC_PolicyCpHash (TPM_CC)(0x0000016E) -#endif -#if CC_PolicyLocality -#define TPM_CC_PolicyLocality (TPM_CC)(0x0000016F) -#endif -#if CC_PolicyNameHash -#define TPM_CC_PolicyNameHash (TPM_CC)(0x00000170) -#endif -#if CC_PolicyOR -#define TPM_CC_PolicyOR (TPM_CC)(0x00000171) -#endif -#if CC_PolicyTicket -#define TPM_CC_PolicyTicket (TPM_CC)(0x00000172) -#endif -#if CC_ReadPublic -#define TPM_CC_ReadPublic (TPM_CC)(0x00000173) -#endif -#if CC_RSA_Encrypt -#define TPM_CC_RSA_Encrypt (TPM_CC)(0x00000174) -#endif -#if CC_StartAuthSession -#define TPM_CC_StartAuthSession (TPM_CC)(0x00000176) -#endif -#if CC_VerifySignature -#define TPM_CC_VerifySignature (TPM_CC)(0x00000177) -#endif -#if CC_ECC_Parameters -#define TPM_CC_ECC_Parameters (TPM_CC)(0x00000178) -#endif -#if CC_FirmwareRead -#define TPM_CC_FirmwareRead (TPM_CC)(0x00000179) -#endif -#if CC_GetCapability -#define TPM_CC_GetCapability (TPM_CC)(0x0000017A) -#endif -#if CC_GetRandom -#define TPM_CC_GetRandom (TPM_CC)(0x0000017B) -#endif -#if CC_GetTestResult -#define TPM_CC_GetTestResult (TPM_CC)(0x0000017C) -#endif -#if CC_Hash -#define TPM_CC_Hash (TPM_CC)(0x0000017D) -#endif -#if CC_PCR_Read -#define TPM_CC_PCR_Read (TPM_CC)(0x0000017E) -#endif -#if CC_PolicyPCR -#define TPM_CC_PolicyPCR (TPM_CC)(0x0000017F) -#endif -#if CC_PolicyRestart -#define TPM_CC_PolicyRestart (TPM_CC)(0x00000180) -#endif -#if CC_ReadClock -#define TPM_CC_ReadClock (TPM_CC)(0x00000181) -#endif -#if CC_PCR_Extend -#define TPM_CC_PCR_Extend (TPM_CC)(0x00000182) -#endif -#if CC_PCR_SetAuthValue -#define TPM_CC_PCR_SetAuthValue (TPM_CC)(0x00000183) -#endif -#if CC_NV_Certify -#define TPM_CC_NV_Certify (TPM_CC)(0x00000184) -#endif -#if CC_EventSequenceComplete -#define TPM_CC_EventSequenceComplete (TPM_CC)(0x00000185) -#endif -#if CC_HashSequenceStart -#define TPM_CC_HashSequenceStart (TPM_CC)(0x00000186) -#endif -#if CC_PolicyPhysicalPresence -#define TPM_CC_PolicyPhysicalPresence (TPM_CC)(0x00000187) -#endif -#if CC_PolicyDuplicationSelect -#define TPM_CC_PolicyDuplicationSelect (TPM_CC)(0x00000188) -#endif -#if CC_PolicyGetDigest -#define TPM_CC_PolicyGetDigest (TPM_CC)(0x00000189) -#endif -#if CC_TestParms -#define TPM_CC_TestParms (TPM_CC)(0x0000018A) -#endif -#if CC_Commit -#define TPM_CC_Commit (TPM_CC)(0x0000018B) -#endif -#if CC_PolicyPassword -#define TPM_CC_PolicyPassword (TPM_CC)(0x0000018C) -#endif -#if CC_ZGen_2Phase -#define TPM_CC_ZGen_2Phase (TPM_CC)(0x0000018D) -#endif -#if CC_EC_Ephemeral -#define TPM_CC_EC_Ephemeral (TPM_CC)(0x0000018E) -#endif -#if CC_PolicyNvWritten -#define TPM_CC_PolicyNvWritten (TPM_CC)(0x0000018F) -#endif -#if CC_PolicyTemplate -#define TPM_CC_PolicyTemplate (TPM_CC)(0x00000190) -#endif -#if CC_CreateLoaded -#define TPM_CC_CreateLoaded (TPM_CC)(0x00000191) -#endif -#if CC_PolicyAuthorizeNV -#define TPM_CC_PolicyAuthorizeNV (TPM_CC)(0x00000192) -#endif -#if CC_EncryptDecrypt2 -#define TPM_CC_EncryptDecrypt2 (TPM_CC)(0x00000193) -#endif -#if CC_AC_GetCapability -#define TPM_CC_AC_GetCapability (TPM_CC)(0x00000194) -#endif -#if CC_AC_Send -#define TPM_CC_AC_Send (TPM_CC)(0x00000195) -#endif -#if CC_Policy_AC_SendSelect -#define TPM_CC_Policy_AC_SendSelect (TPM_CC)(0x00000196) -#endif -#if CC_CertifyX509 -#define TPM_CC_CertifyX509 (TPM_CC)(0x00000197) -#endif -#define CC_VEND 0x20000000 -#if CC_Vendor_TCG_Test -#define TPM_CC_Vendor_TCG_Test (TPM_CC)(0x20000000) -#endif - -// Additional values for benefit of code -#define TPM_CC_FIRST 0x0000011F -#define TPM_CC_LAST 0x00000197 - - -#if COMPRESSED_LISTS -#define ADD_FILL 0 -#else -#define ADD_FILL 1 -#endif - -// Size the array of library commands based on whether or not -// the array is packed (only defined commands) or dense -// (having entries for unimplemented commands) -#define LIBRARY_COMMAND_ARRAY_SIZE (0 \ - + (ADD_FILL || CC_NV_UndefineSpaceSpecial) /* 0x0000011F */ \ - + (ADD_FILL || CC_EvictControl) /* 0x00000120 */ \ - + (ADD_FILL || CC_HierarchyControl) /* 0x00000121 */ \ - + (ADD_FILL || CC_NV_UndefineSpace) /* 0x00000122 */ \ - + ADD_FILL /* 0x00000123 */ \ - + (ADD_FILL || CC_ChangeEPS) /* 0x00000124 */ \ - + (ADD_FILL || CC_ChangePPS) /* 0x00000125 */ \ - + (ADD_FILL || CC_Clear) /* 0x00000126 */ \ - + (ADD_FILL || CC_ClearControl) /* 0x00000127 */ \ - + (ADD_FILL || CC_ClockSet) /* 0x00000128 */ \ - + (ADD_FILL || CC_HierarchyChangeAuth) /* 0x00000129 */ \ - + (ADD_FILL || CC_NV_DefineSpace) /* 0x0000012A */ \ - + (ADD_FILL || CC_PCR_Allocate) /* 0x0000012B */ \ - + (ADD_FILL || CC_PCR_SetAuthPolicy) /* 0x0000012C */ \ - + (ADD_FILL || CC_PP_Commands) /* 0x0000012D */ \ - + (ADD_FILL || CC_SetPrimaryPolicy) /* 0x0000012E */ \ - + (ADD_FILL || CC_FieldUpgradeStart) /* 0x0000012F */ \ - + (ADD_FILL || CC_ClockRateAdjust) /* 0x00000130 */ \ - + (ADD_FILL || CC_CreatePrimary) /* 0x00000131 */ \ - + (ADD_FILL || CC_NV_GlobalWriteLock) /* 0x00000132 */ \ - + (ADD_FILL || CC_GetCommandAuditDigest) /* 0x00000133 */ \ - + (ADD_FILL || CC_NV_Increment) /* 0x00000134 */ \ - + (ADD_FILL || CC_NV_SetBits) /* 0x00000135 */ \ - + (ADD_FILL || CC_NV_Extend) /* 0x00000136 */ \ - + (ADD_FILL || CC_NV_Write) /* 0x00000137 */ \ - + (ADD_FILL || CC_NV_WriteLock) /* 0x00000138 */ \ - + (ADD_FILL || CC_DictionaryAttackLockReset) /* 0x00000139 */ \ - + (ADD_FILL || CC_DictionaryAttackParameters) /* 0x0000013A */ \ - + (ADD_FILL || CC_NV_ChangeAuth) /* 0x0000013B */ \ - + (ADD_FILL || CC_PCR_Event) /* 0x0000013C */ \ - + (ADD_FILL || CC_PCR_Reset) /* 0x0000013D */ \ - + (ADD_FILL || CC_SequenceComplete) /* 0x0000013E */ \ - + (ADD_FILL || CC_SetAlgorithmSet) /* 0x0000013F */ \ - + (ADD_FILL || CC_SetCommandCodeAuditStatus) /* 0x00000140 */ \ - + (ADD_FILL || CC_FieldUpgradeData) /* 0x00000141 */ \ - + (ADD_FILL || CC_IncrementalSelfTest) /* 0x00000142 */ \ - + (ADD_FILL || CC_SelfTest) /* 0x00000143 */ \ - + (ADD_FILL || CC_Startup) /* 0x00000144 */ \ - + (ADD_FILL || CC_Shutdown) /* 0x00000145 */ \ - + (ADD_FILL || CC_StirRandom) /* 0x00000146 */ \ - + (ADD_FILL || CC_ActivateCredential) /* 0x00000147 */ \ - + (ADD_FILL || CC_Certify) /* 0x00000148 */ \ - + (ADD_FILL || CC_PolicyNV) /* 0x00000149 */ \ - + (ADD_FILL || CC_CertifyCreation) /* 0x0000014A */ \ - + (ADD_FILL || CC_Duplicate) /* 0x0000014B */ \ - + (ADD_FILL || CC_GetTime) /* 0x0000014C */ \ - + (ADD_FILL || CC_GetSessionAuditDigest) /* 0x0000014D */ \ - + (ADD_FILL || CC_NV_Read) /* 0x0000014E */ \ - + (ADD_FILL || CC_NV_ReadLock) /* 0x0000014F */ \ - + (ADD_FILL || CC_ObjectChangeAuth) /* 0x00000150 */ \ - + (ADD_FILL || CC_PolicySecret) /* 0x00000151 */ \ - + (ADD_FILL || CC_Rewrap) /* 0x00000152 */ \ - + (ADD_FILL || CC_Create) /* 0x00000153 */ \ - + (ADD_FILL || CC_ECDH_ZGen) /* 0x00000154 */ \ - + (ADD_FILL || CC_HMAC || CC_MAC) /* 0x00000155 */ \ - + (ADD_FILL || CC_Import) /* 0x00000156 */ \ - + (ADD_FILL || CC_Load) /* 0x00000157 */ \ - + (ADD_FILL || CC_Quote) /* 0x00000158 */ \ - + (ADD_FILL || CC_RSA_Decrypt) /* 0x00000159 */ \ - + ADD_FILL /* 0x0000015A */ \ - + (ADD_FILL || CC_HMAC_Start || CC_MAC_Start) /* 0x0000015B */ \ - + (ADD_FILL || CC_SequenceUpdate) /* 0x0000015C */ \ - + (ADD_FILL || CC_Sign) /* 0x0000015D */ \ - + (ADD_FILL || CC_Unseal) /* 0x0000015E */ \ - + ADD_FILL /* 0x0000015F */ \ - + (ADD_FILL || CC_PolicySigned) /* 0x00000160 */ \ - + (ADD_FILL || CC_ContextLoad) /* 0x00000161 */ \ - + (ADD_FILL || CC_ContextSave) /* 0x00000162 */ \ - + (ADD_FILL || CC_ECDH_KeyGen) /* 0x00000163 */ \ - + (ADD_FILL || CC_EncryptDecrypt) /* 0x00000164 */ \ - + (ADD_FILL || CC_FlushContext) /* 0x00000165 */ \ - + ADD_FILL /* 0x00000166 */ \ - + (ADD_FILL || CC_LoadExternal) /* 0x00000167 */ \ - + (ADD_FILL || CC_MakeCredential) /* 0x00000168 */ \ - + (ADD_FILL || CC_NV_ReadPublic) /* 0x00000169 */ \ - + (ADD_FILL || CC_PolicyAuthorize) /* 0x0000016A */ \ - + (ADD_FILL || CC_PolicyAuthValue) /* 0x0000016B */ \ - + (ADD_FILL || CC_PolicyCommandCode) /* 0x0000016C */ \ - + (ADD_FILL || CC_PolicyCounterTimer) /* 0x0000016D */ \ - + (ADD_FILL || CC_PolicyCpHash) /* 0x0000016E */ \ - + (ADD_FILL || CC_PolicyLocality) /* 0x0000016F */ \ - + (ADD_FILL || CC_PolicyNameHash) /* 0x00000170 */ \ - + (ADD_FILL || CC_PolicyOR) /* 0x00000171 */ \ - + (ADD_FILL || CC_PolicyTicket) /* 0x00000172 */ \ - + (ADD_FILL || CC_ReadPublic) /* 0x00000173 */ \ - + (ADD_FILL || CC_RSA_Encrypt) /* 0x00000174 */ \ - + ADD_FILL /* 0x00000175 */ \ - + (ADD_FILL || CC_StartAuthSession) /* 0x00000176 */ \ - + (ADD_FILL || CC_VerifySignature) /* 0x00000177 */ \ - + (ADD_FILL || CC_ECC_Parameters) /* 0x00000178 */ \ - + (ADD_FILL || CC_FirmwareRead) /* 0x00000179 */ \ - + (ADD_FILL || CC_GetCapability) /* 0x0000017A */ \ - + (ADD_FILL || CC_GetRandom) /* 0x0000017B */ \ - + (ADD_FILL || CC_GetTestResult) /* 0x0000017C */ \ - + (ADD_FILL || CC_Hash) /* 0x0000017D */ \ - + (ADD_FILL || CC_PCR_Read) /* 0x0000017E */ \ - + (ADD_FILL || CC_PolicyPCR) /* 0x0000017F */ \ - + (ADD_FILL || CC_PolicyRestart) /* 0x00000180 */ \ - + (ADD_FILL || CC_ReadClock) /* 0x00000181 */ \ - + (ADD_FILL || CC_PCR_Extend) /* 0x00000182 */ \ - + (ADD_FILL || CC_PCR_SetAuthValue) /* 0x00000183 */ \ - + (ADD_FILL || CC_NV_Certify) /* 0x00000184 */ \ - + (ADD_FILL || CC_EventSequenceComplete) /* 0x00000185 */ \ - + (ADD_FILL || CC_HashSequenceStart) /* 0x00000186 */ \ - + (ADD_FILL || CC_PolicyPhysicalPresence) /* 0x00000187 */ \ - + (ADD_FILL || CC_PolicyDuplicationSelect) /* 0x00000188 */ \ - + (ADD_FILL || CC_PolicyGetDigest) /* 0x00000189 */ \ - + (ADD_FILL || CC_TestParms) /* 0x0000018A */ \ - + (ADD_FILL || CC_Commit) /* 0x0000018B */ \ - + (ADD_FILL || CC_PolicyPassword) /* 0x0000018C */ \ - + (ADD_FILL || CC_ZGen_2Phase) /* 0x0000018D */ \ - + (ADD_FILL || CC_EC_Ephemeral) /* 0x0000018E */ \ - + (ADD_FILL || CC_PolicyNvWritten) /* 0x0000018F */ \ - + (ADD_FILL || CC_PolicyTemplate) /* 0x00000190 */ \ - + (ADD_FILL || CC_CreateLoaded) /* 0x00000191 */ \ - + (ADD_FILL || CC_PolicyAuthorizeNV) /* 0x00000192 */ \ - + (ADD_FILL || CC_EncryptDecrypt2) /* 0x00000193 */ \ - + (ADD_FILL || CC_AC_GetCapability) /* 0x00000194 */ \ - + (ADD_FILL || CC_AC_Send) /* 0x00000195 */ \ - + (ADD_FILL || CC_Policy_AC_SendSelect) /* 0x00000196 */ \ - + (ADD_FILL || CC_CertifyX509) /* 0x00000197 */ \ - ) - -#define VENDOR_COMMAND_ARRAY_SIZE (0 + CC_Vendor_TCG_Test) - -#define COMMAND_COUNT (LIBRARY_COMMAND_ARRAY_SIZE + VENDOR_COMMAND_ARRAY_SIZE) - -#define HASH_COUNT \ - (ALG_SHA1 + ALG_SHA256 + ALG_SHA384 + ALG_SHA512 + ALG_SM3_256) - -#define MAX_HASH_BLOCK_SIZE \ - (MAX(ALG_SHA1 * SHA1_BLOCK_SIZE, \ - MAX(ALG_SHA256 * SHA256_BLOCK_SIZE, \ - MAX(ALG_SHA384 * SHA384_BLOCK_SIZE, \ - MAX(ALG_SHA512 * SHA512_BLOCK_SIZE, \ - MAX(ALG_SM3_256 * SM3_256_BLOCK_SIZE, \ - 0)))))) - -#define MAX_DIGEST_SIZE \ - (MAX(ALG_SHA1 * SHA1_DIGEST_SIZE, \ - MAX(ALG_SHA256 * SHA256_DIGEST_SIZE, \ - MAX(ALG_SHA384 * SHA384_DIGEST_SIZE, \ - MAX(ALG_SHA512 * SHA512_DIGEST_SIZE, \ - MAX(ALG_SM3_256 * SM3_256_DIGEST_SIZE, \ - 0)))))) - - -#if MAX_DIGEST_SIZE == 0 || MAX_HASH_BLOCK_SIZE == 0 -#error "Hash data not valid" -#endif - -// Define the 2B structure that would hold any hash block -TPM2B_TYPE(MAX_HASH_BLOCK, MAX_HASH_BLOCK_SIZE); - -// Following typedef is for some old code -typedef TPM2B_MAX_HASH_BLOCK TPM2B_HASH_BLOCK; - -/* Additional symmetric constants */ -#define MAX_SYM_KEY_BITS \ - (MAX(AES_MAX_KEY_SIZE_BITS, MAX(CAMELLIA_MAX_KEY_SIZE_BITS, \ - MAX(SM4_MAX_KEY_SIZE_BITS, MAX(TDES_MAX_KEY_SIZE_BITS, \ - 0))))) - -#define MAX_SYM_KEY_BYTES ((MAX_SYM_KEY_BITS + 7) / 8) - -#define MAX_SYM_BLOCK_SIZE \ - (MAX(AES_MAX_BLOCK_SIZE, MAX(CAMELLIA_MAX_BLOCK_SIZE, \ - MAX(SM4_MAX_BLOCK_SIZE, MAX(TDES_MAX_BLOCK_SIZE, \ - 0))))) - -#if MAX_SYM_KEY_BITS == 0 || MAX_SYM_BLOCK_SIZE == 0 -# error Bad size for MAX_SYM_KEY_BITS or MAX_SYM_BLOCK -#endif - - -#endif // _IMPLEMENTATION_H_ diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/LibSupport.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/LibSupport.h index ea771c559..96473928e 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/LibSupport.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/LibSupport.h @@ -33,21 +33,30 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ // This header file is used to select the library code that gets included in the -// TPM built +// TPM build. #ifndef _LIB_SUPPORT_H_ #define _LIB_SUPPORT_H_ +//********************* +#ifndef RADIX_BITS +# if defined(__x86_64__) || defined(__x86_64) \ + || defined(__amd64__) || defined(__amd64) || defined(_WIN64) || defined(_M_X64) \ + || defined(_M_ARM64) || defined(__aarch64__) +# define RADIX_BITS 64 +# elif defined(__i386__) || defined(__i386) || defined(i386) \ + || defined(_WIN32) || defined(_M_IX86) \ + || defined(_M_ARM) || defined(__arm__) || defined(__thumb__) +# define RADIX_BITS 32 +# else +# error Unable to determine RADIX_BITS from compiler environment +# endif +#endif // RADIX_BITS + // These macros use the selected libraries to the proper include files. -#define LIB_JOIN(x,y) x##y -#define LIB_CONCAT(x,y) LIB_JOIN(x, y) #define LIB_QUOTE(_STRING_) #_STRING_ #define LIB_INCLUDE2(_LIB_, _TYPE_) LIB_QUOTE(_LIB_/TpmTo##_LIB_##_TYPE_.h) #define LIB_INCLUDE(_LIB_, _TYPE_) LIB_INCLUDE2(_LIB_, _TYPE_) -#define SYM_LIBRARY LIB_CONCAT(SYM_LIB_, SYM_LIB) -#define HASH_LIBRARY(_LIB_) LIB_CONCAT(HASH_LIB_, HASH_LIB) -#define MATH_LIBRARY(_LIB_) LIB_CONCAT(MATH_LIB_, MATH_LIB) - // Include the options for hashing and symmetric. Defer the load of the math package // Until the bignum parameters are defined. diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/LtcSettings.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/LtcSettings.h index e4757373e..0e31d344d 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/LtcSettings.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/LtcSettings.h @@ -41,10 +41,12 @@ #ifndef _LTC_SETTINGS_H_ #define _LTC_SETTINGS_H_ -#ifdef TPM_ALG_AES +#if (defined HASH_LIB_LTC) || (defined SYM_LIB_LTC) || (defined MATH_LIB_LTC) + +#if ALG_AES # define LTC_RIJNDAEL #endif -#ifdef TPM_ALG_TDES +#if ALG_TDES # define LTC_DES #endif @@ -77,4 +79,6 @@ _REDUCE_WARNING_LEVEL_(0) #include "tomcrypt.h" _NORMAL_WARNING_LEVEL_ +#endif + #endif // diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/TpmToLtcHash.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/TpmToLtcHash.h index 7b16fc9fb..6f429852c 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/TpmToLtcHash.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/TpmToLtcHash.h @@ -37,13 +37,13 @@ // This header defines the interface between the hashing code and the LIbTomCrypt // hash functions. -#ifndef _TPM_TO_LTC_HASH_H_ -#define _TPM_TO_LTC_HASH_H_ +#ifndef HASH_LIB_DEFINED +#define HASH_LIB_DEFINED #define HASH_LIB_LTC // Avoid pulling in the MPA math if not doing asymmetric with LTC -#if MATH_LIB != LTC +#if !(defined MATH_LIB_LTC) # define LTC_NO_ASYMMETRIC #endif @@ -59,6 +59,9 @@ #define tpmHashStateSHA512_t struct sha512_state #define tpmHashStateSHA384_t struct sha512_state +// The following defines are only needed by CryptHash.c +#ifdef _CRYPT_HASH_C_ + // Define the interface between CryptHash.c to the functions provided by the // library. For each method, define the calling parameters of the method and then // define how the method is invoked in CryptHash.c. @@ -158,13 +161,12 @@ #define tpmHashStateExport_SHA512 memcpy #define tpmHashStateImport_SHA512 memcpy +#endif // _CRYPT_HASH_C_ + // No special processing to initialize the LTC hash library #define LibHashInit() // No special processing at the end of the simulation (i.e., no statistics to print) #define HashLibSimulationEnd() - -#endif // HASH_LIB == LTC - -#endif // +#endif // HASH_LIB_DEFINED diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/TpmToLtcMath.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/TpmToLtcMath.h index f3a2542f2..93ede548d 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/TpmToLtcMath.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/TpmToLtcMath.h @@ -37,8 +37,8 @@ // This file contains the structure definitions used for linking from the TPM // code to the MPA and LTC math libraries. -#ifndef _TPM_TO_LTC_MATH_H_ -#define _TPM_TO_LTC_MATH_H_ +#ifndef MATH_LIB_DEFINED +#define MATH_LIB_DEFINED #define MATH_LIB_LTC @@ -51,11 +51,11 @@ _NORMAL_WARNING_LEVEL_ #if RADIX_BITS != 32 -#error "The mpa library used with LibTopCrypt only works for 32-bit words" +#error "The mpa library used with LibTomCrypt only works for 32-bit words" #endif // These macros handle entering and leaving a scope -// from which an MPA or LibTopCrypt function may be called. +// from which an MPA or LibTomCrypt function may be called. // Many of these functions require a scratch pool from which // they will allocate scratch variables (rather than using their // own stack). @@ -86,4 +86,4 @@ typedef bnCurve_t *bigCurve; // This definition would change if there were something to report #define MathLibSimulationEnd() -#endif +#endif // MATH_LIB_DEFINED diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/TpmToLtcSym.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/TpmToLtcSym.h index c1e518038..68de231a8 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/TpmToLtcSym.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ltc/TpmToLtcSym.h @@ -37,13 +37,13 @@ // // This header file is used to "splice" the TPM to the LTC symmetric cipher code. -#ifndef _TPM_TO_LTC_SYM_H_ -#define _TPM_TO_LTC_SYM_H_ +#ifndef SYM_LIB_DEFINED +#define SYM_LIB_DEFINED #define SYM_LIB_LTC // Avoid pulling in the MPA math if not doing asymmetric with LTC -#if MATH_LIB != LTC +#if !(defined MATH_LIB_LTC) # define LTC_NO_ASYMMETRIC #endif @@ -53,11 +53,11 @@ //******** Linking to the TomCrypt AES code ********************* //*************************************************************** -#ifdef TPM_ALG_SM4 +#if ALG_SM4 #error "SM4 is not available" #endif -#ifdef TPM_ALG_CAMELLIA +#if ALG_CAMELLIA #error "Camellia is not available" #endif @@ -70,21 +70,21 @@ typedef void(*TpmCryptSetSymKeyCall_t)( ); // Macro to put the parameters in the order required by the library -#define SWIZZLE(keySchedule, in, out) \ +#define SWIZZLE(keySchedule, in, out) \ (const void *)(in), (void *)(out), (void *)(keySchedule) // Macros to set up the encryption/decryption key schedules // // AES: -# define TpmCryptSetEncryptKeyAES(key, keySizeInBits, schedule) \ +# define TpmCryptSetEncryptKeyAES(key, keySizeInBits, schedule) \ aes_setup((key), BITS_TO_BYTES(keySizeInBits), 0, (symmetric_key *)(schedule)) -# define TpmCryptSetDecryptKeyAES(key, keySizeInBits, schedule) \ +# define TpmCryptSetDecryptKeyAES(key, keySizeInBits, schedule) \ aes_setup((key), BITS_TO_BYTES(keySizeInBits), 0, (symmetric_key *)(schedule)) // TDES: -# define TpmCryptSetEncryptKeyTDES(key, keySizeInBits, schedule) \ +# define TpmCryptSetEncryptKeyTDES(key, keySizeInBits, schedule) \ TDES_setup((key), (keySizeInBits), (symmetric_key *)(schedule)) -# define TpmCryptSetDecryptKeyTDES(key, keySizeInBits, schedule) \ +# define TpmCryptSetDecryptKeyTDES(key, keySizeInBits, schedule) \ TDES_setup((key), (keySizeInBits), (symmetric_key *)(schedule)) @@ -107,6 +107,4 @@ typedef union tpmCryptKeySchedule_t tpmCryptKeySchedule_t; #define SymLibSimulationEnd() -#endif // SIM_LIB == LTC - -#endif // _TPM_TO_LTC_SYM_H_ +#endif // SYM_LIB_DEFINED diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/NV.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/NV.h index 69170234a..88564f73c 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/NV.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/NV.h @@ -108,7 +108,7 @@ typedef struct { // Defines the end-of-list marker for NV. The list terminator is // a UINT32 of zero, followed by the current value of s_maxCounter which is a // 64-bit value. The structure is defined as an array of 3 UINT32 values so that -// there is no padding between the UINT32 list end marker and the UIT64m maxCounter +// there is no padding between the UINT32 list end marker and the UINT64 maxCounter // value. typedef UINT32 NV_LIST_TERMINATOR[3]; diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/OIDs.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/OIDs.h index 48ac1791d..312ae69ff 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/OIDs.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/OIDs.h @@ -44,82 +44,47 @@ #define MAKE_OID(NAME) \ EXTERN const BYTE OID##NAME[] INITIALIZER({OID##NAME##_VALUE}) -//** Global X509 OIDs -// This is the DER-encoded value for the Key Usage OID (2.5.29.15). This is the -// full OID, not just the numeric value -#define OID_KEY_USAGE_EXTENSTION_VALUE 0x06, 0x03, 0x55, 0x1D, 0x0F -MAKE_OID(_KEY_USAGE_EXTENSTION); - -// This is the DER-encoded value for the TCG-defined TPMA_OBJECT OID -// (2.23.133.10.1.1.1) -#define OID_TCG_TPMA_OBJECT_VALUE 0x06, 0x07, 0x67, 0x81, 0x05, 0x0a, 0x01, \ - 0x01, 0x01 -MAKE_OID(_TCG_TPMA_OBJECT); // These macros allow OIDs to be defined (or not) depending on whether the associated // hash algorithm is implemented. // NOTE: When one of these macros is used, the NAME needs '_" on each side. The // exception is when the macro is used for the hash OID when only a single '_' is // used. -#ifndef ALG_SHA1 -# define ALG_SHA1 NO -#endif #if ALG_SHA1 #define SHA1_OID(NAME) MAKE_OID(NAME##SHA1) #else #define SHA1_OID(NAME) #endif -#ifndef ALG_SHA256 -# define ALG_SHA256 NO -#endif #if ALG_SHA256 #define SHA256_OID(NAME) MAKE_OID(NAME##SHA256) #else #define SHA256_OID(NAME) #endif -#ifndef ALG_SHA384 -# define ALG_SHA384 NO -#endif #if ALG_SHA384 #define SHA384_OID(NAME) MAKE_OID(NAME##SHA384) #else #define SHA#84_OID(NAME) #endif -#ifndef ALG_SHA512 -# define ALG_SHA512 NO -#endif #if ALG_SHA512 #define SHA512_OID(NAME) MAKE_OID(NAME##SHA512) #else #define SHA512_OID(NAME) #endif -#ifndef ALG_SM3_256 -# define ALG_SM3_256 NO -#endif #if ALG_SM3_256 #define SM3_256_OID(NAME) MAKE_OID(NAME##SM2_256) #else #define SM3_256_OID(NAME) #endif -#ifndef ALG_SHA3_256 -# define ALG_SHA3_256 NO -#endif #if ALG_SHA3_256 #define SHA3_256_OID(NAME) MAKE_OID(NAME##SHA3_256) #else #define SHA3_256_OID(NAME) #endif -#ifndef ALG_SHA3_384 -# define ALG_SHA3_384 NO -#endif #if ALG_SHA3_384 #define SHA3_384_OID(NAME) MAKE_OID(NAME##SHA3_384) #else #define SHA3_384_OID(NAME) #endif -#ifndef ALG_SHA3_512 -# define ALG_SHA3_512 NO -#endif #if ALG_SHA3_512 #define SSHA3_512_OID(NAME) MAKE_OID(NAME##SHA3_512) #else diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ossl/TpmToOsslHash.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ossl/TpmToOsslHash.h index ded23fbf5..56f414464 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ossl/TpmToOsslHash.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ossl/TpmToOsslHash.h @@ -64,6 +64,13 @@ # error "The version of OpenSSL used by this code does not support SM3" #endif +// The defines below are only needed when compiling CryptHash.c or CryptSmac.c. +// This isolation is primarily to avoid name space collision. However, if there +// is a real collision, it will likely show up when the linker tries to put things +// together. + +#ifdef _CRYPT_HASH_C_ + typedef BYTE *PBYTE; typedef const BYTE *PCBYTE; @@ -164,6 +171,8 @@ typedef const BYTE *PCBYTE; #define tpmHashStateExport_SHA512 memcpy #define tpmHashStateImport_SHA512 memcpy +#endif // _CRYPT_HASH_C_ + #define LibHashInit() // This definition would change if there were something to report #define HashLibSimulationEnd() diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ossl/TpmToOsslMath.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ossl/TpmToOsslMath.h index 2bd3d5e06..b3123706a 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ossl/TpmToOsslMath.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Ossl/TpmToOsslMath.h @@ -33,7 +33,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ //** Introduction -// This file contains the structure definitions used for ECC in the LibTopCrypt +// This file contains the structure definitions used for ECC in the LibTomCrypt // version of the code. These definitions would change, based on the library. // The ECC-related structures that cross the TPM interface are defined // in TpmTypes.h diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/PRNG_TestVectors.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/PRNG_TestVectors.h index 4995db129..96c7f5b48 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/PRNG_TestVectors.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/PRNG_TestVectors.h @@ -64,7 +64,7 @@ ReturnedBits = 946f5182 d54510b9 461248f5 71ca06c9 */ -// Entropy is the size of a the state. The state is the size of the key +// Entropy is the size of the state. The state is the size of the key // plus the IV. The IV is a block. If Key = 256 and Block = 128 then State = 384 # define DRBG_TEST_INITIATE_ENTROPY \ 0x0d, 0x15, 0xaa, 0x80, 0xb1, 0x6c, 0x3a, 0x10, \ diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/SupportLibraryFunctionPrototypes_fp.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/SupportLibraryFunctionPrototypes_fp.h index 8ca4a1f35..3cdd2c816 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/SupportLibraryFunctionPrototypes_fp.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/SupportLibraryFunctionPrototypes_fp.h @@ -34,7 +34,7 @@ */ //** Introduction // This file contains the function prototypes for the functions that need to be -// present in the selected match library. For each function listed, there should +// present in the selected math library. For each function listed, there should // be a small stub function. That stub provides the interface between the TPM // code and the support library. In most cases, the stub function will only need // to do a format conversion between the TPM big number and the support library diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/SymmetricTest.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/SymmetricTest.h index fbdada71a..bf052152b 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/SymmetricTest.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/SymmetricTest.h @@ -39,7 +39,7 @@ // organization was chosen so that the program that is used to generate the test // vector values does not have to also re-generate this data. #ifndef SELF_TEST_DATA -#error "This file many only be included in AlgorithmTests.c" +#error "This file may only be included in AlgorithmTests.c" #endif #ifndef _SYMMETRIC_TEST_H diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmASN1.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmASN1.h index 2069343dc..eafeed4a7 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmASN1.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmASN1.h @@ -80,7 +80,6 @@ #define ASN1_CONSTRUCTED_SEQUENCE (ASN1_SEQUENCE + ASN1_CONSTRUCTED) - #define MAX_DEPTH 10 // maximum push depth for marshaling context. //** Macros @@ -99,13 +98,12 @@ //*** Marshaling Macros // Marshaling works in reverse order. The offset is set to the top of the buffer and, -// as the buffer is filled, offset counts down to zero. When the full thing is encoded -// it can be moved to the top of the buffer. This happens when the last context is -// closed (when the +// as the buffer is filled, 'offset' counts down to zero. When the full thing is +// encoded it can be moved to the top of the buffer. This happens when the last +// context is closed. #define CHECK_SPACE(context, length) VERIFY(context->offset > length) - //** Structures typedef struct ASN1UnmarshalContext { @@ -126,5 +124,4 @@ typedef struct ASN1MarshalContext { INT16 ends[MAX_DEPTH]; } ASN1MarshalContext; - #endif // _TPMASN1_H_ diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmAlgorithmDefines.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmAlgorithmDefines.h index 5a3b6a648..5954a8447 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmAlgorithmDefines.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmAlgorithmDefines.h @@ -43,18 +43,6 @@ // Table 2:3 - Definition of Base Types // Base Types are in BaseTypes.h - -// Table 2:4 - Defines for Logic Values - - -// Table 0:1 - Defines for Processor Values - - -// Table 0:3 - Defines for Key Size Constants - - -// Table 0:4 - Defines for Implemented Curves - #define ECC_CURVES \ {TPM_ECC_BN_P256, TPM_ECC_BN_P638, TPM_ECC_NIST_P192, \ TPM_ECC_NIST_P224, TPM_ECC_NIST_P256, TPM_ECC_NIST_P384, \ @@ -78,118 +66,6 @@ #define PLATFORM_YEAR TPM_SPEC_YEAR #define PLATFORM_DAY_OF_YEAR TPM_SPEC_DAY_OF_YEAR - -// Table 0:7 - Defines for Implementation Values - - -// Table 0:2 - Defines for Implemented Algorithms - - -// Table 1:2 - Definition of TPM_ALG_ID Constants -typedef UINT16 TPM_ALG_ID; -#define TYPE_OF_TPM_ALG_ID UINT16 -#define ALG_ERROR_VALUE 0x0000 -#define TPM_ALG_ERROR (TPM_ALG_ID)(ALG_ERROR_VALUE) -#define ALG_RSA_VALUE 0x0001 -#define TPM_ALG_RSA (TPM_ALG_ID)(ALG_RSA_VALUE) -#define ALG_TDES_VALUE 0x0003 -#define TPM_ALG_TDES (TPM_ALG_ID)(ALG_TDES_VALUE) -#define ALG_SHA_VALUE 0x0004 -#define TPM_ALG_SHA (TPM_ALG_ID)(ALG_SHA_VALUE) -#define ALG_SHA1_VALUE 0x0004 -#define TPM_ALG_SHA1 (TPM_ALG_ID)(ALG_SHA1_VALUE) -#define ALG_HMAC_VALUE 0x0005 -#define TPM_ALG_HMAC (TPM_ALG_ID)(ALG_HMAC_VALUE) -#define ALG_AES_VALUE 0x0006 -#define TPM_ALG_AES (TPM_ALG_ID)(ALG_AES_VALUE) -#define ALG_MGF1_VALUE 0x0007 -#define TPM_ALG_MGF1 (TPM_ALG_ID)(ALG_MGF1_VALUE) -#define ALG_KEYEDHASH_VALUE 0x0008 -#define TPM_ALG_KEYEDHASH (TPM_ALG_ID)(ALG_KEYEDHASH_VALUE) -#define ALG_XOR_VALUE 0x000A -#define TPM_ALG_XOR (TPM_ALG_ID)(ALG_XOR_VALUE) -#define ALG_SHA256_VALUE 0x000B -#define TPM_ALG_SHA256 (TPM_ALG_ID)(ALG_SHA256_VALUE) -#define ALG_SHA384_VALUE 0x000C -#define TPM_ALG_SHA384 (TPM_ALG_ID)(ALG_SHA384_VALUE) -#define ALG_SHA512_VALUE 0x000D -#define TPM_ALG_SHA512 (TPM_ALG_ID)(ALG_SHA512_VALUE) -#define ALG_NULL_VALUE 0x0010 -#define TPM_ALG_NULL (TPM_ALG_ID)(ALG_NULL_VALUE) -#define ALG_SM3_256_VALUE 0x0012 -#define TPM_ALG_SM3_256 (TPM_ALG_ID)(ALG_SM3_256_VALUE) -#define ALG_SM4_VALUE 0x0013 -#define TPM_ALG_SM4 (TPM_ALG_ID)(ALG_SM4_VALUE) -#define ALG_RSASSA_VALUE 0x0014 -#define TPM_ALG_RSASSA (TPM_ALG_ID)(ALG_RSASSA_VALUE) -#define ALG_RSAES_VALUE 0x0015 -#define TPM_ALG_RSAES (TPM_ALG_ID)(ALG_RSAES_VALUE) -#define ALG_RSAPSS_VALUE 0x0016 -#define TPM_ALG_RSAPSS (TPM_ALG_ID)(ALG_RSAPSS_VALUE) -#define ALG_OAEP_VALUE 0x0017 -#define TPM_ALG_OAEP (TPM_ALG_ID)(ALG_OAEP_VALUE) -#define ALG_ECDSA_VALUE 0x0018 -#define TPM_ALG_ECDSA (TPM_ALG_ID)(ALG_ECDSA_VALUE) -#define ALG_ECDH_VALUE 0x0019 -#define TPM_ALG_ECDH (TPM_ALG_ID)(ALG_ECDH_VALUE) -#define ALG_ECDAA_VALUE 0x001A -#define TPM_ALG_ECDAA (TPM_ALG_ID)(ALG_ECDAA_VALUE) -#define ALG_SM2_VALUE 0x001B -#define TPM_ALG_SM2 (TPM_ALG_ID)(ALG_SM2_VALUE) -#define ALG_ECSCHNORR_VALUE 0x001C -#define TPM_ALG_ECSCHNORR (TPM_ALG_ID)(ALG_ECSCHNORR_VALUE) -#define ALG_ECMQV_VALUE 0x001D -#define TPM_ALG_ECMQV (TPM_ALG_ID)(ALG_ECMQV_VALUE) -#define ALG_KDF1_SP800_56A_VALUE 0x0020 -#define TPM_ALG_KDF1_SP800_56A (TPM_ALG_ID)(ALG_KDF1_SP800_56A_VALUE) -#define ALG_KDF2_VALUE 0x0021 -#define TPM_ALG_KDF2 (TPM_ALG_ID)(ALG_KDF2_VALUE) -#define ALG_KDF1_SP800_108_VALUE 0x0022 -#define TPM_ALG_KDF1_SP800_108 (TPM_ALG_ID)(ALG_KDF1_SP800_108_VALUE) -#define ALG_ECC_VALUE 0x0023 -#define TPM_ALG_ECC (TPM_ALG_ID)(ALG_ECC_VALUE) -#define ALG_SYMCIPHER_VALUE 0x0025 -#define TPM_ALG_SYMCIPHER (TPM_ALG_ID)(ALG_SYMCIPHER_VALUE) -#define ALG_CAMELLIA_VALUE 0x0026 -#define TPM_ALG_CAMELLIA (TPM_ALG_ID)(ALG_CAMELLIA_VALUE) -#define ALG_SHA3_256_VALUE 0x0027 -#define TPM_ALG_SHA3_256 (TPM_ALG_ID)(ALG_SHA3_256_VALUE) -#define ALG_SHA3_384_VALUE 0x0028 -#define TPM_ALG_SHA3_384 (TPM_ALG_ID)(ALG_SHA3_384_VALUE) -#define ALG_SHA3_512_VALUE 0x0029 -#define TPM_ALG_SHA3_512 (TPM_ALG_ID)(ALG_SHA3_512_VALUE) -#define ALG_CMAC_VALUE 0x003F -#define TPM_ALG_CMAC (TPM_ALG_ID)(ALG_CMAC_VALUE) -#define ALG_CTR_VALUE 0x0040 -#define TPM_ALG_CTR (TPM_ALG_ID)(ALG_CTR_VALUE) -#define ALG_OFB_VALUE 0x0041 -#define TPM_ALG_OFB (TPM_ALG_ID)(ALG_OFB_VALUE) -#define ALG_CBC_VALUE 0x0042 -#define TPM_ALG_CBC (TPM_ALG_ID)(ALG_CBC_VALUE) -#define ALG_CFB_VALUE 0x0043 -#define TPM_ALG_CFB (TPM_ALG_ID)(ALG_CFB_VALUE) -#define ALG_ECB_VALUE 0x0044 -#define TPM_ALG_ECB (TPM_ALG_ID)(ALG_ECB_VALUE) -// Values derived from Table 1:2 -#define ALG_FIRST_VALUE 0x0001 -#define TPM_ALG_FIRST (TPM_ALG_ID)(ALG_FIRST_VALUE) -#define ALG_LAST_VALUE 0x0044 -#define TPM_ALG_LAST (TPM_ALG_ID)(ALG_LAST_VALUE) - - -// Table 1:3 - Definition of TPM_ECC_CURVE Constants -typedef UINT16 TPM_ECC_CURVE; -#define TYPE_OF_TPM_ECC_CURVE UINT16 -#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001) -#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002) -#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003) -#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004) -#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005) -#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010) -#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011) -#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020) - - // Table 1:12 - Defines for SHA1 Hash Values #define SHA1_DIGEST_SIZE 20 #define SHA1_BLOCK_SIZE 64 @@ -347,133 +223,6 @@ typedef UINT16 TPM_ECC_CURVE; #define MAX_TDES_BLOCK_SIZE_BYTES TDES_MAX_BLOCK_SIZE -// Table 0:5 - Defines for Implemented Commands - - -// Table 2:12 - Definition of TPM_CC Constants -typedef UINT32 TPM_CC; -#define TYPE_OF_TPM_CC UINT32 -#define TPM_CC_NV_UndefineSpaceSpecial (TPM_CC)(0x0000011F) -#define TPM_CC_EvictControl (TPM_CC)(0x00000120) -#define TPM_CC_HierarchyControl (TPM_CC)(0x00000121) -#define TPM_CC_NV_UndefineSpace (TPM_CC)(0x00000122) -#define TPM_CC_ChangeEPS (TPM_CC)(0x00000124) -#define TPM_CC_ChangePPS (TPM_CC)(0x00000125) -#define TPM_CC_Clear (TPM_CC)(0x00000126) -#define TPM_CC_ClearControl (TPM_CC)(0x00000127) -#define TPM_CC_ClockSet (TPM_CC)(0x00000128) -#define TPM_CC_HierarchyChangeAuth (TPM_CC)(0x00000129) -#define TPM_CC_NV_DefineSpace (TPM_CC)(0x0000012A) -#define TPM_CC_PCR_Allocate (TPM_CC)(0x0000012B) -#define TPM_CC_PCR_SetAuthPolicy (TPM_CC)(0x0000012C) -#define TPM_CC_PP_Commands (TPM_CC)(0x0000012D) -#define TPM_CC_SetPrimaryPolicy (TPM_CC)(0x0000012E) -#define TPM_CC_FieldUpgradeStart (TPM_CC)(0x0000012F) -#define TPM_CC_ClockRateAdjust (TPM_CC)(0x00000130) -#define TPM_CC_CreatePrimary (TPM_CC)(0x00000131) -#define TPM_CC_NV_GlobalWriteLock (TPM_CC)(0x00000132) -#define TPM_CC_GetCommandAuditDigest (TPM_CC)(0x00000133) -#define TPM_CC_NV_Increment (TPM_CC)(0x00000134) -#define TPM_CC_NV_SetBits (TPM_CC)(0x00000135) -#define TPM_CC_NV_Extend (TPM_CC)(0x00000136) -#define TPM_CC_NV_Write (TPM_CC)(0x00000137) -#define TPM_CC_NV_WriteLock (TPM_CC)(0x00000138) -#define TPM_CC_DictionaryAttackLockReset (TPM_CC)(0x00000139) -#define TPM_CC_DictionaryAttackParameters (TPM_CC)(0x0000013A) -#define TPM_CC_NV_ChangeAuth (TPM_CC)(0x0000013B) -#define TPM_CC_PCR_Event (TPM_CC)(0x0000013C) -#define TPM_CC_PCR_Reset (TPM_CC)(0x0000013D) -#define TPM_CC_SequenceComplete (TPM_CC)(0x0000013E) -#define TPM_CC_SetAlgorithmSet (TPM_CC)(0x0000013F) -#define TPM_CC_SetCommandCodeAuditStatus (TPM_CC)(0x00000140) -#define TPM_CC_FieldUpgradeData (TPM_CC)(0x00000141) -#define TPM_CC_IncrementalSelfTest (TPM_CC)(0x00000142) -#define TPM_CC_SelfTest (TPM_CC)(0x00000143) -#define TPM_CC_Startup (TPM_CC)(0x00000144) -#define TPM_CC_Shutdown (TPM_CC)(0x00000145) -#define TPM_CC_StirRandom (TPM_CC)(0x00000146) -#define TPM_CC_ActivateCredential (TPM_CC)(0x00000147) -#define TPM_CC_Certify (TPM_CC)(0x00000148) -#define TPM_CC_PolicyNV (TPM_CC)(0x00000149) -#define TPM_CC_CertifyCreation (TPM_CC)(0x0000014A) -#define TPM_CC_Duplicate (TPM_CC)(0x0000014B) -#define TPM_CC_GetTime (TPM_CC)(0x0000014C) -#define TPM_CC_GetSessionAuditDigest (TPM_CC)(0x0000014D) -#define TPM_CC_NV_Read (TPM_CC)(0x0000014E) -#define TPM_CC_NV_ReadLock (TPM_CC)(0x0000014F) -#define TPM_CC_ObjectChangeAuth (TPM_CC)(0x00000150) -#define TPM_CC_PolicySecret (TPM_CC)(0x00000151) -#define TPM_CC_Rewrap (TPM_CC)(0x00000152) -#define TPM_CC_Create (TPM_CC)(0x00000153) -#define TPM_CC_ECDH_ZGen (TPM_CC)(0x00000154) -#define TPM_CC_HMAC (TPM_CC)(0x00000155) -#define TPM_CC_MAC (TPM_CC)(0x00000155) -#define TPM_CC_Import (TPM_CC)(0x00000156) -#define TPM_CC_Load (TPM_CC)(0x00000157) -#define TPM_CC_Quote (TPM_CC)(0x00000158) -#define TPM_CC_RSA_Decrypt (TPM_CC)(0x00000159) -#define TPM_CC_HMAC_Start (TPM_CC)(0x0000015B) -#define TPM_CC_MAC_Start (TPM_CC)(0x0000015B) -#define TPM_CC_SequenceUpdate (TPM_CC)(0x0000015C) -#define TPM_CC_Sign (TPM_CC)(0x0000015D) -#define TPM_CC_Unseal (TPM_CC)(0x0000015E) -#define TPM_CC_PolicySigned (TPM_CC)(0x00000160) -#define TPM_CC_ContextLoad (TPM_CC)(0x00000161) -#define TPM_CC_ContextSave (TPM_CC)(0x00000162) -#define TPM_CC_ECDH_KeyGen (TPM_CC)(0x00000163) -#define TPM_CC_EncryptDecrypt (TPM_CC)(0x00000164) -#define TPM_CC_FlushContext (TPM_CC)(0x00000165) -#define TPM_CC_LoadExternal (TPM_CC)(0x00000167) -#define TPM_CC_MakeCredential (TPM_CC)(0x00000168) -#define TPM_CC_NV_ReadPublic (TPM_CC)(0x00000169) -#define TPM_CC_PolicyAuthorize (TPM_CC)(0x0000016A) -#define TPM_CC_PolicyAuthValue (TPM_CC)(0x0000016B) -#define TPM_CC_PolicyCommandCode (TPM_CC)(0x0000016C) -#define TPM_CC_PolicyCounterTimer (TPM_CC)(0x0000016D) -#define TPM_CC_PolicyCpHash (TPM_CC)(0x0000016E) -#define TPM_CC_PolicyLocality (TPM_CC)(0x0000016F) -#define TPM_CC_PolicyNameHash (TPM_CC)(0x00000170) -#define TPM_CC_PolicyOR (TPM_CC)(0x00000171) -#define TPM_CC_PolicyTicket (TPM_CC)(0x00000172) -#define TPM_CC_ReadPublic (TPM_CC)(0x00000173) -#define TPM_CC_RSA_Encrypt (TPM_CC)(0x00000174) -#define TPM_CC_StartAuthSession (TPM_CC)(0x00000176) -#define TPM_CC_VerifySignature (TPM_CC)(0x00000177) -#define TPM_CC_ECC_Parameters (TPM_CC)(0x00000178) -#define TPM_CC_FirmwareRead (TPM_CC)(0x00000179) -#define TPM_CC_GetCapability (TPM_CC)(0x0000017A) -#define TPM_CC_GetRandom (TPM_CC)(0x0000017B) -#define TPM_CC_GetTestResult (TPM_CC)(0x0000017C) -#define TPM_CC_Hash (TPM_CC)(0x0000017D) -#define TPM_CC_PCR_Read (TPM_CC)(0x0000017E) -#define TPM_CC_PolicyPCR (TPM_CC)(0x0000017F) -#define TPM_CC_PolicyRestart (TPM_CC)(0x00000180) -#define TPM_CC_ReadClock (TPM_CC)(0x00000181) -#define TPM_CC_PCR_Extend (TPM_CC)(0x00000182) -#define TPM_CC_PCR_SetAuthValue (TPM_CC)(0x00000183) -#define TPM_CC_NV_Certify (TPM_CC)(0x00000184) -#define TPM_CC_EventSequenceComplete (TPM_CC)(0x00000185) -#define TPM_CC_HashSequenceStart (TPM_CC)(0x00000186) -#define TPM_CC_PolicyPhysicalPresence (TPM_CC)(0x00000187) -#define TPM_CC_PolicyDuplicationSelect (TPM_CC)(0x00000188) -#define TPM_CC_PolicyGetDigest (TPM_CC)(0x00000189) -#define TPM_CC_TestParms (TPM_CC)(0x0000018A) -#define TPM_CC_Commit (TPM_CC)(0x0000018B) -#define TPM_CC_PolicyPassword (TPM_CC)(0x0000018C) -#define TPM_CC_ZGen_2Phase (TPM_CC)(0x0000018D) -#define TPM_CC_EC_Ephemeral (TPM_CC)(0x0000018E) -#define TPM_CC_PolicyNvWritten (TPM_CC)(0x0000018F) -#define TPM_CC_PolicyTemplate (TPM_CC)(0x00000190) -#define TPM_CC_CreateLoaded (TPM_CC)(0x00000191) -#define TPM_CC_PolicyAuthorizeNV (TPM_CC)(0x00000192) -#define TPM_CC_EncryptDecrypt2 (TPM_CC)(0x00000193) -#define TPM_CC_AC_GetCapability (TPM_CC)(0x00000194) -#define TPM_CC_AC_Send (TPM_CC)(0x00000195) -#define TPM_CC_Policy_AC_SendSelect (TPM_CC)(0x00000196) -#define TPM_CC_CertifyX509 (TPM_CC)(0x00000197) -#define CC_VEND 0x20000000 -#define TPM_CC_Vendor_TCG_Test (TPM_CC)(0x20000000) - // Additional values for benefit of code #define TPM_CC_FIRST 0x0000011F #define TPM_CC_LAST 0x00000197 diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmBuildSwitches.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmBuildSwitches.h index 948985843..7ab437684 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmBuildSwitches.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmBuildSwitches.h @@ -59,20 +59,6 @@ #undef NO #define NO 0 -#ifndef RADIX_BITS -#if defined(__x86_64__) || defined(__x86_64) \ - || defined(__amd64__) || defined(__amd64) || defined(_WIN64) || defined(_M_X64) \ - || defined(_M_ARM64) || defined(__aarch64__) -# define RADIX_BITS 64 -#elif defined(__i386__) || defined(__i386) || defined(i386) \ - || defined(_WIN32) || defined(_M_IX86) \ - || defined(_M_ARM) || defined(__arm__) || defined(__thumb__) -# define RADIX_BITS 32 -#else -# error Unable to determine RADIX_BITS from compiler environment -#endif -#endif // RADIX_BITS - // Allow the command line to specify a "profile" file #ifdef PROFILE # define PROFILE_QUOTE(a) #a @@ -263,7 +249,7 @@ # endif // Some of the values (such as sizes) are the result of different options set in -// Implementation.h. The combination might not be consistent. A function is defined +// TpmProfile.h. The combination might not be consistent. A function is defined // (TpmSizeChecks()) that is used to verify the sizes at run time. To enable the // function, define this parameter. # if !(defined RUNTIME_SIZE_CHECKS) \ @@ -337,6 +323,13 @@ # define LIBRARY_COMPATIBILITY_CHECK NO // Default: Either YES or NO #endif +// This define is used to control the debug for the CertifyX509 command. +#if !(defined CERTIFYX509_DEBUG) \ + || ((CERTIFYX509_DEBUG != NO) && (CERTIFYX509_DEBUG != YES)) +# undef CERTIFYX509_DEBUG +# define CERTIFYX509_DEBUG YES // Default: Either YES or NO +#endif + // Change these definitions to turn all algorithms or commands ON or OFF. That is, // to turn all algorithms on, set ALG_NO to YES. This is mostly useful as a debug // feature. diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmProfile.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmProfile.h index c5a9a760a..7329f79ba 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmProfile.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmProfile.h @@ -34,7 +34,7 @@ */ /*(Auto-generated) * Created by TpmStructures; Version 4.4 Mar 26, 2019 - * Date: Apr 8, 2019 Time: 03:18:09PM + * Date: Apr 10, 2019 Time: 03:21:33PM */ #ifndef _TPM_PROFILE_H_ @@ -101,9 +101,6 @@ #ifndef FIELD_UPGRADE_IMPLEMENTED #define FIELD_UPGRADE_IMPLEMENTED NO #endif -#ifndef RADIX_BITS -#define RADIX_BITS 32 -#endif #ifndef HASH_ALIGNMENT #define HASH_ALIGNMENT 4 #endif @@ -111,29 +108,29 @@ #define SYMMETRIC_ALIGNMENT 4 #endif #ifndef HASH_LIB -#define HASH_LIB Wolf +#define HASH_LIB Ossl #endif #ifndef SYM_LIB -#define SYM_LIB Wolf +#define SYM_LIB Ossl #endif #ifndef MATH_LIB -#define MATH_LIB Wolf +#define MATH_LIB Ossl #endif #ifndef BSIZE #define BSIZE UINT16 #endif -#ifndef PLATFORM_PCR -#define PLATFORM_PCR 24 -#endif -#ifndef PCR_SELECT_MIN -#define PCR_SELECT_MIN ((PLATFORM_PCR+7)/8) -#endif #ifndef IMPLEMENTATION_PCR #define IMPLEMENTATION_PCR 24 #endif #ifndef PCR_SELECT_MAX #define PCR_SELECT_MAX ((IMPLEMENTATION_PCR+7)/8) #endif +#ifndef PLATFORM_PCR +#define PLATFORM_PCR 24 +#endif +#ifndef PCR_SELECT_MIN +#define PCR_SELECT_MIN ((PLATFORM_PCR+7)/8) +#endif #ifndef DRTM_PCR #define DRTM_PCR 17 #endif @@ -203,8 +200,8 @@ #ifndef PRIMARY_SEED_SIZE #define PRIMARY_SEED_SIZE 32 #endif -#ifndef CONTEXT_ENCRYPT_ALG -#define CONTEXT_ENCRYPT_ALG ALG_AES_VALUE +#ifndef CONTEXT_ENCRYPT_ALGORITHM +#define CONTEXT_ENCRYPT_ALGORITHM AES #endif #ifndef NV_CLOCK_UPDATE_INTERVAL #define NV_CLOCK_UPDATE_INTERVAL 12 @@ -248,11 +245,14 @@ #ifndef TPM_MAX_DERIVATION_BITS #define TPM_MAX_DERIVATION_BITS 8192 #endif -#ifndef SIZE_OF_X509_SERIAL_NUMBER -#define SIZE_OF_X509_SERIAL_NUMBER 20 +#ifndef RSA_MAX_PRIME +#define RSA_MAX_PRIME (MAX_RSA_KEY_BYTES/2) #endif #ifndef RSA_PRIVATE_SIZE -#define RSA_PRIVATE_SIZE ((MAX_RSA_KEY_BYTES*5)/2) +#define RSA_PRIVATE_SIZE (RSA_MAX_PRIME*5) +#endif +#ifndef SIZE_OF_X509_SERIAL_NUMBER +#define SIZE_OF_X509_SERIAL_NUMBER 20 #endif #ifndef PRIVATE_VENDOR_SPECIFIC_BYTES #define PRIVATE_VENDOR_SPECIFIC_BYTES RSA_PRIVATE_SIZE @@ -377,11 +377,6 @@ #define ALG_XOR ALG_YES #endif -// Table 1:3 - Definition of TPM_ECC_CURVE Constants -#ifndef TPM_ECC_NONE -#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000) -#endif - // Table 1:00 - Defines for RSA Asymmetric Cipher Algorithm Constants #ifndef RSA_1024 #define RSA_1024 (ALG_RSA & YES) diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmTypes.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmTypes.h index 075bec841..aefcdf280 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmTypes.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/TpmTypes.h @@ -34,12 +34,240 @@ */ /*(Auto-generated) * Created by TpmStructures; Version 4.4 Mar 26, 2019 - * Date: Apr 2, 2019 Time: 11:00:48AM + * Date: Apr 10, 2019 Time: 03:21:33PM */ #ifndef _TPM_TYPES_H_ #define _TPM_TYPES_H_ +// Table 1:2 - Definition of TPM_ALG_ID Constants +typedef UINT16 TPM_ALG_ID; +#define TYPE_OF_TPM_ALG_ID UINT16 +#define ALG_ERROR_VALUE 0x0000 +#define TPM_ALG_ERROR (TPM_ALG_ID)(ALG_ERROR_VALUE) +#define ALG_RSA_VALUE 0x0001 +#define TPM_ALG_RSA (TPM_ALG_ID)(ALG_RSA_VALUE) +#define ALG_TDES_VALUE 0x0003 +#define TPM_ALG_TDES (TPM_ALG_ID)(ALG_TDES_VALUE) +#define ALG_SHA_VALUE 0x0004 +#define TPM_ALG_SHA (TPM_ALG_ID)(ALG_SHA_VALUE) +#define ALG_SHA1_VALUE 0x0004 +#define TPM_ALG_SHA1 (TPM_ALG_ID)(ALG_SHA1_VALUE) +#define ALG_HMAC_VALUE 0x0005 +#define TPM_ALG_HMAC (TPM_ALG_ID)(ALG_HMAC_VALUE) +#define ALG_AES_VALUE 0x0006 +#define TPM_ALG_AES (TPM_ALG_ID)(ALG_AES_VALUE) +#define ALG_MGF1_VALUE 0x0007 +#define TPM_ALG_MGF1 (TPM_ALG_ID)(ALG_MGF1_VALUE) +#define ALG_KEYEDHASH_VALUE 0x0008 +#define TPM_ALG_KEYEDHASH (TPM_ALG_ID)(ALG_KEYEDHASH_VALUE) +#define ALG_XOR_VALUE 0x000A +#define TPM_ALG_XOR (TPM_ALG_ID)(ALG_XOR_VALUE) +#define ALG_SHA256_VALUE 0x000B +#define TPM_ALG_SHA256 (TPM_ALG_ID)(ALG_SHA256_VALUE) +#define ALG_SHA384_VALUE 0x000C +#define TPM_ALG_SHA384 (TPM_ALG_ID)(ALG_SHA384_VALUE) +#define ALG_SHA512_VALUE 0x000D +#define TPM_ALG_SHA512 (TPM_ALG_ID)(ALG_SHA512_VALUE) +#define ALG_NULL_VALUE 0x0010 +#define TPM_ALG_NULL (TPM_ALG_ID)(ALG_NULL_VALUE) +#define ALG_SM3_256_VALUE 0x0012 +#define TPM_ALG_SM3_256 (TPM_ALG_ID)(ALG_SM3_256_VALUE) +#define ALG_SM4_VALUE 0x0013 +#define TPM_ALG_SM4 (TPM_ALG_ID)(ALG_SM4_VALUE) +#define ALG_RSASSA_VALUE 0x0014 +#define TPM_ALG_RSASSA (TPM_ALG_ID)(ALG_RSASSA_VALUE) +#define ALG_RSAES_VALUE 0x0015 +#define TPM_ALG_RSAES (TPM_ALG_ID)(ALG_RSAES_VALUE) +#define ALG_RSAPSS_VALUE 0x0016 +#define TPM_ALG_RSAPSS (TPM_ALG_ID)(ALG_RSAPSS_VALUE) +#define ALG_OAEP_VALUE 0x0017 +#define TPM_ALG_OAEP (TPM_ALG_ID)(ALG_OAEP_VALUE) +#define ALG_ECDSA_VALUE 0x0018 +#define TPM_ALG_ECDSA (TPM_ALG_ID)(ALG_ECDSA_VALUE) +#define ALG_ECDH_VALUE 0x0019 +#define TPM_ALG_ECDH (TPM_ALG_ID)(ALG_ECDH_VALUE) +#define ALG_ECDAA_VALUE 0x001A +#define TPM_ALG_ECDAA (TPM_ALG_ID)(ALG_ECDAA_VALUE) +#define ALG_SM2_VALUE 0x001B +#define TPM_ALG_SM2 (TPM_ALG_ID)(ALG_SM2_VALUE) +#define ALG_ECSCHNORR_VALUE 0x001C +#define TPM_ALG_ECSCHNORR (TPM_ALG_ID)(ALG_ECSCHNORR_VALUE) +#define ALG_ECMQV_VALUE 0x001D +#define TPM_ALG_ECMQV (TPM_ALG_ID)(ALG_ECMQV_VALUE) +#define ALG_KDF1_SP800_56A_VALUE 0x0020 +#define TPM_ALG_KDF1_SP800_56A (TPM_ALG_ID)(ALG_KDF1_SP800_56A_VALUE) +#define ALG_KDF2_VALUE 0x0021 +#define TPM_ALG_KDF2 (TPM_ALG_ID)(ALG_KDF2_VALUE) +#define ALG_KDF1_SP800_108_VALUE 0x0022 +#define TPM_ALG_KDF1_SP800_108 (TPM_ALG_ID)(ALG_KDF1_SP800_108_VALUE) +#define ALG_ECC_VALUE 0x0023 +#define TPM_ALG_ECC (TPM_ALG_ID)(ALG_ECC_VALUE) +#define ALG_SYMCIPHER_VALUE 0x0025 +#define TPM_ALG_SYMCIPHER (TPM_ALG_ID)(ALG_SYMCIPHER_VALUE) +#define ALG_CAMELLIA_VALUE 0x0026 +#define TPM_ALG_CAMELLIA (TPM_ALG_ID)(ALG_CAMELLIA_VALUE) +#define ALG_SHA3_256_VALUE 0x0027 +#define TPM_ALG_SHA3_256 (TPM_ALG_ID)(ALG_SHA3_256_VALUE) +#define ALG_SHA3_384_VALUE 0x0028 +#define TPM_ALG_SHA3_384 (TPM_ALG_ID)(ALG_SHA3_384_VALUE) +#define ALG_SHA3_512_VALUE 0x0029 +#define TPM_ALG_SHA3_512 (TPM_ALG_ID)(ALG_SHA3_512_VALUE) +#define ALG_CMAC_VALUE 0x003F +#define TPM_ALG_CMAC (TPM_ALG_ID)(ALG_CMAC_VALUE) +#define ALG_CTR_VALUE 0x0040 +#define TPM_ALG_CTR (TPM_ALG_ID)(ALG_CTR_VALUE) +#define ALG_OFB_VALUE 0x0041 +#define TPM_ALG_OFB (TPM_ALG_ID)(ALG_OFB_VALUE) +#define ALG_CBC_VALUE 0x0042 +#define TPM_ALG_CBC (TPM_ALG_ID)(ALG_CBC_VALUE) +#define ALG_CFB_VALUE 0x0043 +#define TPM_ALG_CFB (TPM_ALG_ID)(ALG_CFB_VALUE) +#define ALG_ECB_VALUE 0x0044 +#define TPM_ALG_ECB (TPM_ALG_ID)(ALG_ECB_VALUE) +// Values derived from Table 1:2 +#define ALG_FIRST_VALUE 0x0001 +#define TPM_ALG_FIRST (TPM_ALG_ID)(ALG_FIRST_VALUE) +#define ALG_LAST_VALUE 0x0044 +#define TPM_ALG_LAST (TPM_ALG_ID)(ALG_LAST_VALUE) + +// Table 1:3 - Definition of TPM_ECC_CURVE Constants +typedef UINT16 TPM_ECC_CURVE; +#define TYPE_OF_TPM_ECC_CURVE UINT16 +#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000) +#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001) +#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002) +#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003) +#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004) +#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005) +#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010) +#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011) +#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020) + +// Table 2:12 - Definition of TPM_CC Constants +typedef UINT32 TPM_CC; +#define TYPE_OF_TPM_CC UINT32 +#define TPM_CC_NV_UndefineSpaceSpecial (TPM_CC)(0x0000011F) +#define TPM_CC_EvictControl (TPM_CC)(0x00000120) +#define TPM_CC_HierarchyControl (TPM_CC)(0x00000121) +#define TPM_CC_NV_UndefineSpace (TPM_CC)(0x00000122) +#define TPM_CC_ChangeEPS (TPM_CC)(0x00000124) +#define TPM_CC_ChangePPS (TPM_CC)(0x00000125) +#define TPM_CC_Clear (TPM_CC)(0x00000126) +#define TPM_CC_ClearControl (TPM_CC)(0x00000127) +#define TPM_CC_ClockSet (TPM_CC)(0x00000128) +#define TPM_CC_HierarchyChangeAuth (TPM_CC)(0x00000129) +#define TPM_CC_NV_DefineSpace (TPM_CC)(0x0000012A) +#define TPM_CC_PCR_Allocate (TPM_CC)(0x0000012B) +#define TPM_CC_PCR_SetAuthPolicy (TPM_CC)(0x0000012C) +#define TPM_CC_PP_Commands (TPM_CC)(0x0000012D) +#define TPM_CC_SetPrimaryPolicy (TPM_CC)(0x0000012E) +#define TPM_CC_FieldUpgradeStart (TPM_CC)(0x0000012F) +#define TPM_CC_ClockRateAdjust (TPM_CC)(0x00000130) +#define TPM_CC_CreatePrimary (TPM_CC)(0x00000131) +#define TPM_CC_NV_GlobalWriteLock (TPM_CC)(0x00000132) +#define TPM_CC_GetCommandAuditDigest (TPM_CC)(0x00000133) +#define TPM_CC_NV_Increment (TPM_CC)(0x00000134) +#define TPM_CC_NV_SetBits (TPM_CC)(0x00000135) +#define TPM_CC_NV_Extend (TPM_CC)(0x00000136) +#define TPM_CC_NV_Write (TPM_CC)(0x00000137) +#define TPM_CC_NV_WriteLock (TPM_CC)(0x00000138) +#define TPM_CC_DictionaryAttackLockReset (TPM_CC)(0x00000139) +#define TPM_CC_DictionaryAttackParameters (TPM_CC)(0x0000013A) +#define TPM_CC_NV_ChangeAuth (TPM_CC)(0x0000013B) +#define TPM_CC_PCR_Event (TPM_CC)(0x0000013C) +#define TPM_CC_PCR_Reset (TPM_CC)(0x0000013D) +#define TPM_CC_SequenceComplete (TPM_CC)(0x0000013E) +#define TPM_CC_SetAlgorithmSet (TPM_CC)(0x0000013F) +#define TPM_CC_SetCommandCodeAuditStatus (TPM_CC)(0x00000140) +#define TPM_CC_FieldUpgradeData (TPM_CC)(0x00000141) +#define TPM_CC_IncrementalSelfTest (TPM_CC)(0x00000142) +#define TPM_CC_SelfTest (TPM_CC)(0x00000143) +#define TPM_CC_Startup (TPM_CC)(0x00000144) +#define TPM_CC_Shutdown (TPM_CC)(0x00000145) +#define TPM_CC_StirRandom (TPM_CC)(0x00000146) +#define TPM_CC_ActivateCredential (TPM_CC)(0x00000147) +#define TPM_CC_Certify (TPM_CC)(0x00000148) +#define TPM_CC_PolicyNV (TPM_CC)(0x00000149) +#define TPM_CC_CertifyCreation (TPM_CC)(0x0000014A) +#define TPM_CC_Duplicate (TPM_CC)(0x0000014B) +#define TPM_CC_GetTime (TPM_CC)(0x0000014C) +#define TPM_CC_GetSessionAuditDigest (TPM_CC)(0x0000014D) +#define TPM_CC_NV_Read (TPM_CC)(0x0000014E) +#define TPM_CC_NV_ReadLock (TPM_CC)(0x0000014F) +#define TPM_CC_ObjectChangeAuth (TPM_CC)(0x00000150) +#define TPM_CC_PolicySecret (TPM_CC)(0x00000151) +#define TPM_CC_Rewrap (TPM_CC)(0x00000152) +#define TPM_CC_Create (TPM_CC)(0x00000153) +#define TPM_CC_ECDH_ZGen (TPM_CC)(0x00000154) +#define TPM_CC_HMAC (TPM_CC)(0x00000155) +#define TPM_CC_MAC (TPM_CC)(0x00000155) +#define TPM_CC_Import (TPM_CC)(0x00000156) +#define TPM_CC_Load (TPM_CC)(0x00000157) +#define TPM_CC_Quote (TPM_CC)(0x00000158) +#define TPM_CC_RSA_Decrypt (TPM_CC)(0x00000159) +#define TPM_CC_HMAC_Start (TPM_CC)(0x0000015B) +#define TPM_CC_MAC_Start (TPM_CC)(0x0000015B) +#define TPM_CC_SequenceUpdate (TPM_CC)(0x0000015C) +#define TPM_CC_Sign (TPM_CC)(0x0000015D) +#define TPM_CC_Unseal (TPM_CC)(0x0000015E) +#define TPM_CC_PolicySigned (TPM_CC)(0x00000160) +#define TPM_CC_ContextLoad (TPM_CC)(0x00000161) +#define TPM_CC_ContextSave (TPM_CC)(0x00000162) +#define TPM_CC_ECDH_KeyGen (TPM_CC)(0x00000163) +#define TPM_CC_EncryptDecrypt (TPM_CC)(0x00000164) +#define TPM_CC_FlushContext (TPM_CC)(0x00000165) +#define TPM_CC_LoadExternal (TPM_CC)(0x00000167) +#define TPM_CC_MakeCredential (TPM_CC)(0x00000168) +#define TPM_CC_NV_ReadPublic (TPM_CC)(0x00000169) +#define TPM_CC_PolicyAuthorize (TPM_CC)(0x0000016A) +#define TPM_CC_PolicyAuthValue (TPM_CC)(0x0000016B) +#define TPM_CC_PolicyCommandCode (TPM_CC)(0x0000016C) +#define TPM_CC_PolicyCounterTimer (TPM_CC)(0x0000016D) +#define TPM_CC_PolicyCpHash (TPM_CC)(0x0000016E) +#define TPM_CC_PolicyLocality (TPM_CC)(0x0000016F) +#define TPM_CC_PolicyNameHash (TPM_CC)(0x00000170) +#define TPM_CC_PolicyOR (TPM_CC)(0x00000171) +#define TPM_CC_PolicyTicket (TPM_CC)(0x00000172) +#define TPM_CC_ReadPublic (TPM_CC)(0x00000173) +#define TPM_CC_RSA_Encrypt (TPM_CC)(0x00000174) +#define TPM_CC_StartAuthSession (TPM_CC)(0x00000176) +#define TPM_CC_VerifySignature (TPM_CC)(0x00000177) +#define TPM_CC_ECC_Parameters (TPM_CC)(0x00000178) +#define TPM_CC_FirmwareRead (TPM_CC)(0x00000179) +#define TPM_CC_GetCapability (TPM_CC)(0x0000017A) +#define TPM_CC_GetRandom (TPM_CC)(0x0000017B) +#define TPM_CC_GetTestResult (TPM_CC)(0x0000017C) +#define TPM_CC_Hash (TPM_CC)(0x0000017D) +#define TPM_CC_PCR_Read (TPM_CC)(0x0000017E) +#define TPM_CC_PolicyPCR (TPM_CC)(0x0000017F) +#define TPM_CC_PolicyRestart (TPM_CC)(0x00000180) +#define TPM_CC_ReadClock (TPM_CC)(0x00000181) +#define TPM_CC_PCR_Extend (TPM_CC)(0x00000182) +#define TPM_CC_PCR_SetAuthValue (TPM_CC)(0x00000183) +#define TPM_CC_NV_Certify (TPM_CC)(0x00000184) +#define TPM_CC_EventSequenceComplete (TPM_CC)(0x00000185) +#define TPM_CC_HashSequenceStart (TPM_CC)(0x00000186) +#define TPM_CC_PolicyPhysicalPresence (TPM_CC)(0x00000187) +#define TPM_CC_PolicyDuplicationSelect (TPM_CC)(0x00000188) +#define TPM_CC_PolicyGetDigest (TPM_CC)(0x00000189) +#define TPM_CC_TestParms (TPM_CC)(0x0000018A) +#define TPM_CC_Commit (TPM_CC)(0x0000018B) +#define TPM_CC_PolicyPassword (TPM_CC)(0x0000018C) +#define TPM_CC_ZGen_2Phase (TPM_CC)(0x0000018D) +#define TPM_CC_EC_Ephemeral (TPM_CC)(0x0000018E) +#define TPM_CC_PolicyNvWritten (TPM_CC)(0x0000018F) +#define TPM_CC_PolicyTemplate (TPM_CC)(0x00000190) +#define TPM_CC_CreateLoaded (TPM_CC)(0x00000191) +#define TPM_CC_PolicyAuthorizeNV (TPM_CC)(0x00000192) +#define TPM_CC_EncryptDecrypt2 (TPM_CC)(0x00000193) +#define TPM_CC_AC_GetCapability (TPM_CC)(0x00000194) +#define TPM_CC_AC_Send (TPM_CC)(0x00000195) +#define TPM_CC_Policy_AC_SendSelect (TPM_CC)(0x00000196) +#define TPM_CC_CertifyX509 (TPM_CC)(0x00000197) +#define CC_VEND 0x20000000 +#define TPM_CC_Vendor_TCG_Test (TPM_CC)(0x20000000) + // Table 2:5 - Definition of Types for Documentation Clarity typedef UINT32 TPM_ALGORITHM_ID; #define TYPE_OF_TPM_ALGORITHM_ID UINT32 @@ -61,11 +289,11 @@ typedef UINT32 TPM_SPEC; #define TPM_SPEC_FAMILY (TPM_SPEC)(SPEC_FAMILY) #define SPEC_LEVEL 00 #define TPM_SPEC_LEVEL (TPM_SPEC)(SPEC_LEVEL) -#define SPEC_VERSION 153 +#define SPEC_VERSION 154 #define TPM_SPEC_VERSION (TPM_SPEC)(SPEC_VERSION) #define SPEC_YEAR 2019 #define TPM_SPEC_YEAR (TPM_SPEC)(SPEC_YEAR) -#define SPEC_DAY_OF_YEAR 28 +#define SPEC_DAY_OF_YEAR 81 #define TPM_SPEC_DAY_OF_YEAR (TPM_SPEC)(SPEC_DAY_OF_YEAR) // Table 2:7 - Definition of TPM_GENERATED Constants @@ -546,9 +774,9 @@ typedef UINT32 TPMA_ALGORITHM; #define TPMA_ALGORITHM_INITIALIZER( \ asymmetric, symmetric, hash, object, bits_at_4, \ signing, encrypting, method, bits_at_11) \ - ((asymmetric << 0) + (symmetric << 1) + (hash << 2) + \ + {(asymmetric << 0) + (symmetric << 1) + (hash << 2) + \ (object << 3) + (signing << 8) + (encrypting << 9) + \ - (method << 10)) + (method << 10)} #endif // USE_BIT_FIELD_STRUCTURES #define TYPE_OF_TPMA_OBJECT UINT32 @@ -616,12 +844,12 @@ typedef UINT32 TPMA_OBJECT; noda, encryptedduplication, bits_at_12, \ restricted, decrypt, sign, \ x509sign, bits_at_20) \ - ((fixedtpm << 1) + (stclear << 2) + \ + {(fixedtpm << 1) + (stclear << 2) + \ (fixedparent << 4) + (sensitivedataorigin << 5) + \ (userwithauth << 6) + (adminwithpolicy << 7) + \ (noda << 10) + (encryptedduplication << 11) + \ (restricted << 16) + (decrypt << 17) + \ - (sign << 18) + (x509sign << 19)) + (sign << 18) + (x509sign << 19)} #endif // USE_BIT_FIELD_STRUCTURES #define TYPE_OF_TPMA_SESSION UINT8 @@ -661,9 +889,9 @@ typedef UINT8 TPMA_SESSION; #define TPMA_SESSION_INITIALIZER( \ continuesession, auditexclusive, auditreset, bits_at_3, \ decrypt, encrypt, audit) \ - ((continuesession << 0) + (auditexclusive << 1) + \ + {(continuesession << 0) + (auditexclusive << 1) + \ (auditreset << 2) + (decrypt << 5) + \ - (encrypt << 6) + (audit << 7)) + (encrypt << 6) + (audit << 7)} #endif // USE_BIT_FIELD_STRUCTURES #define TYPE_OF_TPMA_LOCALITY UINT8 @@ -703,8 +931,8 @@ typedef UINT8 TPMA_LOCALITY; #define TPMA_LOCALITY_INITIALIZER( \ tpm_loc_zero, tpm_loc_one, tpm_loc_two, tpm_loc_three, \ tpm_loc_four, extended) \ - ((tpm_loc_zero << 0) + (tpm_loc_one << 1) + (tpm_loc_two << 2) + \ - (tpm_loc_three << 3) + (tpm_loc_four << 4) + (extended << 5)) + {(tpm_loc_zero << 0) + (tpm_loc_one << 1) + (tpm_loc_two << 2) + \ + (tpm_loc_three << 3) + (tpm_loc_four << 4) + (extended << 5)} #endif // USE_BIT_FIELD_STRUCTURES #define TYPE_OF_TPMA_PERMANENT UINT32 @@ -750,9 +978,9 @@ typedef UINT32 TPMA_PERMANENT; ownerauthset, endorsementauthset, lockoutauthset, \ bits_at_3, disableclear, inlockout, \ tpmgeneratedeps, bits_at_11) \ - ((ownerauthset << 0) + (endorsementauthset << 1) + \ + {(ownerauthset << 0) + (endorsementauthset << 1) + \ (lockoutauthset << 2) + (disableclear << 8) + \ - (inlockout << 9) + (tpmgeneratedeps << 10)) + (inlockout << 9) + (tpmgeneratedeps << 10)} #endif // USE_BIT_FIELD_STRUCTURES #define TYPE_OF_TPMA_STARTUP_CLEAR UINT32 @@ -789,8 +1017,8 @@ typedef UINT32 TPMA_STARTUP_CLEAR; // This is the initializer for a TPMA_STARTUP_CLEAR bit array. #define TPMA_STARTUP_CLEAR_INITIALIZER( \ phenable, shenable, ehenable, phenablenv, bits_at_4, orderly) \ - ((phenable << 0) + (shenable << 1) + (ehenable << 2) + \ - (phenablenv << 3) + (orderly << 31)) + {(phenable << 0) + (shenable << 1) + (ehenable << 2) + \ + (phenablenv << 3) + (orderly << 31)} #endif // USE_BIT_FIELD_STRUCTURES #define TYPE_OF_TPMA_MEMORY UINT32 @@ -821,7 +1049,7 @@ typedef UINT32 TPMA_MEMORY; // This is the initializer for a TPMA_MEMORY bit array. #define TPMA_MEMORY_INITIALIZER( \ sharedram, sharednv, objectcopiedtoram, bits_at_3) \ - ((sharedram << 0) + (sharednv << 1) + (objectcopiedtoram << 2)) + {(sharedram << 0) + (sharednv << 1) + (objectcopiedtoram << 2)} #endif // USE_BIT_FIELD_STRUCTURES #define TYPE_OF_TPMA_CC UINT32 @@ -866,9 +1094,9 @@ typedef UINT32 TPMA_CC; #define TPMA_CC_INITIALIZER( \ commandindex, bits_at_16, nv, extensive, flushed, \ chandles, rhandle, v, bits_at_30) \ - ((commandindex << 0) + (nv << 22) + (extensive << 23) + \ + {(commandindex << 0) + (nv << 22) + (extensive << 23) + \ (flushed << 24) + (chandles << 25) + (rhandle << 28) + \ - (v << 29)) + (v << 29)} #endif // USE_BIT_FIELD_STRUCTURES #define TYPE_OF_TPMA_MODES UINT32 @@ -891,7 +1119,7 @@ typedef UINT32 TPMA_MODES; #define TYPE_OF_TPMA_MODES UINT32 #define TPMA_MODES_FIPS_140_2 ((TPMA_MODES)1 << 0) // This is the initializer for a TPMA_MODES bit array. -#define TPMA_MODES_INITIALIZER(fips_140_2, bits_at_1) (fips_140_2 << 0) +#define TPMA_MODES_INITIALIZER(fips_140_2, bits_at_1) {(fips_140_2 << 0)} #endif // USE_BIT_FIELD_STRUCTURES #define TYPE_OF_TPMA_X509_KEY_USAGE UINT32 @@ -945,11 +1173,11 @@ typedef UINT32 TPMA_X509_KEY_USAGE; dataencipherment, keyagreement, keycertsign, \ crlsign, encipheronly, decipheronly, \ bits_at_9) \ - ((digitalsignature << 0) + (nonrepudiation << 1) + \ + {(digitalsignature << 0) + (nonrepudiation << 1) + \ (keyencipherment << 2) + (dataencipherment << 3) + \ (keyagreement << 4) + (keycertsign << 5) + \ (crlsign << 6) + (encipheronly << 7) + \ - (decipheronly << 8)) + (decipheronly << 8)} #endif // USE_BIT_FIELD_STRUCTURES typedef BYTE TPMI_YES_NO; // Table 2:40 /* Interface */ @@ -1948,7 +2176,7 @@ typedef UINT32 TPM_NV_INDEX; #define TPM_NV_INDEX_RH_NV_SHIFT 24 #define TPM_NV_INDEX_RH_NV ((TPM_NV_INDEX)0xff << 24) // This is the initializer for a TPM_NV_INDEX bit array. -#define TPM_NV_INDEX_INITIALIZER(index, rh_nv) ((index << 0) + (rh_nv << 24)) +#define TPM_NV_INDEX_INITIALIZER(index, rh_nv) {(index << 0) + (rh_nv << 24)} #endif // USE_BIT_FIELD_STRUCTURES // Table 2:208 - Definition of TPM_NT Constants @@ -2049,7 +2277,7 @@ typedef UINT32 TPMA_NV; ppread, ownerread, authread, policyread, \ bits_at_20, no_da, orderly, clear_stclear, \ readlocked, written, platformcreate, read_stclear) \ - ((ppwrite << 0) + (ownerwrite << 1) + \ + {(ppwrite << 0) + (ownerwrite << 1) + \ (authwrite << 2) + (policywrite << 3) + \ (tpm_nt << 4) + (policy_delete << 10) + \ (writelocked << 11) + (writeall << 12) + \ @@ -2059,7 +2287,7 @@ typedef UINT32 TPMA_NV; (policyread << 19) + (no_da << 25) + \ (orderly << 26) + (clear_stclear << 27) + \ (readlocked << 28) + (written << 29) + \ - (platformcreate << 30) + (read_stclear << 31)) + (platformcreate << 30) + (read_stclear << 31)} #endif // USE_BIT_FIELD_STRUCTURES typedef struct { // Table 2:211 diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/VendorString.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/VendorString.h index 82dae5461..1576396a2 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/VendorString.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/VendorString.h @@ -45,7 +45,7 @@ // The following #if macro may be deleted after a proper MANUFACTURER is provided. #ifndef MANUFACTURER #error MANUFACTURER is not provided. \ -Please modify include\VendorString.h to provide a specific \ +Please modify include/VendorString.h to provide a specific \ manufacturer name. #endif @@ -65,8 +65,7 @@ manufacturer name. // is provided. #ifndef VENDOR_STRING_1 #error VENDOR_STRING_1 is not provided. \ -Please modify include\VendorString.h to provide a vednor-specific \ -string. +Please modify include/VendorString.h to provide a vendor-specific string. #endif // the more significant 32-bits of a vendor-specific value @@ -82,7 +81,7 @@ string. // The following #if macro may be deleted after a proper FIRMWARE_V1 is provided. #ifndef FIRMWARE_V1 #error FIRMWARE_V1 is not provided. \ -Please modify include\VendorString.h to provide a vendor specific firmware \ +Please modify include/VendorString.h to provide a vendor-specific firmware \ version #endif diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/TpmToWolfHash.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/TpmToWolfHash.h index f4d328b16..507228398 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/TpmToWolfHash.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/TpmToWolfHash.h @@ -37,8 +37,8 @@ // // This header file is used to 'splice' the wolfcrypt hash code into the TPM code. // -#ifndef _TPM_TO_WOLF_HASH_H_ -#define _TPM_TO_WOLF_HASH_H_ +#ifndef HASH_LIB_DEFINED +#define HASH_LIB_DEFINED #define HASH_LIB_WOLF @@ -69,10 +69,17 @@ #define tpmHashStateSHA384_t wc_Sha512 #define tpmHashStateSHA512_t wc_Sha512 -#ifdef TPM_ALG_SM3 +#if ALG_SM3 # error "The version of WolfCrypt used by this code does not support SM3" #endif +// The defines below are only needed when compiling CryptHash.c or CryptSmac.c. +// This isolation is primarily to avoid name space collision. However, if there +// is a real collision, it will likely show up when the linker tries to put things +// together. + +#ifdef _CRYPT_HASH_C_ + typedef BYTE *PBYTE; typedef const BYTE *PCBYTE; @@ -175,8 +182,10 @@ typedef const BYTE *PCBYTE; #define tpmHashStateExport_SHA512 memcpy #define tpmHashStateImport_SHA512 memcpy +#endif // _CRYPT_HASH_C_ + #define LibHashInit() // This definition would change if there were something to report #define HashLibSimulationEnd() -#endif // +#endif // HASH_LIB_DEFINED diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/TpmToWolfMath.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/TpmToWolfMath.h index c8e440185..18b48b931 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/TpmToWolfMath.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/TpmToWolfMath.h @@ -34,14 +34,14 @@ */ //** Introduction -// This file contains the structure definitions used for ECC in the LibTopCrypt +// This file contains the structure definitions used for ECC in the LibTomCrypt // version of the code. These definitions would change, based on the library. // The ECC-related structures that cross the TPM interface are defined // in TpmTypes.h // -#ifndef _TPM_TO_WOLF_MATH_H -#define _TPM_TO_WOLF_MATH_H +#ifndef MATH_LIB_DEFINED +#define MATH_LIB_DEFINED #define MATH_LIB_WOLF @@ -88,4 +88,4 @@ typedef bnCurve_t *bigCurve; // This definition would change if there were something to report #define MathLibSimulationEnd() -#endif +#endif // MATH_LIB_DEFINED diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/TpmToWolfSym.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/TpmToWolfSym.h index 92b6592d0..54e01e3ed 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/TpmToWolfSym.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/TpmToWolfSym.h @@ -37,8 +37,8 @@ // // This header file is used to 'splice' the wolfcrypt library into the TPM code. -#ifndef _TPM_TO_WOLF_SYM_H_ -#define _TPM_TO_WOLF_SYM_H_ +#ifndef SYM_LIB_DEFINED +#define SYM_LIB_DEFINED #define SYM_LIB_WOLF @@ -53,7 +53,7 @@ #error "SM4 is not available" #endif -#if ALG_CAMELLIA +#if ALG_CAMELLIA #error "Camellia is not available" #endif @@ -112,4 +112,4 @@ typedef union tpmCryptKeySchedule_t tpmCryptKeySchedule_t; // This definition would change if there were something to report #define SymLibSimulationEnd() -#endif // _TPM_TO_WOLF_SYM_H_ +#endif // SYM_LIB_DEFINED diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/user_settings.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/user_settings.h index 3c0f6d033..168fcb38c 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/user_settings.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/Wolf/user_settings.h @@ -55,17 +55,17 @@ #define WOLFSSL_AES_DIRECT /* Enable/Disable algorithm support based on TPM implementation header */ -#ifdef ALG_SHA256 +#if ALG_SHA256 #define WOLFSSL_SHA256 #endif -#if ALG_SHA384 || ALG_SHA512 || defined(WOLFSSL_LIB) +#if ALG_SHA384 || ALG_SHA512 #define WOLFSSL_SHA384 #define WOLFSSL_SHA512 #endif -#if ALG_TDES || defined(WOLFSSL_LIB) +#if ALG_TDES #define WOLFSSL_DES_ECB #endif -#if ALG_RSA || defined(WOLFSSL_LIB) +#if ALG_RSA /* Turn on RSA key generation functionality */ #define WOLFSSL_KEY_GEN #endif diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/X509.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/X509.h index 3caf36100..ef3332c2d 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/X509.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/X509.h @@ -66,6 +66,15 @@ #define EXTENSIONS_REF (SUBJECT_PUBLIC_KEY_REF + 1) #define REF_COUNT (EXTENSIONS_REF + 1) +#undef MAKE_OID +#ifdef _X509_SPT_ +# define MAKE_OID(NAME) \ + const BYTE OID##NAME[] = {OID##NAME##_VALUE} +#else +# define MAKE_OID(NAME) \ + extern const BYTE OID##NAME[] +#endif + //** Structures @@ -84,4 +93,42 @@ typedef union x509KeyUsageUnion { UINT32 integer; } x509KeyUsageUnion; + +//** Global X509 Constants +// These values are instanced by X509_spt.c and referenced by other X509-related +// files. + + +// This is the DER-encoded value for the Key Usage OID (2.5.29.15). This is the +// full OID, not just the numeric value +#define OID_KEY_USAGE_EXTENSTION_VALUE 0x06, 0x03, 0x55, 0x1D, 0x0F +MAKE_OID(_KEY_USAGE_EXTENSTION); + +// This is the DER-encoded value for the TCG-defined TPMA_OBJECT OID +// (2.23.133.10.1.1.1) +#define OID_TCG_TPMA_OBJECT_VALUE 0x06, 0x07, 0x67, 0x81, 0x05, 0x0a, 0x01, \ + 0x01, 0x01 +MAKE_OID(_TCG_TPMA_OBJECT); + +#ifdef _X509_SPT_ +const x509KeyUsageUnion keyUsageSign = { TPMA_X509_KEY_USAGE_INITIALIZER( + /* digitalsignature */ 1, /* nonrepudiation */ 0, + /* keyencipherment */ 0, /* dataencipherment */ 0, + /* keyagreement */ 0, /* keycertsign */ 1, + /* crlsign */ 1, /* encipheronly */ 0, + /* decipheronly */ 0, /* bits_at_9 */ 0) }; + +const x509KeyUsageUnion keyUsageDecrypt = { TPMA_X509_KEY_USAGE_INITIALIZER( + /* digitalsignature */ 0, /* nonrepudiation */ 0, + /* keyencipherment */ 1, /* dataencipherment */ 1, + /* keyagreement */ 1, /* keycertsign */ 0, + /* crlsign */ 0, /* encipheronly */ 1, + /* decipheronly */ 1, /* bits_at_9 */ 0) }; +#else +extern x509KeyUsageUnion keyUsageSign; +extern x509KeyUsageUnion keyUsageDecrypt; +#endif + +#undef MAKE_OID + #endif // _X509_H_ diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/prototypes/CommandAudit_fp.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/prototypes/CommandAudit_fp.h index 86852a86a..a9bfa78a8 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/prototypes/CommandAudit_fp.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/prototypes/CommandAudit_fp.h @@ -41,7 +41,7 @@ #define _COMMAND_AUDIT_FP_H_ //*** CommandAuditPreInstall_Init() -// This function initializes the command audit list. This function is simulates +// This function initializes the command audit list. This function simulates // the behavior of manufacturing. A function is used instead of a structure // definition because this is easier than figuring out the initialization value // for a bit array. diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/prototypes/CryptRand_fp.h b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/prototypes/CryptRand_fp.h index a6dc2cec6..34e9cc6ec 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/prototypes/CryptRand_fp.h +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/include/prototypes/CryptRand_fp.h @@ -102,7 +102,7 @@ CryptRandomStir( // Generate a 'randomSize' number or random bytes. LIB_EXPORT UINT16 CryptRandomGenerate( - INT32 randomSize, + UINT16 randomSize, BYTE *buffer ); diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/X509/X509_spt.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/X509/X509_spt.c index 93d3af911..77fd96ba9 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/X509/X509_spt.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/X509/X509_spt.c @@ -36,7 +36,7 @@ #include "Tpm.h" #include "TpmASN1.h" #include "TpmASN1_fp.h" -#include "OIDs.h" +#define _X509_SPT_ #include "X509.h" #include "X509_spt_fp.h" #if ALG_RSA @@ -49,20 +49,7 @@ //# include "X509_SM2_fp.h" #endif // ALG_RSA -//** Global X509 Constants -const x509KeyUsageUnion keyUsageSign = { TPMA_X509_KEY_USAGE_INITIALIZER( - /* digitalsignature */ 1, /* nonrepudiation */ 0, - /* keyencipherment */ 0, /* dataencipherment */ 0, - /* keyagreement */ 0, /* keycertsign */ 1, - /* crlsign */ 1, /* encipheronly */ 0, - /* decipheronly */ 0, /* bits_at_9 */ 0) }; -const x509KeyUsageUnion keyUsageDecrypt = { TPMA_X509_KEY_USAGE_INITIALIZER( - /* digitalsignature */ 0, /* nonrepudiation */ 0, - /* keyencipherment */ 1, /* dataencipherment */ 1, - /* keyagreement */ 1, /* keycertsign */ 0, - /* crlsign */ 0, /* encipheronly */ 1, - /* decipheronly */ 1, /* bits_at_9 */ 0) }; //** Unmarshaling Functions @@ -199,18 +186,19 @@ X509ProcessExtensions( // keyUsage.integer = value; // For KeyUsage: - // the 'sign' attribute is SET if Key Usage includes signing - if(((keyUsageSign.integer & keyUsage.integer) != 0 - && !IS_ATTRIBUTE(attributes, TPMA_OBJECT, sign)) - // and the 'decrypt' attribute is Set if Key Usage includes decryption uses - || ((keyUsageDecrypt.integer & keyUsage.integer) != 0 - && !IS_ATTRIBUTE(attributes, TPMA_OBJECT, decrypt)) - // Check that 'fixedTPM' is SET if Key Usage is non-repudiation - || (IS_ATTRIBUTE(keyUsage.x509, TPMA_X509_KEY_USAGE, nonrepudiation) - && !IS_ATTRIBUTE(attributes, TPMA_OBJECT, fixedTPM)) - || (IS_ATTRIBUTE(keyUsage.x509, TPMA_X509_KEY_USAGE, keyAgreement) - && !IS_ATTRIBUTE(attributes, TPMA_OBJECT, restricted)) - ) + // the 'sign' attribute is SET if Key Usage includes signing + if( ( (keyUsageSign.integer & keyUsage.integer) != 0 + && !IS_ATTRIBUTE(attributes, TPMA_OBJECT, sign)) + // OR the 'decrypt' attribute is Set if Key Usage includes decryption uses + || ( (keyUsageDecrypt.integer & keyUsage.integer) != 0 + && !IS_ATTRIBUTE(attributes, TPMA_OBJECT, decrypt)) + // OR that 'fixedTPM' is SET if Key Usage is non-repudiation + || ( IS_ATTRIBUTE(keyUsage.x509, TPMA_X509_KEY_USAGE, nonrepudiation) + && !IS_ATTRIBUTE(attributes, TPMA_OBJECT, fixedTPM)) + // OR that 'restricted' is SET if Key Usage is key agreement + || ( IS_ATTRIBUTE(keyUsage.x509, TPMA_X509_KEY_USAGE, keyAgreement) + && !IS_ATTRIBUTE(attributes, TPMA_OBJECT, restricted)) + ) return TPM_RCS_ATTRIBUTES; } else diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/Attestation/CertifyX509.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/Attestation/CertifyX509.c index e651f1030..961ed47d7 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/Attestation/CertifyX509.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/Attestation/CertifyX509.c @@ -38,13 +38,9 @@ #include "TpmASN1_fp.h" #include "X509_spt_fp.h" #include "Attest_spt_fp.h" -#include "Platform_fp.h" - #if CC_CertifyX509 // Conditional expansion of this file -#define CERTIFYX509_DEBUG YES - /*(See part 3 specification) // Certify */ @@ -78,16 +74,16 @@ TPM2_CertifyX509( // certTBS holds an array of pointers and lengths. Each entry references the // corresponding value in a TBSCertificate structure. For example, the 1th // element references the version number - stringRef certTBS[REF_COUNT] = {0}; + stringRef certTBS[REF_COUNT] = {{0}}; #define ALLOWED_SEQUENCES (SUBJECT_PUBLIC_KEY_REF - SIGNATURE_REF) - stringRef partial[ALLOWED_SEQUENCES] = {0}; + stringRef partial[ALLOWED_SEQUENCES] = {{0}}; INT16 countOfSequences = 0; INT16 i; // #if CERTIFYX509_DEBUG DebugFileOpen(); DebugDumpBuffer(in->partialCertificate.t.size, in->partialCertificate.t.buffer, - (BYTE *)"partialCertificate"); + "partialCertificate"); #endif // Input Validation @@ -256,7 +252,7 @@ TPM2_CertifyX509( MemoryCopy(fill, certTBS[j].buf, certTBS[j].len); fill += certTBS[j].len; } - DebugDumpBuffer((int)(fill - &fullTBS[0]), fullTBS, (BYTE *)"\nfull TBS"); + DebugDumpBuffer((int)(fill - &fullTBS[0]), fullTBS, "\nfull TBS"); } #endif @@ -269,7 +265,7 @@ TPM2_CertifyX509( out->addedToCertificate.t.size); #if CERTIFYX509_DEBUG DebugDumpBuffer(out->addedToCertificate.t.size, out->addedToCertificate.t.buffer, - (BYTE *)"\naddedToCertificate"); + "\naddedToCertificate"); #endif // only thing missing is the signature result = CryptSign(signKey, &in->inScheme, &out->tbsDigest, &out->signature); diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/EA/PolicyAuthorizeNV.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/EA/PolicyAuthorizeNV.c index e151b3dd1..019548a40 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/EA/PolicyAuthorizeNV.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/EA/PolicyAuthorizeNV.c @@ -35,8 +35,8 @@ #include "Tpm.h" #if CC_PolicyAuthorizeNV // Conditional expansion of this file -#include "Policy_spt_fp.h" #include "PolicyAuthorizeNV_fp.h" +#include "Policy_spt_fp.h" /*(See part 3 specification) // Change policy by a signature from authority diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/Startup/Startup.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/Startup/Startup.c index 95867116e..1039e95aa 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/Startup/Startup.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/Startup/Startup.c @@ -147,11 +147,13 @@ TPM2_Startup( // command has been received. OK = OK && TPMRegisterStartup(); +#ifdef VENDOR_PERMANENT // Read the platform unique value that is used as VENDOR_PERMANENT // authorization value g_platformUniqueDetails.t.size = (UINT16)_plat__GetUnique(1, sizeof(g_platformUniqueDetails.t.buffer), g_platformUniqueDetails.t.buffer); +#endif // Start up subsystems // Start set the safe flag diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/Vendor/Vendor_TCG_Test.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/Vendor/Vendor_TCG_Test.c index 929b14374..c06d50813 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/Vendor/Vendor_TCG_Test.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/command/Vendor/Vendor_TCG_Test.c @@ -33,9 +33,9 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "Tpm.h" -#include "Vendor_TCG_Test_fp.h" #if CC_Vendor_TCG_Test // Conditional expansion of this file +#include "Vendor_TCG_Test_fp.h" TPM_RC TPM2_Vendor_TCG_Test( diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/AlgorithmTests.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/AlgorithmTests.c index 244f42fe4..9d203e5f4 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/AlgorithmTests.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/AlgorithmTests.c @@ -354,7 +354,7 @@ RsaKeyInitialize( } //*** TestRsaEncryptDecrypt() -// These test are for an public key encryption that uses a random value +// These tests are for a public key encryption that uses a random value. static TPM_RC TestRsaEncryptDecrypt( TPM_ALG_ID scheme, // IN: the scheme diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptCmac.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptCmac.c index 6a9af39d0..7440d5f6b 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptCmac.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptCmac.c @@ -39,11 +39,14 @@ // encryption functions of the selected symmetric cryptographic library. //** Includes, Defines, and Typedefs +#define _CRYPT_HASH_C_ #include "Tpm.h" #include "CryptSym.h" #if ALG_CMAC + //** Functions + //*** CryptCmacStart() // This is the function to start the CMAC sequence operation. It initializes the // dispatch functions for the data and end operations for CMAC and initializes the diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptEccData.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptEccData.c index 9e40a0474..06fb85e90 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptEccData.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptEccData.c @@ -154,7 +154,7 @@ ECC_CONST(NIST_P192_n, 24, TO_ECC_192( (bigNum)&NIST_P192_p, (bigNum)&NIST_P192_n, (bigNum)&NIST_P192_h, (bigNum)&NIST_P192_a, (bigNum)&NIST_P192_b, {(bigNum)&NIST_P192_gX, (bigNum)&NIST_P192_gY, (bigNum)&NIST_P192_gZ}}; - + #else const ECC_CURVE_DATA NIST_P192 = { &NIST_P192_p.b, &NIST_P192_n.b, &NIST_P192_h.b, diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptHash.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptHash.c index 9df051df7..3f6ac63a2 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptHash.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptHash.c @@ -37,6 +37,8 @@ // This file contains implementation of cryptographic functions for hashing. // //** Includes, Defines, and Types + +#define _CRYPT_HASH_C_ #include "Tpm.h" #include "CryptHash_fp.h" #include "CryptHash.h" @@ -97,8 +99,8 @@ CryptHashInit( } //*** CryptHashStartup() -// This function is called by TPM2_Startup() in case there is work to do at startup. -// Currently, this is a placeholder. +// This function is called by TPM2_Startup(). It checks that the size of the +// HashDefArray is consistent with the HASH_COUNT. BOOL CryptHashStartup( void @@ -121,7 +123,7 @@ CryptGetHashDef( TPM_ALG_ID hashAlg ) { - INT16 i; + size_t i; #define HASHES (sizeof(HashDefArray) / sizeof(PHASH_DEF)) for(i = 0; i < HASHES; i++) { diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptPrime.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptPrime.c index 98a7652f4..14af46216 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptPrime.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptPrime.c @@ -296,7 +296,20 @@ RsaCheckPrime( } //*** AdjustPrimeCandiate() -// This function adjusts the candidate prime so that it is odd and > root(2)/2. +// For this math, we assume that the RSA numbers are fixed-point numbers with +// the decimal point to the "left" of the most significant bit. This approach helps +// make it clear what is happening with the MSb of the values. +// The two RSA primes have to be large enough so that their product will be a number +// with the necessary number of significant bits. For example, we want to be able +// to multiply two 1024-bit numbers to produce a number with 2028 significant bits. If +// we accept any 1024-bit prime that has its MSb set, then it is possible to produce a +// product that does not have the MSb SET. For example, if we use tiny keys of 16 bits +// and have two 8-bit 'primes' of 0x80, then the public key would be 0x4000 which is +// only 15-bits. So, what we need to do is made sure that each of the primes is large +// enough so that the product of the primes is twice as large as each prime. A little +// arithmetic will show that the only way to do this is to make sure that each of the +// primes is no less than root(2)/2. That's what this functions does. +// This function adjusts the candidate prime so that it is odd and >= root(2)/2. // This allows the product of these two numbers to be .5, which, in fixed point // notation means that the most significant bit is 1. // For this routine, the root(2)/2 (0.7071067811865475) approximated with 0xB505 @@ -305,30 +318,33 @@ RsaCheckPrime( // amount of time all the other computations take, reducing the error is not much of // a cost, but it isn't totally required either. // -// The code maps the most significant crypt_uword_t in 'prime' so that a 32-/64-bit -// value of 0 to 0xB5050...0 and a value of 0xff...f to 0xff...f. It also sets the LSb -// of 'prime' to make sure that the number is odd. +// This function can be replaced with a function that just sets the two most +// significant bits of each prime candidate without introducing any computational +// issues. // -// This code has been fixed so that it will work with a RADIX_SIZE == 64. // -// The function also puts the number on a field boundary. LIB_EXPORT void RsaAdjustPrimeCandidate( bigNum prime ) { - crypt_uword_t msw = prime->d[prime->size - 1]; - crypt_uword_t adjusted; + UINT32 msw; + UINT32 adjusted; + + // If the radix is 32, the compiler should turn this into a simple assignment + msw = prime->d[prime->size - 1] >> ((RADIX_BITS == 64) ? 32 : 0); + // Multiplying 0xff...f by 0x4AFB gives 0xff..f - 0xB5050...0 + adjusted = (msw >> 16) * 0x4AFB; + adjusted += ((msw & 0xFFFF) * 0x4AFB) >> 16; + adjusted += 0xB5050000UL; #if RADIX_BITS == 64 -# define ADD_CONST ((crypt_uword_t)0xB505000000000000ULL) + // Save the low-order 32 bits + prime->d[prime->size - 1] &= 0xFFFFFFFFUL; + // replace the upper 32-bits + prime->d[prime->size -1] |= ((crypt_uword_t)adjusted << 32); #else -# define ADD_CONST ((crypt_uword_t)0xB5050000UL) + prime->d[prime->size - 1] = (crypt_uword_t)adjusted; #endif - // Multiplying 0xff...f by 0x4AFB gives 0xff..f - 0xB5050...0 - adjusted = (crypt_uword_t)(msw >> 16) * (crypt_uword_t)0x4AFB; - adjusted += ((msw & 0xFFFF) * (crypt_uword_t)0x4AFB) >> 16; - adjusted += ADD_CONST; - prime->d[prime->size - 1] = adjusted; // make sure the number is odd prime->d[0] |= 1; } @@ -338,10 +354,11 @@ RsaAdjustPrimeCandidate( // for an RSA prime. TPM_RC BnGeneratePrimeForRSA( - bigNum prime, - UINT32 bits, - UINT32 exponent, - RAND_STATE *rand + bigNum prime, // IN/OUT: points to the BN that will get the + // random value + UINT32 bits, // IN: number of bits to get + UINT32 exponent, // IN: the exponent + RAND_STATE *rand // IN: the random state ) { BOOL found = FALSE; @@ -350,13 +367,14 @@ BnGeneratePrimeForRSA( pAssert(prime->allocated >= BITS_TO_CRYPT_WORDS(bits)); // Only try to handle specific sizes of keys in order to save overhead pAssert((bits % 32) == 0); - prime->size = BITS_TO_CRYPT_WORDS(bits); - while(!found) { - DRBG_Generate(rand, (BYTE *)prime->d, (UINT16)BITS_TO_BYTES(bits)); - if(g_inFailureMode) +// The change below is to make sure that all keys that are generated from the same +// seed value will be the same regardless of the endianess or word size of the CPU. +// DRBG_Generate(rand, (BYTE *)prime->d, (UINT16)BITS_TO_BYTES(bits));// old +// if(g_inFailureMode) // old + if(!BnGetRandomBits(prime, bits, rand)) // new return TPM_RC_FAILURE; RsaAdjustPrimeCandidate(prime); found = RsaCheckPrime(prime, exponent, rand) == TPM_RC_SUCCESS; diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptPrimeSieve.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptPrimeSieve.c index b50f1fad3..6c9c0c174 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptPrimeSieve.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptPrimeSieve.c @@ -324,19 +324,33 @@ PrimeSieve( if(next == 0) goto done; r = composite % next; - // these computations deal with the fact that the field starts at some - // arbitrary offset within the number space. If the field were all numbers, - // then we would have gone through some number of bit clearings before we - // got to the start of this range. We don't know how many there were before, - // but we can tell from the remainder whether we are on an even or odd + // these computations deal with the fact that we have picked a field-sized + // range that is aligned to a 105 count boundary. The problem is, this field + // only contains odd numbers. If we take our prime guess and walk through all + // the numbers using that prime as the 'stride', then every other 'stride' is + // going to be an even number. So, we are actually counting by 2 * the stride + // We want the count to start on an odd number at the start of our field. That + // is, we want to assume that we have counted up to the edge of the field by + // the 'stride' and now we are going to start flipping bits in the field as we + // continue to count up by 'stride'. If we take the base of our field and + // divide by the stride, we find out how much we find out how short the last + // count was from reaching the edge of the bit field. Say we get a quotient of + // 3 and remainder of 1. This means that after 3 strides, we are 1 short of + // the start of the field and the next stride will either land within the + // field or step completely over it. The confounding factor is that our field + // only contains odd numbers and our stride is actually 2 * stride. If the + // quoitent is even, then that means that when we add 2 * stride, we are going + // to hit another even number. So, we have to know if we need to back off + // by 1 stride before we start couting by 2 * stride. + // We can tell from the remainder whether we are on an even or odd // stride when we hit the beginning of the table. If we are on an odd stride // (r & 1), we would start half a stride in (next - r)/2. If we are on an - // even stride, we need 1.5 strides (next + r/2) because the table only has + // even stride, we need 0.5 strides (next - r/2) because the table only has // odd numbers. If the remainder happens to be zero, then the start of the // table is on stride so no adjustment is necessary. if(r & 1) j = (next - r) / 2; else if(r == 0) j = 0; - else j = next - r / 2; + else j = next - (r / 2); for(; j < fieldBits; j += next) ClearBit(j, field, fieldSize); } @@ -466,6 +480,7 @@ PrimeSelectWithSieve( #if RSA_INSTRUMENT static char a[256]; +//*** PrintTuple() char * PrintTuple( UINT32 *i @@ -477,6 +492,7 @@ PrintTuple( #define CLEAR_VALUE(x) memset(x, 0, sizeof(x)) +//*** RsaSimulationEnd() void RsaSimulationEnd( void @@ -510,6 +526,7 @@ RsaSimulationEnd( CLEAR_VALUE(bitsInFieldAfterSieve); } +//*** GetSieveStats() LIB_EXPORT void GetSieveStats( uint32_t *trials, @@ -541,10 +558,14 @@ GetSieveStats( #endif // RSA_KEY_SIEVE #if !RSA_INSTRUMENT + +//*** RsaSimulationEnd() +// Stub for call when not doing instrumentation. void RsaSimulationEnd( void ) { + return; } #endif \ No newline at end of file diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptRand.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptRand.c index 623d40353..c41eb41af 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptRand.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptRand.c @@ -551,8 +551,7 @@ DRBG_SelfTest( //** Public Interface //*** Description // The functions in this section are the interface to the RNG. These -// are the functions that are used by TPM.lib. Other functions are only -// visible to programs in the LtcCryptoEngine. +// are the functions that are used by TPM.lib. //*** CryptRandomStir() // This function is used to cause a reseed. A DRBG_SEED amount of entropy is @@ -605,18 +604,16 @@ CryptRandomStir( // Generate a 'randomSize' number or random bytes. LIB_EXPORT UINT16 CryptRandomGenerate( - INT32 randomSize, + UINT16 randomSize, BYTE *buffer ) { - if(randomSize > UINT16_MAX) - randomSize = UINT16_MAX; - return DRBG_Generate((RAND_STATE *)&drbgDefault, buffer, (UINT16)randomSize); + return DRBG_Generate((RAND_STATE *)&drbgDefault, buffer, randomSize); } -//**** DRBG_InstantiateSeededKdf() +//*** DRBG_InstantiateSeededKdf() // This function is used to instantiate a KDF-based RNG. This is used for derivations. // This function always returns TRUE. LIB_EXPORT BOOL @@ -643,7 +640,7 @@ DRBG_InstantiateSeededKdf( return TRUE; } -//**** DRBG_AdditionalData() +//*** DRBG_AdditionalData() // Function to reseed the DRBG with additional entropy. This is normally called // before computing the protection value of a primary key in the Endorsement // hierarchy. @@ -662,10 +659,12 @@ DRBG_AdditionalData( } -//**** DRBG_InstantiateSeeded() +//*** DRBG_InstantiateSeeded() // This function is used to instantiate a random number generator from seed values. // The nominal use of this generator is to create sequences of pseudo-random -// numbers from a seed value. This function always returns TRUE. +// numbers from a seed value. +// Return Type: TPM_RC +// TPM_RC_FAILURE DRBG self-test failure LIB_EXPORT TPM_RC DRBG_InstantiateSeeded( DRBG_STATE *drbgState, // IN/OUT: buffer to hold the state @@ -713,7 +712,7 @@ DRBG_InstantiateSeeded( return TPM_RC_SUCCESS; } -//**** CryptRandStartup() +//*** CryptRandStartup() // This function is called when TPM_Startup is executed. This function always returns // TRUE. LIB_EXPORT BOOL @@ -755,10 +754,10 @@ CryptRandInit( // This function generates a random sequence according SP800-90A. // If 'random' is not NULL, then 'randomSize' bytes of random values are generated. // If 'random' is NULL or 'randomSize' is zero, then the function returns -// TRUE without generating any bits or updating the reseed counter. -// This function returns 0 if a reseed is required. Otherwise, it returns the -// number of bytes produced which could be less than the number requested if the -// request is too large. +// zero without generating any bits or updating the reseed counter. +// This function returns the number of bytes produced which could be less than the +// number requested if the request is too large ("too large" is implementation +// dependent.) LIB_EXPORT UINT16 DRBG_Generate( RAND_STATE *state, @@ -768,6 +767,8 @@ DRBG_Generate( { if(state == NULL) state = (RAND_STATE *)&drbgDefault; + if(random == NULL) + return 0; // If the caller used a KDF state, generate a sequence from the KDF not to // exceed the limit. @@ -776,9 +777,7 @@ DRBG_Generate( KDF_STATE *kdf = (KDF_STATE *)state; UINT32 counter = (UINT32)kdf->counter; INT32 bytesLeft = randomSize; - - if(random == NULL) - return 0; +// // If the number of bytes to be returned would put the generator // over the limit, then return 0 if((((kdf->counter * kdf->digestSize) + randomSize) * 8) > kdf->limit) diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptRsa.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptRsa.c index 4a18d4b46..dc0ceed57 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptRsa.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptRsa.c @@ -330,7 +330,7 @@ OaepEncode( INT32 i; BYTE mySeed[MAX_DIGEST_SIZE]; BYTE *seed = mySeed; - INT32 hLen = CryptHashGetDigestSize(hashAlg); + UINT16 hLen = CryptHashGetDigestSize(hashAlg); BYTE mask[MAX_RSA_KEY_BYTES]; BYTE *pp; BYTE *pm; @@ -340,7 +340,7 @@ OaepEncode( // A value of zero is not allowed because the KDF can't produce a result // if the digest size is zero. - if(hLen <= 0) + if(hLen == 0) return TPM_RC_VALUE; // Basic size checks diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptSmac.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptSmac.c index b01dc49b7..cd584cf22 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptSmac.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptSmac.c @@ -39,6 +39,7 @@ // encryption functions of the selected symmetric cryptographic library. //** Includes, Defines, and Typedefs +#define _CRYPT_HASH_C_ #include "Tpm.h" #if SMAC_IMPLEMENTED diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptUtil.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptUtil.c index d2a3abd84..fdea4f6da 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptUtil.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/CryptUtil.c @@ -1550,104 +1550,6 @@ CryptGetTestResult( return TPM_RC_SUCCESS; } -//*** CryptIsUniqueSizeValid() -// This function validates that the unique values are consistent. -// NOTE: This is not a comprehensive test of the public key. -// Return Type: BOOL -// TRUE(1) sizes are consistent -// FALSE(0) sizes are not consistent -BOOL -CryptIsUniqueSizeValid( - TPMT_PUBLIC *publicArea // IN: the public area to check - ) -{ - BOOL consistent = FALSE; - UINT16 keySizeInBytes; - - switch(publicArea->type) - { -#if ALG_RSA - case ALG_RSA_VALUE: - keySizeInBytes = BITS_TO_BYTES( - publicArea->parameters.rsaDetail.keyBits); - consistent = publicArea->unique.rsa.t.size == keySizeInBytes; - break; -#endif // ALG_RSA -#if ALG_ECC - case ALG_ECC_VALUE: - { - keySizeInBytes = BITS_TO_BYTES(CryptEccGetKeySizeForCurve( - publicArea->parameters.eccDetail.curveID)); - consistent = keySizeInBytes > 0 - && publicArea->unique.ecc.x.t.size <= keySizeInBytes - && publicArea->unique.ecc.y.t.size <= keySizeInBytes; - } - break; -#endif // ALG_ECC - default: - // For SYMCIPHER and KEYDEDHASH objects, the unique field is the size - // of the nameAlg digest. - consistent = publicArea->unique.sym.t.size - == CryptHashGetDigestSize(publicArea->nameAlg); - break; - } - return consistent; -} - -//*** CryptIsSensitiveSizeValid() -// This function is used by TPM2_LoadExternal() to validate that the sensitive area -// contains a 'sensitive' value that is consistent with the values in the public -// area. -BOOL -CryptIsSensitiveSizeValid( - TPMT_PUBLIC *publicArea, // IN: the object's public part - TPMT_SENSITIVE *sensitiveArea // IN: the object's sensitive part - ) -{ - BOOL consistent; - UINT16 keySizeInBytes; - - switch(publicArea->type) - { -#if ALG_RSA - case ALG_RSA_VALUE: - // sensitive prime value has to be half the size of the public modulus - keySizeInBytes = BITS_TO_BYTES(publicArea->parameters.rsaDetail.keyBits); - consistent = - ((sensitiveArea->sensitive.rsa.t.size * 2) == keySizeInBytes); - break; -#endif -#if ALG_ECC - case ALG_ECC_VALUE: - keySizeInBytes = BITS_TO_BYTES(CryptEccGetKeySizeForCurve( - publicArea->parameters.eccDetail.curveID)); - consistent = (keySizeInBytes > 0) - && (sensitiveArea->sensitive.ecc.t.size == keySizeInBytes); - break; - -#endif - case ALG_SYMCIPHER_VALUE: - keySizeInBytes = - BITS_TO_BYTES(publicArea->parameters.symDetail.sym.keyBits.sym); - consistent = keySizeInBytes == sensitiveArea->sensitive.sym.t.size; - break; - case ALG_KEYEDHASH_VALUE: - keySizeInBytes = CryptHashGetBlockSize(publicArea->nameAlg); - // if the block size is 0, then the algorithm is TPM_ALG_NULL and the - // size of the private part is limited to 128. If the algorithm block - // size is over 128 bytes, then the size is limited to 128 bytes for - // interoperability reasons. - if((keySizeInBytes == 0) || (keySizeInBytes > 128)) - keySizeInBytes = 128; - consistent = sensitiveArea->sensitive.bits.t.size <= keySizeInBytes; - break; - default: - consistent = TRUE; - break; - } - return consistent; -} - //*** CryptValidateKeys() // This function is used to verify that the key material of and object is valid. // For a 'publicOnly' object, the key is verified for size and, if it is an ECC @@ -1852,20 +1754,6 @@ CryptValidateKeys( return TPM_RC_SUCCESS; } -//*** CryptAlgSetImplemented() -// This function initializes the bit vector with one bit for each implemented -// algorithm. This function is called from _TPM_Init(). The vector of implemented -// algorithms should be generated by the part 2 parser so that the -// 'g_implementedAlgorithms' vector can be a constant. That's not how it is now -void -CryptAlgsSetImplemented( - void - ) -{ - AlgorithmGetImplementedVector(&g_implementedAlgorithms); -} - - //*** CryptSelectMac() // This function is used to set the MAC scheme based on the key parameters and // the input scheme. diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/RsaKeyCache.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/RsaKeyCache.c index 69ba52e86..ba8dec83d 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/RsaKeyCache.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/RsaKeyCache.c @@ -66,8 +66,6 @@ #if USE_RSA_KEY_CACHE #include - -#include "Platform_fp.h" #include "RsaKeyCache_fp.h" #if CRT_FORMAT_RSA == YES diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/ltc/TpmToLtcSupport.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/ltc/TpmToLtcSupport.c index 3915c5944..0dcb79ebe 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/ltc/TpmToLtcSupport.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/ltc/TpmToLtcSupport.c @@ -46,7 +46,7 @@ #if defined(HASH_LIB_LTC) || defined(MATH_LIB_LTC) || defined(SYM_LIB_LTC) // This state is used because there is no way to pass the random number state -// to LibTopCrypt. I do not think that this is currently an issue because... +// to LibTomCrypt. I do not think that this is currently an issue because... // Heck, just put in an assert and see what happens. static void *s_randState; diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/ossl/TpmToOsslMath.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/ossl/TpmToOsslMath.c index 4d8b18741..042709ec2 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/ossl/TpmToOsslMath.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/ossl/TpmToOsslMath.c @@ -32,25 +32,13 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -//** Introduction -// -// This file contains the math functions that are not implemented in the BnMath -// library (yet). These math functions will call the OpenSSL library to execute -// the operations. There is a difference between the internal format and the -// OpenSSL format. To call the OpenSSL function, a BIGNUM structure is created -// for each passed variable. The sizes in the bignum_t are copied and the 'd' -// pointer in the BIGNUM is set to point to the 'd' parameter of the bignum_t. -// On return, SetSizeOsslToTpm is used for each returned variable to make sure that -// the pointers are not changed. The size of the returned BIGGNUM is copied to -// bignum_t. - //** Introduction // The functions in this file provide the low-level interface between the TPM code // and the big number and elliptic curve math routines in OpenSSL. // // Most math on big numbers require a context. The context contains the memory in // which OpenSSL creates and manages the big number values. When a OpenSSL math -// will be called that modifies a BIGNUM value, that value must be created in +// function will be called that modifies a BIGNUM value, that value must be created in // an OpenSSL context. The first line of code in such a function must be: // OSSL_ENTER(); and the last operation before returning must be OSSL_LEAVE(). // OpenSSL variables can then be created with BnNewVariable(). Constant values to be diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/wolf/wolfssl.vcxproj b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/wolf/wolfssl.vcxproj index dd13552ab..d36991af2 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/wolf/wolfssl.vcxproj +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/crypt/wolf/wolfssl.vcxproj @@ -30,40 +30,40 @@ {73973223-5EE8-41CA-8E88-1D60E89A237B} wolfssl Win32Proj - 10.0.16299.0 + 10.0.17763.0 $(SolutionDir)..\external\wolfssl\ StaticLibrary - v140 + v141 Unicode true StaticLibrary - v140 + v141 Unicode true StaticLibrary - v140 + v141 Unicode StaticLibrary - v140 + v141 Unicode StaticLibrary - v140 + v141 Unicode StaticLibrary - v140 + v141 Unicode diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/main/CommandDispatcher.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/main/CommandDispatcher.c index 6aaf36d24..bc55a3b0e 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/main/CommandDispatcher.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/main/CommandDispatcher.c @@ -153,7 +153,7 @@ ParseHandleBuffer( COMMAND_DESCRIPTOR_t *desc; BYTE *types; BYTE type; - BYTE dtype; + BYTE dType; // Make sure that nothing strange has happened pAssert(command->index @@ -174,15 +174,15 @@ ParseHandleBuffer( for(type = *types++; // check each byte to make sure that we have not hit the start // of the parameters - (dtype = (type & 0x7F)) < PARAMETER_FIRST_TYPE; + (dType = (type & 0x7F)) < PARAMETER_FIRST_TYPE; // get the next type type = *types++) { // See if unmarshaling of this handle type requires a flag - if(dtype < HANDLE_FIRST_FLAG_TYPE) + if(dType < HANDLE_FIRST_FLAG_TYPE) { // Look up the function to do the unmarshaling - NoFlagFunction *f = (NoFlagFunction *)UnmarshalArray[dtype]; + NoFlagFunction *f = (NoFlagFunction *)UnmarshalArray[dType]; // call it result = f(&(command->handles[command->handleNum]), &command->parameterBuffer, @@ -191,7 +191,7 @@ ParseHandleBuffer( else { // Look up the function - FlagFunction *f = UnmarshalArray[dtype]; + FlagFunction *f = UnmarshalArray[dType]; // Call it setting the flag to the appropriate value result = f(&(command->handles[command->handleNum]), @@ -417,7 +417,8 @@ CommandDispatcher( { const MARSHAL_t f = MarshalArray[dType]; - command->parameterSize += f(&commandOut[offset], &command->responseBuffer, + command->parameterSize += f(&commandOut[offset], + &command->responseBuffer, &maxOutSize); offset = *offsets++; } diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/main/SessionProcess.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/main/SessionProcess.c index 2e95d5112..bd7f89f1e 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/main/SessionProcess.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/main/SessionProcess.c @@ -1737,7 +1737,7 @@ CheckAuthNoSession( //** Response Session Processing //*** Introduction // -// The following functions build the session area in a response, and handle +// The following functions build the session area in a response and handle // the audit sessions (if present). // diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/subsystem/CommandAudit.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/subsystem/CommandAudit.c index 01995da39..306b39b92 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/subsystem/CommandAudit.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/subsystem/CommandAudit.c @@ -41,7 +41,7 @@ //** Functions //*** CommandAuditPreInstall_Init() -// This function initializes the command audit list. This function is simulates +// This function initializes the command audit list. This function simulates // the behavior of manufacturing. A function is used instead of a structure // definition because this is easier than figuring out the initialization value // for a bit array. diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/subsystem/NvDynamic.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/subsystem/NvDynamic.c index 578c99938..d73d4bf8d 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/subsystem/NvDynamic.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/subsystem/NvDynamic.c @@ -1706,7 +1706,7 @@ NvCapGetCounterNumber( static TPMA_NV NvSetStartupAttributes( TPMA_NV attributes, // IN: attributes to change - STARTUP_TYPE type // IN: start up type + STARTUP_TYPE type // IN: start up type ) { // Clear read lock diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/subsystem/PCR.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/subsystem/PCR.c index 0ef50136d..10a096878 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/subsystem/PCR.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/subsystem/PCR.c @@ -896,29 +896,6 @@ PCRRead( return; } -//*** PcrWrite() -// This function is used by _TPM_Hash_End to set a PCR to the computed hash -// of the H-CRTM event. -void -PcrWrite( - TPMI_DH_PCR handle, // IN: PCR handle to be extended - TPMI_ALG_HASH hash, // IN: hash algorithm of PCR - TPM2B_DIGEST *digest // IN: the new value - ) -{ - UINT32 pcr = handle - PCR_FIRST; - BYTE *pcrData; - - // Copy value to the PCR if it is allocated - pcrData = GetPcrPointer(hash, pcr); - if(pcrData != NULL) - { - MemoryCopy(pcrData, digest->t.buffer, digest->t.size); - } - - return; -} - //*** PCRAllocate() // This function is used to change the PCR allocation. // Return Type: TPM_RC diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/support/MathOnByteBuffers.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/support/MathOnByteBuffers.c index 1e933a354..5e68e2376 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/support/MathOnByteBuffers.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/support/MathOnByteBuffers.c @@ -263,19 +263,3 @@ ShiftLeft( return value; } -//*** IsNumeric() -// Verifies that all the characters are simple numeric (0-9) -BOOL -IsNumeric( - TPM2B *value -) -{ - UINT16 i; - for(i = 0; i < value->size; i++) - { - if(value->buffer[i] < '0' || value->buffer[i] > '9') - return FALSE; - } - return TRUE; -} - diff --git a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/support/Memory.c b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/support/Memory.c index 05e13f7d0..cbfa41d32 100644 --- a/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/support/Memory.c +++ b/simulator/ms-tpm-20-ref/TPMCmd/tpm/src/support/Memory.c @@ -189,7 +189,6 @@ Uint16ToByteArray( a[0] = (BYTE)(i); } - //*** Uint32ToByteArray() // Function to write an integer to a byte array void @@ -244,7 +243,6 @@ ByteArrayToUint16( return ((UINT16)a[0] << 8) + a[1]; } - //*** ByteArrayToUint32() // Function to write an integer to a byte array UINT32 diff --git a/simulator/simulator.go b/simulator/simulator.go index 280aa3968..034f650a3 100644 --- a/simulator/simulator.go +++ b/simulator/simulator.go @@ -57,6 +57,7 @@ func Get() (*Simulator, error) { } simulator := &Simulator{} + internal.Reset(true) if err := simulator.on(true); err != nil { return nil, err } @@ -82,6 +83,7 @@ func (s *Simulator) Reset() error { if err := s.off(); err != nil { return err } + internal.Reset(false) return s.on(false) } @@ -91,6 +93,7 @@ func (s *Simulator) ManufactureReset() error { if err := s.off(); err != nil { return err } + internal.Reset(true) return s.on(true) } @@ -119,12 +122,6 @@ func (s *Simulator) Close() error { } func (s *Simulator) on(manufactureReset bool) error { - internal.On() - if manufactureReset { - if err := internal.ManufactureReset(); err != nil { - return err - } - } // TPM2_Startup must be the first command the TPM receives. if err := tpm2.Startup(s, tpm2.StartupClear); err != nil { return fmt.Errorf("startup: %v", err) @@ -138,6 +135,5 @@ func (s *Simulator) off() error { if err := tpm2.Shutdown(s, tpm2.StartupClear); err != nil { return fmt.Errorf("shutdown: %v", err) } - internal.Off() return nil } diff --git a/simulator/simulator_test.go b/simulator/simulator_test.go index d3573d8c6..067199770 100644 --- a/simulator/simulator_test.go +++ b/simulator/simulator_test.go @@ -88,7 +88,7 @@ func TestGetRandom(t *testing.T) { // The default EK modulus returned by the simulator when using a seed of 0. func zeroSeedModulus() *big.Int { mod := new(big.Int) - mod.SetString("26477589937104991909107546555596844814208501488398993637176547657040026510855262969599454342201099113570046958586074392392826189046589605606588308257325163261342553439301667460931252566414147127913702995490057967486186645056306958312086007589909165009386429083077296377200887146918939772513316195006666792119837801758230035524859461860350033253189094242924143497565958844676091714149214599630067691603355200610080948040721792826555203794339873010858621008154912642347482410965625629019620301070822787536053368781567603344040355963007625122652644931867174203344607909482751447522901014476802272093691307744409028025073", 10) + mod.SetString("16916951631746795233120676661491589156159944041454533323301360736206690950055927665898258850365255777475324525235640153431219834851979041935421083247812345676551677241639541392158486693550125570954276972465867114995062336740464652481116557477039581976647612151813804384773839359390083864432536639577227083497558006614244043011423717921293964465162166865351126036685960128739613171620392174911624095420039156957292384191548425395162459332733115699189854006301807847331248289929021522087915411000598437989788501679617747304391662751900488011803826205901900186771991702576478232121332699862815915856148442279432061762451", 10) return mod }

    ^wTd)Yv28h@_%^RBlE|c_j_y?+K$^i zA-XSGU%3T#v#$BTBrneVVe-`O9≦BOU?+{klGb>nzsBr&Q|DB;`+n|lN-t{Wcw_-P+dO~ERJws7qoShyA;!FmMX*+CD?WGGv_yg##y zHC21)23+K4&iYzW?aNB66jO*&dD1(r3%j>X# zyl2Ge0H5GYR$3ugIxSdvfMt0Ei1N>zM{mx-nnnlcHa1**IupwW%Xjfi6%NTT9)Ypx zPhbIC2-H)8vXv@JXw?K|Qi>^`SqjGq57)&c&BQN|s{R0q$!qTsH^C*22XAJu0{Ptc zdWklz(DxtDC_+?SJ;pD9Al2}En*s9>vnk)>;Yx7MPqtLkwsDwt7(W=RhKL6ROW%Y< zb^W3v`+<0-{hz1!4f704CjWq$9qGmEBKM+qd2qH{JJR*?v`mRM(b}~n5-I^#0lHOg z$IADd{fF??Hduv;oQX*TX&cSh`GexT;fY6JX9TQ=JORZnY77qBmFLuw#V7S4mpQ%h zE#&Zqxr)JI%Qy~3>;d}7$!>I3c-Qprh|9@%WFLVnfzdleg9jez?LFVK9WYDxw*rf< zyU@>8EoY^|ctS7WG`FHnN!31g^{$Pb;+ZM>qFU5jl9L>Yw%mKxWo z8X|wJb|=|4_%}=-;;0FaCWE`1W#3ipN8q#x82u>^x+gJauxjnYcgX$Zl2xr=z+A~2Zx6W|+n*nnF!~iQwGSvG_gw+W3cFhgNaJHu% z(9jQBvno3l!e?7vAPd8O)y)MDX&>HI`kt_XZJt+qoxYfj88WIr7*xZ3N_IHzLul{e zK&3hU2uiquanaIVGO2fFgD-JP?9m+5R`;8xzC|&-`?Djb_P@?b_3+N_k6G!Ii{RaR zSmHQO&WoEnp9@pR$sXQb-6JPI0$1w`AQh@SSo=J`q^NSv__uO*p%I0Mb?c>w-tm>Q z2uOjvB|5%CR(Rk7c}sS-;r%!4rDDeHBYMUPRSng3rzm%SC`E$pzbVCi9>~bC0WjY4 zVQRmg);+6@xj6-M>W*%ZDXN*SaUfH8R<7~EUVtAvm7F}2=<%d}8=kyw&5in9^51p+ z5rDelYq&4?Js0@w-*f4l)%yNvu9$zCi{ps7t~CEuS~t(Pe! ziu9gqf9;o6B>qJ!>;xpil|wqdL;1aO<|}7w;7a)an)lO_%FD`7;awAOG1_rg?ksb@ zw9foe3-lHCK1L@xh)pjk4{AtgGkf5*lg8a45eNdbbH7l~X65;g27v)L9B3m6vr)}R za1K|a5$bfdqPY+Pt!V*dw41jI58tvL0+ zQyj+i^aafash*U4_}CJ*Abqy|(Lxq9@%x}Fs*Kf>!==fX#i*>1*`~|5_2R$hBau$a#SSl1?Stq(gEBHe!QosS+0%pg=1=W(RS%{Jno*X?%O*03HFu%Mker0`L{h3suG?jpIDd$4St37$m^ zem}z~PFGl^`iC2f+IUG-3LNZsezLzjL-H~!!gm)s*LQW>;6c2?>h+Y%lIO!ImJT9rbU*8fRZSqJs&S{ zo{fa9j&YjwKGpl;qGvHFR+DnT>2k=zW|_xKOsnaHhqfU-B+*3_V7qZk`1N8GR|;=Hl}iQr+@&XqcxKv`BAQH(RZtcr6GS?3XO z4}=>*uMqgr`l|->Uw(xhivT_eq>9?M5P#&s!FdE$Y@v$i+z{x$g#LJqd`hAdGw~SVdCNusC`L|#F#3PLq*16 z3+c(D`FNo8WpmY-x03zK$t%}MMupt(wZR6o*3#G?eUCC4zpkEmqmZBIGP%K)c?!Ls zl$YuKT&8Ri-BKaa_wKwh^L}|IYvmCDAifQZhX*M?)UO_h>tt0!WM|cEY)zW|e2ooa zSXb} zKd!p?3+p+w8Cqi{SDMPSUCYbUl~Rw(IdaGOXj2~7GRpKu=JCWc}@r9=Y|8%Yn2tDq{V5#ma<&-llX8M;Q6mj zFEY<-0c9m=a2p(WSuQsoJOggM{eAh@0CDUO;N{-~=zy~8_Dx|hywm^eyQ@5XI~wsI zc9nIp5C0Iv1UTzswboakrgAOvsE9pFaUzhllD5U)mf|n7?8ApoH$KDp&hM^tSjIH_ z`jnbY^W~UMgtvf7XqioeV|*wQbd~f{`udj`6rJ7K7aa95y0vvp_1wz2G*eGhF>7ab z)6qq!>p31~Tix6|?Yb5iQke2jj=-XYqlXPjTjVqE1+@_zD(W@8r&Ru5-j=&x_o3O8 zB;K{JMNxTSjFP>tpqB6^>qacKO=^3stzST_fQd^VLzpcIG<&alrZ&2Kx^_LaOY&yW zHEpZK)d0*Jevo3cBX#TgmitJc3Ay9@S?EJq?H){a-g=GvWG~La#lQtV#fDZ9e1%69 z1WJr@=XcdDb;c#3K+^!NbqsW7p~%rwx94YL*4Mf6tu*-lsp?9YFEgllV z5(py4^Uw5PL+z;S^5>k)M#N7_O?~*`>0Va{Hc4b75-7AVKK4UCKRwGqG~u1!M6O3Y zj;xpve!8H)6jRmP6r9G`xi;lNuGgvK^+eS;JyvR?g5guHpWt4t?66pmn|4%2!D6hQ zWm59xe1JizmQYg{VBJYAkbYoazICNc8x_7|8Lw@e%Y&I^V+v)Uj!k!Qa3+_i80qRJJx zqSOxcr0I#!;Z<Yr;9H_$~UTh@rN^}4HNvr^KCMxnFM5$T|Z>xRiR zW-pM2e#W5c<;&ruN?Jm+hqpP+_T5s5q^rg}2EH14AfswPUHYK5NENoFN!P__5N4(^ zvcK%OvCnr6yg@+R?tErt6!*2tw6s3o|KQHPG zz9MUN33I>>BoL9Mg|;KYZGycRjgoIKzP9`3UrFu$CM7#w)^S|3MB%DFs&M)BAx+3h z@QBseZZ;ZQ^+{yX3$k&>!jt!Iikb^8cu8!v2n{^XcoS{=zCnBU5v5_G%q?^jAH2i+ zBx*;qv{dHCzv-Ejy64^cIttrio~DZdD;6QzUJ^FMI8HxC9B_OycEL&IMBt|#hZ z^QpP zo-JL5US@oYh9iQxEAkT;7k97WFFD_AN$J$xzl2!Ln(^j^_gZY5#pBpa*lCEz9tnv! z+OzTrA{G_VBxO}v)YKQj#7XiGQAZGe6jw&&(~Y;6geJWhvG%>$_~g4fkM{5~<>L zNyHujxG`S{&byyMON$$=w_w!-!kn@7?T47x5m++WJrAj^YT?0L>8j_U-=#2`pe62I z@KF~Eo0r^XpeGPaK6?`ELLlO4d!X=n|5}X%4AKQ%(C&yt!Lh3U^sxM5NbS@{QRNL5 zpg>jpcQGghw4NKp$$++Z zYVo&iw)t&*f7xagbI^wW!#3Lh*dP98n^ny7e_88aCLX-}Yk<-(6aV4&0MO{uftPE* zQhMyg%Dv~;M<7R5WB&!q4VoU<*DE8t#jb^FUuzYrGr(A!lUSfhmT1BdzM{rl_+a7Jf*w9UErCF5y3ZD@>C(Y-N7jPlK}k5SrE?LESQvbTCE%0 z+)fFfys-fJgbi+p{O9jDJ@hgE^8281256)huX6{%I(mTQJ2RLAYpPST@_JCyo z?gkp20WEDHlEQ;XrQV5FPz%!9c0;t(D!*w}6t(?9=@v7TAwWxV!m-ORK4kI9Nn84` z;oD3meKggza%ILgs(q@qCsPDle!TDKaNddcGA)bsS0k))GGKMvay>p4FD%72tv97~3+|wdZ?iVdh{OOe%b?9Zqs=d^Rr}{&hg^Q`}xSpkoK|MrWYa@!7 z86MuKB-3dGUOPJzYkX$JOFekqe4Fl@Ez7gSuVNqQkG2vl_=u$XEXDHl_h$Cs{Jrd~ z3+8rgB%W95OOOL@DTyJ_jY3Vvv4|?trIxq#)k&#C7FB!k)NGVpL}e95(z5+}(sMsM zz9<)M*?MzWb1f;~?#oTp5nPZ6$hXQ$GbPRAYcI7-Da4zZTHr*MsYK<$dW=XdCU@4S zrk2f56!e_YCOgoi$y#CWKAo?`k39y6-wdI)a)j5hggDP#AXJ*lhPa2ZOza+>Mo zV~xq9J5evoB(vu*lV5FZk!`k7hU$>L@INgivOqqQW3pAZVU8<%nCe)FB!62%XiOd; zHKgc|aP6UWGVw!u21bVnKG96`G&)->l!KGZdG~*PQ$_KR`LXd>DV| z3;C(ku(SnPc$p-(^Tv=DS;fMT7oKF2zgu6{aFiAP$ccMH5 z3MitFhl|qWusZ?~F7XzgJ^2ngyG;dUxN(JSpB6^Fo*Q*1Y}fvf+B78IAaU@+?CPBN zE?8OE)S{UpUDcOmnSVxSD_9uXBysc=uFn*a7utNsa`lNY(te13g4UO4U+!@hDjkCl zC{=akEgyx>nj{1v9MRv)R>FND3YEh9+oO+wOm0QY>v89MqQk7Y%T6c{$5|D>?vO-3 z*hWG7Jb(W_nXlI=HV$s94ByLbiW-wg>m0B#IHO-KN(=`nN_W7V2&k%R1ag$56;U^H zM6^#hPfydy=jRvcNxHuVUjH7?~Cetl*RuYUv<(6Glzu(UCT$rHz& zEv9UVs{E){QHDD!;ze9V_?uY+9w5I`o zlOrw8{VUl2^~)d zv+$Ie$%bUhfVFL`WKfz4h6mwRs~w6mVQ7z0DoBVfGfsKL84H0q@Pf}7pNHhZQ2W^oYHJ)*=`-@>3UL*V#^ z5YxhbuC3Kd&~|c;obAN{)Xz<2sXjiGYfn$3nXH9(BH|r3M4EQBuRagzyiAFp^aHE2 zRN0$Ov1p3)I0-rm47M>9X!Lmg!s`kSoi7f%?hU*TNA-OYzX}R2OrRZs6>_S9;`gP` z8Z8D`PHw~-|@1TXe7?Y`s2*&Vw(m2z}|x=4w?$3mJzU#+CBvi&P^5j_-~toX_9942)+d+ zs;S0Cu;BOZ0uPi{WmBBHTmocR#$lwf zC=b58AxRwnn10tCMn+Q;-+i&&YP`Z)`*T=^1?z^e=O_;?&4JN1Hq`JZ^)58~o6Z!T z8%xcAp}_|HUQeBU58H#y0HV2rd}|~3CwQ;X-BHV0&NoThTBhMoE=mk!KP}YuDRq6M zZvK+GPN(Njl=RHIgs&IRj(~umWJi431^vyei>z0K=o!pp&X+3hr5A5?f)~Hg(o3Mh z*8xuRu*(g_%kDBBcVh3TrkoWHkv?J)8AeeeDT=&MUoGEmBqu(DBtqjP7P>cd&ytdk z;d(3_MlokNc)8n5FNk1?M z+%*m+3q@kl9Y;zdv4RgH{g9O1v!r6=8m3-MjlvFL2N?xRQ^y56=5i@-1<&;NN}xJ~ zM;qXppDZlAHv3{%3unF_K4L*bA&>uY8tD^!fD}Gg3|vC-?qR;ZcwyZ^{Zkj%Z%VKI zcR2W^W)bxK7PX$zcN=>drXzo6D$}ugtE=~9-NDTyX+m4l0WHIJe1Pit5bsNT=@IuQx>^RYN#Q1un#) z5OG0eiMRu|InpT?KH=Uk_}aULQx`hrFC1utxvz{EB#Nhzi>G)QMS_N;Jz`pMtgS(`SjeIUd;c zlq~g<+td|^HVf%TFdHOJBDh$+P0(K*gcqo#3>&<1Av!YtYobZ+Lv&{V@fME@X`Qdq zOj&KCGDA{Ep?juDIFbde>njs=3S(t?23HKWC;$#M;YZ!JoIq~Z>(47APTfF zN5qP7g;C{NR=17@d&2_rZHR(16Jjms2&S0yNy-RasA%O*SvYaj*Dl_~;T2I1W(1lh z=(f45;R`1jQN1avOQ@X?VdfvR3Jt*~i>R}jQ>^`~tAP_$KF`5jq%Xj(b7h+FJ$-m? zQO7;~u(yy-iUvP6fd<<-Yp>mx_g#*2v&;&y z=b6<0;3l%$sLbw>%TEuk{TgDW9%Ifk4r#>tJ)Y9semBx=K3;s{Ojwo4_#uVa+PMXl z0I9qT(|Gad*ObNZ#1+!KRQ@rZH@(vb`G-C`y*#8=61KAq-A-iRn>6mB8Nq&J=OYmG z=WmuRtYs<~j+K;B7&waS;y2YD>4wNGFeXQrg}T&Ai$la%9^(wL@rMkpqN}Ut{X00L zqc6ZR-r$dEnY+|+p=Ns;QV(zhU zT)`@IkB8*m#Wa4cKRI7`P`kk{u2oj=6Zxa&`u~*I$A^Q3fM2ECw>{w2 zwT1TEOK`8t%cRO_g!WAVH?T}Q29{~Zp45M68VxNgN2$fis$S&Px(p(EZ4$5J?}x_a zAxMCnyl0Zi6`??R{F+)^%VSe`i7If!`_n{4PR*%H*<=vdaIC4+uzHKEh4V6_Wi=ii ze}78-qOi*Hv!1LIh6W^ld3kv{(hJMOmEt3h!wU5g*ZM~4<^13Z$99b*S(z1gn>Q0! zmyy~wKIuvStUHp*RUG~un&UphK1D#n{fB~GWlpg{CwJA{eQ|9B8XbLA=PNDIU72VR zKH|9LCV_|yeya>uciX%$=2aDJ>&p182?^1lK3GkYRYw7na1>&63!6<#^o?{P~|YyAQKqvgPOW2>eMzypH{aH#6O>9=@u#-#)kM zW?1-Ztuav9zA5CzU;jMs16nGQ`;<-THyy%(qUtCo<4hPH>Gx#rbjkJQf%0%#)2n?>8O-Bq!ej?Xf_qf*aKNbM{-jXLkqtjJD4?? z!p+}*5%FR)haYMK1^)+`5&Kg9vWb0-v@yR#yi`el6op7hw^Y`1@-4q!_j0f1W-laZ z+oNqMn>A&K)DD!$k=2OJJD$oHO_K&%dUg9Nb9w_l$=O=$eXvbK9|cErYaN502?nSh z;p4QHS$WcifxnqKSi;jEKjy;X)Iisf^d=&RWM^Dp%}>W5fLUF|G>29u!`V~$>cD8@ zIc!@pA$p(1n`K1|hhe=us9>LO?~Njf7FjDB^$bOxuOh0h3$_8S*Ma&*v7?Vb?ua{m zOB8=pkTAMaNK*NfQ@d_CnK=!mE5^w~ZR`b9F zAby5H7saQnUO#n>;p#qRScdiAmbNABbZHR7c=ODRj;e#MOQ0$)yr9rMc;(f^YW=Bg z>szZ54q0;9pQY}FtSJVAjOall9odQa{ah+9PlnU>@RDbryLns=Mcm9RGs#FcGzM4{ zm@JT`Y{s58#l`Yjr<0mP7yN&`y>(ob>$){OX^=*`m6Q-E0coTW5RfjV!%25I0i{bC zK|*OM>6A`M0YSQ@q`Ri?jjpxM(!Jlk-}9Zbzd!sfV9h7z^IS2;xW+xq8>*;pV*RM@ zT4Hx~SrTM?RkK%pihrGZa`fH0!L1>l(4(>ssTRw!8t!CJQ@4fiP!#j1M{f~T8g^-% zMwOzxoRI6P$855P%5yknENZ7O6ggf6a_k2_@q2TJ@A_WJwt7b%?@G|2utMvR-A1LW z2JvXHBh(#9obprsx1L+G)mRS#mo?@FQFnJWB6!V)72DoA#oaJJ=V_3Q`mC?kH@UpU zvMx5AmZ;HZ*Fdo&-2S2pZ=G+?x7R-0wA;X3jl$}38z+Zk%f(2C!r+=}+u+KGQ`=njbTwNA%{cE=ni}8zC zDN|E-)Ge`7SsO>4n2p+sm0;<3y1F4%SlP|fe57t_jkW19OXt&if5T+{rNuFtd=B}D~`h6Kzk}l|5u4<}=)5Eg^B>&N*8P4+rPwGb{ zM0B1l-8) zTlpt&4v5RDDGyGgaH&&Yj0wW>-29;Cj{;__cXM=R6SWUkZ@4egm{vv+Vi5ZIXU4|( zjkEAm3E!UdCsnp-*BJLHKiWM)K^aR& z*0f#Fmsor-xRg5hc1mb)vSaVI1~*$C^`4;rY#sFoLZOtyTVV}s3ky{@zdiN(GS9?q zBG9rj3TE&#?Y{0s59~0>Nu5k1p2h1o9$-VFtms+vO9Reoj!VwGsYpI zB2R)dVaafJ{Hbf3LQLNF zc_)1L8|!0wYiox$zrH&1t(o9uv*RbDKS;+8`G56}_*b9%df`f0Ja2ZVS!k1LGq&KR znJ{-$(5c8!{xj?tINNLtm%%dh2N# zDc`5_ax3QV!;odz-Z@r9%in>REIBQiAV~~AdjGyWVsuhrj4puFU*+vg+DLn}_kfPy z=%QTNIm!4zxV=dGQz&q&SWxtGk#sS2k4!tX?CxHi`W$(3zaE5CiLXF*=ferx<$<+O z%}1V*@I+o9go08$9YW-CN7Xf7`(%WbvXdI6a**$mtx{|yV3*|CViaQa#xJ|NK{ej{)LtF zbLqQGUq5O4Dc5!@+EIcbUG-1S%~%CR8<&yx-Fk~@9KwC-Lz*%`Ul1+8TPJH%NLQMG z!CpKe;*vB?VueCq!tU#vYF!#V(DZPPYu&-3R#m4Bu9sZ?o{EMR%K2>umoCgnU`@~Y z{lh{LcfLKLZ%Wz<_-YgKilR(FhSPLz8-!ksoneiA6ckUUV4=oo@(@DCY2ri~;efD? zBC%(!YPqXb8Cc+*%EU!WPCx&gI>$AxdL<&~{Q=Pz#W!v&nE9;QPWt%fAK2J4&Iu)Z zDikr~@;T33`2o%M(|57WlEIN;~(|L)RBm;+l4ybKR`Paa^+B*Lv zu#wK=_}-4&H8&+&v&j!td#B{J5w9%sbpxrpJmqZAgqY|z7JZzGEtS3Q%W|a0p8%;2+B8&Xu7}%alD#@E}Wp; zup86MTk4XK&8~@C`B@vTo`n_pm(<5faoS8(kq@Hp+KH1+4Zo*cJW-w>t;$Wu>f;a_ zE_XML9})-~%GHctSdd#{;r5@V;e|QSQB^kL%KsMLkIm*O=3< zjaCv@s!q#6@xqI;2>Sf&dhw0Xs2a2eA3wG~%z9sPr4zKq?cSkl!SsSA-u3Y?( zyF(7)FVWi>zZEs@p9oPo2{B}eJF_o$ydiYCQx4@~8qd&v1>vzaKq#W7XOtn=X_%!3Ym&1>cB_BrP&fHM2A%l~2e!RCI zJ^J;`u*5qFruB3NA_6l~w%% zjz{e?eJowdXF~j^@%+t;G)+L8U}O6;K7zZ5r9Mn{i-DmG@v5L~`e$mfavot8MRQHR zJ}&%-HA>vt=XqBl#H*iSrLH4SKA9r49LX>bMf!j2yDcf;@R3^PPq;6*d*sS+mdFzc zFJUm60xmNg1TP}pgNJCMfJ0Rdgsswm>jic^3!t)oLD$-NfD5{UA=s|^po$nJ`1}oO zDsbtpaB1-6gk-?+U^pNo3tsU#-y!Xq;!+UD*&U!|hWpN*QvWy-(3XQEZC^xQ9Y`OW z5CIr3Vb2eop~05iMNi%-pNQB0{R2dV2>n2rfH~jz=O;wxQGnqIQsbUb+J(B)qlakV zXy{A@NoHlFnCvKCmGl~{=kubOFQ7=9X9^VJJ?hrEi0;H^Ofc1 za`pZ(9z;_i3GorVd?qF=F@8Aqg9k;kDm&BX(_h4m@6|u^s!B*m=wjG6-D{IA2vsSIaenM&@}}c#S^|<-g8CMXzGUCb#J=McF-rztDxY{PR3qv zNRhu?@rtnEt)ZY53Yv>dO1~Hl6Y|$L@PS>}1-u88__Cs>`Z7l_Pz$Ua8D5Z!gNJ_| zva$XvhV%T_&l~v8m0`M(wD#FjMm0J07?aD+k86I^Lu`U53C@`hK15yq?~n!m-OoDG z;E67Q0kvxXKzRIpePKrf;RtOZCZ-r$p>GNC4vBNYSq^#5*Ez4H$N2w2cq_c87MWok zP2cfP?sGxS9PM*3+lx6asfZoE(Q)T)SK=HDGJvgHnQ&Io7oT^T;_U44J~8^%?ZP3l zR&%bRmRv5pJpGSc$^t|T9ck&)y4sU{>DEx9l)6bV(NYdy*$GkhgquQXv5T)$FWvLU zNQgBVHN3gonD^3U+??`P6MY;+Ov9*!y$AA&Q&I$k^F%Mudd>7d_bsk=vlrF8lM>S0 z(S5+=Hzg}HZlp@;u0<*{#d*2qIOzN`Lk7#fzL=H8$HWe}xaBn=F?~VU)Z)DTiYRSd zQ)aB!z(J4TOmV+VwxFP(*O;x1$RP6oDTnCIWf{#SlJme%v#1UymI_nF%O;0CSXXE9 zA8jtS1qfTTtf0*WK~6lRRP~8{(MD;|N*M2gSImzpP$uvlKb9!|w$3oD3w0RYVE%(2 z&uY!iZ3g@}zC?5g>*If-b3MQfI6~^FAJMu+AB4BGt;0B z!Z3TZ?2>9h*v*IHXfMSV2@z`kRKfly{;OBj#%xr*6Dlrb$;M^)g|1_rOj~h^)(`ig zjMchz((cMdDCT#_6Lyfp6mF#B5cJao9*+*#6NhKfE1*sAO<79deS&$rrcc#JNXyWT zzGnAAhb|?aJZnefD(d_s-_>4L&O&;8*Y4S>Ft(KGJVjSMQ%=EfpGZE`@@XD+PkICg z``f5DD1_LVZSSp3CG^4E&`iwnz6cQuSTo}&<`*2^~;gq9*w#Jd}Bb+9hQ{^HY zrIPK0A7;90OrS>6b7AFs2XLMdb%}IlDTDmw8X&r=Hzc})$^mE08DwWF80MU8M3fCnB7CT>g4i(rwwWDRp~MDQ^k1o8f1S0YzI)Ypf>s+ ze1~j`;_Ha@)H1-h9%L_1)XzoUZ-MiE``mhQZy28~XJndEk&g7?Yv1>eqlF#Z2F^uw zwwRG3Pa*;McG!67T@3d*T>iXaAY5i$jM=rW1YOdu^zWbln3j!XF7kOP7GdOssr6`L z`mlB8_PMnaSs15k?|7%u6!qe3&oO&&H$*|*0m_P>$-Jjr-vD}DJ>&?#(dK@Kme0D! z^T>g9giV9Kto8V$c0U8{?%KO^&yS<(@^LyZ4$`rTPkyN}WG-mopi%)fip*7wQWO9f z^~QPBos~ap2&N0#nZJJ^1bhJY_aeg)&b_ns{OyVNN@a<~mPwRxa9h!&vf4}C?9We5 zLJnB=8iPH8sz=jHBrsMx^`*1vEY}g>*AElHExGgjR zjsI2SWB|SQ^Ueu_m<&Vh3Cqet=O>T3nz)KQ z^g=9IS=PfrMcYW~`&)hUGZupHUL_KK-_`JEf35$H6BIf&pwIy*)Ri7dpUeq%B1fQT zGenUu`z@&%;Ng=0&nWQ^F1lLS6JjE!n3U)Md3 zDt#*W%!q3d$;JAU1riAyZyO6XSd$5x!!o>3bb=!TDYpB3@i~ePhkXUHCvnH`ZYQde86#&$x1s=*FJtC1XI*RZW5^dUp1sCh=kZ#|fG^{N*U)aI)zx zb#*fOR3OcE62W*+0%!86R*i4!Z;HP6_%`QiyYjpkbx!s;V{-PScJ|PXFh+HkEznGE zIl#y(qzDnH+VH1!6>Pb-LLM=1M024xQ)&ip)bgC+WRE(QR(G5%87@l5qEXdS3)dYM z+r1<2kFhPZES=C}xoA4Ik$wP;AazM)(wh5*?XI$Z$%tYIrVszTXh){4bRTK(xfl+RNh6fX zz64y}dQ>`FZzqD-y4*L`CTE4?kwb<2aX!>kY43u`N@o?a@CP7~oxF=q2*N34vw(h;d?Y6nN)W$_Nr`ptXec&0*$!&lde%zjmp5f#y&Y<9%4eULNmI5+|J*e~7*=&3AA>6Iu8WL2odvxPkMEHa z7DoRTu2P`Q;>k0jPnro{4@WMhC59h_!?o~wXtlZc_#i~z#K_J>zalgZTl^TA`a^Di zC8zwsmSoUe1Qa!H%+LUpWZfe`7rguoDl^dTzmXH8AV4_gkIq8Gh= z;#tlWQN0K_65*WRTAH~6Tl4p$$VbQ5b!#f|Up)?zyO}>dkpWdLjGyR4vRtWfjZdiU zTmIaTI98>x+dtex^lh}8s_kXRO$edsM1g_ydYbb+L<yYObWQg?LmML+}7;(U6Y- z?r(3==T&OVJ5|13LZiFglxPnsIWr@u;=Hn&*dWM@4XEBI=IXPEux_E9u}i-~;PyF) z2IfrvsU!S<8{zq9`_Y??Sd6=1>mX%H$@owj7mc2zIgy~kjrR_N|DiHcg;QLQmqY+- zBzpPvj_6i~OFto-H*vAkE$Fm|$S&zP(A(viL)YcVMarM5;@iA$2=-|0L4r75Sth96 zu?Wx6|042g!Mv*OVN5U^FQb{tgG*aAWT*zx z1*eAY_{18Vb`1Ko@J(fvLiso$Gd{`Pofsc}%4it*a57ws78iyu|lyh++Z ztUg)o+haVn1m{7p`eTU&EM-DBccJ^)?g*oTi4i9zbPXbF+s|jIefGmN!}TZhw5GeQ zov%v?nOkSL04=iTadA3p@JUpT`0YsIH|Lqveqzaq^C?QtRMy2;r~=j@d+Ud`fjV`w z7DM9?v@=T|zw1nkDl0b^elPRB-CfGX5DWO6m;m;m7z~~d4*3Y{gs@=tWR{dv*Tr&1 zpigLEj`)-DA20X_H7;o69ThqV3u|JUyp9%No8#ObrtlW%vsdR`9-f)i)9)gb6AEWV z0g>pnr=y&?)$!QqQ4|q@^3AraTEtEyk*Ptn!V95ck=FURYNxg;8&iQuYn0Ut;SPi+ z@Z*)yN5GUoM_0-gaWjM-Jv7=b{V`UW6=?KM&-F$kiVJ59qub41#!f+Qpk2e^?|O*h zu^myN{H^iY)I6W?*csQ733k&`s?1J6X9H_n?$1c{S4jHnhrh)p`G1H_sTAiN7Yr{$ z>#Xa7+A|{vMklnt+*7t$mv6&-%=J8`Q_N%T4Cjq&wpCO|f{sDM184(Zq-;a@;3Ao( zRx1t$CHZ~|_EphE{72E1`Hw|c<=tmU#G#Itf!TONiIVr_dMBH@4Oz`D7GFcx2IL{- zN)b;g{L35h$~Ahm>AX1}ni?s6tG*Q|K!#HGe5m}lhE4c?n z&K7H}@-+OLsg~*P;F-q2#f=$K5O*DAfsq4g<4F=E;r!Vw-1ltdr&qbt45pv8A>xV0 z%)+f3sq9?i^bt}lT`dgAc<#v5oO(IGZ@%`MBuI=3j9mWb){Jm85CR>=6WBKf&>O9p z@D7dryCTbnUyuWRMrvMI*euoZP}f?)RMtix+1?#W7>>@I4rOFe?X+*AOqxtk|D5z` zMih6JJ~@uaYtqFF&*96y#N1;XT~R(IR*rK~z@Y4(bHK4_zeARtX?{cWklqd%YaM)v zd-}Dk+swk;#2ia2x>qHUpe??Oskl(T=>EUkp7d7i@P?~i@n-rp!igU__m9c8WH9R{ zK<}2RP3Iyb0V)nK4~kk0v$duSQl~`c?^f)|S`h=S|EfJ<&;o`uj+OOiasbmB2#073tmfaQ~kMfg(*v(!)+N z%rvQ43GkwPCa%1=smCDaXwN=9QpH_)n(ate3F)~WZ700W^0RUOIcokVOL~QI<;eg+ zNOJMnaUdXkql?s;K|tmP`OaVmV3w@YhBlC3RYZ$S0#lL^f zi}M?PZOV#pe|t4N(Eg=U0~*-c~lN9i&PTY!ZwRiJm-&<{~Uj=ruK_c02i9tLYs@hclP?W-a!MMW1m= z1_`W`YBv5(1BaUmg|~QK3`s{8QV_n-E#P=-@P4nUiLyPWY5P$dIj!$oc>k{W)W`F_ z_-qqZ1SIRtsSK=Eh;Mf~b|lWUo`Hp3pEF0Y$SMApT-9q`JrzESb{!OyCY1IeBLxb= z%F0)ogE58C#UGjj1L{*IMz&}rIi_eu#ouZvAO8F+GU)=42ZjK`S>xe#ustOK74B7! zhse^GI&V`iQ`CDUF_?m}?Fii#{WMRR;nTWHeVD;_5qk8a9`eP8m=9fjM^`ZH566UG zaa+A%FkdLQ6hSPBFF7o`cm0Lbx)Oru%Y2tq>gaQ@&=xNRYLXN#K2C4Z9l51j%@79) zR3FYYR#PE9N0BJkyvb=@W$4p$tv7bM2yzo-GK$l?gJ96`mb(!<_UGwXR!0iif<63l zX5{CcOka_Z7=1`2clA4bae4$Xk#6*_Ero}LVXP|6cOv#S{gRE=^w)e%T26 zVQq|gg_XwC)`4;odjWBbgs(6CXZL*W8P_yzj+Qx7aY4Dir8-K_T2(5W*-pEWgl z^l752L};k&DO)Qo7NRnmF#mQ4WT^2Zve;mv938spYG+a*)t}I zg^B z0VSs!kjyb7DJXqNZPnV}++wV9d`idFj2A7XSyv%Fk)_LC5rH~9V6|Py;hfx)@6B0k zQ@EIt6VEzc7%dolBTN#)+*6@dAO2Zn-3fV&Y(5h7cP-j@b(MA1VLE~@Dk|e$aAGEF zqe~FKV5KkZ4pLW(1m^0mC1u)YjV2VwP}qhq4sm2S@pq_?-f8udLG_^>g;wZ#Dp(X= zNO@Ha->G^*fA?HJn91`w*?C^Ho!AY2NYdIyYGuvPCOK-T!q~A`L{!-tNxzs8S&c=% z9IbV)L&sr~m2y z)8t%SO;2liOOY6FK|kVj7|o|RKQbeM&N_wPAvmV2cN`8|LO{Fp=h?nw4*>HG9TCr< z-18&El~t-19(Vy;vzvGB4C9?fT|B2n9$=J&I5YTAjzFL6oYF>U?i41y(vIg>4t)LK zT#QZ9Kw~e%uE&`2FtdE;a~qPTzKn9x)+nX!+WW}|p*KSNxKSmvU5MDp!`_QlBfE4t zZ7LS1>K1bAB`q_))aKzEEbOai%ZrOwzQc;@%!Kp|Vlb!KuMgus?^6u&BAdsUk9f3G z6hSm{2RBg-%`+`%Ox9;ckRdp>Za_;mEPqoMUKRn$UKczAa5!T_F*mQJ%ZlxoWJhTol_n#vci znXj}{R#UTk9H1~78v)_~WL|0zPv{zhK=9n+xMc840|9dMj{xa?mue;qIK&$rUm;_< z=s)I7rT!$e{olc9tn_NYtf&LJ7uVPT?|R8I54hOjy`Q|n2n zNfw>DyP+}Sxp)(OREMV~hhjQTn#3+u>Z?qK@Lq1&Lbss@@6z)nKM~T!j4_FhrsbYQ zcdDNwRG&Mk>UP^Ry}}t(NokdqR^~^F>Kv`ni5{J>p3E&Q9PH*PAR?qRNh^dnmAZv0 zS*NJ(O*56%)fwfkU2Et%^0D6!FX*IyO=FdnzfNwJ2Q`|3PN_|N>4cVjTmRUbzF+4? zOW@6V0}T2$oD`?`Dq$Z!15$-{Q^NQXQKpR`X} zm55ccwvv!P&0xl95rrU@Y)bHnBIBXngHmD*vtO7$Z5*$#dVWthWh08v^tht= zw+9Fj29*~v#i3p=b?ajkPzq#^@iH)U7#Whp-ZFyF}r|FIGP3+w}BDbIVts zQpQc>4@?U_vn`fiUi%$P`>S)k`r#d*6uOL7;2!{bHJF(nCog)61qi^gdc!lqScJ0l z+mWC$r;X7q4_F@(ymcpf;xc2!GF@uISB_2L@niF(EyXmS_P0}jXIp#0lZ}rzXJEC$Y z)?MuNtQ;cw_0gh`hh8BYyY-KB;k{d2CKXLY#>_sU>PuHdQZ%onmm*&ict&B#R>$Q- zjqw<=tpnQ$bTfwg_t62l9iVI%tVuM7okKT{N1)%fp<6|4L+D=lgMLGg+|k{|?C4dg zZbiu zP~}w7?>0re^G%FX)mfMyl}hH!L}*`)&*Hrd?`6W`>={Pd1sPy)_bMa5HBy7G^8vsn z`$0JoSE0Jt=J9zsE~TDi)7sJY$Qmkb@iwd~jp3WiQm*r3ez|_m3wdvr<>{>ok|1^= zfy*j8zUel_3%eFZPT>#3r%$gDPLWSh`cvLHOG8Tae)Men1obV<^yC=sXAbaA02*Bs zW}I_$HXd9TJ>jkb4KCElfTq4K#Tip!Jbu9%vkZFVFV$OJb6*3T``_DCCoq#AwcQvfZA;Wg_vx zV>)Gcrhsw})R>^-+}Hv&CixjT&cWM@sFK{}RV9GKAO%goZ**tUI714TiSvOSfhHj!tm;a=XtSOd<3)O~0r^Y8I z1y6qHHuA3Y(9AaN>%KCh&M*__ep$$lwclHxdr+n}&SvTiXAkzIrAeMUlJPB~cWNj~ zjWGvtR%+ViGTc%KRDx!1*pCNn?Ro2xO~ZPSCFF<< zwmwr>#XYSY<)=^<&M!%Ow2NO?Ss9{lCYy3QEBH-SWyn_(Wm;C*80Kq8abtC{lgCWBN1_broU%2gyM({do8v|Z5GJ*sg2?>Vhkih6HX{alg`^n)I-j-p4xXsi z(&E@^6d%ZI*QSB=g7x1750I;c!hm_hf94;Uety^G#a~Q$y>Hp@OK&$aJL@-v+>{_G zln5fZIqJBFL-2Nzv%knI#*Yt~;eJtai zONoKjj=lChFw4$shn*dm{kVPi>kW ziCV4OeXpVT-)5B2!kkvJ>|o~iPqU5z8pM&3LP!Ga217pbJEcI0KboatSyY`8aMhMw zUp5UU5K%A}7%;HKK<7VE%HySmq zYXQ*sF0R5O(#};)+H>kS(chs%Wwy-Ym~#;0&;2WEw&6GwJZ`3 zMyNDB8LmEF)5r$F!=(q_uqAqcZhd#5e@uCoy2jcRid|8wpWXFFEU2dH#cPD7rI?e^ zu-U!ae)g#H|4%=#yoT+O zfNrG-|LTRT{o{pv@gwCn&Kv&dIY{e&={cHyfs9cz&y)&zxTe<{==N{ONLn~eOI)uw zidQQ^opa$pqYK$D#wq$YiF-3i6v7-zjuKO!YIZYH(mcuqIt`q*Vkm~U5sv*K78pGK zBT$ZEg_5f5R1OZBd$ei+#O>ZS4tP4iLY38ZC1(&g2Qf)q-}o zq(y4~nzv8K@%v9MHeFLp4eNT}ctkJ^`m|DVu-fm5ANSm8EL%98{&)dc4hNrrBGHek zHv)oP{yM`1kyDJ?o5a6D5QfxjQ>NEfAd*a-iabC)$z$jDuuj5{5Nn04^YPN~+$ZNg zK2^&k^y0^UM}n)PpEMxn>26d+2KW8AB6}bX?nLIlAz%LhDm#jmrw+(rIQR)yDdGkeYUFYlvwu$^tu+5@H&7IyTD~&QK=(~0KooVlEPtWD5xGWegs{k(PWaZ5} z2uK#E)?qvK|Ckr+{$iD9f6I%IGE>t$oecvT?Scu}O{YBeqT6pd3lvyMl`*UDiaJb_ z&~Tm4^Wb7nS)|_hkgz$HaM#up%VLaLNxvuUR0?r5)}5Y6Jt6~!*A_> zwdikK{5uBuKa2qIE)JX$lfYYaU{|7CcCbh~Xx+<5AE&xR9DUS~y=iG^r7zhlkxM@> zE`&3J@O6SCxPlbaoE7fQ?(R>MlqZU)_dY#VuWpHx4U(M6VISz_H%v~7pKMDQb|Yyc zn6xIY@<@%Nd|~i5Gw38t79GQXRsIaI9xU5clOO|SoK?6dUHi1KO@g_xWV;&w<-_aC zOTf3|_2TPcj>Zyae2?2sDPEVggnlb#aWI<15V>nE>F|A|i1fK7dtmNC6p2$|jf~$C zPkyR3!pxB|Q-_BtU`$4T9uuPsp9Q6D`ZEx?e=Ke*M#%`^KRO%GrW=AT3V@wvpb%wi z+}K(K{Bl69!4&&gaK(7Ez@kQNB&HB9X5@jJ4D;Nb3z-iFX>h3?jk`CTT$6Ei( z5|%mpYK8Yds<^v<+7ABGvHdYV`meh>0KRtVEW)d$t|Sr~>q)Tx`b~^{LJEjiTb2Ls zHC);MOAS|K*kWi3#H%GJ%N5gYMxUk_3d_shJEfwjYS8K;#8Rf-LmERHtY8{)wtN%6 zt+-3`>e@ZJ``PPwDaGZbDM5TlC2j(g50T3IRN)(HgD(>7daOM&KJ)}Fur{b$h}g;X z57G1MVL86u4YV9ucbQ>?iX5GJ1|@yYQWH{Pj`9_Ipo=O|bb)uVRK&$)>8E(ZnL^=U z=t3-JLIOI6k!4t5Nw(gg75N0Luydk$o`I258JVp#tg~i7OF+2SDtDEx?)^wt!~RWk z5788VZ}#-Ik1iW8kq-ZmPOsIIAdfbn>>Pe*Q@t;wV_GUl8KNHbLLQxV4_(N}hwp#0 zL}aNo)a}mgdt7R^PMVP;1eumY2{jt~8+ug2p_RHGbF$TUnA^I5ou>M%7n-*WO@; zq1UK?PC6+1I+=I-$6I19I1)?qQbu|wG975rNoElfo`v$Qs(xRG=(U!Dx70Hq?(u+O zeOgHhu_ogYM=@%D+z_6+P~H5XhKXlAW&O|3Mdp;=L=c`b2({n}`FElXj^MkENv0|J z!EbRS&CC(M2*11H6oME%@AaYm&c^5AWnA-Ca0C{vAAqK&GCDD>%2thF_BdA#(p?NF4@ z3(NKwcfj1d9nt&uW?K_7ghGy+-&?MbkP8P$rmF0X-n!d(tTZ*Z<0cYYJon{hL-a>Q zI%Tv~-jP zl{3dPL&G9(;HtcI0IT4>9x?pIFvNPc#^rhd|+j{jKLZg#& z>5Y4NoywptStWjgLf3NB$dAb#?UhY`dm^(?AQGw6B6a_NDlmI?uei&b z;o)9|?dc^b#GCj4qg|e=Q3$kNm4+v%0P1k5yoY%ZcmLz(#+9QUusj9LcSwY)yH3>w zd>l3hV5r@XkPlK|2Zld)APsg9o2mg)#nlebXD=LlIEK`5S=9k+G|6#+Yzr5Vi34T} z1Dk1ZL~u09bj*>7tYxdl{Zjz0_=JClbh2R9I8z9^Bq{VLW*~+B*dam*B`&>#ELt~d z&s}~RokFTMHDY|(qDR18r{Gd&M|U+3aot`aci?8q=$mLBrF1;G?t$V5_Fp~=VpD&e zQSl_|W#uWEKW^#0qvXj?cEODFEIRj8C+7kV@aH*J*zQMVjz{1Gdqgi#zzK?xT|DtII=hiOzHPNV|aR!2Z}+4QyPe{Kv+YEC~sK;~JRG z`Px7HTi9fei{dMcKggn^Q#zop_fr#y$L4fhMJMP?b(LqBl<&p=uO2SC0okJxk$FH3V`%# zk^5@x@^V^7#*~pj*Rb4clLx)-;Vp*Xr&w6~`aLppDEP)=rLHl(Z7Qo_d$;@Qs?x(s zjXk{QM0ScW#opJ9R2+gqHSI7A#sk(GA`W)_M4PTIbtYuW#W!pEGsW|-ZjKb1g-oiC z#Ld^9KR7z>v1OHqi)lDeb5=c-e2j?tX>Snaga?K+t>0{o8u_MMxV>ufrc`NId>}2_ zc|D?*v9NpR{Ri)dE^zboNZFmJ*t)LwsxZdW&AdW#AQq!?kYSDLI?Q`oP{FEi-MYb> zEJsxo$57EeBF!6YYK$@OirTrQ`*!iGp_lH^a&7&{#Mg7F59P0nOe3^s5Q8%FnCs|` zqs8c7B23(Sd<|mw+e|y}@UP5R-v6&!N$qDh2cZ`VZw9jT6@@tEKh;Ddz8T5LFXBVI zm%EN_rE*{Mx?Datm}8uOxYl@Z$2u(qJQidba3Y*!uy_$_&FLg;H|ap0^*2itYFDrf zVW1)?QK166YZ-jZA9Okkypch%b-nhRAVvH|%?m9L;J-ZF-a&2uq-1G#;(jCJzu;C_C z^;eSB85Pp&dZV zgwUE?I6lV~C*u8#Zl^tYw>R_SqBlPLFT&=|Mip}|0-S8muZ_dj9youaMgzzUQY-8T z6TFe16tpj&Rh6i1cs@fv*b95G`$%tnE2R%jd|@=vZm47N2B{ z*vklj`+3~nxIZ8XqQEKaq+M;qi)Pq)Te>K;>uiPk|+0&iHIlQB* zGt|4N85v)uCR?-7fl0UItShacydM{`3>x)UK;?04>fgNMgZi1xm#&x(f9$Or3rc9S z2L)Cjq82B5w*#V6k#R zcUECT5>wbmOp5Ni7r{v2B2yDM7bE&sxxW#0Spw?fzt*E=EjYk|!ST|rZlCa9yV2Qi zNu?`|V2WmE4z{^brC$~8y=I~{k~VeF6LxN1=+SO!4HEF0G2o;0MS)53d^+yEVK4Rt zb~X935!yfnEt_}3&<@}xtZB)=_mK-abU~w9(tWuPg{Q^m>pt*UpZ_1+{NkvP{A;3 z!VZV_ze6M~+FVrH_N21#+1u`J01vYdY@y_7hx%NLBI6qmhP{~nILXj| zILU+Xf3e)U55Mh+xRCPY6#<3>o{2@?WZXdKwZm6D6@iM^J4{i+r;?vZ`VL%_4k#q< zcA6cK9qBBA-1E2di$&;zwV*A)w$^A)$T&budUu?Pvr83gFBG*VsbG&?yICKzt#Gp= z=Th@Q^+2V^SdoSXXnLvRMZx<3Fs~wV$i6;b3-!&&Pic(_N&j%uilR zx;N*G?)aRfo!831Q58U>v98~7y$B{pyL=Af&VkP8XNX(92>DpfsL9YMJC8D1EHR%0 z^ppTibgxJFws9v_@}Rj491j;f2(DM6({9*FpYyMap{{aN^f4*K8IABNu*y-|JgTmi z?WRsAU`FcM79v>?WL|K;E`L)u2s#FxO7qYr=4Cqm>#kG$an}{upVay?i5)wjUi(OD zj!$i8J#?5y02Nh=XVMHmR1}CCS-Qh#H}`x>P3V`$qa2|Llof+eN#i>Q-A_FHr z?TTdZ&Sb`8AL3q`ztz#mUgclUjFlK^#!Hzph}Kk|&idEopQN<5rqI zl3l|~e>GrHxS5|(>=5>PtwY%*DtQW+i(CWn$D1m^HaEJ!E+Sbs8c`wie(D7K!xyf#yldr+rhiqiM_G^m>_*{F^58;;s?4|ZR*_YD7v zkWsB+Xxbjt&Ni^k0TN7&!-O}M6VNlQtiDM-Zh7SRj`_!Uh+pV!&QBqfw{fj@N=m-A zRoDcb>V2d<8KW?iYCLo#S5SU`k|6s+mfmnvSol*@$Fk*uDZL9n9bHNBgPo2yIIngl zTS=}5G9PK+Vf$RKRiU&#v9V8kI+i^BY9Q2U*wJdV3}&rm6C6s=*ce(z;J(qlt^Xl2 zN@~Yd+&YNB+V=fgi}$%t#7!ey#z%fxgk=F}%PhE7&F%N(VD50)LkIdevaE}NJsEM_ z;6lbx5@q7!8wTc;5v%V`mAP)2g?UZ-B4{n;qFFWznWqi`!D+sgsP4ceewOMQ-?gzM zI&tf#6FfmgL;IRWqc1?e6w}nnQ-Q5`Xp1qfuYex#q)@w= z$7(XpB=TVdUvpE}R3I8sm>nyU!Sj~ds!(2&(F%4<`J^G)d1^0WGf%%KGW%3H(hPR< zVi51v?m27<>tyTVz*^l2DPu~ELLG_5$6_x<`sDDsLin#OD>#dK=4~j&62#KHh85qj zb*Oyq!X4 zjN}jm>6u=fKIWF~y2;+pj^#%Xl=2yG``xi&Pt|tsb$Z zZl%@=`KtxJQH3AJWwI|rH`VwO>DlN}mRRs{mT75P8p7H-cSSG42>>I$JPVJp{48`& z5{jjHU9a4Z;=c0@tz)i8o;C;>Q0Y~#dkZ{o11~ub2*rj8KrNo5ar7L!VlyQrr6bQ? zh)bT>nx+!dZ9)IiZb~lggMahD2RE&*TMIhgk@3Bj?-IvI#$o#KMZ}+vV_+`<$5CqP z>YOplaN9@OZ+6l$#`*!ixy@N#f`c|&uI{YHW)ZD4w5C#14$_1+-NHVMHG+*oCsm4k zcMGlgjw&Kn6H8dnPwGnOSBjZFIN#%KUoLJHrq;z4vLc~VtiXI~iocEW^L8vYaL&|m zjl>BsOv3{+qBC>*IKIN7*>q0g6~Z-0sk;e=zJB%8b(cKPG!K2Y@M)7m?HK9@W)*P6 zrrWW9Sqj_aM7?lfH?(EIJo_UwDxacD-%}`#@|w8+-hnw zctkO-Le<8(McL=B8DbGP^u#x54dR@L+J_qzp6*6iSQq0;1VF+I|UPrfz z20GBfHB=Aw{mygu0!n+})V zv77**)8NB9Mcj4*>jcM6>Tp-0dWRPz(r(m3q|stZ-55*!9n-Bq-HDi*Z0~Hj(uQr$XHU=C;~E3a%Tk!CqrGLmJ<)baoLq4+h|rT3 z5TFybZ$g3oayKoePC_2lqz+BAo7U=!KYgN^Y$R}ZL%z6?dZfqWk84M@rK2ia~~geGJY#OeMwmw9j2j-}}^zeApC zOVOKFL7f`HNs*>()Sd&^Zxp`PZVec#8;@Xlv8}~qP zhoA}W?k*una0$Vk#x>A^1PxAr;1Jw{dk7HR-Q5BNcWd_M%}nOy&3v=_?eClY?SA_@ zxpd#|dymvPbxu{?s(kZ6PI?9*3=;(bn9wd7$+|4eRL z3R@SphRQ}`nAo`YtEBrF>N55`MbN`BcMXs-44!1>7mQh)1z7pahiju>xu z>pA*gI|kbBZ{c~NU7m@eZP%*Oe!?i3E#fW}Dj;&j)r|H@_4Ca;a22+M^+8g3r+Dd_ zxzHOUhY;|Q$?>($!o)*$Q@@ygB$@}F+_~KO?$aGKoE^gRotU(3`ypS!^aK7f>?BSo z@N1;b`m^(0R)+~P@rI97W~S*A9pvQR5x$p`V~`n@bdX)x5t#5{{TgNSf^sy;dw_WV zxw{ZsyTv0MDHHjGK~aA6u)<3O5A0IHGfINfU-<65H9@?tOug^0N0H>GwCxzhWFK*j z1#Ou^_7IiV8tThi1;XC|5p+G%09g7If$b(&LrJUSWBb<&O@F|yQXVxgYi`;|(IkcC zxvF(F$S_Nkm457?(F%kYn7owk2)}B9c-HEXc3INY|!MDc^+J5*+RL5{%h@RD4OISFLHI@2SSI z^SFfSMiBN+d2z>U9Lta;{V-iFN!(_mIpF;R`zaTO3Qxy)$LKhi9%^bzS6t98=L%8v z0NeDX-~NG`g^h=nR?K%!Pc^vr77ie_E_c$`oP!t#0Gd*dLi6<^AUdS7RJcG0=t_#M zjugE=z96#S@_)=6VIGjBBb)Z%{K`PJ{52b`;fIUK!-L!RMN1_I(2&vHWTIOXuLpvu z8bcw>b_4S^2w%tM7MY_0*)ntDKFW)!_2a%OYqAqeJLN5lw(H!J9D-P@_ML6pM(ezxVly+zfqPqLm?>^wT3AV3S3E^A(Gxjblz%V**!hw=M>b&m4}Pq&$tWJqJDyX*2vqf4by&y8NZa z%1wSI&Qq5g!bjoB)>SdcYfn>1F$OstJcbaD8b}3B%&!Uqi6BEAd6OEOW;TixNrCYg+<~9nzg(qmU^hsC=@QyJ?oy&CFjel2TfK<1qG$8UTPDK6Q7tYWeAz!RY9e`_r6AL4V7;$8uwbJRf)WOw!gnCrF0 z-gKksih(Gl#m1QMpB>^+&_CMNw2?k)i(ELwyr|>eZAc5q+V#~suZc5(tZ((*7&ItW z@(uFBg)O_B;-v$cF#Q`~hN%w&QCbF=fCXQl`_qfjtO7_o6ji9{nciNJK+{~2P7yT! z=xw<15n@z`kaPZots{+*fBI?gwLR#@rA%qq1pD^MaC8Zn#cy;^)Y(ilmh)A}g`t;S zmthkh(zf2P2WwkR?L&RNOB-{G49A;)sbjIA(LbBj@Gn=)P-x3i_)ouaA3_ zYl3O|*B8YLtWbrTtg|M-u0*Wi3g8HPh(ZIDfNmiG{X61*bZ8i$yTClxuFLL6mP*a@ z&`$Fu92UE1eM#*tPGd^zWU;Hxndg#p?F4ga#KKf$exYvNET8tY z0_QNr0*iw$Sf@Jw;N#)vl%)5ELmu2pg8easy^It!?P0LWwm!;yWQcjUlxaZKna_bf zwYrGjD#;`H-!j@b;&rqHR#{qvw0F_CJ!GVYixNkR65ry=OsMN+O*U_Ey9(m}qRo7A z%QEu(nS7dCc?J3>f$Tuhg)2XuV3->fbQYxY&On-g?qMj^ej=I?vT49dhX-% zC$ryaE$Dr3efCjLwx|Drup|FC+%FQ5B0bWfG9i%NUv^>uE_B~SFsDSEX+fe+3*ugC zU2Z|0otJh5uapoItvVd_kiAvt{<4lGv5w_AAp4Jf)m?FbwmsneT+91q8Csy!cG1{k zzi7MGB+OF)f15j^B)UWqd))z z%+ZA=?kvKGGozeF_!H(Jb~t;ON9s6BmZzn$RVM>Vu9s(X$whXe8g=Xo;^*f6`?R$@ zb0#MmSyoz1&O9jkTlUDX)o1+Kb)!|=W>xVca~hxeIdPd|)2hcIe_)pJ zsDH&=Vx$QEOQLOicwFm=TQ($=eQr)=nF6xR zlt@LMI03r=wwH+?V1fG~QP(bM-0rL~^2uvau7+?Qy z5FjFW`44;e|5|68(JxusO6=qJR!RuJL<~kJBi9tM!32{yprB@?-N@$rlTj2S{ahfF zAfTDbR8y(jXx-pz^dZyr9`rQWxjfP5lD@?Jf5toRhyRLV|F|3tBay9apUKgu_3p|| zP*-ur*QD*Q5GM4CyPsofR3GcwcCWtZ9BWf zE;JEq%Y@_RP+50JbOrtpa)+8k0YwAGYSmg!h+sueFSwNXmOD#Q=ovXb^`{UWLQ;QZ zeSb{;j0do-;Pe%@&?Kj)C)MFmW_}Yi?9hXL)P6CHO5X>v!Vj#cg7PLP)4Ul=sMRBe z2X$w?8-vZ*Wy_yU88Hfy-5g!iF%IRK{3AC2$V!{MSVL$F(NofuVYuVk+aa zcs-pGgK7g&wtkg{dr+45Bufnk2>k?U&-OpgG>< zb?4#D#>;<2G2p4WSMn5;ExWSj-*h74AzsXJ3CWvjjrPo)a_auInx+!bsSu0y4g*z?a zB4NdD%@1L*f2ynbfSF}WFY!xPFK;2s=mXCBjiEBH$$zLFKo0$NZHevEYiVvtxW(E6 zLh-K9F3X^81^1wAw~3JnVP5$$7aOZa zWCiUGuBx>5zt#QokFKTlc7|WIt~HAs5poK5`Zj{t^ol~5`AEAp^cd!&Kuc5B@`H=H zO*i^e)y;x>6U4*T;vXCQ8Ev#rb?ljQL)PBCI-qfkH*kivOyo8QNwy%STHK!BnVwc$|(T$7c~0 zKE7qm93Y1c5KQ~m1Mds(yHfm}eZewf4?(3E#)4J+1Z0{RE_tHoo&<^~c&Ku-Y|oJ4 zwIKTLVc?d^>gETllN&3*BP1JgJEzkfiRY2|3+3h6A@J+^?H*Z}2qV^KedzO!x<`u+uuqT z*l3>6#K-D&7_$+w#V^{##ZvlpZha9x^nRJz+k5yO|C43kIZu&EOs29*9!x|25M!5? zer@QjJl(qjt9TR5QLYdBYpJsb&q-q0uRNp;IYgcvJEvgOby2-$^^osRBMZI@D9+N^ z$0mG1LM@>FrCb{h*&N367W^e!Md+APzi?GKN`55@>Z z+1JTa5d(fsz`sqz|6AYjw!DTSJ`Qs)7~pS-z4?9-B~Bau^&?4gUd-ci{#f_kcbk+n zSw_YtX&~|teWdW9@X(!>nHFmRd_VcS=nT1X>ZT{;cxiBpW9{so*(IN=iU0HE7+HK0=FCf#uUkZwj*5}Y z)b(^dP0?)re`$bw89dUid(TOV!l^dT1$T3l81|Rtq#LByR~}g|ph!8*MIck#%gBDz z6yB>1UT=yn<~CqJdmbJ=lq=5|f#}rcij)G#Ik#TJ@V*a2`Cjp&iaW&4d5%@rOE^R& zrgV`L!scKV;!$rfMoiSJbJ=m;P(M|a#IImi(calHKDV(#Z;V3hj^VZo%9J{DYErSQcX^GmKfDU!ZkAO<;oOOE_?P2?`XYeB4Vah*jXw z3isK!Z$@`W!bD6JIopkycMavCwric8pwf}$A-VY$r5A!K zO)q2e-j=~hBaQKvq;>6%Cy}$B)e^y3w2pKLeA!Mqv31w_lnf=Sx|xRyC9Aw0aGAtk-zES0E^ojp1C;n<2-qpv ze=AakgOc;d2N4lgZDnI?Gm{^`TG?5!QS$!fYv2bJBPXB{l-$4Fpk!uhWh4Ri&|?Em zx%s&%`M5X?L`42J%JL@0)JDkXHzX@_e-M zlWp=Uq(H$;GG0=CJ4NKpCFN))mg;$L6fAM~rdO`o0=I=yp;s2IvFT{>;}Clmf%HV$Z;4sQmPIy=;i4y(iy3JBjjBOyQhb8*4y3KM@ zj2t+W*dw80ujTUNqV3E~^&TQ(g;<)o=n>6mn$n5Ue8lquMT-@&s4#Yds4^!7 z#4XRLGc|32U&lkmfg8E=W_ReRbbq^Zpr__KI{5Fmsua=9753Cnp#!xPZr4~>lypCR z4O9yYLzSs1U850gCrt>{qA_BpVX7CM2m39MU-=)Y`~>O8FLKXHB_81K%0@_ zgWu}%&uBiY!87`C>9g9nSUYKRSSg@(WGs}b!WiqKbmVGdpf>9goVS{y*w!7uuM#DM zKW;=TEb*oK_}iV6K=~9QmOpPTI0$iOR*1WVV1DGRXi0>WVp(qCWx_thol6}27GdGr z_0V>UJdqhoynJCs?2{OcK2p+e|B>N>r6&Dyr~K%qV17_i2kEya($09Hq$Lg#{YK~* z`zjiDyPw2V0Xp`hLq90O@T~^*7mCQ#0Hg35MdC(&jK)ujz?M{G15^fj0tfVD7d~?$ z@~v(;Kra>+4zmpc;bg>DtZDDzv7{m}u3;rzlnXOEWW-h2>6(?CW>EFq`QgXJB zFr95G-c&yo)fe4c#NN_g>nEInEDdUA=kUm~`gkihuD7q;7*5y-&d^PUspPs#-yfHX zz9{CLFr78jt|O&*mu$E}>+=5QK!bBJclP1tYlSn}dSNfV@1MC44=B#vp7D%rR@+7n zZyFZWT0?FWNo*iyTRCTzFWQ*iN`Ovgp$D>N@5Zv3G6vkv36{WSE?e{^p!!=1Z!p-Mi>uf&l4c&^8YXM2H&bw;W8H|0KjwHmR zQno%iOCo+}LVW@&P0IH}dGvGSrelupqjY*X;j4YGX419;&DI>_aT^x(5}I`8&l~r{ z2%f3SYl7u@fS{+W`VW*(r2_C~jT{Ve^905Z7jmJ?E{?)i3sR89LhwqZPyrXRlK~8!GU{&DFpU}8oY1K z<}~A-zApqvo`0j8^?UCozKK-u^}Ela?Xw8crKU#h2M^}hv79Dv^u#2|6t)9ZgCw;# zVo4Rg7l;K2W)MXv_ZmgCnYJDh2Dr@aOb1)h7pst%~au=zi!oUq)a?JkvnN69u?N~UE9GQ^dgs1xGTlqQjsw!~v^-@fI28u83`jo}M z(Qc)+4z@RDg)dmYMeViJIC$}*Hf3^&YF~?O&)?eYTSw`PG+9e~wf&c*>PtA{hD$}D zfu26vpR6{RU_AZnDJzX0)@p8TQG43DSm1ry>^ZUeAk+%9uZJX{BYP9&L3ivdf@5m! z#rs1O zY&7;_c6W9i^30F|_4y0>u>~lS>NEHS{f3gX%+mwob@1&8nNP4LV|$tW-l;}g5pY@1 zAL^W}Uva6Y#oH6c@xHB;A9#)$rNu^|4teYUqNhxmk75sQ;~TNa>wy_0Sk0bMZ10eC zo;>%Wy^V#A&HdZjk#KWP^p78708({i2QpyDu~efaQR#@q_)L@bz!cH&%$2WKJM*Tu za!Sz>_{8>EDIxA7(pa!`&&%eaHlpyxm^pc$9_)dW*9H!@w2F?99`C&j7H;?K=D?6H zd%=4@Gd~fl&lBsCB&^?tsIBfb!>xC0HGpXUupfWZ-@M5Yp;*ToEY^Phq9=!>b3MGx zSl7gF7gF#6ZB;iL)w^{wypQS2NayhSqj@2S2*w#bKKE> zZNW~@9gIxOSf$L|tW3<*WF=UiyBfRvkc)qlcv_tGDrQcSU^@q}{SQ%>?{5kTJ0CkYFXvBD^?v$(8HA-E zBQFDjfdzqJfPbL-Iglg>84(c)5dj$q2?+%S85JED104+wod_ET6PJvbf}D()l$4T& zg`Sd%iJFx3G4B&5Hg+y9E(&^nVLlEa7EUgXABDi6prD|mp%Y?Y5OO>seZ=vfe%*fo zJw%2VLwFAdLj{6;2m|*J=Kd>)0%#`!%x^EyUtch=aPSC-NXRItXut*4SRhy!I5=2% zI0OWEc;IRu;CB%GLj>$c?Ba+xszyjuj<_6t(V58966LLUY9oge|$jZqpJXhDy)Y8_`H8C|ax3ILbc6M=fbNBG{dh<3QFeo@A zG$!_aTztZZ#H5c|**Up+`2~d)l~vU>wRQCkZS7w>I=i}idPm2`Cnl$+XJ%Jc*VZ>S zx4v!f937vWo}FJ@US0p_7YqpQFWmzE{-tAo=+{G_U$F4-aPUY!`UL~)4jga~;SnCO zBVvoIA{ja2P;vMn<4Qzlmbao%bE+NU89R-j;?r=g&>sEh+HXDkU+b9v|5nd_cI@x{ zngyZ5!2p8?_YfosI%mbRb|;pJVPUSh3V;0c(;x>5G)~;)C{d-&hKbw@^Dqy9o|C== zkZD#Rv0BOm*V*?V7ZoJtjmt5pw~nvm?c?KHz{gg&xaAQPZ(>A@G%sOI`D)MX3iB|l z?369f(3Sh7;W6C%zxN9F_wC#Hmhs^E&wi=?Y#(FM$N!IOsceF* zDITC%6TiYA)suujpW^J}n&eo(JNA#_>D+zoPFlXKHopsH;PlYIR-zj@%bDX+n-$tb zfoG=1>f;DRvIp&@{WoG^)>hGr(w#^HwN!J1UF=;!NSqwV$+Ix_azr60M zn%@w^?nWsg$l+@JMne?Kqf&iz`G_UYd|2Ktx5vr?or6xjw?9{t=4E=kI>>^^umnvH z@P#qVCl>iR;D4WwYP$`KIRqgtEtuP|qm1vm&Ff-z_IaYIBZRY1Lwj{XjBX`CI0MdJ z>F=8Ka&{VWQi7zSwgt4u^I#WM&;2&}7>Z5rW*%qdzrvYUYcbqaTskJJu01Pg`Db0i zUBdQAeqJ%+^6rkVQ#SNkigW0kpCvroHlUV^J#`ZIi%0@u}Q2DJxC$}wC2yvas*Ly{KY70#aHZesFJSc)Mq_K0fI4s~=(wdR9Cb!yz#)kXG= z&5iTN1_Nn?q+7KmwpO26t0%Z;Tr6Gg#95j9d`e8iLDg{k36Fx?-^9%|QVX*=D(TE! z4<~O!cGYTsa{ez1)1#FCGb`4gwftw-_&+K3C&m8Va>So=?7#mU<6cQsR%vQ(sUAnS zqb-Mf%sxbU=cT2npBLD&ZaM|oEj#0$_yGm?o5uwb^V-rC!5R>28~{}^5Hj3}y&KW* ziiE5iMnXRmTyeV`K?;>Gq(K7z#B&b4nGq@>uyyBK290gkjZ4UZbjt#cT4jLC{iuhH z8jutjz-9d7!H|~cWy`GTkQ0c80o=j+0XFQqs%9zZOQ*naj0Gvu2EoDPfP;N{60xy{2 zGxMj@)AQWj>yE)hM|ii*N1HO=;l3P$U-sg0WW)E^+6%d4eInRDH4wN_scmVf0em@E zV;;|he31t|K;1&3e2_6=qm1_LoXyIi)p}L`Ng+O7>WQTb{}z1jXZ6F^i7)T@4EkJR7R|U+F;BRmoq8J_!^%_6q z&+&@XP}I@AZV#F1C5(3yhplELQZu+9$cllkgGT5&Y{?uHm(m(QpW{ z7_ldB23$OGt33S%B4I8a^yi1pi4^s-kGgaBjs48|-!p(`lOyRZ@$7Hfl0-h%_1$TooO<(FfLlmbW)f~XJMHCJS(XcZP zBphL-lYW9@AI1>`a~>Pr$Zg-(CP0^3$dYGcd9)bG>2eRUjH*f=)bnIMIY#8QASCQ$ zeBl|txG0~3U7qQLqz{u6wC4;N7TJPcM*_)V@+Mc-bw3u~m4dI4=I=pEK$yaji_b4- zudAgsZuFNOFb+sTY3a{Jk{=9U>vy+M z+`VEww%!Jup4HR$LpOy0&?Kr`$k|~_Pf^~xJ2gndW0>*Z`Cb3b-PP3c7-@q040M~Y zlLuhOWr$8z@8U>O9Pu8p-o1?lqOO>C?SEGF`*oSk?8xx#mWGaybk-+LEsE`<2=Q)F z?{N*Qvje1OqnsYG&t#(C)CXxkjHiSdoFaQ&nidLLzXw&n!XhIRlFs|u>nG}3?CA-L z;j9r)lV9H|u>@kmOjaP*L|l;D2k(HK*d>680SAgh0R&qQ_W+Y-*~RcyL)?3{<$?b6 zyf|V@jv`ky2aS~{2`4)t2;@m~UK(1s135-*0)VW6;I@n;P_+)R-N1h4Me;HO1F1+F8HED1FRw{TpLv~@kaU~YRiqJ`9h=4QNX6Rky$yqlxIE1tOothrdPZ)o z7yMSTC+_3RjF(1H{>=jZPuw4L(c7&uJNYn79$Abn8rD{4>2bduk#{~>wv&x@VZ!3X zYP}?>!<*9*1za*U18HibshcD8d~RqXRqNzQybW&0OIswfncLA-&!sUN5(|g@ht8^`Zz#t zIy~zrLZl8~99}g3BmBrs23(Bu%WG^D3h!wR&LR(*-~=c(vtVBsf_6(a5TE8Z_N2w? zR{Dp@h>p7qRj;zoXf>RLXyzRz@ADHXgb2M0UrVx~Jg)U4%s>ltS61wA1RS`Qm1Mm# zpY==_fDEz2&ITH|FhkO-5ahP*zEx(LicTu@*--XbVR?JsyrjUf=Z7xNA$G3KLRY47 z(&O#2MEo}eE!Jnk2rj28NSLdlp}G(Jgp*_)?edGi_uhj{8)Q9>!d_*Zq+Cb5-#q&K zW>pZ`_*1iCl~2X+6*dO2v`{=eMJiiKnmQtQTQ!8MXz9w%*k!9-Y`Vpk3{9KI0ZHKg}7{=#&mhfx7uCrTfv^fuhXmW1T$sh$qR* z=-6AyH&f9EX*`$;-Ocx)$N^sH=O7@Zd|65;$kNM!pGH&otZ;FcO`NHgk+3%Uyxp0G zU+}%@ccZkt5+M(-Zk(Gv#q{eCeL!S@Dbn%E3+8IZ*Yh|dsoM*0rQ(TwBu_Y~EI!pt zaTqxR6Dg<$#AU{H0VsX?>0!QPEx~CW%&ew?kKYl!*xb|^;_Dp#F1zy>uDm&kzsjb7 z%EiT!G*D(9dDc60xRgZp5F;|+w68w1sVNQo=%hid{BG%_ei)9{ErQ-PWW$UI z`K?)Vpd3YF@zP#37Sn){TlrP)6ZzwNkW;Jw?UJZa`pSYXCsR0DF;mDRLQNN@jGNao z5O(cyOJ295xh{;o!Vc1KM)7mW4SRZO>mU-b?#|3Z;G6XInTBr(6MBfiYLkws6z$f)wTrq#3qyN{El1r)nq)+jI06 z76**4>Jxg(RXjXcb3{Vzgq`1Cx(Zo7tXq3ON803y9qCYbr(`4OJSV=~Wb^99D?i@7h1v_NIjY2> zZ>;(Kbb;HCOl;3fX@dF@NQkI6358s@w#5hzstH|AtZB8tRfC`CzC0kR^!MEEkaR7k zZN8Y!tgdgYe|S|Ig>Xf{2On=nnzC#mq^=tnI;H9L3V(_UzdVWG#ESX^&K4ddMm;r| zWk+@Ain)i(jZEDTL&5NBHa`3dO#xa9gN)ow7Z=2Esvmi(!!6J~e2>*Qf}c7m4Hhv?S-zW2-j7|gT865eYvC_5xt!&fW_VJ?k8STLE`a2|G2|* zO*@$qNwz-Kuc;SJ5wGQrevlwo_YKz#j<7U|@2e_}&4sE&WZP@9KRROnUvX}F`Q|JB zXOgi8S+6RRU0r34-(&NVTEIszFjI6SkvIC~?WpuUB6=7LtmOx>10aE$4qcXHPuiS? zg9IUu`LyRLrm*~QWXJ$=>tTwAGt^)73RW3P7fu0{#l(ipl|kQe4^Qc@NhGT}+RX@0 zsiz-*-eRKFwW=D`vauMcp5JO&;XB;AgNGc$r{5}3{Jx9^;=cML{6woFxrDO#<5k)?C|G14E%tA39RTplBsql^ch|yKw$yc461}%dU8@=Cys=Q0ir}m z78ED)0c051%P8f4#L@>wmu}B~=TOY+KV~vT#FjW>>+Vf0g<%lywtaa{S7mi#1jMZx z{>b6FF8#Am>NFrsZ>>H3^dV3eHspxgxCI@crqAE(*_>mZHT(&ipsa;$$$chwq6Bu}^7Z zuCkZTdp&7)68Y$q@Qf{LBvFOQQpxYvk1aQ>;66*xHQU4YXTqJ%% z{S_9-O|k`yTPdGkiwzatS8Tuuvp00PA*!;wZmwR4wMR7|d!u$8VZ z4rB}oZ?g?(1r^mel*I4}9Y2PX2+h9!oJefIxx*7$JRAi>Pstr3VXlEm3hV1A$cBw`-(Oj0&fLGlgUzQpP3Ba z+Oq}1K@q}kCWd||gBF!|G#to{Ck-+J*&%TKXNDLsORQwVc9mpM4-9)d2~(7qxOoLi z`;9Zj;KHdRp^LO-?z>H>vhtV4)tcsaUp3upwv?lEW`xRVCyEqnWL%VX zT06&19ymPX5Ijn7UE4En*KHmv#d(HdTO4NC7gh>@4aiN~qvwj0)ba`MZ_438|uq+P{23?bFZ>g+tzMAaD3!5Pu6{K``BtY|Qky_qU= zb4NCYqoe&At*R`o+)aDB$(|T-1CSo-761n`q5<@OMX$M1XT=6@CG$Ib+kGSG*k?@p zK>{TFZe%`_$TLP(zQ#DQF>z>g*=Pt0;JyHtlys$sjI*{NYtDkNxY2EabfP~!uCj}SeCED$6B(^dV6HvN-AHHmj*mFMfPM^)hRxTBP1@~;tZ)d6#%H12FPs zX|I{8`85CKI@Uha)8bi@>x3@(Uhu zLE6Xw6&wE)ati~f*dc#Wv9S(*sMxhxfQpT7_+#%6@-T!3G*kR7gQ0yW=qs@43bp~r zDa_vhn!^D)DGq>-xd^;xf`R?~3n7qsbnfG8c2OXOVapwwmnam}0c`OjfDY^)0D$=D z0iO;LS)p__-!jmZ0hnxHeE)3KpS1dOUj4~~|H+jh@(8KD1WjuUBPT62Z+kQm@AC-Q z-0urg6f#^1F>AXr#yqdD;ONm#fd!*J9+c*}YQ#*uf65sR( zg4(2v>kM`jVY~)EZ6x7ZgtG28#x&^E5yc(q(v?c&?c?8lW=JE>a<><~#D(-LK2%}^ zcHToGNc8ZOa1pTeuC27(cmWt>#(!u=QQ@v`LWoOpV>8Kj6Kf8#W@tKPHWTl((g8hgt6PrnOVR}y5N|24R+h2d( zb-Ch_i9PgK;f}SJFaud-DSgxeLK$;ReQ}>YSLHDvc2pE3wUi+?$DO9 zOC*!2>(hG>Yd?VA{bhE1%6)8czSRbocw;ip2>C5n#CPQIS+RBatBU8ALQdWqXi7L; zD$`tt;RY;rnN`sx`)5YUA)}Yvmt0R>KL4SPcDik&*2saZPWXI_#AYf#2RwB& z?q0q@yyPz=?VHABV^x|#aDLunXNNQQz3~aMCc1$l3o><}?zBJSooE-qY-iDf5~GiL z5)z7Zg~THfB37nh{ce#f8tPwm0R8t4cmIN}w}-T>z1u9ZO`frHMB3Ha(bWzI9XC*3 zXN_?0ILdL3dqP#3{LR_#?fO4H^DAROx_e3iG0t$url|CJyWug1P0QKTb<)mHbO5;c zql4RbN5D0JSU^|$yp!UXT@f%$uK`nC+SOMWfXwz4y}mSDpXl{yhsr#G?504jk;@br z?m-?`ob9U=7xX(}unyU;<>4|8bb@pl!9pdui*WYSi71hec>)(M4rMTnm8-34R`aZ2 z%3G-^iQ5J6rbDG8jwjH^uEu0)-b&MhUgp0#mQfxUlI#?}CN71ToQlx-XCLfQY+XaN zxb_c-XAzPFbxLu=(w{`Tg;~&hGpj4PJz+L$z;{+)FQ22-7BfSRG+fkS&#(S99LoP^5S_TzgM(w4ia$xrP zO%WC3?<~|Yi^#l>C!frR0^DU7v}iN4fYvQE#31*9lUkOJ_X!fbgWPRM5uWnXasi+8 zCV+pL;gl22+teXY_U(39}v{a@J{vJgIErEQ6aPTZ?=2R%YsF*GKEoG0S8h{YYM#4Hw$WXxPLS)2c%Y#>W- zyEdJJN$Fo`rxzbZHLBUg*;~#qD+!RaUNy(RpBXSPubJv}(FR~OSYm_zDEmzIIIL>v~-{Qj_tO_pSU=6fMbyjW(+b!rCs z9SHXtNljsD7%~oMs8f);Xd9~H?FLi#B1h`^7cx?fju?HNB0J|uWx`f4BO^M7(`^}+#r}*UzWc|nA>CfQ-`s*oZ;=j=q z&90tcGnAyA)yGuuu*Y>8L*tXudo|g!cb~J25W)v4^$2Nk=BrF$TWeXU9p)dr4c!v* zUY4G$N_NK2^N57s5leHABXL9_`9NL>+-Jhc3SGe0?n9q7p zM{|go2_ONb;TtIQ*p_l5b8Rypu&~&bvh?VA#<(r^>cis2Rj_$u`f|NOTR9!Gt=bi| zDfh(4>94I^=**THtulW^YI?U)6(hGs>2(M*4cK71HUV>tAz*+I^O_#Q3n`T6kCR{dhJfhzN0ug^8xq@4CR8!N*WyJ z9uQQBM?N^9s@&3k_XqdvzJR zNkskO0{TjGZ&sN$yTFDKUh&O0|j zbEalvP{lW!CP;b0#7njy_N8{5e3r!Pypb-z-d?o48tvOdv>w_l$zzima%q~hR`H?9 z!rFH$_-c!Earr&=^ori@Ov~LsKF?v8@*(K&HA#iL3Jjgn` z2nU9F>g-t1fCDQ0T*?3Z@p?F&{`dEwZZ9kcxo&<^Y+)2U`+UnJ8!KY&k~hj*RgC^O zZV}llTJ+Xoz#kAyY-o%61+85{q+{{67gvJQPD5O3n3Fz&Y(uIs`m5|^d}_KXCh+$& zL8-=1jsE+yProOjzz0wB@fo$QKh!^XS2fpc(nd}-)}w6+p4UAix`E@M`0Uv!V_;v1x}TFCp&XwA86Xv;F0Z%)y60~eY| zLB6hb+d#Q#L!zvra<mEwK}ueRGmd5@5Lw7;JmGpWHFvupUw=NbqI;wmjGg$ZZ5Ej~`2#8+v6erK&m8?0lrNwZn)# zj*WipwVB54!__&8Au;@M=-hbGX;~@7({pI42M(-1l|HoMW4+X+n;tx-Y;$9jFUiG2 zXZbqrRa7{K>1$faF;6&>a)0r{-Q_Z@@AU}-jT#W#aB*ASxho~4w35x(T3-j0xt3Z5 z>XNdJYe@1+}_-tkE%vPs`G|Xpl@W#HJnUW+yi3KH zg{Vmc@G^PzW{sM@rP8XB;n$kk=D4@PM|0wy1!x~oT~G_n-8kxnVP7NSx(^vH&oMUh zwt6wgL8Zs>9cc=mDMV#Ow&$%#Oc;(G)d`a|EA{@~#qsNu=sN34*$s*)G)7-@!PqAK znBZ{g?rl2Yf5Y+^&iu#C7;vHN=hA+`MYH1G$m}%0f=wr~-$tBuk~6+gS$rr=s|v%!MmO5 zVQyxv7rYH6T_G6$de)=55DO-@D}@3|agum7s7ZtqsnZ(VRK&I6^)}RU*Ndm6v}Jwp zIP`?|Qqi^bf3Wx7aZ#*W)-VVNC|ROJB?$;9IX8$Tk(`r=1Zi?k0xcjpgMbnx=bUrS zl0!q2b52c8eZKO{+%tOSp1E_s_x@)7c;A2QuBNPd`su2A_Fil4wGZEPcRb$8m@tZ> zfj?F9UYtdxVM3PF2wRw}Q@FqF7Mq!2CXh4$lXWtQkxYD%rdej>`n1)VcvCA(Y*5vZ zj4G~KVdoT4fiwSJMZz^Ht|Q5~g8Y7dC{CMBZN;>s465@Ufh+#r;M_=bLzJg(1QMB* zxpOCiIjX&_iua*G61yY#anP7?ZMzO3|?H7#s-mJakD zw}g0(*x5d+dk5xQd*KNc?iGc5WJu|M}DalyJp-Gbt+L<1#S$BXI5$NBP zbg}(A0*l$W^aUlZiDI(}*{Yo%$gagjRPT?(62EA-KB{mXqN*G=PiFLy9o{=-p%1#z z8zO4Vm1*nPqeW9TLi*Tnigb%jeYgO`^8UOzMfZ-EiOy1-?XkN8EhJM`A*Ni~e#^-g zS=?~{SfTHRjDq}p+sx!cfpM{55B|fB^*-3;$w?i_qga`aG;VTyZBf826>o(UIWYYS z(R3(`6V!UR5r|W6nqpOM$#J-VLnN_iy6MZp4=gRa7SC*I{U;U-9l3q3|gkXea-a?~ipNazS%MmG_R* zMO>`x-<4Dxsouuug#%ys6AO^&q__YIhV9>wLa7gZ%~OsKsBdrekBXJj>OqyZRQk5- zko+mOp#!0M1YV&%!UMn)n)49=aY0lB8ESx>pF+ACC4+w7)#jhxvs>jtj%Z@8D%-$@ zb^ko0n&&v`sNRT}1}?UW) zHE*?DctwK-G1iAGvSSR@BAa^r?cW-$78lC9v!_de9nrE9z(!VYKRCz2P(#n2wUVK1 zLXdR`714POEZNfYb%X1-80FYbo|+npk|sFvTi`&TysLnLlHFw#hhA6S;CI3{c@CNG z`SXn7?i;zESx&9}0&=3Uu7pF_O@V-hpi%HwsbNp0V^L3!{WSF$%2v^VuvJ-Tdb*&nU zL*P(LBtLa-VZOicB6)dGRB@{fTVgL(^B$AdIjeRn&|B~>@}bfr=Y@!R+ZNI;g-jhvbp5W_KNJdohOK_y=H!Or zZ&`HMZoB}&nJ1HsELtsIR!0XX8WgxAhI)E-RELcu!rv@J2o#68Q}9rmQ2n z+ZTl?QqgJ;iL=i{1L;`n7C7_qz0(I)ym1FARu+ObRinN|s74N-;+=hZ~@1BCLw?P1>y9*RuZ}R5;yC$6|UjoS(Vh9XLtWn{2 z>3Tr=^+U)N_BP~v9C9OJHX=%nMk=t@EOxTV~l0^tX~c7@_yjWaHQ z1tkZP_21d&AW$g)$9$Uy{_&6k2v7AwLgbkLH-`T=5C6pVU^CBs7@J<;;#ja-dB6T^ zysC&^`?uF9y?lyh;XVioGb-u`UEK@sH63ruLL6Gqfz{wak4E}($UUTu3P9i{1Sl!2 zny;Qh#dXK)Oq$J$&3La2!C5RrERR=vYbq;g{i0Cp$}8m>nIh-lg6&HA`*S8%wLTiS>q#tuqa(qPnkh zEY9P@^x|(tP71#DD@mX#+x7OG&Xlr~YaPF#1q6lR0xXsqP%^xqXd36X7PuQP80)w6 zo-am`;q<;hcS;#pZ|s?g5KFeh{&>(LQR%!(NJN^N8OMj)vL zPgt}t!9%JY-z+|1=FJvn&f|k|EV~YRHF-`p9MLyltzvq`4>Q`cS#u@_)d%~=`6|0_ zK72QtI|nLl_`0oXxu0E_tn(M9Xo{Pa=u4Oq4-rUOmDltDAed`4BNEz>z1*cMkY!(Y zR4()*aA(ak{Xbg0tO^7#1dl z55S9M`@b5hkwXz$^;A2Xu0(z25Uj-%xlxM~vG>^+GCqnf2KXLX)8kLu@9{fLC8o$X z)gzb=*Y@iTz~F3i0^StjJBlz|C1|jr=`bsIxu@Zo!yLKFhj4-YU3|hUvUH5v$Y-8* z0!eRXALtJA62W{p_o=#x!t#!0MX=zf(%MMN)N2aM zCupkQEN3)JP17d@>tu zxcDHvUz#t=R^sz&!uoA}ZH11)Jnv@`Gfd}2CT7e_&KcT5y5Eqn3W~Ud-wf<~H8e+U zr8mIC473((^%6>^wxYwbNqciOsv4X7Pisz^hYq0#r1+$6?}|BVg_5}T64s7GDbl*? zicpbWicg)SU}P+>KxUo|iW8#BWv1PVB%C2xIR@Az+j>yjeA_!>M)Yzc-oCudI_i2& zXbRTT%9oQVO5;{*_2W(jcAZa4GMIxQAc? z5KJni%co;MwePsHcA4m5Hs>F3!(A{V9O5Q+&AtEiw)`o_j8vKQT$po_G@Eqqpj4y0 z`+Z}c;sP^XWz5W`uO>cEG_^1vu#FnQylc z7~=)p*!NTlwRN>k&un4s*4#c6c&TsH9xI}hkfQp*aL`qfQgBV70*?EY9&U$UPg%zJ zG&RdI%z^?qL^sSw4lfzT3m{s%W9!aOU0LD+zVI0 z)6LQ0Z^|#^ewY97lu`F9MO!`8y#Jue;L)SLD3Wt4e&M(_Dy(MSIL!k!kZRQ3aVY&!nqnW1Y9c-^FGLFOL0 ziC8fnK4DX{G8?ce(?VnYuUsQhspec~KxADz(DoAyg{6m!c!2=mkdi3K7JZ{@#XRki z&{bH5N=ICT6jiDtmaUYvg&IDigW~;{GD}j*=A#ZEAR>%Iv;nJCM(pY87Es+&SA6Sh z-F%X#ePY+An6K7lw!M%iRIpt6iirWlQv@ZNa_~b%^!iH4LOPjRSN;=llU7T z?EW~Ja${0Uz1JvHaeYZEYf@8Q3-{)-%2I;wA-;hO8u4CO)eH@1eZ< z^4(Z?8?=LY#pAj^9Q#OFPy z@N8Iu!#~>V1i4!3RmZhP5NH!O9YDw?^$}7<3f*qi;T8p~bYooCd_-B8EHK^5cDSgL zU!ZN2?Lw4*B6|9W?po+VFiw)$`%#Cg#EvGghs5xHH^0(-~Gh$CmkgpgrsAlhv$Xub&-CI9aX^nd6m4_tx~qPw82A88&_9L)HpZmlWP zz{B!x&ufBi;e6Rf*}Iq0kxt2iK3Z290*!mo5O4;uO?qeL(_+g0(n!~*hA*CP3VY-& zTI0h?{q75k?9ibqC?B4Q`evQ(Bs>WIR=6mEZL)1=AI4_g${ycb969h`N07kI+IhE1E6K zVFsV07PjzD-}oGZUVVSB;E|&R9=@!G#-5c%haUIkaGo+m&2P`c(UK=!vVH4h9{8zT z1Pu-w1i{Vcl$VJ12WE#^_xmc@8N`Oqx zXD2Ks%DH)Q^6ftFFH&C?stZUK_}}x{zp&8$vrhW&ZU1XiN&TZO-dlU?H8n2kOOlGA ztCL{hwj;9IK?pMdRic(Rd07C~@c8U204_&DHt&4o`tR7Ef2$jaeq!t@O-mC%opR$8 zcl~DQdJM8C1k}wKO#{qjX!EVT{+e7(7MGHbP+$4f%>e6CM;3$Zq)Xq#kSWf+LtGD_r0QQ_#YQRg*u*p z^v2+PDMpEKEb{xu;0aUagy#`THA5U1a=6EGA&Fc=)ad?sf3lF30@EM|GKE*zCpE~0 zybwQ-M^oQ;{TPg7IPhEu4+QN&e?yXp-!w0>O_j^3soG86$y2!0w~r+#%D`+$y+1e-QCvXQAiq}x z$*vXO0MANf$W5f|uXRPhlM1ujAGApebRz{qu4Qv^X{f`V6B+&3x+^gU3g#o1FGj}l zP^1`|Ri0-b9%yr2mH;de`wb=p{`fx*Is|F6T^hOq6nm?fz!aAn0#l*f5H>n`{yq8i zo&r;s4W>|J*vH8Mdsy>Lm2-*|2}pAj_yvhiH=Ne9hoZhgGcE^0+d>WlkGh!`(WJ2{gz zTM;d^@(WsLM>RH~$!uOlnBK=ZOul}q45$_Q11w=F{eVtah`iuV+{*d}MDopn65JjAZG z%w;9IrI1K5j}Qy#8Jc7BVNu2RF3=L|#PMT4h2*hy)Q=dqL$q|b9jf_#Jg65Pb7+!W=`#fs(#RZw{K1++<5hB{1U!|M_LMQ z%@JbRh`P?-kkW}Oez!hA<|&eC>D@MG@1TZb2P2v-K__Vf6M%gN1sM3T{|%oM#T&@h z>vm?HjB~4sdMz$XQF2)-h#Wd2&V>E(t~l1BkrGj`P9H2b*PV@xHYCTxn{P?Q+o?#N z(<@3w$T7b2;oykdgP;nE%X-nF=EvCD= za)1J;A-KRi>5iyNSn4G*>$H52*7#_%4Te;DPbkl%UP)yB!7=BG!F;RbPsy!qlJ;kFB*=98wq!zelyv|ZJgHTe|9NdE4~f`|1Sq&s8bbf7s#br`bx zW(>45%6^Nah^lWi2>^`jmca8IcnpRqoyl1vyw4Uc?m#Zqen%7k@BTZ*T*{5h3~=dj zBh+-%s$$_R9~@qc2)A){+mK2K)}Er~=;9uz!#5{irK-^*VIeVkf{wQJcY{Iuz#ZrX z)OM;Of4>NRRX6F7Zfx$1olm9&lX=S#!g99-8CpZJk>#1Lgc2|=-8bY_lheZ3bXOiE zFpB6YN9-#tF9`RgEDjwR z7MJ!GrCdKAx-N$-zD&7Mqn;*)%q0MH@sHIb2Zc)7z24<*d)h0OYr^8iAC8;8!P+Dc8`ze8k-9x0M*;6WPk`^pT^fw-5l6-vBd!1c1&I>AUd@ zw`hCKhp2!-O5a4<|1CT4;ZkqT(~JwTogM0CuKJnw1d%I;w(iusb}<)wH}J273if+Q zX-OACHb(Uqs)RXjKwiZ%fCzc-m(t~@{e|Er`iY`FF6*jR=hZz(C7sLE7a=OQ=u5Rf zY1!-Zm11O=B=WUEW}v<}b=%RrZ;3`p2kd3n&9tdSEP98&h{9zs+o&|bq{~X^`thnp zC?Oxys@GbN{EGiOGG_`0qTJi!WzZE-Gdz|0Lg}aX>bRJ^_4+@g^%L*j)`4#B>aVi< zRTRGJ(@7}Q*bTOQs;HBv-7{GKSQ&+&FPpA(g~GOXM-R<@0fqp=kyPM{VaERr$(Q=q zO_g?4tG#aEf(yS4e8-e&l!8EEhYLLXrGEM6QK&iUnJXW$MLRpEdj#EA5VXI|r5ikH zS+pO=9jr{3R9#(TC$ zji9a3QJ7$^Rn$Cv%~v&}7)5lOS{UZGXm59xoW@v%9*Z<5CFkq1GEThF1XE(rv#`Ai ztW#kRbKf6=uhOZT=ECO1TZ9x@#*RR2u4S%ybu#S-QVU0Z%Ne;aj8~|EX92TiaU6VP zJ+}QJxSHLa_XAF9+1a>=<|oymlOtm8bjR=Fl}NEV32D8>x@myU-$A=;hx>s%dE7D% zmLhU5pBXrvJ4pS85C67RuuH?Q>8cAcxWEfdd`QbQSI z(cY`lc&7&RpgxG)H!IBcbr*cQeddM}XVusFx&8e^yeV2*lp;)OaakRR-fu|#Vt^xO z_2pNAuH0poW)z(T)3dYTZKx!J=A-&Bg~%_&_&tk~L*;Y?_fB`ZY*b^`;@q*<#yanRGQCEQjzzrnWhxu3EaSADPLB(3+`VeG;(0u-q>uz+kM`VMu