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lines changed Original file line number Diff line number Diff line change 5252 // The datasheet specifies a typical SPI SCK period (tSCK) of 42 ns,
5353 // see "Table 36-48. SPI Timing Characteristics and Requirements",
5454 // which translates into a maximum SPI clock of 23.8 MHz.
55- // Conservatively, the divider is set for a 12 MHz maximum SPI clock.
55+ // We'll permit use of 24 MHz SPI even though this is slightly out
56+ // of spec. Given how clock dividers work, the next "sensible"
57+ // threshold would be a substantial drop down to 12 MHz.
5658 #if !defined(MAX_SPI)
57- #define MAX_SPI 12000000
59+ #define MAX_SPI 24000000
5860 #endif
5961 #define SPI_MIN_CLOCK_DIVIDER (uint8_t )(1 + ((F_CPU - 1 ) / MAX_SPI))
6062#endif
@@ -81,7 +83,7 @@ class SPISettings {
8183#if defined(__SAMD51__)
8284 this ->clockFreq = clock; // Clipping handled in SERCOM.cpp
8385#else
84- this ->clockFreq = ( clock >= ( MAX_SPI * 2 / SPI_MIN_CLOCK_DIVIDER) ? MAX_SPI * 2 / SPI_MIN_CLOCK_DIVIDER : clock) ;
86+ this ->clockFreq = clock >= MAX_SPI ? MAX_SPI : clock;
8587#endif
8688
8789 this ->bitOrder = (bitOrder == MSBFIRST ? MSB_FIRST : LSB_FIRST);
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