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Add tests for tree-sitter beautify
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‎Makefile

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,11 @@ test_run_pkg_el:
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gen_beautify: recompile
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$(ERT_TESTS) gen_beautify_dir
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gen_beautify_ts: recompile
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$(ERT_TESTS) gen_beautify_dir treesit
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gen_indent: recompile
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$(ERT_TESTS) gen_indent_dir
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$(ERT_TESTS) gen_indent_dir treesit
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gen_indent_ts: recompile
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$(ERT_TESTS) gen_indent_dir treesit

‎test/files/beautify/axi_demux.ts.beauty.sv

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‎test/files/beautify/instances.ts.beauty.sv

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//-----------------------------------------------------------------------------
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// Title : Verilog-Ext Instances Test
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// Project : Verilog-Ext
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//-----------------------------------------------------------------------------
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// File : instances.sv
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// Author : Gonzalo Larumbe
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// Created : 2022/11/15
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// Last modified : 2022/11/15
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//-----------------------------------------------------------------------------
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// Description :
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//
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//-----------------------------------------------------------------------------
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// Copyright (c) Gonzalo Larumbe <gonzalomlarumbe@gmail.com>
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//
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//------------------------------------------------------------------------------
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// Modification history:
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// 2022/11/15 : created
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//-----------------------------------------------------------------------------
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module instances;
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// Regular block
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block0 I_BLOCK0 (
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.Port0 (Port0),
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.Port1 (Port1),
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.Port2 (Port2)
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);
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// Regular block (no space between instance name and parenthesis)
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block1 I_BLOCK1(
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.Port0 (Port0),
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.Port1 (Port1),
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.Port2 (Port2)
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);
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// Regular block with parameters
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block2 #(
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.Param0 (Param0),
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.Param1 (Param1),
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.Param2 (Param2)
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) I_BLOCK2 (
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.Port0 (Port0),
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.Port1 (Port1),
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.Port2 (Port2)
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);
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// Regular block with parameters (no spaces in the identifiers)
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block3#(
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.Param0 (Param0),
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.Param1 (Param1),
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.Param2 (Param2)
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)I_BLOCK3(
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.Port0 (Port0),
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.Port1 (Port1),
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.Port2 (Port2)
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);
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// Generate
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generate
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for (genvar i=0; i<VALUE; i++) begin : gen_test
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block_gen #(
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.Param0 (Param0),
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.Param1 (Param1),
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.Param2 (Param2)
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) I_BLOCK_GEN (
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.Port0 (Port0),
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.Port1 (Port1),
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.Port2 (Port2)
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);
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end : gen_test
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endgenerate
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// Interfaces
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test_if I_TEST_IF (.clk (clk), .rst_n(rst_n));
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test_if_params # (.param1 (param1), .param2(param2)) ITEST_IF_PARAMS (.clk (clk), .rst_n(rst_n));
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test_if_params_array # (.param1 (param1), .param2(param2)) ITEST_IF_PARAMS_ARRAY[5:0] (.clk (clk), .rst_n(rst_n));
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test_if_params_empty #() I_TEST_IF_PARAMS_EMPTY (.clk (clk), .rst_n(rst_n));
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// Comments and whitespaces
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block_ws_0
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I_BLOCK_WS_0 (
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.Port0 (Port0),
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.Port1 (Port1),
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.Port2 (Port2)
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);
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block_ws_1 // Comment
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#( // More comments
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.Param0 (Param0),
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.Param1 (Param1),
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.Param2 (Param2)
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) // Even more comments
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I_BLOCK_WS_1 // More comments here
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(
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.Port0 (Port0),
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.Port1 (Port1),
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.Port2 (Port2)
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);
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endmodule

‎test/files/beautify/ucontroller.ts.beauty.sv

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//-----------------------------------------------------------------------------
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// Title : MicroController Top module
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// Project :
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//-----------------------------------------------------------------------------
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// File : ucontroller.sv
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// Author : Gonzalo Martinez Larumbe
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// Created : 2020/02/16
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// Last modified : 2020/02/16
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//-----------------------------------------------------------------------------
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// Description :
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//
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//-----------------------------------------------------------------------------
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// Copyright (c) Gonzalo Martinez Larumbe <gonzalomlarumbe@gmail.com>
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//
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//------------------------------------------------------------------------------
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// Modification history :
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// 2020/02/16 : created
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//-----------------------------------------------------------------------------
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module ucontroller # (
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parameter logic [31:0] FREQ_CLK = 100000000,
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parameter logic [31:0] TX_SPEED = 115200
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) (
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input logic Clk,
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input logic Rst_n,
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// Serial interface
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input logic RXD,
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output logic TXD,
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// ROM
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input logic [11:0] ROM_Data,
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output logic [11:0] ROM_Addr,
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// Exteral HW
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output logic [7:0] Temp,
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output logic [7:0] Switches
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);
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// Buses arbitrating
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logic DMA_Oen;
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logic DMA_Wen;
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logic DMA_Cs;
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logic CPU_Oen;
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logic CPU_Wen;
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logic CPU_Cs;
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logic [7:0] CPU_Address;
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logic [7:0] DMA_Address;
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logic [7:0] DMA_DataOut;
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logic [7:0] CPU_DataOut;
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logic Dma_Idle;
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// Serial <-> DMA
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logic [7:0] TX_Data;
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logic TX_Ready;
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logic TX_Valid;
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logic Data_Read;
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logic [7:0] RX_Data;
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logic RX_Empty;
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logic RX_Full;
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// DMA/CPU <-> RAM
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logic [7:0] RAM_DataOut;
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logic [7:0] RAM_DataIn;
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// ALU <-> CPU
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logic [7:0] ALU_DataIn;
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logic [7:0] ALU_DataOut;
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alu_op ALU_op;
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logic FlagE;
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logic FlagN;
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logic FlagC;
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logic FlagZ;
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// RAM signals
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logic [7:0] RAM_Address;
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logic RAM_Wen;
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logic RAM_Oen;
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logic RAM_Cs;
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// DMA <-> CPU
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logic Bus_grant;
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logic Bus_req;
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logic Dma_Tx_Ready;
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logic Dma_Tx_Start;
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81+
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// Instances
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cpu I_CPU (
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.Clk,
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.Rst_n,
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// ROM Interface
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.ROM_Data,
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.ROM_Addr,
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// RAM Interface
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.RAM_Addr (CPU_Address),
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.DataOut (CPU_DataOut),
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.DataIn (RAM_DataOut),
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.RAM_Cs (CPU_Cs),
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.RAM_Wen (CPU_Wen),
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.RAM_Oen (CPU_Oen),
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// DMA Interface
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.DMA_Req (Bus_req),
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.DMA_Ack (Bus_grant),
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.DMA_Ready (Dma_Tx_Ready),
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.DMA_Tx_Start (Dma_Tx_Start),
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// ALU inteface
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.ALU_op,
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.ALU_DataOut,
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.ALU_DataIn,
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.FlagZ,
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.FlagC,
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.FlagN,
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.FlagE
109+
);
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alu I_ALU (
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.Clk,
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.Rst_n,
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.InData (ALU_DataIn),
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.OutData (ALU_DataOut),
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.ALU_op,
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.FlagZ,
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.FlagC,
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.FlagN,
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.FlagE
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);
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dma I_DMA (
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.Clk,
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.Rst_n,
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// CPU interface
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.Bus_grant,
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.Bus_req,
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.Dma_Tx_Start,
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.Dma_Tx_Ready,
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.Dma_Idle,
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// Serial interface
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.RX_Data,
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.RX_Empty,
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.RX_Full,
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.Data_Read,
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.TX_Ready,
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.TX_Data,
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.TX_Valid,
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// Ram interface
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.Address (DMA_Address),
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.DataOut (DMA_DataOut),
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.DataIn (RAM_DataOut),
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.Cs (DMA_Cs),
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.Wen (DMA_Wen),
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.Oen (DMA_Oen)
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);
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uart # (
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.FREQ_CLK (FREQ_CLK),
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.TX_SPEED (TX_SPEED)
155+
) I_UART (
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.Clk,
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.Rst_n,
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// TX
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.TX_Valid,
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.TX_DataIn (TX_Data),
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.TX_Ready,
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.TXD,
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// RX
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.Data_Read,
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.Data_Out (RX_Data),
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.RXD,
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.Full (RX_Full),
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.Empty (RX_Empty)
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);
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ram_arbiter I_RAM_ARBITER (
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.Clk,
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.Rst_n,
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.DMA_Bus_req (Bus_req),
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.DMA_Bus_grant (Bus_grant),
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.DMA_Idle (Dma_Idle),
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.CPU_DataOut,
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.DMA_DataOut,
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.RAM_DataIn,
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.CPU_Address,
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.DMA_Address,
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.RAM_Address,
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.CPU_Cs,
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.DMA_Cs,
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.RAM_Cs,
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.CPU_Oen,
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.DMA_Oen,
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.RAM_Oen,
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.CPU_Wen,
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.DMA_Wen,
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.RAM_Wen
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);
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ram I_RAM (
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.Clk,
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.Rst_n,
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.Cs (RAM_Cs),
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.Wen (RAM_Wen),
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.Oen (RAM_Oen),
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.Address (RAM_Address),
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.DataIn (RAM_DataIn),
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.DataOut (RAM_DataOut),
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.Switches,
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.Temp
208+
);
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endmodule: ucontroller

‎test/scripts/ert-tests.sh

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,12 @@ gen_indent_dir () {
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}
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gen_beautify_dir () {
67-
run_elisp_cmd "(verilog-ext-test-beautify-gen-expected-files)"
67+
if [[ $# -ge 1 ]]; then
68+
run_elisp_cmd "(verilog-ext-test-beautify-gen-expected-files :tree-sitter)"
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else
70+
run_elisp_cmd "(verilog-ext-test-beautify-gen-expected-files)"
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fi
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6873
}
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7075
run_tests () {

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