Add tests for tree-sitter beautify

Makefile

@@ -30,9 +30,11 @@ test_run_pkg_el:
 gen_beautify: recompile
 	$(ERT_TESTS) gen_beautify_dir
 
+gen_beautify_ts: recompile
+	$(ERT_TESTS) gen_beautify_dir treesit
+
 gen_indent: recompile
 	$(ERT_TESTS) gen_indent_dir
-	$(ERT_TESTS) gen_indent_dir treesit
 
 gen_indent_ts: recompile
 	$(ERT_TESTS) gen_indent_dir treesit

test/files/beautify/instances.ts.beauty.sv

@@ -0,0 +1,109 @@
+//-----------------------------------------------------------------------------
+// Title         : Verilog-Ext Instances Test
+// Project       : Verilog-Ext
+//-----------------------------------------------------------------------------
+// File          : instances.sv
+// Author        : Gonzalo Larumbe
+// Created       : 2022/11/15
+// Last modified : 2022/11/15
+//-----------------------------------------------------------------------------
+// Description :
+//
+//-----------------------------------------------------------------------------
+// Copyright (c) Gonzalo Larumbe <gonzalomlarumbe@gmail.com>
+//
+//------------------------------------------------------------------------------
+// Modification history:
+// 2022/11/15 : created
+//-----------------------------------------------------------------------------
+
+module instances;
+
+    // Regular block
+    block0 I_BLOCK0 (
+        .Port0 (Port0),
+        .Port1 (Port1),
+        .Port2 (Port2)
+    );
+
+    // Regular block (no space between instance name and parenthesis)
+    block1 I_BLOCK1(
+        .Port0 (Port0),
+        .Port1 (Port1),
+        .Port2 (Port2)
+    );
+
+    // Regular block with parameters
+    block2 #(
+        .Param0 (Param0),
+        .Param1 (Param1),
+        .Param2 (Param2)
+    ) I_BLOCK2 (
+        .Port0 (Port0),
+        .Port1 (Port1),
+        .Port2 (Port2)
+    );
+
+    // Regular block with parameters (no spaces in the identifiers)
+    block3#(
+        .Param0 (Param0),
+        .Param1 (Param1),
+        .Param2 (Param2)
+    )I_BLOCK3(
+        .Port0 (Port0),
+        .Port1 (Port1),
+        .Port2 (Port2)
+    );
+
+    // Generate
+    generate
+        for (genvar i=0; i<VALUE; i++) begin : gen_test
+
+            block_gen #(
+                .Param0 (Param0),
+                .Param1 (Param1),
+                .Param2 (Param2)
+            ) I_BLOCK_GEN (
+                .Port0 (Port0),
+                .Port1 (Port1),
+                .Port2 (Port2)
+            );
+
+        end : gen_test
+    endgenerate
+
+
+    // Interfaces
+    test_if I_TEST_IF (.clk (clk), .rst_n(rst_n));
+
+    test_if_params # (.param1 (param1), .param2(param2)) ITEST_IF_PARAMS (.clk (clk), .rst_n(rst_n));
+
+    test_if_params_array # (.param1 (param1), .param2(param2)) ITEST_IF_PARAMS_ARRAY[5:0] (.clk (clk), .rst_n(rst_n));
+
+    test_if_params_empty #() I_TEST_IF_PARAMS_EMPTY (.clk (clk), .rst_n(rst_n));
+
+
+    // Comments and whitespaces
+    block_ws_0
+        I_BLOCK_WS_0 (
+        .Port0 (Port0),
+        .Port1 (Port1),
+        .Port2 (Port2)
+    );
+
+    block_ws_1 // Comment
+        #(     // More comments
+        .Param0 (Param0),
+        .Param1 (Param1),
+        .Param2 (Param2)
+    ) // Even more comments
+    I_BLOCK_WS_1 // More comments here
+        (
+        .Port0 (Port0),
+        .Port1 (Port1),
+        .Port2 (Port2)
+    );
+
+
+
+endmodule

test/files/beautify/ucontroller.ts.beauty.sv

@@ -0,0 +1,213 @@
+//-----------------------------------------------------------------------------
+// Title         : MicroController Top module
+// Project       :
+//-----------------------------------------------------------------------------
+// File          : ucontroller.sv
+// Author        : Gonzalo Martinez Larumbe
+// Created       : 2020/02/16
+// Last modified : 2020/02/16
+//-----------------------------------------------------------------------------
+// Description :
+//
+//-----------------------------------------------------------------------------
+// Copyright (c) Gonzalo Martinez Larumbe  <gonzalomlarumbe@gmail.com>
+//
+//------------------------------------------------------------------------------
+// Modification history :
+// 2020/02/16 : created
+//-----------------------------------------------------------------------------
+
+
+module ucontroller # (
+    parameter logic [31:0] FREQ_CLK = 100000000,
+    parameter logic [31:0] TX_SPEED = 115200
+) (
+    input logic         Clk,
+    input logic         Rst_n,
+    // Serial interface
+    input logic         RXD,
+    output logic        TXD,
+    // ROM
+    input logic [11:0]  ROM_Data,
+    output logic [11:0] ROM_Addr,
+    // Exteral HW
+    output logic [7:0]  Temp,
+    output logic [7:0]  Switches
+);
+
+
+    // Buses arbitrating
+    logic       DMA_Oen;
+    logic       DMA_Wen;
+    logic       DMA_Cs;
+    logic       CPU_Oen;
+    logic       CPU_Wen;
+    logic       CPU_Cs;
+    logic [7:0] CPU_Address;
+    logic [7:0] DMA_Address;
+    logic [7:0] DMA_DataOut;
+    logic [7:0] CPU_DataOut;
+    logic       Dma_Idle;
+    // Serial <-> DMA
+    logic [7:0] TX_Data;
+    logic       TX_Ready;
+    logic       TX_Valid;
+    logic       Data_Read;
+    logic [7:0] RX_Data;
+    logic       RX_Empty;
+    logic       RX_Full;
+    // DMA/CPU <-> RAM
+    logic [7:0] RAM_DataOut;
+    logic [7:0] RAM_DataIn;
+    // ALU <-> CPU
+    logic [7:0] ALU_DataIn;
+    logic [7:0] ALU_DataOut;
+    alu_op      ALU_op;
+    logic       FlagE;
+    logic       FlagN;
+    logic       FlagC;
+    logic       FlagZ;
+    // RAM signals
+    logic [7:0] RAM_Address;
+    logic       RAM_Wen;
+    logic       RAM_Oen;
+    logic       RAM_Cs;
+    // DMA <-> CPU
+    logic       Bus_grant;
+    logic       Bus_req;
+    logic       Dma_Tx_Ready;
+    logic       Dma_Tx_Start;
+
+
+    // Instances
+    cpu I_CPU (
+        .Clk,
+        .Rst_n,
+        // ROM Interface
+        .ROM_Data,
+        .ROM_Addr,
+        // RAM Interface
+        .RAM_Addr     (CPU_Address),
+        .DataOut      (CPU_DataOut),
+        .DataIn       (RAM_DataOut),
+        .RAM_Cs       (CPU_Cs),
+        .RAM_Wen      (CPU_Wen),
+        .RAM_Oen      (CPU_Oen),
+        // DMA Interface
+        .DMA_Req      (Bus_req),
+        .DMA_Ack      (Bus_grant),
+        .DMA_Ready    (Dma_Tx_Ready),
+        .DMA_Tx_Start (Dma_Tx_Start),
+        // ALU inteface
+        .ALU_op,
+        .ALU_DataOut,
+        .ALU_DataIn,
+        .FlagZ,
+        .FlagC,
+        .FlagN,
+        .FlagE
+    );
+
+
+    alu I_ALU (
+        .Clk,
+        .Rst_n,
+        .InData  (ALU_DataIn),
+        .OutData (ALU_DataOut),
+        .ALU_op,
+        .FlagZ,
+        .FlagC,
+        .FlagN,
+        .FlagE
+    );
+
+
+    dma I_DMA (
+        .Clk,
+        .Rst_n,
+        // CPU interface
+        .Bus_grant,
+        .Bus_req,
+        .Dma_Tx_Start,
+        .Dma_Tx_Ready,
+        .Dma_Idle,
+        // Serial interface
+        .RX_Data,
+        .RX_Empty,
+        .RX_Full,
+        .Data_Read,
+        .TX_Ready,
+        .TX_Data,
+        .TX_Valid,
+        // Ram interface
+        .Address (DMA_Address),
+        .DataOut (DMA_DataOut),
+        .DataIn  (RAM_DataOut),
+        .Cs      (DMA_Cs),
+        .Wen     (DMA_Wen),
+        .Oen     (DMA_Oen)
+    );
+
+
+    uart # (
+        .FREQ_CLK (FREQ_CLK),
+        .TX_SPEED (TX_SPEED)
+    ) I_UART (
+        .Clk,
+        .Rst_n,
+        // TX
+        .TX_Valid,
+        .TX_DataIn (TX_Data),
+        .TX_Ready,
+        .TXD,
+        // RX
+        .Data_Read,
+        .Data_Out  (RX_Data),
+        .RXD,
+        .Full      (RX_Full),
+        .Empty     (RX_Empty)
+    );
+
+
+    ram_arbiter I_RAM_ARBITER (
+        .Clk,
+        .Rst_n,
+        .DMA_Bus_req   (Bus_req),
+        .DMA_Bus_grant (Bus_grant),
+        .DMA_Idle      (Dma_Idle),
+        .CPU_DataOut,
+        .DMA_DataOut,
+        .RAM_DataIn,
+        .CPU_Address,
+        .DMA_Address,
+        .RAM_Address,
+        .CPU_Cs,
+        .DMA_Cs,
+        .RAM_Cs,
+        .CPU_Oen,
+        .DMA_Oen,
+        .RAM_Oen,
+        .CPU_Wen,
+        .DMA_Wen,
+        .RAM_Wen
+    );
+
+
+
+    ram I_RAM (
+        .Clk,
+        .Rst_n,
+        .Cs      (RAM_Cs),
+        .Wen     (RAM_Wen),
+        .Oen     (RAM_Oen),
+        .Address (RAM_Address),
+        .DataIn  (RAM_DataIn),
+        .DataOut (RAM_DataOut),
+        .Switches,
+        .Temp
+    );
+
+
+
+
+endmodule: ucontroller

test/scripts/ert-tests.sh

@@ -64,7 +64,12 @@ gen_indent_dir () {
 }
 
 gen_beautify_dir () {
-    run_elisp_cmd "(verilog-ext-test-beautify-gen-expected-files)"
+    if [[ $# -ge 1 ]]; then
+        run_elisp_cmd "(verilog-ext-test-beautify-gen-expected-files :tree-sitter)"
+    else
+        run_elisp_cmd "(verilog-ext-test-beautify-gen-expected-files)"
+    fi
+
 }
 
 run_tests () {