From ab407c3380779d4128edb8b0b14e38883e56b171 Mon Sep 17 00:00:00 2001
From: Gonzalo Larumbe <gonzalomlarumbe@gmail.com>
Date: Mon, 21 Aug 2023 14:20:36 +0200
Subject: [PATCH] WIP: Update tests with MELPA package

---
 test/verilog-ext-tests-setup-package.el  | 5 ++---
 test/verilog-ext-tests-setup-straight.el | 4 +---
 verilog-ext.el                           | 4 +---
 3 files changed, 4 insertions(+), 9 deletions(-)

diff --git a/test/verilog-ext-tests-setup-package.el b/test/verilog-ext-tests-setup-package.el
index 5a9b0d8..1a224f8 100644
--- a/test/verilog-ext-tests-setup-package.el
+++ b/test/verilog-ext-tests-setup-package.el
@@ -89,9 +89,8 @@
   (setq treesit-font-lock-level 4)
   (message "verilog-ext-tests-tree-sitter-available-p: %s" verilog-ext-tests-tree-sitter-available-p))
 
-;; TODO: Uncomment when integrated into MELPA
-;; (when verilog-ext-tests-tree-sitter-available-p
-;;   (package-install 'verilog-ts-mode))
+(when verilog-ext-tests-tree-sitter-available-p
+  (package-install 'verilog-ts-mode))
 
 
 (provide 'verilog-ext-tests-setup-package)
diff --git a/test/verilog-ext-tests-setup-straight.el b/test/verilog-ext-tests-setup-straight.el
index 28abd49..c3d273d 100644
--- a/test/verilog-ext-tests-setup-straight.el
+++ b/test/verilog-ext-tests-setup-straight.el
@@ -114,9 +114,7 @@
   (message "verilog-ext-tests-tree-sitter-available-p: %s" verilog-ext-tests-tree-sitter-available-p))
 
 (when verilog-ext-tests-tree-sitter-available-p
-  (use-package verilog-ts-mode
-    :straight (:host github :repo "gmlarumbe/verilog-ext"
-               :files ("ts-mode/verilog-ts-mode.el"))))
+  (use-package verilog-ts-mode))
 
 
 (provide 'verilog-ext-tests-setup-straight)
diff --git a/verilog-ext.el b/verilog-ext.el
index 13bf65f..3182706 100644
--- a/verilog-ext.el
+++ b/verilog-ext.el
@@ -25,6 +25,7 @@
 
 ;; Extensions for Verilog Mode:
 ;;
+;;  - Tree-sitter powered `verilog-ts-mode` support
 ;;  - Improved syntax highlighting
 ;;  - Builtin xref backend
 ;;  - Builtin capf function with dot and scope completion
@@ -44,9 +45,6 @@
 ;;  - Convert block end comments to names
 ;;  - Automatically add SystemVerilog keywords to `company-keywords` backend
 ;;  - Port connections utilities
-;;
-;;  Experimental:
-;;  - Tree-sitter powered `verilog-ts-mode` support
 
 ;;; Code: