testsuite/example/test-ecp5_versa: add vendor-library

tgingold · tgingold · commit ad5be7439eb4 · 2025-11-02T12:30:15.000+01:00
to reduce warnings
diff --git a/testsuite/examples/test-ecp5_versa/testsuite.sh b/testsuite/examples/test-ecp5_versa/testsuite.sh
@@ -20,4 +20,4 @@ VERILOG_FILES="\
 
 FREQ=25000000
 
-run_yosys -p "ghdl -gCLK_FREQUENCY=$FREQ --work=ecp5um $top/library/ecp5u/components.vhdl --work=work $VHDL_SYN_FILES -e; read_verilog $VERILOG_FILES; synth_ecp5 -top versa_ecp5_top -json top_ecp5_top.json" -l report.txt -q
+run_yosys -p "ghdl -gCLK_FREQUENCY=$FREQ --work=ecp5um --vendor-library=ecp5um $top/library/ecp5u/components.vhdl --work=work $VHDL_SYN_FILES -e; read_verilog $VERILOG_FILES; synth_ecp5 -top versa_ecp5_top -json top_ecp5_top.json" -l report.txt -q

Original file line number	Diff line number	Diff line change
`@@ -20,4 +20,4 @@ VERILOG_FILES="\`
`20`	`20`
`21`	`21`	`FREQ=25000000`
`22`	`22`
`23`		`-run_yosys -p "ghdl -gCLK_FREQUENCY=$FREQ --work=ecp5um $top/library/ecp5u/components.vhdl --work=work $VHDL_SYN_FILES -e; read_verilog $VERILOG_FILES; synth_ecp5 -top versa_ecp5_top -json top_ecp5_top.json" -l report.txt -q`
	`23`	`+run_yosys -p "ghdl -gCLK_FREQUENCY=$FREQ --work=ecp5um --vendor-library=ecp5um $top/library/ecp5u/components.vhdl --work=work $VHDL_SYN_FILES -e; read_verilog $VERILOG_FILES; synth_ecp5 -top versa_ecp5_top -json top_ecp5_top.json" -l report.txt -q`