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@fukatani
fukatani committed Sep 10, 2015
1 parent 3686ca7 commit ce77056
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Showing 4 changed files with 30 additions and 27 deletions.
28 changes: 14 additions & 14 deletions pyverilog_toolbox/testcode/test_ra.py
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Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@ def test_metrics_func(self):

def test_reg_clone(self):
cc_finder = CodeCloneFinder("reg_clone.v")
clones = sorted(cc_finder.search_regclone(), key = lambda t: t[0])
clones = sorted(cc_finder.search_regclone(), key = lambda t: str(t[0]))
ordered_clones = []
for clone in clones:
ordered_clones.append(str(tuple(sorted(clone, key=lambda t:str(t)))))
Expand Down Expand Up @@ -78,18 +78,18 @@ def test_floating2(self):
"['TOP.IN', 'TOP.reg1[1]', 'TOP.reg3[2]']")

#TODO correspond to travis
## def test_cnt_analyzer(self):
## c_analyzer = CntAnalyzer("norm_cnt2.v")
## cnt_dict = c_analyzer.analyze_cnt()
## self.assertEqual(cnt_dict['TOP.down_cnt'].tostr(),
## "name: TOP.down_cnt\ncategory: down counter\nreset val: 0" +
## "\nmax_val: 4\nmother counter:set([])")
## self.assertEqual(cnt_dict['TOP.up_cnt'].tostr(),
## 'name: TOP.up_cnt\ncategory: up counter\nreset val: 0' +
## '\nmax_val: 6\nmother counter:set([])')
## self.assertEqual(cnt_dict['TOP.up_cnt2'].tostr(),
## "name: TOP.up_cnt2\ncategory: up counter\nreset val: 0" +
## "\nmax_val: 4\nmother counter:set(['TOP.up_cnt'])")
def test_cnt_analyzer(self):
c_analyzer = CntAnalyzer("norm_cnt2.v")
cnt_dict = c_analyzer.analyze_cnt()
self.assertEqual(cnt_dict['TOP.down_cnt'].tostr(),
"name: TOP.down_cnt\ncategory: down counter\nreset val: 0" +
"\nmax_val: 4\nmother counter:()")
self.assertEqual(cnt_dict['TOP.up_cnt'].tostr(),
'name: TOP.up_cnt\ncategory: up counter\nreset val: 0' +
'\nmax_val: 6\nmother counter:()')
self.assertEqual(cnt_dict['TOP.up_cnt2'].tostr(),
"name: TOP.up_cnt2\ncategory: up counter\nreset val: 0" +
"\nmax_val: 4\nmother counter:('TOP.up_cnt',)")
## c_analyzer.make_cnt_event_all()
## self.assertEqual(str(c_analyzer.cnt_dict['TOP.up_cnt'].cnt_event_dict),
## '{2: ["TOP.now=\'d1 @(TOP_up_cnt==3\'d2)", "TOP.is_count_max=\'d1 @(TOP_up_cnt==3\'d2)", "TOP.up_cnt2=\'d0 @(TOP_up_cnt==3\'d2)"]}')
Expand All @@ -99,7 +99,7 @@ def test_cnt_analyzer2(self):
cnt_dict = c_analyzer.analyze_cnt()
self.assertEqual(cnt_dict['TOP.up_cnt'].tostr(),
"name: TOP.up_cnt\ncategory: up counter\nreset val: 0" +
"\nmax_val: 7\nmother counter:set([])")
"\nmax_val: 7\nmother counter:()")

def test_normal(self):
ranalyzer = RegMapAnalyzer("regmap.v", "setup.txt")
Expand Down
3 changes: 2 additions & 1 deletion pyverilog_toolbox/verify_tool/cnt_analyzer.py
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Original file line number Diff line number Diff line change
Expand Up @@ -101,6 +101,7 @@ def make_cnt_event_all(self):
cnt_ref_branch.append((ref_cnt_set, value))
cnt_ref_dict[term_name] = cnt_ref_branch
counter.make_cnt_event_dict(cnt_ref_dict)
#m_setter.enable_dfxxx_eq()
del m_setter

def get_reset_value(self, cnt_name, target_tree, reset_name):
Expand Down Expand Up @@ -310,7 +311,7 @@ def tostr(self):
"\ncategory: " + self.category +
"\nreset val: " + str(self.reset_value) +
"\nmax_val: " + str(self.calc_cnt_period()) +
"\nmother counter:" + str(self.mother_cnts))
"\nmother counter:" + str(tuple(self.mother_cnts)))

class up_down_cnt_profile(cnt_profile):
def __init__(self, name, up_cond, down_cond):
Expand Down
18 changes: 11 additions & 7 deletions pyverilog_toolbox/verify_tool/codeclone_finder.py
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Original file line number Diff line number Diff line change
Expand Up @@ -55,9 +55,11 @@ def search_regclone(self):
#sort for assign code(same assign reg must line up next to)
cd_order = collections.OrderedDict(sorted(code_dict.items(), key=lambda t: t[1] + str(t[0])))
clone_regs = []
cd_values = list(cd_order.values())
cd_keys = list(cd_order.keys())
for cnt in range(len(cd_order.keys()) - 1):
if cd_order.values()[cnt] == cd_order.values()[cnt + 1]:
clone_regs.append((cd_order.keys()[cnt], cd_order.keys()[cnt + 1]))
if cd_values[cnt] == cd_values[cnt + 1]:
clone_regs.append((cd_keys[cnt], cd_keys[cnt + 1]))

if clone_regs:
print('Clone reg pairs:')
Expand Down Expand Up @@ -108,14 +110,16 @@ def judge_invert_reg(values, target_values):
if not 'Reg' in tv.termtype: continue
target_tree = self.makeTree(tk)
functable[tk, bit] = splitter.split(target_tree)
ft_order = collections.OrderedDict(sorted(functable.items(), key=lambda t: t[0]))
ft_order = collections.OrderedDict(sorted(functable.items(), key=lambda t: str(t[0])))

invert_regs = []
ft_values = list(ft_order.values())
ft_keys = list(ft_order.keys())
for cnt in range(len(ft_order.keys()) - 1):
for target_cnt in range(cnt + 1, len(ft_order.keys())):#roop for same formal branch
if ft_order.values()[cnt].keys() != ft_order.values()[target_cnt].keys(): break #not same branch
if judge_invert_reg(ft_order.values()[cnt].values(), ft_order.values()[target_cnt].values()):
invert_regs.append((ft_order.keys()[cnt], ft_order.keys()[target_cnt]))
for target_cnt in range(cnt + 1, len(ft_keys)):#roop for same formal branch
if ft_values[cnt].keys() != ft_values[target_cnt].keys(): break #not same branch
if judge_invert_reg(ft_values[cnt].values(), ft_values[target_cnt].values()):
invert_regs.append((ft_keys[cnt], ft_keys[target_cnt]))
if invert_regs:
print('Invert reg pairs:')
self.deploy_reg_info(invert_regs)
Expand Down
8 changes: 3 additions & 5 deletions pyverilog_toolbox/verify_tool/dataflow_facade.py
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,6 @@
from optparse import OptionParser
import pyverilog.utils.util as util
import pyverilog.dataflow.bindvisitor as BindVisitor
from types import MethodType
from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
from pyverilog_toolbox.verify_tool.bindlibrary import BindLibrary
Expand Down Expand Up @@ -127,9 +126,8 @@ class dataflow_facade(VerilogControlflowAnalyzer):
"""
def __init__(self, code_file_name, topmodule='', config_file=None):
#TODO this corrspondence is temporal.
#pyverilog.dataflow.bindvisitor.BindVisitor._createAlwaysinfo = MethodType(_createAlwaysinfo, None, pyverilog.dataflow.bindvisitor.BindVisitor)
#pyverilog.dataflow.bindvisitor.BindVisitor._is_reset = MethodType(_is_reset, None, pyverilog.dataflow.bindvisitor.BindVisitor)
#pyverilog.dataflow.bindvisitor.BindVisitor._createAlwaysinfo = _createAlwaysinfo.__get__(pyverilog.dataflow.bindvisitor.BindVisitor)
BindVisitor._createAlwaysinfo = _createAlwaysinfo.__get__(BindVisitor)
BindVisitor._is_reset = _is_reset.__get__(BindVisitor)
#
topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist, fsm_vars = self.get_dataflow(code_file_name)

Expand All @@ -155,7 +153,7 @@ def get_dataflow(self, code_file_name, topmodule='', config_file=None):
if args:
filelist = args
elif code_file_name:
if hasattr(code_file_name, "__iter__"):
if hasattr(code_file_name, "__iter__") and not isinstance(code_file_name, str):
filelist = code_file_name
else:
filelist = (code_file_name,)
Expand Down

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