modify coding style

pyverilog_toolbox/testcode/test_ra.py

@@ -49,8 +49,8 @@ def test_reg_clone(self):
         clones = sorted(cc_finder.search_regclone(), key = lambda t: str(t[0]))
         ordered_clones = []
         for clone in clones:
-            ordered_clones.append(str(tuple(sorted(clone, key=lambda t:str(t)))))
-        ordered_clones = sorted(ordered_clones, key=lambda t:str(t))
+            ordered_clones.append(str(tuple(sorted(clone, key=lambda t: str(t)))))
+        ordered_clones = sorted(ordered_clones, key=lambda t: str(t))
         self.assertEqual(ordered_clones,
                         ['((TOP.reg1, 0), (TOP.reg3, 0))', '((TOP.reg3, 0), (TOP.sub.reg1, 0))'])
 
@@ -61,17 +61,17 @@ def test_reg_clone(self):
 
     def test_unreferenced(self):
         u_finder = UnreferencedFinder("unreferenced_variables.v")
-        self.assertEqual(str(sorted(u_finder.search_unreferenced(), key=lambda x:str(x))),
+        self.assertEqual(str(sorted(u_finder.search_unreferenced(), key=lambda x: str(x))),
                         "['TOP.IN2', 'TOP.reg2', 'TOP.reg3', 'TOP.sub.IN']")
 
     def test_floating(self):
         u_finder = UnreferencedFinder("floating.v")
-        self.assertEqual(str(sorted(u_finder.search_floating(), key=lambda x:str(x))),
+        self.assertEqual(str(sorted(u_finder.search_floating(), key=lambda x: str(x))),
                         "['TOP.in1', 'TOP.reg2']")
 
     def test_floating2(self):
         u_finder = UnreferencedFinder("floating2.v")
-        self.assertEqual(str(sorted(u_finder.search_floating(), key=lambda x:str(x))),
+        self.assertEqual(str(sorted(u_finder.search_floating(), key=lambda x: str(x))),
                         "['TOP.IN', 'TOP.reg1[1]', 'TOP.reg3[2]']")
 
     def test_cnt_analyzer(self):

pyverilog_toolbox/verify_tool/bindlibrary.py

@@ -11,7 +11,7 @@
 import sys
 import os
 
-sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
 
 from pyverilog.dataflow.dataflow import *
 
@@ -43,7 +43,7 @@ def dfx_memoize(f):
         """
         def helper(self, target_tree, tree_list, bit, dftype):
             if dftype == DFTerminal:
-                if (target_tree,bit) not in self.cache:
+                if (target_tree, bit) not in self.cache:
                     self.cache[(target_tree, bit)] = f(self, target_tree, set([]), bit, dftype)
                 return tree_list.union(self.cache[(target_tree, bit)])
             else:
@@ -180,7 +180,7 @@ def get_bind_index(self, binds=None, bit=None, term=None, scope=None):
             if scope is not None:
                 binds = self._binddict[scope]
                 term = self._terms[scope]
-            for index,bind in enumerate(binds):
+            for index, bind in enumerate(binds):
                 if bind.lsb is None:
                     return 0
                 if self.get_bind_lsb(bind) <= bit <= self.get_bind_msb(bind):
@@ -213,7 +213,7 @@ def get_bit_width_from_tree(self, tree):
             raise IRREGAL_CODE_FORM("unexpected concat node")
 
     def walk_reg_each_bit(self):
-        for tk, tv in sorted(self._terms.items(), key=lambda x:len(x[0])):
+        for tk, tv in sorted(self._terms.items(), key=lambda x: len(x[0])):
             if tk in self._binddict.keys():
                 for bvi in self._binddict[tk]: #process for each always block
                     bind_lsb = self.get_bind_lsb(bvi)
@@ -222,7 +222,7 @@ def walk_reg_each_bit(self):
                         yield tv, tk, bvi, bit, bind_lsb
 
     def walk_signal(self):
-        for tk, tv in sorted(self._terms.items(), key=lambda x:len(x[0])):
+        for tk, tv in sorted(self._terms.items(), key=lambda x: len(x[0])):
             yield tv, tk
 
     def get_bind_lsb(self, bind):

pyverilog_toolbox/verify_tool/cnt_analyzer.py

@@ -38,9 +38,9 @@ def analyze_cnt(self):
             funcdict = splitter.split(target_tree)
             funcdict = splitter.remove_reset_condition(funcdict)
 
-            up_cond = self.filter(funcdict, self.active_ope, op = 'Plus')
+            up_cond = self.filter(funcdict, self.active_ope, op='Plus')
             up_cond = {conds[-1] for conds in up_cond.keys()}
-            down_cond = self.filter(funcdict, self.active_ope, op = 'Minus')
+            down_cond = self.filter(funcdict, self.active_ope, op='Minus')
             down_cond = {conds[-1] for conds in down_cond.keys()}
 
             new_counter = self.cnt_factory(str(tk), up_cond, down_cond)
@@ -82,7 +82,7 @@ def make_cnt_event_all(self):
         end
         cnt_event_dict[3,'Eq)] = (reg1 <= 1'd1,)
         """
-        def make_cnt_ref_info(cond_dict):
+        def make_cnt_ref_info(cond_dict, cnt_name):
             cnt_ref_info = []
             for cond, term_value in cond_dict.items():
                 reffered_cnts = []
@@ -116,7 +116,7 @@ def make_cnt_ref_info(cond_dict):
                 funcdict = splitter.remove_reset_condition(funcdict)
                 if not funcdict: continue
                 cond_dict = {func[-1]: term_value for func, term_value in funcdict.items()}#extract last condition
-                cnt_ref_info = make_cnt_ref_info(cond_dict)
+                cnt_ref_info = make_cnt_ref_info(cond_dict, cnt_name)
                 if cnt_ref_info:
                     cnt_ref_dict[term_name] = cnt_ref_info
             counter.make_cnt_event_dict(cnt_ref_dict)

pyverilog_toolbox/verify_tool/codeclone_finder.py

@@ -10,7 +10,7 @@
 import os
 from collections import OrderedDict
 
-sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
 
 from pyverilog.dataflow.dataflow import *
 from pyverilog_toolbox.verify_tool.dataflow_facade import *
@@ -45,7 +45,7 @@ def search_regclone(self):
         end
         """
         code_dict = {}
-        for tv,tk,bvi,bit,term_lsb in self.binds.walk_reg_each_bit():
+        for tv, tk, bvi, bit, term_lsb in self.binds.walk_reg_each_bit():
             if not 'Reg' in tv.termtype: continue
             target_tree = self.makeTree(tk)
             code_dict[tk, bit] = target_tree.tocode()
@@ -105,7 +105,7 @@ def judge_invert_reg(values, target_values):
             return True
 
         functable = {}
-        for tv,tk,bvi,bit,term_lsb in self.binds.walk_reg_each_bit():
+        for tv, tk, bvi, bit, term_lsb in self.binds.walk_reg_each_bit():
             if not 'Reg' in tv.termtype: continue
             target_tree = self.makeTree(tk)
             functable[tk, bit] = splitter.split(target_tree)
@@ -128,7 +128,8 @@ def judge_invert_reg(values, target_values):
 
     def deploy_reg_info(self, regs):
         for reg in regs:
-            print(str(reg[0][0]) + '[' + str(reg[0][1]) + '] and ' + str(reg[1][0]) + '[' + str(reg[1][1]) + ']')
+            print(str(reg[0][0]) + '[' + str(reg[0][1]) + '] and ' +
+                  str(reg[1][0]) + '[' + str(reg[1][1]) + ']')
 
     def decorate_html(html_name):
         temp_html = open('temp.html', 'r')

pyverilog_toolbox/verify_tool/dataflow_facade.py

@@ -11,13 +11,14 @@
 import sys
 import os
 
-sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
 
 from optparse import OptionParser
 import pyverilog.utils.util as util
 import pyverilog.dataflow.bindvisitor as BindVisitor
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
+from pyverilog.dataflow.dataflow import *
 from pyverilog_toolbox.verify_tool.bindlibrary import BindLibrary
 from pyverilog.controlflow.controlflow_analyzer import VerilogControlflowAnalyzer
 
@@ -202,7 +203,7 @@ def make_term_ref_dict(self):
     def make_extract_dfterm_dict(self):
         return_dict = {}
         binds = BindLibrary(self.resolved_binddict, self.resolved_terms)
-        for tv,tk,bvi,bit,term_lsb in binds.walk_reg_each_bit():
+        for tv, tk, bvi, bit, term_lsb in binds.walk_reg_each_bit():
             tree = self.makeTree(tk)
             trees = binds.extract_all_dfxxx(tree, set([]), bit - term_lsb, DFTerminal)
             return_dict[(str(tk), bit)] = set([str(tree) for tree in trees])
@@ -229,12 +230,12 @@ def print_dataflow(self):
         """
         terms = self.binds._terms
         print('Term:')
-        for tk, tv in sorted(terms.items(), key=lambda x:len(x[0])):
+        for tk, tv in sorted(terms.items(), key=lambda x: len(x[0])):
             print(tv.tostr())
 
         binddict = self.binds._binddict
         print('Bind:')
-        for bk, bv in sorted(binddict.items(), key=lambda x:len(x[0])):
+        for bk, bv in sorted(binddict.items(), key=lambda x: len(x[0])):
             for bvi in bv:
                 print(bvi.tostr())
 

pyverilog_toolbox/verify_tool/unreferenced_finder.py

@@ -8,16 +8,13 @@
 
 import sys
 import os
-import copy
-import collections
 
-sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
 
 from pyverilog.utils.util import *
 from pyverilog.dataflow.dataflow import *
 from pyverilog_toolbox.verify_tool.dataflow_facade import *
 from pyverilog_toolbox.verify_tool.bindlibrary import *
-import pyverilog.controlflow.splitter as splitter
 
 class UnreferencedFinder(dataflow_facade):
 
@@ -35,15 +32,15 @@ def search_unreferenced(self):
         search input/reg/wire which not referenced any other output/reg/wire.
         """
         signals = []
-        for tv,tk in self.binds.walk_signal():
+        for tv, tk in self.binds.walk_signal():
             #Exclude parameter and function.
             if not set(['Input', 'Reg', 'Wire']) & tv.termtype: continue
             if 'Output' in tv.termtype: continue #because referenced as output.
             signals.append(str(tk))
 
-        for tv,tk,bvi,bit,term_lsb in self.binds.walk_reg_each_bit():
+        for tv, tk, bvi, bit, term_lsb in self.binds.walk_reg_each_bit():
             target_tree = self.makeTree(tk)
-            trees = self.binds.extract_all_dfxxx(target_tree, set([]), bit - tv.lsb.eval(), pyverilog.dataflow.dataflow.DFTerminal)
+            trees = self.binds.extract_all_dfxxx(target_tree, set([]), bit - tv.lsb.eval(), DFTerminal)
             trees.add((bvi.getClockName(), bvi.getClockBit()))
             trees.add((bvi.getResetName(), bvi.getResetBit()))
             for tree, bit in trees:
@@ -58,7 +55,7 @@ def search_unreferenced(self):
     @out_as_html(decorate_html)
     def search_floating(self):
         floating_signals = []
-        for tv,tk in self.binds.walk_signal():
+        for tv, tk in self.binds.walk_signal():
             if not set(['Reg', 'Wire']) & tv.termtype: continue
             if not tk in self.binddict.keys():
                 floating_signals.append(str(tk))