diff --git a/.gitignore b/.gitignore
index 59179eb..4f00ca9 100644
--- a/.gitignore
+++ b/.gitignore
@@ -15,3 +15,4 @@ pyverilog_toolbox.egg-info/
 *.bat
 
 *.html
+pyverilog_toolbox/gui/parsetab.py
diff --git a/pyverilog_toolbox/testcode/test_ra.py b/pyverilog_toolbox/testcode/test_ra.py
index e8433c8..a686676 100644
--- a/pyverilog_toolbox/testcode/test_ra.py
+++ b/pyverilog_toolbox/testcode/test_ra.py
@@ -77,6 +77,13 @@ def test_cnt_analyzer(self):
         self.assertEqual(str(c_analyzer.cnt_dict['TOP.up_cnt'].cnt_event_dict),
                         '{2: ["TOP.now=\'d1 @(TOP_up_cnt==3\'d2)", "TOP.is_count_max=\'d1 @(TOP_up_cnt==3\'d2)", "TOP.up_cnt2=\'d0 @(TOP_up_cnt==3\'d2)"]}')
 
+    def test_cnt_analyzer2(self):
+        c_analyzer = CntAnalyzer("norm_cnt.v")
+        cnt_dict = c_analyzer.analyze_cnt()
+        self.assertEqual(cnt_dict['TOP.up_cnt'].tostr(),
+                        "name: TOP.up_cnt\ncategory: up counter\nreset val: 0" +
+                        "\nmax_val: 7\nmother counter:set([])")
+
     def test_normal(self):
         ranalyzer = RegMapAnalyzer("regmap.v", "setup.txt")
         write_map, read_map = ranalyzer.getRegMaps()
diff --git a/pyverilog_toolbox/verify_tool/cnt_analyzer.py b/pyverilog_toolbox/verify_tool/cnt_analyzer.py
index 560fd04..0a44bf4 100644
--- a/pyverilog_toolbox/verify_tool/cnt_analyzer.py
+++ b/pyverilog_toolbox/verify_tool/cnt_analyzer.py
@@ -47,7 +47,11 @@ def analyze_cnt(self):
             load_const_dict = self.filter(funcdict, self.active_load_const)
             load_const_dict = {conds[-1] : eval_value(value) for conds, value in load_const_dict.items()}
             new_counter.set_load_const_cond(load_const_dict)
-            new_counter.set_max_load_const(max(load_const_dict.values()))
+
+            if load_const_dict:
+                new_counter.set_max_load_const(max(load_const_dict.values()))
+##            else: #free run counter
+##                new_counter.set_max_load_const(2 ** new_counter.msb - 1)
             new_counter.make_load_dict(self.binds)
             new_counter.make_change_cond(self.binds)
             self.cnt_dict[new_counter.name] = new_counter
@@ -96,7 +100,6 @@ def make_cnt_event_all(self):
                     ref_cnt_set = set([term for term in ref_cnt_set if str(term) == cnt_name])
                     cnt_ref_branch.append((ref_cnt_set, value))
                 cnt_ref_dict[term_name] = cnt_ref_branch
-            #print cnt_name, cnt_ref_dict
             counter.make_cnt_event_dict(cnt_ref_dict)
         del m_setter
 
@@ -121,6 +124,9 @@ def active_ope(self, node, **kwargs):
         raise Exception('Need op arg.')
 
     def active_load_const(self, node):
+        """ [FUNCTION]
+        Judge loading const or not.
+        """
         return (isinstance(node, pyverilog.dataflow.dataflow.DFIntConst) or
                 isinstance(node, pyverilog.dataflow.dataflow.DFEvalValue))
 
@@ -134,6 +140,21 @@ def cnt_factory(self, name, up_cond, down_cond):
         else:
             raise Exception(name + ' is irregular counter.')
 
+    def decorate_html(html_name):
+        temp_html = open('temp.html', 'r')
+        out_html = open(html_name, 'w')
+        for line in temp_html:
+            out_html.write(line + '<br>')
+        temp_html.close()
+        out_html.close()
+
+    @out_as_html(decorate_html)
+    def show(self):
+        self.analyze_cnt()
+        self.make_cnt_event_all()
+        for counter in self.cnt_dict.values():
+            print(counter.name, counter.cnt_event_dict)
+
 class cnt_profile(object):
     compare_ope = ('Eq', 'NotEq', 'GreaterEq', 'LessEq', 'GreaterThan', 'LessThan')
     plus_ope = ('NotEq', 'LessEq', 'LessThan')
@@ -193,6 +214,15 @@ def make_load_dict(self, binds):
                 self.load_dict[value] = (tree.operator, cnt_cond)
 
     def make_change_cond(self, binds):
+        """ [FUNCTIONS]
+        search condition such as below.
+
+        ex.
+        if(up_cnt2 != 3'd5 && up_cnt == 3'd5) begin
+            up_cnt2 <= up_cnt2 + 3'd1;
+
+        This counter's max value = 3'd5
+        """
         for cond in self.change_dict:
             tree_list = binds.extract_all_dfxxx(cond, set([]), 0, pyverilog.dataflow.dataflow.DFOperator)
             tree_list = set([tree for tree in tree_list if tree[0].operator in self.plus_ope])
@@ -251,7 +281,7 @@ def calc_cnt_period(self):
                 return self.change_cond[1]
             else:
                 return self.change_cond[1] - 1
-        elif self.load_dict[0]:
+        elif self.load_dict and self.load_dict[0]:
             if self.load_dict[0][0] in self.eq_ope:
                 return self.load_dict[0][1]
             else:
@@ -276,16 +306,11 @@ def __init__(self, name, up_cond, down_cond):
         self._set_category()
     def _set_category(self):
         self.category = 'up/down counter'
-##    def tostr(self):
-##        return (cnt_profile.tostr(self) +
-##                "\nplus cond:" + str(self.up_cond) +
-##                "\nminus cond:" + str(self.down_cond))
+
 class up_cnt_profile(cnt_profile):
     def _set_category(self):
         self.category = 'up counter'
-##    def tostr(self):
-##        return (cnt_profile.tostr(self) +
-##                "\nplus cond:" + str(self.change_dict))
+
 class down_cnt_profile(cnt_profile):
     def _set_category(self):
         self.category = 'down counter'
@@ -293,14 +318,8 @@ def calc_cnt_period(self):
         if self.load_const_cond and self.load_const_cond.values():
             return max(self.load_const_cond.values()) - 1
         return 2 ** (self.msb + 1) - 1
-##    def tostr(self):
-##        return (cnt_profile.tostr(self) +
-##                "\nminus cond:" + str(self.change_cond))
 
 if __name__ == '__main__':
-    cnt_analyzer = CntAnalyzer("../testcode/norm_cnt2.v")
-    cnt_analyzer.analyze_cnt()
-    cnt_analyzer.make_cnt_event_all()
-    for counter in cnt_analyzer.cnt_dict.values():
-        print counter.name, counter.cnt_event_dict
+    cnt_analyzer = CntAnalyzer("../testcode/norm_cnt.v")
+    cnt_analyzer.show()