cnt analyzer for python3

Author: fukatani

pyverilog_toolbox/testcode/norm_cnt2.v

@@ -2,13 +2,11 @@ module TOP(CLK, RSTN, UP_ENABLE, UP_ENABLE2, CLEAR);
   input CLK,RSTN,UP_ENABLE,UP_ENABLE2,CLEAR;
 
   reg [2:0] up_cnt;
-  wire is_count_max = up_cnt == 3'd6;
+  wire is_cnt_four = up_cnt == 4;
 
   always @(posedge CLK or negedge RSTN) begin
     if(!RSTN) begin
       up_cnt <= 0;
-    end else if(is_count_max) begin
-      up_cnt <= 0;
     end else if(up_cnt >= 3'd5) begin
       up_cnt <= 0;
     end else if(CLEAR) begin

pyverilog_toolbox/testcode/simple_cnt.v

@@ -0,0 +1,27 @@
+module TOP(CLK, RSTN);
+  input CLK, RSTN;
+
+  reg [2:0] up_cnt;
+
+  always @(posedge CLK or negedge RSTN) begin
+    if(!RSTN) begin
+      up_cnt <= 0;
+    end else if(up_cnt2 == 3'd6) begin
+      up_cnt <= 0;
+    end else begin
+      up_cnt <= up_cnt + 1;
+    end
+  end
+
+  reg now;
+  always @(posedge CLK or negedge RSTN) begin
+    if(!RSTN) begin
+      now <= 0;
+    end else if(up_cnt == 3'd4) begin
+      now <= 0;
+    end else if(up_cnt == 3'd2) begin
+      now <= 1;
+    end
+  end
+endmodule
+

pyverilog_toolbox/testcode/test_ra.py

@@ -86,13 +86,13 @@ def test_cnt_analyzer(self):
                         "\nmax_val: 4\nmother counter:()")
         self.assertEqual(cnt_dict['TOP.up_cnt'].tostr(),
                         'name: TOP.up_cnt\ncategory: up counter\nreset val: 0' +
-                        '\nmax_val: 6\nmother counter:()')
+                        '\nmax_val: 5\nmother counter:()')
         self.assertEqual(cnt_dict['TOP.up_cnt2'].tostr(),
                         "name: TOP.up_cnt2\ncategory: up counter\nreset val: 0" +
                         "\nmax_val: 4\nmother counter:('TOP.up_cnt',)")
         c_analyzer.make_cnt_event_all()
-##        self.assertEqual(str(c_analyzer.cnt_dict['TOP.up_cnt'].cnt_event_dict),
-##                        '{2: ["TOP.now=\'d1 @(TOP_up_cnt==3\'d2)", "TOP.is_count_max=\'d1 @(TOP_up_cnt==3\'d2)", "TOP.up_cnt2=\'d0 @(TOP_up_cnt==3\'d2)"]}')
+        self.assertEqual(str(c_analyzer.cnt_dict['TOP.up_cnt'].cnt_event_dict),
+                        '{2: ["TOP.now=\'d1 @(TOP_up_cnt==3\'d2)"]}')
 
     def test_cnt_analyzer2(self):
         c_analyzer = CntAnalyzer("norm_cnt.v")

pyverilog_toolbox/verify_tool/bindlibrary.py

@@ -262,7 +262,7 @@ def __init__(self, bind_library) :
         self.scope_dict = bind_library.scope_dict
         self.cache = bind_library.cache
         self.gnb_cache = bind_library.gnb_cache
-        self.disable_dfxxx_eq()
+        #self.disable_dfxxx_eq()
 
     def __del__(self):
         self.enable_dfxxx_eq()

pyverilog_toolbox/verify_tool/cnt_analyzer.py

@@ -79,30 +79,31 @@ def make_cnt_event_all(self):
         end
         cnt_event_dict[3,'Eq)] = (reg1 <= 1'd1,)
         """
-
+        #self.make_term_reffered_dict()
         m_setter = MothernodeSetter(self.binds)
 
         for cnt_name, counter in self.cnt_dict.items():
             cnt_ref_dict = {}
             for term_name in self.term_ref_dict[cnt_name]:
-                if term_name == cnt_name: continue
+                if term_name == cnt_name: continue #exclude self reference
                 scope = self.binds.get_scope(term_name)
                 target_tree = self.makeTree(scope)
                 funcdict = splitter.split(target_tree)
                 funcdict = splitter.remove_reset_condition(funcdict)
+                if not funcdict: continue
                 branch_dict = {func[-1]: value for func, value in funcdict.items()}#extract last condition
 
+                cnt_ref_branch=[]
+                m_setter.disable_dfxxx_eq()
                 for branch, value in branch_dict.items():
-                    cnt_ref_branch=[]
-                    ref_cnt_set = set([])
-                    ref_cnt_set = ref_cnt_set | m_setter.extract_all_dfxxx(branch, set([]), 0, pyverilog.dataflow.dataflow.DFTerminal)
+                    ref_cnt_set = m_setter.extract_all_dfxxx(branch, set([]), 0, pyverilog.dataflow.dataflow.DFTerminal)
                     ref_cnt_set = set([term[0] for term in ref_cnt_set])
                     ref_cnt_set = set([term for term in ref_cnt_set if str(term) == cnt_name])
                     cnt_ref_branch.append((ref_cnt_set, value))
-                cnt_ref_dict[term_name] = cnt_ref_branch
+                if cnt_ref_branch:
+                    cnt_ref_dict[term_name] = cnt_ref_branch
+                m_setter.disable_dfxxx_eq()
             counter.make_cnt_event_dict(cnt_ref_dict)
-        #m_setter.enable_dfxxx_eq()
-        del m_setter
 
     def get_reset_value(self, cnt_name, target_tree, reset_name):
         if target_tree.condnode.operator == 'Ulnot':
@@ -259,26 +260,26 @@ def make_cnt_event_dict(self, cnt_ref_dict):
         """
         self.cnt_event_dict = {}
         for term_name, ref_cnt_set in cnt_ref_dict.items():
+            root_ope = None
             for ref_cnt,value in ref_cnt_set:
                 if len(ref_cnt) != 1:
                     raise Exception('Found redundunt condition description @' + term_name)
                 ref_cnt = tuple(ref_cnt)[0]
 
-                if str(ref_cnt.mother_node) in self.compare_ope:
+                if ref_cnt.mother_node.operator in self.compare_ope:
                     root_ope = ref_cnt.mother_node
                     cond_lsb = 0
                     diff_list = [1,]
                 elif isinstance(ref_cnt.mother_node, pyverilog.dataflow.dataflow.DFPartselect):
-                    if str(ref_cnt.mother_node.mother_node) in compare_ope:
+                    if ref_cnt.mother_node.mother_node.operator in self.compare_ope:
                         root_ope = ref_cnt.mother_node.mother_node
                         cond_lsb = ref_cnt.mother_node.lsb
                     if ref_cnt.mother_node.msb == self.msb:
                         diff_list = [1,]
                     else:
                         diff_list = [i for i in range(1,self.msb - ref_cnt.mother_node.msb)]
-                else:
-                    continue
 
+            if root_ope is None: continue
             if str(root_ope.nextnodes[0]) == str(ref_cnt.name):
                 comp_pair = eval_value(root_ope.nextnodes[1])
             elif str(root_ope.nextnodes[1]) == str(ref_cnt.name):

pyverilog_toolbox/verify_tool/dataflow_facade.py

@@ -190,7 +190,7 @@ def get_dataflow(self, code_file_name, topmodule='', config_file=None):
         return options.topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist, fsm_vars
 
     def make_term_ref_dict(self):
-        self.term_ref_dict ={}
+        self.term_ref_dict = {}
         for tv,tk,bvi,bit,term_lsb in self.binds.walk_reg_each_bit():
             if 'Rename' in tv.termtype: continue
             target_tree = self.makeTree(tk)
@@ -200,6 +200,17 @@ def make_term_ref_dict(self):
                     self.term_ref_dict[str(tree)] = set([])
                 self.term_ref_dict[str(tree)].add(str(tk))
 
+    def make_term_reffered_dict(self):
+        if not self.term_ref_dict:
+            self.make_term_ref_dict
+        self.term_reffered_dict = {}
+        for ref, terms in self.term_ref_dict.items():
+            for term in terms:
+                if not term in self.term_reffered_dict.keys():
+                    self.term_reffered_dict[term] = []
+                self.term_reffered_dict[term].append(ref)
+        #print(self.term_reffered_dict)
+
     def make_extract_dfterm_dict(self):
         return_dict = {}
         binds = BindLibrary(self.resolved_binddict, self.resolved_terms)