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translate.c
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/*
* i386 translation
*
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include "cpu.h"
#include "exec-all.h"
#include "disas.h"
#include "tcg-op.h"
#include "helper.h"
#define GEN_HELPER 1
#include "helper.h"
#define PREFIX_REPZ 0x01
#define PREFIX_REPNZ 0x02
#define PREFIX_LOCK 0x04
#define PREFIX_DATA 0x08
#define PREFIX_ADR 0x10
#ifdef TARGET_X86_64
#define X86_64_ONLY(x) x
#define X86_64_DEF(...) __VA_ARGS__
#define CODE64(s) ((s)->code64)
#define REX_X(s) ((s)->rex_x)
#define REX_B(s) ((s)->rex_b)
/* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
#if 1
#define BUGGY_64(x) NULL
#endif
#else
#define X86_64_ONLY(x) NULL
#define X86_64_DEF(...)
#define CODE64(s) 0
#define REX_X(s) 0
#define REX_B(s) 0
#endif
//#define MACRO_TEST 1
/* global register indexes */
static TCGv_ptr cpu_env;
static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
static TCGv_i32 cpu_cc_op;
static TCGv cpu_regs[CPU_NB_REGS];
/* local temps */
static TCGv cpu_T[2], cpu_T3;
/* local register indexes (only used inside old micro ops) */
static TCGv cpu_tmp0, cpu_tmp4;
static TCGv_ptr cpu_ptr0, cpu_ptr1;
static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
static TCGv_i64 cpu_tmp1_i64;
static TCGv cpu_tmp5;
#include "gen-icount.h"
#ifdef TARGET_X86_64
static int x86_64_hregs;
#endif
typedef struct DisasContext {
/* current insn context */
int override; /* -1 if no override */
int prefix;
int aflag, dflag;
target_ulong pc; /* pc = eip + cs_base */
int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
static state change (stop translation) */
/* current block context */
target_ulong cs_base; /* base of CS segment */
int pe; /* protected mode */
int code32; /* 32 bit code segment */
#ifdef TARGET_X86_64
int lma; /* long mode active */
int code64; /* 64 bit code segment */
int rex_x, rex_b;
#endif
int ss32; /* 32 bit stack segment */
int cc_op; /* current CC operation */
int addseg; /* non zero if either DS/ES/SS have a non zero base */
int f_st; /* currently unused */
int vm86; /* vm86 mode */
int cpl;
int iopl;
int tf; /* TF cpu flag */
int singlestep_enabled; /* "hardware" single step enabled */
int jmp_opt; /* use direct block chaining for direct jumps */
int mem_index; /* select memory access functions */
uint64_t flags; /* all execution flags */
struct TranslationBlock *tb;
int popl_esp_hack; /* for correct popl with esp base handling */
int rip_offset; /* only used in x86_64, but left for simplicity */
int cpuid_features;
int cpuid_ext_features;
int cpuid_ext2_features;
int cpuid_ext3_features;
} DisasContext;
static void gen_eob(DisasContext *s);
static void gen_jmp(DisasContext *s, target_ulong eip);
static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
/* i386 arith/logic operations */
enum {
OP_ADDL,
OP_ORL,
OP_ADCL,
OP_SBBL,
OP_ANDL,
OP_SUBL,
OP_XORL,
OP_CMPL,
};
/* i386 shift ops */
enum {
OP_ROL,
OP_ROR,
OP_RCL,
OP_RCR,
OP_SHL,
OP_SHR,
OP_SHL1, /* undocumented */
OP_SAR = 7,
};
enum {
JCC_O,
JCC_B,
JCC_Z,
JCC_BE,
JCC_S,
JCC_P,
JCC_L,
JCC_LE,
};
/* operand size */
enum {
OT_BYTE = 0,
OT_WORD,
OT_LONG,
OT_QUAD,
};
enum {
/* I386 int registers */
OR_EAX, /* MUST be even numbered */
OR_ECX,
OR_EDX,
OR_EBX,
OR_ESP,
OR_EBP,
OR_ESI,
OR_EDI,
OR_TMP0 = 16, /* temporary operand register */
OR_TMP1,
OR_A0, /* temporary register used when doing address evaluation */
};
static inline void gen_op_movl_T0_0(void)
{
tcg_gen_movi_tl(cpu_T[0], 0);
}
static inline void gen_op_movl_T0_im(int32_t val)
{
tcg_gen_movi_tl(cpu_T[0], val);
}
static inline void gen_op_movl_T0_imu(uint32_t val)
{
tcg_gen_movi_tl(cpu_T[0], val);
}
static inline void gen_op_movl_T1_im(int32_t val)
{
tcg_gen_movi_tl(cpu_T[1], val);
}
static inline void gen_op_movl_T1_imu(uint32_t val)
{
tcg_gen_movi_tl(cpu_T[1], val);
}
static inline void gen_op_movl_A0_im(uint32_t val)
{
tcg_gen_movi_tl(cpu_A0, val);
}
#ifdef TARGET_X86_64
static inline void gen_op_movq_A0_im(int64_t val)
{
tcg_gen_movi_tl(cpu_A0, val);
}
#endif
static inline void gen_movtl_T0_im(target_ulong val)
{
tcg_gen_movi_tl(cpu_T[0], val);
}
static inline void gen_movtl_T1_im(target_ulong val)
{
tcg_gen_movi_tl(cpu_T[1], val);
}
static inline void gen_op_andl_T0_ffff(void)
{
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
}
static inline void gen_op_andl_T0_im(uint32_t val)
{
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
}
static inline void gen_op_movl_T0_T1(void)
{
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
}
static inline void gen_op_andl_A0_ffff(void)
{
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
}
#ifdef TARGET_X86_64
#define NB_OP_SIZES 4
#else /* !TARGET_X86_64 */
#define NB_OP_SIZES 3
#endif /* !TARGET_X86_64 */
#if defined(HOST_WORDS_BIGENDIAN)
#define REG_B_OFFSET (sizeof(target_ulong) - 1)
#define REG_H_OFFSET (sizeof(target_ulong) - 2)
#define REG_W_OFFSET (sizeof(target_ulong) - 2)
#define REG_L_OFFSET (sizeof(target_ulong) - 4)
#define REG_LH_OFFSET (sizeof(target_ulong) - 8)
#else
#define REG_B_OFFSET 0
#define REG_H_OFFSET 1
#define REG_W_OFFSET 0
#define REG_L_OFFSET 0
#define REG_LH_OFFSET 4
#endif
static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
{
TCGv tmp;
switch(ot) {
case OT_BYTE:
tmp = tcg_temp_new();
tcg_gen_ext8u_tl(tmp, t0);
if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xff);
tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
} else {
tcg_gen_shli_tl(tmp, tmp, 8);
tcg_gen_andi_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], ~0xff00);
tcg_gen_or_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], tmp);
}
tcg_temp_free(tmp);
break;
case OT_WORD:
tmp = tcg_temp_new();
tcg_gen_ext16u_tl(tmp, t0);
tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
tcg_temp_free(tmp);
break;
default: /* XXX this shouldn't be reached; abort? */
case OT_LONG:
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a mov. */
tcg_gen_ext32u_tl(cpu_regs[reg], t0);
break;
#ifdef TARGET_X86_64
case OT_QUAD:
tcg_gen_mov_tl(cpu_regs[reg], t0);
break;
#endif
}
}
static inline void gen_op_mov_reg_T0(int ot, int reg)
{
gen_op_mov_reg_v(ot, reg, cpu_T[0]);
}
static inline void gen_op_mov_reg_T1(int ot, int reg)
{
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
}
static inline void gen_op_mov_reg_A0(int size, int reg)
{
TCGv tmp;
switch(size) {
case 0:
tmp = tcg_temp_new();
tcg_gen_ext16u_tl(tmp, cpu_A0);
tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], tmp);
tcg_temp_free(tmp);
break;
default: /* XXX this shouldn't be reached; abort? */
case 1:
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a mov. */
tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
break;
#ifdef TARGET_X86_64
case 2:
tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
break;
#endif
}
}
static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
{
switch(ot) {
case OT_BYTE:
if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
goto std_case;
} else {
tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
tcg_gen_ext8u_tl(t0, t0);
}
break;
default:
std_case:
tcg_gen_mov_tl(t0, cpu_regs[reg]);
break;
}
}
static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
{
gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
}
static inline void gen_op_movl_A0_reg(int reg)
{
tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
}
static inline void gen_op_addl_A0_im(int32_t val)
{
tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
#ifdef TARGET_X86_64
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
#endif
}
#ifdef TARGET_X86_64
static inline void gen_op_addq_A0_im(int64_t val)
{
tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
}
#endif
static void gen_add_A0_im(DisasContext *s, int val)
{
#ifdef TARGET_X86_64
if (CODE64(s))
gen_op_addq_A0_im(val);
else
#endif
gen_op_addl_A0_im(val);
}
static inline void gen_op_addl_T0_T1(void)
{
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
}
static inline void gen_op_jmp_T0(void)
{
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
}
static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
{
switch(size) {
case 0:
tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0);
tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0);
break;
case 1:
tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a nop. */
tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
break;
#ifdef TARGET_X86_64
case 2:
tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
break;
#endif
}
}
static inline void gen_op_add_reg_T0(int size, int reg)
{
switch(size) {
case 0:
tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
tcg_gen_ext16u_tl(cpu_tmp0, cpu_tmp0);
tcg_gen_andi_tl(cpu_regs[reg], cpu_regs[reg], ~0xffff);
tcg_gen_or_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0);
break;
case 1:
tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a nop. */
tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
break;
#ifdef TARGET_X86_64
case 2:
tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
break;
#endif
}
}
static inline void gen_op_set_cc_op(int32_t val)
{
tcg_gen_movi_i32(cpu_cc_op, val);
}
static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
{
tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
if (shift != 0)
tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
/* For x86_64, this sets the higher half of register to zero.
For i386, this is equivalent to a nop. */
tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
}
static inline void gen_op_movl_A0_seg(int reg)
{
tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
}
static inline void gen_op_addl_A0_seg(int reg)
{
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
#ifdef TARGET_X86_64
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
#endif
}
#ifdef TARGET_X86_64
static inline void gen_op_movq_A0_seg(int reg)
{
tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
}
static inline void gen_op_addq_A0_seg(int reg)
{
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
}
static inline void gen_op_movq_A0_reg(int reg)
{
tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
}
static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
{
tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
if (shift != 0)
tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
}
#endif
static inline void gen_op_lds_T0_A0(int idx)
{
int mem_index = (idx >> 2) - 1;
switch(idx & 3) {
case 0:
tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
break;
case 1:
tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
break;
default:
case 2:
tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
break;
}
}
static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
{
int mem_index = (idx >> 2) - 1;
switch(idx & 3) {
case 0:
tcg_gen_qemu_ld8u(t0, a0, mem_index);
break;
case 1:
tcg_gen_qemu_ld16u(t0, a0, mem_index);
break;
case 2:
tcg_gen_qemu_ld32u(t0, a0, mem_index);
break;
default:
case 3:
/* Should never happen on 32-bit targets. */
#ifdef TARGET_X86_64
tcg_gen_qemu_ld64(t0, a0, mem_index);
#endif
break;
}
}
/* XXX: always use ldu or lds */
static inline void gen_op_ld_T0_A0(int idx)
{
gen_op_ld_v(idx, cpu_T[0], cpu_A0);
}
static inline void gen_op_ldu_T0_A0(int idx)
{
gen_op_ld_v(idx, cpu_T[0], cpu_A0);
}
static inline void gen_op_ld_T1_A0(int idx)
{
gen_op_ld_v(idx, cpu_T[1], cpu_A0);
}
static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
{
int mem_index = (idx >> 2) - 1;
switch(idx & 3) {
case 0:
tcg_gen_qemu_st8(t0, a0, mem_index);
break;
case 1:
tcg_gen_qemu_st16(t0, a0, mem_index);
break;
case 2:
tcg_gen_qemu_st32(t0, a0, mem_index);
break;
default:
case 3:
/* Should never happen on 32-bit targets. */
#ifdef TARGET_X86_64
tcg_gen_qemu_st64(t0, a0, mem_index);
#endif
break;
}
}
static inline void gen_op_st_T0_A0(int idx)
{
gen_op_st_v(idx, cpu_T[0], cpu_A0);
}
static inline void gen_op_st_T1_A0(int idx)
{
gen_op_st_v(idx, cpu_T[1], cpu_A0);
}
static inline void gen_jmp_im(target_ulong pc)
{
tcg_gen_movi_tl(cpu_tmp0, pc);
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
}
static inline void gen_string_movl_A0_ESI(DisasContext *s)
{
int override;
override = s->override;
#ifdef TARGET_X86_64
if (s->aflag == 2) {
if (override >= 0) {
gen_op_movq_A0_seg(override);
gen_op_addq_A0_reg_sN(0, R_ESI);
} else {
gen_op_movq_A0_reg(R_ESI);
}
} else
#endif
if (s->aflag) {
/* 32 bit address */
if (s->addseg && override < 0)
override = R_DS;
if (override >= 0) {
gen_op_movl_A0_seg(override);
gen_op_addl_A0_reg_sN(0, R_ESI);
} else {
gen_op_movl_A0_reg(R_ESI);
}
} else {
/* 16 address, always override */
if (override < 0)
override = R_DS;
gen_op_movl_A0_reg(R_ESI);
gen_op_andl_A0_ffff();
gen_op_addl_A0_seg(override);
}
}
static inline void gen_string_movl_A0_EDI(DisasContext *s)
{
#ifdef TARGET_X86_64
if (s->aflag == 2) {
gen_op_movq_A0_reg(R_EDI);
} else
#endif
if (s->aflag) {
if (s->addseg) {
gen_op_movl_A0_seg(R_ES);
gen_op_addl_A0_reg_sN(0, R_EDI);
} else {
gen_op_movl_A0_reg(R_EDI);
}
} else {
gen_op_movl_A0_reg(R_EDI);
gen_op_andl_A0_ffff();
gen_op_addl_A0_seg(R_ES);
}
}
static inline void gen_op_movl_T0_Dshift(int ot)
{
tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
};
static void gen_extu(int ot, TCGv reg)
{
switch(ot) {
case OT_BYTE:
tcg_gen_ext8u_tl(reg, reg);
break;
case OT_WORD:
tcg_gen_ext16u_tl(reg, reg);
break;
case OT_LONG:
tcg_gen_ext32u_tl(reg, reg);
break;
default:
break;
}
}
static void gen_exts(int ot, TCGv reg)
{
switch(ot) {
case OT_BYTE:
tcg_gen_ext8s_tl(reg, reg);
break;
case OT_WORD:
tcg_gen_ext16s_tl(reg, reg);
break;
case OT_LONG:
tcg_gen_ext32s_tl(reg, reg);
break;
default:
break;
}
}
static inline void gen_op_jnz_ecx(int size, int label1)
{
tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
gen_extu(size + 1, cpu_tmp0);
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
}
static inline void gen_op_jz_ecx(int size, int label1)
{
tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
gen_extu(size + 1, cpu_tmp0);
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
}
static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
{
switch (ot) {
case 0: gen_helper_inb(v, n); break;
case 1: gen_helper_inw(v, n); break;
case 2: gen_helper_inl(v, n); break;
}
}
static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
{
switch (ot) {
case 0: gen_helper_outb(v, n); break;
case 1: gen_helper_outw(v, n); break;
case 2: gen_helper_outl(v, n); break;
}
}
static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
uint32_t svm_flags)
{
int state_saved;
target_ulong next_eip;
state_saved = 0;
if (s->pe && (s->cpl > s->iopl || s->vm86)) {
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(cur_eip);
state_saved = 1;
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
switch (ot) {
case 0: gen_helper_check_iob(cpu_tmp2_i32); break;
case 1: gen_helper_check_iow(cpu_tmp2_i32); break;
case 2: gen_helper_check_iol(cpu_tmp2_i32); break;
}
}
if(s->flags & HF_SVMI_MASK) {
if (!state_saved) {
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(cur_eip);
state_saved = 1;
}
svm_flags |= (1 << (4 + ot));
next_eip = s->pc - s->cs_base;
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags),
tcg_const_i32(next_eip - cur_eip));
}
}
static inline void gen_movs(DisasContext *s, int ot)
{
gen_string_movl_A0_ESI(s);
gen_op_ld_T0_A0(ot + s->mem_index);
gen_string_movl_A0_EDI(s);
gen_op_st_T0_A0(ot + s->mem_index);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
gen_op_add_reg_T0(s->aflag, R_EDI);
}
static inline void gen_update_cc_op(DisasContext *s)
{
if (s->cc_op != CC_OP_DYNAMIC) {
gen_op_set_cc_op(s->cc_op);
s->cc_op = CC_OP_DYNAMIC;
}
}
static void gen_op_update1_cc(void)
{
tcg_gen_discard_tl(cpu_cc_src);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
}
static void gen_op_update2_cc(void)
{
tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
}
static inline void gen_op_cmpl_T0_T1_cc(void)
{
tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
}
static inline void gen_op_testl_T0_T1_cc(void)
{
tcg_gen_discard_tl(cpu_cc_src);
tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
}
static void gen_op_update_neg_cc(void)
{
tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
}
/* compute eflags.C to reg */
static void gen_compute_eflags_c(TCGv reg)
{
gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op);
tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
}
/* compute all eflags to cc_src */
static void gen_compute_eflags(TCGv reg)
{
gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op);
tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
}
static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
{
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
switch(jcc_op) {
case JCC_O:
gen_compute_eflags(cpu_T[0]);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
break;
case JCC_B:
gen_compute_eflags_c(cpu_T[0]);
break;
case JCC_Z:
gen_compute_eflags(cpu_T[0]);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
break;
case JCC_BE:
gen_compute_eflags(cpu_tmp0);
tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
break;
case JCC_S:
gen_compute_eflags(cpu_T[0]);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
break;
case JCC_P:
gen_compute_eflags(cpu_T[0]);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
break;
case JCC_L:
gen_compute_eflags(cpu_tmp0);
tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
break;
default:
case JCC_LE:
gen_compute_eflags(cpu_tmp0);
tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
break;
}
}
/* return true if setcc_slow is not needed (WARNING: must be kept in
sync with gen_jcc1) */
static int is_fast_jcc_case(DisasContext *s, int b)
{
int jcc_op;
jcc_op = (b >> 1) & 7;
switch(s->cc_op) {
/* we optimize the cmp/jcc case */
case CC_OP_SUBB:
case CC_OP_SUBW:
case CC_OP_SUBL:
case CC_OP_SUBQ:
if (jcc_op == JCC_O || jcc_op == JCC_P)
goto slow_jcc;
break;
/* some jumps are easy to compute */
case CC_OP_ADDB:
case CC_OP_ADDW:
case CC_OP_ADDL:
case CC_OP_ADDQ:
case CC_OP_LOGICB:
case CC_OP_LOGICW:
case CC_OP_LOGICL:
case CC_OP_LOGICQ:
case CC_OP_INCB:
case CC_OP_INCW:
case CC_OP_INCL:
case CC_OP_INCQ:
case CC_OP_DECB:
case CC_OP_DECW:
case CC_OP_DECL:
case CC_OP_DECQ:
case CC_OP_SHLB:
case CC_OP_SHLW:
case CC_OP_SHLL:
case CC_OP_SHLQ:
if (jcc_op != JCC_Z && jcc_op != JCC_S)
goto slow_jcc;
break;
default:
slow_jcc:
return 0;
}
return 1;
}
/* generate a conditional jump to label 'l1' according to jump opcode
value 'b'. In the fast case, T0 is guaranted not to be used. */
static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
{
int inv, jcc_op, size, cond;
TCGv t0;
inv = b & 1;
jcc_op = (b >> 1) & 7;
switch(cc_op) {
/* we optimize the cmp/jcc case */
case CC_OP_SUBB:
case CC_OP_SUBW:
case CC_OP_SUBL:
case CC_OP_SUBQ:
size = cc_op - CC_OP_SUBB;
switch(jcc_op) {
case JCC_Z:
fast_jcc_z:
switch(size) {
case 0:
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
t0 = cpu_tmp0;
break;
case 1:
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
t0 = cpu_tmp0;
break;
#ifdef TARGET_X86_64
case 2:
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
t0 = cpu_tmp0;
break;
#endif
default:
t0 = cpu_cc_dst;
break;
}
tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
break;
case JCC_S:
fast_jcc_s:
switch(size) {
case 0:
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
0, l1);
break;
case 1:
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
0, l1);
break;
#ifdef TARGET_X86_64
case 2:
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,