This project is a transcription of the PDP-8/I circuit as given in volume II of the maintenance manual into the Antares digital logic simulator.
Clone the repository, open the antares-workspace directory as a workspace in Antares, then open the PDP-8/I project inside that workspace.
There are some example programs in the programs directory that can be imported into the emulated core memory.
Antares allows connecting a virtual oscilloscope to any signal, simply create a global tunnel with the original name of the signal and connect a scope in real-time mode as shown below.
Short introduction coming soon.
| CPU Extension | Description | Implemented |
|---|---|---|
| MC8/I | Memory Extension | ✅ |
| KE8/I | Arithmetic Extension | ✅ |
| KT8/I | Time Sharing Option | ✅ |
| KP8/I | Power Failure Option | ❌ |
| DL8/I | Serial Line Multiplexer | ❌ |
| MP8/I | Memory Parity | ❌ |
| KW8/I | Real Time Clock | ❌ |
The implementation passes the following MAINDECs diagnostic programs:
| Program | What's tested | Pass |
|---|---|---|
| maindec-8i-d01c | AND, TAD, OPR | ✅ |
| maindec-8i-d02b | DCA, auto-indexing, indirect addressing, interrupts | ✅ |
| maindec-08-d04b | JMP | ✅ |
| maindec-08-d05b | JMS | ✅ |
| maindec-08-d07b | ISZ | ✅ |
| maindec-08-d0aa | EAE without DVI, MUY | ✅ |
| maindec-08-d0ba | DVI, MUY | ✅ |
| maindec-08-d1gd | Memory Extension | ✅ |
I'm interested in the PDP-8/I because Oscar Vermeulen built an awesome replica of the front panel. But that replica uses a Raspberry Pi running SIMH, an emulator whose PDP-8 implementation is mainly based on anecdotal behavior rather than the real schematic. Also, SIMH emulates a PDP-8/E instead of an 8/I, so the behavior doesn't quite match what the front panel suggests. For example, single stepping doesn't work and some lamps are never turned on.
There are also some FPGA implementations of the 8/I, but they are based on observations and anecdotes as well. Since the full original schematics of the entire machine are given its maintenance manual and even explained in volume I of that manual, I had the idea to create an FPGA implementation of the original circuit rather than another anecdotal emulator.
That project is called SoCDP-8 and nearly finished. There's also a browser version of it on pdp8.app.
However, converting an asynchronous circuit that uses delay lines and core memory to a modern FPGA with synchronized logic can introduce subtle errors, even more so in the software conversion of that logic that runs in the browser version.
This inspired the idea to transcribe the original circuit without any changes into a digital logic simulator where corner cases can be studied and signals can be compared to the FPGA version. It could also help owners of a real 8/I to diagnose malfunctions in their system since the behavior should exactly match that of an original machine.
That is, to go from something like this original schematic
to this schematic in Antares
