[ARCv3] HS5x - absence of support for atomic llockd/scondd instructions

[pavelvkozlov]

According to the PRM for 32-bit ARCv3 processors (ARC HS5x) atomic instructions llockd and scondd for 64-bit data are available and it would be great to have a support in the tools.
We need this to add optimized set of atomic64_* functions to the Linux kernel for the HS5x.

Now, code like the following returns assembler error:

  __asm__ __volatile__ (
  	"1:\n"
  	"llockd %0, %1\n"
  	"add.f %L0, %L0, %L2\n"
  	"adc %H0, %H0, %H2\n"
  	"scondd %0, %1\n"
  	"bnz 1b\n"
  	: "=&r"(a64), "+ATOMC"(counter)
  	: "ir"(b64)
  	:"cc", "memory");
...
Error: unknown opcode 'llockd' 
Error: unknown opcode 'scondd'

[abrodkin]

Temporary work-around for the Linux kernel for ARC HS58 is available here: foss-for-synopsys-dwc-arc-processors/linux@71455c6.

[claziss]

Fix in foss-for-synopsys-dwc-arc-processors/binutils-gdb@7ae0445

[abrodkin]

Fix back-ported to arc-2022.09 - foss-for-synopsys-dwc-arc-processors/binutils-gdb@c89aa1c.
@pavelvkozlov once new engineering build is out with that fix, please re-try and close this issue.

[claziss]

@BrunoASMauricio Please implement them in QEMU

[abrodkin]

Is a part of arc-2022.09-rc2 available here https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/tag/arc-2022.09-rc2