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ieee802154_dw1000.c
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/*
* Copyright (c) 2020 PHYTEC Messtechnik GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dw1000, LOG_LEVEL_INF);
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/debug/stack.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/net/net_if.h>
#include <zephyr/net/net_pkt.h>
#include <zephyr/sys/byteorder.h>
#include <string.h>
#include <zephyr/random/random.h>
#include <zephyr/debug/stack.h>
#include <math.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/net/ieee802154_radio.h>
#include "ieee802154_dw1000_regs.h"
#define DT_DRV_COMPAT decawave_dw1000
#define DWT_FCS_LENGTH 2U
#define DWT_SPI_CSWAKEUP_FREQ 500000U
#define DWT_SPI_SLOW_FREQ 2000000U
#define DWT_SPI_TRANS_MAX_HDR_LEN 3
#define DWT_SPI_TRANS_REG_MAX_RANGE 0x3F
#define DWT_SPI_TRANS_SHORT_MAX_OFFSET 0x7F
#define DWT_SPI_TRANS_WRITE_OP BIT(7)
#define DWT_SPI_TRANS_SUB_ADDR BIT(6)
#define DWT_SPI_TRANS_EXTEND_ADDR BIT(7)
#define DWT_TS_TIME_UNITS_FS 15650U /* DWT_TIME_UNITS in fs */
#define DW1000_TX_ANT_DLY 16450
#define DW1000_RX_ANT_DLY 16450
/* SHR Symbol Duration in ns */
#define UWB_PHY_TPSYM_PRF64 IEEE802154_PHY_HRP_UWB_PRF64_TPSYM_SYMBOL_PERIOD_NS
#define UWB_PHY_TPSYM_PRF16 IEEE802154_PHY_HRP_UWB_PRF16_TPSYM_SYMBOL_PERIOD_NS
#define UWB_PHY_NUMOF_SYM_SHR_SFD 8
/* PHR Symbol Duration Tdsym in ns */
#define UWB_PHY_TDSYM_PHR_110K 8205.13
#define UWB_PHY_TDSYM_PHR_850K 1025.64
#define UWB_PHY_TDSYM_PHR_6M8 1025.64
#define UWB_PHY_NUMOF_SYM_PHR 18
/* Data Symbol Duration Tdsym in ns */
#define UWB_PHY_TDSYM_DATA_110K 8205.13
#define UWB_PHY_TDSYM_DATA_850K 1025.64
#define UWB_PHY_TDSYM_DATA_6M8 128.21
#define DWT_WORK_QUEUE_STACK_SIZE 512
static struct k_work_q dwt_work_queue;
static K_KERNEL_STACK_DEFINE(dwt_work_queue_stack,
DWT_WORK_QUEUE_STACK_SIZE);
struct dwt_phy_config {
uint8_t channel; /* Channel 1, 2, 3, 4, 5, 7 */
uint8_t dr; /* Data rate DWT_BR_110K, DWT_BR_850K, DWT_BR_6M8 */
uint8_t prf; /* PRF DWT_PRF_16M or DWT_PRF_64M */
uint8_t rx_pac_l; /* DWT_PAC8..DWT_PAC64 */
uint8_t rx_shr_code; /* RX SHR preamble code */
uint8_t rx_ns_sfd; /* non-standard SFD */
uint16_t rx_sfd_to; /* SFD timeout value (in symbols)
* (tx_shr_nsync + 1 + SFD_length - rx_pac_l)
*/
uint8_t tx_shr_code; /* TX SHR preamble code */
uint32_t tx_shr_nsync; /* PLEN index, e.g. DWT_PLEN_64 */
float t_shr;
float t_phr;
float t_dsym;
};
struct dwt_hi_cfg {
struct spi_dt_spec bus;
struct gpio_dt_spec irq_gpio;
struct gpio_dt_spec rst_gpio;
};
#define DWT_STATE_TX 0
#define DWT_STATE_CCA 1
#define DWT_STATE_RX_DEF_ON 2
struct dwt_context {
const struct device *dev;
struct net_if *iface;
const struct spi_config *spi_cfg;
struct spi_config spi_cfg_slow;
struct gpio_callback gpio_cb;
struct k_sem dev_lock;
struct k_sem phy_sem;
struct k_work irq_cb_work;
struct k_thread thread;
struct dwt_phy_config rf_cfg;
atomic_t state;
bool cca_busy;
uint16_t sleep_mode;
uint8_t mac_addr[8];
};
static const struct dwt_hi_cfg dw1000_0_config = {
.bus = SPI_DT_SPEC_INST_GET(0, SPI_WORD_SET(8), 0),
.irq_gpio = GPIO_DT_SPEC_INST_GET(0, int_gpios),
.rst_gpio = GPIO_DT_SPEC_INST_GET(0, reset_gpios),
};
static struct dwt_context dwt_0_context = {
.dev_lock = Z_SEM_INITIALIZER(dwt_0_context.dev_lock, 1, 1),
.phy_sem = Z_SEM_INITIALIZER(dwt_0_context.phy_sem, 0, 1),
.rf_cfg = {
.channel = 5,
.dr = DWT_BR_6M8,
.prf = DWT_PRF_64M,
.rx_pac_l = DWT_PAC8,
.rx_shr_code = 10,
.rx_ns_sfd = 0,
.rx_sfd_to = (129 + 8 - 8),
.tx_shr_code = 10,
.tx_shr_nsync = DWT_PLEN_128,
},
};
/* This struct is used to read all additional RX frame info at one push */
struct dwt_rx_info_regs {
uint8_t rx_fqual[DWT_RX_FQUAL_LEN];
uint8_t rx_ttcki[DWT_RX_TTCKI_LEN];
uint8_t rx_ttcko[DWT_RX_TTCKO_LEN];
/* RX_TIME without RX_RAWST */
uint8_t rx_time[DWT_RX_TIME_FP_RAWST_OFFSET];
} _packed;
static int dwt_configure_rf_phy(const struct device *dev);
static int dwt_spi_read(const struct device *dev,
uint16_t hdr_len, const uint8_t *hdr_buf,
uint32_t data_len, uint8_t *data)
{
struct dwt_context *ctx = dev->data;
const struct dwt_hi_cfg *hi_cfg = dev->config;
const struct spi_buf tx_buf = {
.buf = (uint8_t *)hdr_buf,
.len = hdr_len
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1
};
struct spi_buf rx_buf[2] = {
{
.buf = NULL,
.len = hdr_len,
},
{
.buf = (uint8_t *)data,
.len = data_len,
},
};
const struct spi_buf_set rx = {
.buffers = rx_buf,
.count = 2
};
LOG_DBG("spi read, header length %u, data length %u",
(uint16_t)hdr_len, (uint32_t)data_len);
LOG_HEXDUMP_DBG(hdr_buf, (uint16_t)hdr_len, "rd: header");
if (spi_transceive(hi_cfg->bus.bus, ctx->spi_cfg, &tx, &rx)) {
LOG_ERR("SPI transfer failed");
return -EIO;
}
LOG_HEXDUMP_DBG(data, (uint32_t)data_len, "rd: data");
return 0;
}
static int dwt_spi_write(const struct device *dev,
uint16_t hdr_len, const uint8_t *hdr_buf,
uint32_t data_len, const uint8_t *data)
{
struct dwt_context *ctx = dev->data;
const struct dwt_hi_cfg *hi_cfg = dev->config;
struct spi_buf buf[2] = {
{.buf = (uint8_t *)hdr_buf, .len = hdr_len},
{.buf = (uint8_t *)data, .len = data_len}
};
struct spi_buf_set buf_set = {.buffers = buf, .count = 2};
LOG_DBG("spi write, header length %u, data length %u",
(uint16_t)hdr_len, (uint32_t)data_len);
LOG_HEXDUMP_DBG(hdr_buf, (uint16_t)hdr_len, "wr: header");
LOG_HEXDUMP_DBG(data, (uint32_t)data_len, "wr: data");
if (spi_write(hi_cfg->bus.bus, ctx->spi_cfg, &buf_set)) {
LOG_ERR("SPI read failed");
return -EIO;
}
return 0;
}
/* See 2.2.1.2 Transaction formats of the SPI interface */
static int dwt_spi_transfer(const struct device *dev,
uint8_t reg, uint16_t offset,
size_t buf_len, uint8_t *buf, bool write)
{
uint8_t hdr[DWT_SPI_TRANS_MAX_HDR_LEN] = {0};
size_t hdr_len = 0;
hdr[0] = reg & DWT_SPI_TRANS_REG_MAX_RANGE;
hdr_len += 1;
if (offset != 0) {
hdr[0] |= DWT_SPI_TRANS_SUB_ADDR;
hdr[1] = (uint8_t)offset & DWT_SPI_TRANS_SHORT_MAX_OFFSET;
hdr_len += 1;
if (offset > DWT_SPI_TRANS_SHORT_MAX_OFFSET) {
hdr[1] |= DWT_SPI_TRANS_EXTEND_ADDR;
hdr[2] = (uint8_t)(offset >> 7);
hdr_len += 1;
}
}
if (write) {
hdr[0] |= DWT_SPI_TRANS_WRITE_OP;
return dwt_spi_write(dev, hdr_len, hdr, buf_len, buf);
} else {
return dwt_spi_read(dev, hdr_len, hdr, buf_len, buf);
}
}
static int dwt_register_read(const struct device *dev,
uint8_t reg, uint16_t offset, size_t buf_len, uint8_t *buf)
{
return dwt_spi_transfer(dev, reg, offset, buf_len, buf, false);
}
static int dwt_register_write(const struct device *dev,
uint8_t reg, uint16_t offset, size_t buf_len, uint8_t *buf)
{
return dwt_spi_transfer(dev, reg, offset, buf_len, buf, true);
}
static inline uint32_t dwt_reg_read_u32(const struct device *dev,
uint8_t reg, uint16_t offset)
{
uint8_t buf[sizeof(uint32_t)];
dwt_spi_transfer(dev, reg, offset, sizeof(buf), buf, false);
return sys_get_le32(buf);
}
static inline uint8_t dwt_reg_read_u8(const struct device *dev,
uint8_t reg, uint16_t offset)
{
uint8_t buf;
dwt_spi_transfer(dev, reg, offset, sizeof(buf), &buf, false);
return buf;
}
static inline void dwt_reg_write_u32(const struct device *dev,
uint8_t reg, uint16_t offset, uint32_t val)
{
uint8_t buf[sizeof(uint32_t)];
sys_put_le32(val, buf);
dwt_spi_transfer(dev, reg, offset, sizeof(buf), buf, true);
}
static inline void dwt_reg_write_u16(const struct device *dev,
uint8_t reg, uint16_t offset, uint16_t val)
{
uint8_t buf[sizeof(uint16_t)];
sys_put_le16(val, buf);
dwt_spi_transfer(dev, reg, offset, sizeof(buf), buf, true);
}
static inline void dwt_reg_write_u8(const struct device *dev,
uint8_t reg, uint16_t offset, uint8_t val)
{
dwt_spi_transfer(dev, reg, offset, sizeof(uint8_t), &val, true);
}
static ALWAYS_INLINE void dwt_setup_int(const struct device *dev,
bool enable)
{
const struct dwt_hi_cfg *hi_cfg = dev->config;
unsigned int flags = enable
? GPIO_INT_EDGE_TO_ACTIVE
: GPIO_INT_DISABLE;
gpio_pin_interrupt_configure_dt(&hi_cfg->irq_gpio, flags);
}
static void dwt_reset_rfrx(const struct device *dev)
{
/*
* Apply a receiver-only soft reset,
* see SOFTRESET field description in DW1000 User Manual.
*/
dwt_reg_write_u8(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_SOFTRESET_OFFSET,
DWT_PMSC_CTRL0_RESET_RX);
dwt_reg_write_u8(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_SOFTRESET_OFFSET,
DWT_PMSC_CTRL0_RESET_CLEAR);
}
static void dwt_disable_txrx(const struct device *dev)
{
dwt_setup_int(dev, false);
dwt_reg_write_u8(dev, DWT_SYS_CTRL_ID, DWT_SYS_CTRL_OFFSET,
DWT_SYS_CTRL_TRXOFF);
dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, DWT_SYS_STATUS_OFFSET,
(DWT_SYS_STATUS_ALL_RX_GOOD |
DWT_SYS_STATUS_ALL_RX_TO |
DWT_SYS_STATUS_ALL_RX_ERR |
DWT_SYS_STATUS_ALL_TX));
dwt_setup_int(dev, true);
}
/* timeout time in units of 1.026 microseconds */
static int dwt_enable_rx(const struct device *dev, uint16_t timeout)
{
uint32_t sys_cfg;
uint16_t sys_ctrl = DWT_SYS_CTRL_RXENAB;
sys_cfg = dwt_reg_read_u32(dev, DWT_SYS_CFG_ID, 0);
if (timeout != 0) {
dwt_reg_write_u16(dev, DWT_RX_FWTO_ID, DWT_RX_FWTO_OFFSET,
timeout);
sys_cfg |= DWT_SYS_CFG_RXWTOE;
} else {
sys_cfg &= ~DWT_SYS_CFG_RXWTOE;
}
dwt_reg_write_u32(dev, DWT_SYS_CFG_ID, 0, sys_cfg);
dwt_reg_write_u16(dev, DWT_SYS_CTRL_ID, DWT_SYS_CTRL_OFFSET, sys_ctrl);
return 0;
}
static inline void dwt_irq_handle_rx_cca(const struct device *dev)
{
struct dwt_context *ctx = dev->data;
k_sem_give(&ctx->phy_sem);
ctx->cca_busy = true;
/* Clear all RX event bits */
dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0,
DWT_SYS_STATUS_ALL_RX_GOOD);
}
static inline void dwt_irq_handle_rx(const struct device *dev, uint32_t sys_stat)
{
struct dwt_context *ctx = dev->data;
struct net_pkt *pkt = NULL;
struct dwt_rx_info_regs rx_inf_reg;
float a_const;
uint32_t rx_finfo;
uint32_t ttcki;
uint32_t rx_pacc;
uint32_t cir_pwr;
uint32_t flags_to_clear;
int32_t ttcko;
uint16_t pkt_len;
uint8_t *fctrl;
int8_t rx_level = INT8_MIN;
LOG_DBG("RX OK event, SYS_STATUS 0x%08x", sys_stat);
flags_to_clear = sys_stat & DWT_SYS_STATUS_ALL_RX_GOOD;
rx_finfo = dwt_reg_read_u32(dev, DWT_RX_FINFO_ID, DWT_RX_FINFO_OFFSET);
pkt_len = rx_finfo & DWT_RX_FINFO_RXFLEN_MASK;
rx_pacc = (rx_finfo & DWT_RX_FINFO_RXPACC_MASK) >>
DWT_RX_FINFO_RXPACC_SHIFT;
if (!IS_ENABLED(CONFIG_IEEE802154_L2_PKT_INCL_FCS)) {
pkt_len -= DWT_FCS_LENGTH;
}
pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, pkt_len,
AF_UNSPEC, 0, K_NO_WAIT);
if (!pkt) {
LOG_ERR("No buf available");
goto rx_out_enable_rx;
}
dwt_register_read(dev, DWT_RX_BUFFER_ID, 0, pkt_len, pkt->buffer->data);
dwt_register_read(dev, DWT_RX_FQUAL_ID, 0, sizeof(rx_inf_reg),
(uint8_t *)&rx_inf_reg);
net_buf_add(pkt->buffer, pkt_len);
fctrl = pkt->buffer->data;
/*
* Get Ranging tracking offset and tracking interval
* for Crystal characterization
*/
ttcki = sys_get_le32(rx_inf_reg.rx_ttcki);
ttcko = sys_get_le32(rx_inf_reg.rx_ttcko) & DWT_RX_TTCKO_RXTOFS_MASK;
/* Tracking offset value is a 19-bit signed integer */
if (ttcko & BIT(18)) {
ttcko |= ~DWT_RX_TTCKO_RXTOFS_MASK;
}
/* TODO add:
* net_pkt_set_ieee802154_tcki(pkt, ttcki);
* net_pkt_set_ieee802154_tcko(pkt, ttcko);
*/
LOG_DBG("ttcko %d ttcki: 0x%08x", ttcko, ttcki);
if (IS_ENABLED(CONFIG_NET_PKT_TIMESTAMP)) {
uint8_t ts_buf[sizeof(uint64_t)] = {0};
uint64_t ts_nsec;
memcpy(ts_buf, rx_inf_reg.rx_time, DWT_RX_TIME_RX_STAMP_LEN);
ts_nsec = (sys_get_le64(ts_buf) * DWT_TS_TIME_UNITS_FS) / 1000000U;
net_pkt_set_timestamp_ns(pkt, ts_nsec);
}
/* See 4.7.2 Estimating the receive signal power */
cir_pwr = sys_get_le16(&rx_inf_reg.rx_fqual[6]);
if (ctx->rf_cfg.prf == DWT_PRF_16M) {
a_const = DWT_RX_SIG_PWR_A_CONST_PRF16;
} else {
a_const = DWT_RX_SIG_PWR_A_CONST_PRF64;
}
if (rx_pacc != 0) {
#if defined(CONFIG_NEWLIB_LIBC)
/* From 4.7.2 Estimating the receive signal power */
rx_level = 10.0 * log10f(cir_pwr * BIT(17) /
(rx_pacc * rx_pacc)) - a_const;
#endif
}
net_pkt_set_ieee802154_rssi_dbm(pkt, rx_level);
/*
* Workaround for AAT status bit issue,
* From 5.3.5 Host Notification in DW1000 User Manual:
* "Note: there is a situation that can result in the AAT bit being set
* for the current frame as a result of a previous frame that was
* received and rejected due to frame filtering."
*/
if ((sys_stat & DWT_SYS_STATUS_AAT) && ((fctrl[0] & 0x20) == 0)) {
flags_to_clear |= DWT_SYS_STATUS_AAT;
}
if (ieee802154_handle_ack(ctx->iface, pkt) == NET_OK) {
LOG_INF("ACK packet handled");
goto rx_out_unref_pkt;
}
/* LQI not implemented */
LOG_DBG("Caught a packet (%u) (RSSI: %d)", pkt_len, rx_level);
LOG_HEXDUMP_DBG(pkt->buffer->data, pkt_len, "RX buffer:");
if (net_recv_data(ctx->iface, pkt) == NET_OK) {
goto rx_out_enable_rx;
} else {
LOG_DBG("Packet dropped by NET stack");
}
rx_out_unref_pkt:
if (pkt) {
net_pkt_unref(pkt);
}
rx_out_enable_rx:
dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0, flags_to_clear);
LOG_DBG("Cleared SYS_STATUS flags 0x%08x", flags_to_clear);
if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
/*
* Re-enable reception but in contrast to dwt_enable_rx()
* without to read SYS_STATUS and set delayed option.
*/
dwt_reg_write_u16(dev, DWT_SYS_CTRL_ID, DWT_SYS_CTRL_OFFSET,
DWT_SYS_CTRL_RXENAB);
}
}
static void dwt_irq_handle_tx(const struct device *dev, uint32_t sys_stat)
{
struct dwt_context *ctx = dev->data;
/* Clear TX event bits */
dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0,
DWT_SYS_STATUS_ALL_TX);
LOG_DBG("TX confirmed event");
k_sem_give(&ctx->phy_sem);
}
static void dwt_irq_handle_rxto(const struct device *dev, uint32_t sys_stat)
{
struct dwt_context *ctx = dev->data;
/* Clear RX timeout event bits */
dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0,
DWT_SYS_STATUS_RXRFTO);
dwt_disable_txrx(dev);
/* Receiver reset necessary, see 4.1.6 RX Message timestamp */
dwt_reset_rfrx(dev);
LOG_DBG("RX timeout event");
if (atomic_test_bit(&ctx->state, DWT_STATE_CCA)) {
k_sem_give(&ctx->phy_sem);
ctx->cca_busy = false;
}
}
static void dwt_irq_handle_error(const struct device *dev, uint32_t sys_stat)
{
struct dwt_context *ctx = dev->data;
/* Clear RX error event bits */
dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0, DWT_SYS_STATUS_ALL_RX_ERR);
dwt_disable_txrx(dev);
/* Receiver reset necessary, see 4.1.6 RX Message timestamp */
dwt_reset_rfrx(dev);
LOG_INF("RX error event");
if (atomic_test_bit(&ctx->state, DWT_STATE_CCA)) {
k_sem_give(&ctx->phy_sem);
ctx->cca_busy = true;
return;
}
if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
dwt_enable_rx(dev, 0);
}
}
static void dwt_irq_work_handler(struct k_work *item)
{
struct dwt_context *ctx = CONTAINER_OF(item, struct dwt_context,
irq_cb_work);
const struct device *dev = ctx->dev;
uint32_t sys_stat;
k_sem_take(&ctx->dev_lock, K_FOREVER);
sys_stat = dwt_reg_read_u32(dev, DWT_SYS_STATUS_ID, 0);
if (sys_stat & DWT_SYS_STATUS_RXFCG) {
if (atomic_test_bit(&ctx->state, DWT_STATE_CCA)) {
dwt_irq_handle_rx_cca(dev);
} else {
dwt_irq_handle_rx(dev, sys_stat);
}
}
if (sys_stat & DWT_SYS_STATUS_TXFRS) {
dwt_irq_handle_tx(dev, sys_stat);
}
if (sys_stat & DWT_SYS_STATUS_ALL_RX_TO) {
dwt_irq_handle_rxto(dev, sys_stat);
}
if (sys_stat & DWT_SYS_STATUS_ALL_RX_ERR) {
dwt_irq_handle_error(dev, sys_stat);
}
k_sem_give(&ctx->dev_lock);
}
static void dwt_gpio_callback(const struct device *dev,
struct gpio_callback *cb, uint32_t pins)
{
struct dwt_context *ctx = CONTAINER_OF(cb, struct dwt_context, gpio_cb);
LOG_DBG("IRQ callback triggered %p", ctx);
k_work_submit_to_queue(&dwt_work_queue, &ctx->irq_cb_work);
}
static enum ieee802154_hw_caps dwt_get_capabilities(const struct device *dev)
{
/* TODO: Implement HW-supported AUTOACK + frame pending bit handling. */
return IEEE802154_HW_FCS | IEEE802154_HW_FILTER |
IEEE802154_HW_TXTIME;
}
static uint32_t dwt_get_pkt_duration_ns(struct dwt_context *ctx, uint8_t psdu_len)
{
struct dwt_phy_config *rf_cfg = &ctx->rf_cfg;
float t_psdu = rf_cfg->t_dsym * psdu_len * 8;
return (rf_cfg->t_shr + rf_cfg->t_phr + t_psdu);
}
static int dwt_cca(const struct device *dev)
{
struct dwt_context *ctx = dev->data;
uint32_t cca_dur = (dwt_get_pkt_duration_ns(ctx, 127) +
dwt_get_pkt_duration_ns(ctx, 5)) /
UWB_PHY_TDSYM_PHR_6M8;
if (atomic_test_and_set_bit(&ctx->state, DWT_STATE_CCA)) {
LOG_ERR("Transceiver busy");
return -EBUSY;
}
/* Perform CCA Mode 5 */
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_disable_txrx(dev);
LOG_DBG("CCA duration %u us", cca_dur);
dwt_enable_rx(dev, cca_dur);
k_sem_give(&ctx->dev_lock);
k_sem_take(&ctx->phy_sem, K_FOREVER);
LOG_DBG("CCA finished %p", ctx);
atomic_clear_bit(&ctx->state, DWT_STATE_CCA);
if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_enable_rx(dev, 0);
k_sem_give(&ctx->dev_lock);
}
return ctx->cca_busy ? -EBUSY : 0;
}
static int dwt_ed(const struct device *dev, uint16_t duration,
energy_scan_done_cb_t done_cb)
{
/* TODO: see description Sub-Register 0x23:02 – AGC_CTRL1 */
return -ENOTSUP;
}
static int dwt_set_channel(const struct device *dev, uint16_t channel)
{
struct dwt_context *ctx = dev->data;
struct dwt_phy_config *rf_cfg = &ctx->rf_cfg;
if (channel > 15) {
return -EINVAL;
}
if (channel == 0 || channel == 6 || channel > 7) {
return -ENOTSUP;
}
rf_cfg->channel = channel;
LOG_INF("Set channel %u", channel);
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_disable_txrx(dev);
dwt_configure_rf_phy(dev);
if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
dwt_enable_rx(dev, 0);
}
k_sem_give(&ctx->dev_lock);
return 0;
}
static int dwt_set_pan_id(const struct device *dev, uint16_t pan_id)
{
struct dwt_context *ctx = dev->data;
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_reg_write_u16(dev, DWT_PANADR_ID, DWT_PANADR_PAN_ID_OFFSET, pan_id);
k_sem_give(&ctx->dev_lock);
LOG_INF("Set PAN ID 0x%04x %p", pan_id, ctx);
return 0;
}
static int dwt_set_short_addr(const struct device *dev, uint16_t short_addr)
{
struct dwt_context *ctx = dev->data;
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_reg_write_u16(dev, DWT_PANADR_ID, DWT_PANADR_SHORT_ADDR_OFFSET,
short_addr);
k_sem_give(&ctx->dev_lock);
LOG_INF("Set short 0x%x %p", short_addr, ctx);
return 0;
}
static int dwt_set_ieee_addr(const struct device *dev,
const uint8_t *ieee_addr)
{
struct dwt_context *ctx = dev->data;
LOG_INF("IEEE address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x",
ieee_addr[7], ieee_addr[6], ieee_addr[5], ieee_addr[4],
ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0]);
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_register_write(dev, DWT_EUI_64_ID, DWT_EUI_64_OFFSET,
DWT_EUI_64_LEN, (uint8_t *)ieee_addr);
k_sem_give(&ctx->dev_lock);
return 0;
}
static int dwt_filter(const struct device *dev,
bool set,
enum ieee802154_filter_type type,
const struct ieee802154_filter *filter)
{
if (!set) {
return -ENOTSUP;
}
if (type == IEEE802154_FILTER_TYPE_IEEE_ADDR) {
return dwt_set_ieee_addr(dev, filter->ieee_addr);
} else if (type == IEEE802154_FILTER_TYPE_SHORT_ADDR) {
return dwt_set_short_addr(dev, filter->short_addr);
} else if (type == IEEE802154_FILTER_TYPE_PAN_ID) {
return dwt_set_pan_id(dev, filter->pan_id);
}
return -ENOTSUP;
}
static int dwt_set_power(const struct device *dev, int16_t dbm)
{
struct dwt_context *ctx = dev->data;
LOG_INF("set_txpower not supported %p", ctx);
return 0;
}
static int dwt_tx(const struct device *dev, enum ieee802154_tx_mode tx_mode,
struct net_pkt *pkt, struct net_buf *frag)
{
struct dwt_context *ctx = dev->data;
size_t len = frag->len;
uint32_t tx_time = 0;
uint64_t tmp_fs;
uint32_t tx_fctrl;
uint8_t sys_ctrl = DWT_SYS_CTRL_TXSTRT;
if (atomic_test_and_set_bit(&ctx->state, DWT_STATE_TX)) {
LOG_ERR("Transceiver busy");
return -EBUSY;
}
k_sem_reset(&ctx->phy_sem);
k_sem_take(&ctx->dev_lock, K_FOREVER);
switch (tx_mode) {
case IEEE802154_TX_MODE_DIRECT:
break;
case IEEE802154_TX_MODE_TXTIME:
/*
* tx_time is the high 32-bit of the 40-bit system
* time value at which to send the message.
*/
tmp_fs = net_pkt_timestamp_ns(pkt);
tmp_fs *= 1000U * 1000U;
tx_time = (tmp_fs / DWT_TS_TIME_UNITS_FS) >> 8;
sys_ctrl |= DWT_SYS_CTRL_TXDLYS;
/* DX_TIME is 40-bit register */
dwt_reg_write_u32(dev, DWT_DX_TIME_ID, 1, tx_time);
LOG_DBG("ntx hi32 %x", tx_time);
LOG_DBG("sys hi32 %x",
dwt_reg_read_u32(dev, DWT_SYS_TIME_ID, 1));
break;
default:
LOG_ERR("TX mode %d not supported", tx_mode);
goto error;
}
LOG_HEXDUMP_DBG(frag->data, len, "TX buffer:");
/*
* See "3 Message Transmission" in DW1000 User Manual for
* more details about transmission configuration.
*/
if (dwt_register_write(dev, DWT_TX_BUFFER_ID, 0, len, frag->data)) {
LOG_ERR("Failed to write TX data");
goto error;
}
tx_fctrl = dwt_reg_read_u32(dev, DWT_TX_FCTRL_ID, 0);
/* Clear TX buffer index offset, frame length, and length extension */
tx_fctrl &= ~(DWT_TX_FCTRL_TFLEN_MASK | DWT_TX_FCTRL_TFLE_MASK |
DWT_TX_FCTRL_TXBOFFS_MASK);
/* Set frame length and ranging flag */
tx_fctrl |= (len + DWT_FCS_LENGTH) & DWT_TX_FCTRL_TFLEN_MASK;
tx_fctrl |= DWT_TX_FCTRL_TR;
/* Update Transmit Frame Control register */
dwt_reg_write_u32(dev, DWT_TX_FCTRL_ID, 0, tx_fctrl);
dwt_disable_txrx(dev);
/* Begin transmission */
dwt_reg_write_u8(dev, DWT_SYS_CTRL_ID, DWT_SYS_CTRL_OFFSET, sys_ctrl);
if (sys_ctrl & DWT_SYS_CTRL_TXDLYS) {
uint32_t sys_stat = dwt_reg_read_u32(dev, DWT_SYS_STATUS_ID, 0);
if (sys_stat & DWT_SYS_STATUS_HPDWARN) {
LOG_WRN("Half Period Delay Warning");
}
}
k_sem_give(&ctx->dev_lock);
/* Wait for the TX confirmed event */
k_sem_take(&ctx->phy_sem, K_FOREVER);
if (IS_ENABLED(CONFIG_NET_PKT_TIMESTAMP)) {
uint8_t ts_buf[sizeof(uint64_t)] = {0};
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_register_read(dev, DWT_TX_TIME_ID,
DWT_TX_TIME_TX_STAMP_OFFSET,
DWT_TX_TIME_TX_STAMP_LEN,
ts_buf);
LOG_DBG("ts hi32 %x", (uint32_t)(sys_get_le64(ts_buf) >> 8));
LOG_DBG("sys hi32 %x",
dwt_reg_read_u32(dev, DWT_SYS_TIME_ID, 1));
k_sem_give(&ctx->dev_lock);
tmp_fs = sys_get_le64(ts_buf) * DWT_TS_TIME_UNITS_FS;
net_pkt_set_timestamp_ns(pkt, tmp_fs / 1000000U);
}
atomic_clear_bit(&ctx->state, DWT_STATE_TX);
if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_enable_rx(dev, 0);
k_sem_give(&ctx->dev_lock);
}
return 0;
error:
atomic_clear_bit(&ctx->state, DWT_STATE_TX);
k_sem_give(&ctx->dev_lock);
return -EIO;
}
static void dwt_set_frame_filter(const struct device *dev,
bool ff_enable, uint8_t ff_type)
{
uint32_t sys_cfg_ff = ff_enable ? DWT_SYS_CFG_FFE : 0;
sys_cfg_ff |= ff_type & DWT_SYS_CFG_FF_ALL_EN;
dwt_reg_write_u8(dev, DWT_SYS_CFG_ID, 0, (uint8_t)sys_cfg_ff);
}
static int dwt_configure(const struct device *dev,
enum ieee802154_config_type type,
const struct ieee802154_config *config)
{
struct dwt_context *ctx = dev->data;
LOG_DBG("API configure %p", ctx);
switch (type) {
case IEEE802154_CONFIG_AUTO_ACK_FPB:
LOG_DBG("IEEE802154_CONFIG_AUTO_ACK_FPB");
break;
case IEEE802154_CONFIG_ACK_FPB:
LOG_DBG("IEEE802154_CONFIG_ACK_FPB");
break;
case IEEE802154_CONFIG_PAN_COORDINATOR:
LOG_DBG("IEEE802154_CONFIG_PAN_COORDINATOR");
break;
case IEEE802154_CONFIG_PROMISCUOUS:
LOG_DBG("IEEE802154_CONFIG_PROMISCUOUS");
break;
case IEEE802154_CONFIG_EVENT_HANDLER:
LOG_DBG("IEEE802154_CONFIG_EVENT_HANDLER");
break;
default:
return -EINVAL;
}
return -ENOTSUP;
}
/* driver-allocated attribute memory - constant across all driver instances */
static const struct {
const struct ieee802154_phy_channel_range phy_channel_range[2];
const struct ieee802154_phy_supported_channels phy_supported_channels;
} drv_attr = {
.phy_channel_range = {
{ .from_channel = 1, .to_channel = 5 },
{ .from_channel = 7, .to_channel = 7 },
},
.phy_supported_channels = {
.ranges = drv_attr.phy_channel_range,
.num_ranges = 2U,
},
};
static int dwt_attr_get(const struct device *dev, enum ieee802154_attr attr,
struct ieee802154_attr_value *value)
{
if (ieee802154_attr_get_channel_page_and_range(
attr, IEEE802154_ATTR_PHY_CHANNEL_PAGE_FOUR_HRP_UWB,
&drv_attr.phy_supported_channels, value) == 0) {
return 0;
}
switch (attr) {
case IEEE802154_ATTR_PHY_HRP_UWB_SUPPORTED_PRFS: {
struct dwt_context *ctx = dev->data;
struct dwt_phy_config *rf_cfg = &ctx->rf_cfg;
value->phy_hrp_uwb_supported_nominal_prfs =
rf_cfg->prf == DWT_PRF_64M ? IEEE802154_PHY_HRP_UWB_NOMINAL_64_M
: IEEE802154_PHY_HRP_UWB_NOMINAL_16_M;
return 0;
}
default:
return -ENOENT;
}
}
/*
* Note, the DW_RESET pin should not be driven high externally.
*/
static int dwt_hw_reset(const struct device *dev)
{
const struct dwt_hi_cfg *hi_cfg = dev->config;
if (gpio_pin_configure_dt(&hi_cfg->rst_gpio, GPIO_OUTPUT_ACTIVE)) {
LOG_ERR("Failed to configure GPIO pin %u", hi_cfg->rst_gpio.pin);
return -EINVAL;
}
k_sleep(K_MSEC(1));
gpio_pin_set_dt(&hi_cfg->rst_gpio, 0);
k_sleep(K_MSEC(5));
if (gpio_pin_configure_dt(&hi_cfg->rst_gpio, GPIO_INPUT)) {
LOG_ERR("Failed to configure GPIO pin %u", hi_cfg->rst_gpio.pin);
return -EINVAL;
}
return 0;
}
/*
* SPI speed in INIT state or for wake-up sequence,
* see 2.3.2 Overview of main operational states
*/
static void dwt_set_spi_slow(const struct device *dev, const uint32_t freq)