forked from zephyrproject-rtos/zephyr
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathcan_stm32_bxcan.c
1167 lines (960 loc) · 30.7 KB
/
can_stm32_bxcan.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (c) 2018 Alexander Wachter
* Copyright (c) 2022 Martin Jäger <martin@libre.solar>
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Include soc.h prior to Zephyr CAN headers to pull in HAL fixups */
#include <soc.h>
#include <zephyr/drivers/can.h>
#include <zephyr/drivers/can/transceiver.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
LOG_MODULE_REGISTER(can_stm32, CONFIG_CAN_LOG_LEVEL);
#define CAN_INIT_TIMEOUT (10 * (sys_clock_hw_cycles_per_sec() / MSEC_PER_SEC))
#define DT_DRV_COMPAT st_stm32_bxcan
#define CAN_STM32_NUM_FILTER_BANKS (14)
#define CAN_STM32_MAX_FILTER_ID \
(CONFIG_CAN_MAX_EXT_ID_FILTER + CONFIG_CAN_MAX_STD_ID_FILTER * 2)
#define CAN_STM32_FIRX_STD_IDE_POS (3U)
#define CAN_STM32_FIRX_STD_RTR_POS (4U)
#define CAN_STM32_FIRX_STD_ID_POS (5U)
#define CAN_STM32_FIRX_EXT_IDE_POS (2U)
#define CAN_STM32_FIRX_EXT_RTR_POS (1U)
#define CAN_STM32_FIRX_EXT_STD_ID_POS (21U)
#define CAN_STM32_FIRX_EXT_EXT_ID_POS (3U)
#if (CONFIG_CAN_MAX_STD_ID_FILTER + CONFIG_CAN_MAX_EXT_ID_FILTER * 2) > \
(CAN_STM32_NUM_FILTER_BANKS * 2)
#error Number of configured filters exceeds available filter bank slots.
#endif
struct can_stm32_mailbox {
can_tx_callback_t tx_callback;
void *callback_arg;
};
struct can_stm32_data {
struct can_driver_data common;
struct k_mutex inst_mutex;
struct k_sem tx_int_sem;
struct can_stm32_mailbox mb0;
struct can_stm32_mailbox mb1;
struct can_stm32_mailbox mb2;
can_rx_callback_t rx_cb_std[CONFIG_CAN_MAX_STD_ID_FILTER];
can_rx_callback_t rx_cb_ext[CONFIG_CAN_MAX_EXT_ID_FILTER];
void *cb_arg_std[CONFIG_CAN_MAX_STD_ID_FILTER];
void *cb_arg_ext[CONFIG_CAN_MAX_EXT_ID_FILTER];
enum can_state state;
};
struct can_stm32_config {
const struct can_driver_config common;
CAN_TypeDef *can; /*!< CAN Registers*/
CAN_TypeDef *master_can; /*!< CAN Registers for shared filter */
struct stm32_pclken pclken;
void (*config_irq)(CAN_TypeDef *can);
const struct pinctrl_dev_config *pcfg;
};
/*
* Mutex to prevent simultaneous access to filter registers shared between CAN1
* and CAN2.
*/
static struct k_mutex filter_mutex;
static void can_stm32_signal_tx_complete(const struct device *dev, struct can_stm32_mailbox *mb,
int status)
{
can_tx_callback_t callback = mb->tx_callback;
if (callback != NULL) {
callback(dev, status, mb->callback_arg);
mb->tx_callback = NULL;
}
}
static void can_stm32_rx_fifo_pop(CAN_FIFOMailBox_TypeDef *mbox, struct can_frame *frame)
{
memset(frame, 0, sizeof(*frame));
if (mbox->RIR & CAN_RI0R_IDE) {
frame->id = mbox->RIR >> CAN_RI0R_EXID_Pos;
frame->flags |= CAN_FRAME_IDE;
} else {
frame->id = mbox->RIR >> CAN_RI0R_STID_Pos;
}
if ((mbox->RIR & CAN_RI0R_RTR) != 0) {
frame->flags |= CAN_FRAME_RTR;
} else {
frame->data_32[0] = mbox->RDLR;
frame->data_32[1] = mbox->RDHR;
}
frame->dlc = mbox->RDTR & (CAN_RDT0R_DLC >> CAN_RDT0R_DLC_Pos);
#ifdef CONFIG_CAN_RX_TIMESTAMP
frame->timestamp = ((mbox->RDTR & CAN_RDT0R_TIME) >> CAN_RDT0R_TIME_Pos);
#endif
}
static inline void can_stm32_rx_isr_handler(const struct device *dev)
{
struct can_stm32_data *data = dev->data;
const struct can_stm32_config *cfg = dev->config;
CAN_TypeDef *can = cfg->can;
CAN_FIFOMailBox_TypeDef *mbox;
int filter_id, index;
struct can_frame frame;
can_rx_callback_t callback = NULL;
void *cb_arg;
while (can->RF0R & CAN_RF0R_FMP0) {
mbox = &can->sFIFOMailBox[0];
filter_id = ((mbox->RDTR & CAN_RDT0R_FMI) >> CAN_RDT0R_FMI_Pos);
LOG_DBG("Message on filter_id %d", filter_id);
can_stm32_rx_fifo_pop(mbox, &frame);
if (filter_id < CONFIG_CAN_MAX_EXT_ID_FILTER) {
callback = data->rx_cb_ext[filter_id];
cb_arg = data->cb_arg_ext[filter_id];
} else if (filter_id < CAN_STM32_MAX_FILTER_ID) {
index = filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER;
callback = data->rx_cb_std[index];
cb_arg = data->cb_arg_std[index];
}
if (callback) {
callback(dev, &frame, cb_arg);
}
/* Release message */
can->RF0R |= CAN_RF0R_RFOM0;
}
if (can->RF0R & CAN_RF0R_FOVR0) {
LOG_ERR("RX FIFO Overflow");
CAN_STATS_RX_OVERRUN_INC(dev);
}
}
static int can_stm32_get_state(const struct device *dev, enum can_state *state,
struct can_bus_err_cnt *err_cnt)
{
const struct can_stm32_config *cfg = dev->config;
struct can_stm32_data *data = dev->data;
CAN_TypeDef *can = cfg->can;
if (state != NULL) {
if (!data->common.started) {
*state = CAN_STATE_STOPPED;
} else if (can->ESR & CAN_ESR_BOFF) {
*state = CAN_STATE_BUS_OFF;
} else if (can->ESR & CAN_ESR_EPVF) {
*state = CAN_STATE_ERROR_PASSIVE;
} else if (can->ESR & CAN_ESR_EWGF) {
*state = CAN_STATE_ERROR_WARNING;
} else {
*state = CAN_STATE_ERROR_ACTIVE;
}
}
if (err_cnt != NULL) {
err_cnt->tx_err_cnt =
((can->ESR & CAN_ESR_TEC) >> CAN_ESR_TEC_Pos);
err_cnt->rx_err_cnt =
((can->ESR & CAN_ESR_REC) >> CAN_ESR_REC_Pos);
}
return 0;
}
static inline void can_stm32_bus_state_change_isr(const struct device *dev)
{
struct can_stm32_data *data = dev->data;
struct can_bus_err_cnt err_cnt;
enum can_state state;
const can_state_change_callback_t cb = data->common.state_change_cb;
void *state_change_cb_data = data->common.state_change_cb_user_data;
#ifdef CONFIG_CAN_STATS
const struct can_stm32_config *cfg = dev->config;
CAN_TypeDef *can = cfg->can;
switch (can->ESR & CAN_ESR_LEC) {
case (CAN_ESR_LEC_0):
CAN_STATS_STUFF_ERROR_INC(dev);
break;
case (CAN_ESR_LEC_1):
CAN_STATS_FORM_ERROR_INC(dev);
break;
case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
CAN_STATS_ACK_ERROR_INC(dev);
break;
case (CAN_ESR_LEC_2):
CAN_STATS_BIT1_ERROR_INC(dev);
break;
case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
CAN_STATS_BIT0_ERROR_INC(dev);
break;
case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
CAN_STATS_CRC_ERROR_INC(dev);
break;
default:
break;
}
/* Clear last error code flag */
can->ESR |= CAN_ESR_LEC;
#endif /* CONFIG_CAN_STATS */
(void)can_stm32_get_state(dev, &state, &err_cnt);
if (state != data->state) {
data->state = state;
if (cb != NULL) {
cb(dev, state, err_cnt, state_change_cb_data);
}
}
}
static inline void can_stm32_tx_isr_handler(const struct device *dev)
{
struct can_stm32_data *data = dev->data;
const struct can_stm32_config *cfg = dev->config;
CAN_TypeDef *can = cfg->can;
uint32_t bus_off;
int status;
bus_off = can->ESR & CAN_ESR_BOFF;
if ((can->TSR & CAN_TSR_RQCP0) | bus_off) {
status = can->TSR & CAN_TSR_TXOK0 ? 0 :
can->TSR & CAN_TSR_TERR0 ? -EIO :
can->TSR & CAN_TSR_ALST0 ? -EBUSY :
bus_off ? -ENETUNREACH :
-EIO;
/* clear the request. */
can->TSR |= CAN_TSR_RQCP0;
can_stm32_signal_tx_complete(dev, &data->mb0, status);
}
if ((can->TSR & CAN_TSR_RQCP1) | bus_off) {
status = can->TSR & CAN_TSR_TXOK1 ? 0 :
can->TSR & CAN_TSR_TERR1 ? -EIO :
can->TSR & CAN_TSR_ALST1 ? -EBUSY :
bus_off ? -ENETUNREACH :
-EIO;
/* clear the request. */
can->TSR |= CAN_TSR_RQCP1;
can_stm32_signal_tx_complete(dev, &data->mb1, status);
}
if ((can->TSR & CAN_TSR_RQCP2) | bus_off) {
status = can->TSR & CAN_TSR_TXOK2 ? 0 :
can->TSR & CAN_TSR_TERR2 ? -EIO :
can->TSR & CAN_TSR_ALST2 ? -EBUSY :
bus_off ? -ENETUNREACH :
-EIO;
/* clear the request. */
can->TSR |= CAN_TSR_RQCP2;
can_stm32_signal_tx_complete(dev, &data->mb2, status);
}
if (can->TSR & CAN_TSR_TME) {
k_sem_give(&data->tx_int_sem);
}
}
#ifdef CONFIG_SOC_SERIES_STM32F0X
static void can_stm32_isr(const struct device *dev)
{
const struct can_stm32_config *cfg = dev->config;
CAN_TypeDef *can = cfg->can;
can_stm32_tx_isr_handler(dev);
can_stm32_rx_isr_handler(dev);
if (can->MSR & CAN_MSR_ERRI) {
can_stm32_bus_state_change_isr(dev);
can->MSR |= CAN_MSR_ERRI;
}
}
#else
static void can_stm32_rx_isr(const struct device *dev)
{
can_stm32_rx_isr_handler(dev);
}
static void can_stm32_tx_isr(const struct device *dev)
{
can_stm32_tx_isr_handler(dev);
}
static void can_stm32_state_change_isr(const struct device *dev)
{
const struct can_stm32_config *cfg = dev->config;
CAN_TypeDef *can = cfg->can;
/* Signal bus-off to waiting tx */
if (can->MSR & CAN_MSR_ERRI) {
can_stm32_tx_isr_handler(dev);
can_stm32_bus_state_change_isr(dev);
can->MSR |= CAN_MSR_ERRI;
}
}
#endif
static int can_stm32_enter_init_mode(CAN_TypeDef *can)
{
uint32_t start_time;
can->MCR |= CAN_MCR_INRQ;
start_time = k_cycle_get_32();
while ((can->MSR & CAN_MSR_INAK) == 0U) {
if (k_cycle_get_32() - start_time > CAN_INIT_TIMEOUT) {
can->MCR &= ~CAN_MCR_INRQ;
return -EAGAIN;
}
}
return 0;
}
static int can_stm32_leave_init_mode(CAN_TypeDef *can)
{
uint32_t start_time;
can->MCR &= ~CAN_MCR_INRQ;
start_time = k_cycle_get_32();
while ((can->MSR & CAN_MSR_INAK) != 0U) {
if (k_cycle_get_32() - start_time > CAN_INIT_TIMEOUT) {
return -EAGAIN;
}
}
return 0;
}
static int can_stm32_leave_sleep_mode(CAN_TypeDef *can)
{
uint32_t start_time;
can->MCR &= ~CAN_MCR_SLEEP;
start_time = k_cycle_get_32();
while ((can->MSR & CAN_MSR_SLAK) != 0) {
if (k_cycle_get_32() - start_time > CAN_INIT_TIMEOUT) {
return -EAGAIN;
}
}
return 0;
}
static int can_stm32_get_capabilities(const struct device *dev, can_mode_t *cap)
{
ARG_UNUSED(dev);
*cap = CAN_MODE_NORMAL | CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY | CAN_MODE_ONE_SHOT;
if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) {
*cap |= CAN_MODE_MANUAL_RECOVERY;
}
return 0;
}
static int can_stm32_start(const struct device *dev)
{
const struct can_stm32_config *cfg = dev->config;
struct can_stm32_data *data = dev->data;
CAN_TypeDef *can = cfg->can;
int ret = 0;
k_mutex_lock(&data->inst_mutex, K_FOREVER);
if (data->common.started) {
ret = -EALREADY;
goto unlock;
}
if (cfg->common.phy != NULL) {
ret = can_transceiver_enable(cfg->common.phy, data->common.mode);
if (ret != 0) {
LOG_ERR("failed to enable CAN transceiver (err %d)", ret);
goto unlock;
}
}
CAN_STATS_RESET(dev);
ret = can_stm32_leave_init_mode(can);
if (ret < 0) {
LOG_ERR("Failed to leave init mode");
if (cfg->common.phy != NULL) {
/* Attempt to disable the CAN transceiver in case of error */
(void)can_transceiver_disable(cfg->common.phy);
}
ret = -EIO;
goto unlock;
}
data->common.started = true;
unlock:
k_mutex_unlock(&data->inst_mutex);
return ret;
}
static int can_stm32_stop(const struct device *dev)
{
const struct can_stm32_config *cfg = dev->config;
struct can_stm32_data *data = dev->data;
CAN_TypeDef *can = cfg->can;
int ret = 0;
k_mutex_lock(&data->inst_mutex, K_FOREVER);
if (!data->common.started) {
ret = -EALREADY;
goto unlock;
}
ret = can_stm32_enter_init_mode(can);
if (ret < 0) {
LOG_ERR("Failed to enter init mode");
ret = -EIO;
goto unlock;
}
/* Abort any pending transmissions */
can_stm32_signal_tx_complete(dev, &data->mb0, -ENETDOWN);
can_stm32_signal_tx_complete(dev, &data->mb1, -ENETDOWN);
can_stm32_signal_tx_complete(dev, &data->mb2, -ENETDOWN);
can->TSR |= CAN_TSR_ABRQ2 | CAN_TSR_ABRQ1 | CAN_TSR_ABRQ0;
if (cfg->common.phy != NULL) {
ret = can_transceiver_disable(cfg->common.phy);
if (ret != 0) {
LOG_ERR("failed to enable CAN transceiver (err %d)", ret);
goto unlock;
}
}
data->common.started = false;
unlock:
k_mutex_unlock(&data->inst_mutex);
return ret;
}
static int can_stm32_set_mode(const struct device *dev, can_mode_t mode)
{
can_mode_t supported = CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY | CAN_MODE_ONE_SHOT;
const struct can_stm32_config *cfg = dev->config;
CAN_TypeDef *can = cfg->can;
struct can_stm32_data *data = dev->data;
LOG_DBG("Set mode %d", mode);
if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) {
supported |= CAN_MODE_MANUAL_RECOVERY;
}
if ((mode & ~(supported)) != 0) {
LOG_ERR("unsupported mode: 0x%08x", mode);
return -ENOTSUP;
}
if (data->common.started) {
return -EBUSY;
}
k_mutex_lock(&data->inst_mutex, K_FOREVER);
if ((mode & CAN_MODE_LOOPBACK) != 0) {
/* Loopback mode */
can->BTR |= CAN_BTR_LBKM;
} else {
can->BTR &= ~CAN_BTR_LBKM;
}
if ((mode & CAN_MODE_LISTENONLY) != 0) {
/* Silent mode */
can->BTR |= CAN_BTR_SILM;
} else {
can->BTR &= ~CAN_BTR_SILM;
}
if ((mode & CAN_MODE_ONE_SHOT) != 0) {
/* No automatic retransmission */
can->MCR |= CAN_MCR_NART;
} else {
can->MCR &= ~CAN_MCR_NART;
}
if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) {
if ((mode & CAN_MODE_MANUAL_RECOVERY) != 0) {
/* No automatic recovery from bus-off */
can->MCR &= ~CAN_MCR_ABOM;
} else {
can->MCR |= CAN_MCR_ABOM;
}
}
data->common.mode = mode;
k_mutex_unlock(&data->inst_mutex);
return 0;
}
static int can_stm32_set_timing(const struct device *dev,
const struct can_timing *timing)
{
const struct can_stm32_config *cfg = dev->config;
CAN_TypeDef *can = cfg->can;
struct can_stm32_data *data = dev->data;
k_mutex_lock(&data->inst_mutex, K_FOREVER);
if (data->common.started) {
k_mutex_unlock(&data->inst_mutex);
return -EBUSY;
}
can->BTR = (can->BTR & ~(CAN_BTR_SJW_Msk | CAN_BTR_BRP_Msk |
CAN_BTR_TS1_Msk | CAN_BTR_TS2_Msk)) |
(((timing->sjw - 1) << CAN_BTR_SJW_Pos) & CAN_BTR_SJW_Msk) |
(((timing->phase_seg1 - 1) << CAN_BTR_TS1_Pos) & CAN_BTR_TS1_Msk) |
(((timing->phase_seg2 - 1) << CAN_BTR_TS2_Pos) & CAN_BTR_TS2_Msk) |
(((timing->prescaler - 1) << CAN_BTR_BRP_Pos) & CAN_BTR_BRP_Msk);
k_mutex_unlock(&data->inst_mutex);
return 0;
}
static int can_stm32_get_core_clock(const struct device *dev, uint32_t *rate)
{
const struct can_stm32_config *cfg = dev->config;
const struct device *clock;
int ret;
clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
ret = clock_control_get_rate(clock,
(clock_control_subsys_t) &cfg->pclken,
rate);
if (ret != 0) {
LOG_ERR("Failed call clock_control_get_rate: return [%d]", ret);
return -EIO;
}
return 0;
}
static int can_stm32_get_max_filters(const struct device *dev, bool ide)
{
ARG_UNUSED(dev);
if (ide) {
return CONFIG_CAN_MAX_EXT_ID_FILTER;
} else {
return CONFIG_CAN_MAX_STD_ID_FILTER;
}
}
static int can_stm32_init(const struct device *dev)
{
const struct can_stm32_config *cfg = dev->config;
struct can_stm32_data *data = dev->data;
CAN_TypeDef *can = cfg->can;
struct can_timing timing = { 0 };
const struct device *clock;
uint32_t bank_offset;
int ret;
k_mutex_init(&filter_mutex);
k_mutex_init(&data->inst_mutex);
k_sem_init(&data->tx_int_sem, 0, 1);
if (cfg->common.phy != NULL) {
if (!device_is_ready(cfg->common.phy)) {
LOG_ERR("CAN transceiver not ready");
return -ENODEV;
}
}
clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
if (!device_is_ready(clock)) {
LOG_ERR("clock control device not ready");
return -ENODEV;
}
ret = clock_control_on(clock, (clock_control_subsys_t) &cfg->pclken);
if (ret != 0) {
LOG_ERR("HAL_CAN_Init clock control on failed: %d", ret);
return -EIO;
}
/* Configure dt provided device signals when available */
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("CAN pinctrl setup failed (%d)", ret);
return ret;
}
ret = can_stm32_enter_init_mode(can);
if (ret) {
LOG_ERR("Failed to enter init mode");
return ret;
}
ret = can_stm32_leave_sleep_mode(can);
if (ret) {
LOG_ERR("Failed to exit sleep mode");
return ret;
}
/* configure scale of filter banks < CONFIG_CAN_MAX_EXT_ID_FILTER for ext ids */
bank_offset = (cfg->can == cfg->master_can) ? 0 : CAN_STM32_NUM_FILTER_BANKS;
cfg->master_can->FMR |= CAN_FMR_FINIT;
cfg->master_can->FS1R |= ((1U << CONFIG_CAN_MAX_EXT_ID_FILTER) - 1) << bank_offset;
cfg->master_can->FMR &= ~CAN_FMR_FINIT;
can->MCR &= ~CAN_MCR_TTCM & ~CAN_MCR_ABOM & ~CAN_MCR_AWUM &
~CAN_MCR_NART & ~CAN_MCR_RFLM & ~CAN_MCR_TXFP;
#ifdef CONFIG_CAN_RX_TIMESTAMP
can->MCR |= CAN_MCR_TTCM;
#endif
/* Enable automatic bus-off recovery */
can->MCR |= CAN_MCR_ABOM;
ret = can_calc_timing(dev, &timing, cfg->common.bitrate,
cfg->common.sample_point);
if (ret == -EINVAL) {
LOG_ERR("Can't find timing for given param");
return -EIO;
}
LOG_DBG("Presc: %d, TS1: %d, TS2: %d",
timing.prescaler, timing.phase_seg1, timing.phase_seg2);
LOG_DBG("Sample-point err : %d", ret);
ret = can_set_timing(dev, &timing);
if (ret) {
return ret;
}
ret = can_stm32_set_mode(dev, CAN_MODE_NORMAL);
if (ret) {
return ret;
}
(void)can_stm32_get_state(dev, &data->state, NULL);
cfg->config_irq(can);
can->IER |= CAN_IER_TMEIE;
return 0;
}
static void can_stm32_set_state_change_callback(const struct device *dev,
can_state_change_callback_t cb,
void *user_data)
{
struct can_stm32_data *data = dev->data;
const struct can_stm32_config *cfg = dev->config;
CAN_TypeDef *can = cfg->can;
data->common.state_change_cb = cb;
data->common.state_change_cb_user_data = user_data;
if (cb == NULL) {
can->IER &= ~(CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE);
} else {
can->IER |= CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE;
}
}
#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
static int can_stm32_recover(const struct device *dev, k_timeout_t timeout)
{
const struct can_stm32_config *cfg = dev->config;
struct can_stm32_data *data = dev->data;
CAN_TypeDef *can = cfg->can;
int ret = -EAGAIN;
int64_t start_time;
if (!data->common.started) {
return -ENETDOWN;
}
if ((data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0U) {
return -ENOTSUP;
}
if (!(can->ESR & CAN_ESR_BOFF)) {
return 0;
}
if (k_mutex_lock(&data->inst_mutex, K_FOREVER)) {
return -EAGAIN;
}
ret = can_stm32_enter_init_mode(can);
if (ret) {
goto done;
}
can_stm32_leave_init_mode(can);
start_time = k_uptime_ticks();
while (can->ESR & CAN_ESR_BOFF) {
if (!K_TIMEOUT_EQ(timeout, K_FOREVER) &&
k_uptime_ticks() - start_time >= timeout.ticks) {
goto done;
}
}
ret = 0;
done:
k_mutex_unlock(&data->inst_mutex);
return ret;
}
#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
static int can_stm32_send(const struct device *dev, const struct can_frame *frame,
k_timeout_t timeout, can_tx_callback_t callback,
void *user_data)
{
const struct can_stm32_config *cfg = dev->config;
struct can_stm32_data *data = dev->data;
CAN_TypeDef *can = cfg->can;
uint32_t transmit_status_register = 0;
CAN_TxMailBox_TypeDef *mailbox = NULL;
struct can_stm32_mailbox *mb = NULL;
LOG_DBG("Sending %d bytes on %s. "
"Id: 0x%x, "
"ID type: %s, "
"Remote Frame: %s"
, frame->dlc, dev->name
, frame->id
, (frame->flags & CAN_FRAME_IDE) != 0 ? "extended" : "standard"
, (frame->flags & CAN_FRAME_RTR) != 0 ? "yes" : "no");
if (frame->dlc > CAN_MAX_DLC) {
LOG_ERR("DLC of %d exceeds maximum (%d)", frame->dlc, CAN_MAX_DLC);
return -EINVAL;
}
if ((frame->flags & ~(CAN_FRAME_IDE | CAN_FRAME_RTR)) != 0) {
LOG_ERR("unsupported CAN frame flags 0x%02x", frame->flags);
return -ENOTSUP;
}
if (!data->common.started) {
return -ENETDOWN;
}
if (can->ESR & CAN_ESR_BOFF) {
return -ENETUNREACH;
}
k_mutex_lock(&data->inst_mutex, K_FOREVER);
transmit_status_register = can->TSR;
while (!(transmit_status_register & CAN_TSR_TME)) {
k_mutex_unlock(&data->inst_mutex);
LOG_DBG("Transmit buffer full");
if (k_sem_take(&data->tx_int_sem, timeout)) {
return -EAGAIN;
}
k_mutex_lock(&data->inst_mutex, K_FOREVER);
transmit_status_register = can->TSR;
}
if (transmit_status_register & CAN_TSR_TME0) {
LOG_DBG("Using TX mailbox 0");
mailbox = &can->sTxMailBox[0];
mb = &(data->mb0);
} else if (transmit_status_register & CAN_TSR_TME1) {
LOG_DBG("Using TX mailbox 1");
mailbox = &can->sTxMailBox[1];
mb = &data->mb1;
} else if (transmit_status_register & CAN_TSR_TME2) {
LOG_DBG("Using TX mailbox 2");
mailbox = &can->sTxMailBox[2];
mb = &data->mb2;
}
mb->tx_callback = callback;
mb->callback_arg = user_data;
/* mailbox identifier register setup */
mailbox->TIR &= CAN_TI0R_TXRQ;
if ((frame->flags & CAN_FRAME_IDE) != 0) {
mailbox->TIR |= (frame->id << CAN_TI0R_EXID_Pos)
| CAN_TI0R_IDE;
} else {
mailbox->TIR |= (frame->id << CAN_TI0R_STID_Pos);
}
if ((frame->flags & CAN_FRAME_RTR) != 0) {
mailbox->TIR |= CAN_TI1R_RTR;
} else {
mailbox->TDLR = frame->data_32[0];
mailbox->TDHR = frame->data_32[1];
}
mailbox->TDTR = (mailbox->TDTR & ~CAN_TDT1R_DLC) |
((frame->dlc & 0xF) << CAN_TDT1R_DLC_Pos);
mailbox->TIR |= CAN_TI0R_TXRQ;
k_mutex_unlock(&data->inst_mutex);
return 0;
}
static void can_stm32_set_filter_bank(int filter_id, CAN_FilterRegister_TypeDef *filter_reg,
bool ide, uint32_t id, uint32_t mask)
{
if (ide) {
filter_reg->FR1 = id;
filter_reg->FR2 = mask;
} else {
if ((filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER) % 2 == 0) {
/* even std filter id: first 1/2 bank */
filter_reg->FR1 = id | (mask << 16);
} else {
/* uneven std filter id: first 1/2 bank */
filter_reg->FR2 = id | (mask << 16);
}
}
}
static inline uint32_t can_stm32_filter_to_std_mask(const struct can_filter *filter)
{
uint32_t rtr_mask = !IS_ENABLED(CONFIG_CAN_ACCEPT_RTR);
return (filter->mask << CAN_STM32_FIRX_STD_ID_POS) |
(rtr_mask << CAN_STM32_FIRX_STD_RTR_POS) |
(1U << CAN_STM32_FIRX_STD_IDE_POS);
}
static inline uint32_t can_stm32_filter_to_ext_mask(const struct can_filter *filter)
{
uint32_t rtr_mask = !IS_ENABLED(CONFIG_CAN_ACCEPT_RTR);
return (filter->mask << CAN_STM32_FIRX_EXT_EXT_ID_POS) |
(rtr_mask << CAN_STM32_FIRX_EXT_RTR_POS) |
(1U << CAN_STM32_FIRX_EXT_IDE_POS);
}
static inline uint32_t can_stm32_filter_to_std_id(const struct can_filter *filter)
{
return (filter->id << CAN_STM32_FIRX_STD_ID_POS);
}
static inline uint32_t can_stm32_filter_to_ext_id(const struct can_filter *filter)
{
return (filter->id << CAN_STM32_FIRX_EXT_EXT_ID_POS) |
(1U << CAN_STM32_FIRX_EXT_IDE_POS);
}
static inline int can_stm32_set_filter(const struct device *dev, const struct can_filter *filter)
{
const struct can_stm32_config *cfg = dev->config;
struct can_stm32_data *data = dev->data;
CAN_TypeDef *can = cfg->master_can;
uint32_t mask = 0U;
uint32_t id = 0U;
int filter_id = -ENOSPC;
int bank_offset = 0;
int bank_num;
if (cfg->can != cfg->master_can) {
/* CAN slave instance: start with offset */
bank_offset = CAN_STM32_NUM_FILTER_BANKS;
}
if ((filter->flags & CAN_FILTER_IDE) != 0) {
for (int i = 0; i < CONFIG_CAN_MAX_EXT_ID_FILTER; i++) {
if (data->rx_cb_ext[i] == NULL) {
id = can_stm32_filter_to_ext_id(filter);
mask = can_stm32_filter_to_ext_mask(filter);
filter_id = i;
bank_num = bank_offset + i;
break;
}
}
} else {
for (int i = 0; i < CONFIG_CAN_MAX_STD_ID_FILTER; i++) {
if (data->rx_cb_std[i] == NULL) {
id = can_stm32_filter_to_std_id(filter);
mask = can_stm32_filter_to_std_mask(filter);
filter_id = CONFIG_CAN_MAX_EXT_ID_FILTER + i;
bank_num = bank_offset + CONFIG_CAN_MAX_EXT_ID_FILTER + i / 2;
break;
}
}
}
if (filter_id != -ENOSPC) {
LOG_DBG("Adding filter_id %d, CAN ID: 0x%x, mask: 0x%x",
filter_id, filter->id, filter->mask);
/* set the filter init mode */
can->FMR |= CAN_FMR_FINIT;
can_stm32_set_filter_bank(filter_id, &can->sFilterRegister[bank_num],
(filter->flags & CAN_FILTER_IDE) != 0,
id, mask);
can->FA1R |= 1U << bank_num;
can->FMR &= ~(CAN_FMR_FINIT);
} else {
LOG_WRN("No free filter left");
}
return filter_id;
}
/*
* This driver uses masked mode for all filters (CAN_FM1R left at reset value
* 0x00) in order to simplify mapping between filter match index from the FIFOs
* and array index for the callbacks. All ext ID filters are stored in the
* banks below CONFIG_CAN_MAX_EXT_ID_FILTER, followed by the std ID filters,
* which consume only 1/2 bank per filter.
*
* The more complicated list mode must be implemented if someone requires more
* than 28 std ID or 14 ext ID filters.
*
* Currently, all filter banks are assigned to FIFO 0 and FIFO 1 is not used.
*/
static int can_stm32_add_rx_filter(const struct device *dev, can_rx_callback_t cb,
void *cb_arg, const struct can_filter *filter)
{
struct can_stm32_data *data = dev->data;
int filter_id;
if ((filter->flags & ~(CAN_FILTER_IDE)) != 0) {
LOG_ERR("unsupported CAN filter flags 0x%02x", filter->flags);
return -ENOTSUP;
}
k_mutex_lock(&filter_mutex, K_FOREVER);
k_mutex_lock(&data->inst_mutex, K_FOREVER);
filter_id = can_stm32_set_filter(dev, filter);
if (filter_id >= 0) {
if ((filter->flags & CAN_FILTER_IDE) != 0) {
data->rx_cb_ext[filter_id] = cb;
data->cb_arg_ext[filter_id] = cb_arg;
} else {
data->rx_cb_std[filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER] = cb;
data->cb_arg_std[filter_id - CONFIG_CAN_MAX_EXT_ID_FILTER] = cb_arg;
}
}
k_mutex_unlock(&data->inst_mutex);
k_mutex_unlock(&filter_mutex);
return filter_id;
}
static void can_stm32_remove_rx_filter(const struct device *dev, int filter_id)
{