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‎llvm/lib/Analysis/ScalarEvolution.cpp‎

Lines changed: 35 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15581,6 +15581,7 @@ void ScalarEvolution::LoopGuards::collectFromBlock(
1558115581
Predicate = CmpInst::getSwappedPredicate(Predicate);
1558215582
}
1558315583

15584+
unsigned StartSize = RewriteMap.size();
1558415585
// Check for a condition of the form (-C1 + X < C2). InstCombine will
1558515586
// create this form when combining two checks of the form (X u< C2 + C1) and
1558615587
// (X >=u C1).
@@ -15931,6 +15932,7 @@ void ScalarEvolution::LoopGuards::collectFromBlock(
1593115932
// Guards.RewriteMap. Conditions are processed in reverse order, so the
1593215933
// earliest conditions is processed first. This ensures the SCEVs with the
1593315934
// shortest dependency chains are constructed first.
15935+
SmallVector<std::tuple<CmpInst::Predicate, const SCEV *, const SCEV *>> ToProcess;
1593415936
for (auto [Term, EnterIfTrue] : reverse(Terms)) {
1593515937
SmallVector<Value *, 8> Worklist;
1593615938
SmallPtrSet<Value *, 8> Visited;
@@ -15945,7 +15947,9 @@ void ScalarEvolution::LoopGuards::collectFromBlock(
1594515947
EnterIfTrue ? Cmp->getPredicate() : Cmp->getInversePredicate();
1594615948
const auto *LHS = SE.getSCEV(Cmp->getOperand(0));
1594715949
const auto *RHS = SE.getSCEV(Cmp->getOperand(1));
15948-
CollectCondition(Predicate, LHS, RHS, Guards.RewriteMap);
15950+
// dbgs() << "\n" << *Cmp << "\n";
15951+
15952+
ToProcess.emplace_back(Predicate, LHS, RHS);
1594915953
continue;
1595015954
}
1595115955

@@ -15958,6 +15962,31 @@ void ScalarEvolution::LoopGuards::collectFromBlock(
1595815962
}
1595915963
}
1596015964

15965+
ToProcess = to_vector(ToProcess);
15966+
sort(ToProcess, [&](const auto &A, const auto &B) {
15967+
15968+
const SCEV *X, *Y;
15969+
const auto &[APred, ALHS , ARHS] = A;
15970+
const auto &[BPred, BLHS , BRHS] = B;
15971+
bool AIsDiv = SE.matchURem(ALHS, X, Y) && ARHS->isZero();
15972+
bool BIsDiv = SE.matchURem(BLHS, X, Y) && BRHS->isZero();
15973+
return BIsDiv < AIsDiv;
15974+
/*bool AConst = isa<SCEVConstant>(ARHS);*/
15975+
/*// bool AEq = !(APred == CmpInst::ICMP_EQ || APred == CmpInst::ICMP_NE);*/
15976+
/*bool BConst = isa<SCEVConstant>(BRHS);*/
15977+
/*//bool BEq = !(BPred == CmpInst::ICMP_EQ || BPred == CmpInst::ICMP_NE);*/
15978+
/*return std::tie(AConst) < std::tie(BConst);*/
15979+
});
15980+
for (const auto &[Predicate, LHS, RHS]: ToProcess) {
15981+
CollectCondition(Predicate, LHS, RHS, Guards.RewriteMap);
15982+
}
15983+
15984+
/* for (const auto &[Predicate, LHS, RHS]: reverse(ToProcess)) {*/
15985+
/*CollectCondition(Predicate, LHS, RHS, Guards.RewriteMap);*/
15986+
/*}*/
15987+
15988+
15989+
1596115990
// Let the rewriter preserve NUW/NSW flags if the unsigned/signed ranges of
1596215991
// the replacement expressions are contained in the ranges of the replaced
1596315992
// expressions.
@@ -16096,6 +16125,11 @@ const SCEV *ScalarEvolution::LoopGuards::rewrite(const SCEV *Expr) const {
1609616125
if (RewriteMap.empty())
1609716126
return Expr;
1609816127

16128+
/* dbgs() << "RWM\n";*/
16129+
/*for (const auto &[From, To] : RewriteMap) {*/
16130+
/*dbgs() << "From " << *From << " to " << *To << "\n";*/
16131+
16132+
/*}*/
1609916133
SCEVLoopGuardRewriter Rewriter(SE, *this);
1610016134
return Rewriter.visit(Expr);
1610116135
}

‎llvm/test/Analysis/LoopAccessAnalysis/no-dep-via-loop-guards.ll‎

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -354,13 +354,8 @@ exit:
354354
define void @nodep_via_logical_and_1(ptr %A, i32 %index, i32 %n) {
355355
; CHECK-LABEL: 'nodep_via_logical_and_1'
356356
; CHECK-NEXT: loop:
357-
; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop
358-
; CHECK-NEXT: Unknown data dependence.
357+
; CHECK-NEXT: Memory dependences are safe
359358
; CHECK-NEXT: Dependences:
360-
; CHECK-NEXT: Unknown:
361-
; CHECK-NEXT: %0 = load double, ptr %gep.load, align 8 ->
362-
; CHECK-NEXT: store double %0, ptr %gep.store, align 8
363-
; CHECK-EMPTY:
364359
; CHECK-NEXT: Run-time memory checks:
365360
; CHECK-NEXT: Grouped accesses:
366361
; CHECK-EMPTY:

‎llvm/test/Transforms/IndVarSimplify/loop-guard-order.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,14 +14,14 @@ define void @narrow_iv_precondition_order_1(ptr %start, i32 %base, i8 %n) {
1414
; CHECK-NEXT: [[PRE_1:%.*]] = icmp sgt i32 [[BASE]], [[N_EXT]]
1515
; CHECK-NEXT: br i1 [[PRE_1]], label %[[LOOP_PREHEADER:.*]], label %[[EXIT]]
1616
; CHECK: [[LOOP_PREHEADER]]:
17+
; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[BASE]] to i8
1718
; CHECK-NEXT: br label %[[LOOP:.*]]
1819
; CHECK: [[LOOP]]:
1920
; CHECK-NEXT: [[IV:%.*]] = phi ptr [ [[GEP:%.*]], %[[LOOP]] ], [ [[START]], %[[LOOP_PREHEADER]] ]
2021
; CHECK-NEXT: call void @foo()
2122
; CHECK-NEXT: [[END:%.*]] = load i8, ptr [[IV]], align 1
22-
; CHECK-NEXT: [[END_EXT:%.*]] = zext i8 [[END]] to i32
2323
; CHECK-NEXT: [[GEP]] = getelementptr inbounds i8, ptr [[IV]], i64 1
24-
; CHECK-NEXT: [[EC:%.*]] = icmp sgt i32 [[BASE]], [[END_EXT]]
24+
; CHECK-NEXT: [[EC:%.*]] = icmp ugt i8 [[TMP0]], [[END]]
2525
; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT_LOOPEXIT:.*]]
2626
; CHECK: [[EXIT_LOOPEXIT]]:
2727
; CHECK-NEXT: br label %[[EXIT]]

‎llvm/test/Transforms/LoopUnroll/peel-last-iteration-with-guards.ll‎

Lines changed: 36 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -77,10 +77,14 @@ define i32 @peel_with_guard_known_nonnegative_2(ptr %x, i32 %w) {
7777
; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[W]], -1
7878
; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[SUB]] to i64
7979
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[W]] to i64
80+
; CHECK-NEXT: [[TMP3:%.*]] = add nsw i64 [[WIDE_TRIP_COUNT]], -1
81+
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i64 [[TMP3]], 0
82+
; CHECK-NEXT: br i1 [[TMP2]], label %[[PH_SPLIT:.*]], label %[[EXIT_LOOPEXIT_PEEL_BEGIN:.*]]
83+
; CHECK: [[PH_SPLIT]]:
8084
; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
8185
; CHECK: [[LOOP_HEADER]]:
82-
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
83-
; CHECK-NEXT: [[RED:%.*]] = phi i32 [ 0, %[[PH]] ], [ [[ADD:%.*]], %[[LOOP_LATCH]] ]
86+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[PH_SPLIT]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
87+
; CHECK-NEXT: [[RED:%.*]] = phi i32 [ 0, %[[PH_SPLIT]] ], [ [[ADD:%.*]], %[[LOOP_LATCH]] ]
8488
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i64 [[IV]], [[TMP0]]
8589
; CHECK-NEXT: br i1 [[CMP1]], label %[[IF_THEN:.*]], label %[[LOOP_LATCH]]
8690
; CHECK: [[IF_THEN]]:
@@ -91,13 +95,38 @@ define i32 @peel_with_guard_known_nonnegative_2(ptr %x, i32 %w) {
9195
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
9296
; CHECK-NEXT: [[ADD]] = add nsw i32 [[TMP1]], [[RED]]
9397
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
94-
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[WIDE_TRIP_COUNT]]
95-
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT_LOOPEXIT:.*]], label %[[LOOP_HEADER]]
98+
; CHECK-NEXT: [[TMP4:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], 1
99+
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]
100+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT_LOOPEXIT_PEEL_BEGIN_LOOPEXIT:.*]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP2:![0-9]+]]
101+
; CHECK: [[EXIT_LOOPEXIT_PEEL_BEGIN_LOOPEXIT]]:
102+
; CHECK-NEXT: [[DOTPH:%.*]] = phi i64 [ [[IV_NEXT]], %[[LOOP_LATCH]] ]
103+
; CHECK-NEXT: [[DOTPH1:%.*]] = phi i32 [ [[ADD]], %[[LOOP_LATCH]] ]
104+
; CHECK-NEXT: br label %[[EXIT_LOOPEXIT_PEEL_BEGIN]]
105+
; CHECK: [[EXIT_LOOPEXIT_PEEL_BEGIN]]:
106+
; CHECK-NEXT: [[TMP5:%.*]] = phi i64 [ 0, %[[PH]] ], [ [[DOTPH]], %[[EXIT_LOOPEXIT_PEEL_BEGIN_LOOPEXIT]] ]
107+
; CHECK-NEXT: [[TMP6:%.*]] = phi i32 [ 0, %[[PH]] ], [ [[DOTPH1]], %[[EXIT_LOOPEXIT_PEEL_BEGIN_LOOPEXIT]] ]
108+
; CHECK-NEXT: br label %[[LOOP_HEADER_PEEL:.*]]
109+
; CHECK: [[LOOP_HEADER_PEEL]]:
110+
; CHECK-NEXT: [[CMP1_PEEL:%.*]] = icmp eq i64 [[TMP5]], [[TMP0]]
111+
; CHECK-NEXT: br i1 [[CMP1_PEEL]], label %[[IF_THEN_PEEL:.*]], label %[[LOOP_LATCH_PEEL:.*]]
112+
; CHECK: [[IF_THEN_PEEL]]:
113+
; CHECK-NEXT: tail call void @foo()
114+
; CHECK-NEXT: br label %[[LOOP_LATCH_PEEL]]
115+
; CHECK: [[LOOP_LATCH_PEEL]]:
116+
; CHECK-NEXT: [[ARRAYIDX_PEEL:%.*]] = getelementptr inbounds nuw i32, ptr [[X]], i64 [[TMP5]]
117+
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_PEEL]], align 4
118+
; CHECK-NEXT: [[ADD_PEEL:%.*]] = add nsw i32 [[TMP7]], [[TMP6]]
119+
; CHECK-NEXT: [[IV_NEXT_PEEL:%.*]] = add nuw nsw i64 [[TMP5]], 1
120+
; CHECK-NEXT: [[EC_PEEL:%.*]] = icmp eq i64 [[IV_NEXT_PEEL]], [[WIDE_TRIP_COUNT]]
121+
; CHECK-NEXT: br i1 [[EC_PEEL]], label %[[EXIT_LOOPEXIT_PEEL_NEXT:.*]], label %[[EXIT_LOOPEXIT_PEEL_NEXT]]
122+
; CHECK: [[EXIT_LOOPEXIT_PEEL_NEXT]]:
123+
; CHECK-NEXT: br label %[[LOOP_HEADER_PEEL_NEXT:.*]]
124+
; CHECK: [[LOOP_HEADER_PEEL_NEXT]]:
125+
; CHECK-NEXT: br label %[[EXIT_LOOPEXIT:.*]]
96126
; CHECK: [[EXIT_LOOPEXIT]]:
97-
; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], %[[LOOP_LATCH]] ]
98127
; CHECK-NEXT: br label %[[EXIT]]
99128
; CHECK: [[EXIT]]:
100-
; CHECK-NEXT: [[RED_LCSSA:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[ADD_LCSSA]], %[[EXIT_LOOPEXIT]] ]
129+
; CHECK-NEXT: [[RED_LCSSA:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[ADD_PEEL]], %[[EXIT_LOOPEXIT]] ]
101130
; CHECK-NEXT: ret i32 [[RED_LCSSA]]
102131
;
103132
entry:
@@ -156,7 +185,7 @@ define void @peel_with_guard2(i32 %n) {
156185
; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 1
157186
; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[N]], 1
158187
; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], [[TMP2]]
159-
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT_LOOPEXIT_PEEL_BEGIN_LOOPEXIT:.*]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP2:![0-9]+]]
188+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT_LOOPEXIT_PEEL_BEGIN_LOOPEXIT:.*]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
160189
; CHECK: [[EXIT_LOOPEXIT_PEEL_BEGIN_LOOPEXIT]]:
161190
; CHECK-NEXT: [[DOTPH:%.*]] = phi i32 [ [[IV_NEXT]], %[[LOOP_LATCH]] ]
162191
; CHECK-NEXT: br label %[[EXIT_LOOPEXIT_PEEL_BEGIN]]

‎llvm/test/Transforms/LoopVectorize/min-trip-count-known-via-scev.ll‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -144,8 +144,7 @@ define void @loop_never_executes_precondition_order_1(i64 %start, ptr %dst) {
144144
; CHECK-NEXT: br i1 [[PRE_1]], label %[[LOOP_PREHEADER:.*]], label %[[EXIT]]
145145
; CHECK: [[LOOP_PREHEADER]]:
146146
; CHECK-NEXT: [[TMP0:%.*]] = sub i64 1, [[START]]
147-
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2
148-
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
147+
; CHECK-NEXT: br i1 true, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
149148
; CHECK: [[VECTOR_PH]]:
150149
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2
151150
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
@@ -217,8 +216,7 @@ define void @loop_never_executes_precondition_order_1_predicates_flipped(i64 %st
217216
; CHECK-NEXT: br i1 [[PRE_1]], label %[[LOOP_PREHEADER:.*]], label %[[EXIT]]
218217
; CHECK: [[LOOP_PREHEADER]]:
219218
; CHECK-NEXT: [[TMP0:%.*]] = sub i64 1, [[START]]
220-
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2
221-
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
219+
; CHECK-NEXT: br i1 true, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
222220
; CHECK: [[VECTOR_PH]]:
223221
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2
224222
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]

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