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jmitrevsjmitrevs
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remove cppname (#562)
1 parent aeda609 commit db943b7

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5 files changed

+40
-41
lines changed

5 files changed

+40
-41
lines changed

‎hls4ml/backends/fpga/fpga_types.py‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -184,11 +184,11 @@ def definition_cpp(self, name_suffix='', as_reference=False):
184184

185185
class VivadoArrayVariableDefinition(VariableDefinition):
186186
def definition_cpp(self, name_suffix='', as_reference=False):
187-
return '{type} {name}{suffix}[{shape}]'.format(type=self.type.name, name=self.cppname, suffix=name_suffix, shape=self.size_cpp())
187+
return '{type} {name}{suffix}[{shape}]'.format(type=self.type.name, name=self.name, suffix=name_suffix, shape=self.size_cpp())
188188

189189
class QuartusArrayVariableDefinition(VariableDefinition):
190190
def definition_cpp(self, name_suffix='', as_reference=False):
191-
return '{type} {name}{suffix}[{shape}] {pragma}'.format(type=self.type.name, name=self.cppname, suffix=name_suffix, shape=self.size_cpp(), pragma=self.pragma)
191+
return '{type} {name}{suffix}[{shape}] {pragma}'.format(type=self.type.name, name=self.name, suffix=name_suffix, shape=self.size_cpp(), pragma=self.pragma)
192192

193193
class ArrayVariableConverter(object):
194194
def __init__(self, type_converter, prefix, definition_cls):
@@ -254,9 +254,9 @@ def __init__(self, type_converter):
254254
class VivadoStreamVariableDefinition(VariableDefinition):
255255
def definition_cpp(self, name_suffix='', as_reference=False):
256256
if as_reference: # Function parameter
257-
return 'hls::stream<{type}> &{name}{suffix}'.format(type=self.type.name, name=self.cppname, suffix=name_suffix)
257+
return 'hls::stream<{type}> &{name}{suffix}'.format(type=self.type.name, name=self.name, suffix=name_suffix)
258258
else: # Declaration
259-
return 'hls::stream<{type}> {name}{suffix}("{name}")'.format(type=self.type.name, name=self.cppname, suffix=name_suffix)
259+
return 'hls::stream<{type}> {name}{suffix}("{name}")'.format(type=self.type.name, name=self.name, suffix=name_suffix)
260260

261261
class StreamVariableConverter(object):
262262
def __init__(self, type_converter, prefix, definition_cls):
@@ -315,7 +315,7 @@ def __init__(self, type_converter):
315315

316316
class StaticWeightVariableDefinition(VariableDefinition):
317317
def definition_cpp(self, name_suffix='', as_reference=False):
318-
return '{type} {name}[{size}]'.format(type=self.type.name, name=self.cppname, size=self.data_length)
318+
return '{type} {name}[{size}]'.format(type=self.type.name, name=self.name, size=self.data_length)
319319

320320
class StaticWeightVariableConverter(object):
321321
def __init__(self, type_converter):

‎hls4ml/model/types.py‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -186,7 +186,6 @@ class Variable(object):
186186
def __init__(self, var_name, atype, **kwargs):
187187
self.name = var_name.format(**kwargs)
188188
self.type = atype
189-
self.cppname = re.sub(r'\W|^(?=\d)','_', self.name)
190189

191190
class TensorVariable(Variable):
192191
def __init__(self, shape, dim_names, var_name='layer{index}', type_name='layer{index}_t', precision=None, **kwargs):

‎hls4ml/writer/quartus_writer.py‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -358,10 +358,10 @@ def write_bridge(self, model):
358358
elif '//hls-fpga-machine-learning insert header' in line:
359359
dtype = line.split('#', 1)[1].strip()
360360
inputs_str = ', '.join(
361-
['{type} {name}[{shape}]'.format(type=dtype, name=i.cppname, shape=i.size_cpp()) for i in
361+
['{type} {name}[{shape}]'.format(type=dtype, name=i.member_name, shape=i.size_cpp()) for i in
362362
model_inputs])
363363
outputs_str = ', '.join(
364-
['{type} {name}[{shape}]'.format(type=dtype, name=o.cppname, shape=o.size_cpp()) for o in
364+
['{type} {name}[{shape}]'.format(type=dtype, name=o.member_name, shape=o.size_cpp()) for o in
365365
model_outputs])
366366
insize_str = ', '.join(
367367
['unsigned short &const_size_in_{}'.format(i) for i in range(1, len(model_inputs) + 1)])
@@ -381,8 +381,8 @@ def write_bridge(self, model):
381381
for i in model_inputs:
382382
newline += indent + 'nnet::convert_data<{}, {}, {}>({}, inputs_ap.{});\n'.format(dtype, i.type.name,
383383
i.size_cpp(),
384-
i.cppname,
385-
i.cppname)
384+
i.member_name,
385+
i.member_name)
386386
newline += '\n'
387387

388388
newline += indent + 'output_data outputs_ap;\n'
@@ -394,8 +394,8 @@ def write_bridge(self, model):
394394
newline += indent + 'nnet::convert_data_back<{}, {}, {}>(outputs_ap.{}, {});\n'.format(o.type.name,
395395
dtype,
396396
o.size_cpp(),
397-
o.cppname,
398-
o.cppname)
397+
o.member_name,
398+
o.member_name)
399399
elif '//hls-fpga-machine-learning insert trace_outputs' in line:
400400
newline = ''
401401
for layer in model.get_layers():

‎hls4ml/writer/vivado_accelerator_writer.py‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -251,11 +251,11 @@ def write_wrapper_test(self, model):
251251
elif '{}('.format(model.config.get_project_name()) in line:
252252
indent_amount = line.split(model.config.get_project_name())[0]
253253
newline = indent_amount + '{}_axi(inputs,outputs);\n'.format(model.config.get_project_name())
254-
elif inp.size_cpp() in line or inp.cppname in line or inp.type.name in line:
255-
newline = line.replace(inp.size_cpp(), 'N_IN').replace(inp.cppname, 'inputs').replace(inp.type.name,
254+
elif inp.size_cpp() in line or inp.name in line or inp.type.name in line:
255+
newline = line.replace(inp.size_cpp(), 'N_IN').replace(inp.name, 'inputs').replace(inp.type.name,
256256
'input_axi_t')
257-
elif out.size_cpp() in line or out.cppname in line or out.type.name in line:
258-
newline = line.replace(out.size_cpp(), 'N_OUT').replace(out.cppname, 'outputs').replace(out.type.name,
257+
elif out.size_cpp() in line or out.name in line or out.type.name in line:
258+
newline = line.replace(out.size_cpp(), 'N_OUT').replace(out.name, 'outputs').replace(out.type.name,
259259
'output_axi_t')
260260
else:
261261
newline = line
@@ -289,17 +289,17 @@ def write_wrapper_test(self, model):
289289
'{}_axi.h'.format(model.config.get_project_name()))
290290
elif inp.definition_cpp(name_suffix='_ap') in line:
291291
newline = line.replace(inp.definition_cpp(name_suffix='_ap'),
292-
'input_axi_t {}_ap[N_IN]'.format(inp.cppname))
292+
'input_axi_t {}_ap[N_IN]'.format(inp.name))
293293
elif out.definition_cpp(name_suffix='_ap') in line:
294294
newline = line.replace(out.definition_cpp(name_suffix='_ap'),
295-
'output_axi_t {}_ap[N_OUT]'.format(out.cppname))
295+
'output_axi_t {}_ap[N_OUT]'.format(out.name))
296296
elif '{}('.format(model.config.get_project_name()) in line:
297297
indent_amount = line.split(model.config.get_project_name())[0]
298-
newline = indent_amount + '{}_axi({}_ap,{}_ap);\n'.format(model.config.get_project_name(), inp.cppname,
299-
out.cppname)
300-
elif inp.size_cpp() in line or inp.cppname in line or inp.type.name in line:
298+
newline = indent_amount + '{}_axi({}_ap,{}_ap);\n'.format(model.config.get_project_name(), inp.name,
299+
out.name)
300+
elif inp.size_cpp() in line or inp.name in line or inp.type.name in line:
301301
newline = line.replace(inp.size_cpp(), 'N_IN').replace(inp.type.name, 'input_axi_t')
302-
elif out.size_cpp() in line or out.cppname in line or out.type.name in line:
302+
elif out.size_cpp() in line or out.name in line or out.type.name in line:
303303
newline = line.replace(out.size_cpp(), 'N_OUT').replace(out.type.name, 'output_axi_t')
304304
else:
305305
newline = line

‎hls4ml/writer/vivado_writer.py‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -140,9 +140,9 @@ def write_project_cpp(self, model):
140140
#Add input/output type
141141
elif '//hls-fpga-machine-learning insert IO' in line:
142142
newline = line
143-
all_inputs = [i.cppname for i in model_inputs]
144-
all_outputs = [o.cppname for o in model_outputs]
145-
all_brams = [b.cppname for b in model_brams]
143+
all_inputs = [i.name for i in model_inputs]
144+
all_outputs = [o.name for o in model_outputs]
145+
all_brams = [b.name for b in model_brams]
146146
io_type = model.config.get_config_value("IOType")
147147

148148
if io_type == 'io_parallel':
@@ -372,29 +372,29 @@ def write_test_bench(self, model):
372372
elif '//hls-fpga-machine-learning insert bram' in line:
373373
newline = line
374374
for bram in model_brams:
375-
newline += '#include \"firmware/weights/{}.h\"\n'.format(bram.cppname)
375+
newline += '#include \"firmware/weights/{}.h\"\n'.format(bram.name)
376376
elif '//hls-fpga-machine-learning insert data' in line:
377377
newline = line
378378
offset = 0
379379
for inp in model_inputs:
380380
newline += ' ' + inp.definition_cpp() + ';\n'
381-
newline += ' nnet::copy_data<float, {}, {}, {}>(in, {});\n'.format(inp.type.name, offset, inp.size_cpp(), inp.cppname)
381+
newline += ' nnet::copy_data<float, {}, {}, {}>(in, {});\n'.format(inp.type.name, offset, inp.size_cpp(), inp.name)
382382
offset += inp.size()
383383
for out in model_outputs:
384384
newline += ' ' + out.definition_cpp() + ';\n'
385385
elif '//hls-fpga-machine-learning insert zero' in line:
386386
newline = line
387387
for inp in model_inputs:
388388
newline += ' ' + inp.definition_cpp() + ';\n'
389-
newline += ' nnet::fill_zero<{}, {}>({});\n'.format(inp.type.name, inp.size_cpp(), inp.cppname)
389+
newline += ' nnet::fill_zero<{}, {}>({});\n'.format(inp.type.name, inp.size_cpp(), inp.name)
390390
for out in model_outputs:
391391
newline += ' ' + out.definition_cpp() + ';\n'
392392
elif '//hls-fpga-machine-learning insert top-level-function' in line:
393393
newline = line
394394

395-
input_vars = ','.join([i.cppname for i in model_inputs])
396-
output_vars = ','.join([o.cppname for o in model_outputs])
397-
bram_vars =','.join([b.cppname for b in model_brams])
395+
input_vars = ','.join([i.name for i in model_inputs])
396+
output_vars = ','.join([o.name for o in model_outputs])
397+
bram_vars =','.join([b.name for b in model_brams])
398398

399399
# Concatenate the input, output, and bram variables. Filter out empty/null values
400400
all_vars = ','.join(filter(None, [input_vars, output_vars, bram_vars]))
@@ -412,11 +412,11 @@ def write_test_bench(self, model):
412412
elif '//hls-fpga-machine-learning insert tb-output' in line:
413413
newline = line
414414
for out in model_outputs:
415-
newline += indent + 'nnet::print_result<{}, {}>({}, fout);\n'.format(out.type.name, out.size_cpp(), out.cppname) #TODO enable this
415+
newline += indent + 'nnet::print_result<{}, {}>({}, fout);\n'.format(out.type.name, out.size_cpp(), out.name) #TODO enable this
416416
elif '//hls-fpga-machine-learning insert output' in line or '//hls-fpga-machine-learning insert quantized' in line:
417417
newline = line
418418
for out in model_outputs:
419-
newline += indent + 'nnet::print_result<{}, {}>({}, std::cout, true);\n'.format(out.type.name, out.size_cpp(), out.cppname)
419+
newline += indent + 'nnet::print_result<{}, {}>({}, std::cout, true);\n'.format(out.type.name, out.size_cpp(), out.name)
420420
else:
421421
newline = line
422422
fout.write(newline)
@@ -447,11 +447,11 @@ def write_bridge(self, model):
447447
elif '//hls-fpga-machine-learning insert bram' in line:
448448
newline = line
449449
for bram in model_brams:
450-
newline += '#include \"firmware/weights/{}.h\"\n'.format(bram.cppname)
450+
newline += '#include \"firmware/weights/{}.h\"\n'.format(bram.name)
451451
elif '//hls-fpga-machine-learning insert header' in line:
452452
dtype = line.split('#', 1)[1].strip()
453-
inputs_str = ', '.join(['{type} {name}[{shape}]'.format(type=dtype, name=i.cppname, shape=i.size_cpp()) for i in model_inputs])
454-
outputs_str = ', '.join(['{type} {name}[{shape}]'.format(type=dtype, name=o.cppname, shape=o.size_cpp()) for o in model_outputs])
453+
inputs_str = ', '.join(['{type} {name}[{shape}]'.format(type=dtype, name=i.name, shape=i.size_cpp()) for i in model_inputs])
454+
outputs_str = ', '.join(['{type} {name}[{shape}]'.format(type=dtype, name=o.name, shape=o.size_cpp()) for o in model_outputs])
455455

456456
newline = ''
457457
newline += indent + inputs_str + ',\n'
@@ -461,17 +461,17 @@ def write_bridge(self, model):
461461
newline = ''
462462
for i in model_inputs:
463463
newline += indent + '{var};\n'.format(var=i.definition_cpp(name_suffix='_ap'))
464-
newline += indent + 'nnet::convert_data<{}, {}, {}>({}, {}_ap);\n'.format(dtype, i.type.name, i.size_cpp(), i.cppname, i.cppname)
464+
newline += indent + 'nnet::convert_data<{}, {}, {}>({}, {}_ap);\n'.format(dtype, i.type.name, i.size_cpp(), i.name, i.name)
465465
newline += '\n'
466466

467467
for o in model_outputs:
468468
newline += indent + '{var};\n'.format(var=o.definition_cpp(name_suffix='_ap'))
469469

470470
newline += '\n'
471471

472-
input_vars = ','.join([i.cppname + '_ap' for i in model_inputs])
473-
bram_vars =','.join([b.cppname for b in model_brams])
474-
output_vars = ','.join([o.cppname + '_ap' for o in model_outputs])
472+
input_vars = ','.join([i.name + '_ap' for i in model_inputs])
473+
bram_vars =','.join([b.name for b in model_brams])
474+
output_vars = ','.join([o.name + '_ap' for o in model_outputs])
475475

476476
# Concatenate the input, output, and bram variables. Filter out empty/null values
477477
all_vars = ','.join(filter(None, [input_vars, output_vars, bram_vars]))
@@ -482,7 +482,7 @@ def write_bridge(self, model):
482482
newline += '\n'
483483

484484
for o in model_outputs:
485-
newline += indent + 'nnet::convert_data<{}, {}, {}>({}_ap, {});\n'.format(o.type.name, dtype, o.size_cpp(), o.cppname, o.cppname)
485+
newline += indent + 'nnet::convert_data<{}, {}, {}>({}_ap, {});\n'.format(o.type.name, dtype, o.size_cpp(), o.name, o.name)
486486
elif '//hls-fpga-machine-learning insert trace_outputs' in line:
487487
newline = ''
488488
for layer in model.get_layers():

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