Updated tb template with clock gen module

Author: pConst

example_projects/testbench_template_tb/compile.tcl

@@ -17,7 +17,7 @@
 set library_file_list {
 
   work {main_tb.sv
-        main.sv
+        sim_clk_gen.sv
         clk_divider.sv
         edge_detect.sv
         delay.sv}

example_projects/testbench_template_tb/main_tb.sv

@@ -15,25 +15,30 @@
 module main_tb();
 
 logic clk200;
-initial begin
-  #0 clk200 = 1'b0;
-  forever
-    #2.5 clk200 = ~clk200;
-end
+sim_clk_gen #(
+  .FREQ( 200_000_000 ), // in Hz
+  .PHASE( 0 ),          // in degrees
+  .DUTY( 50 ),          // in percentage
+  .DISTORT( 10 )        // in picoseconds
+) clk200_gen (
+  .ena( 1'b1 ),
+  .clk( clk200 ),
+  .clkd(  )
+);
 
 // external device "asynchronous" clock
-logic clk33a;
-initial begin
-  #0 clk33a = 1'b0;
-  forever
-    #7 clk33a = ~clk33a;
-end
-
 logic clk33;
-//assign clk33 = clk33a;
-always @(*) begin
-  clk33 = #($urandom_range(0, 2000)*10ps) clk33a;
-end
+logic clk33d;
+sim_clk_gen #(
+  .FREQ( 200_000_000 ), // in Hz
+  .PHASE( 0 ),          // in degrees
+  .DUTY( 50 ),          // in percentage
+  .DISTORT( 1000 )      // in picoseconds
+) clk33_gen (
+  .ena( 1'b1 ),
+  .clk( clk33 ),
+  .clkd( clk33d )
+);
 
 logic rst;
 initial begin
@@ -138,13 +143,13 @@ module_under_test #(
 );
 
 // emulating external divice ==================================================
-// that works asynchronously on clk33 clock
+// that works asynchronously on distorted clk33d clock
 
-assign ADC1_SCLKOUT = clk33;
+assign ADC1_SCLKOUT = clk33d;
 
 logic [15:0] test_data = 16'b1010_1100_1100_1111;
 logic [7:0] adc1_seq_cntr = 0;
-always_ff @(posedge clk33) begin
+always_ff @(posedge clk33d) begin
   if( adc1_seq_cntr[7:0]==0 && ~ADC1_nCONV ) begin
     ADC1_BUSY <= 1'b1;
     ADC1_SDOUT <= test_data[15];

example_projects/testbench_template_tb/sim_clk_gen.sv

@@ -0,0 +1,72 @@
+//------------------------------------------------------------------------------
+// sim_clk_gen.sv
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+// Testbench clock generator written in System Verilog
+//
+
+`timescale 1ns / 1ps
+
+module sim_clk_gen #( parameter
+  FREQ  = 200_000_000,  // in Hz
+  PHASE = 0,            // in degrees
+  DUTY  = 50,           // in percentage
+  DISTORT = 200         // in picoseconds
+)(
+  input  ena,
+  output logic clk,     // ideal clock
+  output logic clkd     // distorted clock
+);
+
+  real clk_pd     = 1.0 / FREQ * 1e9;        // convert to ns
+  real clk_on     = DUTY / 100.0 * clk_pd;
+  real clk_off    = (100.0 - DUTY) / 100.0 * clk_pd;
+  real start_dly  = clk_pd / 4 * PHASE / 90;
+
+  logic do_clk;
+
+  initial begin
+    $display("FREQ      = %0d Hz", FREQ);
+    $display("PHASE     = %0d deg", PHASE);
+    $display("DUTY      = %0d %%",  DUTY);
+    $display("DISTORT   = %0d ps", DISTORT);
+
+    $display("PERIOD    = %0.3f ns", clk_pd);
+    $display("CLK_ON    = %0.3f ns", clk_on);
+    $display("CLK_OFF   = %0.3f ns", clk_off);
+    $display("START_DLY = %0.3f ns", start_dly);
+  end
+
+  initial begin
+    clk <= 0;
+    do_clk <= 1;
+  end
+
+  always @ (posedge ena or negedge ena) begin
+    if (ena) begin
+      #(start_dly) do_clk = 1;
+    end else begin
+      #(start_dly) do_clk = 0;
+    end
+  end
+
+  always @(posedge do_clk) begin
+    if( do_clk ) begin
+      clk = 1;
+      while ( do_clk ) begin
+        #(clk_on)  clk = 0;
+        #(clk_off) clk = 1;
+      end
+      clk = 0;
+    end
+  end
+
+  always @(*) begin
+    clkd = #($urandom_range(0, DISTORT)*1ps) clk;
+  end
+
+endmodule
+