Pinned Loading

1. simcommand simcommand Public

   SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.

   SystemVerilog 14 1

2. rtl2graph rtl2graph Public

   FIRRTL passes to transform a LoFIRRTL netlist to a graph for RTL embedding.

   Scala 3

3. chisel-recipes chisel-recipes Public

   A Chisel DSL for imperative control flow machines.

   Scala 1

4. tidalsim tidalsim Public

   Multi-level, sampled simulation using spike/uArch models/RTL for low latency, high fidelity, high throughput simulations

   Jupyter Notebook 5