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Merge pull request #22 from ethereum-optimism/tip/pcw109550/asterisc-contract-test-2
feat: Asterisc contracts VM tests - Forge Test
2 parents 8d7f523 + 1594779 commit 7daecab

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6 files changed

+2600
-19
lines changed

6 files changed

+2600
-19
lines changed

‎rvgo/fast/vm.go‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -685,10 +685,10 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
685685
rdValue = mask32Signed64(shl64(and64(imm, toU64(0x1F)), rs1Value))
686686
case 5: // 101 = SR~
687687
shamt := and64(imm, toU64(0x1F))
688-
switch shr64(toU64(6), imm) { // in rv64i the top 6 bits select the shift type
689-
case 0x00: // 000000 = SRLIW
688+
switch shr64(toU64(5), imm) { // top 7 bits select the shift type
689+
case 0x00: // 0000000 = SRLIW
690690
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), toU64(31))
691-
case 0x10: // 010000 = SRAIW
691+
case 0x20: // 0100000 = SRAIW
692692
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(toU64(31), shamt))
693693
}
694694
}

‎rvgo/slow/vm.go‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -860,10 +860,10 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
860860
rdValue = mask32Signed64(shl64(and64(imm, toU64(0x1F)), rs1Value))
861861
case 5: // 101 = SR~
862862
shamt := and64(imm, toU64(0x1F))
863-
switch shr64(toU64(6), imm).val() { // in rv64i the top 6 bits select the shift type
864-
case 0x00: // 000000 = SRLIW
863+
switch shr64(toU64(5), imm).val() { // top 7 bits select the shift type
864+
case 0x00: // 0000000 = SRLIW
865865
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), toU64(31))
866-
case 0x10: // 010000 = SRAIW
866+
case 0x20: // 0100000 = SRAIW
867867
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(toU64(31), shamt))
868868
}
869869
}

‎rvsol/.gas-snapshot‎

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,95 @@
1+
RISCV_Test:test_add_succeeds() (gas: 175505)
2+
RISCV_Test:test_addi_succeeds() (gas: 174720)
3+
RISCV_Test:test_addiw_succeeds() (gas: 174987)
4+
RISCV_Test:test_addw_succeeds() (gas: 175884)
5+
RISCV_Test:test_amoaddd_succeeds() (gas: 382706)
6+
RISCV_Test:test_amoaddw_succeeds() (gas: 369214)
7+
RISCV_Test:test_amoandd_succeeds() (gas: 382221)
8+
RISCV_Test:test_amoandw_succeeds() (gas: 368804)
9+
RISCV_Test:test_amomaxd_succeeds() (gas: 364731)
10+
RISCV_Test:test_amomaxud_succeeds() (gas: 364541)
11+
RISCV_Test:test_amomaxuw_succeeds() (gas: 350877)
12+
RISCV_Test:test_amomaxw_succeeds() (gas: 351148)
13+
RISCV_Test:test_amomind_succeeds() (gas: 364548)
14+
RISCV_Test:test_amominud_succeeds() (gas: 364454)
15+
RISCV_Test:test_amominuw_succeeds() (gas: 350518)
16+
RISCV_Test:test_amominw_succeeds() (gas: 351001)
17+
RISCV_Test:test_amoord_succeeds() (gas: 382509)
18+
RISCV_Test:test_amoorw_succeeds() (gas: 368930)
19+
RISCV_Test:test_amoswapd_succeeds() (gas: 364122)
20+
RISCV_Test:test_amoswapw_succeeds() (gas: 350330)
21+
RISCV_Test:test_amoxord_succeeds() (gas: 382480)
22+
RISCV_Test:test_amoxorw_succeeds() (gas: 368834)
23+
RISCV_Test:test_and_succeeds() (gas: 175411)
24+
RISCV_Test:test_andi_succeeds() (gas: 174708)
25+
RISCV_Test:test_auipc_succeeds() (gas: 174390)
26+
RISCV_Test:test_beq_succeeds() (gas: 176047)
27+
RISCV_Test:test_bge_succeeds() (gas: 176534)
28+
RISCV_Test:test_bgeu_succeeds() (gas: 176320)
29+
RISCV_Test:test_blt_succeeds() (gas: 176262)
30+
RISCV_Test:test_bltu_succeeds() (gas: 176180)
31+
RISCV_Test:test_bne_succeeds() (gas: 176231)
32+
RISCV_Test:test_csrrc_succeeds() (gas: 175051)
33+
RISCV_Test:test_csrrci_succeeds() (gas: 174245)
34+
RISCV_Test:test_csrrs_succeeds() (gas: 174929)
35+
RISCV_Test:test_csrrsi_succeeds() (gas: 174174)
36+
RISCV_Test:test_csrrw_succeeds() (gas: 174815)
37+
RISCV_Test:test_csrrwi_succeeds() (gas: 174033)
38+
RISCV_Test:test_div_succeeds() (gas: 175828)
39+
RISCV_Test:test_divu_succeeds() (gas: 175560)
40+
RISCV_Test:test_divuw_succeeds() (gas: 176054)
41+
RISCV_Test:test_divw_succeeds() (gas: 176831)
42+
RISCV_Test:test_ebreak_succeeds() (gas: 172772)
43+
RISCV_Test:test_ecall_succeeds() (gas: 175739)
44+
RISCV_Test:test_jal_succeeds() (gas: 175200)
45+
RISCV_Test:test_jalr_succeeds() (gas: 175297)
46+
RISCV_Test:test_lb_succeeds() (gas: 206810)
47+
RISCV_Test:test_lbu_succeeds() (gas: 206019)
48+
RISCV_Test:test_ld_succeeds() (gas: 217344)
49+
RISCV_Test:test_lh_succeeds() (gas: 208942)
50+
RISCV_Test:test_lhu_succeeds() (gas: 208063)
51+
RISCV_Test:test_lrd_succeeds() (gas: 217802)
52+
RISCV_Test:test_lrw_succeeds() (gas: 212114)
53+
RISCV_Test:test_lui_succeeds() (gas: 173754)
54+
RISCV_Test:test_lw_succeeds() (gas: 211910)
55+
RISCV_Test:test_lwu_succeeds() (gas: 211074)
56+
RISCV_Test:test_mul_succeeds() (gas: 175633)
57+
RISCV_Test:test_mulh_succeeds() (gas: 175947)
58+
RISCV_Test:test_mulhsu_succeeds() (gas: 175811)
59+
RISCV_Test:test_mulhu_succeeds() (gas: 175464)
60+
RISCV_Test:test_mulw_succeeds() (gas: 176107)
61+
RISCV_Test:test_or_succeeds() (gas: 175463)
62+
RISCV_Test:test_ori_succeeds() (gas: 174682)
63+
RISCV_Test:test_preimage_read_succeeds() (gas: 357373)
64+
RISCV_Test:test_preimage_write_succeeds() (gas: 207573)
65+
RISCV_Test:test_rem_succeeds() (gas: 175850)
66+
RISCV_Test:test_remu_succeeds() (gas: 175523)
67+
RISCV_Test:test_remuw_succeeds() (gas: 175998)
68+
RISCV_Test:test_remw_succeeds() (gas: 176811)
69+
RISCV_Test:test_sb_succeeds() (gas: 309299)
70+
RISCV_Test:test_scd_succeeds() (gas: 320930)
71+
RISCV_Test:test_scw_succeeds() (gas: 315067)
72+
RISCV_Test:test_sd_succeeds() (gas: 319248)
73+
RISCV_Test:test_sh_succeeds() (gas: 310754)
74+
RISCV_Test:test_sll_succeeds() (gas: 175474)
75+
RISCV_Test:test_slli_succeeds() (gas: 174740)
76+
RISCV_Test:test_slliw_succeeds() (gas: 174975)
77+
RISCV_Test:test_sllw_succeeds() (gas: 175730)
78+
RISCV_Test:test_slt_succeeds() (gas: 175683)
79+
RISCV_Test:test_slti_succeeds() (gas: 174974)
80+
RISCV_Test:test_sltiu_succeeds() (gas: 174735)
81+
RISCV_Test:test_sltu_succeeds() (gas: 175443)
82+
RISCV_Test:test_sra_succeeds() (gas: 176145)
83+
RISCV_Test:test_srai_succeeds() (gas: 175413)
84+
RISCV_Test:test_sraiw_succeeds() (gas: 175546)
85+
RISCV_Test:test_sraw_succeeds() (gas: 176306)
86+
RISCV_Test:test_srl_succeeds() (gas: 175561)
87+
RISCV_Test:test_srli_succeeds() (gas: 174856)
88+
RISCV_Test:test_srliw_succeeds() (gas: 175047)
89+
RISCV_Test:test_srlw_succeeds() (gas: 175709)
90+
RISCV_Test:test_step_abi_succeeds() (gas: 92452)
91+
RISCV_Test:test_sub_succeeds() (gas: 175553)
92+
RISCV_Test:test_subw_succeeds() (gas: 175894)
93+
RISCV_Test:test_sw_succeeds() (gas: 313600)
94+
RISCV_Test:test_xor_succeeds() (gas: 175384)
95+
RISCV_Test:test_xori_succeeds() (gas: 174717)

‎rvsol/src/RISCV.sol‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -510,7 +510,7 @@ contract RISCV {
510510
out := shr64(toU64(25), instr)
511511
}
512512

513-
function parseCSSR(instr) -> out {
513+
function parseCSRR(instr) -> out {
514514
out := shr64(toU64(20), instr)
515515
}
516516

@@ -721,7 +721,7 @@ contract RISCV {
721721
} case 3 { // ?11 = CSRRC(I)
722722
v := and64(out, not64(v))
723723
} default {
724-
revertWithCode(0xbadc0de0) // unkwown CSR mode
724+
revertWithCode(0xbadc0de0) // unknown CSR mode
725725
}
726726
writeCSR(num, v)
727727
}
@@ -1147,10 +1147,10 @@ contract RISCV {
11471147
rdValue := mask32Signed64(shl64(and64(imm, toU64(0x1F)), rs1Value))
11481148
} case 5 { // 101 = SR~
11491149
let shamt := and64(imm, toU64(0x1F))
1150-
switch shr64(toU64(6), imm) // in rv64i the top 6 bits select the shift type
1151-
case 0x00 { // 000000 = SRLIW
1150+
switch shr64(toU64(5), imm) // top 7 bits select the shift type
1151+
case 0x00 { // 0000000 = SRLIW
11521152
rdValue := signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), toU64(31))
1153-
} case 0x10 { // 010000 = SRAIW
1153+
} case 0x20 { // 0100000 = SRAIW
11541154
rdValue := signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(toU64(31), shamt))
11551155
}
11561156
}
@@ -1325,7 +1325,7 @@ contract RISCV {
13251325
setPC(add64(_pc, toU64(4))) // ignore breakpoint
13261326
}
13271327
} default { // CSR instructions
1328-
let imm := parseCSSR(instr)
1328+
let imm := parseCSRR(instr)
13291329
let value := rs1
13301330
if iszero64(and64(funct3, toU64(4))) {
13311331
value := getRegister(rs1)
@@ -1335,7 +1335,7 @@ contract RISCV {
13351335
setRegister(rd, rdValue)
13361336
setPC(add64(_pc, toU64(4)))
13371337
}
1338-
} case 0x2F { // 010_1111: RV32A and RV32A atomic operations extension
1338+
} case 0x2F { // 010_1111: RV{32,64}A and RV{32,64}A atomic operations extension
13391339
// acquire and release bits:
13401340
// aq := and64(shr64(toU64(1), funct7), toU64(1))
13411341
// rl := and64(funct7, toU64(1))
@@ -1348,7 +1348,7 @@ contract RISCV {
13481348
// 0b010 == RV32A W variants
13491349
// 0b011 == RV64A D variants
13501350
let size := shl64(funct3, toU64(1))
1351-
if lt64(size, toU64(4)) {
1351+
if or(lt64(size, toU64(4)), gt64(size, toU64(8))) {
13521352
revertWithCode(0xbada70) // bad AMO size
13531353
}
13541354
let addr := getRegister(rs1)

‎rvsol/test/.gas-snapshot‎

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,95 @@
1+
RISCV_Test:test_add_succeeds() (gas: 175505)
2+
RISCV_Test:test_addi_succeeds() (gas: 174720)
3+
RISCV_Test:test_addiw_succeeds() (gas: 174987)
4+
RISCV_Test:test_addw_succeeds() (gas: 175884)
5+
RISCV_Test:test_amoaddd_succeeds() (gas: 382706)
6+
RISCV_Test:test_amoaddw_succeeds() (gas: 369214)
7+
RISCV_Test:test_amoandd_succeeds() (gas: 382221)
8+
RISCV_Test:test_amoandw_succeeds() (gas: 368804)
9+
RISCV_Test:test_amomaxd_succeeds() (gas: 364731)
10+
RISCV_Test:test_amomaxud_succeeds() (gas: 364541)
11+
RISCV_Test:test_amomaxuw_succeeds() (gas: 350877)
12+
RISCV_Test:test_amomaxw_succeeds() (gas: 351148)
13+
RISCV_Test:test_amomind_succeeds() (gas: 364548)
14+
RISCV_Test:test_amominud_succeeds() (gas: 364454)
15+
RISCV_Test:test_amominuw_succeeds() (gas: 350518)
16+
RISCV_Test:test_amominw_succeeds() (gas: 351001)
17+
RISCV_Test:test_amoord_succeeds() (gas: 382509)
18+
RISCV_Test:test_amoorw_succeeds() (gas: 368930)
19+
RISCV_Test:test_amoswapd_succeeds() (gas: 364122)
20+
RISCV_Test:test_amoswapw_succeeds() (gas: 350330)
21+
RISCV_Test:test_amoxord_succeeds() (gas: 382480)
22+
RISCV_Test:test_amoxorw_succeeds() (gas: 368834)
23+
RISCV_Test:test_and_succeeds() (gas: 175411)
24+
RISCV_Test:test_andi_succeeds() (gas: 174708)
25+
RISCV_Test:test_auipc_succeeds() (gas: 174390)
26+
RISCV_Test:test_beq_succeeds() (gas: 176047)
27+
RISCV_Test:test_bge_succeeds() (gas: 176534)
28+
RISCV_Test:test_bgeu_succeeds() (gas: 176320)
29+
RISCV_Test:test_blt_succeeds() (gas: 176262)
30+
RISCV_Test:test_bltu_succeeds() (gas: 176180)
31+
RISCV_Test:test_bne_succeeds() (gas: 176231)
32+
RISCV_Test:test_csrrc_succeeds() (gas: 175051)
33+
RISCV_Test:test_csrrci_succeeds() (gas: 174245)
34+
RISCV_Test:test_csrrs_succeeds() (gas: 174929)
35+
RISCV_Test:test_csrrsi_succeeds() (gas: 174174)
36+
RISCV_Test:test_csrrw_succeeds() (gas: 174815)
37+
RISCV_Test:test_csrrwi_succeeds() (gas: 174033)
38+
RISCV_Test:test_div_succeeds() (gas: 175828)
39+
RISCV_Test:test_divu_succeeds() (gas: 175560)
40+
RISCV_Test:test_divuw_succeeds() (gas: 176054)
41+
RISCV_Test:test_divw_succeeds() (gas: 176831)
42+
RISCV_Test:test_ebreak_succeeds() (gas: 172772)
43+
RISCV_Test:test_ecall_succeeds() (gas: 175739)
44+
RISCV_Test:test_jal_succeeds() (gas: 175200)
45+
RISCV_Test:test_jalr_succeeds() (gas: 175297)
46+
RISCV_Test:test_lb_succeeds() (gas: 206810)
47+
RISCV_Test:test_lbu_succeeds() (gas: 206019)
48+
RISCV_Test:test_ld_succeeds() (gas: 217344)
49+
RISCV_Test:test_lh_succeeds() (gas: 208942)
50+
RISCV_Test:test_lhu_succeeds() (gas: 208063)
51+
RISCV_Test:test_lrd_succeeds() (gas: 217802)
52+
RISCV_Test:test_lrw_succeeds() (gas: 212114)
53+
RISCV_Test:test_lui_succeeds() (gas: 173754)
54+
RISCV_Test:test_lw_succeeds() (gas: 211910)
55+
RISCV_Test:test_lwu_succeeds() (gas: 211074)
56+
RISCV_Test:test_mul_succeeds() (gas: 175633)
57+
RISCV_Test:test_mulh_succeeds() (gas: 175947)
58+
RISCV_Test:test_mulhsu_succeeds() (gas: 175811)
59+
RISCV_Test:test_mulhu_succeeds() (gas: 175464)
60+
RISCV_Test:test_mulw_succeeds() (gas: 176107)
61+
RISCV_Test:test_or_succeeds() (gas: 175463)
62+
RISCV_Test:test_ori_succeeds() (gas: 174682)
63+
RISCV_Test:test_preimage_read_succeeds() (gas: 357373)
64+
RISCV_Test:test_preimage_write_succeeds() (gas: 207573)
65+
RISCV_Test:test_rem_succeeds() (gas: 175850)
66+
RISCV_Test:test_remu_succeeds() (gas: 175523)
67+
RISCV_Test:test_remuw_succeeds() (gas: 175998)
68+
RISCV_Test:test_remw_succeeds() (gas: 176811)
69+
RISCV_Test:test_sb_succeeds() (gas: 309299)
70+
RISCV_Test:test_scd_succeeds() (gas: 320930)
71+
RISCV_Test:test_scw_succeeds() (gas: 315067)
72+
RISCV_Test:test_sd_succeeds() (gas: 319248)
73+
RISCV_Test:test_sh_succeeds() (gas: 310754)
74+
RISCV_Test:test_sll_succeeds() (gas: 175474)
75+
RISCV_Test:test_slli_succeeds() (gas: 174740)
76+
RISCV_Test:test_slliw_succeeds() (gas: 174975)
77+
RISCV_Test:test_sllw_succeeds() (gas: 175730)
78+
RISCV_Test:test_slt_succeeds() (gas: 175683)
79+
RISCV_Test:test_slti_succeeds() (gas: 174974)
80+
RISCV_Test:test_sltiu_succeeds() (gas: 174735)
81+
RISCV_Test:test_sltu_succeeds() (gas: 175443)
82+
RISCV_Test:test_sra_succeeds() (gas: 176145)
83+
RISCV_Test:test_srai_succeeds() (gas: 175413)
84+
RISCV_Test:test_sraiw_succeeds() (gas: 175546)
85+
RISCV_Test:test_sraw_succeeds() (gas: 176306)
86+
RISCV_Test:test_srl_succeeds() (gas: 175561)
87+
RISCV_Test:test_srli_succeeds() (gas: 174856)
88+
RISCV_Test:test_srliw_succeeds() (gas: 175047)
89+
RISCV_Test:test_srlw_succeeds() (gas: 175709)
90+
RISCV_Test:test_step_abi_succeeds() (gas: 92452)
91+
RISCV_Test:test_sub_succeeds() (gas: 175553)
92+
RISCV_Test:test_subw_succeeds() (gas: 175894)
93+
RISCV_Test:test_sw_succeeds() (gas: 313600)
94+
RISCV_Test:test_xor_succeeds() (gas: 175384)
95+
RISCV_Test:test_xori_succeeds() (gas: 174717)

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