MNIST Handwritten Digit Deep Learning Accelerator ASIC

A deep learning accelerator ASIC chip design to classify images from the MNIST handwritten image dataset.

Source: Wikipedia - MNIST database

Design implementation for Tiny Tapeout.

Thanks to Columbus IEEE Joint Chapter of the Solid-State Circuits and Circuits and Systems Societies!

Example:

Input -->	Serialized to ASIC -->	Neural Network -->	Output
MNIST Image	Cycle Input Pin: 0123456 0123456 ---------------------------------- 0-1 0000000 0000000 2-3 0000000 0000000 4-5 0000000 0111100 6-7 0000111 1111100 8-9 0000111 1100000 10-11 0000011 0000000 12-13 0000001 1000000 14-15 0000000 1110000 16-17 0000000 0110000 18-19 0000001 1110000 20-21 0000011 1100000 22-23 0011111 0000000 24-25 0011110 0000000 26-27 0000000 0000000		BCD: 0101 = 5 7-Segment:5

MNIST Dataset + Preprocessing

Input images from the MNIST Dataset are preprocessed by a raspberry pi and transmitted to the ASIC. The images in MNIST are 28x28 grayscale images. However, as part of the preprocessing step, these images are reduced to a 14x14 black/white image to reduce the amount of data needed to be transmitted to the ASIC and to reduce the complexity of the neural network. Since the images are 14x14, a 8-pin interface (ui_in) is used which transmits 7 pixels at a time for 28 clock cycles to transmit each image. The remaining bit, the most significant bit (MSB), is a active-low signal. pulled low to start transmitting a new image.

Preprocessing Python Script

A preprocessing python script (utility.py) is provided to convert the standard MNIST images into the reduced dataformat used in this project. The script is used to train the network, test the network, convert the pytorch implementation into verilog, and generate cocotb unit-tests directly from the MNIST dataset.

Design

Neural Network

Based on MNIST pytorch example.

class Net(nn.Module):
    def __init__(self):
        super(Net, self).__init__()
        self.conv1 = nn.Conv2d(1, 16, 3, 1)  #1,32,3,1
        self.conv2 = nn.Conv2d(16, 32, 3, 1) #32,64,3,1
        self.dropout1 = nn.Dropout(0.25)
        self.dropout2 = nn.Dropout(0.5)
        self.fc1 = nn.Linear(800, 128) #9216
        self.fc2 = nn.Linear(128, 10)

    def forward(self, x):
        x = self.conv1(x)
        x = F.relu(x)
        x = self.conv2(x)
        x = F.relu(x)
        x = F.max_pool2d(x, 2)
        x = self.dropout1(x)
        x = torch.flatten(x, 1)
        x = self.fc1(x)
        x = F.relu(x)
        x = self.dropout2(x)
        x = self.fc2(x)
        output = F.log_softmax(x, dim=1)
        return output

Hardware Implementation

Implemented into Verilog as a main file: project.v with 3 supporting files for readimage.v, neuralnetwork.v, and decoder.v

Latest GDS Rendering:

Results

Goal - show results of chip vs identical python-based neural network implementation.

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References

@ARTICLE{leflow, author = {{Noronha}, D.~H. and {Salehpour}, B. and {Wilton}, S.~J.~E.}, title = "{LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks}", journal = {ArXiv e-prints}, archivePrefix = "arXiv", eprint = {1807.05317}, keywords = {Computer Science - Machine Learning, Statistics - Machine Learning}, year = 2018, month = jul, adsurl = {http://adsabs.harvard.edu/abs/2018arXiv180705317N} }

• Example Verilog TT Seven Segment Display
• Example Verilog reading an image
• Example PyTorch MNIST Neural Network
• MNIST Database