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[Xtensa] ADD support of the CLAMPS/MINMAX in target parser.
Implement support of the CLAMPS/MINMAX in Xtensa target parser. Fix clang CPUs test.
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-38
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‎clang/test/Driver/xtensa-cpus.c

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10,8 +10,9 @@
1010
// RUN: %clang -target xtensa -### -c %s 2>&1 -mcpu=esp32 | FileCheck -check-prefix=MCPU-ESP32 %s
1111
// MCPU-ESP32: "-target-cpu" "esp32"
1212
// MCPU-ESP32: "-target-feature" "+density" "-target-feature" "+fp" "-target-feature" "+windowed" "-target-feature" "+bool"
13-
// MCPU-ESP32: "-target-feature" "+loop" "-target-feature" "+sext" "-target-feature" "+nsa" "-target-feature" "+mul32"
14-
// MCPU-ESP32: "-target-feature" "+mul32high" "-target-feature" "+div32" "-target-feature" "+mac16" "-target-feature" "+dfpaccel"
13+
// MCPU-ESP32: "-target-feature" "+loop" "-target-feature" "+sext" "-target-feature" "+nsa" "-target-feature" "+clamps"
14+
// MCPU-ESP32: "-target-feature" "+minmax" "-target-feature" "+mul32" "-target-feature" "+mul32high"
15+
// MCPU-ESP32: "-target-feature" "+div32" "-target-feature" "+mac16" "-target-feature" "+dfpaccel"
1516
// MCPU-ESP32: "-target-feature" "+s32c1i" "-target-feature" "+threadptr" "-target-feature" "+atomctl" "-target-feature" "+memctl"
1617
// MCPU-ESP32: "-target-feature" "+debug" "-target-feature" "+exception" "-target-feature" "+highpriinterrupts"
1718
// MCPU-ESP32: "-target-feature" "+coprocessor" "-target-feature" "+interrupt" "-target-feature" "+rvector" "-target-feature" "+timerint"
@@ -20,17 +21,19 @@
2021
// RUN: %clang -target xtensa -### -c %s 2>&1 -mcpu=esp32s2 | FileCheck -check-prefix=MCPU-ESP32S2 %s
2122
// MCPU-ESP32S2: "-target-cpu" "esp32s2"
2223
// MCPU-ESP32S2: "-target-feature" "+density" "-target-feature" "+windowed" "-target-feature" "+sext" "-target-feature" "+nsa"
23-
// MCPU-ESP32S2: "-target-feature" "+mul32" "-target-feature" "+mul32high" "-target-feature" "+div32" "-target-feature" "+threadptr"
24+
// MCPU-ESP32S2: "-target-feature" "+clamps" "-target-feature" "+minmax" "-target-feature" "+mul32"
25+
// MCPU-ESP32S2: "-target-feature" "+mul32high" "-target-feature" "+div32" "-target-feature" "+threadptr"
2426
// MCPU-ESP32S2: "-target-feature" "+memctl" "-target-feature" "+debug" "-target-feature" "+exception" "-target-feature" "+highpriinterrupts"
2527
// MCPU-ESP32S2: "-target-feature" "+coprocessor" "-target-feature" "+interrupt" "-target-feature" "+rvector" "-target-feature" "+timerint"
2628
// MCPU-ESP32S2: "-target-feature" "+prid" "-target-feature" "+regprotect" "-target-feature" "+miscsr" "-target-feature" "+esp32s2"
2729

2830
// RUN: %clang -target xtensa -### -c %s 2>&1 -mcpu=esp32s3 | FileCheck -check-prefix=MCPU-ESP32S3 %s
2931
// MCPU-ESP32S3: "-target-cpu" "esp32s3"
3032
// MCPU-ESP32S3: "-target-feature" "+density" "-target-feature" "+fp" "-target-feature" "+windowed" "-target-feature" "+bool"
31-
// MCPU-ESP32S3: "-target-feature" "+loop" "-target-feature" "+sext" "-target-feature" "+nsa" "-target-feature" "+mul32"
32-
// MCPU-ESP32S3: "-target-feature" "+mul32high" "-target-feature" "+div32" "-target-feature" "+mac16" "-target-feature" "+dfpaccel"
33-
// MCPU-ESP32S3: "-target-feature" "+s32c1i" "-target-feature" "+threadptr" "-target-feature" "+atomctl" "-target-feature" "+memctl"
33+
// MCPU-ESP32S3: "-target-feature" "+loop" "-target-feature" "+sext" "-target-feature" "+nsa" "-target-feature" "+clamps"
34+
// MCPU-ESP32S3: "-target-feature" "+minmax" "-target-feature" "+mul32" "-target-feature" "+mul32high" "-target-feature" "+div32"
35+
// MCPU-ESP32S3: "-target-feature" "+mac16" "-target-feature" "+dfpaccel" "-target-feature" "+s32c1i"
36+
// MCPU-ESP32S3: "-target-feature" "+threadptr" "-target-feature" "+atomctl" "-target-feature" "+memctl"
3437
// MCPU-ESP32S3: "-target-feature" "+debug" "-target-feature" "+exception" "-target-feature" "+highpriinterrupts"
3538
// MCPU-ESP32S3: "-target-feature" "+coprocessor" "-target-feature" "+interrupt" "-target-feature" "+rvector" "-target-feature" "+timerint"
3639
// MCPU-ESP32S3: "-target-feature" "+prid" "-target-feature" "+regprotect" "-target-feature" "+miscsr" "-target-feature" "+esp32s3"

‎llvm/include/llvm/TargetParser/XtensaTargetParser.def

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,8 @@ XTENSA_FEATURE(FK_BOOLEAN, "bool")
2121
XTENSA_FEATURE(FK_LOOP, "loop")
2222
XTENSA_FEATURE(FK_SEXT, "sext")
2323
XTENSA_FEATURE(FK_NSA, "nsa")
24+
XTENSA_FEATURE(FK_CLAMPS, "clamps")
25+
XTENSA_FEATURE(FK_MINMAX, "minmax")
2426
XTENSA_FEATURE(FK_MUL32, "mul32")
2527
XTENSA_FEATURE(FK_MUL32HIGH, "mul32high")
2628
XTENSA_FEATURE(FK_DIV32, "div32")
@@ -57,18 +59,18 @@ XTENSA_CPU(ESP8266, {"esp8266"},
5759
FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_REGPROTECT | FK_PRID))
5860
XTENSA_CPU(ESP32, {"esp32"},
5961
(FK_DENSITY | FK_FP | FK_LOOP | FK_MAC16 | FK_WINDOWED | FK_BOOLEAN |
60-
FK_SEXT | FK_NSA | FK_MUL32 | FK_MUL32HIGH | FK_DFPACCEL | FK_S32C1I | FK_THREADPTR | FK_DIV32 |
61-
FK_ATOMCTL | FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | FK_COPROCESSOR |
62-
FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR))
62+
FK_SEXT | FK_NSA | FK_CLAMPS | FK_MINMAX | FK_MUL32 | FK_MUL32HIGH | FK_DFPACCEL | FK_S32C1I |
63+
FK_THREADPTR | FK_DIV32 | FK_ATOMCTL | FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS |
64+
FK_COPROCESSOR | FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR))
6365
XTENSA_CPU(ESP32S2, {"esp32s2"},
64-
(FK_DENSITY | FK_WINDOWED | FK_SEXT | FK_NSA | FK_MUL32 | FK_MUL32HIGH | FK_THREADPTR | FK_DIV32 |
65-
FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | FK_COPROCESSOR | FK_INTERRUPT |
66-
FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR | FK_ESP32S2OPS))
66+
(FK_DENSITY | FK_WINDOWED | FK_SEXT | FK_NSA | FK_CLAMPS | FK_MINMAX | FK_MUL32 | FK_MUL32HIGH |
67+
FK_THREADPTR | FK_DIV32 | FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | FK_COPROCESSOR |
68+
FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR | FK_ESP32S2OPS))
6769
XTENSA_CPU(ESP32S3, {"esp32s3"},
6870
(FK_DENSITY | FK_FP | FK_LOOP | FK_MAC16 | FK_WINDOWED | FK_BOOLEAN |
69-
FK_SEXT | FK_NSA | FK_MUL32 | FK_MUL32HIGH | FK_DFPACCEL | FK_S32C1I | FK_THREADPTR | FK_DIV32 |
70-
FK_ATOMCTL | FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS | FK_COPROCESSOR |
71-
FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR |
71+
FK_SEXT | FK_NSA | FK_CLAMPS | FK_MINMAX | FK_MUL32 | FK_MUL32HIGH | FK_DFPACCEL | FK_S32C1I |
72+
FK_THREADPTR | FK_DIV32 | FK_ATOMCTL | FK_MEMCTL | FK_DEBUG | FK_EXCEPTION | FK_HIGHPRIINTERRUPTS |
73+
FK_COPROCESSOR | FK_INTERRUPT | FK_RVECTOR | FK_TIMERINT | FK_PRID | FK_REGPROTECT | FK_MISCSR |
7274
FK_ESP32S3OPS))
7375

7476
#undef XTENSA_CPU

‎llvm/include/llvm/TargetParser/XtensaTargetParser.h

Lines changed: 24 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -36,28 +36,30 @@ enum FeatureKind : uint64_t {
3636
FK_LOOP = 1 << 5,
3737
FK_SEXT = 1 << 6,
3838
FK_NSA = 1 << 7,
39-
FK_MUL32 = 1 << 8,
40-
FK_MUL32HIGH = 1 << 9,
41-
FK_DIV32 = 1 << 10,
42-
FK_MAC16 = 1 << 11,
43-
FK_DFPACCEL = 1 << 12,
44-
FK_S32C1I = 1 << 13,
45-
FK_THREADPTR = 1 << 14,
46-
FK_EXTENDEDL32R = 1 << 15,
47-
FK_ATOMCTL = 1 << 16,
48-
FK_MEMCTL = 1 << 17,
49-
FK_DEBUG = 1 << 18,
50-
FK_EXCEPTION = 1 << 19,
51-
FK_HIGHPRIINTERRUPTS = 1 << 20,
52-
FK_COPROCESSOR = 1 << 21,
53-
FK_INTERRUPT = 1 << 22,
54-
FK_RVECTOR = 1 << 23,
55-
FK_TIMERINT = 1 << 24,
56-
FK_PRID = 1 << 25,
57-
FK_REGPROTECT = 1 << 26,
58-
FK_MISCSR = 1 << 27,
59-
FK_ESP32S2OPS = 1 << 28,
60-
FK_ESP32S3OPS = 1 << 29
39+
FK_CLAMPS = 1 << 8,
40+
FK_MINMAX = 1 << 9,
41+
FK_MUL32 = 1 << 10,
42+
FK_MUL32HIGH = 1 << 11,
43+
FK_DIV32 = 1 << 12,
44+
FK_MAC16 = 1 << 13,
45+
FK_DFPACCEL = 1 << 14,
46+
FK_S32C1I = 1 << 15,
47+
FK_THREADPTR = 1 << 16,
48+
FK_EXTENDEDL32R = 1 << 17,
49+
FK_ATOMCTL = 1 << 18,
50+
FK_MEMCTL = 1 << 19,
51+
FK_DEBUG = 1 << 20,
52+
FK_EXCEPTION = 1 << 21,
53+
FK_HIGHPRIINTERRUPTS = 1 << 22,
54+
FK_COPROCESSOR = 1 << 23,
55+
FK_INTERRUPT = 1 << 24,
56+
FK_RVECTOR = 1 << 25,
57+
FK_TIMERINT = 1 << 26,
58+
FK_PRID = 1 << 27,
59+
FK_REGPROTECT = 1 << 28,
60+
FK_MISCSR = 1 << 29,
61+
FK_ESP32S2OPS = 1 << 30,
62+
FK_ESP32S3OPS = 1ULL << 31
6163
};
6264

6365
CPUKind parseCPUKind(StringRef CPU);

‎llvm/lib/Target/Xtensa/XtensaInstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1346,7 +1346,7 @@ def SEXT : RRR_Inst<0x00, 0x03, 0x02, (outs AR:$r), (ins AR:$s, imm7_22:$imm),
13461346
//===----------------------------------------------------------------------===//
13471347

13481348
def CLAMPS : RRR_Inst<0x00, 0x03, 0x03, (outs AR:$r), (ins AR:$s, imm7_22:$imm),
1349-
"clamps\t$r, $s, $imm", []>, Requires<[HasSEXT]> {
1349+
"clamps\t$r, $s, $imm", []>, Requires<[HasCLAMPS]> {
13501350
bits<4> imm;
13511351

13521352
let t = imm;

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