@@ -96,6 +96,29 @@ typedef enum {
9696 UART_PARITY_ERROR
9797} hardwareSerial_error_t;
9898
99+ typedef enum {
100+ UART_CLK_SRC_DEFAULT = UART_SCLK_DEFAULT,
101+ #if SOC_UART_SUPPORT_APB_CLK
102+ UART_CLK_SRC_APB = UART_SCLK_APB,
103+ #endif
104+ #if SOC_UART_SUPPORT_PLL_F40M_CLK
105+ UART_CLK_SRC_PLL = UART_SCLK_PLL_F40M,
106+ #elif SOC_UART_SUPPORT_PLL_F80M_CLK
107+ UART_CLK_SRC_PLL = UART_SCLK_PLL_F80M,
108+ #elif CONFIG_IDF_TARGET_ESP32H2
109+ UART_CLK_SRC_PLL = UART_SCLK_PLL_F48M,
110+ #endif
111+ #if SOC_UART_SUPPORT_XTAL_CLK
112+ UART_CLK_SRC_XTAL = UART_SCLK_XTAL,
113+ #endif
114+ #if SOC_UART_SUPPORT_RTC_CLK
115+ UART_CLK_SRC_RTC = UART_SCLK_RTC,
116+ #endif
117+ #if SOC_UART_SUPPORT_REF_TICK
118+ UART_CLK_SRC_REF_TICK = UART_SCLK_REF_TICK,
119+ #endif
120+ } SerialClkSrc;
121+
99122#ifndef ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE
100123#ifndef CONFIG_ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE
101124#define ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE 2048
@@ -344,6 +367,17 @@ class HardwareSerial : public Stream {
344367 // UART_MODE_RS485_COLLISION_DETECT = 0x03 mode: RS485 collision detection UART mode (used for test purposes)
345368 // UART_MODE_RS485_APP_CTRL = 0x04 mode: application control RS485 UART mode (used for test purposes)
346369 bool setMode (SerialMode mode);
370+ // Used to set the UART clock source mode. It must be set before calling begin(), otherwise it won't have any effect.
371+ // Not all clock source are available to every SoC. The compatible option are listed here:
372+ // UART_CLK_SRC_DEFAULT :: any SoC - it will set whatever IDF defines as the default UART Clock Source
373+ // UART_CLK_SRC_APB :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
374+ // UART_CLK_SRC_PLL :: ESP32-C2, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2 and ESP32-P4
375+ // UART_CLK_SRC_XTAL :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
376+ // UART_CLK_SRC_RTC :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
377+ // UART_CLK_SRC_REF_TICK :: ESP32 and ESP32-S2
378+ // Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
379+ // Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source
380+ bool setClockSource (SerialClkSrc clkSrc);
347381 size_t setRxBufferSize (size_t new_size);
348382 size_t setTxBufferSize (size_t new_size);
349383
0 commit comments