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MabezDevMabezDev
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Merge pull request #25 from jessebraham/feature/deprecate
Add the PAC to the repo, add deprecation notice to `README.md`
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‎Cargo.toml

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@@ -1,35 +1,22 @@
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[package]
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name = "esp8266-hal"
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version = "0.5.1"
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authors = [
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"Robin Appelman <robin@icewind.nl>",
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"Jesse Braham <jesse@beta7.io>",
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]
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name = "esp8266-hal"
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version = "0.5.1"
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authors = ["Jesse Braham <jesse@beta7.io>", "Robin Appelman <robin@icewind.nl>"]
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edition = "2021"
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description = "HAL for ESP8266 microcontrollers"
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repository = "https://github.com/esp-rs/esp8266-hal"
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license = "MIT OR Apache-2.0"
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keywords = [
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"embedded",
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"embedded-hal",
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"esp",
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"esp8266",
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"no-std",
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]
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categories = [
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"embedded",
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"hardware-support",
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"no-std",
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]
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keywords = ["embedded", "embedded-hal", "esp", "esp8266", "no-std"]
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categories = ["embedded", "hardware-support", "no-std"]
2512

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[dependencies]
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embedded-hal = { version = "0.2", features = ["unproven"] }
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esp8266 = "0.6"
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esp8266 = { version = "0.6", path = "./esp8266" }
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nb = "1.0"
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paste = { version = "1.0", optional = true }
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void = { version = "1.0", default-features = false }
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xtensa-lx = { version = "0.7", features = ["esp8266"] }
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paste = { version = "1.0", optional = true }
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void = { version = "1.0", default-features = false }
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xtensa-lx = { version = "0.7", features = ["esp8266"] }
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xtensa-lx-rt = { version = "0.12", features = ["esp8266"], optional = true }
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[dependencies.esp8266-hal-proc-macros]

‎README.md

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# esp8266-hal
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> ⚠️ **NOTE** this HAL is now in maintenence mode. No further development is planned at this time, however PRs may still be accepted.
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> ⚠️ **NOTE** this HAL is deprecated, no further development is planned.
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An experimental hardware abstraction layer for the [ESP8266](https://en.wikipedia.org/wiki/ESP8266) written in Rust.
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‎esp8266/.cargo/config.toml

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[build]
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target = "xtensa-esp8266-none-elf"
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[unstable]
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build-std = ["core"]

‎esp8266/Cargo.toml

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[package]
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name = "esp8266"
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version = "0.7.0"
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edition = "2021"
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rust-version = "1.67"
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description = "Peripheral access crate for the ESP8266"
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repository = "https://github.com/esp-rs/esp-pacs"
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license = "MIT OR Apache-2.0"
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keywords = [
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"embedded",
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"esp8266",
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"no-std",
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"wifi",
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]
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categories = [
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"embedded",
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"hardware-support",
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"no-std",
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]
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include = [
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"src/**",
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"build.rs",
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"device.x",
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]
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[lib]
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bench = false
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test = false
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[dependencies]
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critical-section = { version = "1.1.1", optional = true }
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vcell = "0.1.3"
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xtensa-lx = "0.8.0"
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[features]
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default = ["xtensa-lx/esp8266"]
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rt = []
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impl-register-debug = []

‎esp8266/README.md

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# esp8266
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[![Crates.io](https://img.shields.io/crates/v/esp8266?labelColor=1C2C2E&color=C96329&logo=Rust&style=flat-square)](https://crates.io/crates/esp8266)
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[![docs.rs](https://img.shields.io/docsrs/esp8266?labelColor=1C2C2E&color=C96329&logo=rust&style=flat-square)](https://docs.rs/esp8266)
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![Crates.io](https://img.shields.io/crates/l/esp8266?labelColor=1C2C2E&style=flat-square)
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[![Matrix](https://img.shields.io/matrix/esp-rs:matrix.org?label=join%20matrix&labelColor=1C2C2E&color=BEC5C9&logo=matrix&style=flat-square)](https://matrix.to/#/#esp-rs:matrix.org)
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A **P**eripheral **A**ccess **C**rate (**PAC**) for the **esp8266** from Espressif. See the [svd2rust] repository for more information on how to use this crate.
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If you find any problems with the included SVD file please open an issue in the [espressif/svd] repository so that the fixes can be applied upstream.
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[svd2rust]: https://github.com/rust-embedded/svd2rust
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[espressif/svd]: https://github.com/espressif/svd
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## [Documentation](https://docs.rs/esp8266)
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## License
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Licensed under either of:
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- Apache License, Version 2.0 ([LICENSE-APACHE](../LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)
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- MIT license ([LICENSE-MIT](../LICENSE-MIT) or http://opensource.org/licenses/MIT)
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at your option.
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### Contribution
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Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in
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the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without
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any additional terms or conditions.

‎esp8266/build.rs

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#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"]
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use std::env;
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use std::fs::File;
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use std::io::Write;
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use std::path::PathBuf;
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fn main() {
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if env::var_os("CARGO_FEATURE_RT").is_some() {
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let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
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File::create(out.join("device.x"))
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.unwrap()
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.write_all(include_bytes!("device.x"))
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.unwrap();
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println!("cargo:rustc-link-search={}", out.display());
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println!("cargo:rerun-if-changed=device.x");
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}
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println!("cargo:rerun-if-changed=build.rs");
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}

‎esp8266/device.x

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‎esp8266/src/dport.rs

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#[doc = r"Register block"]
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#[repr(C)]
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#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
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pub struct RegisterBlock {
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_reserved0: [u8; 0x04],
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edge_int_enable: EDGE_INT_ENABLE,
7+
_reserved1: [u8; 0x04],
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spi_cache: SPI_CACHE,
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_reserved2: [u8; 0x04],
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dport_ctl: DPORT_CTL,
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_reserved3: [u8; 0x08],
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spi_interrupt_type: SPI_INTERRUPT_TYPE,
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spi_cache_target: SPI_CACHE_TARGET,
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ioswap: IOSWAP,
15+
}
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impl RegisterBlock {
17+
#[doc = "0x04 - EDGE_INT_ENABLE"]
18+
#[inline(always)]
19+
pub const fn edge_int_enable(&self) -> &EDGE_INT_ENABLE {
20+
&self.edge_int_enable
21+
}
22+
#[doc = "0x0c - Controls SPI memory-mapped caching"]
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#[inline(always)]
24+
pub const fn spi_cache(&self) -> &SPI_CACHE {
25+
&self.spi_cache
26+
}
27+
#[doc = "0x14 - DPORT_CTL"]
28+
#[inline(always)]
29+
pub const fn dport_ctl(&self) -> &DPORT_CTL {
30+
&self.dport_ctl
31+
}
32+
#[doc = "0x20 - SPI interrupt type register"]
33+
#[inline(always)]
34+
pub const fn spi_interrupt_type(&self) -> &SPI_INTERRUPT_TYPE {
35+
&self.spi_interrupt_type
36+
}
37+
#[doc = "0x24 - Control where the cache is mapped (unconfirmed)"]
38+
#[inline(always)]
39+
pub const fn spi_cache_target(&self) -> &SPI_CACHE_TARGET {
40+
&self.spi_cache_target
41+
}
42+
#[doc = "0x28 - IO Swap register"]
43+
#[inline(always)]
44+
pub const fn ioswap(&self) -> &IOSWAP {
45+
&self.ioswap
46+
}
47+
}
48+
#[doc = "EDGE_INT_ENABLE (rw) register accessor: EDGE_INT_ENABLE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_int_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_int_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_int_enable`] module"]
49+
pub type EDGE_INT_ENABLE = crate::Reg<edge_int_enable::EDGE_INT_ENABLE_SPEC>;
50+
#[doc = "EDGE_INT_ENABLE"]
51+
pub mod edge_int_enable;
52+
#[doc = "DPORT_CTL (rw) register accessor: DPORT_CTL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dport_ctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dport_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dport_ctl`] module"]
53+
pub type DPORT_CTL = crate::Reg<dport_ctl::DPORT_CTL_SPEC>;
54+
#[doc = "DPORT_CTL"]
55+
pub mod dport_ctl;
56+
#[doc = "IOSWAP (rw) register accessor: IO Swap register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioswap::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioswap::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioswap`] module"]
57+
pub type IOSWAP = crate::Reg<ioswap::IOSWAP_SPEC>;
58+
#[doc = "IO Swap register"]
59+
pub mod ioswap;
60+
#[doc = "SPI_CACHE (rw) register accessor: Controls SPI memory-mapped caching\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cache::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cache::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_cache`] module"]
61+
pub type SPI_CACHE = crate::Reg<spi_cache::SPI_CACHE_SPEC>;
62+
#[doc = "Controls SPI memory-mapped caching"]
63+
pub mod spi_cache;
64+
#[doc = "SPI_INTERRUPT_TYPE (r) register accessor: SPI interrupt type register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_interrupt_type::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_interrupt_type`] module"]
65+
pub type SPI_INTERRUPT_TYPE = crate::Reg<spi_interrupt_type::SPI_INTERRUPT_TYPE_SPEC>;
66+
#[doc = "SPI interrupt type register"]
67+
pub mod spi_interrupt_type;
68+
#[doc = "SPI_CACHE_TARGET (rw) register accessor: Control where the cache is mapped (unconfirmed)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_cache_target::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_cache_target::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_cache_target`] module"]
69+
pub type SPI_CACHE_TARGET = crate::Reg<spi_cache_target::SPI_CACHE_TARGET_SPEC>;
70+
#[doc = "Control where the cache is mapped (unconfirmed)"]
71+
pub mod spi_cache_target;

‎esp8266/src/dport/dport_ctl.rs

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#[doc = "Register `DPORT_CTL` reader"]
2+
pub type R = crate::R<DPORT_CTL_SPEC>;
3+
#[doc = "Register `DPORT_CTL` writer"]
4+
pub type W = crate::W<DPORT_CTL_SPEC>;
5+
#[doc = "Field `DPORT_CTL_DOUBLE_CLK` reader - "]
6+
pub type DPORT_CTL_DOUBLE_CLK_R = crate::BitReader;
7+
#[doc = "Field `DPORT_CTL_DOUBLE_CLK` writer - "]
8+
pub type DPORT_CTL_DOUBLE_CLK_W<'a, REG> = crate::BitWriter<'a, REG>;
9+
impl R {
10+
#[doc = "Bit 0"]
11+
#[inline(always)]
12+
pub fn dport_ctl_double_clk(&self) -> DPORT_CTL_DOUBLE_CLK_R {
13+
DPORT_CTL_DOUBLE_CLK_R::new((self.bits & 1) != 0)
14+
}
15+
}
16+
#[cfg(feature = "impl-register-debug")]
17+
impl core::fmt::Debug for R {
18+
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19+
f.debug_struct("DPORT_CTL")
20+
.field(
21+
"dport_ctl_double_clk",
22+
&format_args!("{}", self.dport_ctl_double_clk().bit()),
23+
)
24+
.finish()
25+
}
26+
}
27+
#[cfg(feature = "impl-register-debug")]
28+
impl core::fmt::Debug for crate::generic::Reg<DPORT_CTL_SPEC> {
29+
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
30+
core::fmt::Debug::fmt(&self.read(), f)
31+
}
32+
}
33+
impl W {
34+
#[doc = "Bit 0"]
35+
#[inline(always)]
36+
#[must_use]
37+
pub fn dport_ctl_double_clk(&mut self) -> DPORT_CTL_DOUBLE_CLK_W<DPORT_CTL_SPEC> {
38+
DPORT_CTL_DOUBLE_CLK_W::new(self, 0)
39+
}
40+
#[doc = r" Writes raw bits to the register."]
41+
#[doc = r""]
42+
#[doc = r" # Safety"]
43+
#[doc = r""]
44+
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
45+
#[inline(always)]
46+
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
47+
self.bits = bits;
48+
self
49+
}
50+
}
51+
#[doc = "DPORT_CTL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dport_ctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dport_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
52+
pub struct DPORT_CTL_SPEC;
53+
impl crate::RegisterSpec for DPORT_CTL_SPEC {
54+
type Ux = u32;
55+
}
56+
#[doc = "`read()` method returns [`dport_ctl::R`](R) reader structure"]
57+
impl crate::Readable for DPORT_CTL_SPEC {}
58+
#[doc = "`write(|w| ..)` method takes [`dport_ctl::W`](W) writer structure"]
59+
impl crate::Writable for DPORT_CTL_SPEC {
60+
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
61+
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
62+
}
63+
#[doc = "`reset()` method sets DPORT_CTL to value 0"]
64+
impl crate::Resettable for DPORT_CTL_SPEC {
65+
const RESET_VALUE: Self::Ux = 0;
66+
}

‎esp8266/src/dport/edge_int_enable.rs

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#[doc = "Register `EDGE_INT_ENABLE` reader"]
2+
pub type R = crate::R<EDGE_INT_ENABLE_SPEC>;
3+
#[doc = "Register `EDGE_INT_ENABLE` writer"]
4+
pub type W = crate::W<EDGE_INT_ENABLE_SPEC>;
5+
#[doc = "Field `Register` reader - "]
6+
pub type REGISTER_R = crate::FieldReader<u32>;
7+
#[doc = "Field `Register` writer - "]
8+
pub type REGISTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9+
#[doc = "Field `wdt_edge_int_enable` reader - Enable the watchdog timer edge interrupt"]
10+
pub type WDT_EDGE_INT_ENABLE_R = crate::BitReader;
11+
#[doc = "Field `wdt_edge_int_enable` writer - Enable the watchdog timer edge interrupt"]
12+
pub type WDT_EDGE_INT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
13+
#[doc = "Field `timer1_edge_int_enable` reader - Enable the timer1 edge interrupt"]
14+
pub type TIMER1_EDGE_INT_ENABLE_R = crate::BitReader;
15+
#[doc = "Field `timer1_edge_int_enable` writer - Enable the timer1 edge interrupt"]
16+
pub type TIMER1_EDGE_INT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
17+
impl R {
18+
#[doc = "Bits 0:31"]
19+
#[inline(always)]
20+
pub fn register(&self) -> REGISTER_R {
21+
REGISTER_R::new(self.bits)
22+
}
23+
#[doc = "Bit 0 - Enable the watchdog timer edge interrupt"]
24+
#[inline(always)]
25+
pub fn wdt_edge_int_enable(&self) -> WDT_EDGE_INT_ENABLE_R {
26+
WDT_EDGE_INT_ENABLE_R::new((self.bits & 1) != 0)
27+
}
28+
#[doc = "Bit 1 - Enable the timer1 edge interrupt"]
29+
#[inline(always)]
30+
pub fn timer1_edge_int_enable(&self) -> TIMER1_EDGE_INT_ENABLE_R {
31+
TIMER1_EDGE_INT_ENABLE_R::new(((self.bits >> 1) & 1) != 0)
32+
}
33+
}
34+
#[cfg(feature = "impl-register-debug")]
35+
impl core::fmt::Debug for R {
36+
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37+
f.debug_struct("EDGE_INT_ENABLE")
38+
.field("register", &format_args!("{}", self.register().bits()))
39+
.field(
40+
"wdt_edge_int_enable",
41+
&format_args!("{}", self.wdt_edge_int_enable().bit()),
42+
)
43+
.field(
44+
"timer1_edge_int_enable",
45+
&format_args!("{}", self.timer1_edge_int_enable().bit()),
46+
)
47+
.finish()
48+
}
49+
}
50+
#[cfg(feature = "impl-register-debug")]
51+
impl core::fmt::Debug for crate::generic::Reg<EDGE_INT_ENABLE_SPEC> {
52+
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
53+
core::fmt::Debug::fmt(&self.read(), f)
54+
}
55+
}
56+
impl W {
57+
#[doc = "Bits 0:31"]
58+
#[inline(always)]
59+
#[must_use]
60+
pub fn register(&mut self) -> REGISTER_W<EDGE_INT_ENABLE_SPEC> {
61+
REGISTER_W::new(self, 0)
62+
}
63+
#[doc = "Bit 0 - Enable the watchdog timer edge interrupt"]
64+
#[inline(always)]
65+
#[must_use]
66+
pub fn wdt_edge_int_enable(&mut self) -> WDT_EDGE_INT_ENABLE_W<EDGE_INT_ENABLE_SPEC> {
67+
WDT_EDGE_INT_ENABLE_W::new(self, 0)
68+
}
69+
#[doc = "Bit 1 - Enable the timer1 edge interrupt"]
70+
#[inline(always)]
71+
#[must_use]
72+
pub fn timer1_edge_int_enable(&mut self) -> TIMER1_EDGE_INT_ENABLE_W<EDGE_INT_ENABLE_SPEC> {
73+
TIMER1_EDGE_INT_ENABLE_W::new(self, 1)
74+
}
75+
#[doc = r" Writes raw bits to the register."]
76+
#[doc = r""]
77+
#[doc = r" # Safety"]
78+
#[doc = r""]
79+
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
80+
#[inline(always)]
81+
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
82+
self.bits = bits;
83+
self
84+
}
85+
}
86+
#[doc = "EDGE_INT_ENABLE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_int_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_int_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
87+
pub struct EDGE_INT_ENABLE_SPEC;
88+
impl crate::RegisterSpec for EDGE_INT_ENABLE_SPEC {
89+
type Ux = u32;
90+
}
91+
#[doc = "`read()` method returns [`edge_int_enable::R`](R) reader structure"]
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impl crate::Readable for EDGE_INT_ENABLE_SPEC {}
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#[doc = "`write(|w| ..)` method takes [`edge_int_enable::W`](W) writer structure"]
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impl crate::Writable for EDGE_INT_ENABLE_SPEC {
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const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
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}
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#[doc = "`reset()` method sets EDGE_INT_ENABLE to value 0"]
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impl crate::Resettable for EDGE_INT_ENABLE_SPEC {
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const RESET_VALUE: Self::Ux = 0;
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}

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