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geertugeertu
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[WIP] riscv: dts: starfive-jh7100: Convert to JH7100 Clock Generator bindings
Convert the StarFive JH7100 Device Trees to the preliminary JH7100 Clock Generator bindings: - Add placeholders for the OSC0 and OSC1 crystals in the SoC .dtsi file, - Fill the OSC0 and OSC1 crystal clock rates in the board .dts file, - Replace all explicitly-defined fixed-frequency clocks by a single clock controller device node, - Update clock references. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
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‎arch/riscv/boot/dts/starfive/jh7100-starlight.dts‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,14 @@
117117
};
118118
};
119119

120+
&osc0_clk {
121+
clock-frequency = <25000000>;
122+
};
123+
124+
&osc1_clk {
125+
clock-frequency = <27000000>;
126+
};
127+
120128
&qspi {
121129
nor_flash: nor-flash@0 {
122130
compatible = "spi-flash";

‎arch/riscv/boot/dts/starfive/jh7100.dtsi‎

Lines changed: 46 additions & 132 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
33

44
/dts-v1/;
5+
#include <dt-bindings/clock/starfive-jh7100-clkgen.h>
56
#include <dt-bindings/starfive_fb.h>
67
#include <dt-bindings/gpio/gpio.h>
78

@@ -68,120 +69,18 @@
6869
};
6970
};
7071

71-
hfclk: hfclk {
72-
#clock-cells = <0>;
73-
compatible = "fixed-clock";
74-
clock-frequency = <25000000>;
75-
};
76-
77-
rtcclk: rtcclk {
78-
#clock-cells = <0>;
79-
compatible = "fixed-clock";
80-
clock-frequency = <6250000>;
81-
};
82-
83-
i2c0clk: i2c0clk {
84-
#clock-cells = <0>;
85-
compatible = "fixed-clock";
86-
clock-frequency = <49500000>;
87-
};
88-
89-
i2c2clk: i2c2clk {
90-
#clock-cells = <0>;
91-
compatible = "fixed-clock";
92-
clock-frequency = <50000000>;
93-
};
94-
95-
axiclk: axiclk {
96-
#clock-cells = <0>;
97-
compatible = "fixed-clock";
98-
clock-frequency = <500000000>;
99-
};
100-
101-
ahb0clk: ahb0clk {
102-
#clock-cells = <0>;
103-
compatible = "fixed-clock";
104-
clock-frequency = <250000000>;
105-
};
106-
107-
ahb2clk: ahb2clk {
108-
#clock-cells = <0>;
109-
compatible = "fixed-clock";
110-
clock-frequency = <125000000>;
111-
};
112-
113-
apb1clk: apb1clk {
114-
#clock-cells = <0>;
115-
compatible = "fixed-clock";
116-
clock-frequency = <125000000>;
117-
};
118-
119-
apb2clk: apb2clk {
120-
#clock-cells = <0>;
121-
compatible = "fixed-clock";
122-
clock-frequency = <125000000>;
123-
};
124-
125-
jpuclk: jpuclk {
126-
#clock-cells = <0>;
127-
compatible = "fixed-clock";
128-
clock-frequency = <333333333>;
129-
};
130-
131-
vpuclk: vpuclk {
132-
#clock-cells = <0>;
133-
compatible = "fixed-clock";
134-
clock-frequency = <400000000>;
135-
};
136-
137-
gmacclk: gmacclk {
138-
#clock-cells = <0>;
72+
osc0_clk: osc0 {
13973
compatible = "fixed-clock";
140-
clock-frequency = <25000000>;
141-
};
142-
143-
qspi_clk: qspi-clk {
14474
#clock-cells = <0>;
145-
compatible = "fixed-clock";
146-
clock-frequency = <50000000>;
75+
/* This value must be overridden by the board */
76+
clock-frequency = <0>;
14777
};
14878

149-
uartclk: uartclk {
150-
#clock-cells = <0>;
79+
osc1_clk: osc1 {
15180
compatible = "fixed-clock";
152-
clock-frequency = <100000000>;
153-
};
154-
155-
hs_uartclk: hs_uartclk {
15681
#clock-cells = <0>;
157-
compatible = "fixed-clock";
158-
clock-frequency = <74250000>;
159-
};
160-
161-
dwmmc_biuclk: dwmmc_biuclk {
162-
#clock-cells = <0>;
163-
compatible = "fixed-clock";
164-
clock-frequency = <100000000>;
165-
};
166-
167-
/*
168-
dwmmc_ciuclk: dwmmc_ciuclk {
169-
#clock-cells = <0>;
170-
compatible = "fixed-clock";
171-
clock-frequency = <100000000>;
172-
};
173-
*/
174-
175-
spiclk: spiclk {
176-
#clock-cells = <0>;
177-
compatible = "fixed-clock";
178-
clock-frequency = <50000000>;
179-
};
180-
181-
pwmclk: pwmclk {
182-
#clock-cells = <0>;
183-
compatible = "fixed-clock";
184-
clock-frequency = <125000000>;
82+
/* This value must be overridden by the board */
83+
clock-frequency = <0>;
18584
};
18685

18786
soc {
@@ -248,13 +147,22 @@
248147
riscv,ndev = <127>;
249148
};
250149

150+
clkgen: clock-controller@11800000 {
151+
compatible = "starfive,jh7100-clkgen";
152+
reg = <0x0 0x11800000 0x0 0x10000>;
153+
clocks = <&osc0_clk>, <&osc1_clk>;
154+
clock-names = "osc0", "osc1";
155+
#clock-cells = <1>;
156+
};
157+
251158
uart0: serial@11870000 {
252159
compatible = "snps,dw-apb-uart";
253160
interrupts = <92>;
254161
reg = <0x0 0x11870000 0x0 0x10000>;
255162
reg-io-width = <4>;
256163
reg-shift = <2>;
257-
clocks = <&hs_uartclk>, <&apb1clk>;
164+
clocks = <&clkgen JH7100_CLK_HS_UART>,
165+
<&clkgen JH7100_CLK_APB1>;
258166
clock-names = "baudclk", "apb_pclk";
259167
current-clock = <74250000>;
260168
current-speed = <115200>;
@@ -267,7 +175,8 @@
267175
reg = <0x0 0x11880000 0x0 0x10000>;
268176
reg-io-width = <4>;
269177
reg-shift = <2>;
270-
clocks = <&hs_uartclk>, <&apb1clk>;
178+
clocks = <&clkgen JH7100_CLK_HS_UART>,
179+
<&clkgen JH7100_CLK_APB1>;
271180
clock-names = "baudclk", "apb_pclk";
272181
current-clock = <74250000>;
273182
current-speed = <115200>;
@@ -280,7 +189,8 @@
280189
reg = <0x0 0x12430000 0x0 0x10000>;
281190
reg-io-width = <4>;
282191
reg-shift = <2>;
283-
clocks = <&uartclk>, <&apb2clk>;
192+
clocks = <&clkgen JH7100_CLK_UART>,
193+
<&clkgen JH7100_CLK_APB2>;
284194
clock-names = "baudclk", "apb_pclk";
285195
current-clock = <100000000>;
286196
current-speed = <115200>;
@@ -293,7 +203,8 @@
293203
reg = <0x0 0x12440000 0x0 0x10000>;
294204
reg-io-width = <4>;
295205
reg-shift = <2>;
296-
clocks = <&uartclk>, <&apb2clk>;
206+
clocks = <&clkgen JH7100_CLK_UART>,
207+
<&clkgen JH7100_CLK_APB2>;
297208
clock-names = "baudclk", "apb_pclk";
298209
current-clock = <100000000>;
299210
current-speed = <115200>;
@@ -303,7 +214,8 @@
303214
dma2p: dma-controller@100b0000 {
304215
compatible = "snps,axi-dma-1.01a";
305216
reg = <0x0 0x100b0000 0x0 0x10000>;
306-
clocks = <&axiclk>, <&ahb0clk>;
217+
clocks = <&clkgen JH7100_CLK_AXI>,
218+
<&clkgen JH7100_CLK_AHB0>;
307219
clock-names = "core-clk", "cfgr-clk";
308220
interrupts = <2>;
309221
#dma-cells = <1>;
@@ -319,7 +231,8 @@
319231
dma1p: dma-controller@10500000 {
320232
compatible = "snps,axi-dma-1.01a";
321233
reg = <0x0 0x10500000 0x0 0x10000>;
322-
clocks = <&axiclk>, <&ahb0clk>;
234+
clocks = <&clkgen JH7100_CLK_AXI>,
235+
<&clkgen JH7100_CLK_AHB0>;
323236
clock-names = "core-clk", "cfgr-clk";
324237
interrupts = <1>;
325238
#dma-cells = <1>;
@@ -362,7 +275,7 @@
362275
compatible = "snps,designware-i2c";
363276
reg = <0x0 0x118b0000 0x0 0x10000>;
364277
interrupts = <96>;
365-
clocks = <&i2c0clk>;
278+
clocks = <&clkgen JH7100_CLK_I2C0>;
366279
clock-frequency = <100000>;
367280
i2c-sda-hold-time-ns = <300>;
368281
i2c-sda-falling-time-ns = <500>;
@@ -378,7 +291,7 @@
378291
compatible = "snps,designware-i2c";
379292
reg = <0x0 0x118c0000 0x0 0x10000>;
380293
interrupts = <97>;
381-
clocks = <&i2c0clk>;
294+
clocks = <&clkgen JH7100_CLK_I2C0>;
382295
clock-frequency = <400000>;
383296
i2c-sda-hold-time-ns = <300>;
384297
i2c-sda-falling-time-ns = <100>;
@@ -394,7 +307,7 @@
394307
compatible = "snps,designware-i2c";
395308
reg = <0x0 0x12450000 0x0 0x10000>;
396309
interrupts = <74>;
397-
clocks = <&i2c2clk>;
310+
clocks = <&clkgen JH7100_CLK_I2C2>;
398311
clock-frequency = <100000>;
399312
i2c-sda-hold-time-ns = <300>;
400313
i2c-sda-falling-time-ns = <500>;
@@ -407,7 +320,7 @@
407320
compatible = "starfive,vic-rng";
408321
reg = <0x0 0x118d0000 0x0 0x10000>;
409322
interrupts = <98>;
410-
clocks = <&hfclk>;
323+
clocks = <&clkgen JH7100_CLK_HF>;
411324
};
412325

413326
crypto: crypto@100d0000 {
@@ -416,7 +329,7 @@
416329
<0x0 0x11800234 0x0 0xc>;
417330
reg-names = "secmem", "secclk";
418331
interrupts = <31>;
419-
clocks = <&hfclk>;
332+
clocks = <&clkgen JH7100_CLK_HF>;
420333
};
421334

422335
/* gmac device configuration */
@@ -437,7 +350,7 @@
437350
snps,perfect-filter-entries = <128>;
438351
rx-fifo-depth = <32768>;
439352
tx-fifo-depth = <16384>;
440-
clocks = <&gmacclk>;
353+
clocks = <&clkgen JH7100_CLK_GMAC>;
441354
clock-names = "stmmaceth";
442355
snps,fixed-burst;
443356
snps,no-pbl-x8 = <1>;
@@ -459,7 +372,7 @@
459372
reg = <0x0 0x11900000 0x0 0x300>;
460373
memory-region = <&jpu_reserved>;
461374
interrupts = <24>;
462-
clocks = <&jpuclk>;
375+
clocks = <&clkgen JH7100_CLK_JPU>;
463376
clock-names = "jpege";
464377
reg-names = "control";
465378
status = "okay";
@@ -470,7 +383,7 @@
470383
reg = <0 0x118f0000 0 0x10000>;
471384
//memory-region = <&vpu_reserved>;
472385
interrupts = <23>;
473-
clocks = <&vpuclk>;
386+
clocks = <&clkgen JH7100_CLK_VPU>;
474387
clock-names = "vcodec";
475388
status = "okay";
476389
};
@@ -479,7 +392,7 @@
479392
compatible = "cm,cm521-vpu";
480393
reg = <0x0 0x118e0000 0x0 0x4000>;
481394
interrupts = <26>;
482-
clocks = <&vpuclk>;
395+
clocks = <&clkgen JH7100_CLK_VPU>;
483396
clock-names = "vcodec";
484397
reg-names = "control";
485398
};
@@ -489,7 +402,7 @@
489402
reg = <0x0 0x12490000 0x0 0x10000>;
490403
reg-names = "control";
491404
sifive,approx-period = <100000000>;
492-
clocks = <&pwmclk>;
405+
clocks = <&clkgen JH7100_CLK_PWM>;
493406
#pwm-cells = <3>;
494407
sifive,npwm = <8>;
495408

@@ -502,7 +415,7 @@
502415
reg = <0x0 0x11860000 0x0 0x10000>,
503416
<0x0 0x20000000 0x0 0x20000000>;
504417
interrupts = <3>;
505-
clocks = <&qspi_clk>;
418+
clocks = <&clkgen JH7100_CLK_QSPI>;
506419
cdns,fifo-depth = <256>;
507420
cdns,fifo-width = <4>;
508421
cdns,trigger-address = <0x0>;
@@ -517,7 +430,7 @@
517430
#size-cells = <0>;
518431
interrupts = <FIXME>;
519432
reg = <0x0 0x11890000 0x0 0x10000>;
520-
clocks = <&spiclk>;
433+
clocks = <&clkgen JH7100_CLK_SPI>;
521434
status = "disabled";
522435
};
523436

@@ -527,7 +440,7 @@
527440
#size-cells = <0>;
528441
interrupts = <FIXME>;
529442
reg = <0x0 0x118a0000 0x0 0x10000>;
530-
clocks = <&spiclk>;
443+
clocks = <&clkgen JH7100_CLK_SPI>;
531444
status = "disabled";
532445
};
533446
*/
@@ -538,7 +451,7 @@
538451
#size-cells = <0>;
539452
interrupts = <70>;
540453
reg = <0x0 0x12410000 0x0 0x10000>;
541-
clocks = <&spiclk>;
454+
clocks = <&clkgen JH7100_CLK_SPI>;
542455
status = "disabled";
543456
};
544457

@@ -548,7 +461,7 @@
548461
<0x10 0x72000000 0x0 0x00001000>,
549462
<0x10 0x72001000 0x0 0x00fff000>,
550463
<0x0 0x124b0000 0x0 0x00010000>;
551-
clocks = <&hfclk>;
464+
clocks = <&clkgen JH7100_CLK_HF>;
552465
firmware-name = "vp6_elf";
553466
dsp-irq = <19 20>;
554467
dsp-irq-src = <0x20 0x21>;
@@ -567,7 +480,7 @@
567480
compatible = "snps,dw-mshc";
568481
reg = <0x0 0x10000000 0x0 0x10000>;
569482
interrupts = <4>;
570-
clocks = <&dwmmc_biuclk>;
483+
clocks = <&clkgen JH7100_CLK_DWMMC_BIU>;
571484
clock-names = "biu";
572485
clock-frequency = <100000000>;
573486
data-addr = <0>;
@@ -580,7 +493,7 @@
580493
compatible = "snps,dw-mshc";
581494
reg = <0x0 0x10010000 0x0 0x10000>;
582495
interrupts = <5>;
583-
clocks = <&dwmmc_biuclk>;
496+
clocks = <&clkgen JH7100_CLK_DWMMC_BIU>;
584497
clock-names = "biu";
585498
clock-frequency = <100000000>;
586499
data-addr = <0>;
@@ -603,7 +516,8 @@
603516
<0x0 0x12260000 0x0 0x10000>;
604517
reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
605518
memory-region = <&sffb_reserved>;
606-
clocks = <&uartclk>, <&apb2clk>;
519+
clocks = <&clkgen JH7100_CLK_UART>,
520+
<&clkgen JH7100_CLK_APB2>;
607521
clock-names = "baudclk", "apb_pclk";
608522
status = "okay";
609523
ddr-format = <WIN_FMT_RGB565>;/*LCDC win_format*/

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