Add more documentation, new feactures and fix bugs.

Author: ericsonj

.gitignore

@@ -1 +1,2 @@
 target/
+launch-linux/

README.md

@@ -1,10 +1,40 @@
 # Verilog Format
 
-Java console aplication for verilog formatter.
+Console application for apply format to verilog file.
 
-![sample](images/verilog-format.gif) 
+![sample](images/verilog-format.gif)
 
-## How to use (Linux)
+## How to use
+
+Application options:
+
+```
+usage: [java -jar verilog-format.jar|./verilog-format|verilog-format.exe]
+       [-f <pathname>] [-h] [-p] [-s <verilog-format.properties>] [-v]
+ -f,--format <pathname>                      verilog file
+ -h,--help                                   print this message
+ -p,--print                                  print file formated
+ -s,--settings <verilog-format.properties>   settings config
+ -v,--version                                verilog-format version
+```
+
+## Examples
+
+```sh
+## Print input_file.v formatted
+$ ./verilog-format -p -f input_file.v -s verilog-format.properties 
+
+## Format input_file.v
+$ ./verilog-format -f input_file.v -s verilog-format.properties
+
+## Format input_file.v
+## If .verilog-format.properties exist in project folder, this is used,
+## otherwise default setting is used..
+$ ./verilog-format -f input_file.v
+
+```
+
+## Install in Linux
 
 1. Clone repository.
 
@@ -28,7 +58,7 @@ Java console aplication for verilog formatter.
 
     `$ sudo cp /opt/verilog-format/verilog-format /usr/bin/`
 
-## How to use (Windows)
+## Install in Windows
 
 1. Clone repository or download [verilog-format-WIN.zip](bin/verilog-format-WIN.zip)  
 
@@ -40,4 +70,148 @@ For build de project, Maven is needed.
 
 `$ cd verilog-format`  
 `$ mvn clean package`  
-`$ ls target/`  
+`$ ls target/` 
+
+## Verilog-Format Style Options
+
+This options are setting in `.verilog-format.properties` file.
+
+### Example
+
+```properties
+## File .verilog-format.properties
+IndentWidth=4
+IndentType=space
+SpacesBeforeTrailingComments=0
+SpacesAfterTrailingComments=0
+AlignLineComments=true
+AlignNoBlockingAssignments=true
+AlignBlockingAssignments=true
+SpacesInParentheses=false
+SpacesInSquareBrackets=false
+```
+
+---
+### IndentWidth=[number]
+
+```verilog
+// IndentWidth=4  #(default)
+always @(posedge clk)
+    if (load == 1)
+        bitc <= 0;
+    else if (load == 0 && clk_baud == 1)
+        bitc <= bitc + 1;
+
+// IndentWidth=1
+always @(posedge clk)
+ if (load == 1)
+  bitc <= 0;
+ else if (load == 0 && clk_baud == 1)
+  bitc <= bitc + 1;
+```
+--- 
+### IndentType=[space|tab]
+```verilog
+// IndentType=space  #(default)
+always @(posedge clk)
+    if (load == 1)
+        bitc <= 0;
+    else if (load == 0 && clk_baud == 1)
+        bitc <= bitc + 1;
+
+// IndentType=tab  #  not recommended yet
+always @(posedge clk)
+<tab>if (load == 1)
+<tab><tab>bitc <= 0;
+<tab>else if (load == 0 && clk_baud == 1)
+<tab><tab>bitc <= bitc + 1;
+```
+---
+### SpacesInParentheses=[true|false]
+```verilog
+// SpacesInParentheses=false  #(default)
+always @(posedge clk)
+    if (load == 1)
+
+// SpacesInParentheses=true
+always @( posedge clk )
+    if ( load == 1 )
+```
+---
+
+### SpacesInSquareBrackets=[true|false]
+```verilog
+// SpacesInSquareBrackets=false  #(default)
+reg [DW-1:0] rom [0:NPOS-1];
+
+always @(posedge clk) begin
+    data <= rom[addr];
+end
+
+// SpacesInSquareBrackets=true
+reg [ DW-1:0 ] rom [ 0:NPOS-1 ];
+    
+always @(posedge clk) begin
+    data <= rom[ addr ];
+```
+---
+### AlignBlockingAssignments=[true|false]
+```verilog
+// AlignBlockingAssignments=true  #(default)
+assign load    = (state == START) ? 1 : 0;
+assign baud_en = (state == IDLE) ? 0 : 1;
+
+// AlignBlockingAssignments=false
+assign load = (state == START) ? 1 : 0;
+assign baud_en = (state == IDLE) ? 0 : 1;
+
+```
+---
+### AlignNoBlockingAssignments=[true|false]
+```verilog
+// AlignNoBlockingAssignments=true  #(default)
+state_ts   <= IDLE;
+state_pad  <= IDLE;
+state_wait <= IDLE;
+
+// AlignNoBlockingAssignments=false
+state_ts <= IDLE;
+state_pad <= IDLE;
+state_wait <= IDLE;
+```
+---
+### AlignLineComments=[true|false]
+```verilog
+// AlignLineComments=false  #(default)
+always @(posedge clk) // always
+    if (load == 1)  // if
+        bitc <= 0; //
+    else if (load == 0 && clk_baud == 1) // else if
+        bitc <= bitc + 1; //
+
+// AlignLineComments=true
+always @(posedge clk)                    // always
+    if (load == 1)                       // if
+        bitc <= 0;                       //
+    else if (load == 0 && clk_baud == 1) // else if
+        bitc <= bitc + 1;                //
+```
+---
+### SpacesBeforeTrailingComments=[number]
+```verilog
+// SpacesBeforeTrailingComments=1  #(default)
+localparam IDLE  = 0; //IDLE
+
+// SpacesBeforeTrailingComments=0
+localparam IDLE  = 0;//IDLE
+```
+---
+### SpacesAfterTrailingComments=[number]
+```verilog
+// SpacesAfterTrailingComments=0  #(default)
+localparam IDLE  = 0; //IDLE
+
+// SpacesAfterTrailingComments=3
+localparam IDLE  = 0; //   IDLE
+```
+---

bin/verilog-format-LINUX.zip

@@ -0,0 +1,15 @@
+#!/bin/sh
+
+#MOV TO BIN
+cd bin/
+
+# BUILD FOR LINUX
+cp ../target/*-full.jar verilog-format.jar
+cp ../launch-linux/verilog-format .
+zip verilog-format-LINUX.zip verilog-format.jar verilog-format
+rm verilog-format.jar verilog-format
+
+# BUILD FOR WIN
+cp ../target/verilog-format.exe .
+zip verilog-format-WIN.zip verilog-format.exe
+rm verilog-format.exe

bin/verilog-format-WIN.zip

@@ -3,7 +3,7 @@
     <modelVersion>4.0.0</modelVersion>
     <groupId>net.ericsonj</groupId>
     <artifactId>verilog-format</artifactId>
-    <version>1.0.0</version>
+    <version>1.0.1</version>
     <packaging>jar</packaging>
     <properties>
         <project.build.sourceEncoding>UTF-8</project.build.sourceEncoding>

build-dist

@@ -73,7 +73,7 @@ public FormatSetting getSetting() {
     }
 
     public int getSpacesAfterTrailingComments() {
-        return this.setting.getIntValue(SPACES_AFTER_TRAILING_COMMENTS, 1);
+        return this.setting.getIntValue(SPACES_AFTER_TRAILING_COMMENTS, 0);
     }
 
     public int getSpacesBeforeTrailingComments() {

images/verilog-format.gif

@@ -14,12 +14,14 @@
  */
 public class FormatSetting {
 
+    public static final String FILE_PROP = "verilog-format.properties";
+
     private File file;
     private Properties prop;
     private boolean filePresent;
 
     public FormatSetting() {
-        this(new File("verilog-format.properties"));
+        this(new File(FILE_PROP));
     }
 
     public FormatSetting(File file) {
@@ -46,13 +48,13 @@ public FormatSetting(File file) {
     public String getStringValue(String key, String defaultValue) {
         return prop.getProperty(key, defaultValue);
     }
-    
+
     public int getIntValue(String key, int defaultValue) {
         int value = Integer.parseInt(prop.getProperty(key, String.valueOf(defaultValue)));
         return value;
     }
-    
-    public boolean getBooleanValue(String key, boolean defaultValue){
+
+    public boolean getBooleanValue(String key, boolean defaultValue) {
         String value = getStringValue(key, String.valueOf(defaultValue));
         return Boolean.valueOf(value);
     }

pom.xml

@@ -8,6 +8,6 @@
  */
 public class Global {
 
-    public static final String VERSION = "1.0.0";
+    public static final String VERSION = "1.0.1";
 
 }