Add block comment statement for testing

Author: ericsonj

nbactions.xml

@@ -10,7 +10,7 @@
                 <goal>org.codehaus.mojo:exec-maven-plugin:1.5.0:exec</goal>
             </goals>
             <properties>
-                <exec.args>-classpath %classpath net.ericsonj.verilog.VerilogFormat -p -f verilog/module.v</exec.args>
+                <exec.args>-classpath %classpath net.ericsonj.verilog.VerilogFormat -f verilog/genrom.v</exec.args>
                 <exec.executable>java</exec.executable>
                 <exec.workingdir>/home/ericson/PROJECTS/JAVA/MAVEN/verilog-format</exec.workingdir>
             </properties>
@@ -25,7 +25,7 @@
                 <goal>org.codehaus.mojo:exec-maven-plugin:1.5.0:exec</goal>
             </goals>
             <properties>
-                <exec.args>-agentlib:jdwp=transport=dt_socket,server=n,address=${jpda.address} -classpath %classpath net.ericsonj.verilog.VerilogFormat -p -f verilog/module.v</exec.args>
+                <exec.args>-agentlib:jdwp=transport=dt_socket,server=n,address=${jpda.address} -classpath %classpath net.ericsonj.verilog.VerilogFormat -f verilog/genrom.v</exec.args>
                 <exec.executable>java</exec.executable>
                 <jpda.listen>true</jpda.listen>
                 <exec.workingdir>/home/ericson/PROJECTS/JAVA/MAVEN/verilog-format</exec.workingdir>
@@ -41,7 +41,7 @@
                 <goal>org.codehaus.mojo:exec-maven-plugin:1.5.0:exec</goal>
             </goals>
             <properties>
-                <exec.args>-classpath %classpath net.ericsonj.verilog.VerilogFormat -p -f verilog/module.v</exec.args>
+                <exec.args>-classpath %classpath net.ericsonj.verilog.VerilogFormat -f verilog/genrom.v</exec.args>
                 <exec.executable>java</exec.executable>
                 <exec.workingdir>/home/ericson/PROJECTS/JAVA/MAVEN/verilog-format</exec.workingdir>
             </properties>

src/main/java/net/ericsonj/verilog/IndentationStyle.java

@@ -2,6 +2,7 @@
 
 import java.util.LinkedList;
 import net.ericsonj.verilog.statements.Always;
+import net.ericsonj.verilog.statements.BlockComment;
 import net.ericsonj.verilog.statements.Case;
 import net.ericsonj.verilog.statements.For;
 import net.ericsonj.verilog.statements.Forever;
@@ -24,6 +25,7 @@ public class IndentationStyle implements StyleImp {
     public IndentationStyle() {
         this.indents = new LinkedList<>();
 
+        this.indents.add(new BlockComment());
         this.indents.add(new For());
         this.indents.add(new While());
         this.indents.add(new Repeat());

src/main/java/net/ericsonj/verilog/statements/BlockComment.java

@@ -0,0 +1,53 @@
+package net.ericsonj.verilog.statements;
+
+import net.ericsonj.verilog.FileFormat;
+
+/**
+ *
+ * @author Ericson Joseph <ericsonjoseph@gmail.com>
+ *
+ * Create on Feb 28, 2019 12:42:31 AM
+ */
+public class BlockComment extends AbstractStatement<BlockCommentState> {
+
+    @Override
+    public boolean isInitStatement(FileFormat format, String line) {
+        return line.matches("/\\*.*");
+    }
+
+    @Override
+    public BlockCommentState getInitStateElement(FileFormat format, String liine) {
+        BlockCommentState state = new BlockCommentState();
+        state.setBaseIndent(format.getCountIndent());
+        state.setState(BlockCommentState.STATE.INIT);
+        return state;
+    }
+
+    @Override
+    public Class<BlockCommentState> getStateType() {
+        return BlockCommentState.class;
+    }
+
+    @Override
+    public String stateMachine(FileFormat format, BlockCommentState state, String line) {
+        switch (state.getState()) {
+            case INIT:
+                if (line.matches("/\\*.*") && line.matches(".*\\*/")) {
+                    format.states.poll();
+                } else if (line.matches("/\\*.*")) {
+                    state.setState(BlockCommentState.STATE.COMMENT);
+                    return indent(format, line);
+                }
+                break;
+            case COMMENT:
+                if (line.matches(".*\\*/")) {
+                    format.states.poll();
+                }
+                return indent(format, " " + line);
+            default:
+                throw new AssertionError(state.getState().name());
+        }
+        return null;
+    }
+
+}

src/main/java/net/ericsonj/verilog/statements/BlockCommentState.java

@@ -0,0 +1,33 @@
+package net.ericsonj.verilog.statements;
+
+import net.ericsonj.verilog.StatementState;
+
+/**
+ *
+ * @author Ericson Joseph <ericsonjoseph@gmail.com>
+ *
+ * Create on Feb 28, 2019 12:43:30 AM
+ */
+public class BlockCommentState extends StatementState {
+
+    public enum STATE {
+        INIT,
+        COMMENT
+    }
+
+    private BlockCommentState.STATE state;
+
+    public BlockCommentState() {
+        super("blockcomment", 0);
+        this.state = STATE.INIT;
+    }
+
+    public STATE getState() {
+        return state;
+    }
+
+    public void setState(STATE state) {
+        this.state = state;
+    }
+
+}

verilog/genrom.v

@@ -1,17 +1,18 @@
 
 /**
-* File:   genrom.v
-* Author: Ericson Joseph
-*
-* Created on January 28, 2019,  8:15 PM
-*/
+ * File:   genrom.v
+ * Author: Ericson Joseph
+ *
+ * Created on January 28, 2019,  8:15 PM
+ */
 
 module genrom #(parameter AW = 5,
                 parameter DW = 4)
                (input clk,
                 input wire [AW-1:0] addr,
                 output reg [DW-1:0] data);
 
+    
     parameter ROMFILE = "rom1.list";
 
     localparam NPOS = 2 ** AW;
@@ -26,4 +27,5 @@ module genrom #(parameter AW = 5,
         $readmemh(ROMFILE, rom);
     end
 
+    
 endmodule