Generic Xtensa LX port

Initial Cadence patch

Author: ianstcdns

README

@@ -121,7 +121,7 @@ Debug targets
 ARM: AArch64, ARM11, ARM7, ARM9, Cortex-A/R (v7-A/R), Cortex-M (ARMv{6/7/8}-M),
 FA526, Feroceon/Dragonite, XScale.
 ARCv2, AVR32, DSP563xx, DSP5680xx, EnSilica eSi-RISC, EJTAG (MIPS32, MIPS64),
-Intel Quark, LS102x-SAP, NDS32, RISC-V, ST STM8.
+Espressif, Intel Quark, LS102x-SAP, NDS32, RISC-V, ST STM8, Xtensa.
 
 Flash drivers
 -------------

doc/openocd.texi

@@ -4895,6 +4895,7 @@ compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
 @item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
 @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
 The current implementation supports eSi-32xx cores.
+@item @code{esp32s2} -- this is a single-core SoC with Xtensa core.
 @item @code{fa526} -- resembles arm920 (w/o Thumb).
 @item @code{feroceon} -- resembles arm926.
 @item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
@@ -4933,6 +4934,7 @@ And two debug interfaces cores:
 @item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
 @item @code{xscale} -- this is actually an architecture,
 not a CPU type. It is based on the ARMv5 architecture.
+@item @code{xtensa} -- this is a generic Cadence/Tensilica Xtensa core.
 @end itemize
 @end deffn
 
@@ -10964,33 +10966,158 @@ OpenOCD supports debugging STM8 through the STMicroelectronics debug
 protocol SWIM, @pxref{swimtransport,,SWIM}.
 
 @section Xtensa Architecture
-Xtensa processors are based on a modular, highly flexible 32-bit RISC architecture
-that can easily scale from a tiny, cache-less controller or task engine to a high-performance
-SIMD/VLIW DSP provided by Cadence.
-@url{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip/tensilica-xtensa-controllers-and-extensible-processors.html}.
 
-OpenOCD supports generic Xtensa processors implementation which can be customized by
-simply providing vendor-specific core configuration which controls every configurable
+Xtensa is a highly-customizable, user-extensible microprocessor and DSP 
+architecture for complex embedded systems provided by Cadence Design 
+Systems, Inc.  See the 
+@uref{https://www.cadence.com/en_US/home/tools/ip/tensilica-ip.html, Tensilica IP}
+website for additional information and documentation.
+
+OpenOCD supports generic Xtensa processor implementations which can be customized by
+providing a core-specific configuration file which describes every enabled 
 Xtensa architecture option, e.g. number of address registers, exceptions, reduced
-size instructions support, memory banks configuration etc. Also OpenOCD supports SMP
-configurations for Xtensa processors with any number of cores and allows to configure
-their debug signals interconnection (so-called "break/stall networks") which control how
-debug signals are distributed among cores. Xtensa "break networks" are compatible with
-ARM's Cross Trigger Interface (CTI). For debugging code on Xtensa chips OpenOCD
-uses JTAG protocol. Currently OpenOCD implements several Epsressif Xtensa-based chips of
+size instructions support, memory banks configuration etc.  OpenOCD also supports SMP
+configurations for Xtensa processors with any number of cores and allows configuring
+their debug interconnect (termed "break/stall networks"), which control how debug
+signals are distributed among cores.  Xtensa "break networks" are compatible with
+ARM's Cross Trigger Interface (CTI).  OpenOCD implements both generic Xtensa targets
+as well as several Epsressif Xtensa-based chips from the 
 @uref{https://www.espressif.com/en/products/socs, ESP32 family}.
 
-@subsection General Xtensa Commands
+OCD sessions for Xtensa processor and DSP targets are accessed via the Xtensa
+Debug Module (XDM), which provides external connectivity either through a 
+traditional JTAG interface or an ARM DAP interface.  If used, the DAP interface
+can control Xtensa targets through JTAG or SWD probes.
+
+@subsection Xtensa Core Configuration
+
+Due to the high level of configurability in Xtensa cores, the Xtensa target
+configuration is composed of two categories: 
+
+@enumerate
+@item Base Xtensa support common to all core configurations, and
+@item Core-specific support as configured for individual cores.
+@end enumerate
+
+All common Xtensa support is built into the OpenOCD Xtensa target layer and 
+is enabled through a combination of TCL scripts: the target-specific 
+@code{target/xtensa.cfg} and a board-specific @code{board/xtensa-*.cfg}, 
+similar to other target architectures.
+
+Importantly, core-specific configuration information must be provided by 
+the user, and takes the form of an @code{xtensa-core-XXX.cfg} TCL script that
+defines the core's configurable features through a series of Xtensa 
+configuration commands (detailed below).
+
+This core-specific @code{xtensa-core-XXX.cfg} file is typically either:
+
+@itemize @bullet
+@item Located within the Xtensa core configuration build as 
+@code{src/config/xtensa-core-openocd.cfg}, or 
+@item Generated by running the command @code{xt-gdb --dump-oocd-config} 
+from the Xtensa processor tool-chain's command-line tools.
+@end itemize
+
+NOTE: @code{xtensa-core-XXX.cfg} must match the target Xtensa hardware 
+connected to OpenOCD.
+
+Some example Xtensa configurations are bundled with OpenOCD for reference:
+@itemize @bullet
+@item Cadence Palladium VDebug emulation target.  The user can combine their 
+@code{xtensa-core-XXX.cfg} with the provided
+@code{board/xtensa-palladium-vdebug.cfg} to debug an emulated Xtensa RTL design.
+@item NXP MIMXRT685-EVK evaluation kit.  The relevant configuration files are 
+@code{board/xtensa-rt685-jlink.cfg} and @code{board/xtensa-core-nxp_rt600.cfg}.
+Additional information is provided by 
+@uref{https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt600-evaluation-kit:MIMXRT685-EVK,
+NXP}.
+@end itemize
+
+@subsection Xtensa Configuration Commands
+
+@deffn {Command} {xtensa xtdef} (@option{LX}|@option{NX})
+Configure the Xtensa target architecture.  Currently, Xtensa support is limited
+to LX6, LX7, and NX cores.
+@end deffn
+
+@deffn {Command} {xtensa xtopt} option value
+Configure Xtensa target options that are relevant to the debug subsystem.
+@var{option} is one of: @option{bigendian}, @option{arnum}, @option{windowed}, 
+@option{cpenable}, @option{exceptions}, @option{intnum}, @option{hipriints}, 
+@option{excmlevel}, @option{intlevels}, @option{debuglevel}, 
+@option{ibreaknum}, or @option{dbreaknum}.  @var{value} is an integer with
+the exact range determined by each particular option.  
+
+NOTE: Some options are specific to Xtensa LX or Xtensa NX architecture, while 
+others may be common to both but have different valid ranges.
+@end deffn
+
+@deffn {Command} {xtensa xtmem} (@option{iram}|@option{dram}|@option{sram}|@option{irom}|@option{drom}|@option{srom}) baseaddr bytes
+Configure Xtensa target memory.  Memory type determines access rights, 
+where RAMs are read/write while ROMs are read-only.  @var{baseaddr} and
+@var{bytes} are both integers, typically hexadecimal and decimal, respectively.
+@end deffn
+
+@deffn {Command} {xtensa xtmem} (@option{icache}|@option{dcache}) linebytes cachebytes ways [writeback]
+Configure Xtensa processor cache.  All parameters are required except for
+the optional @option{writeback} parameter; all are integers.
+@end deffn
+
+@deffn {Command} {xtensa xtmpu} numfgseg minsegsz lockable execonly
+Configure an Xtensa Memory Protection Unit (MPU).  MPUs can restrict access
+and/or control cacheability of specific address ranges, but are lighter-weight
+than a full traditional MMU.  All parameters are required; all are integers.
+@end deffn
+
+@deffn {Command} {xtensa xtmmu} numirefillentries numdrefillentries
+(Xtensa-LX only) Configure an Xtensa Memory Management Unit (MMU).  Both 
+parameters are required; both are integers.
+@end deffn
+
+@deffn {Command} {xtensa xtregs} numregs
+Configure the total number of registers for the Xtensa core.  Configuration
+logic expects to subsequently process this number of @code{xtensa xtreg} 
+definitions.  @var{numregs} is an integer.
+@end deffn
+
+@deffn {Command} {xtensa xtregfmt} (@option{sparse}|@option{contiguous}) [general]
+Configure the type of register map used by GDB to access the Xtensa core.  
+Generic Xtensa tools (e.g. xt-gdb) require @option{sparse} mapping (default) while 
+Espressif tools expect @option{contiguous} mapping.  Contiguous mapping takes an
+additional, optional integer parameter @option{general}, which specifies the number 
+of general registers used in handling g/G packets.
+@end deffn
+
+@deffn {Command} {xtensa xtreg} name offset
+Configure an Xtensa core register.  All core registers are 32 bits wide,
+while TIE and user registers may have variable widths.  @var{name} is a 
+character string identifier while @var{offset} is a hexadecimal integer.
+@end deffn
+
+@subsection Xtensa Debug Module Configuration Commands
+
+@deffn {Command} {xtensa dm offset} value
+Configure the Xtensa Debug Module (DM) to apply a fixed offset when accessing
+debug registers behind a DAP interface (typically over APB).  The offset
+value must be aligned to the size of the DM register file, typically 16KB.
+@end deffn
+
+@subsection Xtensa Operation Commands
+
+@deffn {Command} {xtensa maskisr} (@option{on}|@option{off})
+(Xtensa-LX only) Mask or unmask Xtensa interrupts during instruction step.  
+When masked, an interrupt that occurs during a step operation is handled and 
+its ISR is executed, with the user's debug session returning after potentially 
+executing many instructions.  When unmasked, a triggered interrupt will result 
+in execution progressing the requested number of instructions into the relevant 
+vector/ISR code.
+@end deffn
 
 @deffn {Command} {xtensa set_permissive} (0|1)
 By default accessing memory beyond defined regions is forbidden. This commnd controls memory access address check.
 When set to (1), skips access controls and address range check before read/write memory.
 @end deffn
 
-@deffn {Command} {xtensa maskisr} (on|off)
-Selects whether interrupts will be disabled during stepping over single instruction. The default configuration is (off).
-@end deffn
-
 @deffn {Command} {xtensa smpbreak} [none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]
 Configures debug signals connection ("break network") for currently selected core.
 @itemize @bullet
@@ -11014,6 +11141,8 @@ This feature is not well implemented and tested yet.
 @end itemize
 @end deffn
 
+@subsection Xtensa Performance Monitor Configuration
+
 @deffn {Command} {xtensa perfmon_enable} <counter_id> <select> [mask] [kernelcnt] [tracelevel]
 Enable and start performance counter.
 @itemize @bullet
@@ -11033,6 +11162,8 @@ whether to count.
 Dump performance counter value. If no argument specified, dumps all counters.
 @end deffn
 
+@subsection Xtensa Trace Configuration
+
 @deffn {Command} {xtensa tracestart} [pc <pcval>/[<maskbitcount>]] [after <n> [ins|words]]
 Set up and start a HW trace. Optionally set PC address range to trigger tracing stop when reached during program execution.
 This command also allows to specify the amount of data to capture after stop trigger activation.

src/rtos/rtos_freertos_stackings.c

@@ -55,6 +55,7 @@ static const struct stack_register_offset rtos_freertos_esp32_stack_offsets[] =
 	{ XT_REG_IDX_AR13, 0x40, 32 },		/* A13 */
 	{ XT_REG_IDX_AR14, 0x44, 32 },		/* A14 */
 	{ XT_REG_IDX_AR15, 0x48, 32 },		/* A15 */
+#if 0	// TODO: how to handle this...
 	{ XT_REG_IDX_AR16, -1, 32 },		/* A16 */ /* A16-A63 aren't in the stack frame because they've been flushed to the stack earlier */
 	{ XT_REG_IDX_AR17, -1, 32 },		/* A17 */
 	{ XT_REG_IDX_AR18, -1, 32 },		/* A18 */
@@ -143,6 +144,7 @@ static const struct stack_register_offset rtos_freertos_esp32_stack_offsets[] =
 	{ XT_REG_IDX_F15, -1, 32 },		/* f15 */
 	{ XT_REG_IDX_FCR, -1, 32 },		/* fcr */
 	{ XT_REG_IDX_FSR, -1, 32 },		/* fsr */
+#endif
 };
 
 static const struct stack_register_offset rtos_freertos_esp32_s2_stack_offsets[] = {
@@ -163,6 +165,7 @@ static const struct stack_register_offset rtos_freertos_esp32_s2_stack_offsets[]
 	{ XT_REG_IDX_AR13, 0x40, 32 },		/* A13 */
 	{ XT_REG_IDX_AR14, 0x44, 32 },		/* A14 */
 	{ XT_REG_IDX_AR15, 0x48, 32 },		/* A15 */
+#if 0	// TODO: how to handle this...
 	{ XT_REG_IDX_AR16, -1, 32 },		/* A16 */ /* A16-A63 aren't in the stack frame because they've been flushed to the stack earlier */
 	{ XT_REG_IDX_AR17, -1, 32 },		/* A17 */
 	{ XT_REG_IDX_AR18, -1, 32 },		/* A18 */
@@ -219,6 +222,7 @@ static const struct stack_register_offset rtos_freertos_esp32_s2_stack_offsets[]
 	{ XT_REG_IDX_PS, 0x08, 32 },		/* ps */
 	{ XT_REG_IDX_THREADPTR, -1, 32 },		/* threadptr */
 	{ ESP32_S2_REG_IDX_GPIOOUT, -1, 32 },		/* gpio_out */
+#endif
 };
 
 static const struct stack_register_offset rtos_freertos_esp32_s3_stack_offsets[] = {
@@ -239,6 +243,7 @@ static const struct stack_register_offset rtos_freertos_esp32_s3_stack_offsets[]
 	{ XT_REG_IDX_AR13, 0x40, 32 },		/* A13 */
 	{ XT_REG_IDX_AR14, 0x44, 32 },		/* A14 */
 	{ XT_REG_IDX_AR15, 0x48, 32 },		/* A15 */
+#if 0	// TODO: how to handle this...
 	{ XT_REG_IDX_AR16, -1, 32 },		/* A16 */ /* A16-A63 aren't in the stack frame because they've been flushed to the stack earlier */
 	{ XT_REG_IDX_AR17, -1, 32 },		/* A17 */
 	{ XT_REG_IDX_AR18, -1, 32 },		/* A18 */
@@ -350,6 +355,7 @@ static const struct stack_register_offset rtos_freertos_esp32_s3_stack_offsets[]
 	{ ESP32_S3_REG_IDX_Q5, -1, 128 },		/* q5 */
 	{ ESP32_S3_REG_IDX_Q6, -1, 128 },		/* q6 */
 	{ ESP32_S3_REG_IDX_Q7, -1, 128 },		/* q7 */
+#endif
 };
 
 //WARNING: There's some deeper magic going on when reading this. Please
@@ -369,6 +375,7 @@ static const struct stack_register_offset rtos_freertos_esp32_voluntary_stack_of
 	{ XT_REG_IDX_AR9, 0x44, 32 },		/* A9 */
 	{ XT_REG_IDX_AR10, 0x48, 32 },		/* A10 */
 	{ XT_REG_IDX_AR11, 0x4c, 32 },		/* A11 */
+#if 0	// TODO: how to handle this...
 	{ XT_REG_IDX_AR12, -1, 32 },		/* A12 */ /* A12-A63 aren't in the stack frame because they've been flushed to the stack earlier or not relevant*/
 	{ XT_REG_IDX_AR13, -1, 32 },		/* A13 */
 	{ XT_REG_IDX_AR14, -1, 32 },		/* A14 */
@@ -461,6 +468,7 @@ static const struct stack_register_offset rtos_freertos_esp32_voluntary_stack_of
 	{ XT_REG_IDX_F15, -1, 32 },		/* f15 */
 	{ XT_REG_IDX_FCR, -1, 32 },		/* fcr */
 	{ XT_REG_IDX_FSR, -1, 32 },		/* fsr */
+#endif
 };
 
 
@@ -478,6 +486,7 @@ static const struct stack_register_offset rtos_freertos_esp32_s2_voluntary_stack
 	{ XT_REG_IDX_AR9, 0x44, 32 },		/* A9 */
 	{ XT_REG_IDX_AR10, 0x48, 32 },		/* A10 */
 	{ XT_REG_IDX_AR11, 0x4c, 32 },		/* A11 */
+#if 0	// TODO: how to handle this...
 	{ XT_REG_IDX_AR12, -1, 32 },		/* A12 */ /* A12-A63 aren't in the stack frame because they've been flushed to the stack earlier or not relevant*/
 	{ XT_REG_IDX_AR13, -1, 32 },		/* A13 */
 	{ XT_REG_IDX_AR14, -1, 32 },		/* A14 */
@@ -538,6 +547,7 @@ static const struct stack_register_offset rtos_freertos_esp32_s2_voluntary_stack
 	{ XT_REG_IDX_PS, 0x18, 32 },		/* ps */
 	{ XT_REG_IDX_THREADPTR, -1, 32 },		/* threadptr */
 	{ ESP32_S2_REG_IDX_GPIOOUT, -1, 32 },		/* gpio_out */
+#endif
 };
 
 static const struct stack_register_offset rtos_freertos_esp32_s3_voluntary_stack_offsets[] = {
@@ -554,6 +564,7 @@ static const struct stack_register_offset rtos_freertos_esp32_s3_voluntary_stack
 	{ XT_REG_IDX_AR9, 0x44, 32 },		/* A9 */
 	{ XT_REG_IDX_AR10, 0x48, 32 },		/* A10 */
 	{ XT_REG_IDX_AR11, 0x4c, 32 },		/* A11 */
+#if 0	// TODO: how to handle this...
 	{ XT_REG_IDX_AR12, -1, 32 },		/* A12 */ /* A12-A63 aren't in the stack frame because they've been flushed to the stack earlier or not relevant*/
 	{ XT_REG_IDX_AR13, -1, 32 },		/* A13 */
 	{ XT_REG_IDX_AR14, -1, 32 },		/* A14 */
@@ -669,6 +680,7 @@ static const struct stack_register_offset rtos_freertos_esp32_s3_voluntary_stack
 	{ ESP32_S3_REG_IDX_Q5, -1, 128 },		/* q5 */
 	{ ESP32_S3_REG_IDX_Q6, -1, 128 },		/* q6 */
 	{ ESP32_S3_REG_IDX_Q7, -1, 128 },		/* q7 */
+#endif
 };
 
 const struct rtos_register_stacking rtos_freertos_esp32_stacking = {

src/rtos/rtos_nuttx_stackings.c

@@ -93,6 +93,7 @@ static const struct stack_register_offset nuttx_stack_offsets_esp32[] = {
 
 	/* A16-A63 aren't in the stack frame because they've been flushed to the stack earlier */
 
+#if 0	// TODO: how to handle this...
 	{ XT_REG_IDX_AR16, -1, 32 },		/* A16 */
 	{ XT_REG_IDX_AR17, -1, 32 },		/* A17 */
 	{ XT_REG_IDX_AR18, -1, 32 },		/* A18 */
@@ -185,6 +186,7 @@ static const struct stack_register_offset nuttx_stack_offsets_esp32[] = {
 	{ XT_REG_IDX_F15, -1, 32 },		/* f15 */
 	{ XT_REG_IDX_FCR, -1, 32 },		/* fcr */
 	{ XT_REG_IDX_FSR, -1, 32 },		/* fsr */
+#endif
 };
 
 const struct rtos_register_stacking nuttx_stacking_cortex_m = {

src/server/gdb_server.c

@@ -1343,6 +1343,8 @@ static int gdb_set_registers_packet(struct connection *connection,
 	packet_p = packet;
 	for (i = 0; i < reg_list_size; i++) {
 		uint8_t *bin_buf;
+		if (reg_list[i] == NULL || reg_list[i]->exist == false)
+            continue;
 		int chars = (DIV_ROUND_UP(reg_list[i]->size, 8) * 2);
 
 		if (packet_p + chars > packet + packet_size)
@@ -1395,7 +1397,7 @@ static int gdb_get_register_packet(struct connection *connection,
 	if (retval != ERROR_OK)
 		return gdb_error(connection, retval);
 
-	if (reg_list_size <= reg_num) {
+	if ((reg_list_size <= reg_num) || (!reg_list[reg_num])) {
 		LOG_ERROR("gdb requested a non-existing register (reg_num=%d)", reg_num);
 		return ERROR_SERVER_REMOTE_CLOSED;
 	}
@@ -1457,7 +1459,7 @@ static int gdb_set_register_packet(struct connection *connection,
 		return gdb_error(connection, retval);
 	}
 
-	if (reg_list_size <= reg_num) {
+	if ((reg_list_size <= reg_num) || (!reg_list[reg_num])) {
 		LOG_ERROR("gdb requested a non-existing register (reg_num=%d)", reg_num);
 		free(bin_buf);
 		free(reg_list);
@@ -1790,7 +1792,10 @@ static int gdb_breakpoint_watchpoint_packet(struct connection *connection,
 		case 1:
 			if (packet[0] == 'Z') {
 				retval = breakpoint_add(target, address, size, bp_type);
-				if (retval != ERROR_OK) {
+				if (retval == ERROR_TARGET_INVALID) {
+					/* SW breakpoints not supported */
+					gdb_put_packet(connection, "", 0);
+				} else if (retval != ERROR_OK) {
 					retval = gdb_error(connection, retval);
 					if (retval != ERROR_OK)
 						return retval;
@@ -2975,6 +2980,11 @@ static int gdb_query_packet(struct connection *connection,
 		gdb_connection->noack_mode = 1;
 		gdb_put_packet(connection, "OK", 2);
 		return ERROR_OK;
+	} else if (target_supports_gdb_query_custom(target)) {
+		char *buffer = NULL;
+		int ret = target_gdb_query_custom(target, packet, &buffer);
+		gdb_put_packet(connection, buffer, strlen(buffer));
+		return ret;
 	}
 
 	gdb_put_packet(connection, "", 0);