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Fix reference problem
1 parent 238f6ec commit 5c8d4ab

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-5
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+5
-5
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src/obj/mips.rs

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ pub fn process_code(
2424
for chunk in data.chunks_exact(4) {
2525
let reloc = relocs.iter().find(|r| (r.address as u32 & !3) == cur_addr);
2626
let code = u32::from_be_bytes(chunk.try_into()?);
27-
let mut instruction = Instruction::new(code, cur_addr, InstrCategory::CPU);
27+
let instruction = Instruction::new(code, cur_addr, InstrCategory::CPU);
2828

2929
let op = instruction.unique_id as u8;
3030
ops.push(op);
@@ -38,7 +38,7 @@ pub fn process_code(
3838
.get_operands_slice()
3939
.iter()
4040
.map(|op| match op {
41-
OperandType::cpu_immediate | OperandType::cpu_label => {
41+
OperandType::cpu_immediate | OperandType::cpu_label | OperandType::cpu_branch_target_label => {
4242
if is_branch {
4343
ObjInsArg::BranchOffset(branch_offset)
4444
} else if let Some(reloc) = reloc {
@@ -52,17 +52,17 @@ pub fn process_code(
5252
ObjInsArg::Reloc
5353
}
5454
} else {
55-
ObjInsArg::MipsArg(op.disassemble(instruction, None))
55+
ObjInsArg::MipsArg(op.disassemble(&instruction, None))
5656
}
5757
}
5858
OperandType::cpu_immediate_base => {
5959
if reloc.is_some() {
6060
ObjInsArg::RelocWithBase
6161
} else {
62-
ObjInsArg::MipsArg(op.disassemble(instruction, None))
62+
ObjInsArg::MipsArg(op.disassemble(&instruction, None))
6363
}
6464
}
65-
_ => ObjInsArg::MipsArg(op.disassemble(instruction, None)),
65+
_ => ObjInsArg::MipsArg(op.disassemble(&instruction, None)),
6666
})
6767
.collect();
6868
insts.push(ObjIns {

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