socfpga_enclustra_mercury_aa1.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
 */

/ {
	compatible = "altr,socfpga-arria10", "altr,socfpga";

	aliases {
		serial0 = &uart1;
		ethernet0 = &gmac0;
		spi0 = &qspi;
		i2c0 = &i2c1;
		i2c1 = &i2c0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	/* define i2c label to be used in baseboard dtsi */
	soc {
		i2c_encl: i2c@ffc02300 {
		};
		i2c_encl_fpga: i2c@ffc02200 {
		};
	};

};

&osc1 {
	clock-frequency = <33330000>;
};

&i2c_encl {
	i2c-sda-hold-time-ns = <300>;
	status = "okay";

	clock-frequency = <100000>;

	atsha204a: atsha204a@64 {
		compatible = "atmel,atsha204a";
		reg = <0x64>;
	};

	isl12022: isl12022@6f {
		compatible = "isl,isl12022";
		reg = <0x6f>;
	};
};

&i2c_encl_fpga {
	i2c-sda-hold-time-ns = <300>;
	status = "disabled";
};

&uart1 {
	status = "okay";
};

&mmc {
	status = "okay";
	cap-sd-highspeed;
	broken-cd;
	bus-width = <4>;
};

&eccmgr {
	sdmmca-ecc@ff8c2c00 {
		compatible = "altr,socfpga-sdmmc-ecc";
		reg = <0xff8c2c00 0x400>;
		altr,ecc-parent = <&mmc>;
		interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
					 <47 IRQ_TYPE_LEVEL_HIGH>,
					 <16 IRQ_TYPE_LEVEL_HIGH>,
					 <48 IRQ_TYPE_LEVEL_HIGH>;
	};
};

&qspi {
	status = "okay";

	flash0: s25fl512s@0 {
		u-boot,dm-pre-reloc;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spansion,s25fl512s", "jedec,spi-nor";
		reg = <0>;

		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		spi-max-frequency = <10000000>;

		page-size = <256>;
		cdns,block-size = <16>; /* 2^16, 64KB */
		cdns,read-delay = <4>;
		cdns,tshsl-ns = <50>;
		cdns,tsd2d-ns = <50>;
		cdns,tchsh-ns = <4>;
		cdns,tslch-ns = <4>;

		partition@raw {
			label = "Flash Raw";
			reg = <0x0 0x4000000>;
		};
	};
};

&watchdog1 {
	status = "disabled";
};

&gmac0 {
	status = "okay";
	/delete-property/ mac-address;
	phy-mode = "rgmii";
	phy-handle = <&phy3>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";

		phy3: ethernet-phy@3 {
			reg = <3>;

			/* Add 2ns RX clock delay (1.2ns + 0.78ns)*/
			rxc-skew-ps = <1680>;
			rxd0-skew-ps = <420>;
			rxd1-skew-ps = <420>;
			rxd2-skew-ps = <420>;
			rxd3-skew-ps = <420>;
			rxdv-skew-ps = <420>;

			/* Add 1.38ns TX clock delay (0.96ns + 0.42ns)*/
			txc-skew-ps = <1860>;
			txd0-skew-ps = <0>;
			txd1-skew-ps = <0>;
			txd2-skew-ps = <0>;
			txd3-skew-ps = <0>;
			txen-skew-ps = <0>;
		};
	};
};

&usb0 {
	status = "okay";
	dr_mode = "host";
};