@@ -344,10 +344,10 @@ static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
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/* First/last register type for the 'normal' register types (i.e. general
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purpose, floating point, altivec, and VSX registers). */
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- #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, S2PP_REG_TYPE )
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+ #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE )
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- #define IS_FP_VECT_REG_TYPE(RTYPE) (IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE ) || IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE))
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+ #define IS_FP_VECT_REG_TYPE(RTYPE) (IN_RANGE(RTYPE, VSX_REG_TYPE, S2PP_REG_TYPE ) || IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE))
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/* Register classes we care about in secondary reload or go if legitimate
@@ -358,7 +358,7 @@ enum rs6000_reload_reg_type {
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RELOAD_REG_GPR, /* General purpose registers. */
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RELOAD_REG_FPR, /* Traditional floating point regs. */
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RELOAD_REG_VMX, /* Altivec (VMX) registers. */
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- RELOAD_REG_FXV, /* Altivec (VMX) registers. */
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+ // RELOAD_REG_FXV, /* Altivec (VMX) registers. */
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RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
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N_RELOAD_REG
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};
@@ -367,7 +367,7 @@ enum rs6000_reload_reg_type {
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into real registers, and skip the ANY class, which is just an OR of the
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bits. */
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#define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
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- #define LAST_RELOAD_REG_CLASS RELOAD_REG_FXV
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+ #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
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/* Map reload register type to a register in the register class. */
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struct reload_reg_map_type {
@@ -5490,7 +5490,7 @@ output_vec_const_move (rtx *operands)
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}
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mode = GET_MODE (splat_vec);
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if (mode == V8HImode)
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- return "fxvsplath %0,0";
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+ return "#";//" fxvsplath %0,0";
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else if (mode == V16QImode)
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return "#";
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else
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