diff --git a/compiler/x/codegen/OMRInstOpCode.enum b/compiler/x/codegen/OMRInstOpCode.enum index b06f3b11ba..21493d6547 100644 --- a/compiler/x/codegen/OMRInstOpCode.enum +++ b/compiler/x/codegen/OMRInstOpCode.enum @@ -70,3 +70,16 @@ VMOVDQU16RegMem = VMOVDQU16RegReg, VMOVDQU32RegReg = MOVDQURegReg, VMOVDQU32RegMem = MOVDQURegReg, VMOVDQU64RegMem = VMOVDQU64RegReg, +VPSLLVWRegRegMem = VPSLLVWRegRegReg, +VPSRAVWRegRegMem = VPSRAVWRegRegReg, +VPSRLVWRegRegMem = VPSRLVWRegRegReg, +VPSLLVDRegRegMem = VPSLLVDRegRegReg, +VPSRAVDRegRegMem = VPSRAVDRegRegReg, +VPSRLVDRegRegMem = VPSRLVDRegRegReg, +VPSLLVQRegRegMem = VPSLLVQRegRegReg, +VPSRAVQRegRegMem = VPSRAVQRegRegReg, +VPSRLVQRegRegMem = VPSRLVQRegRegReg, +VPROLVDRegRegMem = VPROLVDRegRegReg, +VPROLVQRegRegMem = VPROLVQRegRegReg, +VPRORVDRegRegMem = VPRORVDRegRegReg, +VPRORVQRegRegMem = VPRORVQRegRegReg, diff --git a/compiler/x/codegen/OMRTreeEvaluator.cpp b/compiler/x/codegen/OMRTreeEvaluator.cpp index 5b165f9c77..13f5b7c256 100644 --- a/compiler/x/codegen/OMRTreeEvaluator.cpp +++ b/compiler/x/codegen/OMRTreeEvaluator.cpp @@ -77,6 +77,7 @@ #include "codegen/InstOpCode.hpp" #include "x/codegen/BinaryCommutativeAnalyser.hpp" #include "x/codegen/SubtractAnalyser.hpp" +#include "x/codegen/X86OpcodeTable.hpp" class TR_OpaqueClassBlock; class TR_OpaqueMethodBlock; @@ -4007,102 +4008,6 @@ OMR::X86::TreeEvaluator::ibyteswapEvaluator(TR::Node *node, TR::CodeGenerator *c return target; } -enum ArithmeticOps : uint32_t - { - ArithmeticInvalid, - BinaryArithmeticAdd, - BinaryArithmeticSub, - BinaryArithmeticMul, - BinaryArithmeticDiv, - BinaryArithmeticAnd, - BinaryArithmeticOr, - BinaryArithmeticXor, - BinaryArithmeticMin, - BinaryArithmeticMax, - NumBinaryArithmeticOps, - UnaryArithmeticAbs, - UnaryArithmeticSqrt, - LastOp, - NumUnaryArithmeticOps = LastOp - NumBinaryArithmeticOps + 1 - }; - -static const TR::InstOpCode::Mnemonic BinaryArithmeticOpCodesForReg[TR::NumOMRTypes][NumBinaryArithmeticOps] = - { - // Invalid, Add, Sub, Mul, Div, And, Or, Xor min max - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // NoType - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Int8 - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Int16 - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Int32 - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Int64 - { TR::InstOpCode::bad, TR::InstOpCode::ADDSSRegReg, TR::InstOpCode::SUBSSRegReg, TR::InstOpCode::MULSSRegReg, TR::InstOpCode::DIVSSRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Float - { TR::InstOpCode::bad, TR::InstOpCode::ADDSDRegReg, TR::InstOpCode::SUBSDRegReg, TR::InstOpCode::MULSDRegReg, TR::InstOpCode::DIVSDRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Double - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Address - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Aggregate - - }; - -static const TR::InstOpCode::Mnemonic VectorBinaryArithmeticOpCodesForReg[TR::NumVectorElementTypes][NumBinaryArithmeticOps] = - { - // Invalid, Add, Sub, Mul, Div, And, Or, Xor min max - { TR::InstOpCode::bad, TR::InstOpCode::PADDBRegReg, TR::InstOpCode::PSUBBRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::PMINSBRegReg, TR::InstOpCode::PMAXSBRegReg }, // Int8 - { TR::InstOpCode::bad, TR::InstOpCode::PADDWRegReg, TR::InstOpCode::PSUBWRegReg, TR::InstOpCode::PMULLWRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::PMINSWRegReg, TR::InstOpCode::PMAXSWRegReg }, // Int16 - { TR::InstOpCode::bad, TR::InstOpCode::PADDDRegReg, TR::InstOpCode::PSUBDRegReg, TR::InstOpCode::PMULLDRegReg, TR::InstOpCode::bad, TR::InstOpCode::PANDRegReg, TR::InstOpCode::PORRegReg, TR::InstOpCode::PXORRegReg, TR::InstOpCode::PMINSDRegReg, TR::InstOpCode::PMAXSDRegReg }, // Int32 - { TR::InstOpCode::bad, TR::InstOpCode::PADDQRegReg, TR::InstOpCode::PSUBQRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::PANDRegReg, TR::InstOpCode::PORRegReg, TR::InstOpCode::PXORRegReg, TR::InstOpCode::PMINSQRegReg, TR::InstOpCode::PMAXSQRegReg }, // Int64 - { TR::InstOpCode::bad, TR::InstOpCode::ADDPSRegReg, TR::InstOpCode::SUBPSRegReg, TR::InstOpCode::MULPSRegReg, TR::InstOpCode::DIVPSRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::MINPSRegReg, TR::InstOpCode::MAXPSRegReg }, // Float - { TR::InstOpCode::bad, TR::InstOpCode::ADDPDRegReg, TR::InstOpCode::SUBPDRegReg, TR::InstOpCode::MULPDRegReg, TR::InstOpCode::DIVPDRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::MINPDRegReg, TR::InstOpCode::MAXPDRegReg }, // Double - }; - - - -static const TR::InstOpCode::Mnemonic BinaryArithmeticOpCodesForMem[TR::NumOMRTypes][NumBinaryArithmeticOps] = - { - // Invalid, Add, Sub, Mul, Div, And, Or, Xor min max - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // NoType - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Int8 - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Int16 - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Int32 - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Int64 - { TR::InstOpCode::bad, TR::InstOpCode::ADDSSRegMem, TR::InstOpCode::SUBSSRegMem, TR::InstOpCode::MULSSRegMem, TR::InstOpCode::DIVSSRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Float - { TR::InstOpCode::bad, TR::InstOpCode::ADDSDRegMem, TR::InstOpCode::SUBSDRegMem, TR::InstOpCode::MULSDRegMem, TR::InstOpCode::DIVSDRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Double - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Address - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Aggregate - }; - - -static const TR::InstOpCode::Mnemonic VectorBinaryArithmeticOpCodesForMem[TR::NumVectorElementTypes][NumBinaryArithmeticOps] = - { - // Invalid, Add, Sub, Mul, Div, And, Or, Xor min max - { TR::InstOpCode::bad, TR::InstOpCode::PADDBRegMem, TR::InstOpCode::PSUBBRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::PMINSBRegMem, TR::InstOpCode::PMAXSBRegMem }, // Int8 - { TR::InstOpCode::bad, TR::InstOpCode::PADDWRegMem, TR::InstOpCode::PSUBWRegMem, TR::InstOpCode::PMULLWRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::PMINSWRegMem, TR::InstOpCode::PMAXSWRegMem }, // Int16 - { TR::InstOpCode::bad, TR::InstOpCode::PADDDRegMem, TR::InstOpCode::PSUBDRegMem, TR::InstOpCode::PMULLDRegMem, TR::InstOpCode::bad, TR::InstOpCode::PANDRegMem, TR::InstOpCode::PORRegMem, TR::InstOpCode::PXORRegMem, TR::InstOpCode::PMINSDRegMem, TR::InstOpCode::PMAXSDRegMem }, // Int32 - { TR::InstOpCode::bad, TR::InstOpCode::PADDQRegMem, TR::InstOpCode::PSUBQRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::PANDRegMem, TR::InstOpCode::PORRegMem, TR::InstOpCode::PXORRegMem, TR::InstOpCode::PMINSQRegMem, TR::InstOpCode::PMAXSQRegMem }, // Int64 - { TR::InstOpCode::bad, TR::InstOpCode::ADDPSRegMem, TR::InstOpCode::SUBPSRegMem, TR::InstOpCode::MULPSRegMem, TR::InstOpCode::DIVPSRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Float - { TR::InstOpCode::bad, TR::InstOpCode::ADDPDRegMem, TR::InstOpCode::SUBPDRegMem, TR::InstOpCode::MULPDRegMem, TR::InstOpCode::DIVPDRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // Double - }; - -static const TR::InstOpCode::Mnemonic VectorUnaryArithmeticOpCodesForReg[TR::NumVectorElementTypes][NumUnaryArithmeticOps] = - { - // Invalid, abs, sqrt - { TR::InstOpCode::bad, TR::InstOpCode::PABSBRegReg, TR::InstOpCode::bad }, // Int8 - { TR::InstOpCode::bad, TR::InstOpCode::PABSWRegReg, TR::InstOpCode::bad }, // Int16 - { TR::InstOpCode::bad, TR::InstOpCode::PABSDRegReg, TR::InstOpCode::bad }, // Int32 - { TR::InstOpCode::bad, TR::InstOpCode::PABSQRegReg, TR::InstOpCode::bad }, // Int64 - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::SQRTPSRegReg }, // Float - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::SQRTPDRegReg }, // Double - }; - - -static const TR::InstOpCode::Mnemonic VectorUnaryArithmeticOpCodesForMem[TR::NumVectorElementTypes][NumUnaryArithmeticOps] = - { - // Invalid, abs, sqrt - { TR::InstOpCode::bad, TR::InstOpCode::PABSBRegMem, TR::InstOpCode::bad }, // Int8 - { TR::InstOpCode::bad, TR::InstOpCode::PABSWRegMem, TR::InstOpCode::bad }, // Int16 - { TR::InstOpCode::bad, TR::InstOpCode::PABSDRegMem, TR::InstOpCode::bad }, // Int32 - { TR::InstOpCode::bad, TR::InstOpCode::PABSQRegMem, TR::InstOpCode::bad }, // Int64 - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::VSQRTPSRegMem }, // Float - { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::VSQRTPDRegMem }, // Double - }; - static const TR::ILOpCodes MemoryLoadOpCodes[TR::NumOMRTypes] = { TR::BadILOp, // NoType @@ -4127,6 +4032,22 @@ TR::InstOpCode OMR::X86::TreeEvaluator::getNativeSIMDOpcode(TR::ILOpCodes opcode bool isMaskOp = OMR::ILOpCode(opcode).isVectorMasked(); switch (OMR::ILOpCode::getVectorOperation(opcode)) { + case TR::vmrol: + case TR::vrol: + binaryOp = BinaryRotateLeft; + break; + case TR::vmshl: + case TR::vshl: + binaryOp = BinaryLogicalShiftLeft; + break; + case TR::vmshr: + case TR::vshr: + binaryOp = BinaryLogicalShiftRight; + break; + case TR::vmushr: + case TR::vushr: + binaryOp = BinaryArithmeticShiftRight; + break; case TR::vmadd: case TR::vadd: binaryOp = BinaryArithmeticAdd; @@ -4189,13 +4110,13 @@ TR::InstOpCode OMR::X86::TreeEvaluator::getNativeSIMDOpcode(TR::ILOpCodes opcode if (binaryOp != ArithmeticInvalid) { - memOpcode = VectorBinaryArithmeticOpCodesForMem[elementType - 1][binaryOp]; - regOpcode = VectorBinaryArithmeticOpCodesForReg[elementType - 1][binaryOp]; + memOpcode = VectorBinaryArithmeticOpCodesForMem[binaryOp][elementType - 1]; + regOpcode = VectorBinaryArithmeticOpCodesForReg[binaryOp][elementType - 1]; } else { - memOpcode = VectorUnaryArithmeticOpCodesForMem[elementType - 1][unaryOp - NumBinaryArithmeticOps]; - regOpcode = VectorUnaryArithmeticOpCodesForReg[elementType - 1][unaryOp - NumBinaryArithmeticOps]; + memOpcode = VectorUnaryArithmeticOpCodesForMem[unaryOp - NumBinaryArithmeticOps][elementType - 1]; + regOpcode = VectorUnaryArithmeticOpCodesForReg[unaryOp - NumBinaryArithmeticOps][elementType - 1]; } return memForm ? memOpcode : regOpcode; @@ -4697,7 +4618,7 @@ TR::Register* OMR::X86::TreeEvaluator::floatingPointBinaryArithmeticEvaluator(TR if (operandNode1->getRegister() || operandNode1->getReferenceCount() != 1 || operandNode1->getOpCodeValue() != MemoryLoadOpCodes[type] || - BinaryArithmeticOpCodesForMem[type][arithmetic] == TR::InstOpCode::bad) + BinaryArithmeticOpCodesForMem[arithmetic][type] == TR::InstOpCode::bad) { useRegMemForm = false; } @@ -4708,8 +4629,8 @@ TR::Register* OMR::X86::TreeEvaluator::floatingPointBinaryArithmeticEvaluator(TR TR::Register* resultReg = cg->allocateRegister(operandReg0->getKind()); resultReg->setIsSinglePrecision(operandReg0->isSinglePrecision()); - TR::InstOpCode::Mnemonic opCode = useRegMemForm ? BinaryArithmeticOpCodesForMem[type][arithmetic] : - BinaryArithmeticOpCodesForReg[type][arithmetic]; + TR::InstOpCode::Mnemonic opCode = useRegMemForm ? BinaryArithmeticOpCodesForMem[arithmetic][type] : + BinaryArithmeticOpCodesForReg[arithmetic][type]; TR_ASSERT_FATAL(opCode != TR::InstOpCode::bad, "floatingPointBinaryArithmeticEvaluator: unsupported data type or arithmetic."); @@ -5106,8 +5027,8 @@ OMR::X86::TreeEvaluator::vfmaEvaluator(TR::Node *node, TR::CodeGenerator *cg) } else { - TR::InstOpCode mulOpcode = VectorBinaryArithmeticOpCodesForReg[et - 1][BinaryArithmeticMul]; - TR::InstOpCode addOpcode = VectorBinaryArithmeticOpCodesForReg[et - 1][BinaryArithmeticAdd]; + TR::InstOpCode mulOpcode = VectorBinaryArithmeticOpCodesForReg[BinaryArithmeticMul][et - 1]; + TR::InstOpCode addOpcode = VectorBinaryArithmeticOpCodesForReg[BinaryArithmeticAdd][et - 1]; TR_ASSERT_FATAL(mulOpcode.getMnemonic() != TR::InstOpCode::bad, "No multiplication opcode found"); TR_ASSERT_FATAL(addOpcode.getMnemonic() != TR::InstOpCode::bad, "No addition opcode found"); @@ -5711,7 +5632,7 @@ OMR::X86::TreeEvaluator::arrayToVectorMaskHelper(TR::Node *node, TR::CodeGenerat { TR::Register *result = cg->allocateRegister(TR_VRF); TR::InstOpCode xorOpcode = TR::InstOpCode::PXORRegReg; - TR::InstOpCode subOp = VectorBinaryArithmeticOpCodesForReg[et - 1][BinaryArithmeticSub]; + TR::InstOpCode subOp = VectorBinaryArithmeticOpCodesForReg[BinaryArithmeticSub][et - 1]; OMR::X86::Encoding xorEncoding = xorOpcode.getSIMDEncoding(&cg->comp()->target().cpu, vl); OMR::X86::Encoding subEncoding = subOp.getSIMDEncoding(&cg->comp()->target().cpu, vl); TR_ASSERT_FATAL(xorEncoding != OMR::X86::Bad, "No suitable encoding form for pxor opcode"); @@ -6145,49 +6066,49 @@ OMR::X86::TreeEvaluator::vexpandEvaluator(TR::Node *node, TR::CodeGenerator *cg) TR::Register* OMR::X86::TreeEvaluator::vshlEvaluator(TR::Node *node, TR::CodeGenerator *cg) { - return TR::TreeEvaluator::unImpOpEvaluator(node, cg); + return TR::TreeEvaluator::vectorBinaryArithmeticEvaluator(node, cg); } TR::Register* OMR::X86::TreeEvaluator::vmshlEvaluator(TR::Node *node, TR::CodeGenerator *cg) { - return TR::TreeEvaluator::unImpOpEvaluator(node, cg); + return TR::TreeEvaluator::vectorBinaryArithmeticEvaluator(node, cg); } TR::Register* OMR::X86::TreeEvaluator::vshrEvaluator(TR::Node *node, TR::CodeGenerator *cg) { - return TR::TreeEvaluator::unImpOpEvaluator(node, cg); + return TR::TreeEvaluator::vectorBinaryArithmeticEvaluator(node, cg); } TR::Register* OMR::X86::TreeEvaluator::vmshrEvaluator(TR::Node *node, TR::CodeGenerator *cg) { - return TR::TreeEvaluator::unImpOpEvaluator(node, cg); + return TR::TreeEvaluator::vectorBinaryArithmeticEvaluator(node, cg); } TR::Register* OMR::X86::TreeEvaluator::vushrEvaluator(TR::Node *node, TR::CodeGenerator *cg) { - return TR::TreeEvaluator::unImpOpEvaluator(node, cg); + return TR::TreeEvaluator::vectorBinaryArithmeticEvaluator(node, cg); } TR::Register* OMR::X86::TreeEvaluator::vmushrEvaluator(TR::Node *node, TR::CodeGenerator *cg) { - return TR::TreeEvaluator::unImpOpEvaluator(node, cg); + return TR::TreeEvaluator::vectorBinaryArithmeticEvaluator(node, cg); } TR::Register* OMR::X86::TreeEvaluator::vrolEvaluator(TR::Node *node, TR::CodeGenerator *cg) { - return TR::TreeEvaluator::unImpOpEvaluator(node, cg); + return TR::TreeEvaluator::vectorBinaryArithmeticEvaluator(node, cg); } TR::Register* OMR::X86::TreeEvaluator::vmrolEvaluator(TR::Node *node, TR::CodeGenerator *cg) { - return TR::TreeEvaluator::unImpOpEvaluator(node, cg); + return TR::TreeEvaluator::vectorBinaryArithmeticEvaluator(node, cg); } TR::Register* diff --git a/compiler/x/codegen/X86OpcodeTable.hpp b/compiler/x/codegen/X86OpcodeTable.hpp new file mode 100644 index 0000000000..6839ff33c9 --- /dev/null +++ b/compiler/x/codegen/X86OpcodeTable.hpp @@ -0,0 +1,140 @@ +/******************************************************************************* + * Copyright IBM Corp. and others 2023 + * + * This program and the accompanying materials are made available under + * the terms of the Eclipse Public License 2.0 which accompanies this + * distribution and is available at http://eclipse.org/legal/epl-2.0 + * or the Apache License, Version 2.0 which accompanies this distribution + * and is available at https://www.apache.org/licenses/LICENSE-2.0. + * + * This Source Code may also be made available under the following Secondary + * Licenses when the conditions for such availability set forth in the + * Eclipse Public License, v. 2.0 are satisfied: GNU General Public License, + * version 2 with the GNU Classpath Exception [1] and GNU General Public + * License, version 2 with the OpenJDK Assembly Exception [2]. + * + * [1] https://www.gnu.org/software/classpath/license.html + * [2] https://openjdk.org/legal/assembly-exception.html + * + * SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0-only WITH Classpath-exception-2.0 OR GPL-2.0-only WITH OpenJDK-assembly-exception-1.0 + *******************************************************************************/ + +#ifndef OMR_X86OPCODETABLE_HPP +#define OMR_X86OPCODETABLE_HPP + +#include +#include "codegen/InstOpCode.hpp" + +enum ArithmeticOps : uint32_t + { + ArithmeticInvalid, + BinaryArithmeticAdd, + BinaryArithmeticSub, + BinaryArithmeticMul, + BinaryArithmeticDiv, + BinaryArithmeticAnd, + BinaryArithmeticOr, + BinaryArithmeticXor, + BinaryArithmeticMin, + BinaryArithmeticMax, + BinaryLogicalShiftLeft, + BinaryLogicalShiftRight, + BinaryArithmeticShiftRight, + BinaryRotateLeft, + BinaryRotateRight, + NumBinaryArithmeticOps, + UnaryArithmeticAbs, + UnaryArithmeticSqrt, + LastOp, + NumUnaryArithmeticOps = LastOp - NumBinaryArithmeticOps + 1 + }; + +// TODO: Truncate the table +static const TR::InstOpCode::Mnemonic BinaryArithmeticOpCodesForReg[NumBinaryArithmeticOps][TR::NumOMRTypes] = + { + // NoType Int8, Int16, Int32, Int64, Float, Double, Address, Aggregate + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticInvalid + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::ADDSSRegReg, TR::InstOpCode::ADDSDRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticAdd + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::SUBSSRegReg, TR::InstOpCode::SUBSDRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticSub + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::MULSSRegReg, TR::InstOpCode::MULSDRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticMul + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::DIVSSRegReg, TR::InstOpCode::DIVSDRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticDiv + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticAnd + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticOr, + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticXor + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticMin + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticMax + }; + +// TODO: Truncate the table +static const TR::InstOpCode::Mnemonic BinaryArithmeticOpCodesForMem[NumBinaryArithmeticOps][TR::NumOMRTypes] = + { + // NoType Int8, Int16, Int32, Int64, Float, Double, Address, Aggregate + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticInvalid + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::ADDSSRegMem, TR::InstOpCode::ADDSDRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticAdd + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::SUBSSRegMem, TR::InstOpCode::SUBSDRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticSub + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::MULSSRegMem, TR::InstOpCode::MULSDRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticMul + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::DIVSSRegMem, TR::InstOpCode::DIVSDRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticDiv + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticAnd + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticOr, + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticXor + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticMin + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticMax + }; + +static const TR::InstOpCode::Mnemonic VectorBinaryArithmeticOpCodesForReg[NumBinaryArithmeticOps][TR::NumVectorElementTypes] = + { + // Int8, Int16, Int32, Int64, Float, Double + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticInvalid + { TR::InstOpCode::PADDBRegReg, TR::InstOpCode::PADDWRegReg, TR::InstOpCode::PADDDRegReg, TR::InstOpCode::PADDQRegReg, TR::InstOpCode::ADDPSRegReg, TR::InstOpCode::ADDPDRegReg }, // BinaryArithmeticAdd + { TR::InstOpCode::PSUBBRegReg, TR::InstOpCode::PSUBWRegReg, TR::InstOpCode::PSUBDRegReg, TR::InstOpCode::PSUBQRegReg, TR::InstOpCode::SUBPSRegReg, TR::InstOpCode::SUBPDRegReg }, // BinaryArithmeticSub + { TR::InstOpCode::bad, TR::InstOpCode::PMULLWRegReg, TR::InstOpCode::PMULLDRegReg, TR::InstOpCode::bad, TR::InstOpCode::MULPSRegReg, TR::InstOpCode::MULPDRegReg }, // BinaryArithmeticMul + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::DIVPSRegReg, TR::InstOpCode::DIVPDRegReg }, // BinaryArithmeticDiv + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::PANDRegReg, TR::InstOpCode::PANDRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticAnd + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::PORRegReg, TR::InstOpCode::PORRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticOr, + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::PXORRegReg, TR::InstOpCode::PXORRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticXor + { TR::InstOpCode::PMINSBRegReg, TR::InstOpCode::PMINSWRegReg, TR::InstOpCode::PMINSDRegReg, TR::InstOpCode::PMINSQRegReg, TR::InstOpCode::MINPSRegReg, TR::InstOpCode::MINPDRegReg }, // BinaryArithmeticMin + { TR::InstOpCode::PMAXSBRegReg, TR::InstOpCode::PMAXSWRegReg, TR::InstOpCode::PMAXSDRegReg, TR::InstOpCode::PMAXSQRegReg, TR::InstOpCode::MAXPSRegReg, TR::InstOpCode::MAXPDRegReg }, // BinaryArithmeticMax + { TR::InstOpCode::bad, TR::InstOpCode::VPSLLVWRegRegReg, TR::InstOpCode::VPSLLVDRegRegReg, TR::InstOpCode::VPSLLVQRegRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryLogicalShiftLeft + { TR::InstOpCode::bad, TR::InstOpCode::VPSRAVWRegRegReg, TR::InstOpCode::VPSRAVDRegRegReg, TR::InstOpCode::VPSRAVQRegRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryLogicalShiftRight + { TR::InstOpCode::bad, TR::InstOpCode::VPSRLVWRegRegReg, TR::InstOpCode::VPSRLVDRegRegReg, TR::InstOpCode::VPSRLVQRegRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticShiftRight + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::VPROLVDRegRegReg, TR::InstOpCode::VPROLVQRegRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryRotateLeft + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::VPRORVDRegRegReg, TR::InstOpCode::VPRORVQRegRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad } // BinaryRotateRight + }; + +static const TR::InstOpCode::Mnemonic VectorBinaryArithmeticOpCodesForMem[NumBinaryArithmeticOps][TR::NumVectorElementTypes] = + { + // Int8, Int16, Int32, Int64, Float, Double + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticInvalid + { TR::InstOpCode::PADDBRegMem, TR::InstOpCode::PADDWRegMem, TR::InstOpCode::PADDDRegMem, TR::InstOpCode::PADDQRegMem, TR::InstOpCode::ADDPSRegMem, TR::InstOpCode::ADDPDRegMem }, // BinaryArithmeticAdd + { TR::InstOpCode::PSUBBRegMem, TR::InstOpCode::PSUBWRegMem, TR::InstOpCode::PSUBDRegMem, TR::InstOpCode::PSUBQRegMem, TR::InstOpCode::SUBPSRegMem, TR::InstOpCode::SUBPDRegMem }, // BinaryArithmeticSub + { TR::InstOpCode::bad, TR::InstOpCode::PMULLWRegMem, TR::InstOpCode::PMULLDRegMem, TR::InstOpCode::bad, TR::InstOpCode::MULPSRegMem, TR::InstOpCode::MULPDRegMem }, // BinaryArithmeticMul + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::DIVPSRegMem, TR::InstOpCode::DIVPDRegMem }, // BinaryArithmeticDiv + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::PANDRegMem, TR::InstOpCode::PANDRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticAnd + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::PORRegMem, TR::InstOpCode::PORRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticOr, + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::PXORRegMem, TR::InstOpCode::PXORRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticXor + { TR::InstOpCode::PMINSBRegMem, TR::InstOpCode::PMINSWRegMem, TR::InstOpCode::PMINSDRegMem, TR::InstOpCode::PMINSQRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticMin + { TR::InstOpCode::PMAXSBRegMem, TR::InstOpCode::PMAXSWRegMem, TR::InstOpCode::PMAXSDRegMem, TR::InstOpCode::PMAXSQRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticMax + { TR::InstOpCode::bad, TR::InstOpCode::VPSLLVWRegRegMem, TR::InstOpCode::VPSLLVDRegRegMem, TR::InstOpCode::VPSLLVQRegRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryLogicalShiftLeft + { TR::InstOpCode::bad, TR::InstOpCode::VPSRAVWRegRegMem, TR::InstOpCode::VPSRAVDRegRegMem, TR::InstOpCode::VPSRAVQRegRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryLogicalShiftRight + { TR::InstOpCode::bad, TR::InstOpCode::VPSRLVWRegRegMem, TR::InstOpCode::VPSRLVDRegRegMem, TR::InstOpCode::VPSRLVQRegRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryArithmeticShiftRight + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::VPROLVDRegRegMem, TR::InstOpCode::VPROLVQRegRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad }, // BinaryRotateLeft + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::VPRORVDRegRegMem, TR::InstOpCode::VPRORVQRegRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad } // BinaryRotateRight + }; + +static const TR::InstOpCode::Mnemonic VectorUnaryArithmeticOpCodesForReg[NumUnaryArithmeticOps][TR::NumVectorElementTypes] = + { + // Int8, Int16, Int32, Int64, Float, Double + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // UnaryArithmeticInvalid, + { TR::InstOpCode::PABSBRegReg, TR::InstOpCode::PABSWRegReg, TR::InstOpCode::PABSDRegReg, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // UnaryArithmeticAbs, + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::SQRTPSRegReg, TR::InstOpCode::SQRTPDRegReg } // UnaryArithmeticSqrt, + }; + +static const TR::InstOpCode::Mnemonic VectorUnaryArithmeticOpCodesForMem[NumUnaryArithmeticOps][TR::NumVectorElementTypes] = + { + // Int8, Int16, Int32, Int64, Float, Double + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // UnaryArithmeticInvalid, + { TR::InstOpCode::PABSBRegMem, TR::InstOpCode::PABSWRegMem, TR::InstOpCode::PABSDRegMem, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad }, // UnaryArithmeticAbs, + { TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::bad, TR::InstOpCode::VSQRTPSRegMem, TR::InstOpCode::VSQRTPDRegMem } // UnaryArithmeticSqrt, + }; + +#endif diff --git a/compiler/x/codegen/X86Ops.ins b/compiler/x/codegen/X86Ops.ins index 2a6f20ceee..fdd548cc1a 100644 --- a/compiler/x/codegen/X86Ops.ins +++ b/compiler/x/codegen/X86Ops.ins @@ -5533,6 +5533,103 @@ INSTRUCTION(PSRLQRegImm1, psrlq, X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F) ), +INSTRUCTION(VPSLLVWRegRegReg, psllvw, + BINARY(VEX_L128, VEX_vReg_, PREFIX_66, REX_W, ESCAPE_0F38, 0x12, 0, ModRM_RM__, Immediate_0), + PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SourceRegisterInModRM), + PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget | IA32OpProp1_SourceCanBeMemRef), + FEATURES(X86FeatureProp_EVEX128Supported | X86FeatureProp_EVEX128RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512VL | X86FeatureProp_EVEX256RequiresAVX512BW | + X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | X86FeatureProp_EVEX256RequiresAVX512BW | + X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F)), +INSTRUCTION(VPSLLVDRegRegReg, psllvd, + BINARY(VEX_L128, VEX_vReg_, PREFIX_66, REX__, ESCAPE_0F38, 0x47, 0, ModRM_RM__, Immediate_0), + PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SourceRegisterInModRM), + PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget | IA32OpProp1_SourceCanBeMemRef), + FEATURES(X86FeatureProp_VEX128Supported | X86FeatureProp_VEX128RequiresAVX2 | X86FeatureProp_VEX256Supported | X86FeatureProp_VEX256RequiresAVX2 | + X86FeatureProp_EVEX128Supported | X86FeatureProp_EVEX128RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512VL | + X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | + X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F)), +INSTRUCTION(VPSLLVQRegRegReg, psllvq, + BINARY(VEX_L128, VEX_vReg_, PREFIX_66, REX_W, ESCAPE_0F38, 0x47, 0, ModRM_RM__, Immediate_0), + PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SourceRegisterInModRM), + PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget | IA32OpProp1_SourceCanBeMemRef), + FEATURES(X86FeatureProp_VEX128Supported | X86FeatureProp_VEX128RequiresAVX2 | X86FeatureProp_VEX256Supported | X86FeatureProp_VEX256RequiresAVX2 | + X86FeatureProp_EVEX128Supported | X86FeatureProp_EVEX128RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512VL | + X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | + X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F)), +INSTRUCTION(VPSRAVWRegRegReg, vpsravw, + BINARY(VEX_L128, VEX_vReg_, PREFIX_66, REX_W, ESCAPE_0F38, 0x11, 0, ModRM_RM__, Immediate_0), + PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SourceRegisterInModRM), + PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget | IA32OpProp1_SourceCanBeMemRef), + FEATURES(X86FeatureProp_EVEX128Supported | X86FeatureProp_EVEX128RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512VL | X86FeatureProp_EVEX256RequiresAVX512BW | + X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | X86FeatureProp_EVEX256RequiresAVX512BW | + X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F)), +INSTRUCTION(VPSRAVDRegRegReg, vpsravd, + BINARY(VEX_L128, VEX_vReg_, PREFIX_66, REX__, ESCAPE_0F38, 0x46, 0, ModRM_RM__, Immediate_0), + PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SourceRegisterInModRM), + PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget | IA32OpProp1_SourceCanBeMemRef), + FEATURES(X86FeatureProp_VEX128Supported | X86FeatureProp_VEX128RequiresAVX2 | X86FeatureProp_VEX256Supported | X86FeatureProp_VEX256RequiresAVX2 | + X86FeatureProp_EVEX128Supported | X86FeatureProp_EVEX128RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512VL | + X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | + X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F)), +INSTRUCTION(VPSRAVQRegRegReg, vpsravq, + BINARY(VEX_L128, VEX_vReg_, PREFIX_66, REX_W, ESCAPE_0F38, 0x46, 0, ModRM_RM__, Immediate_0), + PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SourceRegisterInModRM), + PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget | IA32OpProp1_SourceCanBeMemRef), + FEATURES(X86FeatureProp_EVEX128Supported | X86FeatureProp_EVEX128RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512VL | + X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | + X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F)), +INSTRUCTION(VPSRLVWRegRegReg, vpsrlvw, + BINARY(VEX_L128, VEX_vReg_, PREFIX_66, REX_W, ESCAPE_0F38, 0x10, 0, ModRM_RM__, Immediate_0), + PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SourceRegisterInModRM), + PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget | IA32OpProp1_SourceCanBeMemRef), + FEATURES(X86FeatureProp_EVEX128Supported | X86FeatureProp_EVEX128RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512VL | X86FeatureProp_EVEX256RequiresAVX512BW | + X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | X86FeatureProp_EVEX256RequiresAVX512BW | + X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F)), +INSTRUCTION(VPSRLVDRegRegReg, vpsrlvd, + BINARY(VEX_L128, VEX_vReg_, PREFIX_66, REX__, ESCAPE_0F38, 0x45, 0, ModRM_RM__, Immediate_0), + PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SourceRegisterInModRM), + PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget | IA32OpProp1_SourceCanBeMemRef), + FEATURES(X86FeatureProp_VEX128Supported | X86FeatureProp_VEX128RequiresAVX2 | X86FeatureProp_VEX256Supported | X86FeatureProp_VEX256RequiresAVX2 | + X86FeatureProp_EVEX128Supported | X86FeatureProp_EVEX128RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512VL | + X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | + X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F)), +INSTRUCTION(VPSRLVQRegRegReg, vpsrlvq, + BINARY(VEX_L128, VEX_vReg_, PREFIX_66, REX_W, ESCAPE_0F38, 0x45, 0, ModRM_RM__, Immediate_0), + PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SourceRegisterInModRM), + PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget | IA32OpProp1_SourceCanBeMemRef), + FEATURES(X86FeatureProp_VEX128Supported | X86FeatureProp_VEX128RequiresAVX2 | X86FeatureProp_VEX256Supported | X86FeatureProp_VEX256RequiresAVX2 | + X86FeatureProp_EVEX128Supported | X86FeatureProp_EVEX128RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512VL | + X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | + X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F)), +INSTRUCTION(VPROLVDRegRegReg, vprolvd, + BINARY(VEX_L128, VEX_vReg_, PREFIX_66, REX__, ESCAPE_0F38, 0x15, 0, ModRM_RM__, Immediate_0), + PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SourceRegisterInModRM), + PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget | IA32OpProp1_SourceCanBeMemRef), + FEATURES(X86FeatureProp_EVEX128Supported | X86FeatureProp_EVEX128RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512VL | + X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | + X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F)), +INSTRUCTION(VPROLVQRegRegReg, vprolvq, + BINARY(VEX_L128, VEX_vReg_, PREFIX_66, REX_W, ESCAPE_0F38, 0x15, 0, ModRM_RM__, Immediate_0), + PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SourceRegisterInModRM), + PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget | IA32OpProp1_SourceCanBeMemRef), + FEATURES(X86FeatureProp_EVEX128Supported | X86FeatureProp_EVEX128RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512VL | + X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | + X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F)), + +INSTRUCTION(VPRORVDRegRegReg, vprorvd, + BINARY(VEX_L128, VEX_vReg_, PREFIX_66, REX__, ESCAPE_0F38, 0x14, 0, ModRM_RM__, Immediate_0), + PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SourceRegisterInModRM), + PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget | IA32OpProp1_SourceCanBeMemRef), + FEATURES(X86FeatureProp_EVEX128Supported | X86FeatureProp_EVEX128RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512VL | + X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | + X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F)), +INSTRUCTION(VPRORVQRegRegReg, vprorvq, + BINARY(VEX_L128, VEX_vReg_, PREFIX_66, REX_W, ESCAPE_0F38, 0x14, 0, ModRM_RM__, Immediate_0), + PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_SourceRegisterInModRM), + PROPERTY1(IA32OpProp1_XMMSource | IA32OpProp1_XMMTarget | IA32OpProp1_SourceCanBeMemRef), + FEATURES(X86FeatureProp_EVEX128Supported | X86FeatureProp_EVEX128RequiresAVX512F | X86FeatureProp_EVEX128RequiresAVX512VL | + X86FeatureProp_EVEX256Supported | X86FeatureProp_EVEX256RequiresAVX512F | X86FeatureProp_EVEX256RequiresAVX512VL | + X86FeatureProp_EVEX512Supported | X86FeatureProp_EVEX512RequiresAVX512F)), INSTRUCTION(VPTERNLOGDRegMaskRegRegImm1, vpternlogd, BINARY(EVEX_L128, VEX_vReg_, PREFIX_66, REX__, ESCAPE_0F3A, 0x25, 0, ModRM_RM__, Immediate_1), PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_ByteImmediate | IA32OpProp_SourceRegisterInModRM), diff --git a/fvtest/compilertriltest/VectorTest.cpp b/fvtest/compilertriltest/VectorTest.cpp index eb32d16ac5..83ff6760da 100644 --- a/fvtest/compilertriltest/VectorTest.cpp +++ b/fvtest/compilertriltest/VectorTest.cpp @@ -1100,3 +1100,22 @@ INSTANTIATE_TEST_CASE_P(Long128ReductionTest, BinaryDataDriven128Int64Test, ::te std::make_tuple(TR::vreductionMax, BinaryLongTest { { 100 }, { 100, -100}, {}, }), std::make_tuple(TR::vreductionMax, BinaryLongTest { { 9223372036854775804 }, { 9223372036854775801, 9223372036854775804}, {}, }) ))); + +INSTANTIATE_TEST_CASE_P(Short128ShiftRotateTest, BinaryDataDriven128Int16Test, ::testing::ValuesIn(*TRTest::MakeVector>( + std::make_tuple(TR::vshl, BinaryShortTest { { 2, 2, 16, 0 }, { 1, 2, 4, 5}, { 1, 0, 2, 70}, }), + std::make_tuple(TR::vshr, BinaryShortTest { { 1, 4, 0, 4 }, { 2, 4, 8, 9}, { 1, 0, 10, 1 }, }), + std::make_tuple(TR::vrol, BinaryShortTest { { 7, 4, 8, 8193 }, { 0x7000, 4, 8, 9}, { 4, 0, 16, -3 }, }) +))); + +INSTANTIATE_TEST_CASE_P(Int128ShiftRotateTest, BinaryDataDriven128Int32Test, ::testing::ValuesIn(*TRTest::MakeVector>( + std::make_tuple(TR::vshl, BinaryIntTest { { 2, 2, 16, 0 }, { 1, 2, 4, 5}, { 1, 0, 2, 70}, }), + std::make_tuple(TR::vshr, BinaryIntTest { { 1, 4, 0, 4 }, { 2, 4, 8, 9}, { 1, 0, 10, 1 }, }), + std::make_tuple(TR::vrol, BinaryIntTest { { 7, 4, 8, 536870913 }, { 0x70000000, 4, 8, 9}, { 4, 0, 32, -3 }, }) +))); + +INSTANTIATE_TEST_CASE_P(Long128ShiftRotateTest, BinaryDataDriven128Int64Test, ::testing::ValuesIn(*TRTest::MakeVector>( + std::make_tuple(TR::vshl, BinaryLongTest { { 2, 2, 16, 0 }, { 1, 2, 4, 5}, { 1, 0, 2, 70}, }), + std::make_tuple(TR::vshr, BinaryLongTest { { 1, 4, 0, 4 }, { 2, 4, 8, 9}, { 1, 0, 10, 1 }, }), + std::make_tuple(TR::vrol, BinaryLongTest { { 30064771072, 4 }, { 0x70000000, 4}, { 4, 0 }, }), + std::make_tuple(TR::vrol, BinaryLongTest { { 8, 2305843009213693953 }, { 8, 9}, { 64, -3 }, }) +))); diff --git a/fvtest/compilerunittest/x/BinaryEncoder.cpp b/fvtest/compilerunittest/x/BinaryEncoder.cpp index be6457c890..639ab28376 100644 --- a/fvtest/compilerunittest/x/BinaryEncoder.cpp +++ b/fvtest/compilerunittest/x/BinaryEncoder.cpp @@ -552,6 +552,8 @@ TEST_P(XRegRegRegEncEncodingTest, encode) { INSTANTIATE_TEST_CASE_P(AVXRegRegRegSimdVEX128Test, XRegRegRegEncEncodingTest, ::testing::ValuesIn(*TRTest::MakeVector>( std::make_tuple(TR::InstOpCode::VFMADD213PDRegRegReg, TR::RealRegister::xmm0, TR::RealRegister::xmm1, TR::RealRegister::xmm0, OMR::X86::VEX_L128, "c4e2f1a8c0"), std::make_tuple(TR::InstOpCode::VFMADD213PSRegRegReg, TR::RealRegister::xmm1, TR::RealRegister::xmm0, TR::RealRegister::xmm1, OMR::X86::VEX_L128, "c4e279a8c9"), + std::make_tuple(TR::InstOpCode::VPSLLVDRegRegReg, TR::RealRegister::xmm3, TR::RealRegister::xmm2, TR::RealRegister::xmm2, OMR::X86::VEX_L128, "c4e26947da"), + std::make_tuple(TR::InstOpCode::VPSLLVQRegRegReg, TR::RealRegister::xmm4, TR::RealRegister::xmm3, TR::RealRegister::xmm3, OMR::X86::VEX_L128, "c4e2e147e3"), std::make_tuple(TR::InstOpCode::PCMPEQBRegReg, TR::RealRegister::xmm1, TR::RealRegister::xmm0, TR::RealRegister::xmm1, OMR::X86::VEX_L128, "c5f974c9"), std::make_tuple(TR::InstOpCode::PCMPEQWRegReg, TR::RealRegister::xmm1, TR::RealRegister::xmm0, TR::RealRegister::xmm1, OMR::X86::VEX_L128, "c5f975c9"), std::make_tuple(TR::InstOpCode::PCMPEQDRegReg, TR::RealRegister::xmm1, TR::RealRegister::xmm0, TR::RealRegister::xmm1, OMR::X86::VEX_L128, "c5f976c9"), @@ -587,6 +589,11 @@ INSTANTIATE_TEST_CASE_P(AVXRegRegRegSimdVEX128Test, XRegRegRegEncEncodingTest, : INSTANTIATE_TEST_CASE_P(AVXRegRegRegSimdVEX256Test, XRegRegRegEncEncodingTest, ::testing::ValuesIn(*TRTest::MakeVector>( std::make_tuple(TR::InstOpCode::VFMADD213PDRegRegReg, TR::RealRegister::ymm0, TR::RealRegister::ymm1, TR::RealRegister::ymm0, OMR::X86::VEX_L256, "c4e2f5a8c0"), std::make_tuple(TR::InstOpCode::VFMADD213PSRegRegReg, TR::RealRegister::ymm1, TR::RealRegister::ymm0, TR::RealRegister::ymm1, OMR::X86::VEX_L256, "c4e27da8c9"), + std::make_tuple(TR::InstOpCode::VPSLLVDRegRegReg, TR::RealRegister::ymm3, TR::RealRegister::ymm2, TR::RealRegister::ymm2, OMR::X86::VEX_L256, "c4e26d47da"), + std::make_tuple(TR::InstOpCode::VPSLLVQRegRegReg, TR::RealRegister::ymm4, TR::RealRegister::ymm3, TR::RealRegister::ymm3, OMR::X86::VEX_L256, "c4e2e547e3"), + std::make_tuple(TR::InstOpCode::VPSRAVDRegRegReg, TR::RealRegister::ymm3, TR::RealRegister::ymm2, TR::RealRegister::ymm2, OMR::X86::VEX_L256, "c4e26d46da"), + std::make_tuple(TR::InstOpCode::VPSRLVDRegRegReg, TR::RealRegister::ymm3, TR::RealRegister::ymm2, TR::RealRegister::ymm2, OMR::X86::VEX_L256, "c4e26d45da"), + std::make_tuple(TR::InstOpCode::VPSRLVQRegRegReg, TR::RealRegister::ymm4, TR::RealRegister::ymm3, TR::RealRegister::ymm3, OMR::X86::VEX_L256, "c4e2e545e3"), std::make_tuple(TR::InstOpCode::ORPDRegReg, TR::RealRegister::ymm0, TR::RealRegister::ymm15, TR::RealRegister::ymm15, OMR::X86::VEX_L256, "c4c18556c7"), std::make_tuple(TR::InstOpCode::PADDBRegReg, TR::RealRegister::ymm0, TR::RealRegister::ymm15, TR::RealRegister::ymm15, OMR::X86::VEX_L256, "c4c105fcc7"), std::make_tuple(TR::InstOpCode::PADDWRegReg, TR::RealRegister::ymm1, TR::RealRegister::ymm14, TR::RealRegister::ymm8, OMR::X86::VEX_L256, "c4c10dfdc8"), @@ -614,6 +621,19 @@ INSTANTIATE_TEST_CASE_P(AVXRegRegRegSimdVEX256Test, XRegRegRegEncEncodingTest, : INSTANTIATE_TEST_CASE_P(AVXRegRegRegSimdEVEX128Test, XRegRegRegEncEncodingTest, ::testing::ValuesIn(*TRTest::MakeVector>( std::make_tuple(TR::InstOpCode::VFMADD213PDRegRegReg, TR::RealRegister::xmm0, TR::RealRegister::xmm1, TR::RealRegister::xmm0, OMR::X86::EVEX_L128, "62f2f508a8c0"), std::make_tuple(TR::InstOpCode::VFMADD213PSRegRegReg, TR::RealRegister::xmm1, TR::RealRegister::xmm0, TR::RealRegister::xmm1, OMR::X86::EVEX_L128, "62f27d08a8c9"), + std::make_tuple(TR::InstOpCode::VPSLLVWRegRegReg, TR::RealRegister::xmm2, TR::RealRegister::xmm1, TR::RealRegister::xmm1, OMR::X86::EVEX_L128, "62f2f50812d1"), + std::make_tuple(TR::InstOpCode::VPSLLVDRegRegReg, TR::RealRegister::xmm3, TR::RealRegister::xmm2, TR::RealRegister::xmm2, OMR::X86::EVEX_L128, "62f26d0847da"), + std::make_tuple(TR::InstOpCode::VPSLLVQRegRegReg, TR::RealRegister::xmm4, TR::RealRegister::xmm3, TR::RealRegister::xmm3, OMR::X86::EVEX_L128, "62f2e50847e3"), + std::make_tuple(TR::InstOpCode::VPSRAVWRegRegReg, TR::RealRegister::xmm0, TR::RealRegister::xmm1, TR::RealRegister::xmm1, OMR::X86::EVEX_L128, "62f2f50811c1"), + std::make_tuple(TR::InstOpCode::VPSRAVDRegRegReg, TR::RealRegister::xmm1, TR::RealRegister::xmm8, TR::RealRegister::xmm8, OMR::X86::EVEX_L128, "62d23d0846c8"), + std::make_tuple(TR::InstOpCode::VPSRAVQRegRegReg, TR::RealRegister::xmm2, TR::RealRegister::xmm15, TR::RealRegister::xmm15, OMR::X86::EVEX_L128, "62d2850846d7"), + std::make_tuple(TR::InstOpCode::VPSRLVWRegRegReg, TR::RealRegister::xmm3, TR::RealRegister::xmm1, TR::RealRegister::xmm1, OMR::X86::EVEX_L128, "62f2f50810d9"), + std::make_tuple(TR::InstOpCode::VPSRLVDRegRegReg, TR::RealRegister::xmm4, TR::RealRegister::xmm2, TR::RealRegister::xmm2, OMR::X86::EVEX_L128, "62f26d0845e2"), + std::make_tuple(TR::InstOpCode::VPSRLVQRegRegReg, TR::RealRegister::xmm5, TR::RealRegister::xmm3, TR::RealRegister::xmm3, OMR::X86::EVEX_L128, "62f2e50845eb"), + std::make_tuple(TR::InstOpCode::VPROLVDRegRegReg, TR::RealRegister::xmm2, TR::RealRegister::xmm15, TR::RealRegister::xmm15, OMR::X86::EVEX_L128, "62d2050815d7"), + std::make_tuple(TR::InstOpCode::VPROLVQRegRegReg, TR::RealRegister::xmm3, TR::RealRegister::xmm1, TR::RealRegister::xmm1, OMR::X86::EVEX_L128, "62f2f50815d9"), + std::make_tuple(TR::InstOpCode::VPRORVDRegRegReg, TR::RealRegister::xmm4, TR::RealRegister::xmm2, TR::RealRegister::xmm2, OMR::X86::EVEX_L128, "62f26d0814e2"), + std::make_tuple(TR::InstOpCode::VPRORVQRegRegReg, TR::RealRegister::xmm5, TR::RealRegister::xmm3, TR::RealRegister::xmm3, OMR::X86::EVEX_L128, "62f2e50814eb"), std::make_tuple(TR::InstOpCode::ORPDRegReg, TR::RealRegister::xmm0, TR::RealRegister::xmm15, TR::RealRegister::xmm15, OMR::X86::EVEX_L128, "62d1850856c7"), std::make_tuple(TR::InstOpCode::PADDBRegReg, TR::RealRegister::xmm0, TR::RealRegister::xmm15, TR::RealRegister::xmm15, OMR::X86::EVEX_L128, "62d10508fcc7"), std::make_tuple(TR::InstOpCode::PADDWRegReg, TR::RealRegister::xmm1, TR::RealRegister::xmm14, TR::RealRegister::xmm8, OMR::X86::EVEX_L128, "62d10d08fdc8"), @@ -641,6 +661,19 @@ INSTANTIATE_TEST_CASE_P(AVXRegRegRegSimdEVEX128Test, XRegRegRegEncEncodingTest, INSTANTIATE_TEST_CASE_P(AVXRegRegRegSimdEVEX256Test, XRegRegRegEncEncodingTest, ::testing::ValuesIn(*TRTest::MakeVector>( std::make_tuple(TR::InstOpCode::VFMADD213PDRegRegReg, TR::RealRegister::ymm0, TR::RealRegister::ymm1, TR::RealRegister::ymm0, OMR::X86::EVEX_L256, "62f2f528a8c0"), std::make_tuple(TR::InstOpCode::VFMADD213PSRegRegReg, TR::RealRegister::ymm1, TR::RealRegister::ymm0, TR::RealRegister::ymm1, OMR::X86::EVEX_L256, "62f27d28a8c9"), + std::make_tuple(TR::InstOpCode::VPSLLVWRegRegReg, TR::RealRegister::ymm2, TR::RealRegister::ymm1, TR::RealRegister::ymm1, OMR::X86::EVEX_L256, "62f2f52812d1"), + std::make_tuple(TR::InstOpCode::VPSLLVDRegRegReg, TR::RealRegister::ymm3, TR::RealRegister::ymm2, TR::RealRegister::ymm2, OMR::X86::EVEX_L256, "62f26d2847da"), + std::make_tuple(TR::InstOpCode::VPSLLVQRegRegReg, TR::RealRegister::ymm4, TR::RealRegister::ymm3, TR::RealRegister::ymm3, OMR::X86::EVEX_L256, "62f2e52847e3"), + std::make_tuple(TR::InstOpCode::VPSRAVWRegRegReg, TR::RealRegister::ymm0, TR::RealRegister::ymm1, TR::RealRegister::ymm1, OMR::X86::EVEX_L256, "62f2f52811c1"), + std::make_tuple(TR::InstOpCode::VPSRAVDRegRegReg, TR::RealRegister::ymm1, TR::RealRegister::ymm8, TR::RealRegister::ymm8, OMR::X86::EVEX_L256, "62d23d2846c8"), + std::make_tuple(TR::InstOpCode::VPSRAVQRegRegReg, TR::RealRegister::ymm2, TR::RealRegister::ymm15, TR::RealRegister::ymm15, OMR::X86::EVEX_L256, "62d2852846d7"), + std::make_tuple(TR::InstOpCode::VPSRLVWRegRegReg, TR::RealRegister::ymm3, TR::RealRegister::ymm1, TR::RealRegister::ymm1, OMR::X86::EVEX_L256, "62f2f52810d9"), + std::make_tuple(TR::InstOpCode::VPSRLVDRegRegReg, TR::RealRegister::ymm4, TR::RealRegister::ymm2, TR::RealRegister::ymm2, OMR::X86::EVEX_L256, "62f26d2845e2"), + std::make_tuple(TR::InstOpCode::VPSRLVQRegRegReg, TR::RealRegister::ymm5, TR::RealRegister::ymm3, TR::RealRegister::ymm3, OMR::X86::EVEX_L256, "62f2e52845eb"), + std::make_tuple(TR::InstOpCode::VPROLVDRegRegReg, TR::RealRegister::ymm2, TR::RealRegister::ymm15, TR::RealRegister::ymm15, OMR::X86::EVEX_L256, "62d2052815d7"), + std::make_tuple(TR::InstOpCode::VPROLVQRegRegReg, TR::RealRegister::ymm3, TR::RealRegister::ymm1, TR::RealRegister::ymm1, OMR::X86::EVEX_L256, "62f2f52815d9"), + std::make_tuple(TR::InstOpCode::VPRORVDRegRegReg, TR::RealRegister::ymm4, TR::RealRegister::ymm2, TR::RealRegister::ymm2, OMR::X86::EVEX_L256, "62f26d2814e2"), + std::make_tuple(TR::InstOpCode::VPRORVQRegRegReg, TR::RealRegister::ymm5, TR::RealRegister::ymm3, TR::RealRegister::ymm3, OMR::X86::EVEX_L256, "62f2e52814eb"), std::make_tuple(TR::InstOpCode::ORPDRegReg, TR::RealRegister::ymm0, TR::RealRegister::ymm15, TR::RealRegister::ymm15, OMR::X86::EVEX_L256, "62d1852856c7"), std::make_tuple(TR::InstOpCode::PADDBRegReg, TR::RealRegister::ymm0, TR::RealRegister::ymm15, TR::RealRegister::ymm15, OMR::X86::EVEX_L256, "62d10528fcc7"), std::make_tuple(TR::InstOpCode::PADDWRegReg, TR::RealRegister::ymm1, TR::RealRegister::ymm14, TR::RealRegister::ymm8, OMR::X86::EVEX_L256, "62d10d28fdc8"), @@ -668,6 +701,19 @@ INSTANTIATE_TEST_CASE_P(AVXRegRegRegSimdEVEX256Test, XRegRegRegEncEncodingTest, INSTANTIATE_TEST_CASE_P(AVXRegRegRegSimdEVEX512Test, XRegRegRegEncEncodingTest, ::testing::ValuesIn(*TRTest::MakeVector>( std::make_tuple(TR::InstOpCode::VFMADD213PDRegRegReg, TR::RealRegister::zmm0, TR::RealRegister::zmm1, TR::RealRegister::zmm0, OMR::X86::EVEX_L512, "62f2f548a8c0"), std::make_tuple(TR::InstOpCode::VFMADD213PSRegRegReg, TR::RealRegister::zmm1, TR::RealRegister::zmm0, TR::RealRegister::zmm1, OMR::X86::EVEX_L512, "62f27d48a8c9"), + std::make_tuple(TR::InstOpCode::VPSLLVWRegRegReg, TR::RealRegister::zmm2, TR::RealRegister::zmm1, TR::RealRegister::zmm1, OMR::X86::EVEX_L512, "62f2f54812d1"), + std::make_tuple(TR::InstOpCode::VPSLLVDRegRegReg, TR::RealRegister::zmm3, TR::RealRegister::zmm2, TR::RealRegister::zmm2, OMR::X86::EVEX_L512, "62f26d4847da"), + std::make_tuple(TR::InstOpCode::VPSLLVQRegRegReg, TR::RealRegister::zmm4, TR::RealRegister::zmm3, TR::RealRegister::zmm3, OMR::X86::EVEX_L512, "62f2e54847e3"), + std::make_tuple(TR::InstOpCode::VPSRAVWRegRegReg, TR::RealRegister::zmm0, TR::RealRegister::zmm1, TR::RealRegister::zmm1, OMR::X86::EVEX_L512, "62f2f54811c1"), + std::make_tuple(TR::InstOpCode::VPSRAVDRegRegReg, TR::RealRegister::zmm1, TR::RealRegister::zmm8, TR::RealRegister::zmm8, OMR::X86::EVEX_L512, "62d23d4846c8"), + std::make_tuple(TR::InstOpCode::VPSRAVQRegRegReg, TR::RealRegister::zmm2, TR::RealRegister::zmm15, TR::RealRegister::zmm15, OMR::X86::EVEX_L512, "62d2854846d7"), + std::make_tuple(TR::InstOpCode::VPSRLVWRegRegReg, TR::RealRegister::zmm3, TR::RealRegister::zmm1, TR::RealRegister::zmm1, OMR::X86::EVEX_L512, "62f2f54810d9"), + std::make_tuple(TR::InstOpCode::VPSRLVDRegRegReg, TR::RealRegister::zmm4, TR::RealRegister::zmm2, TR::RealRegister::zmm2, OMR::X86::EVEX_L512, "62f26d4845e2"), + std::make_tuple(TR::InstOpCode::VPSRLVQRegRegReg, TR::RealRegister::zmm5, TR::RealRegister::zmm3, TR::RealRegister::zmm3, OMR::X86::EVEX_L512, "62f2e54845eb"), + std::make_tuple(TR::InstOpCode::VPROLVDRegRegReg, TR::RealRegister::zmm2, TR::RealRegister::zmm15, TR::RealRegister::zmm15, OMR::X86::EVEX_L512, "62d2054815d7"), + std::make_tuple(TR::InstOpCode::VPROLVQRegRegReg, TR::RealRegister::zmm3, TR::RealRegister::zmm1, TR::RealRegister::zmm1, OMR::X86::EVEX_L512, "62f2f54815d9"), + std::make_tuple(TR::InstOpCode::VPRORVDRegRegReg, TR::RealRegister::zmm4, TR::RealRegister::zmm2, TR::RealRegister::zmm2, OMR::X86::EVEX_L512, "62f26d4814e2"), + std::make_tuple(TR::InstOpCode::VPRORVQRegRegReg, TR::RealRegister::zmm5, TR::RealRegister::zmm3, TR::RealRegister::zmm3, OMR::X86::EVEX_L512, "62f2e54814eb"), std::make_tuple(TR::InstOpCode::ORPDRegReg, TR::RealRegister::zmm0, TR::RealRegister::zmm15, TR::RealRegister::zmm15, OMR::X86::EVEX_L512, "62d1854856c7"), std::make_tuple(TR::InstOpCode::PADDBRegReg, TR::RealRegister::zmm0, TR::RealRegister::zmm15, TR::RealRegister::zmm15, OMR::X86::EVEX_L512, "62d10548fcc7"), std::make_tuple(TR::InstOpCode::PADDWRegReg, TR::RealRegister::zmm1, TR::RealRegister::zmm14, TR::RealRegister::zmm8, OMR::X86::EVEX_L512, "62d10d48fdc8"),