From bfb09be0e890b08a6dca12604ffd9314136b0121 Mon Sep 17 00:00:00 2001 From: Dhruv Chopra Date: Thu, 19 Sep 2019 13:40:00 -0400 Subject: [PATCH] Fix register order when generating SELECT instruction The masks for the SELECT instruction are generated such that the false result in a ternary is favored. Thus, the register order needs to be rearranged when generating the instruction. Signed-off-by: Dhruv Chopra --- compiler/z/codegen/ControlFlowEvaluator.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/z/codegen/ControlFlowEvaluator.cpp b/compiler/z/codegen/ControlFlowEvaluator.cpp index 0c53e13849..a8a8ccec32 100644 --- a/compiler/z/codegen/ControlFlowEvaluator.cpp +++ b/compiler/z/codegen/ControlFlowEvaluator.cpp @@ -3035,7 +3035,7 @@ OMR::Z::TreeEvaluator::ternaryEvaluator(TR::Node *node, TR::CodeGenerator *cg) generateRRInstruction(cg, compareOp, node, firstReg, secondReg); auto mnemonic = trueVal->getOpCode().is8Byte() ? TR::InstOpCode::SELGR : TR::InstOpCode::SELR; - generateRRFInstruction(cg, mnemonic, node, trueReg, trueReg, falseReg, getMaskForBranchCondition(TR::TreeEvaluator::mapBranchConditionToLOCRCondition(bc))); + generateRRFInstruction(cg, mnemonic, node, trueReg, falseReg, trueReg, getMaskForBranchCondition(TR::TreeEvaluator::mapBranchConditionToLOCRCondition(bc))); } else if (TR::Compiler->target.cpu.getSupportsArch(TR::CPU::z196)) { @@ -3101,7 +3101,7 @@ OMR::Z::TreeEvaluator::ternaryEvaluator(TR::Node *node, TR::CodeGenerator *cg) if (TR::Compiler->target.cpu.getSupportsArch(TR::CPU::z15)) { auto mnemonic = trueVal->getOpCode().is8Byte() ? TR::InstOpCode::SELGR : TR::InstOpCode::SELR; - generateRRFInstruction(cg, mnemonic, node, trueReg, trueReg, falseReg, getMaskForBranchCondition(TR::InstOpCode::COND_BER)); + generateRRFInstruction(cg, mnemonic, node, trueReg, falseReg, trueReg, getMaskForBranchCondition(TR::InstOpCode::COND_BER)); } else if (TR::Compiler->target.cpu.getSupportsArch(TR::CPU::z196)) {