diff --git a/include_core/omrport.h b/include_core/omrport.h index c437be500d..0d56be809e 100644 --- a/include_core/omrport.h +++ b/include_core/omrport.h @@ -1172,42 +1172,91 @@ typedef struct OMROSKernelInfo { typedef enum OMRProcessorArchitecture { OMR_PROCESSOR_UNDEFINED, + OMR_PROCESSOR_FIRST, - OMR_PROCESSOR_S390_UNKNOWN, + // 390 Processors + OMR_PROCESSOR_S390_FIRST = OMR_PROCESSOR_FIRST, + OMR_PROCESSOR_S390_UNKNOWN = OMR_PROCESSOR_S390_FIRST, OMR_PROCESSOR_S390_GP6, + OMR_PROCESSOR_S390_Z10 = OMR_PROCESSOR_S390_GP6, OMR_PROCESSOR_S390_GP7, OMR_PROCESSOR_S390_GP8, OMR_PROCESSOR_S390_GP9, + OMR_PROCESSOR_S390_Z196 = OMR_PROCESSOR_S390_GP9, OMR_PROCESSOR_S390_GP10, + OMR_PROCESSOR_S390_ZEC12 = OMR_PROCESSOR_S390_GP10, OMR_PROCESSOR_S390_GP11, + OMR_PROCESSOR_S390_Z13 = OMR_PROCESSOR_S390_GP11, OMR_PROCESSOR_S390_GP12, + OMR_PROCESSOR_S390_Z14 = OMR_PROCESSOR_S390_GP12, OMR_PROCESSOR_S390_GP13, + OMR_PROCESSOR_S390_Z15 = OMR_PROCESSOR_S390_GP13, OMR_PROCESSOR_S390_GP14, - - OMR_PROCESSOR_PPC_UNKNOWN, - OMR_PROCESSOR_PPC_7XX, - OMR_PROCESSOR_PPC_GP, - OMR_PROCESSOR_PPC_GR, - OMR_PROCESSOR_PPC_NSTAR, - OMR_PROCESSOR_PPC_PULSAR, + OMR_PROCESSOR_S390_ZNEXT = OMR_PROCESSOR_S390_GP14, + OMR_PROCESSOR_S390_LAST = OMR_PROCESSOR_S390_GP14, + + // ARM Processors + OMR_PROCESSOR_ARM_FIRST, + OMR_PROCESSOR_ARM_UNKNOWN = OMR_PROCESSOR_ARM_FIRST, + OMR_PROCESSOR_ARM_V6, + OMR_PROCESSOR_ARM_V7, + OMR_PROCESSOR_ARM_LAST = OMR_PROCESSOR_ARM_V7, + + // ARM64 / AARCH64 Processors + OMR_PROCESSOR_ARM64_FISRT, + OMR_PROCESSOR_ARM64_UNKNOWN = OMR_PROCESSOR_ARM64_FISRT, + OMR_PROCESSOR_ARM64_V8_A, + OMR_PROCESSOR_ARM64_LAST = OMR_PROCESSOR_ARM64_V8_A, + + // PPC Processors + OMR_PROCESSOR_PPC_FIRST, + OMR_PROCESSOR_PPC_UNKNOWN = OMR_PROCESSOR_PPC_FIRST, + OMR_PROCESSOR_PPC_RIOS1, OMR_PROCESSOR_PPC_PWR403, OMR_PROCESSOR_PPC_PWR405, OMR_PROCESSOR_PPC_PWR440, OMR_PROCESSOR_PPC_PWR601, OMR_PROCESSOR_PPC_PWR602, OMR_PROCESSOR_PPC_PWR603, + OMR_PROCESSOR_PPC_82XX, + OMR_PROCESSOR_PPC_7XX, OMR_PROCESSOR_PPC_PWR604, - OMR_PROCESSOR_PPC_PWR620, + // The following processors support SQRT in hardware + OMR_PROCESSOR_PPC_HW_SQRT_FIRST, + OMR_PROCESSOR_PPC_RIOS2 = OMR_PROCESSOR_PPC_HW_SQRT_FIRST, + OMR_PROCESSOR_PPC_PWR2S, + // The following processors are 64-bit implementations + OMR_PROCESSOR_PPC_64BIT_FIRST, + OMR_PROCESSOR_PPC_PWR620 = OMR_PROCESSOR_PPC_64BIT_FIRST, OMR_PROCESSOR_PPC_PWR630, - OMR_PROCESSOR_PPC_RIOS1, - OMR_PROCESSOR_PPC_RIOS2, - OMR_PROCESSOR_PPC_P6, - OMR_PROCESSOR_PPC_P7, + OMR_PROCESSOR_PPC_NSTAR, + OMR_PROCESSOR_PPC_PULSAR, + // The following processors support the PowerPC AS architecture + // PPC AS includes the new branch hint 'a' and 't' bits + OMR_PROCESSOR_PPC_AS_FIRST, + OMR_PROCESSOR_PPC_GP = OMR_PROCESSOR_PPC_AS_FIRST, + OMR_PROCESSOR_PPC_GR, + // The following processors support VMX + OMR_PROCESSOR_PPC_VMX_FIRST, + OMR_PROCESSOR_PPC_GPUL = OMR_PROCESSOR_PPC_VMX_FIRST, + OMR_PROCESSOR_PPC_HW_ROUND_FIRST, + OMR_PROCESSOR_PPC_HW_COPY_SIGN_FIRST = OMR_PROCESSOR_PPC_HW_ROUND_FIRST, + OMR_PROCESSOR_PPC_P6 = OMR_PROCESSOR_PPC_HW_COPY_SIGN_FIRST, + OMR_PROCESOSR_PPC_ATLAS, + OMR_PROCESSOR_PPC_BALANCED, + OMR_PROCESSOR_PPC_CELLPX, + // The following processors support VSX + OMR_PROCESSOR_PPC_VSX_FIRST, + OMR_PROCESSOR_PPC_P7 = OMR_PROCESSOR_PPC_VSX_FIRST, OMR_PROCESSOR_PPC_P8, OMR_PROCESSOR_PPC_P9, + OMR_PROCESSOR_PPC_LAST = OMR_PROCESSOR_PPC_P9, - OMR_PROCESSOR_X86_UNKNOWN, - OMR_PROCESSOR_X86_INTELPENTIUM, + // X86 Processors + OMR_PROCESSOR_X86_FIRST, + OMR_PROCESSOR_X86_UNKNOWN = OMR_PROCESSOR_X86_FIRST, + OMR_PROCESSOR_X86_INTEL_FIRST, + OMR_PROCESSOR_X86_INTELPENTIUM = OMR_PROCESSOR_X86_INTEL_FIRST, OMR_PROCESSOR_X86_INTELP6, OMR_PROCESSOR_X86_INTELPENTIUM4, OMR_PROCESSOR_X86_INTELCORE2, @@ -1215,11 +1264,19 @@ typedef enum OMRProcessorArchitecture { OMR_PROCESSOR_X86_INTELNEHALEM, OMR_PROCESSOR_X86_INTELWESTMERE, OMR_PROCESSOR_X86_INTELSANDYBRIDGE, + OMR_PROCESSOR_X86_INTELIVYBRIDGE, OMR_PROCESSOR_X86_INTELHASWELL, - OMR_PROCESSOR_X86_AMDK5, + OMR_PROCESSOR_X86_INTELBROADWELL, + OMR_PROCESSOR_X86_INTELSKYLAKE, + OMR_PROCESSOR_X86_INTEL_LAST = OMR_PROCESSOR_X86_INTELSKYLAKE, + OMR_PROCESSOR_X86_AMD_FIRST, + OMR_PROCESSOR_X86_AMDK5 = OMR_PROCESSOR_X86_AMD_FIRST, OMR_PROCESSOR_X86_AMDK6, OMR_PROCESSOR_X86_AMDATHLONDURON, OMR_PROCESSOR_X86_AMDOPTERON, + OMR_PROCESSOR_X86_AMDFAMILY15H, + OMR_PROCESSOR_X86_AMD_LAST = OMR_PROCESSOR_X86_AMDFAMILY15H, + OMR_PROCESSOR_X86_LAST = OMR_PROCESSOR_X86_AMDFAMILY15H, OMR_PROCESOR_RISCV32_UNKNOWN, OMR_PROCESOR_RISCV64_UNKNOWN, @@ -1228,8 +1285,8 @@ typedef enum OMRProcessorArchitecture { } OMRProcessorArchitecture; -/* Holds processor type and features used with j9sysinfo_get_processor_description - * and j9sysinfo_processor_has_feature +/* Holds processor type and features used with omrsysinfo_get_processor_description + * and omrsysinfo_processor_has_feature */ #define OMRPORT_SYSINFO_FEATURES_SIZE 5 typedef struct OMRProcessorDesc { @@ -1419,7 +1476,7 @@ typedef struct OMRProcessorDesc { #define OMR_FEATURE_X86_MCE 7 /* Machine Check Exception. */ #define OMR_FEATURE_X86_CX8 8 /* Compare-and-exchange 8 bytes (64 bits) instruction */ #define OMR_FEATURE_X86_APIC 9 /* APIC On-Chip. */ -#define OMR_FEATURE_X86_10 10 /* Reserved */ +#define OMR_FEATURE_X86_0_10 10 /* Reserved */ #define OMR_FEATURE_X86_SEP 11 /* SYSENTER and SYSEXIT Instructions. */ #define OMR_FEATURE_X86_MTRR 12 /* Memory Type Range Registers. */ #define OMR_FEATURE_X86_PGE 13 /* Page Global Bit. */ @@ -1429,7 +1486,7 @@ typedef struct OMRProcessorDesc { #define OMR_FEATURE_X86_PSE_36 17 /* 36-Bit Page Size Extension. */ #define OMR_FEATURE_X86_PSN 18 /* Processor Serial Number. */ #define OMR_FEATURE_X86_CLFSH 19 /* CLFLUSH Instruction. */ -#define OMR_FEATURE_X86_20 20 /* Reserved */ +#define OMR_FEATURE_X86_0_20 20 /* Reserved */ #define OMR_FEATURE_X86_DS 21 /* Debug Store. */ #define OMR_FEATURE_X86_ACPI 22 /* Thermal Monitor and Software Controlled Clock Facilities. */ #define OMR_FEATURE_X86_MMX 23 /* Intel MMX Technology. */ @@ -1439,7 +1496,7 @@ typedef struct OMRProcessorDesc { #define OMR_FEATURE_X86_SS 27 /* Self Snoop. */ #define OMR_FEATURE_X86_HTT 28 /* Hyper Threading. */ #define OMR_FEATURE_X86_TM 29 /* Thermal Monitor. */ -#define OMR_FEATURE_X86_30 30 /* Reserved */ +#define OMR_FEATURE_X86_0_30 30 /* Reserved */ #define OMR_FEATURE_X86_PBE 31 /* Pending Break Enable. */ /* INTEL INSTRUCTION SET REFERENCE, A-M @@ -1456,12 +1513,12 @@ typedef struct OMRProcessorDesc { #define OMR_FEATURE_X86_TM2 32 + 8 /* Thermal Monitor 2. */ #define OMR_FEATURE_X86_SSSE3 32 + 9 /* Supplemental Streaming SIMD Extensions 3 */ #define OMR_FEATURE_X86_CNXT_ID 32 + 10 /* L1 Context ID. */ -#define OMR_FEATURE_X86_11 32 + 11 /* Reserved */ +#define OMR_FEATURE_X86_SDBG 32 + 11 /* Processor supports IA32_DEBUG_INTERFACE MSR for silicon debug. */ #define OMR_FEATURE_X86_FMA 32 + 12 /* FMA extensions using YMM state. */ #define OMR_FEATURE_X86_CMPXCHG16B 32 + 13 /* CMPXCHG16B Available. */ #define OMR_FEATURE_X86_XTPR 32 + 14 /* xTPR Update Control. */ #define OMR_FEATURE_X86_PDCM 32 + 15 /* Perfmon and Debug Capability. */ -#define OMR_FEATURE_X86_16 32 + 16 /* Reserved. */ +#define OMR_FEATURE_X86_1_16 32 + 16 /* Reserved. */ #define OMR_FEATURE_X86_PCID 32 + 17 /* Process-context identifiers. */ #define OMR_FEATURE_X86_DCA 32 + 18 /* Processor supports the ability to prefetch data from a memory mapped device. */ #define OMR_FEATURE_X86_SSE4_1 32 + 19 /* Processor supports SSE4.1. */ @@ -1476,6 +1533,45 @@ typedef struct OMRProcessorDesc { #define OMR_FEATURE_X86_AVX 32 + 28 /* Processor supports the AVX instruction extensions. */ #define OMR_FEATURE_X86_F16C 32 + 29 /* 16-bit floating-point conversion instructions. */ #define OMR_FEATURE_X86_RDRAND 32 + 30 /* Processor supports RDRAND instruction. */ +#define OMR_FEATURE_X86_1_31 32 + 31 /* Not used */ + + +/* INTEL INSTRUCTION SET REFERENCE, A-M + * Vol. 2A 3-194 Table 3-8. Feature Information Returned in the EBX Register + */ +#define OMR_FEATURE_X86_FSGSBASE 64 + 0 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ +#define OMR_FEATURE_X86_IA32_TSC_ADJUST 64 + 1 /* MSR is supported if 1 */ +#define OMR_FEATURE_X86_SGX 64 + 2 /* Software Guard Extensions */ +#define OMR_FEATURE_X86_BMI1 64 + 3 /* BMI1 */ +#define OMR_FEATURE_X86_HLE 64 + 4 /* HLE */ +#define OMR_FEATURE_X86_AVX2 64 + 5 /* AVX2 */ +#define OMR_FEATURE_X86_FDP_EXCPTN_ONLY 64 + 6 /* x87 FPU Data Pointer updated only on x87 exceptions if 1 */ +#define OMR_FEATURE_X86_SMEP 64 + 7 /* Supervisor-Mode Execution Prevention */ +#define OMR_FEATURE_X86_BMI2 64 + 8 /* BMI2 */ +#define OMR_FEATURE_X86_ERMSB 64 + 9 /* Enhanced REP MOVSB/STOSB */ +#define OMR_FEATURE_X86_INVPCID 64 + 10 /* Processor supports INVPCID instruction for system software that manages process-context +identifiers */ +#define OMR_FEATURE_X86_RTM 64 + 11 /* RTM */ +#define OMR_FEATURE_X86_RDT_M 64 + 12 /* Processor supports Intel Resource Director Technology Monitoring */ +#define OMR_FEATURE_X86_DEPRECATES_FPUCSDS 64 + 13 /* Deprecates FPU CS and FPU DS values */ +#define OMR_FEATURE_X86_MPX 64 + 14 /* Processor supports Intel Memory Protection Extensions */ +#define OMR_FEATURE_X86_RDT_A 64 + 15 /* Processor supports Intel Resource Director Technology Allocation capability */ +#define OMR_FEATURE_X86_2_16 64 + 16 /* Reserved */ +#define OMR_FEATURE_X86_2_17 64 + 17 /* Reserved */ +#define OMR_FEATURE_X86_RDSEED 64 + 18 /* RDSEED */ +#define OMR_FEATURE_X86_ADX 64 + 19 /* ADX */ +#define OMR_FEATURE_X86_SMAP 64 + 20 /* Processor supports Supervisor-Mode Access Prevention */ +#define OMR_FEATURE_X86_2_21 64 + 21 /* Reserved */ +#define OMR_FEATURE_X86_2_22 64 + 22 /* Reserved */ +#define OMR_FEATURE_X86_CLFLUSHOPT 64 + 23 /* CLFLUSHOPT */ +#define OMR_FEATURE_X86_CLWB 64 + 24 /* CLWB */ +#define OMR_FEATURE_INTEL_PROCESSOR_TRACE 64 + 25 /* Intel Processor Trace */ +#define OMR_FEATURE_X86_2_26 64 + 26 /* Reserved */ +#define OMR_FEATURE_X86_2_27 64 + 27 /* Reserved */ +#define OMR_FEATURE_X86_2_28 64 + 28 /* Reserved */ +#define OMR_FEATURE_X86_SHA 64 + 29 /* Processor supports Intel Secure Hash Algorithm extensions */ +#define OMR_FEATURE_X86_2_30 64 + 30 /* Reserved */ +#define OMR_FEATURE_X86_2_31 64 + 31 /* Reserved */ struct OMRPortLibrary; typedef struct J9Heap J9Heap; diff --git a/port/common/omrsysinfo_helpers.c b/port/common/omrsysinfo_helpers.c index 4dad82a901..f1cf19145c 100644 --- a/port/common/omrsysinfo_helpers.c +++ b/port/common/omrsysinfo_helpers.c @@ -32,43 +32,77 @@ #include "portnls.h" #include -#if defined(WIN32) + +#if (defined(J9X86) || defined(J9HAMMER)) +#if defined(OMR_OS_WINDOWS) #include -#endif /* defined(WIN32) */ +#define cpuid(CPUInfo, EAXValue) __cpuid(CPUInfo, EAXValue) +#define cpuidex(CPUInfo, EAXValue, ECXValue) __cpuidex(CPUInfo, EAXValue, ECXValue) +#else +#include +#include +#define cpuid(CPUInfo, EAXValue) __cpuid(EAXValue, CPUInfo[0], CPUInfo[1], CPUInfo[2], CPUInfo[3]) +#define cpuidex(CPUInfo, EAXValue, ECXValue) __cpuid_count(EAXValue, ECXValue, CPUInfo[0], CPUInfo[1], CPUInfo[2], CPUInfo[3]) +inline unsigned long long _xgetbv(unsigned int ecx) +{ + unsigned int eax, edx; + __asm__ __volatile__("xgetbv" : "=a"(eax), "=d"(edx) : "c"(ecx)); + return ((unsigned long long)edx << 32) | eax; +} +#endif /* defined(OMR_OS_WINDOWS) */ /* defines for the CPUID instruction */ -#define CPUID_VENDOR_INFO 0 -#define CPUID_FAMILY_INFO 1 - -#define CPUID_VENDOR_INTEL "GenuineIntel" -#define CPUID_VENDOR_AMD "AuthenticAMD" -#define CPUID_VENDOR_LENGTH 12 - -#define CPUID_SIGNATURE_FAMILY 0x00000F00 -#define CPUID_SIGNATURE_MODEL 0x000000F0 -#define CPUID_SIGNATURE_EXTENDEDMODEL 0x000F0000 - -#define CPUID_SIGNATURE_FAMILY_SHIFT 8 -#define CPUID_SIGNATURE_MODEL_SHIFT 4 -#define CPUID_SIGNATURE_EXTENDEDMODEL_SHIFT 12 - -#define CPUID_FAMILYCODE_INTELPENTIUM 0x05 -#define CPUID_FAMILYCODE_INTELCORE 0x06 -#define CPUID_FAMILYCODE_INTELPENTIUM4 0x0F - -#define CPUID_MODELCODE_INTELHASWELL 0x3A -#define CPUID_MODELCODE_SANDYBRIDGE 0x2A -#define CPUID_MODELCODE_INTELWESTMERE 0x25 -#define CPUID_MODELCODE_INTELNEHALEM 0x1E -#define CPUID_MODELCODE_INTELCORE2 0x0F - -#define CPUID_FAMILYCODE_AMDKSERIES 0x05 -#define CPUID_FAMILYCODE_AMDATHLON 0x06 -#define CPUID_FAMILYCODE_AMDOPTERON 0x0F - -#define CPUID_MODELCODE_AMDK5 0x04 - -static void omrsysinfo_get_x86_cpuid(uint32_t leaf, uint32_t *cpuInfo); +#define CPUID_EAX 0 +#define CPUID_EBX 1 +#define CPUID_ECX 2 +#define CPUID_EDX 3 + +#define CPUID_VENDOR_INFO 0 +#define CPUID_FAMILY_INFO 1 + +#define CPUID_VENDOR_INTEL "GenuineIntel" +#define CPUID_VENDOR_AMD "AuthenticAMD" +#define CPUID_VENDOR_LENGTH 12 + +#define CPUID_SIGNATURE_STEPPING 0x0000000F +#define CPUID_SIGNATURE_MODEL 0x000000F0 +#define CPUID_SIGNATURE_FAMILY 0x00000F00 +#define CPUID_SIGNATURE_PROCESSOR 0x00003000 +#define CPUID_SIGNATURE_EXTENDEDMODEL 0x000F0000 +#define CPUID_SIGNATURE_EXTENDEDFAMILY 0x0FF00000 + +#define CPUID_SIGNATURE_STEPPING_SHIFT 0 +#define CPUID_SIGNATURE_MODEL_SHIFT 4 +#define CPUID_SIGNATURE_FAMILY_SHIFT 8 +#define CPUID_SIGNATURE_PROCESSOR_SHIFT 12 +#define CPUID_SIGNATURE_EXTENDEDMODEL_SHIFT 16 +#define CPUID_SIGNATURE_EXTENDEDFAMILY_SHIFT 20 + +#define CPUID_FAMILYCODE_INTELPENTIUM 0x05 +#define CPUID_FAMILYCODE_INTELCORE 0x06 +#define CPUID_FAMILYCODE_INTELPENTIUM4 0x0F + +#define CPUID_MODELCODE_INTELSKYLAKE 0x55 +#define CPUID_MODELCODE_INTELBROADWELL 0x4F +#define CPUID_MODELCODE_INTELHASWELL_1 0x3F +#define CPUID_MODELCODE_INTELHASWELL_2 0x3C +#define CPUID_MODELCODE_INTELIVYBRIDGE_1 0x3E +#define CPUID_MODELCODE_INTELIVYBRIDGE_2 0x3A +#define CPUID_MODELCODE_INTELSANDYBRIDGE 0x2A +#define CPUID_MODELCODE_INTELSANDYBRIDGE_EP 0x2D +#define CPUID_MODELCODE_INTELWESTMERE_EP 0x2C +#define CPUID_MODELCODE_INTELWESTMERE_EX 0x2F +#define CPUID_MODELCODE_INTELNEHALEM 0x1A +#define CPUID_MODELCODE_INTELCORE2_HARPERTOWN 0x17 +#define CPUID_MODELCODE_INTELCORE2_WOODCREST_CLOVERTOWN 0x0F + +#define CPUID_FAMILYCODE_AMDKSERIES 0x05 +#define CPUID_FAMILYCODE_AMDATHLON 0x06 +#define CPUID_FAMILYCODE_AMDOPTERON 0x0F + +#define CPUID_MODELCODE_AMDK5 0x04 + +#define CUPID_EXTENDEDFAMILYCODE_AMDOPTERON 0x06 /** * @internal @@ -89,14 +123,14 @@ omrsysinfo_get_x86_description(struct OMRPortLibrary *portLibrary, OMRProcessorD desc->processor = OMR_PROCESSOR_X86_UNKNOWN; /* vendor */ - omrsysinfo_get_x86_cpuid(CPUID_VENDOR_INFO, CPUInfo); - memcpy(vendor + 0, &CPUInfo[1], sizeof(uint32_t)); - memcpy(vendor + 4, &CPUInfo[3], sizeof(uint32_t)); - memcpy(vendor + 8, &CPUInfo[2], sizeof(uint32_t)); + cpuid(CPUInfo, CPUID_VENDOR_INFO); + memcpy(vendor + 0, &CPUInfo[CPUID_EBX], sizeof(uint32_t)); + memcpy(vendor + 4, &CPUInfo[CPUID_EDX], sizeof(uint32_t)); + memcpy(vendor + 8, &CPUInfo[CPUID_ECX], sizeof(uint32_t)); /* family and model */ - omrsysinfo_get_x86_cpuid(CPUID_FAMILY_INFO, CPUInfo); - processorSignature = CPUInfo[0]; + cpuid(CPUInfo, CPUID_FAMILY_INFO); + processorSignature = CPUInfo[CPUID_EAX]; familyCode = (processorSignature & CPUID_SIGNATURE_FAMILY) >> CPUID_SIGNATURE_FAMILY_SHIFT; if (0 == strncmp(vendor, CPUID_VENDOR_INTEL, CPUID_VENDOR_LENGTH)) { switch (familyCode) { @@ -107,20 +141,41 @@ omrsysinfo_get_x86_description(struct OMRPortLibrary *portLibrary, OMRProcessorD { uint32_t modelCode = (processorSignature & CPUID_SIGNATURE_MODEL) >> CPUID_SIGNATURE_MODEL_SHIFT; uint32_t extendedModelCode = (processorSignature & CPUID_SIGNATURE_EXTENDEDMODEL) >> CPUID_SIGNATURE_EXTENDEDMODEL_SHIFT; - uint32_t totalModelCode = modelCode + extendedModelCode; - - if (totalModelCode > CPUID_MODELCODE_INTELHASWELL) { + uint32_t totalModelCode = modelCode + (extendedModelCode << 4); + + switch (totalModelCode) { + case CPUID_MODELCODE_INTELSKYLAKE: + desc->processor = OMR_PROCESSOR_X86_INTELSKYLAKE; + break; + case CPUID_MODELCODE_INTELBROADWELL: + desc->processor = OMR_PROCESSOR_X86_INTELBROADWELL; + break; + case CPUID_MODELCODE_INTELHASWELL_1: + case CPUID_MODELCODE_INTELHASWELL_2: desc->processor = OMR_PROCESSOR_X86_INTELHASWELL; - } else if (totalModelCode >= CPUID_MODELCODE_SANDYBRIDGE) { + break; + case CPUID_MODELCODE_INTELIVYBRIDGE_1: + case CPUID_MODELCODE_INTELIVYBRIDGE_2: + desc->processor = OMR_PROCESSOR_X86_INTELIVYBRIDGE; + break; + case CPUID_MODELCODE_INTELSANDYBRIDGE: + case CPUID_MODELCODE_INTELSANDYBRIDGE_EP: desc->processor = OMR_PROCESSOR_X86_INTELSANDYBRIDGE; - } else if (totalModelCode >= CPUID_MODELCODE_INTELWESTMERE) { + break; + case CPUID_MODELCODE_INTELWESTMERE_EP: + case CPUID_MODELCODE_INTELWESTMERE_EX: desc->processor = OMR_PROCESSOR_X86_INTELWESTMERE; - } else if (totalModelCode >= CPUID_MODELCODE_INTELNEHALEM) { + break; + case CPUID_MODELCODE_INTELNEHALEM: desc->processor = OMR_PROCESSOR_X86_INTELNEHALEM; - } else if (totalModelCode == CPUID_MODELCODE_INTELCORE2) { + break; + case CPUID_MODELCODE_INTELCORE2_HARPERTOWN: + case CPUID_MODELCODE_INTELCORE2_WOODCREST_CLOVERTOWN: desc->processor = OMR_PROCESSOR_X86_INTELCORE2; - } else { + break; + default: desc->processor = OMR_PROCESSOR_X86_INTELP6; + break; } break; } @@ -136,79 +191,37 @@ omrsysinfo_get_x86_description(struct OMRPortLibrary *portLibrary, OMRProcessorD if (modelCode < CPUID_MODELCODE_AMDK5) { desc->processor = OMR_PROCESSOR_X86_AMDK5; } - desc->processor = OMR_PROCESSOR_X86_AMDK6; + else { + desc->processor = OMR_PROCESSOR_X86_AMDK6; + } break; } case CPUID_FAMILYCODE_AMDATHLON: desc->processor = OMR_PROCESSOR_X86_AMDATHLONDURON; break; case CPUID_FAMILYCODE_AMDOPTERON: - desc->processor = OMR_PROCESSOR_X86_AMDOPTERON; + { + uint32_t extendedFamilyCode = (processorSignature & CPUID_SIGNATURE_EXTENDEDFAMILY) >> CPUID_SIGNATURE_EXTENDEDFAMILY_SHIFT; + if (extendedFamilyCode < CUPID_EXTENDEDFAMILYCODE_AMDOPTERON) { + desc->processor = OMR_PROCESSOR_X86_AMDOPTERON; + } + else { + desc->processor = OMR_PROCESSOR_X86_AMDFAMILY15H; + } break; } + } } desc->physicalProcessor = desc->processor; /* features */ - desc->features[0] = CPUInfo[3]; - desc->features[1] = CPUInfo[2]; - desc->features[2] = 0; /* reserved for future expansion */ + desc->features[0] = CPUInfo[CPUID_EDX]; + desc->features[1] = CPUInfo[CPUID_ECX]; - return 0; -} + cpuidex(CPUInfo, 7, 0); + desc->features[2] = CPUInfo[CPUID_EBX]; -/** - * Assembly code to get the register data from CPUID instruction - * This function executes the CPUID instruction based on which we can detect - * if the environment is virtualized or not, and also get the Hypervisor Vendor - * Name based on the same instruction. The leaf value specifies what information - * to return. - * - * @param[in] leaf The leaf value to the CPUID instruction. - * @param[out] cpuInfo Reference to the an integer array which holds the data - * of EAX,EBX,ECX and EDX registers. - * cpuInfo[0] To hold the EAX register data, value in this register at - * the time of CPUID tells what information to return - * EAX=0x1,returns the processor Info and feature bits - * in EBX,ECX,EDX registers. - * EAX=0x40000000 returns the Hypervisor Vendor Names - * in the EBX,ECX,EDX registers. - * cpuInfo[1] For EAX = 0x40000000 hold first 4 characters of the - * Hypervisor Vendor String - * cpuInfo[2] For EAX = 0x1, the 31st bit of ECX tells if its - * running on Hypervisor or not,For EAX = 0x40000000 holds the second - * 4 characters of the the Hypervisor Vendor String - * cpuInfo[3] For EAX = 0x40000000 hold the last 4 characters of the - * Hypervisor Vendor String - * - */ - -static void -omrsysinfo_get_x86_cpuid(uint32_t leaf, uint32_t *cpuInfo) -{ - cpuInfo[0] = leaf; - -/* Implemented for x86 & x86_64 bit platforms */ -#if defined(WIN32) - /* Specific CPUID instruction available in Windows */ - __cpuid(cpuInfo, cpuInfo[0]); - -#elif defined(LINUX) || defined(OSX) -#if defined(J9X86) - __asm volatile - ("mov %%ebx, %%edi;" - "cpuid;" - "mov %%ebx, %%esi;" - "mov %%edi, %%ebx;" - :"+a" (cpuInfo[0]), "=S" (cpuInfo[1]), "=c" (cpuInfo[2]), "=d" (cpuInfo[3]) - : :"edi"); - -#elif defined(J9HAMMER) - __asm volatile( - "cpuid;" - :"+a" (cpuInfo[0]), "=b" (cpuInfo[1]), "=c" (cpuInfo[2]), "=d" (cpuInfo[3]) - ); -#endif -#endif + return 0; } +#endif /* (defined(J9X86) || defined(J9HAMMER)) */ diff --git a/port/common/omrsysinfo_helpers.h b/port/common/omrsysinfo_helpers.h index 1ed7bdc051..6201860614 100644 --- a/port/common/omrsysinfo_helpers.h +++ b/port/common/omrsysinfo_helpers.h @@ -30,7 +30,9 @@ #include "omrport.h" +#if (defined(J9X86) || defined(J9HAMMER)) extern intptr_t omrsysinfo_get_x86_description(struct OMRPortLibrary *portLibrary, OMRProcessorDesc *desc); +#endif #endif /* SYSINFOHELPERS_H_ */ diff --git a/port/unix/omrsysinfo.c b/port/unix/omrsysinfo.c index 0170b73186..8da086adb7 100644 --- a/port/unix/omrsysinfo.c +++ b/port/unix/omrsysinfo.c @@ -631,7 +631,7 @@ omrsysinfo_processor_has_feature(struct OMRPortLibrary *portLibrary, OMRProcesso #if defined(J9OS_I5) #if defined(J9OS_I5_V5R4) - if ((OMR_FEATURE_PPC_HAS_VSX == feature) || (OMRPORT_PPC_FEATURE_HAS_ALTIVEC == feature) || (OMRPORT_PPC_FEATURE_HTM == feature)) { + if ((OMR_FEATURE_PPC_HAS_VSX == feature) || (OMR_FEATURE_PPC_HAS_ALTIVEC == feature) || (OMR_FEATURE_PPC_HTM == feature)) { Trc_PRT_sysinfo_processor_has_feature_Exit((UDATA)rc); return rc; }