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AArch64: Add ARM64CondTrg1Src2Instruction to ARM64Debug.cpp #4185

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merged 1 commit into from
Aug 2, 2019

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knn-k
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@knn-k knn-k commented Aug 1, 2019

This commit adds support for a new instruction kind,
ARM64CondTrg1Src2Instruction, to ARM64Debug.cpp.

Signed-off-by: KONNO Kazuhiro konno@jp.ibm.com

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knn-k commented Aug 1, 2019

It generates output like the following:

[ 0x7f2b0cbc40] 5 cselw w0, w0, w1, ge

print(pOutFile, instr->getTargetRegister(), TR_WordReg); trfprintf(pOutFile, ", ");
print(pOutFile, instr->getSource1Register(), TR_WordReg); trfprintf(pOutFile, ", ");
print(pOutFile, instr->getSource2Register(), TR_WordReg);
trfprintf(pOutFile, ", %s", ARM64ConditionNames[cc_invert(instr->getConditionCode())]);
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Apologies if I'm just missing it, but why is the condition code inverted here?

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That is my mistake. I copied the line from print(TR::ARM64Trg1CondInstruction) which inverts the condition for cset alias.
Fixed the code.

@0xdaryl 0xdaryl self-assigned this Aug 2, 2019
This commit adds support for a new instruction kind,
ARM64CondTrg1Src2Instruction, to ARM64Debug.cpp.

Signed-off-by: KONNO Kazuhiro <konno@jp.ibm.com>
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0xdaryl commented Aug 2, 2019

@genie-omr build aarch64

@0xdaryl 0xdaryl merged commit 6e99760 into eclipse-omr:master Aug 2, 2019
@knn-k knn-k deleted the aarch64debug6 branch August 2, 2019 02:17
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3 participants