From 82933d6f8d94c479e3aeb0d79c533b62e9720889 Mon Sep 17 00:00:00 2001
From: Harry Yu <harryyu1994@gmail.com>
Date: Wed, 13 May 2020 01:17:13 -0400
Subject: [PATCH] Replace CPU APIs on Power

Issue: #4339

Signed-off-by: Harry Yu <harryyu1994@gmail.com>
---
 compiler/env/OMRCPU.cpp                     |  14 +-
 compiler/env/OMRCPU.hpp                     |   5 +-
 compiler/p/codegen/BinaryEvaluator.cpp      |  20 +--
 compiler/p/codegen/ControlFlowEvaluator.cpp |   4 +-
 compiler/p/codegen/FPTreeEvaluator.cpp      |  41 +++--
 compiler/p/codegen/GenerateInstructions.cpp |  20 +--
 compiler/p/codegen/OMRCodeGenerator.cpp     |  65 ++++----
 compiler/p/codegen/OMRMachine.cpp           |  16 +-
 compiler/p/codegen/OMRMemoryReference.cpp   |   2 +-
 compiler/p/codegen/OMRTreeEvaluator.cpp     |  57 +++----
 compiler/p/codegen/PPCBinaryEncoding.cpp    |   2 +-
 compiler/p/codegen/PPCInstruction.cpp       |  28 ++--
 compiler/p/codegen/PPCSystemLinkage.cpp     |   4 +-
 compiler/p/codegen/UnaryEvaluator.cpp       |   4 +-
 compiler/p/env/OMRCPU.cpp                   | 172 ++++++++++++++++++--
 compiler/p/env/OMRCPU.hpp                   |  26 ++-
 include_core/omrport.h                      |   2 +-
 17 files changed, 314 insertions(+), 168 deletions(-)

diff --git a/compiler/env/OMRCPU.cpp b/compiler/env/OMRCPU.cpp
index 86d0b5b76ba..9ea0a481423 100644
--- a/compiler/env/OMRCPU.cpp
+++ b/compiler/env/OMRCPU.cpp
@@ -87,7 +87,11 @@ OMR::CPU::CPU() :
 #endif
    }
 
-OMR::CPU::CPU(const OMRProcessorDesc& processorDescription) : 
+OMR::CPU::CPU(const OMRProcessorDesc& processorDescription) :
+   _processor(TR_NullProcessor),
+   _endianness(TR::endian_unknown),
+   _majorArch(TR::arch_unknown),
+   _minorArch(TR::m_arch_none),
    _processorDescription(processorDescription)
    {
 #ifdef OMR_ENV_LITTLE_ENDIAN
@@ -137,7 +141,6 @@ OMR::CPU::CPU(const OMRProcessorDesc& processorDescription) :
 #endif
    }
 
-
 TR::CPU *
 OMR::CPU::self()
    {
@@ -156,13 +159,6 @@ OMR::CPU::detect(OMRPortLibrary * const omrPortLib)
    return TR::CPU(processorDescription);
    }
 
-bool
-OMR::CPU::is(OMRProcessorArchitecture p)
-   {
-   TR_ASSERT_FATAL(TR::Compiler->omrPortLib != NULL, "Should not be calling this OMR level API without a valid port library pointer. Perhaps we did not initialize the port library properly?\n");
-   return _processorDescription.processor == p;
-   }
-
 bool
 OMR::CPU::supportsFeature(uint32_t feature)
    {
diff --git a/compiler/env/OMRCPU.hpp b/compiler/env/OMRCPU.hpp
index cd731b101c8..4fb4c07acd7 100644
--- a/compiler/env/OMRCPU.hpp
+++ b/compiler/env/OMRCPU.hpp
@@ -138,6 +138,7 @@ class OMR_EXTENSIBLE CPU
    void setMinorArch(TR::MinorArchitecture a) { _minorArch = a; }
    bool isI386() { return _minorArch == TR::m_arch_i386; }
    bool isAMD64() { return _minorArch == TR::m_arch_amd64; }
+   void applyUserOptions() {}
 
    /** 
     * @brief Determines whether the Transactional Memory (TM) facility is available on the current processor.
@@ -150,7 +151,7 @@ class OMR_EXTENSIBLE CPU
     * @param[in] p : the input processor type
     * @return true when current processor is the same as the input processor type
     */
-   bool is(OMRProcessorArchitecture p);
+   bool is(OMRProcessorArchitecture p) { return _processorDescription.processor == p; }
 
    /**
     * @brief Determines whether current processor is equal or newer than the input processor type
@@ -170,7 +171,7 @@ class OMR_EXTENSIBLE CPU
     * @brief Retrieves current processor's processor description
     * @return processor description which includes processor type and processor features
     */
-   const OMRProcessorDesc & getProcessorDescription() const { return _processorDescription; }
+   OMRProcessorDesc getProcessorDescription() { return _processorDescription; }
 
    /** 
     * @brief Determines whether current processor supports the input processor feature
diff --git a/compiler/p/codegen/BinaryEvaluator.cpp b/compiler/p/codegen/BinaryEvaluator.cpp
index 20da8ddac61..3323a6c5d43 100644
--- a/compiler/p/codegen/BinaryEvaluator.cpp
+++ b/compiler/p/codegen/BinaryEvaluator.cpp
@@ -204,7 +204,7 @@ TR::Register *OMR::Power::TreeEvaluator::iaddEvaluator(TR::Node *node, TR::CodeG
 
    TR::Node *firstChild = node->getFirstChild();
 
-  if (cg->comp()->target().cpu.id() >= TR_PPCp9 &&
+   if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9)  &&
       firstChild->getOpCodeValue() == TR::imul &&
       firstChild->getReferenceCount() == 1 &&
       firstChild->getRegister() == NULL)
@@ -508,7 +508,7 @@ TR::Register *OMR::Power::TreeEvaluator::laddEvaluator(TR::Node *node, TR::CodeG
          return trgReg;
          }
 
-      if (cg->comp()->target().cpu.id() >= TR_PPCp9 &&
+      if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9) &&
           !setsOrReadsCC &&
           (node->getOpCodeValue() == TR::ladd || node->getOpCodeValue() == TR::aladd) &&
           firstChild->getOpCodeValue() == TR::lmul &&
@@ -1621,7 +1621,7 @@ static TR::Register *signedIntegerDivisionOrRemainderAnalyser(TR::Node
             generateTrg1Src1Instruction(cg, TR::InstOpCode::neg, node, trgReg, trgReg);
          }
       }
-   else if (cg->comp()->target().cpu.id() >= TR_PPCp9 && isRemainder)
+   else if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9) && isRemainder)
       {
       if (divisorReg == NULL)
          divisorReg = cg->evaluate(node->getSecondChild());
@@ -2078,7 +2078,7 @@ strengthReducingLongDivideOrRemainder32BitMode(TR::Node *node,      TR::CodeGene
 
          if (isRemainder)
             {
-            if (cg->comp()->target().cpu.id() >= TR_PPCp9)
+            if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
                {
                generateTrg1Src2Instruction(cg, TR::InstOpCode::moduw, node, dr_l, dd_l, dr_l);
                }
@@ -2099,7 +2099,7 @@ strengthReducingLongDivideOrRemainder32BitMode(TR::Node *node,      TR::CodeGene
 
    TR_RuntimeHelper helper;
 
-   if (cg->comp()->target().cpu.id() >= TR_PPCp7 && !isDivisorImpossible32Bit)
+   if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) && !isDivisorImpossible32Bit)
       helper = isSignedOp ? TR_PPClongDivideEP : TR_PPCunsignedLongDivideEP;
    else
       helper = isSignedOp ? TR_PPClongDivide : TR_PPCunsignedLongDivide;
@@ -2154,7 +2154,7 @@ TR::Register *OMR::Power::TreeEvaluator::iremEvaluator(TR::Node *node, TR::CodeG
          {
          TR::Register *divisorReg = cg->evaluate(secondChild);
          trgReg = cg->allocateRegister();
-         if(cg->comp()->target().cpu.id() >= TR_PPCp9)
+         if(cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
             {
             generateTrg1Src2Instruction(cg, TR::InstOpCode::modsw, node, trgReg, dividendReg, divisorReg);
             }
@@ -2210,7 +2210,7 @@ TR::Register *OMR::Power::TreeEvaluator::iremEvaluator(TR::Node *node, TR::CodeG
             generateConditionalBranchInstruction(cg, TR::InstOpCode::beq, node, doneLabel, condReg);
             cg->stopUsingRegister(condReg);
             }
-         if(cg->comp()->target().cpu.id() >= TR_PPCp9)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
             {
             generateTrg1Src2Instruction(cg, TR::InstOpCode::modsw, node, trgReg, dividendReg, divisorReg);
             }
@@ -2250,7 +2250,7 @@ TR::Register *lrem64Evaluator(TR::Node *node, TR::CodeGenerator *cg)
          {
          TR::Register *divisorReg = cg->evaluate(secondChild);
          trgReg = cg->allocateRegister();
-         if(cg->comp()->target().cpu.id() >= TR_PPCp9)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
             {
             generateTrg1Src2Instruction(cg, TR::InstOpCode::modsd, node, trgReg, dividendReg, divisorReg);
             }
@@ -2306,7 +2306,7 @@ TR::Register *lrem64Evaluator(TR::Node *node, TR::CodeGenerator *cg)
             generateConditionalBranchInstruction(cg, TR::InstOpCode::beq, node, doneLabel, condReg);
             cg->stopUsingRegister(condReg);
             }
-         if (cg->comp()->target().cpu.id() >= TR_PPCp9)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
             {
             generateTrg1Src2Instruction(cg, TR::InstOpCode::modsd, node, trgReg, dividendReg, divisorReg);
             }
@@ -2350,7 +2350,7 @@ TR::Register *OMR::Power::TreeEvaluator::lremEvaluator(TR::Node *node, TR::CodeG
 static bool isPower9Extswsli(TR::CodeGenerator *cg, TR::Node *node)
    {
    static bool disableExtswsli = feGetEnv("TR_DisableExtswsli");
-   if (disableExtswsli || cg->comp()->target().cpu.id() < TR_PPCp9)
+   if (disableExtswsli || !cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
       return false;
 
    TR::Node *lhs = node->getFirstChild();
diff --git a/compiler/p/codegen/ControlFlowEvaluator.cpp b/compiler/p/codegen/ControlFlowEvaluator.cpp
index 7dbdb146eaf..f21b1ae55ab 100644
--- a/compiler/p/codegen/ControlFlowEvaluator.cpp
+++ b/compiler/p/codegen/ControlFlowEvaluator.cpp
@@ -2497,7 +2497,7 @@ TR::Register *OMR::Power::TreeEvaluator::lcmpEvaluator(TR::Node *node, TR::CodeG
       {
       if (secondChild->getOpCode().isLoadConst() && secondChild->getLongInt()==0)
          {
-         if (cg->comp()->target().cpu.id() >= TR_PPCp9)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
             {
             TR::Register *condReg = cg->allocateRegister(TR_CCR);
             generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::cmpi8, node, condReg, src1Reg, 0);
@@ -2518,7 +2518,7 @@ TR::Register *OMR::Power::TreeEvaluator::lcmpEvaluator(TR::Node *node, TR::CodeG
       else
          {
          TR::Register *src2Reg = cg->evaluate(secondChild);
-         if (cg->comp()->target().cpu.id() >= TR_PPCp9)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
             {
             TR::Register *condReg = cg->allocateRegister(TR_CCR);
             generateTrg1Src2Instruction(cg, TR::InstOpCode::cmp8, node, condReg, src1Reg, src2Reg);
diff --git a/compiler/p/codegen/FPTreeEvaluator.cpp b/compiler/p/codegen/FPTreeEvaluator.cpp
index ad191b96e56..5ea618a6f1b 100644
--- a/compiler/p/codegen/FPTreeEvaluator.cpp
+++ b/compiler/p/codegen/FPTreeEvaluator.cpp
@@ -116,7 +116,7 @@ TR::Register *OMR::Power::TreeEvaluator::fbits2iEvaluator(TR::Node *node, TR::Co
       }
    else
       {
-      floatReg = cg->comp()->target().cpu.id() >= TR_PPCp8 ? cg->gprClobberEvaluate(child) : cg->evaluate(child);
+      floatReg = cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) ? cg->gprClobberEvaluate(child) : cg->evaluate(child);
       generateMvFprGprInstructions(cg, node, fpr2gprSp, cg->comp()->target().is64Bit(),target, floatReg);
       childEval = floatReg == child->getRegister();
       cg->decReferenceCount(child);
@@ -204,7 +204,7 @@ TR::Register *OMR::Power::TreeEvaluator::lbits2dEvaluator(TR::Node *node, TR::Co
       else
          {
          TR::Register *longReg = cg->evaluate(child);
-         if (cg->comp()->target().cpu.id() >= TR_PPCp8)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
             {
             TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
             generateMvFprGprInstructions(cg, node, gpr2fprHost32, false, target, longReg->getHighOrder(), longReg->getLowOrder(), tmp1);
@@ -273,7 +273,7 @@ TR::Register *OMR::Power::TreeEvaluator::dbits2lEvaluator(TR::Node *node, TR::Co
          {
          highReg = cg->allocateRegister();
          lowReg = cg->allocateRegister();
-         if (cg->comp()->target().cpu.id() >= TR_PPCp8)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
             {
             TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
             generateMvFprGprInstructions(cg, node, fpr2gprHost32, false, highReg, lowReg, doubleReg, tmp1);
@@ -650,7 +650,7 @@ TR::Register *OMR::Power::TreeEvaluator::vsplatsEvaluator(TR::Node *node, TR::Co
       TR::Register *tempReg = cg->evaluate(child);
       TR::Register *resReg = cg->allocateRegister(TR_VRF);
 
-      if (!disableDirectMove && cg->comp()->target().cpu.id() >= TR_PPCp8 && cg->comp()->target().cpu.getPPCSupportsVSX())
+      if (!disableDirectMove && cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) && cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX))
          {
          generateMvFprGprInstructions(cg, node, gprLow2fpr, false, resReg, tempReg);
          generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::xxspltw, node, resReg, resReg, 0x1);
@@ -682,7 +682,7 @@ TR::Register *OMR::Power::TreeEvaluator::vsplatsEvaluator(TR::Node *node, TR::Co
       TR::Register *srcReg = cg->evaluate(child);
       TR::Register *trgReg = cg->allocateRegister(TR_VRF);
 
-      if (!disableDirectMove && cg->comp()->target().cpu.id() >= TR_PPCp8 && cg->comp()->target().cpu.getPPCSupportsVSX())
+      if (!disableDirectMove && cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) && cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX))
          {
          if (cg->comp()->target().is64Bit())
             {
@@ -1390,7 +1390,7 @@ TR::Register *OMR::Power::TreeEvaluator::int2dbl(TR::Node * node, TR::Register *
          }
       else
          {
-         if (cg->comp()->target().cpu.id() >= TR_PPCp6 && node->getOpCodeValue() != TR::iu2f && node->getOpCodeValue() != TR::iu2d)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6) && node->getOpCodeValue() != TR::iu2f && node->getOpCodeValue() != TR::iu2d)
             generateMvFprGprInstructions(cg, node, gprLow2fpr, false, trgReg, srcReg);
          else
             {
@@ -1401,7 +1401,7 @@ TR::Register *OMR::Power::TreeEvaluator::int2dbl(TR::Node * node, TR::Register *
             else
                generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::srawi, node, tempReg, srcReg, 31);
 
-            if (cg->comp()->target().cpu.id() >= TR_PPCp8)
+            if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
                {
                TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
                generateMvFprGprInstructions(cg, node, gpr2fprHost32, false, trgReg, tempReg, srcReg, tmp1);
@@ -1412,7 +1412,7 @@ TR::Register *OMR::Power::TreeEvaluator::int2dbl(TR::Node * node, TR::Register *
             cg->stopUsingRegister(tempReg);
             }
          }
-      if ((cg->comp()->target().cpu.id() >= TR_PPCp7) &&
+      if ((cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7)) &&
           (node->getOpCodeValue() == TR::i2f || node->getOpCodeValue() == TR::iu2f))
          {
          // Generate the code to produce the float result here, setting the register flag is done afterwards
@@ -1460,9 +1460,9 @@ TR::Register *OMR::Power::TreeEvaluator::i2fEvaluator(TR::Node *node, TR::CodeGe
    TR::Register *tempReg;
    TR::Register *trgReg;
 
-   if (((cg->comp()->target().cpu.id() >= TR_PPCp7 &&
+   if (((cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) &&
        (node->getOpCodeValue() == TR::iu2f && (child->getOpCodeValue() == TR::iuload || child->getOpCodeValue() == TR::iuloadi))) ||
-       (cg->comp()->target().cpu.id() >= TR_PPCp6 &&
+       (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6) &&
        (node->getOpCodeValue() == TR::i2f && (child->getOpCodeValue() == TR::iload || child->getOpCodeValue() == TR::iloadi)))) &&
        child->getReferenceCount() == 1 && child->getRegister() == NULL &&
        !(child->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP()))
@@ -1474,7 +1474,7 @@ TR::Register *OMR::Power::TreeEvaluator::i2fEvaluator(TR::Node *node, TR::CodeGe
       if (node->getOpCodeValue() == TR::i2f)
          {
          generateTrg1MemInstruction(cg, TR::InstOpCode::lfiwax, node, tempReg, tempMR);
-         if (cg->comp()->target().cpu.id() >= TR_PPCp7)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7))
             {
             generateTrg1Src1Instruction(cg, TR::InstOpCode::fcfids, node, trgReg, tempReg);
             }
@@ -1508,9 +1508,9 @@ TR::Register *OMR::Power::TreeEvaluator::i2dEvaluator(TR::Node *node, TR::CodeGe
    TR::Node     *child      = node->getFirstChild();
    TR::Register *trgReg;
 
-   if (((cg->comp()->target().cpu.id() >= TR_PPCp7 &&
+   if (((cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) &&
        (node->getOpCodeValue() == TR::iu2d && (child->getOpCodeValue() == TR::iuload || child->getOpCodeValue() == TR::iuloadi))) ||
-       (cg->comp()->target().cpu.id() >= TR_PPCp6 &&
+       (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6) &&
        node->getOpCodeValue() == TR::i2d && (child->getOpCodeValue() == TR::iload || child->getOpCodeValue() == TR::iloadi))) &&
        child->getReferenceCount()==1 &&
        child->getRegister() == NULL &&
@@ -1555,7 +1555,7 @@ TR::Register *OMR::Power::TreeEvaluator::long2dbl(TR::Node *node, TR::CodeGenera
          generateMvFprGprInstructions(cg, node, gpr2fprHost64, false, trgReg, srcReg);
       else
          {
-         if (cg->comp()->target().cpu.id() >= TR_PPCp8)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
             {
             TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
             generateMvFprGprInstructions(cg, node, gpr2fprHost32, false, trgReg, srcReg->getHighOrder(), srcReg->getLowOrder(), tmp1);
@@ -1609,14 +1609,14 @@ TR::Register *OMR::Power::TreeEvaluator::long2float(TR::Node *node, TR::CodeGene
    TR::Register *srcReg  = cg->evaluate(child);
    TR::Register *trgReg     = cg->allocateSinglePrecisionRegister(TR_FPR);
 
-   if (cg->comp()->target().cpu.id() >= TR_PPCp7 &&
+   if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) &&
       (cg->is64BitProcessor() || (cg->comp()->compileRelocatableCode() && cg->comp()->target().is64Bit())))
       {
       if (cg->comp()->target().is64Bit())
          generateMvFprGprInstructions(cg, node, gpr2fprHost64, false, trgReg, srcReg);
       else
          {
-         if (cg->comp()->target().cpu.id() >= TR_PPCp8)
+         if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
             {
             TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
             generateMvFprGprInstructions(cg, node, gpr2fprHost32, false, trgReg, srcReg->getHighOrder(), srcReg->getLowOrder(), tmp1);
@@ -1697,7 +1697,7 @@ TR::Register *OMR::Power::TreeEvaluator::l2fEvaluator(TR::Node *node, TR::CodeGe
    {
    TR::Register *trgReg;
    TR::Node     *child      = node->getFirstChild();
-   if (cg->comp()->target().cpu.id() >= TR_PPCp7 &&
+   if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) &&
        node->getOpCodeValue() == TR::l2f &&
        (child->getOpCodeValue() == TR::lload || child->getOpCodeValue() == TR::lloadi) &&
        child->getReferenceCount()==1 &&
@@ -1725,8 +1725,7 @@ TR::Register *OMR::Power::TreeEvaluator::l2dEvaluator(TR::Node *node, TR::CodeGe
    {
    TR::Register *trgReg;
    TR::Node     *child      = node->getFirstChild();
-   if (
-       cg->comp()->target().cpu.id() >= TR_PPCp7 &&
+   if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) &&
        node->getOpCodeValue() == TR::l2d &&
        (child->getOpCodeValue() == TR::lload || child->getOpCodeValue() == TR::lloadi) &&
        child->getReferenceCount()==1 &&
@@ -2033,7 +2032,7 @@ TR::Register *OMR::Power::TreeEvaluator::dcmpneEvaluator(TR::Node *node, TR::Cod
 TR::Register *OMR::Power::TreeEvaluator::dcmpltEvaluator(TR::Node *node, TR::CodeGenerator *cg)
    {
    int64_t imm = 0;
-   if (cg->comp()->target().cpu.id() >= TR_PPCp9)
+   if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
       {
       imm = (TR::RealRegister::CRCC_GT <<  TR::RealRegister::pos_RT | TR::RealRegister::CRCC_LT <<  TR::RealRegister::pos_RA | TR::RealRegister::CRCC_LT << TR::RealRegister::pos_RB);
       }
@@ -2282,7 +2281,7 @@ static TR::Register *compareFloatAndSetOrderedBoolean(TR::InstOpCode::Mnemonic b
       cfop->addTargetRegister(trgReg);
       cfop->addSourceRegister(src1Reg);
       cfop->addSourceRegister(src2Reg);
-      if (cg->comp()->target().cpu.id() >= TR_PPCp9 && branchOp2 == TR::InstOpCode::bad && imm != 0)
+      if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9) && branchOp2 == TR::InstOpCode::bad && imm != 0)
          {
          cfop->addSourceImmediate(imm);
          }
diff --git a/compiler/p/codegen/GenerateInstructions.cpp b/compiler/p/codegen/GenerateInstructions.cpp
index 1c6ffe94143..5871d2d20cd 100644
--- a/compiler/p/codegen/GenerateInstructions.cpp
+++ b/compiler/p/codegen/GenerateInstructions.cpp
@@ -62,7 +62,7 @@ TR::Instruction *generateMvFprGprInstructions(TR::CodeGenerator *cg, TR::Node *n
    {
    TR::MemoryReference *tempMRStore1, *tempMRStore2, *tempMRLoad1, *tempMRLoad2;
    static bool disableDirectMove = feGetEnv("TR_disableDirectMove") ? true : false;
-   bool checkp8DirectMove = cg->comp()->target().cpu.id() >= TR_PPCp8 && !disableDirectMove && cg->comp()->target().cpu.getPPCSupportsVSX();
+   bool checkp8DirectMove = cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) && !disableDirectMove && cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX);
    bool isLittleEndian = cg->comp()->target().cpu.isLittleEndian();
 
    // it's fine if reg3 and reg2 are assigned in modes they are not used
@@ -166,7 +166,7 @@ TR::Instruction *generateMvFprGprInstructions(TR::CodeGenerator *cg, TR::Node *n
       else if (mode == gprLow2fpr)
          cursor = generateMemSrc1Instruction(cg, TR::InstOpCode::stw, node, tempMRStore1, reg1, cursor);
 
-      if ((nonops == false) && (cg->comp()->target().cpu.id() >= TR_PPCgp))
+      if ((nonops == false) && (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_GP)))
          {
     	 // Insert 3 nops to break up the load/stores into separate groupings,
     	 // thus preventing a costly stall
@@ -208,7 +208,7 @@ TR::Instruction *generateInstruction(TR::CodeGenerator *cg, TR::InstOpCode::Mnem
 
 TR::Instruction *generateAlignmentNopInstruction(TR::CodeGenerator *cg, TR::Node * n, uint32_t alignment, TR::Instruction *preced)
    {
-   auto op = cg->comp()->target().cpu.id() >= TR_PPCp6 ? TR::InstOpCode::genop : TR::InstOpCode::nop;
+   auto op = cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6) ? TR::InstOpCode::genop : TR::InstOpCode::nop;
 
    if (preced)
       return new (cg->trHeapMemory()) TR::PPCAlignmentNopInstruction(op, n, alignment, preced, cg);
@@ -315,7 +315,7 @@ TR::Instruction *generateConditionalBranchInstruction(TR::CodeGenerator *cg, TR:
    TR::LabelSymbol *sym, TR::Register *cr, TR::Instruction *preced)
    {
    // if processor does not support branch hints
-   if (cg->comp()->target().cpu.id() < TR_PPCgp)   
+   if (!cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_GP))
       return generateConditionalBranchInstruction(cg, op, n, sym, cr, preced);
 
    if (cr->isFlippedCCR())
@@ -330,7 +330,7 @@ TR::Instruction *generateDepConditionalBranchInstruction(TR::CodeGenerator *cg,
    TR::LabelSymbol *sym, TR::Register *cr, TR::RegisterDependencyConditions *cond, TR::Instruction *preced)
    {
    // if processor does not support branch hints
-   if (cg->comp()->target().cpu.id() < TR_PPCgp)   
+   if (!cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_GP))  
       return generateDepConditionalBranchInstruction(cg, op, n, sym, cr, cond, preced);
    
    if (cr->isFlippedCCR())
@@ -393,7 +393,7 @@ TR::Instruction *generateDepConditionalBranchInstruction(TR::CodeGenerator *cg,
 TR::Instruction *generateTrg1Src1ImmInstruction(TR::CodeGenerator *cg, TR::InstOpCode::Mnemonic op, TR::Node * n,
    TR::Register *treg, TR::Register *s1reg, intptr_t imm, TR::Instruction *preced)
    {
-   if (cg->comp()->target().cpu.id() == TR_PPCp6 && TR::InstOpCode(op).isCompare())
+   if (cg->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P6) && TR::InstOpCode(op).isCompare())
       treg->resetFlippedCCR();
    if (preced)
       return new (cg->trHeapMemory()) TR::PPCTrg1Src1ImmInstruction(op, n, treg, s1reg, imm, preced, cg);
@@ -403,7 +403,7 @@ TR::Instruction *generateTrg1Src1ImmInstruction(TR::CodeGenerator *cg, TR::InstO
 TR::Instruction *generateTrg1Src1ImmInstruction(TR::CodeGenerator *cg, TR::InstOpCode::Mnemonic op, TR::Node * n,
    TR::Register *treg, TR::Register *s1reg, TR::Register *cr0reg, int32_t imm, TR::Instruction *preced)
    {
-   if (cg->comp()->target().cpu.id() == TR_PPCp6)
+   if (cg->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P6))
       cr0reg->resetFlippedCCR();
    if (preced)
       return new (cg->trHeapMemory()) TR::PPCTrg1Src1ImmInstruction(op, n,treg, s1reg, cr0reg, imm, preced, cg);
@@ -458,7 +458,7 @@ TR::Instruction *generateTrg1Src2Instruction(TR::CodeGenerator *cg, TR::InstOpCo
    {
    TR::Compilation * comp = cg->comp();
    static bool disableFlipCompare = feGetEnv("TR_DisableFlipCompare") != NULL;
-   if (!disableFlipCompare && cg->comp()->target().cpu.id() == TR_PPCp6 &&
+   if (!disableFlipCompare && cg->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P6) &&
        TR::InstOpCode(op).isCompare() &&
        n->getOpCode().isBranch() && n->getOpCode().isBooleanCompare())
       {
@@ -484,7 +484,7 @@ TR::Instruction *generateTrg1Src2Instruction(TR::CodeGenerator *cg, TR::InstOpCo
 TR::Instruction *generateTrg1Src2Instruction(TR::CodeGenerator *cg, TR::InstOpCode::Mnemonic op, TR::Node * n,
    TR::Register *treg, TR::Register *s1reg, TR::Register *s2reg, TR::Register *cr0Reg, TR::Instruction *preced)
    {
-   if (cg->comp()->target().cpu.id() == TR_PPCp6)
+   if (cg->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P6))
       cr0Reg->resetFlippedCCR();
    return new (cg->trHeapMemory()) TR::PPCTrg1Src2Instruction(op, n, treg, s1reg, s2reg, cr0Reg, preced, cg);
    }
@@ -516,7 +516,7 @@ TR::Instruction *generateTrg1Src1Imm2Instruction(TR::CodeGenerator *cg, TR::Inst
 TR::Instruction *generateTrg1Src1Imm2Instruction(TR::CodeGenerator *cg, TR::InstOpCode::Mnemonic op, TR::Node * n,
    TR::Register *trgReg, TR::Register *srcReg, TR::Register *cr0reg, int32_t imm1, int64_t imm2, TR::Instruction *preced)
    {
-   if (cg->comp()->target().cpu.id() == TR_PPCp6)
+   if (cg->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P6))
       cr0reg->resetFlippedCCR();
    if (preced)
       return new (cg->trHeapMemory()) TR::PPCTrg1Src1Imm2Instruction(op, n, trgReg, srcReg, cr0reg, imm1, imm2, preced, cg);
diff --git a/compiler/p/codegen/OMRCodeGenerator.cpp b/compiler/p/codegen/OMRCodeGenerator.cpp
index f01d1cd220f..1dd5bef4d22 100644
--- a/compiler/p/codegen/OMRCodeGenerator.cpp
+++ b/compiler/p/codegen/OMRCodeGenerator.cpp
@@ -218,7 +218,7 @@ OMR::Power::CodeGenerator::CodeGenerator() :
        }
     self()->setSupportsArrayCmp();
 
-    if (self()->comp()->target().cpu.getPPCSupportsVSX())
+    if (self()->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX))
        {
        static bool disablePPCTRTO = (feGetEnv("TR_disablePPCTRTO") != NULL);
        static bool disablePPCTRTO255 = (feGetEnv("TR_disablePPCTRTO255") != NULL);
@@ -281,11 +281,11 @@ OMR::Power::CodeGenerator::CodeGenerator() :
     * TODO: TM is currently not compatible with read barriers. If read barriers are required, TM is disabled until the issue is fixed.
     *       TM is now disabled by default, due to various reasons (OS, hardware, etc), unless it is explicitly enabled.
     */
-   if (self()->comp()->target().cpu.getPPCSupportsTM() && self()->comp()->getOption(TR_EnableTM) &&
+   if (self()->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HTM) && self()->comp()->getOption(TR_EnableTM) &&
        !self()->comp()->getOption(TR_DisableTM) && TR::Compiler->om.readBarrierType() == gc_modron_readbar_none)
       self()->setSupportsTM();
 
-   if (self()->comp()->target().cpu.getPPCSupportsVMX() && self()->comp()->target().cpu.getPPCSupportsVSX())
+   if (self()->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_ALTIVEC) && self()->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX))
       self()->setSupportsAutoSIMD();
 
    if (!self()->comp()->getOption(TR_DisableRegisterPressureSimulation))
@@ -504,24 +504,29 @@ OMR::Power::CodeGenerator::mulDecompositionCostIsJustified(
 
    // Notice: the total simple operations is (2*numOfOperations-1). The following checking is a heuristic
    //         on processors we still care about.
-   switch (self()->comp()->target().cpu.id())
+   switch (self()->comp()->target().cpu.getProcessorDescription().processor)
       {
-      case TR_PPCpwr630: // 2S+1M FXU out-of-order
+      case OMR_PROCESSOR_PPC_PWR630: // 2S+1M FXU out-of-order
+         TR_ASSERT_FATAL(self()->comp()->target().cpu.id() == TR_PPCpwr630, "TR_PPCpwr630");
          return (numOfOperations<=4);
 
-      case TR_PPCnstar:
-      case TR_PPCpulsar: // 1S+1M FXU in-order
+      case OMR_PROCESSOR_PPC_NSTAR:
+      case OMR_PROCESSOR_PPC_PULSAR: // 1S+1M FXU in-order
+         TR_ASSERT_FATAL(self()->comp()->target().cpu.id() == TR_PPCnstar || self()->comp()->target().cpu.id() == TR_PPCpulsar, "TR_PPCnstar, TR_PPCpulsar");
          return (numOfOperations<=8);
 
-      case TR_PPCgpul:
-      case TR_PPCgp:
-      case TR_PPCgr:    // 2 FXU out-of-order back-to-back 2 cycles. Mul is only 4 to 6 cycles
+      case OMR_PROCESSOR_PPC_GPUL:
+      case OMR_PROCESSOR_PPC_GP:
+      case OMR_PROCESSOR_PPC_GR:    // 2 FXU out-of-order back-to-back 2 cycles. Mul is only 4 to 6 cycles
+         TR_ASSERT_FATAL(self()->comp()->target().cpu.id() == TR_PPCgpul || self()->comp()->target().cpu.id() == TR_PPCgp || self()->comp()->target().cpu.id() == TR_PPCgr, "TR_PPCgpul, TR_PPCgp, TR_PPCgr");
          return (numOfOperations<=2);
 
-      case TR_PPCp6:    // Mul is on FPU for 17cycles blocking other operations
+      case OMR_PROCESSOR_PPC_P6:    // Mul is on FPU for 17cycles blocking other operations
+         TR_ASSERT_FATAL(self()->comp()->target().cpu.id() == TR_PPCp6, "TR_PPCp6");
          return (numOfOperations<=16);
 
-      case TR_PPCp7:    // Mul blocks other operations for up to 4 cycles
+      case OMR_PROCESSOR_PPC_P7:    // Mul blocks other operations for up to 4 cycles
+         TR_ASSERT_FATAL(self()->comp()->target().cpu.id() == TR_PPCp7, "TR_PPCp7");
          return (numOfOperations<=3);
 
       default:          // assume a generic design similar to 604
@@ -614,7 +619,7 @@ TR::Instruction *OMR::Power::CodeGenerator::generateNop(TR::Node *n, TR::Instruc
 
 TR::Instruction *OMR::Power::CodeGenerator::generateGroupEndingNop(TR::Node *node , TR::Instruction *preced)
    {
-   if (self()->comp()->target().cpu.id() >= TR_PPCp6) // handles P7, P8
+   if (self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6)) // handles P7, P8
       {
       preced = self()->generateNop(node , preced , TR_NOPEndGroup);
       }
@@ -1100,8 +1105,8 @@ static void recordFormPeephole(TR::CodeGenerator *cg, TR::Instruction *cmpiInstr
          if (current->getOpCode().hasRecordForm())
             {
             // avoid certain record forms on POWER4/POWER5
-            if (comp->target().cpu.id() == TR_PPCgp ||
-                comp->target().cpu.id() == TR_PPCgr)
+            if (comp->target().cpu.is(OMR_PROCESSOR_PPC_GP) ||
+                comp->target().cpu.is(OMR_PROCESSOR_PPC_GR))
                {
                TR::InstOpCode::Mnemonic opCode = current->getOpCodeValue();
                // addc_r, subfc_r, divw_r and divd_r are microcoded
@@ -1560,7 +1565,7 @@ void OMR::Power::CodeGenerator::doPeephole()
       {
       self()->setCurrentBlockIndex(instructionCursor->getBlockIndex());
 
-      if ((self()->comp()->target().cpu.id() == TR_PPCp6) && instructionCursor->isTrap())
+      if ((self()->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P6)) && instructionCursor->isTrap())
          {
 #if defined(AIXPPC)
          trapPeephole(self(),instructionCursor);
@@ -2812,7 +2817,7 @@ bool OMR::Power::CodeGenerator::isGlobalRegisterAvailable(TR_GlobalRegisterNumbe
 
 bool OMR::Power::CodeGenerator::supportsSinglePrecisionSQRT()
    {
-   return self()->comp()->target().cpu.getSupportsHardwareSQRT();
+   return self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_HW_SQRT_FIRST);
    }
 
 
@@ -2860,12 +2865,12 @@ bool OMR::Power::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode
    {
 
    // alignment issues
-   if (self()->comp()->target().cpu.id() < TR_PPCp8 &&
+   if (!self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) &&
        dt != TR::Double &&
        dt != TR::Int64)
       return false;
 
-   if (self()->comp()->target().cpu.id() >= TR_PPCp8 &&
+   if (self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) &&
        (opcode.getOpCodeValue() == TR::vadd || opcode.getOpCodeValue() == TR::vsub) &&
        dt == TR::Int64)
       return true;
@@ -2917,14 +2922,14 @@ bool OMR::Power::CodeGenerator::getSupportsOpCodeForAutoSIMD(TR::ILOpCode opcode
 bool
 OMR::Power::CodeGenerator::getSupportsEncodeUtf16LittleWithSurrogateTest()
    {
-   return self()->comp()->target().cpu.getPPCSupportsVSX() &&
+   return self()->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX) &&
           !self()->comp()->getOption(TR_DisableSIMDUTF16LEEncoder);
    }
 
 bool
 OMR::Power::CodeGenerator::getSupportsEncodeUtf16BigWithSurrogateTest()
    {
-   return self()->comp()->target().cpu.getPPCSupportsVSX() &&
+   return self()->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX) &&
           !self()->comp()->getOption(TR_DisableSIMDUTF16BEEncoder);
    }
 
@@ -3300,7 +3305,7 @@ void TR_PPCScratchRegisterManager::addScratchRegistersToDependencyList(
 
 TR::SymbolReference & OMR::Power::CodeGenerator::getArrayCopySymbolReference()
    {
-   if (self()->comp()->target().cpu.id() >= TR_PPCp6)
+   if (self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6))
       return *_symRefTab->findOrCreateRuntimeHelper(TR_PPCarrayCopy_dp, false, false, false);
    else
       return *_symRefTab->findOrCreateRuntimeHelper(TR_PPCarrayCopy, false, false, false);
@@ -3308,7 +3313,7 @@ TR::SymbolReference & OMR::Power::CodeGenerator::getArrayCopySymbolReference()
 
 TR::SymbolReference & OMR::Power::CodeGenerator::getWordArrayCopySymbolReference()
    {
-   if (self()->comp()->target().cpu.id() >= TR_PPCp6)
+   if (self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6))
       return *_symRefTab->findOrCreateRuntimeHelper(TR_PPCwordArrayCopy_dp, false, false, false);
    else
       return *_symRefTab->findOrCreateRuntimeHelper(TR_PPCwordArrayCopy, false, false, false);
@@ -3316,7 +3321,7 @@ TR::SymbolReference & OMR::Power::CodeGenerator::getWordArrayCopySymbolReference
 
 TR::SymbolReference & OMR::Power::CodeGenerator::getHalfWordArrayCopySymbolReference()
    {
-   if (self()->comp()->target().cpu.id() >= TR_PPCp6)
+   if (self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6))
       return *_symRefTab->findOrCreateRuntimeHelper(TR_PPChalfWordArrayCopy_dp, false, false, false);
    else
       return *_symRefTab->findOrCreateRuntimeHelper(TR_PPChalfWordArrayCopy, false, false, false);
@@ -3324,7 +3329,7 @@ TR::SymbolReference & OMR::Power::CodeGenerator::getHalfWordArrayCopySymbolRefer
 
 TR::SymbolReference & OMR::Power::CodeGenerator::getForwardArrayCopySymbolReference()
    {
-   if (self()->comp()->target().cpu.id() >= TR_PPCp6)
+   if (self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6))
       return *_symRefTab->findOrCreateRuntimeHelper(TR_PPCforwardArrayCopy_dp, false, false, false);
    else
       return *_symRefTab->findOrCreateRuntimeHelper(TR_PPCforwardArrayCopy, false, false, false);
@@ -3332,7 +3337,7 @@ TR::SymbolReference & OMR::Power::CodeGenerator::getForwardArrayCopySymbolRefere
 
 TR::SymbolReference &OMR::Power::CodeGenerator::getForwardWordArrayCopySymbolReference()
    {
-   if (self()->comp()->target().cpu.id() >= TR_PPCp6)
+   if (self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6))
       return *_symRefTab->findOrCreateRuntimeHelper(TR_PPCforwardWordArrayCopy_dp, false, false, false);
    else
       return *_symRefTab->findOrCreateRuntimeHelper(TR_PPCforwardWordArrayCopy, false, false, false);
@@ -3340,19 +3345,17 @@ TR::SymbolReference &OMR::Power::CodeGenerator::getForwardWordArrayCopySymbolRef
 
 TR::SymbolReference &OMR::Power::CodeGenerator::getForwardHalfWordArrayCopySymbolReference()
    {
-   if (self()->comp()->target().cpu.id() >= TR_PPCp6)
+   if (self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6))
       return *_symRefTab->findOrCreateRuntimeHelper(TR_PPCforwardHalfWordArrayCopy_dp, false, false, false);
    else
       return *_symRefTab->findOrCreateRuntimeHelper(TR_PPCforwardHalfWordArrayCopy, false, false, false);
    }
 
-
 bool OMR::Power::CodeGenerator::supportsTransientPrefetch()
    {
-   return TR::comp()->target().cpu.id() >= TR_PPCp7;
+   return TR::comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7);
    }
 
-
 bool OMR::Power::CodeGenerator::is64BitProcessor()
    {
    /*
@@ -3365,7 +3368,7 @@ bool OMR::Power::CodeGenerator::is64BitProcessor()
       }
    else
       {
-      return self()->comp()->target().cpu.getPPCis64bit();
+      return self()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_64BIT_FIRST);
       }
    }
 
diff --git a/compiler/p/codegen/OMRMachine.cpp b/compiler/p/codegen/OMRMachine.cpp
index 77314a9513c..7d2f5a11b8d 100644
--- a/compiler/p/codegen/OMRMachine.cpp
+++ b/compiler/p/codegen/OMRMachine.cpp
@@ -201,7 +201,7 @@ void OMR::Power::Machine::initREGAssociations()
    // Power8/SAR:  confine to the smallest set of registers we can get away, because map cache
    // Others:      neutral --- take Power6 way for now
 
-   int rollingAllocator = !(self()->cg()->comp()->target().cpu.id() == TR_PPCp8);
+   int rollingAllocator = !(self()->cg()->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P8));
 
 
    _inUseFPREnd = rollingAllocator?lastFPRv:0;
@@ -279,7 +279,7 @@ TR::RealRegister *OMR::Power::Machine::findBestFreeRegister(TR::Instruction *cur
    // For FPR/VSR/VRF
    if (rk == TR_FPR || rk == TR_VSX_SCALAR || rk == TR_VSX_VECTOR || rk == TR_VRF)
       {
-      int rollingAllocator = !(self()->cg()->comp()->target().cpu.id() == TR_PPCp8);
+      int rollingAllocator = !(self()->cg()->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P8));
 
       // Find the best in the used FPR set so far
       int i, idx;
@@ -395,7 +395,7 @@ TR::RealRegister *OMR::Power::Machine::findBestFreeRegister(TR::Instruction *cur
          iNew = interference & currentReg;
 
          //Inject interference for last four assignments to prevent write-after-write dependancy in same p6 dispatch group.
-         if(rk == TR_GPR && (self()->cg()->comp()->target().cpu.id() == TR_PPCp6))
+         if(rk == TR_GPR && (self()->cg()->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P6)))
             {
             if (_lastGPRAssigned != -1)
                iNew |= currentReg & _lastGPRAssigned;
@@ -421,7 +421,7 @@ TR::RealRegister *OMR::Power::Machine::findBestFreeRegister(TR::Instruction *cur
             }
          }
       //Track the last four registers used for use in above interference injection.
-      if ((rk == TR_GPR) && (freeRegister != NULL) && (self()->cg()->comp()->target().cpu.id() == TR_PPCp6))
+      if ((rk == TR_GPR) && (freeRegister != NULL) && (self()->cg()->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P6)))
          {
          _4thLastGPRAssigned = _3rdLastGPRAssigned;
          _3rdLastGPRAssigned = _2ndLastGPRAssigned;
@@ -837,7 +837,7 @@ TR::RealRegister *OMR::Power::Machine::freeBestRegister(TR::Instruction     *cur
          // Until stack frame is 16-byte aligned, we cannot use VMX load/store here
          // So, we use VSX load/store instead as a work-around
 
-         TR_ASSERT(self()->cg()->comp()->target().cpu.getPPCSupportsVSX(), "VSX support not enabled");
+         TR_ASSERT(self()->cg()->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX), "VSX support not enabled");
 
          tempIndexRegister = self()->findBestFreeRegister(currentInstruction, TR_GPR);
          if (tempIndexRegister  == NULL)
@@ -1081,7 +1081,7 @@ TR::RealRegister *OMR::Power::Machine::reverseSpillState(TR::Instruction      *c
          // Until stack frame is 16-byte aligned, we cannot use VMX load/store here
          // So, we use VSX load/store instead as a work-around
 
-         TR_ASSERT(self()->cg()->comp()->target().cpu.getPPCSupportsVSX(), "VSX support not enabled");
+         TR_ASSERT(self()->cg()->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX), "VSX support not enabled");
 
          tempIndexRegister  = self()->findBestFreeRegister(currentInstruction, TR_GPR);
          if (tempIndexRegister  == NULL)
@@ -1192,7 +1192,7 @@ void OMR::Power::Machine::coerceRegisterAssignment(TR::Instruction
 				   (currentAssignedRegister!=NULL && currentAssignedRegister->getKind()==ctv_rk);
 
       // RegisterExchange: GPR/VRF have xor op always, and only CCR has no xor after P6
-      bool needTemp = !((ctv_rk == TR_GPR) || (ctv_rk == TR_VRF) || (self()->cg()->comp()->target().cpu.getPPCSupportsVSX() && ctv_rk!=TR_CCR));
+      bool needTemp = !((ctv_rk == TR_GPR) || (ctv_rk == TR_VRF) || (self()->cg()->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX) && ctv_rk!=TR_CCR));
 
       if (targetRegister->getState() == TR::RealRegister::Blocked)
          {
@@ -1778,7 +1778,7 @@ static void registerCopy(TR::Instruction     *precedingInstruction,
    TR::Instruction *instr = NULL;
 
    // Go for performance, disregarding the dirty SP de-normal condition
-   bool useVSXLogical = cg->comp()->target().cpu.getPPCSupportsVSX();
+   bool useVSXLogical = cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX);
    switch (rk)
       {
       case TR_GPR:
diff --git a/compiler/p/codegen/OMRMemoryReference.cpp b/compiler/p/codegen/OMRMemoryReference.cpp
index d353c6c975b..ac0b5159ff4 100644
--- a/compiler/p/codegen/OMRMemoryReference.cpp
+++ b/compiler/p/codegen/OMRMemoryReference.cpp
@@ -580,7 +580,7 @@ void OMR::Power::MemoryReference::populateMemoryReference(TR::Node *subTree, TR:
             cg->decReferenceCount(integerChild);
             }
          else if (integerChild->getEvaluationPriority(cg)>addressChild->getEvaluationPriority(cg) &&
-                  !(subTree->getOpCode().isArrayRef() && cg->comp()->target().cpu.id()==TR_PPCp6))
+                  !(subTree->getOpCode().isArrayRef() && cg->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P6)))
             {
             self()->populateMemoryReference(integerChild, cg);
             self()->populateMemoryReference(addressChild, cg);
diff --git a/compiler/p/codegen/OMRTreeEvaluator.cpp b/compiler/p/codegen/OMRTreeEvaluator.cpp
index f67600f615e..69af52c8b8a 100644
--- a/compiler/p/codegen/OMRTreeEvaluator.cpp
+++ b/compiler/p/codegen/OMRTreeEvaluator.cpp
@@ -406,7 +406,7 @@ TR::Register *OMR::Power::TreeEvaluator::iloadEvaluator(TR::Node *node, TR::Code
 
    if (needSync)
       {
-      TR::TreeEvaluator::postSyncConditions(node, cg, tempReg, tempMR, cg->comp()->target().cpu.id() >= TR_PPCp7 ? TR::InstOpCode::lwsync : TR::InstOpCode::isync);
+      TR::TreeEvaluator::postSyncConditions(node, cg, tempReg, tempMR, cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) ? TR::InstOpCode::lwsync : TR::InstOpCode::isync);
       }
 
    tempMR->decNodeReferenceCounts(cg);
@@ -560,7 +560,7 @@ TR::Register *OMR::Power::TreeEvaluator::aloadEvaluator(TR::Node *node, TR::Code
 
    if (needSync)
       {
-      TR::TreeEvaluator::postSyncConditions(node, cg, tempReg, tempMR, cg->comp()->target().cpu.id() >= TR_PPCp7 ? TR::InstOpCode::lwsync : TR::InstOpCode::isync);
+      TR::TreeEvaluator::postSyncConditions(node, cg, tempReg, tempMR, cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) ? TR::InstOpCode::lwsync : TR::InstOpCode::isync);
       }
    tempMR->decNodeReferenceCounts(cg);
 
@@ -601,7 +601,7 @@ TR::Register *OMR::Power::TreeEvaluator::lloadEvaluator(TR::Node *node, TR::Code
          generateTrg1MemInstruction(cg, TR::InstOpCode::ld, node, trgReg, tempMR);
       if (needSync)
          {
-         TR::TreeEvaluator::postSyncConditions(node, cg, trgReg, tempMR, cg->comp()->target().cpu.id() >= TR_PPCp7 ? TR::InstOpCode::lwsync : TR::InstOpCode::isync);
+         TR::TreeEvaluator::postSyncConditions(node, cg, trgReg, tempMR, cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) ? TR::InstOpCode::lwsync : TR::InstOpCode::isync);
          }
 
       tempMR->decNodeReferenceCounts(cg);
@@ -633,7 +633,7 @@ TR::Register *OMR::Power::TreeEvaluator::lloadEvaluator(TR::Node *node, TR::Code
             {
             TR::MemoryReference *tempMRStore1 = new (cg->trHeapMemory()) TR::MemoryReference(node, location->getSymbolReference(), 8, cg);
             generateMemSrc1Instruction(cg, TR::InstOpCode::stfd, node, tempMRStore1, doubleReg);
-            generateInstruction(cg, cg->comp()->target().cpu.id() >= TR_PPCp7 ? TR::InstOpCode::lwsync : TR::InstOpCode::isync, node);
+            generateInstruction(cg, cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) ? TR::InstOpCode::lwsync : TR::InstOpCode::isync, node);
             tempMRStore1->decNodeReferenceCounts(cg);
             }
          tempMRLoad1->forceIndexedForm(node, cg);
@@ -667,14 +667,14 @@ TR::Register *OMR::Power::TreeEvaluator::lloadEvaluator(TR::Node *node, TR::Code
                TR::MemoryReference *tempMRLoad1 = new (cg->trHeapMemory()) TR::MemoryReference(node, *tempMRStore1, 0, 4, cg);
                TR::MemoryReference *tempMRLoad2 = new (cg->trHeapMemory()) TR::MemoryReference(node, *tempMRStore1, 4, 4, cg);
                generateMemSrc1Instruction(cg, TR::InstOpCode::stfd, node, tempMRStore1, doubleReg);
-               generateInstruction(cg, cg->comp()->target().cpu.id() >= TR_PPCp7 ? TR::InstOpCode::lwsync : TR::InstOpCode::isync, node);
+               generateInstruction(cg, cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) ? TR::InstOpCode::lwsync : TR::InstOpCode::isync, node);
                generateTrg1MemInstruction(cg, TR::InstOpCode::lwz, node, highReg, tempMRLoad1);
                generateTrg1MemInstruction(cg, TR::InstOpCode::lwz, node, lowReg, tempMRLoad2);
                cg->freeSpill(location, 8, 0);
                }
             else
                {
-               if (cg->comp()->target().cpu.id() >= TR_PPCp8)
+               if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
                   {
                   TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
                   generateMvFprGprInstructions(cg, node, fpr2gprHost32, false, highReg, lowReg, doubleReg, tmp1);
@@ -764,7 +764,7 @@ TR::Register *OMR::Power::TreeEvaluator::commonByteLoadEvaluator(TR::Node *node,
    generateTrg1MemInstruction(cg, TR::InstOpCode::lbz, node, trgReg, tempMR);
    if (needSync)
       {
-      TR::TreeEvaluator::postSyncConditions(node, cg, trgReg, tempMR, cg->comp()->target().cpu.id() >= TR_PPCp7 ? TR::InstOpCode::lwsync : TR::InstOpCode::isync);
+      TR::TreeEvaluator::postSyncConditions(node, cg, trgReg, tempMR, cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) ? TR::InstOpCode::lwsync : TR::InstOpCode::isync);
       }
 
    if (signExtend)
@@ -817,7 +817,7 @@ TR::Register *OMR::Power::TreeEvaluator::sloadEvaluator(TR::Node *node, TR::Code
 
    if (needSync)
       {
-      TR::TreeEvaluator::postSyncConditions(node, cg, tempReg, tempMR, cg->comp()->target().cpu.id() >= TR_PPCp7 ? TR::InstOpCode::lwsync : TR::InstOpCode::isync);
+      TR::TreeEvaluator::postSyncConditions(node, cg, tempReg, tempMR, cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) ? TR::InstOpCode::lwsync : TR::InstOpCode::isync);
       }
 
    tempMR->decNodeReferenceCounts(cg);
@@ -840,7 +840,7 @@ TR::Register *OMR::Power::TreeEvaluator::cloadEvaluator(TR::Node *node, TR::Code
    generateTrg1MemInstruction(cg, TR::InstOpCode::lhz, node, tempReg, tempMR);
    if (needSync)
       {
-      TR::TreeEvaluator::postSyncConditions(node, cg, tempReg, tempMR, cg->comp()->target().cpu.id() >= TR_PPCp7 ? TR::InstOpCode::lwsync : TR::InstOpCode::isync);
+      TR::TreeEvaluator::postSyncConditions(node, cg, tempReg, tempMR, cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) ? TR::InstOpCode::lwsync : TR::InstOpCode::isync);
       }
 
    tempMR->decNodeReferenceCounts(cg);
@@ -1232,7 +1232,7 @@ TR::Register *OMR::Power::TreeEvaluator::lstoreEvaluator(TR::Node *node, TR::Cod
                   tempMRStore2->forceIndexedForm(node, cg);
                   TR::Register *highReg = cg->allocateRegister();
                   TR::Register *lowReg = cg->allocateRegister();
-                  if (cg->comp()->target().cpu.id() >= TR_PPCp8)
+                  if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
                      {
                      TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
                      generateMvFprGprInstructions(cg, node, fpr2gprHost32, false, highReg, lowReg, doubleReg, tmp1);
@@ -1254,7 +1254,7 @@ TR::Register *OMR::Power::TreeEvaluator::lstoreEvaluator(TR::Node *node, TR::Cod
                }
             else
                {
-               if (cg->comp()->target().cpu.id() >= TR_PPCp8)
+               if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
                   {
                   TR::Register * tmp1 = cg->allocateRegister(TR_FPR);
                   generateMvFprGprInstructions(cg, node, gpr2fprHost32, false, doubleReg, valueReg->getHighOrder(), valueReg->getLowOrder(), tmp1);
@@ -1828,7 +1828,7 @@ TR::Register *OMR::Power::TreeEvaluator::viremEvaluator(TR::Node *node, TR::Code
       TR::Register *trgAReg = cg->allocateRegister();
       generateTrg1MemInstruction(cg, TR::InstOpCode::lwa, node, srcA1Reg, new (cg->trHeapMemory()) TR::MemoryReference(srcV1IdxReg, i * 4, 4, cg));
       generateTrg1MemInstruction(cg, TR::InstOpCode::lwa, node, srcA2Reg, new (cg->trHeapMemory()) TR::MemoryReference(srcV2IdxReg, i * 4, 4, cg));
-      if (cg->comp()->target().cpu.id() >= TR_PPCp9)
+      if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
          {
          generateTrg1Src2Instruction(cg, TR::InstOpCode::modsw, node, trgAReg, srcA1Reg, srcA2Reg);
          }
@@ -1898,7 +1898,7 @@ TR::Register *OMR::Power::TreeEvaluator::vigetelemEvaluator(TR::Node *node, TR::
 TR::Register *OMR::Power::TreeEvaluator::getvelemEvaluator(TR::Node *node, TR::CodeGenerator *cg)
    {
    static bool disableDirectMove = feGetEnv("TR_disableDirectMove") ? true : false;
-   if (!disableDirectMove && cg->comp()->target().cpu.id() >= TR_PPCp8 && cg->comp()->target().cpu.getPPCSupportsVSX())
+   if (!disableDirectMove && cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) && cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX))
       {
       return TR::TreeEvaluator::getvelemDirectMoveHelper(node, cg);
       }
@@ -3061,8 +3061,7 @@ static void inlineArrayCopy(TR::Node *node, int64_t byteLen, TR::Register *src,
    store =TR::InstOpCode::Op_st;
 
    static bool disableLEArrayCopyInline  = (feGetEnv("TR_disableLEArrayCopyInline") != NULL);
-   TR_Processor  processor = cg->comp()->target().cpu.id();
-   bool  supportsLEArrayCopyInline = (processor >= TR_PPCp8) && !disableLEArrayCopyInline && cg->comp()->target().cpu.isLittleEndian() && cg->comp()->target().cpu.hasFPU() && cg->comp()->target().is64Bit();
+   bool  supportsLEArrayCopyInline = (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8)) && !disableLEArrayCopyInline && cg->comp()->target().cpu.isLittleEndian() && cg->comp()->target().cpu.hasFPU() && cg->comp()->target().is64Bit();
 
    TR::RealRegister::RegNum tempDep, srcDep, dstDep, cndDep;
    tempDep = TR::RealRegister::NoReg;
@@ -4577,9 +4576,7 @@ TR::Register *OMR::Power::TreeEvaluator::arraycopyEvaluator(TR::Node *node, TR::
       }
 
    static bool disableVSXArrayCopy  = (feGetEnv("TR_disableVSXArrayCopy") != NULL);
-   TR_Processor  processor = cg->comp()->target().cpu.id();
-
-   bool  supportsVSX = (processor >= TR_PPCp8) && !disableVSXArrayCopy && cg->comp()->target().cpu.getPPCSupportsVSX();
+   bool  supportsVSX = (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8)) && !disableVSXArrayCopy && cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_PPC_HAS_VSX);
 
    static bool disableLEArrayCopyHelper  = (feGetEnv("TR_disableLEArrayCopyHelper") != NULL);
    static bool disableVSXArrayCopyInlining = (feGetEnv("TR_enableVSXArrayCopyInlining") == NULL); // Disabling due to a performance regression
@@ -4602,7 +4599,7 @@ TR::Register *OMR::Power::TreeEvaluator::arraycopyEvaluator(TR::Node *node, TR::
 
    TR::RegisterDependencyConditions *conditions;
    int32_t numDeps = 0;
-   if(processor >= TR_PPCp8 && supportsVSX)
+   if(cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) && supportsVSX)
       {
       numDeps = cg->comp()->target().is64Bit() ? 10 : 13;
       if (supportsLEArrayCopy)
@@ -4615,7 +4612,7 @@ TR::Register *OMR::Power::TreeEvaluator::arraycopyEvaluator(TR::Node *node, TR::
    else
    if (cg->comp()->target().is64Bit())
       {
-      if (processor >= TR_PPCp6)
+      if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6))
          numDeps = 12;
       else
          numDeps = 8;
@@ -4650,7 +4647,7 @@ TR::Register *OMR::Power::TreeEvaluator::arraycopyEvaluator(TR::Node *node, TR::
    TR::addDependency(conditions, tmp1Reg, TR::RealRegister::gr5, TR_GPR, cg);
    TR::addDependency(conditions, tmp2Reg, TR::RealRegister::gr6, TR_GPR, cg);
 
-   if(processor >= TR_PPCp8 && supportsVSX)
+   if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) && supportsVSX)
       {
       vec0Reg = cg->allocateRegister(TR_VRF);
       vec1Reg = cg->allocateRegister(TR_VRF);
@@ -4688,7 +4685,7 @@ TR::Register *OMR::Power::TreeEvaluator::arraycopyEvaluator(TR::Node *node, TR::
          TR::addDependency(conditions, NULL, TR::RealRegister::fp11, TR_FPR, cg);
          }
       }
-   else if (processor >= TR_PPCp6)
+   else if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6))
       {
       // stfdp arrayCopy used
       TR::addDependency(conditions, NULL, TR::RealRegister::fp8, TR_FPR, cg);
@@ -4709,28 +4706,28 @@ TR::Register *OMR::Power::TreeEvaluator::arraycopyEvaluator(TR::Node *node, TR::
 
          if (node->isForwardArrayCopy())
             {
-            if(processor >= TR_PPCp8 && supportsVSX)
+            if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) && supportsVSX)
                {
                helper = TR_PPCforwardQuadWordArrayCopy_vsx;
                }
             else
             if (node->isWordElementArrayCopy())
                {
-               if (processor >= TR_PPCp6)
+               if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6))
                   helper = TR_PPCforwardWordArrayCopy_dp;
                else
                   helper = TR_PPCforwardWordArrayCopy;
                }
             else if (node->isHalfWordElementArrayCopy())
                {
-               if (processor >= TR_PPCp6 )
+               if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6))
                   helper = TR_PPCforwardHalfWordArrayCopy_dp;
                else
                   helper = TR_PPCforwardHalfWordArrayCopy;
                }
             else
                {
-               if (processor >= TR_PPCp6)
+               if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6))
                   helper = TR_PPCforwardArrayCopy_dp;
                else
                   {
@@ -4740,28 +4737,28 @@ TR::Register *OMR::Power::TreeEvaluator::arraycopyEvaluator(TR::Node *node, TR::
             }
          else // We are not sure it is forward or we have to do backward
             {
-            if(processor >= TR_PPCp8 && supportsVSX)
+            if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) && supportsVSX)
                {
                helper = TR_PPCquadWordArrayCopy_vsx;
                }
             else
             if (node->isWordElementArrayCopy())
                {
-               if (processor >= TR_PPCp6)
+               if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6))
                   helper = TR_PPCwordArrayCopy_dp;
                else
                   helper = TR_PPCwordArrayCopy;
                }
             else if (node->isHalfWordElementArrayCopy())
                {
-               if (processor >= TR_PPCp6)
+               if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6))
                   helper = TR_PPChalfWordArrayCopy_dp;
                else
                   helper = TR_PPChalfWordArrayCopy;
                }
             else
                {
-               if (processor >= TR_PPCp6)
+               if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6))
                   helper = TR_PPCarrayCopy_dp;
                else
                   {
diff --git a/compiler/p/codegen/PPCBinaryEncoding.cpp b/compiler/p/codegen/PPCBinaryEncoding.cpp
index 6f0d072300c..880b640aa4a 100644
--- a/compiler/p/codegen/PPCBinaryEncoding.cpp
+++ b/compiler/p/codegen/PPCBinaryEncoding.cpp
@@ -862,7 +862,7 @@ OMR::Power::Instruction::fillBinaryEncodingFields(uint32_t *cursor)
          // TODO: Split genop into two instructions depending on version of Power in use
          if (self()->getOpCodeValue() == TR::InstOpCode::genop)
             {
-            TR::RealRegister *r = self()->cg()->machine()->getRealRegister(TR::Compiler->target.cpu.id() > TR_PPCp6 ? TR::RealRegister::gr2 : TR::RealRegister::gr1);
+            TR::RealRegister *r = self()->cg()->machine()->getRealRegister(TR::Compiler->target.cpu.isAtLeast(OMR_PROCESSOR_PPC_P7) ? TR::RealRegister::gr2 : TR::RealRegister::gr1);
             fillFieldRA(self(), cursor, r);
             fillFieldRS(self(), cursor, r);
             }
diff --git a/compiler/p/codegen/PPCInstruction.cpp b/compiler/p/codegen/PPCInstruction.cpp
index fbba50030a6..a7c080b5601 100644
--- a/compiler/p/codegen/PPCInstruction.cpp
+++ b/compiler/p/codegen/PPCInstruction.cpp
@@ -1028,7 +1028,7 @@ TR::PPCTrg1MemInstruction::PPCTrg1MemInstruction(
 
 bool TR::PPCTrg1MemInstruction::encodeMutexHint()
    {
-   return cg()->comp()->target().cpu.id() >= TR_PPCp6 && (getOpCodeValue() == TR::InstOpCode::lwarx || getOpCodeValue() == TR::InstOpCode::ldarx);
+   return cg()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P6) && (getOpCodeValue() == TR::InstOpCode::lwarx || getOpCodeValue() == TR::InstOpCode::ldarx);
    }
 
 
@@ -1298,7 +1298,7 @@ void TR::PPCControlFlowInstruction::assignRegisters(TR_RegisterKinds kindToBeAss
          cg()->traceRAInstruction(cursor = generateLabelInstruction(cg(), TR::InstOpCode::label, currentNode, label2, cursor));
          break;
       case TR::InstOpCode::setbool:
-         if (cg()->comp()->target().cpu.id() >= TR_PPCp9 && getCmpOpValue() == TR::InstOpCode::fcmpu && (getOpCode2Value() == TR::InstOpCode::blt || getOpCode2Value() ==  TR::InstOpCode::bgt))
+         if (cg()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9) && getCmpOpValue() == TR::InstOpCode::fcmpu && (getOpCode2Value() == TR::InstOpCode::blt || getOpCode2Value() ==  TR::InstOpCode::bgt))
             {
 
             /* Used with: dcmpgt, dcmplt, fcmpgt and fcmplt*/
@@ -1368,7 +1368,7 @@ void TR::PPCControlFlowInstruction::assignRegisters(TR_RegisterKinds kindToBeAss
       case TR::InstOpCode::idiv:
          cg()->traceRAInstruction(cursor = generateTrg1Src1ImmInstruction(cg(), TR::InstOpCode::cmpi4, currentNode, getTargetRegister(0), getSourceRegister(1), -1, cursor));
          cg()->traceRAInstruction(cursor = generateTrg1Src1Instruction(cg(), TR::InstOpCode::neg, currentNode, getTargetRegister(1), getSourceRegister(0), cursor));
-         if (cg()->comp()->target().cpu.id() >= TR_PPCgp)
+         if (cg()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_GP))
             // use PPC AS branch hint
             cg()->traceRAInstruction(cursor = generateConditionalBranchInstruction(cg(), TR::InstOpCode::beq, PPCOpProp_BranchUnlikely, currentNode, label2, getTargetRegister(0), cursor));
          else
@@ -1379,12 +1379,12 @@ void TR::PPCControlFlowInstruction::assignRegisters(TR_RegisterKinds kindToBeAss
       case TR::InstOpCode::irem:
          cg()->traceRAInstruction(cursor = generateTrg1Src1ImmInstruction(cg(), TR::InstOpCode::cmpi4, currentNode, getTargetRegister(0), getSourceRegister(1), -1, cursor));
          cg()->traceRAInstruction(cursor = generateTrg1ImmInstruction(cg(), TR::InstOpCode::li, currentNode, getTargetRegister(1), 0, cursor));
-         if (cg()->comp()->target().cpu.id() >= TR_PPCgp)
+         if (cg()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_GP))
             // use PPC AS branch hint
             cg()->traceRAInstruction(cursor = generateConditionalBranchInstruction(cg(), TR::InstOpCode::beq, PPCOpProp_BranchUnlikely, currentNode, label2, getTargetRegister(0), cursor));
          else
             cg()->traceRAInstruction(cursor = generateConditionalBranchInstruction(cg(), TR::InstOpCode::beq, currentNode, label2, getTargetRegister(0), cursor));
-         if (cg()->comp()->target().cpu.id() >= TR_PPCp9)
+         if (cg()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
             {
             cg()->traceRAInstruction(cursor = generateTrg1Src2Instruction(cg(), TR::InstOpCode::modsw, currentNode, getTargetRegister(1), getSourceRegister(0), getSourceRegister(1), cursor));
             }
@@ -1399,7 +1399,7 @@ void TR::PPCControlFlowInstruction::assignRegisters(TR_RegisterKinds kindToBeAss
       case TR::InstOpCode::ldiv:
          cg()->traceRAInstruction(cursor = generateTrg1Src1ImmInstruction(cg(), TR::InstOpCode::cmpi8, currentNode, getTargetRegister(0), getSourceRegister(1), -1, cursor));
          cg()->traceRAInstruction(cursor = generateTrg1Src1Instruction(cg(), TR::InstOpCode::neg, currentNode, getTargetRegister(1), getSourceRegister(0), cursor));
-         if (cg()->comp()->target().cpu.id() >= TR_PPCgp)
+         if (cg()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_GP))
             // use PPC AS branch hint
             cg()->traceRAInstruction(cursor = generateConditionalBranchInstruction(cg(), TR::InstOpCode::beq, PPCOpProp_BranchUnlikely, currentNode, label2, getTargetRegister(0), cursor));
          else
@@ -1410,12 +1410,12 @@ void TR::PPCControlFlowInstruction::assignRegisters(TR_RegisterKinds kindToBeAss
       case TR::InstOpCode::lrem:
          cg()->traceRAInstruction(cursor = generateTrg1Src1ImmInstruction(cg(), TR::InstOpCode::cmpi8, currentNode, getTargetRegister(0), getSourceRegister(1), -1, cursor));
          cg()->traceRAInstruction(cursor = generateTrg1ImmInstruction(cg(), TR::InstOpCode::li, currentNode, getTargetRegister(1), 0, cursor));
-         if (cg()->comp()->target().cpu.id() >= TR_PPCgp)
+         if (cg()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_GP))
             // use PPC AS branch hint
             cg()->traceRAInstruction(cursor = generateConditionalBranchInstruction(cg(), TR::InstOpCode::beq, PPCOpProp_BranchUnlikely, currentNode, label2, getTargetRegister(0), cursor));
          else
             cg()->traceRAInstruction(cursor = generateConditionalBranchInstruction(cg(), TR::InstOpCode::beq, currentNode, label2, getTargetRegister(0), cursor));
-         if (cg()->comp()->target().cpu.id() >= TR_PPCp9)
+         if (cg()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P9))
             {
             cg()->traceRAInstruction(cursor = generateTrg1Src2Instruction(cg(), TR::InstOpCode::modsd, currentNode, getTargetRegister(1), getSourceRegister(0), getSourceRegister(1), cursor));
             }
@@ -1432,19 +1432,19 @@ void TR::PPCControlFlowInstruction::assignRegisters(TR_RegisterKinds kindToBeAss
          cg()->traceRAInstruction(cursor = generateTrg1Src1Instruction(cg(), TR::InstOpCode::fctiwz, currentNode, getTargetRegister(1), getSourceRegister(0), cursor));
          cg()->traceRAInstruction(cursor = generateTrg1ImmInstruction(cg(), TR::InstOpCode::li, currentNode, getTargetRegister(2), 0, cursor));
 
-         if (cg()->comp()->target().cpu.id() < TR_PPCp8)
+         if (!cg()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
             {
             tempMR = new (cg()->trHeapMemory()) TR::MemoryReference(cg()->getStackPointerRegister(), -8, 8, cg());
             cg()->traceRAInstruction(cursor = generateMemSrc1Instruction(cg(), TR::InstOpCode::stfd, currentNode, tempMR, getTargetRegister(1), cursor));
             }
 
-         if (cg()->comp()->target().cpu.id() >= TR_PPCgp)
+         if (cg()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_GP))
             // use PPC AS branch hint
             cg()->traceRAInstruction(cursor = generateConditionalBranchInstruction(cg(), TR::InstOpCode::bne, PPCOpProp_BranchUnlikely, currentNode, label2, getTargetRegister(0), cursor));
          else
             cg()->traceRAInstruction(cursor = generateConditionalBranchInstruction(cg(), TR::InstOpCode::bne, currentNode, label2, getTargetRegister(0), cursor));
 
-         if (cg()->comp()->target().cpu.id() >= TR_PPCp8)
+         if (cg()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8))
             cg()->traceRAInstruction(cursor = generateTrg1Src1Instruction(cg(), TR::InstOpCode::mfvsrwz, currentNode, getTargetRegister(2), getTargetRegister(1), cursor));
          else
             cg()->traceRAInstruction(cursor = generateTrg1MemInstruction(cg(), TR::InstOpCode::lwz, currentNode, getTargetRegister(2), new (cg()->trHeapMemory()) TR::MemoryReference(currentNode, *tempMR, 4, 4, cg()), cursor));
@@ -1462,13 +1462,13 @@ void TR::PPCControlFlowInstruction::assignRegisters(TR_RegisterKinds kindToBeAss
             cg()->traceRAInstruction(cursor = generateTrg1ImmInstruction(cg(), TR::InstOpCode::li, currentNode, getTargetRegister(2), 0, cursor));
             cg()->traceRAInstruction(cursor = generateTrg1ImmInstruction(cg(), TR::InstOpCode::li, currentNode, getTargetRegister(3), 0, cursor));
             }
-         if (cg()->comp()->target().cpu.id() < TR_PPCp8 || cg()->comp()->target().is32Bit())
+         if (!cg()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8)|| cg()->comp()->target().is32Bit())
             {
             tempMR = new (cg()->trHeapMemory()) TR::MemoryReference(cg()->getStackPointerRegister(), -8, 8, cg());
             cg()->traceRAInstruction(cursor = generateMemSrc1Instruction(cg(), TR::InstOpCode::stfd, currentNode, tempMR, getTargetRegister(1), cursor));
             }
 
-         if (cg()->comp()->target().cpu.id() >= TR_PPCgp)
+         if (cg()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_GP))
             // use PPC AS branch hint
             cg()->traceRAInstruction(cursor = generateConditionalBranchInstruction(cg(), TR::InstOpCode::bne, PPCOpProp_BranchUnlikely, currentNode, label2, getTargetRegister(0), cursor));
          else
@@ -1476,7 +1476,7 @@ void TR::PPCControlFlowInstruction::assignRegisters(TR_RegisterKinds kindToBeAss
 
          if (cg()->comp()->target().is64Bit())
             {
-            if (cg()->comp()->target().cpu.id() >= TR_PPCp8 && cg()->comp()->target().is64Bit())
+            if (cg()->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P8) && cg()->comp()->target().is64Bit())
                cg()->traceRAInstruction(cursor = generateTrg1Src1Instruction(cg(), TR::InstOpCode::mfvsrd, currentNode, getTargetRegister(2), getTargetRegister(1), cursor));
             else
                cg()->traceRAInstruction(cursor = generateTrg1MemInstruction(cg(), TR::InstOpCode::ld, currentNode, getTargetRegister(2), tempMR, cursor));
diff --git a/compiler/p/codegen/PPCSystemLinkage.cpp b/compiler/p/codegen/PPCSystemLinkage.cpp
index 2849190f77e..3876e896a37 100644
--- a/compiler/p/codegen/PPCSystemLinkage.cpp
+++ b/compiler/p/codegen/PPCSystemLinkage.cpp
@@ -680,7 +680,7 @@ TR::PPCSystemLinkage::createPrologue(
 
    if (savedFirst <= TR::RealRegister::LastGPR)
       {
-      if (cg()->comp()->target().cpu.id() == TR_PPCgp || cg()->comp()->target().is64Bit() ||
+      if (cg()->comp()->target().cpu.is(OMR_PROCESSOR_PPC_GP) || cg()->comp()->target().is64Bit() ||
           (!comp()->getOption(TR_OptimizeForSpace) &&
            TR::RealRegister::LastGPR - savedFirst <= 3))
          for (regIndex=TR::RealRegister::LastGPR; regIndex>=savedFirst; regIndex=(TR::RealRegister::RegNum)((uint32_t)regIndex-1))
@@ -783,7 +783,7 @@ TR::PPCSystemLinkage::createEpilogue(TR::Instruction *cursor)
 
    if (savedFirst <= TR::RealRegister::LastGPR)
       {
-      if (cg()->comp()->target().cpu.id() == TR_PPCgp || cg()->comp()->target().is64Bit() ||
+      if (cg()->comp()->target().cpu.is(OMR_PROCESSOR_PPC_GP) || cg()->comp()->target().is64Bit() ||
           (!comp()->getOption(TR_OptimizeForSpace) &&
            TR::RealRegister::LastGPR - savedFirst <= 3))
          for (regIndex=TR::RealRegister::LastGPR; regIndex>=savedFirst; regIndex=(TR::RealRegister::RegNum)((uint32_t)regIndex-1))
diff --git a/compiler/p/codegen/UnaryEvaluator.cpp b/compiler/p/codegen/UnaryEvaluator.cpp
index f723cfefd81..7bf966030a2 100644
--- a/compiler/p/codegen/UnaryEvaluator.cpp
+++ b/compiler/p/codegen/UnaryEvaluator.cpp
@@ -520,7 +520,7 @@ TR::Register *OMR::Power::TreeEvaluator::i2sEvaluator(TR::Node *node, TR::CodeGe
    TR::Node *child  = node->getFirstChild();
    TR::Register *trgReg = cg->allocateRegister();
 
-   if (cg->comp()->target().cpu.id() != TR_PPCp6 &&  // avoid algebraic loads on P6
+   if (!cg->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P6) &&  // avoid algebraic loads on P6
        child->getReferenceCount() == 1 &&
        child->getOpCode().isMemoryReference() &&
        child->getRegister() == NULL)
@@ -663,7 +663,7 @@ TR::Register *OMR::Power::TreeEvaluator::l2sEvaluator(TR::Node *node, TR::CodeGe
       {
       TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(child, 2, cg);
       tempMR->addToOffset(node, cg->comp()->target().cpu.isBigEndian()?6:0, cg);
-      if (cg->comp()->target().cpu.id() == TR_PPCp6)  // avoid algebraic loads on P6
+      if (cg->comp()->target().cpu.is(OMR_PROCESSOR_PPC_P6))  // avoid algebraic loads on P6
          {
          generateTrg1MemInstruction(cg, TR::InstOpCode::lhz, node, trgReg, tempMR);
          generateTrg1Src1Instruction(cg, TR::InstOpCode::extsh, node, trgReg, trgReg);
diff --git a/compiler/p/env/OMRCPU.cpp b/compiler/p/env/OMRCPU.cpp
index 1421bae2ca3..0fbaa3d55f2 100644
--- a/compiler/p/env/OMRCPU.cpp
+++ b/compiler/p/env/OMRCPU.cpp
@@ -20,21 +20,56 @@
  *******************************************************************************/
 
 #include "env/CPU.hpp"
-
+#include "env/CompilerEnv.hpp"
 #include "env/Processors.hpp"
 #include "infra/Assert.hpp"
 
+char* feGetEnv(const char*);
+
+bool
+OMR::Power::CPU::getPPCSupportsAES()
+   {
+   return self()->supportsFeature(OMR_FEATURE_PPC_HAS_ALTIVEC) && self()->isAtLeast(OMR_PROCESSOR_PPC_P8) && self()->supportsFeature(OMR_FEATURE_PPC_HAS_VSX);
+   }
+
 bool
-OMR::Power::CPU::getPPCis64bit()
+OMR::Power::CPU::hasPopulationCountInstruction()
    {
-   TR_ASSERT(self()->id() >= TR_FirstPPCProcessor && self()->id() <= TR_LastPPCProcessor, "Not a valid PPC Processor Type");
-   return (self()->id() >= TR_FirstPPC64BitProcessor)? true : false;
+#if defined(J9OS_I5)
+   return false;
+#else
+   return self()->isAtLeast(OMR_PROCESSOR_PPC_P7);
+#endif
+   }
+
+bool
+OMR::Power::CPU::supportsDecimalFloatingPoint()
+   {
+   return self()->supportsFeature(OMR_FEATURE_PPC_HAS_DFP);
+   }
+
+bool 
+OMR::Power::CPU::getSupportsHardwareSQRT()
+   {
+   return self()->isAtLeast(OMR_PROCESSOR_PPC_HW_SQRT_FIRST);
+   }
+
+bool
+OMR::Power::CPU::getSupportsHardwareRound()
+   {
+   return self()->isAtLeast(OMR_PROCESSOR_PPC_HW_ROUND_FIRST);
+   }
+
+bool
+OMR::Power::CPU::getSupportsHardwareCopySign()
+   {
+   return self()->isAtLeast(OMR_PROCESSOR_PPC_HW_COPY_SIGN_FIRST);
    }
 
 bool
 OMR::Power::CPU::supportsTransactionalMemoryInstructions()
    {
-   return self()->getPPCSupportsTM();
+   return self()->supportsFeature(OMR_FEATURE_PPC_HTM);
    }
 
 bool
@@ -45,23 +80,128 @@ OMR::Power::CPU::isTargetWithinIFormBranchRange(intptr_t targetAddress, intptr_t
           range >= self()->maxIFormBranchBackwardOffset();
    }
 
-bool 
-OMR::Power::CPU::getSupportsHardwareSQRT()
+bool
+OMR::Power::CPU::supportsFeature(uint32_t feature)
    {
-   TR_ASSERT(self()->id() >= TR_FirstPPCProcessor && self()->id() <= TR_LastPPCProcessor, "Not a valid PPC Processor Type");
-   return self()->id() >= TR_FirstPPCHwSqrtProcessor;
+   if (TR::Compiler->omrPortLib == NULL)
+      {
+      return false;
+      }
+
+   OMRPORT_ACCESS_FROM_OMRPORT(TR::Compiler->omrPortLib);
+   return (TRUE == omrsysinfo_processor_has_feature(&_processorDescription, feature));
    }
 
 bool
-OMR::Power::CPU::getSupportsHardwareRound()
+OMR::Power::CPU::is(OMRProcessorArchitecture p)
    {
-   TR_ASSERT(self()->id() >= TR_FirstPPCProcessor && self()->id() <= TR_LastPPCProcessor, "Not a valid PPC Processor Type");
-   return self()->id() >= TR_FirstPPCHwRoundProcessor;
+   if (TR::Compiler->omrPortLib == NULL)
+      return self()->id() == self()->get_old_processor_type_from_new_processor_type(p);
+
+   TR_ASSERT_FATAL((_processorDescription.processor == p) == (self()->id() == self()->get_old_processor_type_from_new_processor_type(p)), "is test %d failed, id() %d, _processorDescription.processor %d", p, self()->id(), _processorDescription.processor);
+   return _processorDescription.processor == p;
    }
-   
+
 bool
-OMR::Power::CPU::getSupportsHardwareCopySign()
+OMR::Power::CPU::isAtLeast(OMRProcessorArchitecture p)
+   {
+   if (TR::Compiler->omrPortLib == NULL)
+      return self()->id() >= self()->get_old_processor_type_from_new_processor_type(p);
+
+   TR_ASSERT_FATAL((_processorDescription.processor >= p) == (self()->id() >= self()->get_old_processor_type_from_new_processor_type(p)), "is at least test %d failed, id() %d, _processorDescription.processor %d", p, self()->id(), _processorDescription.processor);
+   return _processorDescription.processor >= p;
+   }
+
+bool
+OMR::Power::CPU::isAtMost(OMRProcessorArchitecture p)
+   {
+   if (TR::Compiler->omrPortLib == NULL)
+      return self()->id() <= self()->get_old_processor_type_from_new_processor_type(p);
+
+   TR_ASSERT_FATAL((_processorDescription.processor <= p) == (self()->id() <= self()->get_old_processor_type_from_new_processor_type(p)), "is at most test %d failed, id() %d, _processorDescription.processor %d", p, self()->id(), _processorDescription.processor);
+   return _processorDescription.processor <= p;
+   }
+
+TR_Processor
+OMR::Power::CPU::get_old_processor_type_from_new_processor_type(OMRProcessorArchitecture p)
+   {
+   switch(p)
+      {
+      case OMR_PROCESSOR_PPC_FIRST:
+         return TR_FirstPPCProcessor;
+      case OMR_PROCESSOR_PPC_RIOS1:
+         return TR_PPCrios1;
+      case OMR_PROCESSOR_PPC_PWR403:
+         return TR_PPCpwr403;
+      case OMR_PROCESSOR_PPC_PWR405:
+         return TR_PPCpwr405;
+      case OMR_PROCESSOR_PPC_PWR440:
+         return TR_PPCpwr440;
+      case OMR_PROCESSOR_PPC_PWR601:
+         return TR_PPCpwr601;
+      case OMR_PROCESSOR_PPC_PWR602:
+         return TR_PPCpwr602;
+      case OMR_PROCESSOR_PPC_PWR603:
+         return TR_PPCpwr603;
+      case OMR_PROCESSOR_PPC_82XX:
+         return TR_PPC82xx;
+      case OMR_PROCESSOR_PPC_7XX:
+         return TR_PPC7xx;
+      case OMR_PROCESSOR_PPC_PWR604:
+         return TR_PPCpwr604;
+      case OMR_PROCESSOR_PPC_RIOS2:
+         return TR_PPCrios2;
+      case OMR_PROCESSOR_PPC_PWR2S:
+         return TR_PPCpwr2s;
+      case OMR_PROCESSOR_PPC_PWR620:
+         return TR_PPCpwr620;
+      case OMR_PROCESSOR_PPC_PWR630:
+         return TR_PPCpwr630;
+      case OMR_PROCESSOR_PPC_NSTAR:
+         return TR_PPCnstar;
+      case OMR_PROCESSOR_PPC_PULSAR:
+         return TR_PPCpulsar;
+      case OMR_PROCESSOR_PPC_GP:
+         return TR_PPCgp;
+      case OMR_PROCESSOR_PPC_GR:
+         return TR_PPCgr;
+      case OMR_PROCESSOR_PPC_GPUL:
+         return TR_PPCgpul;
+      case OMR_PROCESSOR_PPC_P6:
+         return TR_PPCp6;
+      case OMR_PROCESSOR_PPC_ATLAS:
+         return TR_PPCatlas;
+      case OMR_PROCESSOR_PPC_BALANCED:
+         return TR_PPCbalanced;
+      case OMR_PROCESSOR_PPC_CELLPX:
+         return TR_PPCcellpx;
+      case OMR_PROCESSOR_PPC_P7:
+         return TR_PPCp7;
+      case OMR_PROCESSOR_PPC_P8:
+         return TR_PPCp8;
+      case OMR_PROCESSOR_PPC_P9:
+         return TR_PPCp9;
+      case OMR_PROCESSOR_PPC_P10:
+         return TR_PPCp10;
+      default:
+         TR_ASSERT_FATAL(false, "Unknown processor!");
+      }
+   return TR_FirstPPCProcessor;
+   }
+
+void
+OMR::Power::CPU::applyUserOptions()
    {
-   TR_ASSERT(self()->id() >= TR_FirstPPCProcessor && self()->id() <= TR_LastPPCProcessor, "Not a valid PPC Processor Type");
-   return self()->id() >= TR_FirstPPCHwCopySignProcessor;
+   // P10 support is not yet well-tested, so it's currently gated behind an environment
+   // variable to prevent it from being used by accident by users who use old versions of
+   // OMR once P10 chips become available.
+   if (_processorDescription.processor == OMR_PROCESSOR_PPC_P10)
+      {
+      static bool enableP10 = feGetEnv("TR_EnableExperimentalPower10Support");
+      if (!enableP10)
+         {
+         _processorDescription.processor = OMR_PROCESSOR_PPC_P9;
+         _processorDescription.physicalProcessor = OMR_PROCESSOR_PPC_P9;
+         }
+      }
    }
diff --git a/compiler/p/env/OMRCPU.hpp b/compiler/p/env/OMRCPU.hpp
index 9c82578af03..9c957745a4b 100644
--- a/compiler/p/env/OMRCPU.hpp
+++ b/compiler/p/env/OMRCPU.hpp
@@ -48,7 +48,13 @@ class OMR_EXTENSIBLE CPU : public OMR::CPU
    {
 protected:
 
-   CPU() : OMR::CPU() {}
+   CPU() :
+         OMR::CPU()
+      {
+      _processorDescription.processor = OMR_PROCESSOR_PPC_UNKNOWN;
+      _processorDescription.physicalProcessor = OMR_PROCESSOR_PPC_UNKNOWN;
+      memset(_processorDescription.features, 0, OMRPORT_SYSINFO_FEATURES_SIZE*sizeof(uint32_t));
+      }
    CPU(const OMRProcessorDesc& processorDescription) : OMR::CPU(processorDescription) {}
 
 public:
@@ -56,15 +62,13 @@ class OMR_EXTENSIBLE CPU : public OMR::CPU
    bool getSupportsHardwareSQRT();
    bool getSupportsHardwareRound();
    bool getSupportsHardwareCopySign();
+   bool getPPCSupportsAES();
 
-   bool getPPCis64bit();
-   bool getPPCSupportsVMX() { return false; }
-   bool getPPCSupportsVSX() { return false; }
-   bool getPPCSupportsAES() { return false; }
-   bool getPPCSupportsTM()  { return false; }
+   bool hasPopulationCountInstruction();
+   bool supportsDecimalFloatingPoint();
 
    /** @brief Determines whether the Transactional Memory (TM) facility is available on the current processor.
-    *         Alias of getPPCSupportsTM() as a platform agnostic query.
+    *         Alias of supportsFeature(OMR_FEATURE_PPC_HTM) as a platform agnostic query.
     *
     *  @return true if TM is available, false otherwise.
     */
@@ -99,7 +103,13 @@ class OMR_EXTENSIBLE CPU : public OMR::CPU
     * @return true if the target is within range; false otherwise.
     */
    bool isTargetWithinIFormBranchRange(intptr_t targetAddress, intptr_t sourceAddress);
-
+  
+   bool supportsFeature(uint32_t feature);
+   bool is(OMRProcessorArchitecture p);
+   bool isAtLeast(OMRProcessorArchitecture p);
+   bool isAtMost(OMRProcessorArchitecture p);
+   TR_Processor get_old_processor_type_from_new_processor_type(OMRProcessorArchitecture p);
+   void applyUserOptions();
    };
 
 }
diff --git a/include_core/omrport.h b/include_core/omrport.h
index 58c11fda1d7..2c7dbcdfec0 100644
--- a/include_core/omrport.h
+++ b/include_core/omrport.h
@@ -1247,7 +1247,7 @@ typedef enum OMRProcessorArchitecture {
 	OMR_PROCESSOR_PPC_HW_ROUND_FIRST,
 	OMR_PROCESSOR_PPC_HW_COPY_SIGN_FIRST = OMR_PROCESSOR_PPC_HW_ROUND_FIRST,
 	OMR_PROCESSOR_PPC_P6 = OMR_PROCESSOR_PPC_HW_COPY_SIGN_FIRST,
-	OMR_PROCESOSR_PPC_ATLAS,
+	OMR_PROCESSOR_PPC_ATLAS,
 	OMR_PROCESSOR_PPC_BALANCED,
 	OMR_PROCESSOR_PPC_CELLPX,
 	// The following processors support VSX