From 7186e94283def6d2c43307630a4d95df6fb1487a Mon Sep 17 00:00:00 2001
From: Vidushi Shukla <vidushi.shukla@gmail.com>
Date: Fri, 5 May 2023 16:10:07 +0530
Subject: [PATCH] Provide support for LZCNT and TZCNT in X86Ops.ins

---
 compiler/x/codegen/X86Ops.ins               | 30 +++++++++++++++++++++
 fvtest/compilerunittest/x/BinaryEncoder.cpp | 10 +++++++
 2 files changed, 40 insertions(+)

diff --git a/compiler/x/codegen/X86Ops.ins b/compiler/x/codegen/X86Ops.ins
index f501c527b4d..880c23fe086 100644
--- a/compiler/x/codegen/X86Ops.ins
+++ b/compiler/x/codegen/X86Ops.ins
@@ -2545,6 +2545,21 @@ INSTRUCTION(LEA8RegMem, lea,
             PROPERTY0(IA32OpProp_ModifiesTarget),
             PROPERTY1(IA32OpProp1_LongSource | IA32OpProp1_LongTarget | IA32OpProp1_SourceIsMemRef),
             FEATURES(0)),
+INSTRUCTION(LZCNT2RegReg, lzcnt,
+            BINARY(VEX_L___, VEX_vNONE, PREFIX_66_F3, REX__, ESCAPE_0F__, 0xbd, 0, ModRM_RM__, Immediate_0),
+            PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_ShortTarget | IA32OpProp_ShortSource | IA32OpProp_ModifiesZeroFlag | IA32OpProp_ModifiesCarryFlag | IA32OpProp_SourceRegisterInModRM ),
+            PROPERTY1(0),
+            FEATURES(0)),
+INSTRUCTION(LZCNT4RegReg, lzcnt,
+            BINARY(VEX_L___, VEX_vNONE, PREFIX_F3, REX__, ESCAPE_0F__, 0xbd, 0, ModRM_RM__, Immediate_0),
+            PROPERTY0(IA32OpProp_ModifiesTarget |  IA32OpProp_IntSource | IA32OpProp_IntTarget | IA32OpProp_ModifiesZeroFlag | IA32OpProp_ModifiesCarryFlag | IA32OpProp_SourceRegisterInModRM ),
+            PROPERTY1(0),
+            FEATURES(0)),
+INSTRUCTION(LZCNT8RegReg, lzcnt,
+            BINARY(VEX_L___, VEX_vNONE, PREFIX_F3, REX_W, ESCAPE_0F__, 0xbd, 0, ModRM_RM__, Immediate_0),
+            PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_ModifiesZeroFlag | IA32OpProp_ModifiesCarryFlag | IA32OpProp_SourceRegisterInModRM ),
+            PROPERTY1(IA32OpProp1_LongSource | IA32OpProp1_LongTarget),
+            FEATURES(0)),
 INSTRUCTION(S1MemReg, mov,
             BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_____, 0x88, 0, ModRM_MR__, Immediate_0),
             PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_ByteSource | IA32OpProp_ByteTarget),
@@ -5144,6 +5159,21 @@ INSTRUCTION(TEST8MemReg, test,
             PROPERTY0(IA32OpProp_ModifiesOverflowFlag | IA32OpProp_ModifiesSignFlag | IA32OpProp_ModifiesZeroFlag | IA32OpProp_ModifiesParityFlag | IA32OpProp_ModifiesCarryFlag | IA32OpProp_UsesTarget),
             PROPERTY1(IA32OpProp1_LongSource | IA32OpProp1_LongTarget | IA32OpProp1_FusableCompare),
             FEATURES(0)),
+INSTRUCTION(TZCNT2RegReg, tzcnt,
+            BINARY(VEX_L___, VEX_vNONE, PREFIX_66_F3, REX__, ESCAPE_0F__, 0xbc, 0, ModRM_RM__, Immediate_0),
+            PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_ShortTarget | IA32OpProp_ShortSource | IA32OpProp_ModifiesZeroFlag | IA32OpProp_ModifiesCarryFlag | IA32OpProp_SourceRegisterInModRM ),
+            PROPERTY1(0),
+            FEATURES(0)),
+INSTRUCTION(TZCNT4RegReg, tzcnt,
+            BINARY(VEX_L___, VEX_vNONE, PREFIX_F3, REX__, ESCAPE_0F__, 0xbc, 0, ModRM_RM__, Immediate_0),
+            PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_IntTarget | IA32OpProp_IntSource | IA32OpProp_ModifiesZeroFlag | IA32OpProp_ModifiesCarryFlag | IA32OpProp_SourceRegisterInModRM ),
+            PROPERTY1(0),
+            FEATURES(0)),
+INSTRUCTION(TZCNT8RegReg, tzcnt,
+            BINARY(VEX_L___, VEX_vNONE, PREFIX_F3, REX_W, ESCAPE_0F__, 0xbc, 0, ModRM_RM__, Immediate_0),
+            PROPERTY0(IA32OpProp_ModifiesTarget | IA32OpProp_ModifiesZeroFlag | IA32OpProp_ModifiesCarryFlag | IA32OpProp_SourceRegisterInModRM ),
+            PROPERTY1(IA32OpProp1_LongSource | IA32OpProp1_LongTarget),
+            FEATURES(0)),
 INSTRUCTION(UD2, ud2,
             BINARY(VEX_L___, VEX_vNONE, PREFIX___, REX__, ESCAPE_0F__, 0x0b, 0, ModRM_NONE, Immediate_0),
             PROPERTY0(0),
diff --git a/fvtest/compilerunittest/x/BinaryEncoder.cpp b/fvtest/compilerunittest/x/BinaryEncoder.cpp
index ccadd6ea23a..d024892583e 100644
--- a/fvtest/compilerunittest/x/BinaryEncoder.cpp
+++ b/fvtest/compilerunittest/x/BinaryEncoder.cpp
@@ -695,6 +695,16 @@ INSTANTIATE_TEST_CASE_P(AVX512MaskRegSimdEVEX512Test, XRegRegEncEncodingTest, ::
     std::make_tuple(TR::InstOpCode::VPMOVB2MRegReg,    TR::RealRegister::k2, TR::RealRegister::xmm5,   OMR::X86::EVEX_L128,  "62f27e0829d5")
 )));
 
+INSTANTIATE_TEST_CASE_P(GeneralPurposeRegRegTest, XRegRegEncEncodingTest, ::testing::ValuesIn(*TRTest::MakeVector<std::tuple<TR::InstOpCode::Mnemonic, TR::RealRegister::RegNum, TR::RealRegister::RegNum, OMR::X86::Encoding, TRTest::BinaryInstruction>>(
+    std::make_tuple(TR::InstOpCode::LZCNT2RegReg,   TR::RealRegister::eax,  TR::RealRegister::ecx, OMR::X86::Default, "66f30fbdc1"),
+    std::make_tuple(TR::InstOpCode::LZCNT4RegReg,   TR::RealRegister::eax,  TR::RealRegister::ecx, OMR::X86::Default, "f30fbdc1"),
+    std::make_tuple(TR::InstOpCode::LZCNT8RegReg,   TR::RealRegister::eax,  TR::RealRegister::ecx, OMR::X86::Default, "f3480fbdc1"),
+
+    std::make_tuple(TR::InstOpCode::TZCNT2RegReg,   TR::RealRegister::eax,  TR::RealRegister::ecx, OMR::X86::Default, "66f30fbcc1"),
+    std::make_tuple(TR::InstOpCode::TZCNT4RegReg,   TR::RealRegister::eax,  TR::RealRegister::ecx, OMR::X86::Default, "f30fbcc1"),
+    std::make_tuple(TR::InstOpCode::TZCNT8RegReg,   TR::RealRegister::eax,  TR::RealRegister::ecx, OMR::X86::Default, "f3480fbcc1")
+)));
+
 INSTANTIATE_TEST_CASE_P(Branch, XRegRegEncodingTest, ::testing::ValuesIn(*TRTest::MakeVector<std::tuple<TR::InstOpCode::Mnemonic, TR::RealRegister::RegNum, TR::RealRegister::RegNum, TRTest::BinaryInstruction>>(
     std::make_tuple(TR::InstOpCode::XOR4RegReg,    TR::RealRegister::eax, TR::RealRegister::eax,    "33c0"),
     std::make_tuple(TR::InstOpCode::XOR4RegReg,    TR::RealRegister::ecx, TR::RealRegister::ebp,    "33cd"),