diff --git a/compiler/z/env/OMRCPU.cpp b/compiler/z/env/OMRCPU.cpp index 6045ec4b489..f9e7065909c 100644 --- a/compiler/z/env/OMRCPU.cpp +++ b/compiler/z/env/OMRCPU.cpp @@ -382,3 +382,55 @@ OMR::Z::CPU::isTargetWithinBranchRelativeRILRange(intptrj_t targetAddress, intpt return (targetAddress == sourceAddress + ((intptrj_t)((int32_t)((targetAddress - sourceAddress) / 2))) * 2) && (targetAddress % 2 == 0); } + +void +OMR::Z::CPU::postInitialization() + { + if (self()->isAtLeast(OMR_PROCESSOR_S390_Z10) && TR::Options::getCmdLineOptions()->getOption(TR_DisableZ10)) + self()->setProcessor(OMR_PROCESSOR_S390_FIRST); + else if (self()->isAtLeast(OMR_PROCESSOR_S390_Z196) && TR::Options::getCmdLineOptions()->getOption(TR_DisableZ196)) + self()->setProcessor(OMR_PROCESSOR_S390_Z10); + else if (self()->isAtLeast(OMR_PROCESSOR_S390_ZEC12) && TR::Options::getCmdLineOptions()->getOption(TR_DisableZEC12)) + self()->setProcessor(OMR_PROCESSOR_S390_Z196); + else if (self()->isAtLeast(OMR_PROCESSOR_S390_Z13) && TR::Options::getCmdLineOptions()->getOption(TR_DisableZ13)) + self()->setProcessor(OMR_PROCESSOR_S390_ZEC12); + else if (self()->isAtLeast(OMR_PROCESSOR_S390_Z14) && TR::Options::getCmdLineOptions()->getOption(TR_DisableZ14)) + self()->setProcessor(OMR_PROCESSOR_S390_Z13); + else if (self()->isAtLeast(OMR_PROCESSOR_S390_Z15) && TR::Options::getCmdLineOptions()->getOption(TR_DisableZ15)) + self()->setProcessor(OMR_PROCESSOR_S390_Z14); + else if (self()->isAtLeast(OMR_PROCESSOR_S390_ZNEXT) && TR::Options::getCmdLineOptions()->getOption(TR_DisableZNext)) + self()->setProcessor(OMR_PROCESSOR_S390_Z15); + + if (!self()->isAtLeast(OMR_PROCESSOR_S390_Z10)) + { + self()->disableFeature(OMR_FEATURE_S390_DFP); + } + + if (!self()->isAtLeast(OMR_PROCESSOR_S390_Z196)) + { + self()->disableFeature(OMR_FEATURE_S390_HIGH_WORD); + } + + if (!self()->isAtLeast(OMR_PROCESSOR_S390_ZEC12)) + { + self()->disableFeature(OMR_FEATURE_S390_TE); + } + + if (!self()->isAtLeast(OMR_PROCESSOR_S390_Z13)) + { + self()->disableFeature(OMR_FEATURE_S390_VECTOR_FACILITY); + } + + if (!self()->isAtLeast(OMR_PROCESSOR_S390_Z14)) + { + self()->disableFeature(OMR_FEATURE_S390_VECTOR_PACKED_DECIMAL); + } + + if (!self()->isAtLeast(OMR_PROCESSOR_S390_Z15)) + { + self()->disableFeature(OMR_FEATURE_S390_MISCELLANEOUS_INSTRUCTION_EXTENSION_3); + self()->disableFeature(OMR_FEATURE_S390_VECTOR_FACILITY_ENHANCEMENT_2); + self()->disableFeature(OMR_FEATURE_S390_VECTOR_PACKED_DECIMAL_ENHANCEMENT_FACILITY); + } + } +