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[wasm] Add WidenUpper and WidenLower SIMD intrins #80117

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Merged
merged 2 commits into from
Jan 3, 2023
Merged

[wasm] Add WidenUpper and WidenLower SIMD intrins #80117

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b5dec44
[wasm] Add WidenUpper and WidenLower SIMD intrins
radekdoulik Jan 3, 2023
85c6ffb
Fix build
radekdoulik Jan 3, 2023
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69 changes: 35 additions & 34 deletions src/mono/mono/mini/mini-llvm.c
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Original file line number Diff line number Diff line change
Expand Up @@ -7690,7 +7690,41 @@ MONO_RESTORE_WARNING
values [ins->dreg] = LLVMBuildLoad2 (builder, var_type, var, "");
break;
}

#if defined(TARGET_ARM64) || defined(TARGET_WASM)
case OP_FCVTL:
case OP_FCVTL2: {
LLVMTypeRef ret_t = simd_class_to_llvm_type (ctx, ins->klass);
gboolean high = ins->opcode == OP_FCVTL2;
LLVMValueRef result = lhs;
if (high)
result = extract_high_elements (ctx, result);
result = LLVMBuildFPExt (builder, result, ret_t, "fcvtl");
values [ins->dreg] = result;
break;
}
case OP_SSHLL:
case OP_SSHLL2:
case OP_USHLL:
case OP_USHLL2: {
LLVMTypeRef ret_t = simd_class_to_llvm_type (ctx, ins->klass);
gboolean high = FALSE;
gboolean is_unsigned = FALSE;
switch (ins->opcode) {
case OP_SSHLL2: high = TRUE; break;
case OP_USHLL2: high = TRUE; case OP_USHLL: is_unsigned = TRUE; break;
}
LLVMValueRef result = lhs;
if (high)
result = extract_high_elements (ctx, result);
if (is_unsigned)
result = LLVMBuildZExt (builder, result, ret_t, "ushll");
else
result = LLVMBuildSExt (builder, result, ret_t, "ushll");
result = LLVMBuildShl (builder, result, create_shift_vector (ctx, result, rhs), "");
values [ins->dreg] = result;
break;
}
#endif
#if defined(TARGET_X86) || defined(TARGET_AMD64) || defined(TARGET_ARM64) || defined(TARGET_WASM)
case OP_EXTRACTX_U2:
case OP_XEXTRACT_I1:
Expand Down Expand Up @@ -10074,17 +10108,6 @@ MONO_RESTORE_WARNING
values [ins->dreg] = result;
break;
}
case OP_ARM64_FCVTL:
case OP_ARM64_FCVTL2: {
LLVMTypeRef ret_t = simd_class_to_llvm_type (ctx, ins->klass);
gboolean high = ins->opcode == OP_ARM64_FCVTL2;
LLVMValueRef result = lhs;
if (high)
result = extract_high_elements (ctx, result);
result = LLVMBuildFPExt (builder, result, ret_t, "arm64_fcvtl");
values [ins->dreg] = result;
break;
}
case OP_ARM64_FCVTXN:
case OP_ARM64_FCVTXN2:
case OP_ARM64_FCVTN:
Expand Down Expand Up @@ -10772,28 +10795,6 @@ MONO_RESTORE_WARNING
values [ins->dreg] = result;
break;
}
case OP_ARM64_SSHLL:
case OP_ARM64_SSHLL2:
case OP_ARM64_USHLL:
case OP_ARM64_USHLL2: {
LLVMTypeRef ret_t = simd_class_to_llvm_type (ctx, ins->klass);
gboolean high = FALSE;
gboolean is_unsigned = FALSE;
switch (ins->opcode) {
case OP_ARM64_SSHLL2: high = TRUE; break;
case OP_ARM64_USHLL2: high = TRUE; case OP_ARM64_USHLL: is_unsigned = TRUE; break;
}
LLVMValueRef result = lhs;
if (high)
result = extract_high_elements (ctx, result);
if (is_unsigned)
result = LLVMBuildZExt (builder, result, ret_t, "arm64_ushll");
else
result = LLVMBuildSExt (builder, result, ret_t, "arm64_ushll");
result = LLVMBuildShl (builder, result, create_shift_vector (ctx, result, rhs), "");
values [ins->dreg] = result;
break;
}
case OP_ARM64_SLI:
case OP_ARM64_SRI: {
LLVMTypeRef intrin_result_t = simd_class_to_llvm_type (ctx, ins->klass);
Expand Down
15 changes: 7 additions & 8 deletions src/mono/mono/mini/mini-ops.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1614,11 +1614,6 @@ MINI_OP(OP_ARM64_USHR, "arm64_ushr", XREG, XREG, IREG)
MINI_OP3(OP_ARM64_USRA, "arm64_usra", XREG, XREG, XREG, IREG)
MINI_OP3(OP_ARM64_SSRA, "arm64_ssra", XREG, XREG, XREG, IREG)

MINI_OP(OP_ARM64_USHLL, "arm64_ushll", XREG, XREG, IREG)
MINI_OP(OP_ARM64_USHLL2, "arm64_ushll2", XREG, XREG, IREG)
MINI_OP(OP_ARM64_SSHLL, "arm64_sshll", XREG, XREG, IREG)
MINI_OP(OP_ARM64_SSHLL2, "arm64_sshll2", XREG, XREG, IREG)

/* Narrowing arm64 shifts that aren't decomposed into urshl or srshl. */
MINI_OP(OP_ARM64_XNSHIFT_SCALAR, "arm64_xrshift_scalar", XREG, XREG, IREG)
MINI_OP(OP_ARM64_XNSHIFT, "arm64_xnshift", XREG, XREG, IREG)
Expand Down Expand Up @@ -1706,9 +1701,6 @@ MINI_OP(OP_ARM64_FCVTN2, "arm64_fcvtn2", XREG, XREG, XREG)
MINI_OP(OP_ARM64_FCVTXN, "arm64_fcvtxn", XREG, XREG, NONE)
MINI_OP(OP_ARM64_FCVTXN2, "arm64_fcvtxn2", XREG, XREG, XREG)

MINI_OP(OP_ARM64_FCVTL, "arm64_fcvtl", XREG, XREG, NONE)
MINI_OP(OP_ARM64_FCVTL2, "arm64_fcvtl2", XREG, XREG, NONE)

MINI_OP(OP_ARM64_CMTST, "arm64_cmtst", XREG, XREG, XREG)

MINI_OP(OP_ARM64_BIC, "arm64_bic", XREG, XREG, XREG)
Expand Down Expand Up @@ -1763,6 +1755,13 @@ MINI_OP3(OP_ARM64_SQRDMLSH_SCALAR, "arm64_sqrdmlsh_scalar", XREG, XREG, XREG, XR

#endif // TARGET_ARM64

MINI_OP(OP_FCVTL, "convert_to_higher_precision", XREG, XREG, NONE)
MINI_OP(OP_FCVTL2, "convert_to_higher_precision_2", XREG, XREG, NONE)
MINI_OP(OP_USHLL, "unsigned_shift_left_long", XREG, XREG, IREG)
MINI_OP(OP_USHLL2, "unsigned_shift_left_long_2", XREG, XREG, IREG)
MINI_OP(OP_SSHLL, "signed_shift_left_long", XREG, XREG, IREG)
MINI_OP(OP_SSHLL2, "signed_shift_left_long_2", XREG, XREG, IREG)

#if defined(TARGET_WASM)
MINI_OP(OP_WASM_ONESCOMPLEMENT, "wasm_onescomplement", XREG, XREG, NONE)
#endif
Expand Down
15 changes: 7 additions & 8 deletions src/mono/mono/mini/simd-intrinsics.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1682,19 +1682,18 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi
}
case SN_WidenLower:
case SN_WidenUpper: {
#ifdef TARGET_ARM64
#if defined(TARGET_ARM64) || defined(TARGET_WASM)
if (!is_element_type_primitive (fsig->params [0]))
return NULL;

int op = id == SN_WidenLower ? OP_XLOWER : OP_XUPPER;
MonoInst *lower_or_upper_half = emit_simd_ins_for_sig (cfg, klass, op, 0, arg0_type, fsig, args);

if (type_enum_is_float (arg0_type)) {
return emit_simd_ins (cfg, klass, OP_ARM64_FCVTL, lower_or_upper_half->dreg, -1);
return emit_simd_ins (cfg, klass, OP_FCVTL, lower_or_upper_half->dreg, -1);
} else {
int zero = alloc_ireg (cfg);
MONO_EMIT_NEW_ICONST (cfg, zero, 0);
op = type_enum_is_unsigned (arg0_type) ? OP_ARM64_USHLL : OP_ARM64_SSHLL;
op = type_enum_is_unsigned (arg0_type) ? OP_USHLL : OP_SSHLL;
return emit_simd_ins (cfg, klass, op, lower_or_upper_half->dreg, zero);
}
#else
Expand Down Expand Up @@ -2563,9 +2562,9 @@ static SimdIntrinsic advsimd_methods [] = {
{SN_CompareLessThanScalar, OP_XCOMPARE_SCALAR, CMP_LT, OP_XCOMPARE_SCALAR, CMP_LT_UN, OP_XCOMPARE_FP_SCALAR, CMP_LT},
{SN_CompareTest, OP_ARM64_CMTST},
{SN_CompareTestScalar, OP_ARM64_CMTST},
{SN_ConvertToDouble, OP_CVT_SI_FP, None, OP_CVT_UI_FP, None, OP_ARM64_FCVTL},
{SN_ConvertToDouble, OP_CVT_SI_FP, None, OP_CVT_UI_FP, None, OP_FCVTL},
{SN_ConvertToDoubleScalar, OP_CVT_SI_FP_SCALAR, None, OP_CVT_UI_FP_SCALAR},
{SN_ConvertToDoubleUpper, OP_ARM64_FCVTL2},
{SN_ConvertToDoubleUpper, OP_FCVTL2},
{SN_ConvertToInt32RoundAwayFromZero, OP_XOP_OVR_X_X, INTRINS_AARCH64_ADV_SIMD_FCVTAS},
{SN_ConvertToInt32RoundAwayFromZeroScalar, OP_XOP_OVR_SCALAR_X_X, INTRINS_AARCH64_ADV_SIMD_FCVTAS},
{SN_ConvertToInt32RoundToEven, OP_XOP_OVR_X_X, INTRINS_AARCH64_ADV_SIMD_FCVTNS},
Expand Down Expand Up @@ -2803,8 +2802,8 @@ static SimdIntrinsic advsimd_methods [] = {
{SN_ShiftLeftLogicalSaturateUnsigned, OP_ARM64_SQSHLU},
{SN_ShiftLeftLogicalSaturateUnsignedScalar, OP_ARM64_SQSHLU_SCALAR},
{SN_ShiftLeftLogicalScalar, OP_ARM64_SHL},
{SN_ShiftLeftLogicalWideningLower, OP_ARM64_SSHLL, None, OP_ARM64_USHLL},
{SN_ShiftLeftLogicalWideningUpper, OP_ARM64_SSHLL2, None, OP_ARM64_USHLL2},
{SN_ShiftLeftLogicalWideningLower, OP_SSHLL, None, OP_USHLL},
{SN_ShiftLeftLogicalWideningUpper, OP_SSHLL2, None, OP_USHLL2},
{SN_ShiftLogical, OP_XOP_OVR_X_X_X, INTRINS_AARCH64_ADV_SIMD_USHL},
{SN_ShiftLogicalRounded, OP_XOP_OVR_X_X_X, INTRINS_AARCH64_ADV_SIMD_URSHL},
{SN_ShiftLogicalRoundedSaturate, OP_XOP_OVR_X_X_X, INTRINS_AARCH64_ADV_SIMD_UQRSHL},
Expand Down