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Arm64/Sve: Handle ConvertTo* APIs properly #103876

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merged 4 commits into from
Jun 24, 2024
Merged

Arm64/Sve: Handle ConvertTo* APIs properly #103876

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f1a02da
Handle ConvertTo* APIs properly
kunalspathak Jun 24, 2024
e594696
add missing default
kunalspathak Jun 24, 2024
96bd1c9
Update src/coreclr/jit/lowerarmarch.cpp
kunalspathak Jun 24, 2024
2d7e1ee
Update src/coreclr/jit/lowerarmarch.cpp
kunalspathak Jun 24, 2024
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12 changes: 12 additions & 0 deletions src/coreclr/jit/hwintrinsic.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1477,6 +1477,18 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
break;
}
}
#elif defined(TARGET_ARM64)
switch (intrinsic)
{
case NI_Sve_ConvertToInt32:
case NI_Sve_ConvertToUInt32:
// Save the base type of return SIMD. It is used to contain this intrinsic inside
// ConditionalSelect.
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sig->retTypeSigClass));
break;
default:
break;
}
#endif // TARGET_XARCH

break;
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14 changes: 14 additions & 0 deletions src/coreclr/jit/hwintrinsiccodegenarm64.cpp
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Expand Up @@ -490,6 +490,20 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
{
assert(!instrIsRMW);

// Special handling for ConvertTo* APIs
// Just need to change the opt here.
switch (intrinEmbMask.id)
{
case NI_Sve_ConvertToInt32:
case NI_Sve_ConvertToUInt32:
{
opt = intrinEmbMask.baseType == TYP_DOUBLE ? INS_OPTS_D_TO_S : INS_OPTS_SCALABLE_S;
break;
}
default:
break;
}

if (targetReg != falseReg)
{
// If targetReg is not the same as `falseReg` then need to move
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35 changes: 28 additions & 7 deletions src/coreclr/jit/lowerarmarch.cpp
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Expand Up @@ -3347,14 +3347,35 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
// Handle op2
if (op2->OperIsHWIntrinsic())
{
uint32_t maskSize = genTypeSize(node->GetSimdBaseType());
uint32_t operSize = genTypeSize(op2->AsHWIntrinsic()->GetSimdBaseType());

if ((maskSize == operSize) && IsInvariantInRange(op2, node) &&
op2->isEmbeddedMaskingCompatibleHWIntrinsic())
if (IsInvariantInRange(op2, node) && op2->isEmbeddedMaskingCompatibleHWIntrinsic())
{
MakeSrcContained(node, op2);
op2->MakeEmbMaskOp();
uint32_t maskSize = genTypeSize(node->GetSimdBaseType());
uint32_t operSize = genTypeSize(op2->AsHWIntrinsic()->GetSimdBaseType());
if (maskSize == operSize)
{
// If the size of baseType of operation matches that of maskType, then contain
// the operation
MakeSrcContained(node, op2);
op2->MakeEmbMaskOp();
}
else
{
// Else check if this operation has an auxiliary type that matches the
// mask size.
GenTreeHWIntrinsic* embOp = op2->AsHWIntrinsic();

// For now, make sure that we get here only for intrinsics that we are
// sure about to rely on auxiliary type's size.
assert((embOp->GetHWIntrinsicId() == NI_Sve_ConvertToInt32) ||
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Do you intend for this assert to go away once @ebepho implements ConvertToInt64, or should we keep checking for intrinsics with different base/return types? If the latter, I wonder if we ought to add a flag for these types of intrinsics.

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For now, we will update the assert, but may be later, we might consider adding a flag. For now, I want to see if there are more intrinsic categories that falls under this.

(embOp->GetHWIntrinsicId() == NI_Sve_ConvertToUInt32));

uint32_t auxSize = genTypeSize(embOp->GetAuxiliaryType());
if (maskSize == auxSize)
{
MakeSrcContained(node, op2);
op2->MakeEmbMaskOp();
}
}
}
}

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