Description
Issue #35730 describes an Intel architecture erratum related to JCC instructions and the performance impact of the microcode mitigation that was implemented.
The performance impact causes seemingly random and significant regressions, due to code and instruction alignment, especially in micro-benchmarks, that can make analyzing the performance impact of JIT and other changes difficult and frustrating.
This issue is to implement a mode in the JIT to avoid the JCC erratum by altering generated code to avoid triggering the erratum condition. This will likely involve strategic insertion of NOP instructions. This mode will primarily be useful to aid developers analyzing the performance impact of JIT (and other) changes. Based on code size regressions and other performance characteristics of the mode, we can consider it for permanent enabling on affected platforms.