Assertion failed '((emitThisGCrefRegs | emitThisByrefRegs) & regMask) && (ins == INS_inc || ins == INS_dec || ins == INS_inc_l || ins == INS_dec_l)'

[BruceForstall]

Failure in runtime-coreclr libraries-jitstress pipeline, System.IO.Hashing.Tests, x86/x64, multiple stress modes:

https://dev.azure.com/dnceng/public/_build/results?buildId=1180694&view=ms.vss-test-web.build-test-results-tab&runId=35530936&resultId=178029&paneView=dotnet-dnceng.dnceng-build-release-tasks.helix-test-information-tab

----- start Thu Jun 10 08:11:49 UTC 2021 =============== To repro directly: =====================================================
pushd .
/datadisks/disk1/work/9E8D08E8/p/dotnet exec --runtimeconfig System.IO.Hashing.Tests.runtimeconfig.json --depsfile System.IO.Hashing.Tests.deps.json xunit.console.dll System.IO.Hashing.Tests.dll -xml testResults.xml -nologo -nocolor -notrait category=IgnoreForCI -notrait category=OuterLoop -notrait category=failing 
popd
===========================================================================================================
/datadisks/disk1/work/9E8D08E8/w/B45109C0/e /datadisks/disk1/work/9E8D08E8/w/B45109C0/e
  Discovering: System.IO.Hashing.Tests (method display = ClassAndMethod, method display options = None)
  Discovered:  System.IO.Hashing.Tests (found 153 test cases)
  Starting:    System.IO.Hashing.Tests (parallel test collections = on, max threads = 2)

Assert failure(PID 25624 [0x00006418], Thread: 25638 [0x6426]): Assertion failed '((emitThisGCrefRegs | emitThisByrefRegs) & regMask) && (ins == INS_inc || ins == INS_dec || ins == INS_inc_l || ins == INS_dec_l)' in 'System.IO.Hashing.Tests.NonCryptoHashTestDriver:InstanceMultiAppendGetCurrentHashDriver(TestCase):this' during 'Emit code' (IL size 172)

    File: /__w/1/s/src/coreclr/jit/emitxarch.cpp Line: 11749
    Image: /datadisks/disk1/work/9E8D08E8/p/dotnet

Gathering state for process 25624 dotnet
Writing minidump with heap to file /home/helixbot/dotnetbuild/dumps/coredump.25624.dmp
Written 134455296 bytes (32826 pages) to core file
Dump successfully written
./RunTests.sh: line 162: 25624 Aborted                 (core dumped) "$RUNTIME_PATH/dotnet" exec --runtimeconfig System.IO.Hashing.Tests.runtimeconfig.json --depsfile System.IO.Hashing.Tests.deps.json xunit.console.dll System.IO.Hashing.Tests.dll -xml testResults.xml -nologo -nocolor -notrait category=IgnoreForCI -notrait category=OuterLoop -notrait category=failing $RSP_FILE
/datadisks/disk1/work/9E8D08E8/w/B45109C0/e
----- end Thu Jun 10 08:11:57 UTC 2021 ----- exit code 134 ----------------------------------------------------------

@dotnet/jit-contrib

[tannergooding]

I wonder if this is similar to #10821 and #51728

The APIs here are making decently heavy use of Span<T> and this is a similar assert that an operation that is expected on a byref isn't on a byref.

[BruceForstall]

This is new code, as of #53623.

cc @bartonjs The new test tickles some JIT bug under optimization.

[BruceForstall]

@tannergooding It looks like you're right. The stackalloc creates a long, then there's a silly amount of var=var that is byref, followed by add:

N565 (  2,  5) [000064] ---X---N----        t64 = *  LCLHEAP   long   REG rdi $484
                                                  /--*  t64    long
N567 (  2,  5) [000567] DA-X--------              *  STORE_LCL_VAR long   V50 tmp40        d:2 rdi REG rdi
N569 (???,???) [002056] ------------                 IL_OFFSET void   IL offset: 0x4f REG NA
N571 (  1,  1) [000572] ------------       t572 =    LCL_VAR   byref  V50 tmp40        u:2 rdi (last use) REG rdi $484
                                                  /--*  t572   byref
N573 (  5,  4) [000551] DA----------              *  STORE_LCL_VAR byref  V158 tmp148      d:2 rdi REG rdi
N575 (???,???) [002057] ------------                 IL_OFFSET void   IL offset: 0x4f REG NA
N577 (  3,  2) [001609] -------N----      t1609 =    LCL_VAR   byref  V158 tmp148      u:2 rdi (last use) REG rdi $484
                                                  /--*  t1609  byref
N579 (  7,  5) [001610] DA----------              *  STORE_LCL_VAR byref  V139 tmp129      d:2 rdi REG rdi
N581 (???,???) [002058] ------------                 IL_OFFSET void   IL offset: 0x4f REG NA
N583 (???,???) [002059] ------------                 IL_OFFSET void   IL offset: 0x61 REG NA
N585 (  3,  2) [001612] ------------      t1612 =    LCL_VAR   byref  V139 tmp129      u:2 rdi (last use) REG rdi $484
                                                  /--*  t1612  byref
N587 (  7,  5) [001613] DA----------              *  STORE_LCL_VAR byref  V133 tmp123      d:2 rdi REG rdi
N589 (???,???) [002060] ------------                 IL_OFFSET void   IL offset: 0x63 REG NA
N591 (  3,  2) [001619] ------------      t1619 =    LCL_VAR   byref  V133 tmp123      u:2 rdi (last use) REG rdi $484
                                                  /--*  t1619  byref
N593 (  7,  5) [001620] DA----------              *  STORE_LCL_VAR byref  V127 tmp117      d:2 rdi REG rdi
N595 (???,???) [002061] ------------                 IL_OFFSET void   IL offset: 0x66 REG NA
N597 (  3,  2) [000582] ------------       t582 =    LCL_VAR   byref  V127 tmp117      u:2 rdi (last use) REG rdi $484
                                                  /--*  t582   byref
N599 (  3,  3) [000613] DA--G-------              *  STORE_LCL_VAR byref  V53 tmp43        d:2 rdi REG rdi
N601 (???,???) [002062] ------------                 IL_OFFSET void   IL offset: 0x66 REG NA
N603 (???,???) [002063] ------------                 IL_OFFSET void   IL offset: 0x66 REG NA
N605 (  1,  4) [001982] -c----------      t1982 =    CNS_INT   int    255 REG NA $5a
                                                  /--*  t1982  int
N607 (  1,  4) [000640] DA----------              *  STORE_LCL_VAR int    V54 tmp44        d:2 rcx REG rcx
N609 (???,???) [002064] ------------                 IL_OFFSET void   IL offset: 0x66 REG NA
N611 (???,???) [002065] ------------                 IL_OFFSET void   IL offset: 0x66 REG NA
N613 (???,???) [002066] ------------                 IL_OFFSET void   IL offset: 0x66 REG NA
N615 (???,???) [002067] ------------                 IL_OFFSET void   IL offset: 0x66 REG NA
N617 (  1,  1) [000610] ------------       t610 =    LCL_VAR   byref  V53 tmp43        u:2 rdi (last use) REG rdi $484
N619 (  1,  1) [000609] -c----------       t609 =    CNS_INT   long   1 REG NA $104
                                                  /--*  t610   byref
                                                  +--*  t609   long
N621 (  3,  3) [000611] ------------       t611 = *  ADD       byref  REG rdi $187

[BruceForstall]

@tannergooding @bartonjs Can we disable the appropriate tests under Checked runtime / JIT stress modes? How do we do that?

[tannergooding]

I'm not aware of how to disable a libraries test for a given CI leg (such as JIT stress). @ViktorHofer do we have this capability today?

[BruceForstall]

Well, I tried using:

[SkipOnCoreClr("https://github.com/dotnet/runtime/issues/54007", RuntimeConfiguration.Checked)]

but couldn't get it to work.

Maybe @safern has a suggestion?

[safern]

[SkipOnCoreClr("https://github.com//issues/54007", RuntimeConfiguration.Checked)]

That should've worked. The logic is pretty "simple" to skip on that case: https://github.com/dotnet/arcade/blob/398bdff17042af6ae8131a661860b13ef247ecff/src/Microsoft.DotNet.XUnitExtensions/src/Discoverers/SkipOnCoreClrDiscoverer.cs#L50

Let me know if you can't get it to work and I can see what's going on with the discoverer.

[BruceForstall]

@tannergooding I presume this issue will get fixed with your #53684? (Assuming you fix that PR and get it back in.)

[tannergooding]

I presume this issue will get fixed with your #53684? (Assuming you fix that PR and get it back in.)

@BruceForstall It should. However, there is more testing and work I have to do to determine "why" my fix isn't "complete" (and since I'm largely only working on it in my spare time, I'm not sure when I'll get it finalized).

As is, it looks like the change might be more complicated because eliding no moves (that is preserving every "redundant" move and just emitting the assembly for it) looks to cause problems, which leads me to believe there are some more complicated liveness issues here and that might be what's causing my original PR to fail under certain stress environments.