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Problems with LSRA's resolution phase #47194

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@kunalspathak

Description

@kunalspathak

Problem statement

This issue captures various problems with existing resolution phase of register allocator.

While doing some other investigation, I noticed a scenario where we create new BB during resolution phase, but the compensation code inside them is identical.

; ...
       je       SHORT G_M59092_IG32
       cmp      edx, 1
       je       SHORT G_M59092_IG32
       mov      gword ptr [rbp-100H], r13
       jmp      G_M59092_IG42
						;; bbWeight=2    PerfScore 25.50
G_M59092_IG29:
       mov      gword ptr [rbp-100H], r13
       jmp      G_M59092_IG42
						;; bbWeight=1    PerfScore 3.00
G_M59092_IG30:
       mov      gword ptr [rbp-100H], r13
       jmp      G_M59092_IG42
						;; bbWeight=1    PerfScore 3.00
; ...
; ...
G_M59092_IG45:
       mov      gword ptr [rbp-100H], r13
       jmp      SHORT G_M59092_IG42
						;; bbWeight=1    PerfScore 3.00
G_M59092_IG46:
       mov      gword ptr [rbp-100H], r13
       jmp      SHORT G_M59092_IG42
						;; bbWeight=1    PerfScore 3.00
G_M59092_IG47:
       mov      gword ptr [rbp-100H], r13
       jmp      SHORT G_M59092_IG42
						;; bbWeight=1    PerfScore 3.00
; ...

Investigate if we could come with single basic block in such case that has the required code and all other jump to that block. As an effect, this increases the PerfScore from 3.00 to 24.00 triggering regression while doing asmdiffs.

category:design
theme:register-allocator
skill-level:expert
cost:large
impact:medium

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area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

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