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[RISC-V] Utilize SH(X)ADD instruction for GT_INDEX_ADDR
1 parent 8700d89 commit f8907d2

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2 files changed

+13
-3
lines changed

2 files changed

+13
-3
lines changed

src/coreclr/jit/codegen.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -866,7 +866,8 @@ class CodeGen final : public CodeGenInterface
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#endif // TARGET_ARMARCH || TARGET_LOONGARCH64 || TARGET_RISCV64
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#if defined(TARGET_RISCV64)
869-
void genShxaddInstruction(GenTreeShxadd *shxadd);
869+
void genShxaddInstruction(GenTreeShxadd* shxadd);
870+
instruction getShxaddVariant(int scale, bool useUnsignedVariant);
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#endif
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872873
#if defined(TARGET_ARMARCH)

src/coreclr/jit/codegenriscv64.cpp

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5531,7 +5531,16 @@ void CodeGen::genCodeForIndexAddr(GenTreeIndexAddr* node)
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// dest = base + (index << scale)
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if (node->gtElemSize <= 64)
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{
5534-
genScaledAdd(attr, node->GetRegNum(), base->GetRegNum(), index->GetRegNum(), scale, tempReg);
5534+
instruction shxaddIns = getShxaddVariant(scale, (genTypeSize(index) == 4));
5535+
5536+
if (shxaddIns != INS_none)
5537+
{
5538+
GetEmitter()->emitIns_R_R_R(shxaddIns, attr, node->GetRegNum(), index->GetRegNum(), base->GetRegNum());
5539+
}
5540+
else
5541+
{
5542+
genScaledAdd(attr, node->GetRegNum(), base->GetRegNum(), index->GetRegNum(), scale, tempReg);
5543+
}
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}
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else
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{
@@ -6641,7 +6650,7 @@ void CodeGen::genLeaInstruction(GenTreeAddrMode* lea)
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genProduceReg(lea);
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}
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6644-
instruction getShxaddVariant(int scale, bool useUnsignedVariant)
6653+
instruction CodeGen::getShxaddVariant(int scale, bool useUnsignedVariant)
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{
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if (useUnsignedVariant)
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{

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