JIT: Slightly refactor handling of conditions/conditional branches in the backend (#82020)

Slightly refactor how compares are represented and processed in the backend in
preparation of lifting the remaining cmov restrictions.

- Change all compare nodes to always produce values and never set flags. That
  is, GT_EQ/GT_NE/GT_LT/GT_LE/GT_GE/GT_GT/GT_TEST_EQ/GT_TEST_NE now are all
  "normal" nodes, always.

- Stop optimizing compares by looking for a user JTRUE node. Instead, we
  optimize the compare when we see it (for example, EQ/NE(AND(x, y), 0) is
  turned into GT_TEST_EQ/GT_TEST_NE(x, y)), but we do not change the user JTRUE
  node to a JCC node. We now never create SETCC nodes when we see the compare,
  and we always turn JTRUE nodes into JCC nodes with a proper condition.

- Handle the transformation from JTRUE to JCC when we actually get to JTRUE. The
  transformation that now happens is:

  1. The compare node is turned into a GT_CMP (for GT_EQ to GT_GT) or GT_TEST
  node (for GT_TEST_EQ/GT_TEST_NE) node. These nodes are always void-typed and
  do not produce values; they only set the CPU flags, and correspond directly to
  low-level target instructions (like cmp/test).

  2. The JTRUE is turned into JCC with the condition from the compare.

  For arm64/xarch, we handle optimizing EQ/NE(node_that_sets_zero_flag, 0) at
  this stage too now.

- Introduce new xarch backend-only GT_BITTEST_EQ/GT_BITTEST_NE that semantically
  correspond to (x & (1 << y)) != 0. The corresponding "set flags" node is GT_BT
  and already exists. We would previously transform (x & (1 << y)) != 0 into
  GT_BT + GT_SETCC (when the user was not a JTRUE). This is now transformed into
  GT_BITTEST_EQ/GT_BITTEST_NE instead, which are completely normal nodes. The
  processing of JTRUE handles the transformation into BT + JCC.

- Change some of the emitter compare peepholes to work with this scheme. This
  requires some lookahead when we see them, but allows us to get rid of an
  "ugly" flag.

- Allow liveness to DCE GT_CMP/GT_TEST when they have had GTF_SET_FLAGS unset
  (due to FG optimizations). We already allowed this for GT_EQ, so this showed
  up as some regressions.

Some example LIR diffs:

```diff
  Generating: N033 (???,???) [000136] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-] REG NA
  Generating: N035 (  1,  1) [000009] -----------                    t9 =    LCL_VAR   int    V02 loc1         u:1 ecx REG ecx $141
  Generating: N037 (  1,  1) [000011] -c---------                   t11 =    CNS_INT   int    16 REG NA $42
                                                                          ┌──▌  t9     int    
                                                                          ├──▌  t11    int    
- Generating: N039 (  3,  3) [000012] N------N-U-                         ▌  GE        void   REG NA $142
+ Generating: N039 (  3,  3) [000012] -------N-U-                         ▌  CMP       void   REG NA
  IN0005:        cmp      ecx, 16
- Generating: N041 (  5,  5) [000013] -----------                         ▌  JTRUE     void   REG NA $VN.Void
+ Generating: N041 (???,???) [000144] -----------                            JCC       void   cond=UGE REG NA
  IN0006:        jae      L_M20112_BB03
                                                                          ┌──▌  t112   ubyte  
                                                                          ├──▌  t54    int    
- Generating: N061 ( 22, 14) [000060] ---XGO-----                         ▌  BT        void   REG NA
+ Generating: N061 ( 22, 14) [000060] ---XGO-----                   t60 = ▌  BITTEST_NE int    REG eax
  IN0009:        bt       eax, esi
- Generating: N063 (???,???) [000144] -----------                  t144 =    SETCC     int    cond=C REG eax
  IN000a:        setb     al
  IN000b:        movzx    eax, al
-                                                                         ┌──▌  t144   int    
+                                                                         ┌──▌  t60   int    
  Generating: N065 ( 23, 15) [000061] ---XGO-----                         ▌  RETURN    int    REG NA <l:$1c8, c:$1c7>
```

Author: jakobbotsch

src/coreclr/jit/codegen.h

@@ -902,6 +902,10 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 
     void genCompareFloat(GenTree* treeNode);
     void genCompareInt(GenTree* treeNode);
+#ifdef TARGET_XARCH
+    bool genCanAvoidEmittingCompareAgainstZero(GenTree* tree, var_types opType);
+    GenTreeCC* genTryFindFlagsConsumer(GenTree* flagsProducer);
+#endif
 
 #ifdef FEATURE_SIMD
 #ifdef TARGET_ARM64
@@ -1077,7 +1081,6 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 
 #ifdef TARGET_XARCH
     void genCodeForShiftRMW(GenTreeStoreInd* storeInd);
-    void genCodeForBT(GenTreeOp* bt);
 #endif // TARGET_XARCH
 
     void genCodeForCast(GenTreeOp* tree);
@@ -1192,7 +1195,6 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     void genCallInstruction(GenTreeCall* call X86_ARG(target_ssize_t stackArgBytes));
     void genJmpMethod(GenTree* jmp);
     BasicBlock* genCallFinally(BasicBlock* block);
-    void genCodeForJumpTrue(GenTreeOp* jtrue);
 #if defined(TARGET_LOONGARCH64)
     // TODO: refactor for LA.
     void genCodeForJumpCompare(GenTreeOp* tree);

src/coreclr/jit/codegenarm.cpp

@@ -1257,13 +1257,9 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree)
     regNumber targetReg = tree->GetRegNum();
     emitter*  emit      = GetEmitter();
 
-    genConsumeIfReg(op1);
-    genConsumeIfReg(op2);
-
     if (varTypeIsFloating(op1Type))
     {
         assert(op1Type == op2Type);
-        assert(!tree->OperIs(GT_CMP));
         emit->emitInsBinary(INS_vcmp, emitTypeSize(op1Type), op1, op2);
         // vmrs with register 0xf has special meaning of transferring flags
         emit->emitIns_R(INS_vmrs, EA_4BYTE, REG_R15);

src/coreclr/jit/codegenarm64.cpp

@@ -4578,7 +4578,7 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree)
         // We don't support swapping op1 and op2 to generate cmp reg, imm
         assert(!op1->isContainedIntOrIImmed());
 
-        instruction ins = tree->OperIs(GT_TEST_EQ, GT_TEST_NE) ? INS_tst : INS_cmp;
+        instruction ins = tree->OperIs(GT_TEST_EQ, GT_TEST_NE, GT_TEST) ? INS_tst : INS_cmp;
 
         if (op2->isContainedIntOrIImmed())
         {

src/coreclr/jit/codegenarmarch.cpp

@@ -349,16 +349,11 @@ void CodeGen::genCodeForTreeNode(GenTree* treeNode)
         case GT_LE:
         case GT_GE:
         case GT_GT:
-        case GT_CMP:
-#ifdef TARGET_ARM64
-        case GT_TEST_EQ:
         case GT_TEST_NE:
-            // On ARM64 genCodeForCompare does not consume its own operands because
-            // genCodeForBinary also has this behavior and it can end up calling
-            // genCodeForCompare when generating compare chains for GT_AND.
-            // Thus, we must do it here.
+        case GT_TEST_EQ:
+        case GT_CMP:
+        case GT_TEST:
             genConsumeOperands(treeNode->AsOp());
-#endif // TARGET_ARM64
             genCodeForCompare(treeNode->AsOp());
             break;
 
@@ -368,10 +363,6 @@ void CodeGen::genCodeForTreeNode(GenTree* treeNode)
             break;
 #endif
 
-        case GT_JTRUE:
-            genCodeForJumpTrue(treeNode->AsOp());
-            break;
-
 #ifdef TARGET_ARM64
         case GT_JCMP:
             genCodeForJumpCompare(treeNode->AsOp());

src/coreclr/jit/codegenlinear.cpp

@@ -2588,51 +2588,6 @@ void CodeGen::genStoreLongLclVar(GenTree* treeNode)
 #endif // !defined(TARGET_64BIT)
 
 #ifndef TARGET_LOONGARCH64
-//------------------------------------------------------------------------
-// genCodeForJumpTrue: Generate code for a GT_JTRUE node.
-//
-// Arguments:
-//    jtrue - The node
-//
-void CodeGen::genCodeForJumpTrue(GenTreeOp* jtrue)
-{
-    assert(compiler->compCurBB->bbJumpKind == BBJ_COND);
-    assert(jtrue->OperIs(GT_JTRUE));
-
-    GenTreeOp*   relop     = jtrue->gtGetOp1()->AsOp();
-    GenCondition condition = GenCondition::FromRelop(relop);
-
-    if (condition.PreferSwap())
-    {
-        condition = GenCondition::Swap(condition);
-    }
-
-#if defined(TARGET_XARCH)
-    if ((condition.GetCode() == GenCondition::FNEU) &&
-        (relop->gtGetOp1()->GetRegNum() == relop->gtGetOp2()->GetRegNum()) &&
-        !relop->gtGetOp1()->isUsedFromSpillTemp() && !relop->gtGetOp2()->isUsedFromSpillTemp())
-    {
-        // For floating point, `x != x` is a common way of
-        // checking for NaN. So, in the case where both
-        // operands are the same, we can optimize codegen
-        // to only do a single check.
-
-        condition = GenCondition(GenCondition::P);
-    }
-
-    if (relop->MarkedForSignJumpOpt())
-    {
-        // If relop was previously marked for a signed jump check optimization because of SF flag
-        // reuse, replace jge/jl with jns/js.
-
-        assert(relop->OperGet() == GT_LT || relop->OperGet() == GT_GE);
-        condition = (relop->OperGet() == GT_LT) ? GenCondition(GenCondition::S) : GenCondition(GenCondition::NS);
-    }
-
-#endif
-
-    inst_JCC(condition, compiler->compCurBB->bbJumpDest);
-}
 
 //------------------------------------------------------------------------
 // genCodeForJcc: Generate code for a GT_JCC node.