Skip to content

Commit eb655cf

Browse files
a74nha74nh
authored
ARM64-SVE: Always call emitIns_Mov when canskip is true (#106693)
1 parent 779baa6 commit eb655cf

File tree

1 file changed

+57
-133
lines changed

1 file changed

+57
-133
lines changed

‎src/coreclr/jit/hwintrinsiccodegenarm64.cpp‎

Lines changed: 57 additions & 133 deletions
Original file line numberDiff line numberDiff line change
@@ -368,13 +368,9 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
368368
{
369369
if (isRMW)
370370
{
371-
if (targetReg != op1Reg)
372-
{
373-
assert(targetReg != op2Reg);
374-
assert(targetReg != op3Reg);
375-
376-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
377-
}
371+
assert((targetReg == op1Reg) || (targetReg != op2Reg));
372+
assert((targetReg == op1Reg) || (targetReg != op3Reg));
373+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
378374

379375
HWIntrinsicImmOpHelper helper(this, intrin.op4, node);
380376

@@ -416,14 +412,9 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
416412
{
417413
if (isRMW)
418414
{
419-
if (targetReg != op1Reg)
420-
{
421-
assert(targetReg != op2Reg);
422-
assert(targetReg != op3Reg);
423-
424-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
425-
}
426-
415+
assert((targetReg == op1Reg) || (targetReg != op2Reg));
416+
assert((targetReg == op1Reg) || (targetReg != op3Reg));
417+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
427418
GetEmitter()->emitIns_R_R_R_I(ins, emitSize, targetReg, op2Reg, op3Reg, 0, opt);
428419
}
429420
else
@@ -773,21 +764,16 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
773764
switch (intrinEmbMask.id)
774765
{
775766
case NI_Sve_CreateBreakPropagateMask:
776-
if (targetReg != embMaskOp1Reg)
777-
{
778-
GetEmitter()->emitIns_Mov(INS_sve_mov, emitSize, targetReg, embMaskOp2Reg,
779-
/* canSkip */ true);
780-
}
767+
assert((targetReg == embMaskOp2Reg) || (targetReg != embMaskOp1Reg));
768+
GetEmitter()->emitIns_Mov(INS_sve_mov, emitSize, targetReg, embMaskOp2Reg,
769+
/* canSkip */ true);
781770
emitInsHelper(targetReg, maskReg, embMaskOp1Reg);
782771
break;
783772

784773
case NI_Sve_AddSequentialAcross:
785-
assert(targetReg != embMaskOp2Reg);
786-
if (targetReg != embMaskOp1Reg)
787-
{
788-
GetEmitter()->emitIns_Mov(INS_fmov, GetEmitter()->optGetSveElemsize(embOpt),
789-
targetReg, embMaskOp1Reg, /* canSkip */ true);
790-
}
774+
assert((targetReg == op1Reg) || (targetReg != embMaskOp2Reg));
775+
GetEmitter()->emitIns_Mov(INS_fmov, GetEmitter()->optGetSveElemsize(embOpt), targetReg,
776+
embMaskOp1Reg, /* canSkip */ true);
791777
emitInsHelper(targetReg, maskReg, embMaskOp2Reg);
792778
break;
793779

@@ -1063,15 +1049,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
10631049
{
10641050
if (isRMW)
10651051
{
1066-
if (targetReg != op2Reg)
1067-
{
1068-
assert(targetReg != op1Reg);
1069-
1070-
GetEmitter()->emitIns_Mov(ins_Move_Extend(intrin.op2->TypeGet(), false),
1071-
emitTypeSize(node), targetReg, op2Reg,
1072-
/* canSkip */ true);
1073-
}
1074-
1052+
assert((targetReg == op2Reg) || (targetReg != op1Reg));
1053+
GetEmitter()->emitIns_Mov(ins_Move_Extend(intrin.op2->TypeGet(), false),
1054+
emitTypeSize(node), targetReg, op2Reg,
1055+
/* canSkip */ true);
10751056
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op1Reg, opt);
10761057
}
10771058
else
@@ -1088,13 +1069,9 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
10881069
}
10891070
else if (isRMW)
10901071
{
1091-
if (targetReg != op1Reg)
1092-
{
1093-
assert(targetReg != op2Reg);
1094-
1095-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg,
1096-
/* canSkip */ true);
1097-
}
1072+
assert((targetReg == op1Reg) || (targetReg != op2Reg));
1073+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg,
1074+
/* canSkip */ true);
10981075
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op2Reg, opt);
10991076
}
11001077
else
@@ -1110,27 +1087,20 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
11101087
{
11111088
if (HWIntrinsicInfo::IsExplicitMaskedOperation(intrin.id))
11121089
{
1113-
if (targetReg != op2Reg)
1114-
{
1115-
assert(targetReg != op1Reg);
1116-
assert(targetReg != op3Reg);
1117-
1118-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op2Reg,
1119-
/* canSkip */ true);
1120-
}
1090+
assert((targetReg == op1Reg) || (targetReg != op1Reg));
1091+
assert((targetReg == op1Reg) || (targetReg != op3Reg));
11211092

1093+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op2Reg,
1094+
/* canSkip */ true);
11221095
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op1Reg, op3Reg, opt);
11231096
}
11241097
else
11251098
{
1126-
if (targetReg != op1Reg)
1127-
{
1128-
assert(targetReg != op2Reg);
1129-
assert(targetReg != op3Reg);
1099+
assert((targetReg == op1Reg) || (targetReg != op2Reg));
1100+
assert((targetReg == op1Reg) || (targetReg != op3Reg));
11301101

1131-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg,
1132-
/* canSkip */ true);
1133-
}
1102+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg,
1103+
/* canSkip */ true);
11341104
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op2Reg, op3Reg, opt);
11351105
}
11361106
}
@@ -1384,12 +1354,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
13841354
case NI_AdvSimd_InsertScalar:
13851355
{
13861356
assert(isRMW);
1387-
if (targetReg != op1Reg)
1388-
{
1389-
assert(targetReg != op3Reg);
1390-
1391-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
1392-
}
1357+
assert((targetReg == op1Reg) || (targetReg != op3Reg));
1358+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
13931359

13941360
HWIntrinsicImmOpHelper helper(this, intrin.op2, node);
13951361

@@ -1405,12 +1371,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
14051371
case NI_AdvSimd_Arm64_InsertSelectedScalar:
14061372
{
14071373
assert(isRMW);
1408-
if (targetReg != op1Reg)
1409-
{
1410-
assert(targetReg != op3Reg);
1411-
1412-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
1413-
}
1374+
assert((targetReg == op1Reg) || (targetReg != op3Reg));
1375+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
14141376

14151377
const int resultIndex = (int)intrin.op2->AsIntCon()->gtIconVal;
14161378
const int valueIndex = (int)intrin.op4->AsIntCon()->gtIconVal;
@@ -1421,12 +1383,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
14211383
case NI_AdvSimd_LoadAndInsertScalar:
14221384
{
14231385
assert(isRMW);
1424-
if (targetReg != op1Reg)
1425-
{
1426-
assert(targetReg != op3Reg);
1427-
1428-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
1429-
}
1386+
assert((targetReg == op1Reg) || (targetReg != op3Reg));
1387+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
14301388

14311389
HWIntrinsicImmOpHelper helper(this, intrin.op2, node);
14321390

@@ -1466,11 +1424,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
14661424
targetFieldReg = node->GetRegByIndex(fieldIdx);
14671425
op1FieldReg = fieldNode->GetRegNum();
14681426

1469-
if (targetFieldReg != op1FieldReg)
1470-
{
1471-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(fieldNode), targetFieldReg, op1FieldReg,
1472-
/* canSkip */ true);
1473-
}
1427+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(fieldNode), targetFieldReg, op1FieldReg,
1428+
/* canSkip */ true);
14741429
fieldIdx++;
14751430
}
14761431

@@ -2000,11 +1955,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
20001955
break;
20011956
}
20021957

2003-
if (targetReg != op1Reg)
2004-
{
2005-
assert(targetReg != op3Reg);
2006-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
2007-
}
1958+
assert((targetReg == op1Reg) || (targetReg != op3Reg));
1959+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
20081960
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op2Reg, op3Reg, opt);
20091961
break;
20101962
}
@@ -2330,12 +2282,9 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
23302282
case NI_Sve_SaturatingIncrementBy8BitElementCount:
23312283
{
23322284
assert(isRMW);
2333-
if (targetReg != op1Reg)
2334-
{
2335-
assert(targetReg != op2Reg);
2336-
assert(targetReg != op3Reg);
2337-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
2338-
}
2285+
assert((targetReg == op1Reg) || (targetReg != op2Reg));
2286+
assert((targetReg == op1Reg) || (targetReg != op3Reg));
2287+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
23392288

23402289
if (intrin.op2->IsCnsIntOrI() && intrin.op3->IsCnsIntOrI())
23412290
{
@@ -2387,11 +2336,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
23872336
case NI_Sve_SaturatingIncrementByActiveElementCount:
23882337
{
23892338
// RMW semantics
2390-
if (targetReg != op1Reg)
2391-
{
2392-
assert(targetReg != op2Reg);
2393-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
2394-
}
2339+
assert((targetReg == op1Reg) || (targetReg != op2Reg));
2340+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
23952341

23962342
// Switch instruction if arg1 is unsigned.
23972343
if (varTypeIsUnsigned(node->GetAuxiliaryType()))
@@ -2430,13 +2376,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
24302376
case NI_Sve_ExtractVector:
24312377
{
24322378
assert(isRMW);
2433-
2434-
if (targetReg != op1Reg)
2435-
{
2436-
assert(targetReg != op2Reg);
2437-
2438-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
2439-
}
2379+
assert((targetReg == op1Reg) || (targetReg != op2Reg));
2380+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
24402381

24412382
HWIntrinsicImmOpHelper helper(this, intrin.op3, node);
24422383

@@ -2454,13 +2395,9 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
24542395
{
24552396
assert(isRMW);
24562397
assert(emitter::isFloatReg(op2Reg) == varTypeIsFloating(intrin.baseType));
2457-
if (targetReg != op1Reg)
2458-
{
2459-
assert(targetReg != op2Reg);
2460-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg,
2461-
/* canSkip */ true);
2462-
}
2463-
2398+
assert((targetReg == op1Reg) || (targetReg != op2Reg));
2399+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg,
2400+
/* canSkip */ true);
24642401
GetEmitter()->emitInsSve_R_R(ins, emitSize, targetReg, op2Reg, opt);
24652402
break;
24662403
}
@@ -2483,13 +2420,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
24832420
{
24842421
assert(isRMW);
24852422
assert(HWIntrinsicInfo::IsExplicitMaskedOperation(intrin.id));
2486-
2487-
if (targetReg != op2Reg)
2488-
{
2489-
assert(targetReg != op1Reg);
2490-
GetEmitter()->emitIns_Mov(INS_sve_mov, emitTypeSize(node), targetReg, op2Reg, /* canSkip */ true);
2491-
}
2492-
2423+
assert((targetReg == op2Reg) || (targetReg != op1Reg));
2424+
GetEmitter()->emitIns_Mov(INS_sve_mov, emitTypeSize(node), targetReg, op2Reg, /* canSkip */ true);
24932425
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op1Reg, INS_OPTS_SCALABLE_B);
24942426
break;
24952427
}
@@ -2543,14 +2475,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
25432475

25442476
emitSize = emitTypeSize(node);
25452477

2546-
if (targetReg != op2Reg)
2547-
{
2548-
assert(targetReg != op1Reg);
2549-
assert(targetReg != op3Reg);
2550-
GetEmitter()->emitIns_Mov(INS_mov, emitSize, targetReg, op2Reg,
2551-
/* canSkip */ true);
2552-
}
2553-
2478+
assert((targetReg == op2Reg) || (targetReg != op1Reg));
2479+
assert((targetReg == op2Reg) || (targetReg != op3Reg));
2480+
GetEmitter()->emitIns_Mov(INS_mov, emitSize, targetReg, op2Reg,
2481+
/* canSkip */ true);
25542482
GetEmitter()->emitInsSve_R_R_R(ins, emitSize, targetReg, op1Reg, op3Reg, opt,
25552483
INS_SCALABLE_OPTS_NONE);
25562484
break;
@@ -2564,14 +2492,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
25642492
{
25652493
assert(emitter::isFloatReg(targetReg));
25662494
assert(varTypeIsFloating(node->gtType) || varTypeIsSIMD(node->gtType));
2567-
2568-
if (targetReg != op2Reg)
2569-
{
2570-
assert(targetReg != op1Reg);
2571-
assert(targetReg != op3Reg);
2572-
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op2Reg,
2573-
/* canSkip */ true);
2574-
}
2495+
assert((targetReg == op2Reg) || (targetReg != op1Reg));
2496+
assert((targetReg == op2Reg) || (targetReg != op3Reg));
2497+
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op2Reg,
2498+
/* canSkip */ true);
25752499
GetEmitter()->emitInsSve_R_R_R(ins, EA_SCALABLE, targetReg, op1Reg, op3Reg, opt,
25762500
INS_SCALABLE_OPTS_WITH_SIMD_SCALAR);
25772501
break;

0 commit comments

Comments
 (0)