Skip to content

Commit ddd465b

Browse files
amanasifkhalidamanasifkhalid
authored
JIT ARM64-SVE: Remove INS_SCALABLE_OPTS_SHIFT (#99258)
1 parent 4db4491 commit ddd465b

File tree

6 files changed

+144
-131
lines changed

6 files changed

+144
-131
lines changed

‎src/coreclr/jit/codegenarm64.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2241,8 +2241,7 @@ void CodeGen::instGen_Set_Reg_To_Imm(emitAttr size,
22412241
{
22422242
if (emitter::emitIns_valid_imm_for_mov(imm, size))
22432243
{
2244-
GetEmitter()->emitIns_R_I(INS_mov, size, reg, imm, INS_OPTS_NONE,
2245-
INS_SCALABLE_OPTS_NONE DEBUGARG(targetHandle) DEBUGARG(gtFlags));
2244+
GetEmitter()->emitIns_R_I(INS_mov, size, reg, imm, INS_OPTS_NONE DEBUGARG(targetHandle) DEBUGARG(gtFlags));
22462245
}
22472246
else
22482247
{

‎src/coreclr/jit/codegenarm64test.cpp

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -6760,20 +6760,20 @@ void CodeGen::genArm64EmitterUnitTestsSve()
67606760
// IF_SVE_EB_1A
67616761
theEmitter->emitIns_R_I(INS_sve_dup, EA_SCALABLE, REG_V0, -128,
67626762
INS_OPTS_SCALABLE_B); // DUP <Zd>.<T>, #<imm>{, <shift>}
6763-
theEmitter->emitIns_R_I(INS_sve_dup, EA_SCALABLE, REG_V1, 0, INS_OPTS_SCALABLE_H,
6764-
INS_SCALABLE_OPTS_SHIFT); // DUP <Zd>.<T>, #<imm>{, <shift>}
6763+
theEmitter->emitIns_R_I(INS_sve_dup, EA_SCALABLE, REG_V1, 0,
6764+
INS_OPTS_SCALABLE_H); // DUP <Zd>.<T>, #<imm>{, <shift>}
67656765
theEmitter->emitIns_R_I(INS_sve_dup, EA_SCALABLE, REG_V2, 5,
67666766
INS_OPTS_SCALABLE_S); // DUP <Zd>.<T>, #<imm>{, <shift>}
67676767
theEmitter->emitIns_R_I(INS_sve_dup, EA_SCALABLE, REG_V3, 127,
67686768
INS_OPTS_SCALABLE_D); // DUP <Zd>.<T>, #<imm>{, <shift>}
6769-
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V4, 0,
6770-
INS_OPTS_SCALABLE_B); // MOV <Zd>.<T>, #<imm>{, <shift>}
6771-
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V5, -128, INS_OPTS_SCALABLE_H,
6772-
INS_SCALABLE_OPTS_SHIFT); // MOV <Zd>.<T>, #<imm>{, <shift>}
6773-
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V6, 5, INS_OPTS_SCALABLE_S,
6774-
INS_SCALABLE_OPTS_SHIFT); // MOV <Zd>.<T>, #<imm>{, <shift>}
6775-
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V7, 127, INS_OPTS_SCALABLE_D,
6776-
INS_SCALABLE_OPTS_SHIFT); // MOV <Zd>.<T>, #<imm>{, <shift>}
6769+
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V4, 256,
6770+
INS_OPTS_SCALABLE_D); // MOV <Zd>.<T>, #<imm>{, <shift>}
6771+
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V5, -32768,
6772+
INS_OPTS_SCALABLE_H); // MOV <Zd>.<T>, #<imm>{, <shift>}
6773+
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V6, 1280,
6774+
INS_OPTS_SCALABLE_S); // MOV <Zd>.<T>, #<imm>{, <shift>}
6775+
theEmitter->emitIns_R_I(INS_sve_mov, EA_SCALABLE, REG_V7, 32512,
6776+
INS_OPTS_SCALABLE_D); // MOV <Zd>.<T>, #<imm>{, <shift>}
67776777

67786778
// IF_SVE_EB_1B
67796779
theEmitter->emitIns_R(INS_sve_fmov, EA_SCALABLE, REG_V0, INS_OPTS_SCALABLE_B); // FMOV <Zd>.<T>, #0.0
@@ -6784,18 +6784,18 @@ void CodeGen::genArm64EmitterUnitTestsSve()
67846784
// IF_SVE_EC_1A
67856785
theEmitter->emitIns_R_I(INS_sve_add, EA_SCALABLE, REG_V0, 0,
67866786
INS_OPTS_SCALABLE_B); // ADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
6787-
theEmitter->emitIns_R_I(INS_sve_sqadd, EA_SCALABLE, REG_V1, 0, INS_OPTS_SCALABLE_H,
6788-
INS_SCALABLE_OPTS_SHIFT); // SQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
6789-
theEmitter->emitIns_R_I(INS_sve_sqsub, EA_SCALABLE, REG_V2, 1,
6787+
theEmitter->emitIns_R_I(INS_sve_sqadd, EA_SCALABLE, REG_V1, 5,
6788+
INS_OPTS_SCALABLE_H); // SQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
6789+
theEmitter->emitIns_R_I(INS_sve_sqsub, EA_SCALABLE, REG_V2, 128,
67906790
INS_OPTS_SCALABLE_S); // SQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
6791-
theEmitter->emitIns_R_I(INS_sve_sub, EA_SCALABLE, REG_V3, 128,
6791+
theEmitter->emitIns_R_I(INS_sve_sub, EA_SCALABLE, REG_V3, 255,
67926792
INS_OPTS_SCALABLE_D); // SUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
6793-
theEmitter->emitIns_R_I(INS_sve_subr, EA_SCALABLE, REG_V4, 255,
6794-
INS_OPTS_SCALABLE_B); // SUBR <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
6795-
theEmitter->emitIns_R_I(INS_sve_uqadd, EA_SCALABLE, REG_V5, 5, INS_OPTS_SCALABLE_H,
6796-
INS_SCALABLE_OPTS_SHIFT); // UQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
6797-
theEmitter->emitIns_R_I(INS_sve_uqsub, EA_SCALABLE, REG_V6, 255, INS_OPTS_SCALABLE_S,
6798-
INS_SCALABLE_OPTS_SHIFT); // UQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
6793+
theEmitter->emitIns_R_I(INS_sve_subr, EA_SCALABLE, REG_V4, 256,
6794+
INS_OPTS_SCALABLE_D); // SUBR <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
6795+
theEmitter->emitIns_R_I(INS_sve_uqadd, EA_SCALABLE, REG_V5, 1280,
6796+
INS_OPTS_SCALABLE_H); // UQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
6797+
theEmitter->emitIns_R_I(INS_sve_uqsub, EA_SCALABLE, REG_V6, 65280,
6798+
INS_OPTS_SCALABLE_S); // UQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
67996799

68006800
// IF_SVE_EG_3A
68016801
theEmitter->emitIns_R_R_R_I(INS_sve_sdot, EA_SCALABLE, REG_V1, REG_V2, REG_V0, 0,

‎src/coreclr/jit/emit.h

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1458,16 +1458,6 @@ class emitter
14581458
assert(!idIsSmallDsc());
14591459
idAddr()->_idRegBit = val ? 1 : 0;
14601460
}
1461-
bool idOptionalShift() const
1462-
{
1463-
assert(!idIsSmallDsc());
1464-
return (idAddr()->_idRegBit == 1);
1465-
}
1466-
void idOptionalShift(bool val)
1467-
{
1468-
assert(!idIsSmallDsc());
1469-
idAddr()->_idRegBit = val ? 1 : 0;
1470-
}
14711461
insSvePattern idSvePattern() const
14721462
{
14731463
assert(!idIsSmallDsc());
@@ -1488,6 +1478,17 @@ class emitter
14881478
assert(!idIsSmallDsc());
14891479
idAddr()->_idReg4 = (regNumber)idSvePrfop;
14901480
}
1481+
bool idHasShift() const
1482+
{
1483+
return !idIsSmallDsc() && (idAddr()->_idRegBit == 1);
1484+
}
1485+
void idHasShift(bool val)
1486+
{
1487+
if (!idIsSmallDsc())
1488+
{
1489+
idAddr()->_idRegBit = val ? 1 : 0;
1490+
}
1491+
}
14911492
#endif // TARGET_ARM64
14921493

14931494
#endif // TARGET_ARMARCH

0 commit comments

Comments
 (0)