From d6d383edb3578e6a4abfe12d1b818d2cfffb918c Mon Sep 17 00:00:00 2001 From: Alexander Soldatov Date: Thu, 6 Jul 2023 17:21:49 +0300 Subject: [PATCH] [RISC-V] Increase instruction group size (#88468) Similar to ARM default IG size is not enough for prolog generation. --- src/coreclr/jit/emit.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/coreclr/jit/emit.h b/src/coreclr/jit/emit.h index aa7b428d36de3..0c4beddd0acc6 100644 --- a/src/coreclr/jit/emit.h +++ b/src/coreclr/jit/emit.h @@ -2368,9 +2368,9 @@ class emitter // CLANG_FORMAT_COMMENT_ANCHOR; -#if defined(TARGET_ARMARCH) || defined(TARGET_LOONGARCH64) -// ARM32 and ARM64 both can require a bigger prolog instruction group. One scenario is where -// a function uses all the incoming integer and single-precision floating-point arguments, +#if defined(TARGET_ARMARCH) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64) +// ARM32/64, LoongArch and RISC-V can require a bigger prolog instruction group. One scenario +// is where a function uses all the incoming integer and single-precision floating-point arguments, // and must store them all to the frame on entry. If the frame is very large, we generate // ugly code like: // movw r10, 0x488 @@ -2387,7 +2387,7 @@ class emitter #else #define SC_IG_BUFFER_NUM_SMALL_DESCS 14 #define SC_IG_BUFFER_NUM_LARGE_DESCS 50 -#endif // !(TARGET_ARMARCH || TARGET_LOONGARCH64) +#endif // !(TARGET_ARMARCH || TARGET_LOONGARCH64 || TARGET_RISCV64) size_t emitIGbuffSize;