[Arm64] Use SIMD register to zero init frame (#46609)

* Inline "stp q-reg, q-reg, addr-reg" for frames >= 32 bytes

* Use a pair of "stp q-reg, q-reg, addr-reg" in a loop that clears 64 bytes per iteration for frames >= 192 bytes

* Use dc zva instruction when the instruction is permitted and its block size is set to 64 bytes for frames >= 256 bytes

Author: echesakov

src/coreclr/inc/corinfoinstructionset.h

@@ -27,14 +27,15 @@ enum CORINFO_InstructionSet
     InstructionSet_Atomics=9,
     InstructionSet_Vector64=10,
     InstructionSet_Vector128=11,
-    InstructionSet_ArmBase_Arm64=12,
-    InstructionSet_AdvSimd_Arm64=13,
-    InstructionSet_Aes_Arm64=14,
-    InstructionSet_Crc32_Arm64=15,
-    InstructionSet_Dp_Arm64=16,
-    InstructionSet_Rdm_Arm64=17,
-    InstructionSet_Sha1_Arm64=18,
-    InstructionSet_Sha256_Arm64=19,
+    InstructionSet_Dczva=12,
+    InstructionSet_ArmBase_Arm64=13,
+    InstructionSet_AdvSimd_Arm64=14,
+    InstructionSet_Aes_Arm64=15,
+    InstructionSet_Crc32_Arm64=16,
+    InstructionSet_Dp_Arm64=17,
+    InstructionSet_Rdm_Arm64=18,
+    InstructionSet_Sha1_Arm64=19,
+    InstructionSet_Sha256_Arm64=20,
 #endif // TARGET_ARM64
 #ifdef TARGET_AMD64
     InstructionSet_X86Base=1,
@@ -457,6 +458,8 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
             return "Vector64";
         case InstructionSet_Vector128 :
             return "Vector128";
+        case InstructionSet_Dczva :
+            return "Dczva";
 #endif // TARGET_ARM64
 #ifdef TARGET_AMD64
         case InstructionSet_X86Base :

src/coreclr/inc/jiteeversionguid.h

@@ -32,11 +32,11 @@
 //////////////////////////////////////////////////////////////////////////////////////////////////////////
 //
 
-constexpr GUID JITEEVersionIdentifier = { /* 000b3acb-92d2-4003-8760-e545241dd9a8 */
-    0x000b3acb,
-    0x92d2,
-    0x4003,
-    {0x87, 0x60, 0xe5, 0x45, 0x24, 0x1d, 0xd9, 0xa8}
+constexpr GUID JITEEVersionIdentifier = { /* 960894e2-ec41-4088-82bb-bdcbac4ac2d3 */
+    0x960894e2,
+    0xec41,
+    0x4088,
+    {0x82, 0xbb, 0xbd, 0xcb, 0xac, 0x4a, 0xc2, 0xd3}
 };
 
 //////////////////////////////////////////////////////////////////////////////////////////////////////////

src/coreclr/jit/codegenarm64.cpp

@@ -54,7 +54,8 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 //                          Default: false.
 //
 // Return Value:
-//    returns true if the immediate was too large and tmpReg was used and modified.
+//    returns true if the immediate was small enough to be encoded inside instruction. If not,
+//    returns false meaning the immediate was too large and tmpReg was used and modified.
 //
 bool CodeGen::genInstrWithConstant(instruction ins,
                                    emitAttr    attr,