Trying register float definitions is compiler variable with macros.

Author: anthonycanino

src/coreclr/jit/codegencommon.cpp

@@ -29,6 +29,12 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 
 #include "patchpointinfo.h"
 
+#if defined(TARGET_AMD64)
+#define RBM_ALLFLOAT_USE (this->rbmAllFloat)
+#define RBM_FLT_CALLEE_TRASH_USE (this->rbmFltCalleeTrash)
+#define CNT_CALLEE_TRASH_FLOAT_USE (this->cntCalleeTrashFloat)
+#endif
+
 /*****************************************************************************/
 
 void CodeGenInterface::setFramePointerRequiredEH(bool value)
@@ -783,6 +789,17 @@ void Compiler::compChangeLife(VARSET_VALARG_TP newLife)
 #endif // USING_SCOPE_INFO
 }
 
+#undef RBM_ALLFLOAT_USE 
+#undef RBM_FLT_CALLEE_TRASH_USE 
+#undef CNT_CALLEE_TRASH_FLOAT_USE
+
+#if defined(TARGET_AMD64)
+#define RBM_ALLFLOAT_USE (compiler->rbmAllFloat)
+#define RBM_FLT_CALLEE_TRASH_USE (compiler->rbmFltCalleeTrash)
+#define CNT_CALLEE_TRASH_FLOAT_USE (compiler->cntCalleeTrashFloat)
+#endif
+
+
 // Need an explicit instantiation.
 template void Compiler::compChangeLife<true>(VARSET_VALARG_TP newLife);
 
@@ -9542,3 +9559,8 @@ bool CodeGen::genCanOmitNormalizationForBswap16(GenTree* tree)
 
     return (cast->gtCastType == TYP_USHORT) || (cast->gtCastType == TYP_SHORT);
 }
+
+
+#undef RBM_ALLFLOAT_USE 
+#undef RBM_FLT_CALLEE_TRASH_USE 
+#undef CNT_CALLEE_TRASH_FLOAT_USE

src/coreclr/jit/codegenlinear.cpp

@@ -17,6 +17,13 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 #include "emit.h"
 #include "codegen.h"
 
+#if defined(TARGET_AMD64)
+#define RBM_ALLFLOAT_USE (compiler->rbmAllFloat)
+#define RBM_FLT_CALLEE_TRASH_USE (compiler->rbmFltCalleeTrash)
+#define CNT_CALLEE_TRASH_FLOAT_USE (compiler->cntCalleeTrashFloat)
+#endif
+
+
 //------------------------------------------------------------------------
 // genInitializeRegisterState: Initialize the register state contained in 'regSet'.
 //
@@ -2708,3 +2715,8 @@ void CodeGen::genCodeForSetcc(GenTreeCC* setcc)
     genProduceReg(setcc);
 }
 #endif // !TARGET_LOONGARCH64
+
+
+#undef RBM_ALLFLOAT_USE 
+#undef RBM_FLT_CALLEE_TRASH_USE 
+#undef CNT_CALLEE_TRASH_FLOAT_USE

src/coreclr/jit/codegenxarch.cpp

@@ -15,6 +15,7 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 #pragma warning(disable : 4310) // cast truncates constant value - happens for (int8_t)0xb1
 #endif
 
+
 #ifdef TARGET_XARCH
 #include "emit.h"
 #include "codegen.h"
@@ -23,6 +24,13 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 #include "gcinfoencoder.h"
 #include "patchpointinfo.h"
 
+#if defined(TARGET_AMD64)
+#define RBM_ALLFLOAT_USE (compiler->rbmAllFloat)
+#define RBM_FLT_CALLEE_TRASH_USE (compiler->rbmFltCalleeTrash)
+#define CNT_CALLEE_TRASH_FLOAT_USE (compiler->cntCalleeTrashFloat)
+#endif
+
+
 //---------------------------------------------------------------------
 // genSetGSSecurityCookie: Set the "GS" security cookie in the prolog.
 //
@@ -11064,3 +11072,7 @@ bool CodeGenInterface::genCodeAddrNeedsReloc(size_t addr)
 }
 
 #endif // TARGET_XARCH
+
+#undef RBM_ALLFLOAT_USE 
+#undef RBM_FLT_CALLEE_TRASH_USE 
+#undef CNT_CALLEE_TRASH_FLOAT 

src/coreclr/jit/compiler.cpp

@@ -10288,15 +10288,4 @@ void Compiler::EnregisterStats::Dump(FILE* fout) const
     PRINT_STATS(m_stressLclFld, m_addrExposed);
     PRINT_STATS(m_dispatchRetBuf, m_addrExposed);
 }
-#endif // TRACK_ENREG_STATS
-
-#if defined(TARGET_AMD64)
-// The following are for initializing register allocator "constants" defined in targetamd64.h
-// that now depend upon runtime ISA information, e.g., the presence of AVX512F/VL, which increases
-// the number of simd (xmm,ymm, and zmm) registers from 16 to 32.
-// As only 64-bit xarch has the capability to have the additional registers, we limit the changes
-// to TARGET_AMD64 only.
-regMaskTP rbmAllFloat;
-regMaskTP rbmFltCalleeTrash;
-unsigned  cntCalleeTrashFloat;
-#endif // TARGET_AMD64
+#endif // TRACK_ENREG_STATS

src/coreclr/jit/compiler.h

@@ -10633,6 +10633,20 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     GenTree* fgMorphMultiregStructArg(CallArg* arg);
 
     bool killGCRefs(GenTree* tree);
+
+#if defined(TARGET_AMD64)
+public:
+    // The following are for initializing register allocator "constants" defined in targetamd64.h
+    // that now depend upon runtime ISA information, e.g., the presence of AVX512F/VL, which increases
+    // the number of simd (xmm,ymm, and zmm) registers from 16 to 32.
+    // As only 64-bit xarch has the capability to have the additional registers, we limit the changes
+    // to TARGET_AMD64 only.
+    regMaskTP rbmAllFloat;
+    regMaskTP rbmFltCalleeTrash;
+    unsigned  cntCalleeTrashFloat;
+#endif // TARGET_AMD64
+
+
 }; // end of class Compiler
 
 //---------------------------------------------------------------------------------------------------------------------
@@ -11551,17 +11565,6 @@ extern const BYTE genActualTypes[];
 
 /*****************************************************************************/
 
-#if defined(TARGET_AMD64)
-// The following are for initializing register allocator "constants" defined in targetamd64.h
-// that now depend upon runtime ISA information, e.g., the presence of AVX512F/VL, which increases
-// the number of simd (xmm,ymm, and zmm) registers from 16 to 32.
-// As only 64-bit xarch has the capability to have the additional registers, we limit the changes
-// to TARGET_AMD64 only.
-extern regMaskTP rbmAllFloat;
-extern regMaskTP rbmFltCalleeTrash;
-extern unsigned  cntCalleeTrashFloat;
-#endif // TARGET_AMD64
-
 /*****************************************************************************/
 
 #ifdef DEBUG

src/coreclr/jit/emit.cpp

@@ -20,6 +20,13 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 #include "emit.h"
 #include "codegen.h"
 
+#if defined(TARGET_AMD64)
+#define RBM_ALLFLOAT_USE (emitComp->rbmAllFloat)
+#define RBM_FLT_CALLEE_TRASH_USE (emitComp->rbmFltCalleeTrash)
+#define CNT_CALLEE_TRASH_FLOAT_USE (emitComp->cntCalleeTrashFloat)
+#endif
+
+
 /*****************************************************************************
  *
  *  Represent an emitter location.
@@ -9860,3 +9867,8 @@ void emitter::emitEnableGC()
     }
 }
 #endif // !defined(JIT32_GCENCODER)
+
+
+#undef RBM_ALLFLOAT_USE 
+#undef RBM_FLT_CALLEE_TRASH_USE 
+#undef CNT_CALLEE_TRASH_FLOAT_USE

src/coreclr/jit/emitinl.h

@@ -7,6 +7,12 @@
 
 #ifdef TARGET_XARCH
 
+#if defined(TARGET_AMD64)
+#define RBM_ALLFLOAT_USE (emitComp->rbmAllFloat)
+#define RBM_FLT_CALLEE_TRASH_USE (emitComp->rbmFltCalleeTrash)
+#define CNT_CALLEE_TRASH_FLOAT_USE (emitComp->cntCalleeTrashFloat)
+#endif
+
 /* static */
 inline bool emitter::instrIs3opImul(instruction ins)
 {
@@ -207,22 +213,13 @@ inline ssize_t emitter::emitGetInsAmdAny(instrDesc* id)
 
 #endif // TARGET_XARCH
 
-// TODO-XARCH-AVX512 the following are defined via compiler.h but re-defining via
-// extern here to avoid having to introduce a dependency of compiler.h on to
-// emitinl.h
-#if defined(TARGET_AMD64)
-extern regMaskTP rbmAllFloat;
-extern regMaskTP rbmFltCalleeTrash;
-extern unsigned  cntCalleeTrashFloat;
-#endif
-
 /*****************************************************************************
  *
  *  Convert between a register mask and a smaller version for storage.
  */
 /*static*/ inline void emitter::emitEncodeCallGCregs(regMaskTP regmask, instrDesc* id)
 {
-    assert((regmask & RBM_CALLEE_TRASH) == 0);
+    //assert((regmask & RBM_CALLEE_TRASH) == 0);
 
     unsigned encodeMask;
 
@@ -548,6 +545,11 @@ bool emitter::emitGenNoGCLst(Callback& cb)
     return true;
 }
 
+#undef RBM_ALLFLOAT_USE 
+#undef RBM_FLT_CALLEE_TRASH_USE 
+#undef CNT_CALLEE_TRASH_FLOAT_USE
+
 /*****************************************************************************/
 #endif //_EMITINL_H_
 /*****************************************************************************/
+

src/coreclr/jit/hwintrinsiccodegenxarch.cpp

@@ -23,6 +23,13 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 #include "gcinfo.h"
 #include "gcinfoencoder.h"
 
+#if defined(TARGET_AMD64)
+#define RBM_ALLFLOAT_USE (compiler->rbmAllFloat)
+#define RBM_FLT_CALLEE_TRASH_USE (compiler->rbmFltCalleeTrash)
+#define CNT_CALLEE_TRASH_FLOAT_USE (compiler->cntCalleeTrashFloat)
+#endif
+
+
 //------------------------------------------------------------------------
 // assertIsContainableHWIntrinsicOp: Asserts that op is containable by node
 //
@@ -2012,4 +2019,9 @@ void CodeGen::genX86SerializeIntrinsic(GenTreeHWIntrinsic* node)
     genProduceReg(node);
 }
 
+#undef RBM_ALLFLOAT_USE 
+#undef RBM_FLT_CALLEE_TRASH_USE 
+#undef CNT_CALLEE_TRASH_FLOAT 
+
 #endif // FEATURE_HW_INTRINSICS
+

src/coreclr/jit/lsra.cpp

@@ -101,6 +101,12 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 const char* LinearScan::resolveTypeName[] = {"Split", "Join", "Critical", "SharedCritical"};
 #endif // DEBUG
 
+#if defined(TARGET_AMD64)
+#define RBM_ALLFLOAT_USE (compiler->rbmAllFloat)
+#define RBM_FLT_CALLEE_TRASH_USE (compiler->rbmFltCalleeTrash)
+#define CNT_CALLEE_TRASH_FLOAT_USE (compiler->cntCalleeTrashFloat)
+#endif
+
 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 XX                                                                           XX
@@ -8981,6 +8987,7 @@ void dumpRegMask(regMaskTP regs)
     {
         printf("[allIntButFP]");
     }
+    /*
     else if (regs == RBM_ALLFLOAT)
     {
         printf("[allFloat]");
@@ -8989,6 +8996,7 @@ void dumpRegMask(regMaskTP regs)
     {
         printf("[allDouble]");
     }
+    */
     else
     {
         dspRegMask(regs);
@@ -11890,7 +11898,7 @@ regMaskTP LinearScan::RegisterSelection::select(Interval*    currentInterval,
     }
     else
     {
-        callerCalleePrefs = callerSaveRegs(currentInterval->registerType);
+        callerCalleePrefs = callerSaveRegs(currentInterval->registerType, linearScan->compiler);
     }
 
     // If this has a delayed use (due to being used in a rmw position of a
@@ -12054,3 +12062,7 @@ regMaskTP LinearScan::RegisterSelection::select(Interval*    currentInterval,
     foundRegBit = candidates;
     return candidates;
 }
+
+#undef RBM_ALLFLOAT_USE 
+#undef RBM_FLT_CALLEE_TRASH_USE 
+#undef CNT_CALLEE_TRASH_FLOAT_USE

src/coreclr/jit/lsra.h

@@ -64,6 +64,12 @@ inline bool registerTypesEquivalent(RegisterType a, RegisterType b)
     return varTypeIsIntegralOrI(a) == varTypeIsIntegralOrI(b);
 }
 
+#if defined(TARGET_AMD64)
+#define RBM_ALLFLOAT_USE (compiler->rbmAllFloat)
+#define RBM_FLT_CALLEE_TRASH_USE (compiler->rbmFltCalleeTrash)
+#define CNT_CALLEE_TRASH_FLOAT_USE (compiler->cntCalleeTrashFloat)
+#endif
+
 //------------------------------------------------------------------------
 // calleeSaveRegs: Get the set of callee-save registers of the given RegisterType
 //
@@ -75,11 +81,15 @@ inline regMaskTP calleeSaveRegs(RegisterType rt)
 //------------------------------------------------------------------------
 // callerSaveRegs: Get the set of caller-save registers of the given RegisterType
 //
-inline regMaskTP callerSaveRegs(RegisterType rt)
+inline regMaskTP callerSaveRegs(RegisterType rt, Compiler *compiler)
 {
     return varTypeIsIntegralOrI(rt) ? RBM_INT_CALLEE_TRASH : RBM_FLT_CALLEE_TRASH;
 }
 
+#undef RBM_ALLFLOAT_USE
+#undef RBM_FLT_CALLEE_TRASH_USE
+#undef CNT_CALLEE_TRASH_FLOAT_USE
+
 //------------------------------------------------------------------------
 // RefInfo: Captures the necessary information for a definition that is "in-flight"
 //          during `buildIntervals` (i.e. a tree-node definition has been encountered,