Implement ShuffleNative methods and optimise Shuffle for non-constant indices (#99596)

* Squash into 1 commit

* Remove internal dependency on ShuffleUnsafe's behaviour wrt high bit

* Optimise some codegen

- Optimise comparison in `gtNewSimdShuffleNodeVariable` for xarch
- Optimise for constant vector in Vector256.Shuffle{Unsafe} when have AVX2 only

* jit format

* jit format

* Simplify logic for using Shuffle for ShuffleUnsafe

* Move `ShuffleUnsafeModified` out of `Base64Helper`

- This was requested feedback via Discord

* Remove unnecessary `CompExactlyDependsOn` and `using`s

* Update SearchValues.cs

* Support AVX-512/AVX-10.1 acceleration of Shuffle V128<ulong/long/double>

* Additional optimisation for V512 constant index shuffle

- When 128-bit lanes are not crossed, emit vpshufb instead of vperm*

* jit format & typo

* Fix operand order

* Changes to `IsValidForShuffle` & jit format

- Ensure we use IsValidForShuffle correctly (i.e., ensure all cases that could be emittet at some point, are able to be done)
- jit format changes

* jit format

* Update hwintrinsicxarch.cpp

* Update hwintrinsicxarch.cpp

* Update gentree.cpp

- Implement preferring `vshufpd`/`vpshufd`/`vshufps` (when same size & possible & no zeroing) over `vpshufb` (when no crossing lane) over `vpermd`/`vpermps`/`vpermpd`/the ushort & byte equivalents in constant index case

Update gentree.cpp

- Continuation of previous commit, for the variable index shuffle stuff

Update gentree.cpp

Update gentree.cpp

Fix typo

* Make `op2DupSafe` be consistently ordered

- Adjust code such that `op2DupSafe` is consistently ordered with respect to `retNode`(it happens to end up before now) - this is the likely cause of the test failures

* jit format

* Use `compIsEvexOpportunisticallySupported` instead of explicit AVX-10 in remaining places

* jit format

* Update gentree.cpp

- Ensure `op1` side effects are done before `op2` side effects

* Update Vector128.cs

* Use `BlockNonDeterministicIntrinsics` instead of `CompExactlyDependsOn`

- As per feedback

* Ensure V128<byte> ShuffleUnsafe is not regressed on mono

* Update gentree.cpp

* Rename `ShuffleUnsafe` to `ShuffleNative`

- And do a full review of the logic & comments of all my code
- Fix 3 bugs (2 pre-existing)
- Simplify/improve some code

* jit format

* jit format again

* um

* Move assertion on arm64 to correct spot

* Normalize indices for `vpshufb` in all cases of constant indices Shuffle

- This is a nice-to-have, not a correctness issue - it matches what we're doing throughout the rest of the function, and keeps the asm more readable imo

* jit format

* Revert last pair of commits

- There's other places where they're not normalised. could be done, but not really worth the trouble probably

* Feedback

* Address some feedback & a bug fix

- Implement a bunch of feedback
- Fix an oversight in `IsValidForShuffle` where we don't treat something as variable indices that gets emitted as such

* Ensure ShuffleNative's behaviour with reflection/function pointers/etc. is the same as a normal call

- Not a particularly pretty solution to the problem, but it should work correctly at least

* jit format & compilation error

* jit format & fix buuld

* jit format & fix build

* jit format

* Update hwintrinsicxarch.cpp

* Update gentree.cpp

Missing `!= nullptr` & typo in comment & add additional comments in a few places.

* Fix mono code

* Mono: also cast arguments

* Move mono impl back into c#

- This should fix the mono issues (wasm impl assumes indices are constant)
- Additionally ensure V128.Shuffle(byte/sbyte) is vectorised for all mono platforms with ssse3 or arm64 advsimd or packedsimd, when given variable indices

* Update Vector128.cs

* um

---------

Co-authored-by: Tanner Gooding <tagoo@outlook.com>
Co-authored-by: Egor Bogatov <egorbo@gmail.com>

Author: 3 people

src/coreclr/jit/compiler.h

@@ -3340,11 +3340,19 @@ class Compiler
     GenTree* gtNewSimdRoundNode(
         var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize);
 
+    GenTree* gtNewSimdShuffleVariableNode(var_types   type,
+                                          GenTree*    op1,
+                                          GenTree*    op2,
+                                          CorInfoType simdBaseJitType,
+                                          unsigned    simdSize,
+                                          bool        isShuffleNative);
+
     GenTree* gtNewSimdShuffleNode(var_types   type,
                                   GenTree*    op1,
                                   GenTree*    op2,
                                   CorInfoType simdBaseJitType,
-                                  unsigned    simdSize);
+                                  unsigned    simdSize,
+                                  bool        isShuffleNative);
 
     GenTree* gtNewSimdSqrtNode(
         var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize);
@@ -4669,7 +4677,11 @@ class Compiler
                                         bool                  mustExpand);
 
 #ifdef FEATURE_HW_INTRINSICS
-    bool IsValidForShuffle(GenTreeVecCon* vecCon, unsigned simdSize, var_types simdBaseType) const;
+    bool IsValidForShuffle(GenTree* indices,
+                           unsigned simdSize,
+                           var_types simdBaseType,
+                           bool* canBecomeValid,
+                           bool isShuffleNative) const;
 
     GenTree* impHWIntrinsic(NamedIntrinsic        intrinsic,
                             CORINFO_CLASS_HANDLE  clsHnd,